2012-10-23 19:02:30 +02:00
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;; Machine description for AArch64 architecture.
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2015-01-05 13:33:28 +01:00
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;; Copyright (C) 2009-2015 Free Software Foundation, Inc.
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2012-10-23 19:02:30 +02:00
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;; Contributed by ARM Ltd.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; -------------------------------------------------------------------
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;; Mode Iterators
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;; -------------------------------------------------------------------
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;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
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(define_mode_iterator GPI [SI DI])
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;; Iterator for QI and HI modes
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(define_mode_iterator SHORT [QI HI])
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;; Iterator for all integer modes (up to 64-bit)
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(define_mode_iterator ALLI [QI HI SI DI])
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;; Iterator for all integer modes that can be extended (up to 64-bit)
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(define_mode_iterator ALLX [QI HI SI])
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;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
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(define_mode_iterator GPF [SF DF])
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2015-07-29 14:27:05 +02:00
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;; Iterator for General Purpose Float registers, inc __fp16.
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(define_mode_iterator GPF_F16 [HF SF DF])
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2012-10-23 19:02:30 +02:00
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;; Integer vector modes.
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(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
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;; vector and scalar, 64 & 128-bit container, all integer modes
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(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
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;; vector and scalar, 64 & 128-bit container: all vector integer modes;
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;; 64-bit scalar integer mode
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(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
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;; Double vector modes.
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(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
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;; vector, 64-bit container, all integer modes
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(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
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;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
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(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
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;; Quad vector modes.
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(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
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2014-09-04 18:06:13 +02:00
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;; VQ without 2 element modes.
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(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF])
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;; Quad vector with only 2 element modes.
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(define_mode_iterator VQ_2E [V2DI V2DF])
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2013-07-23 14:20:05 +02:00
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;; This mode iterator allows :P to be used for patterns that operate on
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;; addresses in different modes. In LP64, only DI will match, while in
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;; ILP32, either can match.
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(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
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(DI "ptr_mode == DImode || Pmode == DImode")])
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2012-10-23 19:02:30 +02:00
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;; This mode iterator allows :PTR to be used for patterns that operate on
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;; pointer-sized quantities. Exactly one of the two alternatives will match.
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2013-07-23 14:20:05 +02:00
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(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
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2012-10-23 19:02:30 +02:00
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;; Vector Float modes.
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(define_mode_iterator VDQF [V2SF V4SF V2DF])
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2014-09-22 18:24:57 +02:00
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;; Vector Float modes, and DF.
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(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
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2013-09-16 11:53:11 +02:00
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;; Vector single Float modes.
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(define_mode_iterator VDQSF [V2SF V4SF])
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2013-05-14 16:56:13 +02:00
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;; Modes suitable to use as the return type of a vcond expression.
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(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
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2013-05-01 12:33:57 +02:00
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;; All Float modes.
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(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
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2012-10-23 19:02:30 +02:00
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;; Vector Float modes with 2 elements.
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(define_mode_iterator V2F [V2SF V2DF])
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;; All modes.
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(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
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2013-01-14 18:48:52 +01:00
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;; All vector modes and DI.
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(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
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2013-11-26 11:03:14 +01:00
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;; All vector modes and DI and DF.
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(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
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V2DI V2SF V4SF V2DF DI DF])
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2012-10-23 19:02:30 +02:00
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;; Vector modes for Integer reduction across lanes.
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aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap for big-endian.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
(reduc_<sur>plus_<mode>): Factorize V2DI into this.
(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
and also change to float UNSPEC.
(reduc_maxmin_uns>_<mode>): Remove V2DI.
* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
result access for big-endian.
(__LANE0): New macro used to fix up lane access of 'across-lanes'
intrinsics for big-endian.
* config/aarch64/iterators.md (VDQV): Add V2DI.
(VDQV_S): New.
(vp): New mode attribute.
From-SVN: r205269
2013-11-22 16:34:36 +01:00
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(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
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;; Vector modes(except V2DI) for Integer reduction across lanes.
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(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
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2012-10-23 19:02:30 +02:00
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;; All double integer narrow-able modes.
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(define_mode_iterator VDN [V4HI V2SI DI])
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;; All quad integer narrow-able modes.
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(define_mode_iterator VQN [V8HI V4SI V2DI])
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;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
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(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
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;; All quad integer widen-able modes.
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(define_mode_iterator VQW [V16QI V8HI V4SI])
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;; Double vector modes for combines.
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(define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
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;; Vector modes except double int.
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(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
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arm_neon.h (vrecpe_u32, [...]): Rewrite using builtin functions.
* config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite using
builtin functions.
(vfma_f32, vfmaq_f32, vfmaq_f64, vfma_n_f32, vfmaq_n_f32, vfmaq_n_f64,
vfms_f32, vfmsq_f32, vfmsq_f64): Likewise.
(vhsub_s8, vhsub_u8, vhsub_s16, vhsub_u16, vhsub_s32, vhsub_u32,
vhsubq_s8, vhsubq_u8, vhsubq_s16, vhsubq_u16, vhsubq_s32, vhsubq_u32,
vsubhn_s16, vsubhn_u16, vsubhn_s32, vsubhn_u32, vsubhn_s64, vsubhn_u66,
vrsubhn_s16, vrsubhn_u16, vrsubhn_s32, vrsubhn_u32, vrsubhn_s64,
vrsubhn_u64, vsubhn_high_s16, vsubhn_high_u16, vsubhn_high_s32,
vsubhn_high_u32, vsubhn_high_s64, vsubhn_high_u64, vrsubhn_high_s16,
vrsubhn_high_u16, vrsubhn_high_s32, vrsubhn_high_u32, vrsubhn_high_s64,
vrsubhn_high_u64): Likewise.
* config/aarch64/iterators.md (VDQ_SI): New mode iterator.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_URECPE.
* config/aarch64/aarch64-simd.md (aarch64_urecpe<mode>): New pattern.
* config/aarch64/aarch64-simd-builtins.def (shsub, uhsub, subhn, rsubhn,
subhn2, rsubhn2, urecpe): New builtins.
Co-Authored-By: Haijian Zhang <z.zhanghaijian@huawei.com>
Co-Authored-By: Jiji Jiang <jiangjiji@huawei.com>
Co-Authored-By: Pengfei Sui <suipengfei@huawei.com>
From-SVN: r218484
2014-12-08 15:19:44 +01:00
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;; Vector modes for S type.
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(define_mode_iterator VDQ_SI [V2SI V4SI])
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2013-08-09 11:28:51 +02:00
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;; Vector modes for Q and H types.
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(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
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2012-10-23 19:02:30 +02:00
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;; Vector modes for H and S types.
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(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
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2014-04-24 10:05:07 +02:00
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;; Vector modes for H, S and D types.
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(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
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2012-10-23 19:02:30 +02:00
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;; Vector and scalar integer modes for H and S
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(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
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;; Vector and scalar 64-bit container: 16, 32-bit integer modes
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(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
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;; Vector 64-bit container: 16, 32-bit integer modes
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(define_mode_iterator VD_HSI [V4HI V2SI])
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;; Scalar 64-bit container: 16, 32-bit integer modes
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(define_mode_iterator SD_HSI [HI SI])
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;; Vector 64-bit container: 16, 32-bit integer modes
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(define_mode_iterator VQ_HSI [V8HI V4SI])
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;; All byte modes.
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(define_mode_iterator VB [V8QI V16QI])
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2014-11-21 17:56:21 +01:00
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;; 2 and 4 lane SI modes.
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(define_mode_iterator VS [V2SI V4SI])
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2012-10-23 19:02:30 +02:00
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(define_mode_iterator TX [TI TF])
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;; Opaque structure modes.
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(define_mode_iterator VSTRUCT [OI CI XI])
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;; Double scalar modes
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(define_mode_iterator DX [DI DF])
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2013-09-16 11:50:21 +02:00
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;; Modes available for <f>mul lane operations.
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(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
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;; Modes available for <f>mul lane operations changing lane count.
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(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
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2012-10-23 19:02:30 +02:00
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;; ------------------------------------------------------------------
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;; Unspec enumerations for Advance SIMD. These could well go into
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;; aarch64.md but for their use in int_iterators here.
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;; ------------------------------------------------------------------
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(define_c_enum "unspec"
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[
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UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
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UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
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2015-01-28 11:08:57 +01:00
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UNSPEC_ABS ; Used in aarch64-simd.md.
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2013-05-01 17:16:14 +02:00
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UNSPEC_FMAX ; Used in aarch64-simd.md.
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UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
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2012-10-23 19:02:30 +02:00
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UNSPEC_FMAXV ; Used in aarch64-simd.md.
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2013-05-01 17:16:14 +02:00
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UNSPEC_FMIN ; Used in aarch64-simd.md.
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UNSPEC_FMINNMV ; Used in aarch64-simd.md.
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2012-10-23 19:02:30 +02:00
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UNSPEC_FMINV ; Used in aarch64-simd.md.
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UNSPEC_FADDV ; Used in aarch64-simd.md.
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[AArch64] Use new reduc_plus_scal optabs, inc. for __builtins
* config/aarch64/aarch64-simd-builtins.def
(reduc_splus_<mode>/VDQF, reduc_uplus_<mode>/VDQF, reduc_splus_v4sf):
Remove.
(reduc_plus_scal_<mode>, reduc_plus_scal_v4sf): New.
* config/aarch64/aarch64-simd.md (reduc_<sur>plus_mode): Remove.
(reduc_splus_<mode>, reduc_uplus_<mode>, reduc_plus_scal_<mode>): New.
(reduc_<sur>plus_mode): Change SUADDV -> UNSPEC_ADDV, rename to...
(aarch64_reduc_plus_internal<mode>): ...this.
(reduc_<sur>plus_v2si): Change SUADDV -> UNSPEC_ADDV, rename to...
(aarch64_reduc_plus_internalv2si): ...this.
(reduc_splus_<mode>/V2F): Rename to...
(aarch64_reduc_plus_internal<mode>): ...this.
* config/aarch64/iterators.md
(UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove.
(UNSPEC_ADDV): New.
(sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV.
* config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8,
vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64,
vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32,
vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to
__builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper.
From-SVN: r216738
2014-10-27 16:20:18 +01:00
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UNSPEC_ADDV ; Used in aarch64-simd.md.
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2012-10-23 19:02:30 +02:00
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UNSPEC_SMAXV ; Used in aarch64-simd.md.
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UNSPEC_SMINV ; Used in aarch64-simd.md.
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UNSPEC_UMAXV ; Used in aarch64-simd.md.
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UNSPEC_UMINV ; Used in aarch64-simd.md.
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UNSPEC_SHADD ; Used in aarch64-simd.md.
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UNSPEC_UHADD ; Used in aarch64-simd.md.
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UNSPEC_SRHADD ; Used in aarch64-simd.md.
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UNSPEC_URHADD ; Used in aarch64-simd.md.
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UNSPEC_SHSUB ; Used in aarch64-simd.md.
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UNSPEC_UHSUB ; Used in aarch64-simd.md.
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UNSPEC_SRHSUB ; Used in aarch64-simd.md.
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UNSPEC_URHSUB ; Used in aarch64-simd.md.
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UNSPEC_ADDHN ; Used in aarch64-simd.md.
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UNSPEC_RADDHN ; Used in aarch64-simd.md.
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UNSPEC_SUBHN ; Used in aarch64-simd.md.
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UNSPEC_RSUBHN ; Used in aarch64-simd.md.
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UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
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UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
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|
|
|
|
UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQDMULH ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_PMUL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USQADD ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SUQADD ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQXTUN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQXTN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_UQXTN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SSRA ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USRA ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SRSRA ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_URSRA ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SRSHR ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_URSHR ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQSHLU ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_UQSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQSHRN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_UQSHRN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SRSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_URSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SQRSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_UQRSHL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SSLI ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USLI ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SSRI ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USRI ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SSHLL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_USHLL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_ADDP ; Used in aarch64-simd.md.
|
2012-12-05 12:36:00 +01:00
|
|
|
UNSPEC_TBL ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_CONCAT ; Used in vector permute patterns.
|
2012-12-05 12:42:37 +01:00
|
|
|
UNSPEC_ZIP1 ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_ZIP2 ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_UZP1 ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_UZP2 ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_TRN1 ; Used in vector permute patterns.
|
|
|
|
|
UNSPEC_TRN2 ; Used in vector permute patterns.
|
Detect EXT patterns to vec_perm_const, use for EXT intrinsics
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): New static data.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
New patterns.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
patterns for EXT.
(aarch64_evpc_ext): New function.
* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.
* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.
From-SVN: r211058
2014-05-29 18:57:42 +02:00
|
|
|
UNSPEC_EXT ; Used in aarch64-simd.md.
|
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.
* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
* config/aarch64/iterators.md (REVERSE): New iterator.
(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
(rev_op): New int_attribute.
* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
Replace temporary __asm__ with __builtin_shuffle.
From-SVN: r211174
2014-06-03 13:28:55 +02:00
|
|
|
UNSPEC_REV64 ; Used in vector reverse patterns (permute).
|
|
|
|
|
UNSPEC_REV32 ; Used in vector reverse patterns (permute).
|
|
|
|
|
UNSPEC_REV16 ; Used in vector reverse patterns (permute).
|
Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
|
|
|
UNSPEC_AESE ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_AESD ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_AESMC ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_AESIMC ; Used in aarch64-simd.md.
|
Implement support for AArch64 Crypto SHA1.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 15:55:47 +01:00
|
|
|
UNSPEC_SHA1C ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA1M ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA1P ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA1H ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
|
2013-12-19 16:00:53 +01:00
|
|
|
UNSPEC_SHA256H ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
|
2013-12-19 16:04:19 +01:00
|
|
|
UNSPEC_PMULL ; Used in aarch64-simd.md.
|
|
|
|
|
UNSPEC_PMULL2 ; Used in aarch64-simd.md.
|
2015-01-21 18:53:44 +01:00
|
|
|
UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
|
2015-04-30 17:52:24 +02:00
|
|
|
UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
|
2012-10-23 19:02:30 +02:00
|
|
|
])
|
|
|
|
|
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Mode attributes
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
|
|
|
|
|
;; 32-bit version and "%x0" in the 64-bit version.
|
|
|
|
|
(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
|
|
|
|
|
|
2014-04-22 13:34:52 +02:00
|
|
|
;; For inequal width int to float conversion
|
|
|
|
|
(define_mode_attr w1 [(SF "w") (DF "x")])
|
|
|
|
|
(define_mode_attr w2 [(SF "x") (DF "w")])
|
|
|
|
|
|
2013-04-02 11:02:17 +02:00
|
|
|
;; For constraints used in scalar immediate vector moves
|
|
|
|
|
(define_mode_attr hq [(HI "h") (QI "q")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; For scalar usage of vector/FP registers
|
|
|
|
|
(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
|
2013-05-01 12:33:57 +02:00
|
|
|
(SF "s") (DF "d")
|
2012-10-23 19:02:30 +02:00
|
|
|
(V8QI "") (V16QI "")
|
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
|
(V2DI "") (V2SF "")
|
|
|
|
|
(V4SF "") (V2DF "")])
|
|
|
|
|
|
|
|
|
|
;; For scalar usage of vector/FP registers, narrowing
|
|
|
|
|
(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
|
|
|
|
|
(V8QI "") (V16QI "")
|
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
|
(V2DI "") (V2SF "")
|
|
|
|
|
(V4SF "") (V2DF "")])
|
|
|
|
|
|
|
|
|
|
;; For scalar usage of vector/FP registers, widening
|
|
|
|
|
(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
|
|
|
|
|
(V8QI "") (V16QI "")
|
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
|
(V2DI "") (V2SF "")
|
|
|
|
|
(V4SF "") (V2DF "")])
|
|
|
|
|
|
2013-07-26 12:54:59 +02:00
|
|
|
;; Register Type Name and Vector Arrangement Specifier for when
|
|
|
|
|
;; we are doing scalar for DI and SIMD for SI (ignoring all but
|
|
|
|
|
;; lane 0).
|
|
|
|
|
(define_mode_attr rtn [(DI "d") (SI "")])
|
|
|
|
|
(define_mode_attr vas [(DI "") (SI ".2s")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Map a floating point mode to the appropriate register name prefix
|
|
|
|
|
(define_mode_attr s [(SF "s") (DF "d")])
|
|
|
|
|
|
|
|
|
|
;; Give the length suffix letter for a sign- or zero-extension.
|
|
|
|
|
(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
|
|
|
|
|
|
|
|
|
|
;; Give the number of bits in the mode
|
|
|
|
|
(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
|
|
|
|
|
|
|
|
|
|
;; Give the ordinal of the MSB in the mode
|
|
|
|
|
(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
|
|
|
|
|
|
|
|
|
|
;; Attribute to describe constants acceptable in logical operations
|
|
|
|
|
(define_mode_attr lconst [(SI "K") (DI "L")])
|
|
|
|
|
|
2014-11-04 12:23:10 +01:00
|
|
|
;; Attribute to describe constants acceptable in atomic logical operations
|
|
|
|
|
(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Map a mode to a specific constraint character.
|
|
|
|
|
(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
|
|
|
|
|
|
|
|
|
|
(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
|
|
|
|
|
(V4HI "4h") (V8HI "8h")
|
|
|
|
|
(V2SI "2s") (V4SI "4s")
|
|
|
|
|
(DI "1d") (DF "1d")
|
|
|
|
|
(V2DI "2d") (V2SF "2s")
|
|
|
|
|
(V4SF "4s") (V2DF "2d")])
|
|
|
|
|
|
2014-04-24 10:05:07 +02:00
|
|
|
(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
|
|
|
|
|
(V4SI "32") (V2DI "64")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
|
|
|
|
|
(V4HI ".4h") (V8HI ".8h")
|
|
|
|
|
(V2SI ".2s") (V4SI ".4s")
|
|
|
|
|
(V2DI ".2d") (V2SF ".2s")
|
|
|
|
|
(V4SF ".4s") (V2DF ".2d")
|
|
|
|
|
(DI "") (SI "")
|
|
|
|
|
(HI "") (QI "")
|
2013-05-01 12:33:57 +02:00
|
|
|
(TI "") (SF "")
|
|
|
|
|
(DF "")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
;; Register suffix narrowed modes for VQN.
|
|
|
|
|
(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
|
|
|
|
|
(V2DI ".2s")
|
|
|
|
|
(DI "") (SI "")
|
|
|
|
|
(HI "")])
|
|
|
|
|
|
|
|
|
|
;; Mode-to-individual element type mapping.
|
|
|
|
|
(define_mode_attr Vetype [(V8QI "b") (V16QI "b")
|
|
|
|
|
(V4HI "h") (V8HI "h")
|
|
|
|
|
(V2SI "s") (V4SI "s")
|
|
|
|
|
(V2DI "d") (V2SF "s")
|
|
|
|
|
(V4SF "s") (V2DF "d")
|
2013-10-15 17:30:00 +02:00
|
|
|
(SF "s") (DF "d")
|
2012-10-23 19:02:30 +02:00
|
|
|
(QI "b") (HI "h")
|
|
|
|
|
(SI "s") (DI "d")])
|
|
|
|
|
|
|
|
|
|
;; Mode-to-bitwise operation type mapping.
|
|
|
|
|
(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
|
|
|
|
|
(V4HI "8b") (V8HI "16b")
|
|
|
|
|
(V2SI "8b") (V4SI "16b")
|
|
|
|
|
(V2DI "16b") (V2SF "8b")
|
2013-11-26 11:03:14 +01:00
|
|
|
(V4SF "16b") (V2DF "16b")
|
2014-12-19 18:48:15 +01:00
|
|
|
(DI "8b") (DF "8b")
|
|
|
|
|
(SI "8b")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
;; Define element mode for each vector mode.
|
|
|
|
|
(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
|
|
|
|
|
(V4HI "HI") (V8HI "HI")
|
|
|
|
|
(V2SI "SI") (V4SI "SI")
|
|
|
|
|
(DI "DI") (V2DI "DI")
|
|
|
|
|
(V2SF "SF") (V4SF "SF")
|
2013-09-16 11:50:21 +02:00
|
|
|
(V2DF "DF") (DF "DF")
|
2012-10-23 19:02:30 +02:00
|
|
|
(SI "SI") (HI "HI")
|
|
|
|
|
(QI "QI")])
|
|
|
|
|
|
2014-06-20 10:51:34 +02:00
|
|
|
;; 64-bit container modes the inner or scalar source mode.
|
|
|
|
|
(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
|
|
|
|
|
(V4HI "V4HI") (V8HI "V4HI")
|
2013-01-25 12:35:03 +01:00
|
|
|
(V2SI "V2SI") (V4SI "V2SI")
|
|
|
|
|
(DI "DI") (V2DI "DI")
|
|
|
|
|
(V2SF "V2SF") (V4SF "V2SF")
|
|
|
|
|
(V2DF "DF")])
|
|
|
|
|
|
2014-06-20 10:51:34 +02:00
|
|
|
;; 128-bit container modes the inner or scalar source mode.
|
2013-01-25 12:35:03 +01:00
|
|
|
(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
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(V4HI "V8HI") (V8HI "V8HI")
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(V2SI "V4SI") (V4SI "V4SI")
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(DI "V2DI") (V2DI "V2DI")
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(V2SF "V2SF") (V4SF "V4SF")
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(V2DF "V2DF") (SI "V4SI")
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(HI "V8HI") (QI "V16QI")])
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2012-10-23 19:02:30 +02:00
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;; Half modes of all vector modes.
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(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
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(V4HI "V2HI") (V8HI "V4HI")
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(V2SI "SI") (V4SI "V2SI")
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(V2DI "DI") (V2SF "SF")
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(V4SF "V2SF") (V2DF "DF")])
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;; Double modes of vector modes.
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(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
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(V2SI "V4SI") (V2SF "V4SF")
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(SI "V2SI") (DI "V2DI")
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(DF "V2DF")])
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;; Double modes of vector modes (lower case).
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(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
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(V2SI "v4si") (V2SF "v4sf")
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2013-06-12 17:34:06 +02:00
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(SI "v2si") (DI "v2di")
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(DF "v2df")])
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2012-10-23 19:02:30 +02:00
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;; Narrowed modes for VDN.
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(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
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(DI "V2SI")])
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;; Narrowed double-modes for VQN (Used for XTN).
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(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
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(V2DI "V2SI")
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(DI "SI") (SI "HI")
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(HI "QI")])
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;; Narrowed quad-modes for VQN (Used for XTN2).
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(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
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(V2DI "V4SI")])
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;; Register suffix narrowed modes for VQN.
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(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
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(V2DI "2s")])
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;; Register suffix narrowed modes for VQN.
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(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
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(V2DI "4s")])
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;; Widened modes of vector modes.
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(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
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(V2SI "V2DI") (V16QI "V8HI")
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(V8HI "V4SI") (V4SI "V2DI")
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(HI "SI") (SI "DI")]
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)
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[AArch64] Remove/merge redundant iterators
* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3,
bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3,
ior<mode>3, xor<mode>3, one_cmpl<mode>2,
aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>,
aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>,
aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed,
ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3,
reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>,
vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>):
Change VDQ to VDQ_I.
(mul<mode>3): Change VDQM to VDQ_BHSI.
(aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>,
aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3,
aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI.
(*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>,
aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>,
aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>):
Change VDW to VD_BHSI.
(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>):
Change VDIC to VD_BHSI.
* config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl,
saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n,
ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI.
* config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW,
VDIC, VDQQHS): Remove.
(Vwtype): Update comment (changing VDW to VD_BHSI).
From-SVN: r218310
2014-12-03 13:12:07 +01:00
|
|
|
;; Widened mode register suffixes for VD_BHSI/VQW.
|
2012-10-23 19:02:30 +02:00
|
|
|
(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
|
|
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|
|
(V2SI "2d") (V16QI "8h")
|
|
|
|
|
(V8HI "4s") (V4SI "2d")])
|
|
|
|
|
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|
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|
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;; Widened mode register suffixes for VDW/VQW.
|
|
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|
|
(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
|
|
|
|
|
(V2SI ".2d") (V16QI ".8h")
|
|
|
|
|
(V8HI ".4s") (V4SI ".2d")
|
|
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(SI "") (HI "")])
|
|
|
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|
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|
|
;; Lower part register suffixes for VQW.
|
|
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|
|
(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
|
|
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|
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(V4SI "2s")])
|
|
|
|
|
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|
|
;; Define corresponding core/FP element mode for each vector mode.
|
|
|
|
|
(define_mode_attr vw [(V8QI "w") (V16QI "w")
|
|
|
|
|
(V4HI "w") (V8HI "w")
|
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|
|
(V2SI "w") (V4SI "w")
|
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(DI "x") (V2DI "x")
|
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|
(V2SF "s") (V4SF "s")
|
|
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|
|
(V2DF "d")])
|
|
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|
|
|
2013-08-09 11:28:51 +02:00
|
|
|
;; Corresponding core element mode for each vector mode. This is a
|
|
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|
|
;; variation on <vw> mapping FP modes to GP regs.
|
|
|
|
|
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
|
|
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|
|
(V4HI "w") (V8HI "w")
|
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(V2SI "w") (V4SI "w")
|
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(DI "x") (V2DI "x")
|
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(V2SF "w") (V4SF "w")
|
|
|
|
|
(V2DF "x")])
|
|
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|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Double vector types for ALLX.
|
|
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|
|
(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
|
|
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|
|
;; Mode of result of comparison operations.
|
|
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|
|
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
|
|
|
|
|
(V4HI "V4HI") (V8HI "V8HI")
|
|
|
|
|
(V2SI "V2SI") (V4SI "V4SI")
|
2012-12-05 12:36:00 +01:00
|
|
|
(DI "DI") (V2DI "V2DI")
|
2012-10-23 19:02:30 +02:00
|
|
|
(V2SF "V2SI") (V4SF "V4SI")
|
2013-05-01 12:33:57 +02:00
|
|
|
(V2DF "V2DI") (DF "DI")
|
|
|
|
|
(SF "SI")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-01-18 17:34:10 +01:00
|
|
|
;; Lower case mode of results of comparison operations.
|
|
|
|
|
(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
|
|
|
|
|
(V4HI "v4hi") (V8HI "v8hi")
|
|
|
|
|
(V2SI "v2si") (V4SI "v4si")
|
|
|
|
|
(DI "di") (V2DI "v2di")
|
|
|
|
|
(V2SF "v2si") (V4SF "v4si")
|
2013-05-01 12:33:57 +02:00
|
|
|
(V2DF "v2di") (DF "di")
|
|
|
|
|
(SF "si")])
|
2013-01-18 17:34:10 +01:00
|
|
|
|
2014-09-25 18:54:38 +02:00
|
|
|
;; Lower case element modes (as used in shift immediate patterns).
|
|
|
|
|
(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
|
|
|
|
|
(V4HI "hi") (V8HI "hi")
|
|
|
|
|
(V2SI "si") (V4SI "si")
|
|
|
|
|
(DI "di") (V2DI "di")
|
|
|
|
|
(QI "qi") (HI "hi")
|
|
|
|
|
(SI "si")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Vm for lane instructions is restricted to FP_LO_REGS.
|
|
|
|
|
(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
|
|
|
|
|
(V2SI "w") (V4SI "w") (SI "w")])
|
|
|
|
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|
|
|
(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
|
|
|
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|
|
(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
|
|
|
|
|
|
|
|
|
|
(define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
|
|
|
|
|
(V2SI "V8SI") (V2SF "V8SF")
|
2015-07-30 18:04:08 +02:00
|
|
|
(DI "V4DI") (DF "V4DF")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
(define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI")
|
|
|
|
|
(V2SI "V12SI") (V2SF "V12SF")
|
2015-07-30 18:04:08 +02:00
|
|
|
(DI "V6DI") (DF "V6DF")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
(define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI")
|
|
|
|
|
(V2SI "V16SI") (V2SF "V16SF")
|
2015-07-30 18:04:08 +02:00
|
|
|
(DI "V8DI") (DF "V8DF")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
|
|
|
|
|
|
2014-04-28 23:05:51 +02:00
|
|
|
;; Mode of pair of elements for each vector mode, to define transfer
|
|
|
|
|
;; size for structure lane/dup loads and stores.
|
|
|
|
|
(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI")
|
|
|
|
|
(V4HI "SI") (V8HI "SI")
|
|
|
|
|
(V2SI "V2SI") (V4SI "V2SI")
|
|
|
|
|
(DI "V2DI") (V2DI "V2DI")
|
|
|
|
|
(V2SF "V2SF") (V4SF "V2SF")
|
|
|
|
|
(DF "V2DI") (V2DF "V2DI")])
|
|
|
|
|
|
|
|
|
|
;; Similar, for three elements.
|
|
|
|
|
(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
|
|
|
|
|
(V4HI "BLK") (V8HI "BLK")
|
|
|
|
|
(V2SI "BLK") (V4SI "BLK")
|
|
|
|
|
(DI "EI") (V2DI "EI")
|
|
|
|
|
(V2SF "BLK") (V4SF "BLK")
|
|
|
|
|
(DF "EI") (V2DF "EI")])
|
|
|
|
|
|
|
|
|
|
;; Similar, for four elements.
|
|
|
|
|
(define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI")
|
|
|
|
|
(V4HI "V4HI") (V8HI "V4HI")
|
|
|
|
|
(V2SI "V4SI") (V4SI "V4SI")
|
|
|
|
|
(DI "OI") (V2DI "OI")
|
|
|
|
|
(V2SF "V4SF") (V4SF "V4SF")
|
|
|
|
|
(DF "OI") (V2DF "OI")])
|
|
|
|
|
|
|
|
|
|
|
2012-11-20 11:07:34 +01:00
|
|
|
;; Mode for atomic operation suffixes
|
|
|
|
|
(define_mode_attr atomic_sfx
|
|
|
|
|
[(QI "b") (HI "h") (SI "") (DI "")])
|
|
|
|
|
|
2014-04-22 13:34:52 +02:00
|
|
|
(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
|
|
|
|
|
(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
|
|
|
|
|
|
|
|
|
|
;; for the inequal width integer to fp conversions
|
|
|
|
|
(define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
|
|
|
|
|
(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
[AArch64] Rewrite the vdup_lane intrinsics in C
gcc/
* config/aarch64/aarch64-simd-builtins.def
(dup_lane_scalar): Remove.
* config/aarch64/aarch64-simd.md
(aarch64_simd_dup): Add 'w->w' alternative.
(aarch64_dup_lane<mode>): Allow for VALL.
(aarch64_dup_lane_scalar<mode>): Remove.
(aarch64_dup_lane_<vswap_width_name><mode>): New.
(aarch64_get_lane_signed<mode>): Add w->w altenative.
(aarch64_get_lane_unsigned<mode>): Likewise.
(aarch64_get_lane<mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_evpc_dup): New.
(aarch64_expand_vec_perm_const_1): Use aarch64_evpc_dup.
* config/aarch64/iterators.md (VSWAP_WIDTH): New.
(VCON): Change container of V2SF.
(vswap_width_name): Likewise.
* config/aarch64/arm_neon.h
(__aarch64_vdup_lane_any): New.
(__aarch64_vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
(vdup<q>_n_<psuf><8,16,32,64>): Convert to C implementation.
(vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
gcc/testsuite/
* gcc.target/aarch64/scalar_intrinsics.c
(vdup<bhsd>_lane<su><8,16,32,64>): Force values to SIMD registers.
From-SVN: r202180
2013-09-02 18:22:10 +02:00
|
|
|
(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
|
|
|
|
|
(V4HI "V8HI") (V8HI "V4HI")
|
|
|
|
|
(V2SI "V4SI") (V4SI "V2SI")
|
|
|
|
|
(DI "V2DI") (V2DI "DI")
|
|
|
|
|
(V2SF "V4SF") (V4SF "V2SF")
|
|
|
|
|
(DF "V2DF") (V2DF "DF")])
|
|
|
|
|
|
|
|
|
|
(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
|
|
|
|
|
(V4HI "to_128") (V8HI "to_64")
|
|
|
|
|
(V2SI "to_128") (V4SI "to_64")
|
|
|
|
|
(DI "to_128") (V2DI "to_64")
|
|
|
|
|
(V2SF "to_128") (V4SF "to_64")
|
|
|
|
|
(DF "to_128") (V2DF "to_64")])
|
|
|
|
|
|
2013-09-16 11:50:21 +02:00
|
|
|
;; For certain vector-by-element multiplication instructions we must
|
|
|
|
|
;; constrain the HI cases to use only V0-V15. This is covered by
|
|
|
|
|
;; the 'x' constraint. All other modes may use the 'w' constraint.
|
|
|
|
|
(define_mode_attr h_con [(V2SI "w") (V4SI "w")
|
|
|
|
|
(V4HI "x") (V8HI "x")
|
|
|
|
|
(V2SF "w") (V4SF "w")
|
|
|
|
|
(V2DF "w") (DF "w")])
|
|
|
|
|
|
|
|
|
|
;; Defined to 'f' for types whose element type is a float type.
|
|
|
|
|
(define_mode_attr f [(V8QI "") (V16QI "")
|
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
|
(DI "") (V2DI "")
|
|
|
|
|
(V2SF "f") (V4SF "f")
|
|
|
|
|
(V2DF "f") (DF "f")])
|
|
|
|
|
|
2013-10-15 17:30:00 +02:00
|
|
|
;; Defined to '_fp' for types whose element type is a float type.
|
|
|
|
|
(define_mode_attr fp [(V8QI "") (V16QI "")
|
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
|
(DI "") (V2DI "")
|
|
|
|
|
(V2SF "_fp") (V4SF "_fp")
|
|
|
|
|
(V2DF "_fp") (DF "_fp")
|
|
|
|
|
(SF "_fp")])
|
|
|
|
|
|
2013-10-15 17:26:15 +02:00
|
|
|
;; Defined to '_q' for 128-bit types.
|
|
|
|
|
(define_mode_attr q [(V8QI "") (V16QI "_q")
|
2013-10-15 17:30:00 +02:00
|
|
|
(V4HI "") (V8HI "_q")
|
|
|
|
|
(V2SI "") (V4SI "_q")
|
|
|
|
|
(DI "") (V2DI "_q")
|
|
|
|
|
(V2SF "") (V4SF "_q")
|
|
|
|
|
(V2DF "_q")
|
|
|
|
|
(QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
|
2013-10-15 17:26:15 +02:00
|
|
|
|
aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap for big-endian.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
(reduc_<sur>plus_<mode>): Factorize V2DI into this.
(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
and also change to float UNSPEC.
(reduc_maxmin_uns>_<mode>): Remove V2DI.
* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
result access for big-endian.
(__LANE0): New macro used to fix up lane access of 'across-lanes'
intrinsics for big-endian.
* config/aarch64/iterators.md (VDQV): Add V2DI.
(VDQV_S): New.
(vp): New mode attribute.
From-SVN: r205269
2013-11-22 16:34:36 +01:00
|
|
|
(define_mode_attr vp [(V8QI "v") (V16QI "v")
|
|
|
|
|
(V4HI "v") (V8HI "v")
|
|
|
|
|
(V2SI "p") (V4SI "v")
|
|
|
|
|
(V2DI "p") (V2DF "p")
|
|
|
|
|
(V2SF "p") (V4SF "v")])
|
|
|
|
|
|
2014-11-21 17:56:21 +01:00
|
|
|
(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
|
|
|
|
|
(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
|
|
|
|
|
|
2015-01-21 18:53:44 +01:00
|
|
|
(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
|
|
|
|
|
|
2015-06-26 16:00:56 +02:00
|
|
|
;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
|
|
|
|
|
;; No need of iterator for -fPIC as it use got_lo12 for both modes.
|
|
|
|
|
(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Code Iterators
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
;; This code iterator allows the various shifts supported on the core
|
|
|
|
|
(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
|
|
|
|
|
|
|
|
|
|
;; This code iterator allows the shifts supported in arithmetic instructions
|
|
|
|
|
(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for logical operations
|
|
|
|
|
(define_code_iterator LOGICAL [and ior xor])
|
|
|
|
|
|
2014-12-19 18:59:23 +01:00
|
|
|
;; Code iterator for logical operations whose :nlogical works on SIMD registers.
|
|
|
|
|
(define_code_iterator NLOGICAL [and ior])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Code iterator for sign/zero extension
|
|
|
|
|
(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
|
|
|
|
|
|
|
|
|
|
;; All division operations (signed/unsigned)
|
|
|
|
|
(define_code_iterator ANY_DIV [div udiv])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for sign/zero extraction
|
|
|
|
|
(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for equality comparisons
|
|
|
|
|
(define_code_iterator EQL [eq ne])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for less-than and greater/equal-to
|
|
|
|
|
(define_code_iterator LTGE [lt ge])
|
|
|
|
|
|
|
|
|
|
;; Iterator for __sync_<op> operations that where the operation can be
|
|
|
|
|
;; represented directly RTL. This is all of the sync operations bar
|
|
|
|
|
;; nand.
|
2012-11-20 11:07:34 +01:00
|
|
|
(define_code_iterator atomic_op [plus minus ior xor and])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
;; Iterator for integer conversions
|
|
|
|
|
(define_code_iterator FIXUORS [fix unsigned_fix])
|
|
|
|
|
|
2013-04-29 12:54:32 +02:00
|
|
|
;; Iterator for float conversions
|
|
|
|
|
(define_code_iterator FLOATUORS [float unsigned_float])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Code iterator for variants of vector max and min.
|
|
|
|
|
(define_code_iterator MAXMIN [smax smin umax umin])
|
|
|
|
|
|
2013-05-01 17:16:14 +02:00
|
|
|
(define_code_iterator FMAXMIN [smax smin])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Code iterator for variants of vector max and min.
|
|
|
|
|
(define_code_iterator ADDSUB [plus minus])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for variants of vector saturating binary ops.
|
|
|
|
|
(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for variants of vector saturating unary ops.
|
|
|
|
|
(define_code_iterator UNQOPS [ss_neg ss_abs])
|
|
|
|
|
|
|
|
|
|
;; Code iterator for signed variants of vector saturating binary ops.
|
|
|
|
|
(define_code_iterator SBINQOPS [ss_plus ss_minus])
|
|
|
|
|
|
2013-05-01 12:33:57 +02:00
|
|
|
;; Comparison operators for <F>CM.
|
|
|
|
|
(define_code_iterator COMPARISONS [lt le eq ge gt])
|
|
|
|
|
|
|
|
|
|
;; Unsigned comparison operators.
|
|
|
|
|
(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
|
|
|
|
|
|
2013-05-01 12:46:00 +02:00
|
|
|
;; Unsigned comparison operators.
|
|
|
|
|
(define_code_iterator FAC_COMPARISONS [lt le ge gt])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Code Attributes
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Map rtl objects to optab names
|
|
|
|
|
(define_code_attr optab [(ashift "ashl")
|
|
|
|
|
(ashiftrt "ashr")
|
|
|
|
|
(lshiftrt "lshr")
|
|
|
|
|
(rotatert "rotr")
|
|
|
|
|
(sign_extend "extend")
|
|
|
|
|
(zero_extend "zero_extend")
|
|
|
|
|
(sign_extract "extv")
|
|
|
|
|
(zero_extract "extzv")
|
2013-04-29 13:04:56 +02:00
|
|
|
(fix "fix")
|
|
|
|
|
(unsigned_fix "fixuns")
|
2013-04-29 12:54:32 +02:00
|
|
|
(float "float")
|
|
|
|
|
(unsigned_float "floatuns")
|
2012-10-23 19:02:30 +02:00
|
|
|
(and "and")
|
|
|
|
|
(ior "ior")
|
|
|
|
|
(xor "xor")
|
|
|
|
|
(not "one_cmpl")
|
|
|
|
|
(neg "neg")
|
|
|
|
|
(plus "add")
|
|
|
|
|
(minus "sub")
|
|
|
|
|
(ss_plus "qadd")
|
|
|
|
|
(us_plus "qadd")
|
|
|
|
|
(ss_minus "qsub")
|
|
|
|
|
(us_minus "qsub")
|
|
|
|
|
(ss_neg "qneg")
|
|
|
|
|
(ss_abs "qabs")
|
|
|
|
|
(eq "eq")
|
|
|
|
|
(ne "ne")
|
|
|
|
|
(lt "lt")
|
2013-05-01 12:33:57 +02:00
|
|
|
(ge "ge")
|
|
|
|
|
(le "le")
|
|
|
|
|
(gt "gt")
|
|
|
|
|
(ltu "ltu")
|
|
|
|
|
(leu "leu")
|
|
|
|
|
(geu "geu")
|
|
|
|
|
(gtu "gtu")])
|
|
|
|
|
|
|
|
|
|
;; For comparison operators we use the FCM* and CM* instructions.
|
|
|
|
|
;; As there are no CMLE or CMLT instructions which act on 3 vector
|
|
|
|
|
;; operands, we must use CMGE or CMGT and swap the order of the
|
|
|
|
|
;; source operands.
|
|
|
|
|
|
|
|
|
|
(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
|
|
|
|
|
(ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
|
|
|
|
|
(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
|
|
|
|
|
(ltu "2") (leu "2") (geu "1") (gtu "1")])
|
|
|
|
|
(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
|
|
|
|
|
(ltu "1") (leu "1") (geu "2") (gtu "2")])
|
|
|
|
|
|
|
|
|
|
(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
|
|
|
|
|
(ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-04-29 13:04:56 +02:00
|
|
|
(define_code_attr fix_trunc_optab [(fix "fix_trunc")
|
|
|
|
|
(unsigned_fix "fixuns_trunc")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Optab prefix for sign/zero-extending operations
|
|
|
|
|
(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
|
|
|
|
|
(div "") (udiv "u")
|
|
|
|
|
(fix "") (unsigned_fix "u")
|
2013-04-29 12:54:32 +02:00
|
|
|
(float "s") (unsigned_float "u")
|
2012-10-23 19:02:30 +02:00
|
|
|
(ss_plus "s") (us_plus "u")
|
|
|
|
|
(ss_minus "s") (us_minus "u")])
|
|
|
|
|
|
|
|
|
|
;; Similar for the instruction mnemonics
|
|
|
|
|
(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
|
|
|
|
|
(lshiftrt "lsr") (rotatert "ror")])
|
|
|
|
|
|
|
|
|
|
;; Map shift operators onto underlying bit-field instructions
|
|
|
|
|
(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
|
|
|
|
|
(lshiftrt "ubfx") (rotatert "extr")])
|
|
|
|
|
|
|
|
|
|
;; Logical operator instruction mnemonics
|
|
|
|
|
(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
|
|
|
|
|
|
|
|
|
|
;; Similar, but when not(op)
|
|
|
|
|
(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
|
|
|
|
|
|
|
|
|
|
;; Sign- or zero-extending load
|
|
|
|
|
(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
|
|
|
|
|
|
|
|
|
|
;; Sign- or zero-extending data-op
|
|
|
|
|
(define_code_attr su [(sign_extend "s") (zero_extend "u")
|
|
|
|
|
(sign_extract "s") (zero_extract "u")
|
|
|
|
|
(fix "s") (unsigned_fix "u")
|
2013-05-01 17:16:14 +02:00
|
|
|
(div "s") (udiv "u")
|
|
|
|
|
(smax "s") (umax "u")
|
|
|
|
|
(smin "s") (umin "u")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2015-01-27 16:20:14 +01:00
|
|
|
;; Emit conditional branch instructions.
|
|
|
|
|
(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; Emit cbz/cbnz depending on comparison type.
|
|
|
|
|
(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
|
|
|
|
|
|
|
|
|
|
;; Emit tbz/tbnz depending on comparison type.
|
|
|
|
|
(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
|
|
|
|
|
|
|
|
|
|
;; Max/min attributes.
|
2013-05-01 17:16:14 +02:00
|
|
|
(define_code_attr maxmin [(smax "max")
|
|
|
|
|
(smin "min")
|
|
|
|
|
(umax "max")
|
|
|
|
|
(umin "min")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
;; MLA/MLS attributes.
|
|
|
|
|
(define_code_attr as [(ss_plus "a") (ss_minus "s")])
|
|
|
|
|
|
2012-11-20 11:07:34 +01:00
|
|
|
;; Atomic operations
|
|
|
|
|
(define_code_attr atomic_optab
|
|
|
|
|
[(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
|
|
|
|
|
|
|
|
|
|
(define_code_attr atomic_op_operand
|
|
|
|
|
[(ior "aarch64_logical_operand")
|
|
|
|
|
(xor "aarch64_logical_operand")
|
|
|
|
|
(and "aarch64_logical_operand")
|
|
|
|
|
(plus "aarch64_plus_operand")
|
|
|
|
|
(minus "aarch64_plus_operand")])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Int Iterators.
|
|
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
|
|
|
|
|
UNSPEC_SMAXV UNSPEC_SMINV])
|
|
|
|
|
|
2013-05-01 17:16:14 +02:00
|
|
|
(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
|
|
|
|
|
UNSPEC_FMAXNMV UNSPEC_FMINNMV])
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
|
(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
|
|
|
|
|
UNSPEC_SRHADD UNSPEC_URHADD
|
|
|
|
|
UNSPEC_SHSUB UNSPEC_UHSUB
|
|
|
|
|
UNSPEC_SRHSUB UNSPEC_URHSUB])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
|
|
|
|
|
UNSPEC_SUBHN UNSPEC_RSUBHN])
|
|
|
|
|
|
|
|
|
|
(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
|
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UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
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2013-05-01 17:16:14 +02:00
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(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
|
2012-10-23 19:02:30 +02:00
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(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
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(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
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(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
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(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
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UNSPEC_SRSHL UNSPEC_URSHL])
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(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
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(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
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|
UNSPEC_SQRSHL UNSPEC_UQRSHL])
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(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
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UNSPEC_SRSRA UNSPEC_URSRA])
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(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
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UNSPEC_SSRI UNSPEC_USRI])
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(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
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(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
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(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
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UNSPEC_SQSHRN UNSPEC_UQSHRN
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UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
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2012-12-05 12:42:37 +01:00
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(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
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|
UNSPEC_TRN1 UNSPEC_TRN2
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UNSPEC_UZP1 UNSPEC_UZP2])
|
2012-10-23 19:02:30 +02:00
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|
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.
* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
* config/aarch64/iterators.md (REVERSE): New iterator.
(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
(rev_op): New int_attribute.
* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
Replace temporary __asm__ with __builtin_shuffle.
From-SVN: r211174
2014-06-03 13:28:55 +02:00
|
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(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
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|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
|
2013-04-29 12:17:51 +02:00
|
|
|
UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
|
|
|
|
|
UNSPEC_FRINTA])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
|
|
|
|
(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
|
[AArch64] Map fcvt intrinsics to builtin name directly.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Use new names for
fcvt builtins.
* config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as...
(lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This.
(fcvtzu): Split as...
(lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This.
(fcvtas): Split as...
(lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This.
(fcvtau): Split as...
(lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This.
(fcvtps): Split as...
(lceilv2sf, lceilv4sf, lceilv2df): ...This.
(fcvtpu): Split as...
(lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This.
(fcvtms): Split as...
(lfloorv2sf, lfloorv4sf, lfloorv2df): ...This.
(fcvtmu): Split as...
(lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This.
(lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New.
(lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise.
(lfrintnusf, lfrintnudf): Likewise.
* config/aarch64/aarch64-simd.md
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Convert to
define_insn.
(aarch64_fcvt<frint_suffix><su><mode>): Remove.
* config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN.
(fcvt_pattern): Likewise.
From-SVN: r198398
2013-04-29 12:51:46 +02:00
|
|
|
UNSPEC_FRINTA UNSPEC_FRINTN])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
2013-04-22 14:36:52 +02:00
|
|
|
(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
|
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
|
|
|
|
|
UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
|
|
|
|
|
UNSPEC_CRC32CW UNSPEC_CRC32CX])
|
|
|
|
|
|
Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
|
|
|
(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
|
|
|
|
|
(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
|
|
|
|
|
|
Implement support for AArch64 Crypto SHA1.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 15:55:47 +01:00
|
|
|
(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
|
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|
|
2013-12-19 16:00:53 +01:00
|
|
|
(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
|
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
;; -------------------------------------------------------------------
|
|
|
|
|
;; Int Iterators Attributes.
|
|
|
|
|
;; -------------------------------------------------------------------
|
2013-05-01 17:16:14 +02:00
|
|
|
(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
|
|
|
|
|
(UNSPEC_UMINV "umin")
|
|
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|
|
(UNSPEC_SMAXV "smax")
|
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|
|
|
(UNSPEC_SMINV "smin")
|
|
|
|
|
(UNSPEC_FMAX "smax_nan")
|
|
|
|
|
(UNSPEC_FMAXNMV "smax")
|
|
|
|
|
(UNSPEC_FMAXV "smax_nan")
|
|
|
|
|
(UNSPEC_FMIN "smin_nan")
|
|
|
|
|
(UNSPEC_FMINNMV "smin")
|
|
|
|
|
(UNSPEC_FMINV "smin_nan")])
|
|
|
|
|
|
|
|
|
|
(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
|
|
|
|
|
(UNSPEC_UMINV "umin")
|
|
|
|
|
(UNSPEC_SMAXV "smax")
|
|
|
|
|
(UNSPEC_SMINV "smin")
|
|
|
|
|
(UNSPEC_FMAX "fmax")
|
|
|
|
|
(UNSPEC_FMAXNMV "fmaxnm")
|
|
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|
|
(UNSPEC_FMAXV "fmax")
|
|
|
|
|
(UNSPEC_FMIN "fmin")
|
|
|
|
|
(UNSPEC_FMINNMV "fminnm")
|
|
|
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|
(UNSPEC_FMINV "fmin")])
|
2012-10-23 19:02:30 +02:00
|
|
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|
|
|
|
|
(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
|
|
|
|
|
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
|
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|
(UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
|
|
|
|
|
(UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
|
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|
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|
(UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
|
|
|
|
|
(UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
|
|
|
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|
(UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
|
|
|
|
|
(UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
|
|
|
|
|
(UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
|
|
|
|
|
(UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
|
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(UNSPEC_SSLI "s") (UNSPEC_USLI "u")
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(UNSPEC_SSRI "s") (UNSPEC_USRI "u")
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(UNSPEC_USRA "u") (UNSPEC_SSRA "s")
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(UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
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(UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
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(UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
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(UNSPEC_UQSHL "u")
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(UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
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(UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
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(UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
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(UNSPEC_USHL "u") (UNSPEC_SSHL "s")
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(UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
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(UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
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(UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
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])
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(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
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(UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
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(UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
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(UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
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(UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
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(UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
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])
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(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
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(UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
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(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
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(UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
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(UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
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(UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
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(define_int_attr addsub [(UNSPEC_SHADD "add")
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(UNSPEC_UHADD "add")
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(UNSPEC_SRHADD "add")
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(UNSPEC_URHADD "add")
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(UNSPEC_SHSUB "sub")
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(UNSPEC_UHSUB "sub")
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(UNSPEC_SRHSUB "sub")
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(UNSPEC_URHSUB "sub")
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(UNSPEC_ADDHN "add")
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(UNSPEC_SUBHN "sub")
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(UNSPEC_RADDHN "add")
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(UNSPEC_RSUBHN "sub")
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(UNSPEC_ADDHN2 "add")
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(UNSPEC_SUBHN2 "sub")
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(UNSPEC_RADDHN2 "add")
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(UNSPEC_RSUBHN2 "sub")])
|
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2014-09-25 18:54:38 +02:00
|
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(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
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(UNSPEC_SSRI "offset_")
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(UNSPEC_USRI "offset_")])
|
2012-10-23 19:02:30 +02:00
|
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|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
;; Standard pattern names for floating-point rounding instructions.
|
|
|
|
|
(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
|
|
|
|
|
(UNSPEC_FRINTP "ceil")
|
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|
|
(UNSPEC_FRINTM "floor")
|
|
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|
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(UNSPEC_FRINTI "nearbyint")
|
|
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|
|
(UNSPEC_FRINTX "rint")
|
2013-04-29 12:17:51 +02:00
|
|
|
(UNSPEC_FRINTA "round")
|
|
|
|
|
(UNSPEC_FRINTN "frintn")])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
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|
|
;; frint suffix for floating-point rounding instructions.
|
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|
|
(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
|
|
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|
|
(UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
|
2013-04-29 12:17:51 +02:00
|
|
|
(UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
|
|
|
|
|
(UNSPEC_FRINTN "n")])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
|
|
|
|
(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
|
[AArch64] Map fcvt intrinsics to builtin name directly.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Use new names for
fcvt builtins.
* config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as...
(lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This.
(fcvtzu): Split as...
(lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This.
(fcvtas): Split as...
(lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This.
(fcvtau): Split as...
(lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This.
(fcvtps): Split as...
(lceilv2sf, lceilv4sf, lceilv2df): ...This.
(fcvtpu): Split as...
(lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This.
(fcvtms): Split as...
(lfloorv2sf, lfloorv4sf, lfloorv2df): ...This.
(fcvtmu): Split as...
(lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This.
(lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New.
(lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise.
(lfrintnusf, lfrintnudf): Likewise.
* config/aarch64/aarch64-simd.md
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Convert to
define_insn.
(aarch64_fcvt<frint_suffix><su><mode>): Remove.
* config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN.
(fcvt_pattern): Likewise.
From-SVN: r198398
2013-04-29 12:51:46 +02:00
|
|
|
(UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
|
|
|
|
|
(UNSPEC_FRINTN "frintn")])
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
2012-12-05 12:42:37 +01:00
|
|
|
(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
|
|
|
|
|
(UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
|
|
|
|
|
(UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
|
|
|
|
|
|
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.
* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
* config/aarch64/iterators.md (REVERSE): New iterator.
(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
(rev_op): New int_attribute.
* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
Replace temporary __asm__ with __builtin_shuffle.
From-SVN: r211174
2014-06-03 13:28:55 +02:00
|
|
|
; op code for REV instructions (size within which elements are reversed).
|
|
|
|
|
(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
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(UNSPEC_REV16 "16")])
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2012-12-05 12:42:37 +01:00
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(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
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(UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
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(UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
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2013-04-22 14:36:52 +02:00
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(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
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Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
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2014-06-11 11:17:18 +02:00
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(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
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(UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
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(UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
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(UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
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(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
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(UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
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(UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
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(UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
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Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
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(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
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(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
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Implement support for AArch64 Crypto SHA1.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 15:55:47 +01:00
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(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
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(UNSPEC_SHA1M "m")])
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2013-12-19 16:00:53 +01:00
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(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
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