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x86: fix swapped operand handling for BNDMOV The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns.
2018-03-22 08:32:50 +01:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/opts.s: Add bndmov cases.
* testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
testsuite/gas/i386/sse2avx-opts.d,
testsuite/gas/i386/sse2avx-opts-intel.d: Adjust expectations.
x86/Intel: fix fallout from earlier template folding While many templates allowing multiple suitably matching XMM/YMM/ZMM operand sizes can be folded, a few need to be split in order to not wrongly accept "xmmword ptr" operands when only XMM registers are permitted (and memory operands are more narrow). Add a test case validating this.
2018-03-22 08:31:43 +01:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size): Extend sub-xmmword
exceptions.
* testsuite/gas/i386/xmmword.l, testsuite/gas/i386/xmmword.s:
New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: fold a few XOP templates Also add a new test case verifying that mixed operands of SIMD insns with a size-less memory operand in the middle are properly rejected.
2018-03-22 08:29:45 +01:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Also match 2nd and 4th
operand's register sizes.
* testsuite/gas/i386/unspec.l, testsuite/gas/i386/unspec.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
Updated Spanish translation for the bfd/ sub-directory, and updated Ukranian translation for the gas/ sub-directory. bfd * po/es.po: Updated Spanish translation. gas * po/uk.po: Updated Ukranian translation.
2018-03-19 11:49:13 +01:00
2018-03-19 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
RISC-V: Emit better warning for unknown CSR. gas/ * config/tc-riscv.c (check_absolute_expr): Expand comment. New parameter maybe_csr. If maybe_csr and O_symbol, print CSR name. (riscv_ip): Add new argument to check_absolute_expr calls. * testsuite/gas/riscv/bad-csr.d: New. * testsuite/gas/riscv/bad-csr.l: New. * testsuite/gas/riscv/bad-csr.s: New.
2018-03-16 18:03:57 +01:00
2018-03-16 Jim Wilson <jimw@sifive.com>
* config/tc-riscv.c (check_absolute_expr): Expand comment. New
parameter maybe_csr. If maybe_csr and O_symbol, print CSR name.
(riscv_ip): Add new argument to check_absolute_expr calls.
* testsuite/gas/riscv/bad-csr.d: New.
* testsuite/gas/riscv/bad-csr.l: New.
* testsuite/gas/riscv/bad-csr.s: New.
RISC-V: Add .insn support. gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.
2018-03-15 00:04:03 +01:00
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (opcode_name_list): New.
(opcode_names_hash): Likewise.
(init_opcode_names_hash): Likewise.
(opcode_name_lookup): Likewise.
(validate_riscv_insn): New argument length, and add new format
which used in .insn directive.
(md_begin): Refine hash table initialization logic into
init_opcode_hash.
(init_opcode_hash): New.
(my_getOpcodeExpression): Parse opcode name for .insn.
(riscv_ip): New argument hash, able to handle .insn directive.
(s_riscv_insn): Handler for .insn directive.
(riscv_pseudo_table): New entry for .insn.
* doc/c-riscv.texi: Add documentation for .insn directive.
* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
* testsuite/gas/riscv/insn.s: Likewise.
Updated Russian and Brazilian Portuguese translations. ld * po/pt_BR.po: Updated Brazilian Portuguese translation. opcodes * po/pt_BR.po: Updated Brazilian Portuguese translation. gas * po/ru.po: Updated Russian translation.
2018-03-13 17:57:29 +01:00
2018-03-13 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
x86: Encode EVEX instructions with VEX128 if possible If EVEX encoding isn't required, we can encode EVEX instructions with VEX128. * config/tc-i386.c (optimize_encoding): Encode EVEX instructions with VEX128 if EVEX encoding isn't required. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
2018-03-09 17:10:27 +01:00
2018-03-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Encode EVEX instructions
with VEX128 if EVEX encoding isn't required.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
x86: Strip whitespace in check_VecOperations Since the addition of pseudo prefixes changed how the scrubber treats '{', we need to explicitly strip whitespace in check_VecOperations (). * config/tc-i386.c (check_VecOperations): Strip whitespace. * testsuite/gas/i386/optimize-1.s: Add whitespaces before {%k7} and {z}, * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
2018-03-09 12:51:19 +01:00
2018-03-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_VecOperations): Strip whitespace.
* testsuite/gas/i386/optimize-1.s: Add whitespaces before
{%k7} and {z},
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
x86: Optimize with EVEX128 encoding for AVX512VL We can optimize AVX512 instructions with EVEX128 only if AVX512VL is enabled: 1. Instruction is an AVX512VL instruction. Or 2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl". We should optimize EVEX instructions with EVEX128 encoding when pseudo {evex} prefix is used. * config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags. (md_parse_option): Likewise. (optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags for cpuavx512vl instead of cpu_arch_flags. Optimize EVEX with EVEX128 when EVEX encoding is required. * testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5, x86-64-optimize-5 and x86-64-optimize-6. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/optimize-4.d: New file. * testsuite/gas/i386/optimize-4.s: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
2018-03-09 04:57:35 +01:00
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
(md_parse_option): Likewise.
(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
for cpuavx512vl instead of cpu_arch_flags. Optimize EVEX with
EVEX128 when EVEX encoding is required.
* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
x86-64-optimize-5 and x86-64-optimize-6.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: New file.
* testsuite/gas/i386/optimize-4.s: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
x86-64: Also optimize "clr reg64" "clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as "xor reg32, reg32". gas/ * config/tc-i386.c (optimize_encoding): Also encode "clr reg64" as "xor reg32, reg32". * testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests. * testsuite/gas/i386/x86-64-optimize-1.d: Updated. opcodes/ * i386-opc.tbl: Add Optimize to clr. * i386-tbl.h: Regenerated.
2018-03-08 15:41:34 +01:00
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
x86: Remove support for old (<= 2.8.1) versions of gcc Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and fdivrp instructions. Assembler translates them to correct ones with a warning: [hjl@gnu-cfl-1 gas]$ cat x.s fsubp %st(3),%st [hjl@gnu-cfl-1 gas]$ gcc -c x.s x.s: Assembler messages: x.s:1: Warning: translating to `fsubp %st,%st(3)' [hjl@gnu-cfl-1 gas]$ This patch removes support for old (<= 2.8.1) versions of gcc: [hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s x.s: Assembler messages: x.s:1: Error: operand type mismatch for `fsubp' [hjl@gnu-cfl-1 gas]$ gas/ * NEWS: Mention -mold-gcc removal. * config/tc-i386.c (i386_error): Remove old_gcc_only. (old_gcc): Removed. (match_template): Remove old gcc support. (OPTION_MOLD_GCC): Removed. (OPTION_MRELAX_RELOCATIONS): Updated. (md_longopts): Remove OPTION_MOLD_GCC. (md_parse_option): Likewise. (md_show_usage): Remove -mold-gcc. * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old (<= 2.8.1) versions of gcc. * testsuite/gas/i386/intel.s: Likewise. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intel.e: Likewise. * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general. include/ * opcode/i386 (OLDGCC_COMPAT): Removed. opcodes/ * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp instructions for old (<= 2.8.1) versions of gcc. * i386-tbl.h: Regenerated.
2018-03-08 15:31:32 +01:00
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention -mold-gcc removal.
* config/tc-i386.c (i386_error): Remove old_gcc_only.
(old_gcc): Removed.
(match_template): Remove old gcc support.
(OPTION_MOLD_GCC): Removed.
(OPTION_MRELAX_RELOCATIONS): Updated.
(md_longopts): Remove OPTION_MOLD_GCC.
(md_parse_option): Likewise.
(md_show_usage): Remove -mold-gcc.
* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
(<= 2.8.1) versions of gcc.
* testsuite/gas/i386/intel.s: Likewise.
* testsuite/gas/i386/general.l: Updated.
* testsuite/gas/i386/intel-intel.d: Likewise.
* testsuite/gas/i386/intel.d: Likewise.
* testsuite/gas/i386/intel.e: Likewise.
* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.
x86: fold several AVX512VL templates The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold these as far as possible, and also fold register-only forms. Further folding is possible, but needs other prereq work done first. A note regarding EVEXDYN: This is intended to be used only when no other properties of the template would make is_evex_encoding() return true. In all "normal" cases I think it is preferable to omit this indicator, to keep the table half way readable.
2018-03-08 08:58:55 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (is_evex_encoding): New.
(optimize_encoding, md_assemble, md_assemble,
VEX_check_operands, build_modrm_byte): Use is_evex_encoding.
(build_evex_prefix): Derive EVEX length field from actual
operands if the template allows multiple ones.
x86: fold certain AVX512 rotate and shift templates Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust VexNDD handling to cope with these, allowing their register and memory forms to be folded.
2018-03-08 08:58:05 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (build_modrm_byte): Make VexNDD handling cope
with 3rd (immediate) operand.
x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIX They aren't really useful (anymore?): The conflicting operand size check isn't applicable to any insn validly using respective memory operand sizes (and if they're used wrongly, another error would result), and the logic in process_suffix() can be easily changed to work without them. While re-structuring conditionals in process_suffix() also drop the CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode table.
2018-03-08 08:52:27 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (XMMWORD_MNEM_SUFFIX, YMMWORD_MNEM_SUFFIX,
ZMMWORD_MNEM_SUFFIX): Delete.
(process_suffix): Drop their uses. Re-arrange final part of
logic into a switch() statement. Drop special casing of
cmpxchg8b.
x86: correct operand size match checks for BMI/BMI2 insns Some BMI/BMI2 insns allow their middle operands to be a memory one. In such a case, matching register types between operands 0 and 1 as well as 1 and 2 won't help - operands 0 and 2 also need to be checked.
2018-03-08 08:51:18 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Also match register
operands 0 and 2 for 3-operand forms.
* testsuite/gas/i386/unspec64.l, testsuite/gas/i386/unspec64.s:
New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: fold redundant expressions in process_suffix() There's no point repeatedly evaluating i.types[op].bitfield.reg.
2018-03-08 08:50:13 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Do common part of register
checks first.
x86: simplify result processing of cpu_flags_match() Make more obvious what the success and failure paths are, and in particular that what used to be at the "skip" label can't be reached by what used to be straight line code.
2018-03-08 08:48:10 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_insn): Move success return up. Combine
failure returns.
x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match() Just like for the AVX/AES and AVX/PCLMUL combinations, AVX/GFN, AVX512F/GFNI, AVX512F/VAES, and AVX512F/PCLMUL need special handling to deal with the pair of required checks specified in the templates.
2018-03-08 08:47:32 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_flags_match): Add GFNI check to AVX
logic. Add respective logic for AVX512F.
* testsuite/gas/i386/arch-avx-1.s: Add GFNI test.
testsuite/gas/i386/arch-avx-1.d,
testsuite/gas/i386/arch-avx-1-1.l,
testsuite/gas/i386/arch-avx-1-2.l,
testsuite/gas/i386/arch-avx-1-3.l,
testsuite/gas/i386/arch-avx-1-4.l,
testsuite/gas/i386/arch-avx-1-5.l,
testsuite/gas/i386/arch-avx-1-6.l: Adjust expectations.
* testsuite/gas/i386/arch-avx-1-7.l,
testsuite/gas/i386/arch-avx-1-7.s,
testsuite/gas/i386/arch-avx-1-8.l,
testsuite/gas/i386/arch-avx-1-8.s,
testsuite/gas/i386/avx512f-plain.l,
testsuite/gas/i386/avx512f-plain.s,
testsuite/gas/i386/avx512vl-plain.l,
testsuite/gas/i386/avx512vl-plain.s: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: change AVX512VL handling in cpu_flags_match() In order to add an AVX512F counterpart to the present AVX checking, it is better to move the AVX512VL check out of the conditional it's currently in.
2018-03-08 08:45:56 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_flags_match): Move AVX512VL check ahead.
x86: drop CPU_FLAGS_32BIT_MATCH It has become a plain alias of CPU_FLAGS_ARCH_MATCH now.
2018-03-08 08:45:25 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (CPU_FLAGS_32BIT_MATCH): Delete.
(cpu_flags_match): Use CPU_FLAGS_ARCH_MATCH instead of
CPU_FLAGS_32BIT_MATCH.
x86: simplify AVX checks in cpu_flags_match() No caller cares about the specifics of CPU_FLAGS_{AES,AVX,PCLMUL}_MATCH, so drop those and fold the nested if()-s.
2018-03-08 08:44:52 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (CPU_FLAGS_AES_MATCH, CPU_FLAGS_AVX_MATCH,
CPU_FLAGS_PCLMUL_MATCH): Delete.
(CPU_FLAGS_32BIT_MATCH): Drop uses of deleted CPU_FLAGS_*_MATCH.
(cpu_flags_match): Combine AVX checks into
single if().
x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCH
2018-03-08 08:44:12 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_flags_match): Drop "else" branches
setting CPU_FLAGS_ARCH_MATCH.
x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns When aiming at not mixing SSE and AVX insns, these should be warned about the same way other non-AVX ones are treated.
2018-03-08 08:35:01 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Extend SSE check conditional.
* testsuite/gas/i386/ilp32/x86-64-sse-check-none.d,
testsuite/gas/i386/ilp32/x86-64-sse-check-warn.d,
testsuite/gas/i386/ilp32/x86-64-sse-check.d,
testsuite/gas/i386/sse-check-none.d,
testsuite/gas/i386/sse-check-warn.d,
testsuite/gas/i386/x86-64-sse-check.d,
testsuite/gas/i386/x86-64-sse-check-none.d,
testsuite/gas/i386/x86-64-sse-check-warn.d: Refer to sse-check.d.
* testsuite/gas/i386/sse-check.s: Add AES, GFNI, and PCLMUL
tests.
* testsuite/gas/i386/sse-check-none.s: Replace code by inclusion
of sse-check.s.
* testsuite/gas/i386/sse-check.d: Adjust expectations.
* testsuite/gas/i386/sse-check-error.l,
testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.
* testsuite/gas/i386/sse-check-warn.e: Likewise.
x86: drop FloatD It can be expressed by D, when making the consumer look at operand size to tell apart both uses.
2018-03-08 08:34:09 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_size_match): Drop / replace uses of
.floatd.
x86/Intel: correct disassembly of fsub*/fdiv* fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).
2018-03-08 08:33:06 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/intel-intel.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: adjust 4-XMM-register-group related warning Drop "second": For one there's no other source register (the other source operand is in memory), and in Intel syntax such numbering would also be wrong. Take the opportunity and also - properly place declarations ahead of statements - use %u format for unsigned int arguments - fix indentation
2018-03-08 08:27:28 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Access operands only
after operand count assertion. Sanitize warning text. Fix
indentation.
* testsuite/gas/i386/avx512_4fmaps-warn.l,
gas/i386/x86-64-avx512_4fmaps-warn.l: Adjust expectations.
x86: bogus VMOVD with 64-bit operands should only allow for registers These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands.
2018-03-08 08:26:35 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-movd.s: Drop bogus vmovd memory forms.
* testsuite/gas/i386/x86-64-movd.d,
testsuite/gas/i386/x86-64-movd-intel.d: Adjust expectations.
x86: fold AVX vcvtpd2ps memory forms This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.
2018-03-08 08:25:31 +01:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_and_not): New.
(build_modrm_byte): Use it to prevent clearing unrelated bits.
Really remove unnecessary power9 group terminating nop Oops, not tested well enough. -mpower9 sets all the PPC_OPCODE_POWERn for n <= 9. * config/tc-ppc.c (ppc_handle_align): Correct last patch. Really don't emit a group terminating nop for power9. Simplify cpu tests.
2018-03-08 05:04:09 +01:00
2018-03-08 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_handle_align): Correct last patch. Really
don't emit a group terminating nop for power9. Simplify cpu
tests.
Remove unnecessary power9 group terminating nop Power9 doesn't have a group terminating nop, so we may as well emit a normal nop for power9. Not that it matters a great deal, I believe ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware. * config/tc-ppc.c (ppc_handle_align): Don't emit a group terminating nop for power9.
2018-03-08 00:47:41 +01:00
2018-03-08 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_handle_align): Don't emit a group
terminating nop for power9.
x86: Rewrite NOP generation for fill and alignment Rewrite NOP generation for fill and code alignment by: 1. Add a 11-byte NOP with another 0x66 prefix. 2. Remove the multi-byte NOP entries which consist of 2 instructions. 3. Select proper NOPs based on ISA and processor tuning. 4. Generate multiple NOPs with the longer NOPs first followed by the shorter NOP. 5. Use jump for larger NOP padding: a. > 8 bytes (2 NOPs) in 16-bit mode. b. > 14 bytes (2 NOPs) for older processors. c. > 77 bytes (7 NOPs) for newer processors. 6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095. PR gas/22874 * config/tc-i386.c (f32_5): Removed. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (alt64_11): Likewise. (alt64_patt): Likewise. (jump_disp8): New. (jump32_disp32): Likewise. (jump16_disp32): Likewise. (alt_11): Likewise. (f32_patt): Updated. (f16_patt): Likewise. (alt_patt): Add alt_11. (i386_align_code): Merged with ... (i386_generate_nops): This. Rewritten. (fits_in_imm7): Moved before i386_generate_nops. (fits_in_imm31): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to 4095. (i386_align_code): Removed. (HANDLE_ALIGN): Rewritten with i386_generate_nops. * doc/as.texinfo: Update limits of control byte for x86 .nops directive. * testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7. * gas/testsuite/gas/i386/noavx-3.l: Updated. * gas/testsuite/gas/i386/nop-1.d: Likewise. * gas/testsuite/gas/i386/nop-1.s: Likewise. * gas/testsuite/gas/i386/nop-2.d: Likewise. * gas/testsuite/gas/i386/nop-2.s: Likewise. * gas/testsuite/gas/i386/nop-3.d: Likewise. * gas/testsuite/gas/i386/nop-4.d: Likewise. * gas/testsuite/gas/i386/nop-5.d: Likewise. * gas/testsuite/gas/i386/nop-5.s: Likewise. * gas/testsuite/gas/i386/nop-6.d: Likewise. * gas/testsuite/gas/i386/nop-bad-1.l: Likewise. * gas/testsuite/gas/i386/nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386.d: Likewise. * gas/testsuite/gas/i386/nops-1-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/nops-1.d: Likewise. * gas/testsuite/gas/i386/nops-2-core2.d: Likewise. * gas/testsuite/gas/i386/nops-2-i386.d: Likewise. * gas/testsuite/gas/i386/nops-2.d: Likewise. * gas/testsuite/gas/i386/nops-3-i386.d: Likewise. * gas/testsuite/gas/i386/nops-3-i686.d: Likewise. * gas/testsuite/gas/i386/nops-3.d: Likewise. * gas/testsuite/gas/i386/nops-4-i386.d: Likewise. * gas/testsuite/gas/i386/nops-4-i686.d: Likewise. * gas/testsuite/gas/i386/nops-4.d: Likewise. * gas/testsuite/gas/i386/nops-4a-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-6.d: Likewise. * gas/testsuite/gas/i386/nops16-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-7.d: New file. * gas/testsuite/gas/i386/nops-7.s: Likewise. * gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07 13:18:45 +01:00
2018-03-07 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22874
* config/tc-i386.c (f32_5): Removed.
(f32_8): Likewise.
(f32_9): Likewise.
(f32_10): Likewise.
(f32_11): Likewise.
(f32_12): Likewise.
(f32_13): Likewise.
(f32_14): Likewise.
(f16_5): Likewise.
(f16_6): Likewise.
(f16_7): Likewise.
(f16_8): Likewise.
(jump_31): Likewise.
(alt64_11): Likewise.
(alt64_patt): Likewise.
(jump_disp8): New.
(jump32_disp32): Likewise.
(jump16_disp32): Likewise.
(alt_11): Likewise.
(f32_patt): Updated.
(f16_patt): Likewise.
(alt_patt): Add alt_11.
(i386_align_code): Merged with ...
(i386_generate_nops): This. Rewritten.
(fits_in_imm7): Moved before i386_generate_nops.
(fits_in_imm31): Likewise.
* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to
4095.
(i386_align_code): Removed.
(HANDLE_ALIGN): Rewritten with i386_generate_nops.
* doc/as.texinfo: Update limits of control byte for x86 .nops
directive.
* testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7.
* gas/testsuite/gas/i386/noavx-3.l: Updated.
* gas/testsuite/gas/i386/nop-1.d: Likewise.
* gas/testsuite/gas/i386/nop-1.s: Likewise.
* gas/testsuite/gas/i386/nop-2.d: Likewise.
* gas/testsuite/gas/i386/nop-2.s: Likewise.
* gas/testsuite/gas/i386/nop-3.d: Likewise.
* gas/testsuite/gas/i386/nop-4.d: Likewise.
* gas/testsuite/gas/i386/nop-5.d: Likewise.
* gas/testsuite/gas/i386/nop-5.s: Likewise.
* gas/testsuite/gas/i386/nop-6.d: Likewise.
* gas/testsuite/gas/i386/nop-bad-1.l: Likewise.
* gas/testsuite/gas/i386/nops-1-core2.d: Likewise.
* gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-1-i386.d: Likewise.
* gas/testsuite/gas/i386/nops-1-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-1-k8.d: Likewise.
* gas/testsuite/gas/i386/nops-1.d: Likewise.
* gas/testsuite/gas/i386/nops-2-core2.d: Likewise.
* gas/testsuite/gas/i386/nops-2-i386.d: Likewise.
* gas/testsuite/gas/i386/nops-2.d: Likewise.
* gas/testsuite/gas/i386/nops-3-i386.d: Likewise.
* gas/testsuite/gas/i386/nops-3-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-3.d: Likewise.
* gas/testsuite/gas/i386/nops-4-i386.d: Likewise.
* gas/testsuite/gas/i386/nops-4-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-4.d: Likewise.
* gas/testsuite/gas/i386/nops-4a-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-5-i686.d: Likewise.
* gas/testsuite/gas/i386/nops-5.d: Likewise.
* gas/testsuite/gas/i386/nops-6.d: Likewise.
* gas/testsuite/gas/i386/nops16-1.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
* gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise.
* gas/testsuite/gas/i386/nops-7.d: New file.
* gas/testsuite/gas/i386/nops-7.s: Likewise.
* gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
XCOFF disassembler xcoff (32-bit) objdump accepted but ignored -M options unless -mpowerpc was also given. This patch fixes that, leaving the default as -Mpwr for xcoff. I've also enabled more tests for xcoff targets. binutils/ * configure.ac: Add objdump_private_desc_xcoff for rs6000. * configure: Regenerate. gas/ * testsuite/gas/ppc/aix.exp: Run for rs6000 too. * testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets. * testsuite/gas/ppc/machine.d: Don't run for PE targets. opcodes/ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for bfd_arch_rs6000. * disassemble.h (print_insn_rs6000): Delete. * ppc-dis.c (powerpc_init_dialect): Handle rs6000. (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. (print_insn_rs6000): Delete.
2018-03-07 01:36:15 +01:00
2018-03-07 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
* testsuite/gas/ppc/machine.d: Don't run for PE targets.
[ARM] Fix NULL dereference of march_ext_opt Commit 4d354d8b8932d450c77fd52f3501662827523014 introduced a NULL pointer dereference by replacing a pointer assignment by a pointer dereference assignment without adding a NULL pointer check. This patch fixes it. 2018-03-02 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (md_begin): Add NULL pointer check before dereferencing march_ext_opt.
2018-03-02 11:46:32 +01:00
2018-03-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (md_begin): Add NULL pointer check before
dereferencing march_ext_opt.
[ARM] Clean up selection of feature bits I've always found the code in ARM backend of gas to control what CPU/architecture and FPU are selected by the user and to support autodetection of features complex and confusing. Chief among the issues I have with that code is the lack of comments to explain the meaning of the various variables. This patch addresses that and much more: - add comments to explain meaning of all arm_feature_set variables - keep track of currently selected CPU, extensions and FPU in a separate set of new variables - make naming of variable more consistent - remove dead code - simplify handling of extensions The overall approach is as follows: * restrict m*_opt variable to hold the feature bits of the corresponding mcpu/march/mfpu command-line options * record selected CPU, extensions and FPU in new selected_* during md_begin * whenever a .cpu/.arch/.arch_extension/.fpu directive is met, update the corresponding selected_* variables (eg. selected_arch, then selected_cpu for a .cpu or .arch directive) and then finally cpu_variant from them * pass extension feature set pointer by value to arm_parse_extension since it's only ever called from arm_parse_cpu and arm_parse_arch which allocate the extension feature set themselves * likewise, remove allocation from s_arm_arch_extension since the use of arm_feature_set structure for selected_ext rather than a pointer alleviate the need for it * in autodetection mode, only set all CPU fits in cpu_variant but leave selected_cpu* variables unset * in md_begin, remove dead "else if" to set a default FPU when no FPU was selected. Setting a default FPU based on CPU as did the code before it turn dead should be based on the default FPU field of the CPU and architecture table as will be done in a separate patch. Logic is wrong anyway since it sets VFP2 as default FPU for Armv6-M and Armv7-M Hopefully that should be enough to understand the change but if not feel free to ask questions about the patch. While I believe the new code is easier to understand, it remains complex and the old one was even more complex so the change is difficult to understand. 2018-03-01 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (cpu_variant, arm_arch_used, thumb_arch_used, legacy_cpu, legacy_fpu, mcpu_cpu_opt, dyn_mcpu_ext_opt, mcpu_fpu_opt, march_cpu_opt, dyn_march_ext_opt, march_fpu_opt, mfpu_opt, object_arch, selected_cpu): Comment meaning of variables. (dyn_mcpu_ext_opt): Also rename into ... (mcpu_ext_opt): This. (dyn_march_ext_opt): Also rename into ... (march_ext_opt): This. (object_arch): Also rename into ... (selected_object_arch): This and make it a plain arm_feature_set structure. (selected_arch, selected_ext, selected_fpu): New static variables. (mark_feature_used): Fix comments, feature is marked as used iff it is currently allowed. (do_bx): Adapt to change in name and type of object_arch. (md_begin): Set selected_arch rather than mcpu_cpu_opt, selected_ext rather than dyn_mcpu_ext_opt and selected_fpu rather than mfpu_opt. Remove dead code to set default FPU if architecture version is greater than 5. Set all CPU bits of cpu_variant directly in autodection leaving mcpu_cpu_opt, selected_arch and selected_cpu unset. (arm_parse_extension): Take extension feature set pointer parameter by value rather than by pointer. Remove allocation code. Adapt code accordingly. (arm_parse_cpu): Adapt to variable renaming and changes in arm_parse_extension () signature. (arm_parse_arch): Likewise. (aeabi_set_public_attributes): Also set selected_arch and selected_ext in addition to selected_cpu. Set flags_arch and flags_ext from them instead of selected_cpu. Adapt to variables renaming and type change. (arm_md_post_relax): Adapt to variable renaming. (s_arm_cpu): Set selcted_cpu_cpu and selected_ext instead of mcpu_cpu_opt and dyn_mcpu_ext_opt. Set selected_cpu from them and cpu_variant from selected_cpu and selected_fpu. (s_arm_arch): Likewise. (s_arm_object_arch): Adapt to variable renaming. (s_arm_arch_extension): Use ARM_CPU_IS_ANY instead of checking feature set against arm_any. Check selected_arch rather than *mcpu_cpu_opt. Set selected_ext rather than *dyn_mcpu_ext_opt and remove allocation code. (s_arm_fpu): Set selected_fpu instead of mfpu_opt. Set all CPU feature bits if in autodetection mode.
2018-03-01 17:22:28 +01:00
2018-03-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_variant, arm_arch_used, thumb_arch_used,
legacy_cpu, legacy_fpu, mcpu_cpu_opt, dyn_mcpu_ext_opt,
mcpu_fpu_opt, march_cpu_opt, dyn_march_ext_opt, march_fpu_opt,
mfpu_opt, object_arch, selected_cpu): Comment meaning of variables.
(dyn_mcpu_ext_opt): Also rename into ...
(mcpu_ext_opt): This.
(dyn_march_ext_opt): Also rename into ...
(march_ext_opt): This.
(object_arch): Also rename into ...
(selected_object_arch): This and make it a plain arm_feature_set
structure.
(selected_arch, selected_ext, selected_fpu): New static variables.
(mark_feature_used): Fix comments, feature is marked as used iff it is
currently allowed.
(do_bx): Adapt to change in name and type of object_arch.
(md_begin): Set selected_arch rather than mcpu_cpu_opt, selected_ext
rather than dyn_mcpu_ext_opt and selected_fpu rather than mfpu_opt.
Remove dead code to set default FPU if architecture version is greater
than 5. Set all CPU bits of cpu_variant directly in autodection
leaving mcpu_cpu_opt, selected_arch and selected_cpu unset.
(arm_parse_extension): Take extension feature set pointer parameter by
value rather than by pointer. Remove allocation code. Adapt code
accordingly.
(arm_parse_cpu): Adapt to variable renaming and changes in
arm_parse_extension () signature.
(arm_parse_arch): Likewise.
(aeabi_set_public_attributes): Also set selected_arch and selected_ext
in addition to selected_cpu. Set flags_arch and flags_ext from them
instead of selected_cpu. Adapt to variables renaming and type change.
(arm_md_post_relax): Adapt to variable renaming.
(s_arm_cpu): Set selcted_cpu_cpu and selected_ext instead of
mcpu_cpu_opt and dyn_mcpu_ext_opt. Set selected_cpu from them and
cpu_variant from selected_cpu and selected_fpu.
(s_arm_arch): Likewise.
(s_arm_object_arch): Adapt to variable renaming.
(s_arm_arch_extension): Use ARM_CPU_IS_ANY instead of checking feature
set against arm_any. Check selected_arch rather than *mcpu_cpu_opt.
Set selected_ext rather than *dyn_mcpu_ext_opt and remove allocation
code.
(s_arm_fpu): Set selected_fpu instead of mfpu_opt. Set all CPU feature
bits if in autodetection mode.
x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128 When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq] instructions can be encoded with VEX128 or EVEX128 encodings. gas/ * config/tc-i386.c (optimize_encoding): Optimize AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. opcodes/ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 vpsub[bwdq] instructions. * i386-tbl.h: Regenerated.
2018-03-01 15:08:04 +01:00
2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Optimize AVX256 and
AVX512 vpsub[bwdq] instructions.
* testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and
AVX512 vpsub[bwdq] instructions.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
Add missing translations to ALL_LINGUAS binutils/ * configure.ac (ALL_LINGUAS): Add sr. Sort. * configure: Regenerate. gas/ * configure.ac (ALL_LINGUAS): Add uk. Sort. * configure: Regenerate. gprof/ * configure.ac (ALL_LINGUAS): Add it, ro, ru, uk. Sort. * configure: Regenerate. ld/ * configure.ac (ALL_LINGUAS): Add ja. Sort. * configure: Regenerate. opcodes/ * configure.ac (ALL_LINGUAS): Sort. * configure: Regenerate.
2018-02-28 22:56:51 +01:00
2018-03-01 Alan Modra <amodra@gmail.com>
* configure.ac (ALL_LINGUAS): Add uk. Sort.
* configure: Regenerate.
gas: Rename .nop directive to .nops Since directives of NO_PSEUDO_DOT targets don't have the leading '.' and "nop" can be a valid instruction, rename .nop directive to .nops to avoid conflict. * NEWS: Rename .nop to .nops. * doc/as.texinfo: Likewise. * read.c (potable): Add "nops". Remove "nop". (s_nop): Renamed to ... (s_nops): This. * read.h (s_nop): Renamed to ... (s_nops): This. * write.c (cvt_frag_to_fill): Rename .nop to .nops. (md_generate_nops): Likewise. (relax_segment): Likewise. * testsuite/gas/i386/nop-1.d: Updated. * testsuite/gas/i386/nop-1.s: Likewise. * testsuite/gas/i386/nop-2.d: Likewise. * testsuite/gas/i386/nop-2.s: Likewise. * testsuite/gas/i386/nop-3.d: Likewise. * testsuite/gas/i386/nop-3.s: Likewise. * testsuite/gas/i386/nop-4.d: Likewise. * testsuite/gas/i386/nop-4.s: Likewise. * testsuite/gas/i386/nop-5.d: Likewise. * testsuite/gas/i386/nop-5.s: Likewise. * testsuite/gas/i386/nop-6.d: Likewise. * testsuite/gas/i386/nop-6.s: Likewise. * testsuite/gas/i386/nop-bad-1.l: Likewise. * testsuite/gas/i386/nop-bad-1.s: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-nop-2.d: Likewise. * testsuite/gas/i386/x86-64-nop-3.d: Likewise. * testsuite/gas/i386/x86-64-nop-4.d: Likewise. * testsuite/gas/i386/x86-64-nop-5.d: Likewise. * testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-27 23:45:48 +01:00
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Rename .nop to .nops.
* doc/as.texinfo: Likewise.
* read.c (potable): Add "nops". Remove "nop".
(s_nop): Renamed to ...
(s_nops): This.
* read.h (s_nop): Renamed to ...
(s_nops): This.
* write.c (cvt_frag_to_fill): Rename .nop to .nops.
(md_generate_nops): Likewise.
(relax_segment): Likewise.
* testsuite/gas/i386/nop-1.d: Updated.
* testsuite/gas/i386/nop-1.s: Likewise.
* testsuite/gas/i386/nop-2.d: Likewise.
* testsuite/gas/i386/nop-2.s: Likewise.
* testsuite/gas/i386/nop-3.d: Likewise.
* testsuite/gas/i386/nop-3.s: Likewise.
* testsuite/gas/i386/nop-4.d: Likewise.
* testsuite/gas/i386/nop-4.s: Likewise.
* testsuite/gas/i386/nop-5.d: Likewise.
* testsuite/gas/i386/nop-5.s: Likewise.
* testsuite/gas/i386/nop-6.d: Likewise.
* testsuite/gas/i386/nop-6.s: Likewise.
* testsuite/gas/i386/nop-bad-1.l: Likewise.
* testsuite/gas/i386/nop-bad-1.s: Likewise.
* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* testsuite/gas/i386/x86-64-nop-2.d: Likewise.
* testsuite/gas/i386/x86-64-nop-3.d: Likewise.
* testsuite/gas/i386/x86-64-nop-4.d: Likewise.
* testsuite/gas/i386/x86-64-nop-5.d: Likewise.
* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
x86: Add -O[2|s] assembler command-line options On x86, some instructions have alternate shorter encodings: 1. When the upper 32 bits of destination registers of andq $imm31, %r64 testq $imm31, %r64 xorq %r64, %r64 subq %r64, %r64 known to be zero, we can encode them without the REX_W bit: andl $imm31, %r32 testl $imm31, %r32 xorl %r32, %r32 subl %r32, %r32 This optimization is enabled with -O, -O2 and -Os. 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit immediate to 64-bit destination register, we can use it to encode 64-bit mov with 32-bit immediates. This optimization is enabled with -O, -O2 and -Os. 3. Since the upper bits of destination registers of VEX128 and EVEX128 instructions are extended to zero, if all bits of destination registers of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128 encoding to encode AVX256 or AVX512 instructions. When 2 source registers are identical, AVX256 and AVX512 andn and xor instructions: VOP %reg, %reg, %dest_reg can be encoded with VOP128 %reg, %reg, %dest_reg This optimization is enabled with -O2 and -Os. 4. 16-bit, 32-bit and 64-bit register tests with immediate may be encoded as 8-bit register test with immediate. This optimization is enabled with -Os. This patch does: 1. Add {nooptimize} pseudo prefix to disable instruction size optimization. 2. Add optimize to i386_opcode_modifier to tell assembler that encoding of an instruction may be optimized. gas/ PR gas/22871 * NEWS: Mention -O[2|s]. * config/tc-i386.c (_i386_insn): Add no_optimize. (optimize): New. (optimize_for_space): Likewise. (fits_in_imm7): New function. (fits_in_imm31): Likewise. (optimize_encoding): Likewise. (md_assemble): Call optimize_encoding to optimize encoding. (parse_insn): Handle {nooptimize}. (md_shortopts): Append "O::". (md_parse_option): Handle -On. * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well as {nooptimize}. * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler. * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2, optimize-3, x86-64-optimize-1, x86-64-optimize-2, x86-64-optimize-3 and x86-64-optimize-4. * testsuite/gas/i386/optimize-1.d: New file. * testsuite/gas/i386/optimize-1.s: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. opcodes/ PR gas/22871 * i386-gen.c (opcode_modifiers): Add Optimize. * i386-opc.h (Optimize): New enum. (i386_opcode_modifier): Add optimize. * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, vpxord and vpxorq. * i386-tbl.h: Regenerated.
2018-02-27 16:36:33 +01:00
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
Add a new Portuguese translation for the binutils sub-directory, and update the Russian translation for the gas sub-directory. gas * po/ru.po: Updated Russian translation. binutils* po/pt.po: New Portuguese translation. * configure.ac (ALL_LINGUAS): Add pt. * configure: Regenerate.
2018-02-27 13:27:30 +01:00
2018-02-27 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
GAS/doc: Clean up `.dc' and `.ds' directive descriptions gas/ * doc/as.texinfo (Pseudo Ops): Clean up `.dc' and `.ds' descriptions.
2018-02-26 17:11:03 +01:00
2018-02-26 Maciej W. Rozycki <macro@mips.com>
* doc/as.texinfo (Pseudo Ops): Clean up `.dc' and `.ds'
descriptions.
Fix typo in documentation of assembler's .dc directive. * doc/as.texinfo (Dc): Fix typo.
2018-02-26 12:28:23 +01:00
2018-02-26 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Dc): Fix typo.
MIPS messages More standardization of messages. bfd/ * elfxx-mips.c: Standardize error/warning messages. binutils/ * testsuite/binutils-all/mips/mips-reginfo-n32.d, * testsuite/binutils-all/mips/mips-reginfo.d: Update. gas/ * testsuite/gas/mips/reginfo-2.l: Update. ld/ * testsuite/ld-mips-elf/attr-gnu-4-12.d, * testsuite/ld-mips-elf/attr-gnu-4-13.d, * testsuite/ld-mips-elf/attr-gnu-4-14.d, * testsuite/ld-mips-elf/attr-gnu-4-16.d, * testsuite/ld-mips-elf/attr-gnu-4-17.d, * testsuite/ld-mips-elf/attr-gnu-4-18.d, * testsuite/ld-mips-elf/attr-gnu-4-19.d, * testsuite/ld-mips-elf/attr-gnu-4-21.d, * testsuite/ld-mips-elf/attr-gnu-4-23.d, * testsuite/ld-mips-elf/attr-gnu-4-24.d, * testsuite/ld-mips-elf/attr-gnu-4-25.d, * testsuite/ld-mips-elf/attr-gnu-4-26.d, * testsuite/ld-mips-elf/attr-gnu-4-27.d, * testsuite/ld-mips-elf/attr-gnu-4-28.d, * testsuite/ld-mips-elf/attr-gnu-4-29.d, * testsuite/ld-mips-elf/attr-gnu-4-31.d, * testsuite/ld-mips-elf/attr-gnu-4-32.d, * testsuite/ld-mips-elf/attr-gnu-4-34.d, * testsuite/ld-mips-elf/attr-gnu-4-35.d, * testsuite/ld-mips-elf/attr-gnu-4-36.d, * testsuite/ld-mips-elf/attr-gnu-4-37.d, * testsuite/ld-mips-elf/attr-gnu-4-38.d, * testsuite/ld-mips-elf/attr-gnu-4-39.d, * testsuite/ld-mips-elf/attr-gnu-4-41.d, * testsuite/ld-mips-elf/attr-gnu-4-42.d, * testsuite/ld-mips-elf/attr-gnu-4-43.d, * testsuite/ld-mips-elf/attr-gnu-4-45.d, * testsuite/ld-mips-elf/attr-gnu-4-46.d, * testsuite/ld-mips-elf/attr-gnu-4-47.d, * testsuite/ld-mips-elf/attr-gnu-4-48.d, * testsuite/ld-mips-elf/attr-gnu-4-49.d, * testsuite/ld-mips-elf/attr-gnu-4-52.d, * testsuite/ld-mips-elf/attr-gnu-4-53.d, * testsuite/ld-mips-elf/attr-gnu-4-54.d, * testsuite/ld-mips-elf/attr-gnu-4-58.d, * testsuite/ld-mips-elf/attr-gnu-4-59.d, * testsuite/ld-mips-elf/attr-gnu-4-61.d, * testsuite/ld-mips-elf/attr-gnu-4-62.d, * testsuite/ld-mips-elf/attr-gnu-4-63.d, * testsuite/ld-mips-elf/attr-gnu-4-64.d, * testsuite/ld-mips-elf/attr-gnu-4-68.d, * testsuite/ld-mips-elf/attr-gnu-4-69.d, * testsuite/ld-mips-elf/attr-gnu-4-71.d, * testsuite/ld-mips-elf/attr-gnu-4-72.d, * testsuite/ld-mips-elf/attr-gnu-4-73.d, * testsuite/ld-mips-elf/attr-gnu-4-74.d, * testsuite/ld-mips-elf/attr-gnu-4-78.d, * testsuite/ld-mips-elf/attr-gnu-4-79.d, * testsuite/ld-mips-elf/attr-gnu-4-81.d, * testsuite/ld-mips-elf/attr-gnu-4-89.d, * testsuite/ld-mips-elf/attr-gnu-8-12.d, * testsuite/ld-mips-elf/attr-gnu-8-21.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d, * testsuite/ld-mips-elf/bal-jalx-pic-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic.d, * testsuite/ld-mips-elf/mode-change-error-1.d, * testsuite/ld-mips-elf/unaligned-branch-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-r6-2.d, * testsuite/ld-mips-elf/unaligned-branch.d, * testsuite/ld-mips-elf/unaligned-jalx-1.d, * testsuite/ld-mips-elf/unaligned-jalx-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jump-micromips.d, * testsuite/ld-mips-elf/unaligned-jump-mips16.d, * testsuite/ld-mips-elf/unaligned-jump.d: Update.
2018-02-20 11:32:16 +01:00
2018-02-26 Alan Modra <amodra@gmail.com>
BFD messages bfd/ * archive.c, * bfd.c, * linker.c, * reloc.c, * stabs.c, * syms.c: Standardize error/warning messages. binutils/ * testsuite/binutils-all/mips/mips-reginfo-n32.d, * testsuite/binutils-all/mips/mips-reginfo.d: Update. gas/ * testsuite/gas/mips/reginfo-2.l: Update. ld/ * testsuite/ld-arm/cmse-implib-errors.out, * testsuite/ld-arm/cmse-new-earlier-later-implib.out, * testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out, * testsuite/ld-arm/cmse-new-wrong-implib.out, * testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out, * testsuite/ld-arm/cmse-veneers-wrong-entryfct.out, * testsuite/ld-cris/badgotr1.d, * testsuite/ld-cris/tls-err-24.d, * testsuite/ld-cris/tls-err-25.d, * testsuite/ld-cris/tls-err-26.d, * testsuite/ld-cris/tls-err-27.d, * testsuite/ld-cris/tls-err-28.d, * testsuite/ld-cris/tls-err-40.d, * testsuite/ld-cris/tls-err-44.d, * testsuite/ld-cris/tls-err-48.d, * testsuite/ld-cris/tls-err-52.d, * testsuite/ld-cris/tls-err-53.d, * testsuite/ld-cris/tls-err-55.d, * testsuite/ld-cris/tls-err-56.d, * testsuite/ld-cris/tls-err-62.d, * testsuite/ld-cris/tls-err-65.d, * testsuite/ld-cris/tls-err-77.d, * testsuite/ld-elf/empty-implib.out, * testsuite/ld-elf/indirect.exp: Update.
2018-02-21 03:39:29 +01:00
* testsuite/gas/mips/reginfo-2.l: Update.
2018-02-23 Alan Modra <amodra@gmail.com>
MIPS messages More standardization of messages. bfd/ * elfxx-mips.c: Standardize error/warning messages. binutils/ * testsuite/binutils-all/mips/mips-reginfo-n32.d, * testsuite/binutils-all/mips/mips-reginfo.d: Update. gas/ * testsuite/gas/mips/reginfo-2.l: Update. ld/ * testsuite/ld-mips-elf/attr-gnu-4-12.d, * testsuite/ld-mips-elf/attr-gnu-4-13.d, * testsuite/ld-mips-elf/attr-gnu-4-14.d, * testsuite/ld-mips-elf/attr-gnu-4-16.d, * testsuite/ld-mips-elf/attr-gnu-4-17.d, * testsuite/ld-mips-elf/attr-gnu-4-18.d, * testsuite/ld-mips-elf/attr-gnu-4-19.d, * testsuite/ld-mips-elf/attr-gnu-4-21.d, * testsuite/ld-mips-elf/attr-gnu-4-23.d, * testsuite/ld-mips-elf/attr-gnu-4-24.d, * testsuite/ld-mips-elf/attr-gnu-4-25.d, * testsuite/ld-mips-elf/attr-gnu-4-26.d, * testsuite/ld-mips-elf/attr-gnu-4-27.d, * testsuite/ld-mips-elf/attr-gnu-4-28.d, * testsuite/ld-mips-elf/attr-gnu-4-29.d, * testsuite/ld-mips-elf/attr-gnu-4-31.d, * testsuite/ld-mips-elf/attr-gnu-4-32.d, * testsuite/ld-mips-elf/attr-gnu-4-34.d, * testsuite/ld-mips-elf/attr-gnu-4-35.d, * testsuite/ld-mips-elf/attr-gnu-4-36.d, * testsuite/ld-mips-elf/attr-gnu-4-37.d, * testsuite/ld-mips-elf/attr-gnu-4-38.d, * testsuite/ld-mips-elf/attr-gnu-4-39.d, * testsuite/ld-mips-elf/attr-gnu-4-41.d, * testsuite/ld-mips-elf/attr-gnu-4-42.d, * testsuite/ld-mips-elf/attr-gnu-4-43.d, * testsuite/ld-mips-elf/attr-gnu-4-45.d, * testsuite/ld-mips-elf/attr-gnu-4-46.d, * testsuite/ld-mips-elf/attr-gnu-4-47.d, * testsuite/ld-mips-elf/attr-gnu-4-48.d, * testsuite/ld-mips-elf/attr-gnu-4-49.d, * testsuite/ld-mips-elf/attr-gnu-4-52.d, * testsuite/ld-mips-elf/attr-gnu-4-53.d, * testsuite/ld-mips-elf/attr-gnu-4-54.d, * testsuite/ld-mips-elf/attr-gnu-4-58.d, * testsuite/ld-mips-elf/attr-gnu-4-59.d, * testsuite/ld-mips-elf/attr-gnu-4-61.d, * testsuite/ld-mips-elf/attr-gnu-4-62.d, * testsuite/ld-mips-elf/attr-gnu-4-63.d, * testsuite/ld-mips-elf/attr-gnu-4-64.d, * testsuite/ld-mips-elf/attr-gnu-4-68.d, * testsuite/ld-mips-elf/attr-gnu-4-69.d, * testsuite/ld-mips-elf/attr-gnu-4-71.d, * testsuite/ld-mips-elf/attr-gnu-4-72.d, * testsuite/ld-mips-elf/attr-gnu-4-73.d, * testsuite/ld-mips-elf/attr-gnu-4-74.d, * testsuite/ld-mips-elf/attr-gnu-4-78.d, * testsuite/ld-mips-elf/attr-gnu-4-79.d, * testsuite/ld-mips-elf/attr-gnu-4-81.d, * testsuite/ld-mips-elf/attr-gnu-4-89.d, * testsuite/ld-mips-elf/attr-gnu-8-12.d, * testsuite/ld-mips-elf/attr-gnu-8-21.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d, * testsuite/ld-mips-elf/bal-jalx-pic-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic.d, * testsuite/ld-mips-elf/mode-change-error-1.d, * testsuite/ld-mips-elf/unaligned-branch-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-r6-2.d, * testsuite/ld-mips-elf/unaligned-branch.d, * testsuite/ld-mips-elf/unaligned-jalx-1.d, * testsuite/ld-mips-elf/unaligned-jalx-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jump-micromips.d, * testsuite/ld-mips-elf/unaligned-jump-mips16.d, * testsuite/ld-mips-elf/unaligned-jump.d: Update.
2018-02-20 11:32:16 +01:00
* testsuite/gas/mips/reginfo-2.l: Update.
Document the assembler's .dc, .dcb and .ds directives. * doc/as.texinfo (Pseudo Ops): Add nodes for .dc, .dcb and .ds.
2018-02-23 11:43:53 +01:00
2018-02-23 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Pseudo Ops): Add nodes for .dc, .dcb and .ds.
nds32: Support target directive .ict_model.
2018-02-23 07:25:25 +01:00
2018-02-23 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-nds32.c (ict_model): New function. Hook new
directive .ict_model.
(nds32_insert_relax_entry): Tag the bits of entry relocation
for .ict_model.
x86: Add {rex} pseudo prefix Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Note that this differs from the rex prefix which generates REX prefix unconditionally. gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated. opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated.
2018-02-22 15:18:27 +01:00
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
Fix memory access violation when attempting to shorten a suffixed micromips instruction during lookup. PR 22014 * config/tc-mips.c (mips_lookup_insn): Use memmove to strip the instruction size suffix.
2018-02-22 13:49:49 +01:00
2018-02-22 A. Wilcox <awilfox@adelielinux.org>
PR 22014
* config/tc-mips.c (mips_lookup_insn): Use memmove to strip the
instruction size suffix.
MIPS16/GAS/testsuite: Add cross-section R_MIPS16_PC16_S1 relocation tests Add a pair of MIPS16 branch tests to verify correct R_MIPS16_PC16_S1 relocation generation for cross-section references in a single source. This complements commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support"). gas/ * testsuite/gas/mips/mips16-branch-reloc-4.d: New test. * testsuite/gas/mips/mips16-branch-reloc-5.d: New test. * testsuite/gas/mips/mips16-branch-reloc-4.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-5.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-02-20 21:51:37 +01:00
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/mips16-branch-reloc-4.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-5.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas: xtensa: limit size of auto litpools Literal movement code may grow auto litpool so big that it won't be possible to jump around it. Limit the size of auto litpools by 1/2 of the jump range. gas/ 2018-02-20 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (struct litpool_frag): Add new field literal_count. (MAX_AUTO_POOL_LITERALS, MAX_EXPLICIT_POOL_LITERALS) (MAX_POOL_LITERALS): New macro definitions. (auto_litpool_limit): Initialize to 0. (md_parse_option): Set auto_litpool_limit in the presence of --auto-litpools option. (xtensa_maybe_create_literal_pool_frag): Zero-initialize literal_count field. (xg_find_litpool): New function. Make sure that found literal pool size is within the limit. (xtensa_move_literals): Extract literal pool search code into the new function. * testsuite/gas/xtensa/all.exp: Add auto-litpools-2 test. * testsuite/gas/xtensa/auto-litpools-2.d: New file. * testsuite/gas/xtensa/auto-litpools-2.s: New file. * testsuite/gas/xtensa/auto-litpools.d: Fix up changed addresses. * testsuite/gas/xtensa/auto-litpools.s: Change literal value so that objdump doesn't get out of sync.
2018-02-08 19:28:52 +01:00
2018-02-20 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (struct litpool_frag): Add new field
literal_count.
(MAX_AUTO_POOL_LITERALS, MAX_EXPLICIT_POOL_LITERALS)
(MAX_POOL_LITERALS): New macro definitions.
(auto_litpool_limit): Initialize to 0.
(md_parse_option): Set auto_litpool_limit in the presence of
--auto-litpools option.
(xtensa_maybe_create_literal_pool_frag): Zero-initialize
literal_count field.
(xg_find_litpool): New function. Make sure that found literal
pool size is within the limit.
(xtensa_move_literals): Extract literal pool search code into
the new function.
* testsuite/gas/xtensa/all.exp: Add auto-litpools-2 test.
* testsuite/gas/xtensa/auto-litpools-2.d: New file.
* testsuite/gas/xtensa/auto-litpools-2.s: New file.
* testsuite/gas/xtensa/auto-litpools.d: Fix up changed
addresses.
* testsuite/gas/xtensa/auto-litpools.s: Change literal value so
that objdump doesn't get out of sync.
Clarify .arch_extension possible values Documentation for .arch_extension says it accepts the same architectural extensions as those accepted by -mcpu. Given the name and the fact that -march for obvious reason also accept the same extensions, I believe it's worth mentioning that it accepts the same extensions as both -march and -mcpu. This commit addresses that. 2018-02-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * doc/c-arm.texi (.arch_extension): Mention extensions it accepts are also the same as -march.
2018-02-20 13:48:50 +01:00
2018-02-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
* doc/c-arm.texi (.arch_extension): Mention extensions it accepts are
also the same as -march.
Add .nop assembler directive Implement the '.nop SIZE[, CONTROL]' assembler directive, which emits SIZE bytes filled with no-op instructions. SIZE is absolute expression. The optional CONTROL byte controls how no-op instructions should be generated. If the comma and @var{control} are omitted, CONTROL is assumed to be zero. For Intel 80386 and AMD x86-64 targets, CONTROL byte specifies the size limit of a single no-op instruction. The valid values of CONTROL byte are between 0 and 8 for 16-bit mode, between 0 and 10 for 32-bit mode, between 0 and 11 for 64-bit mode. When 0 is used, the no-op size limit is set to the maximum supported size. 2 new relax states, rs_space_nop and rs_fill_nop, are added to enum _relax_state, which are similar to rs_space and rs_fill, respectively, but they fill with no-op instructions, instead of a single byte. A target backend must override the default md_generate_nops to generate proper no-op instructions. Otherwise, an error of unimplemented .nop directive will be issued whenever .nop directive is used. * NEWS: Mention .nop directive. * as.h (_relax_state): Add rs_space_nop and rs_fill_nop. * read.c (potable): Add .nop. (s_nop): New function. * read.h (s_nop): New prototype. * write.c (cvt_frag_to_fill): Handle rs_space_nop and rs_fill_nop. (md_generate_nops): New function. (relax_segment): Likewise. (write_contents): Use md_generate_nops for rs_fill_nop. * config/tc-i386.c (alt64_11): New. (alt64_patt): Likewise. (md_convert_frag): Handle rs_space_nop. (i386_output_nops): New function. (i386_generate_nops): Likewise. (i386_align_code): Call i386_output_nops. * config/tc-i386.h (i386_generate_nops): New. (md_generate_nops): Likewise. * doc/as.texinfo: Document .nop directive. * testsuite/gas/i386/i386.exp: Run .nop directive tests. * testsuite/gas/i386/nop-1.d: New file. * testsuite/gas/i386/nop-1.s: Likewise. * testsuite/gas/i386/nop-2.d: Likewise. * testsuite/gas/i386/nop-2.s: Likewise. * testsuite/gas/i386/nop-3.d: Likewise. * testsuite/gas/i386/nop-3.s: Likewise. * testsuite/gas/i386/nop-4.d: Likewise. * testsuite/gas/i386/nop-4.s: Likewise. * testsuite/gas/i386/nop-5.d: Likewise. * testsuite/gas/i386/nop-5.s: Likewise. * testsuite/gas/i386/nop-6.d: Likewise. * testsuite/gas/i386/nop-6.s: Likewise. * testsuite/gas/i386/nop-bad-1.l: Likewise. * testsuite/gas/i386/nop-bad-1.s: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-nop-2.d: Likewise. * testsuite/gas/i386/x86-64-nop-3.d: Likewise. * testsuite/gas/i386/x86-64-nop-4.d: Likewise. * testsuite/gas/i386/x86-64-nop-5.d: Likewise. * testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-17 14:20:42 +01:00
2018-02-17 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention .nop directive.
* as.h (_relax_state): Add rs_space_nop and rs_fill_nop.
* read.c (potable): Add .nop.
(s_nop): New function.
* read.h (s_nop): New prototype.
* write.c (cvt_frag_to_fill): Handle rs_space_nop and
rs_fill_nop.
(md_generate_nops): New function.
(relax_segment): Likewise.
(write_contents): Use md_generate_nops for rs_fill_nop.
* config/tc-i386.c (alt64_11): New.
(alt64_patt): Likewise.
(md_convert_frag): Handle rs_space_nop.
(i386_output_nops): New function.
(i386_generate_nops): Likewise.
(i386_align_code): Call i386_output_nops.
* config/tc-i386.h (i386_generate_nops): New.
(md_generate_nops): Likewise.
* doc/as.texinfo: Document .nop directive.
* testsuite/gas/i386/i386.exp: Run .nop directive tests.
* testsuite/gas/i386/nop-1.d: New file.
* testsuite/gas/i386/nop-1.s: Likewise.
* testsuite/gas/i386/nop-2.d: Likewise.
* testsuite/gas/i386/nop-2.s: Likewise.
* testsuite/gas/i386/nop-3.d: Likewise.
* testsuite/gas/i386/nop-3.s: Likewise.
* testsuite/gas/i386/nop-4.d: Likewise.
* testsuite/gas/i386/nop-4.s: Likewise.
* testsuite/gas/i386/nop-5.d: Likewise.
* testsuite/gas/i386/nop-5.s: Likewise.
* testsuite/gas/i386/nop-6.d: Likewise.
* testsuite/gas/i386/nop-6.s: Likewise.
* testsuite/gas/i386/nop-bad-1.l: Likewise.
* testsuite/gas/i386/nop-bad-1.s: Likewise.
* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* testsuite/gas/i386/x86-64-nop-2.d: Likewise.
* testsuite/gas/i386/x86-64-nop-3.d: Likewise.
* testsuite/gas/i386/x86-64-nop-4.d: Likewise.
* testsuite/gas/i386/x86-64-nop-5.d: Likewise.
* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
Fix AArch32 build attributes for Armv8.4-A. The build attribute number for Armv8.4-A is currently incorrectly set to that of Armv8-M. This patch fixes that by setting it as part of the Armv8-A family and adds a test for it. gas/ 2018-02-15 Tamar Christina <tamar.christina@arm.com> * config/tc-arm.c (cpu_arch_ver): Renumber ARM_ARCH_V8_4A. * testsuite/gas/arm/attr-march-armv8_4-a.d: New.
2018-02-15 18:08:14 +01:00
2018-02-15 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (cpu_arch_ver): Renumber ARM_ARCH_V8_4A.
* testsuite/gas/arm/attr-march-armv8_4-a.d: New.
gas: xtensa: fix trampoline placement For jumps requiring multiple trampolines trampoline placement code may place multiple sequential trampolines into the same frag. Don't do that. gas/ 2018-02-13 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline frag that contains source address.
2018-02-11 06:59:54 +01:00
2018-02-13 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline
frag that contains source address.
Fix ARm assembler so that it rejects invalid immediate values for the Thumb ORR instruction. PR 22773 * config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR instruction before assuming that it is a MOV instruction. * testsuite/gas/arm/pr22773.s: New test. * testsuite/gas/arm/pr22773.d: New test driver. * testsuite/gas/arm/pr22773.l: New expected output.
2018-02-13 17:50:04 +01:00
2018-02-13 Nick Clifton <nickc@redhat.com>
PR 22773
* config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR
instruction before assuming that it is a MOV instruction.
* testsuite/gas/arm/pr22773.s: New test.
* testsuite/gas/arm/pr22773.d: New test driver.
* testsuite/gas/arm/pr22773.l: New expected output.
x86-64: Generate branch with PLT32 relocation Since there is no need to prepare for PLT branch on x86-64, generate R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be used as a marker for 32-bit PC-relative branches. To compile Linux kernel, this patch: From: "H.J. Lu" <hjl.tools@gmail.com> Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32 On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared objects must use PIC PLT. To use PIC PLT, you need to load _GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on x86-64 since x86-64 uses PC-relative PLT. On x86-64, for 32-bit PC-relative branches, we can generate PLT32 relocation, instead of PC32 relocation, which can also be used as a marker for 32-bit PC-relative branches. Linker can always reduce PLT32 relocation to PC32 if function is defined locally. Local functions should use PC32 relocation. As far as Linux kernel is concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32 since Linux kernel doesn't use PLT. is needed. It is available on hjl/plt32/master branch at https://github.com/hjl-tools/linux bfd/ PR gas/22791 * elf64-x86-64.c (is_32bit_relative_branch): Removed. (elf_x86_64_relocate_section): Check PIC relocations in PIE. Remove is_32bit_relative_branch usage. Disallow PC32 reloc against protected function in shared object. gas/ PR gas/22791 * config/tc-i386.c (need_plt32_p): New function. (output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible. (md_estimate_size_before_relax): Likewise. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/x86-64-jump.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-3.d: Likewise. * testsuite/gas/i386/ilp32/reloc64.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. ld/ PR gas/22791 * testsuite/ld-x86-64/mpx1c.rd: Updated. * testsuite/ld-x86-64/pr22791-1.err: New file. * testsuite/ld-x86-64/pr22791-1a.c: Likewise. * testsuite/ld-x86-64/pr22791-1b.s: Likewise. * testsuite/ld-x86-64/pr22791-2.rd: Likewise. * testsuite/ld-x86-64/pr22791-2a.s: Likewise. * testsuite/ld-x86-64/pr22791-2b.c: Likewise. * testsuite/ld-x86-64/pr22791-2c.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
2018-02-13 16:34:22 +01:00
2018-02-13 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22791
* config/tc-i386.c (need_plt32_p): New function.
(output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible.
(md_estimate_size_before_relax): Likewise.
* testsuite/gas/i386/reloc64.d: Updated.
* testsuite/gas/i386/x86-64-jump.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-3.d: Likewise.
* testsuite/gas/i386/ilp32/reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
MIPS/GAS/testsuite: Correct duplicate `Loongson-3A tests' test name Correct a duplicate `Loongson-3A tests' GAS test name introduced with commit 986754024085 ("Add Loongson3A specific instructions"), <https://sourceware.org/ml/binutils/2010-12/msg00447.html>, shared between gas/testsuite/gas/mips/loongson-3a.d and gas/testsuite/gas/mips/loongson-3a-2.d. gas/ * testsuite/gas/mips/loongson-3a-2.d: Rename test.
2018-02-13 13:56:29 +01:00
2018-02-13 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/loongson-3a-2.d: Rename test.
Fix compile time warning messages from gcc version 8 about cast between incompatible function types. PR 22823 bfd Fix compile time warnings generated by gcc version 8. * libbfd-in.h: Remove extraneous text from prototypes. Add prototypes for bfd_false_any, bfd_true_any, bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any, bfd_n1_any, bfd_void_any. (_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy function. (_bfd_generic_bfd_merge_private_bfd_data): Likewise. (_bfd_generic_bfd_set_private_flags): Likewise. (_bfd_generic_bfd_copy_private_section_data): Likewise. (_bfd_generic_bfd_copy_private_symbol_data): Likewise. (_bfd_generic_bfd_copy_private_header_data): Likewise. (_bfd_generic_bfd_print_private_bfd_data): Likewise. (_bfd_noarchive_construct_extended_name_table): Likewise. (_bfd_noarchive_truncate_arname): Likewise. (_bfd_noarchive_write_ar_hdr): Likewise. (_bfd_noarchive_get_elt_at_index): Likewise. (_bfd_nosymbols_canonicalize_symtab): Likewise. (_bfd_nosymbols_print_symbol): Likewise. (_bfd_nosymbols_get_symbol_info): Likewise. (_bfd_nosymbols_get_symbol_version_string): Likewise. (_bfd_nosymbols_bfd_is_local_label_name): Likewise. (_bfd_nosymbols_bfd_is_target_special_symbol): Likewise. (_bfd_nosymbols_get_lineno): Likewise. (_bfd_nosymbols_find_nearest_line): Likewise. (_bfd_nosymbols_find_line): Likewise. (_bfd_nosymbols_find_inliner_info): Likewise. (_bfd_nosymbols_bfd_make_debug_symbol): Likewise. (_bfd_nosymbols_read_minisymbols): Likewise. (_bfd_nosymbols_minisymbol_to_symbol): Likewise. (_bfd_norelocs_bfd_reloc_type_lookup): Likewise. (_bfd_norelocs_bfd_reloc_name_lookup): Likewise. (_bfd_nowrite_set_arch_mach): Likewise. (_bfd_nowrite_set_section_contents): Likewise. (_bfd_nolink_sizeof_headers): Likewise. (_bfd_nolink_bfd_get_relocated_section_contents): Likewise. (_bfd_nolink_bfd_relax_section): Likewise. (_bfd_nolink_bfd_gc_sections): Likewise. (_bfd_nolink_bfd_lookup_section_flags): Likewise. (_bfd_nolink_bfd_merge_sections): Likewise. (_bfd_nolink_bfd_is_group_section): Likewise. (_bfd_nolink_bfd_discard_group): Likewise. (_bfd_nolink_bfd_link_hash_table_create): Likewise. (_bfd_nolink_bfd_link_add_symbols): Likewise. (_bfd_nolink_bfd_link_just_syms): Likewise. (_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise. (_bfd_nolink_bfd_final_link): Likewise. (_bfd_nolink_bfd_link_split_section): Likewise. (_bfd_nolink_section_already_linked): Likewise. (_bfd_nolink_bfd_define_common_symbol): Likewise. (_bfd_nolink_bfd_define_start_stop): Likewise. (_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise. (_bfd_nodynamic_get_synthetic_symtab): Likewise. (_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise. (_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise. * libbfd.c (bfd_false_any): New function. Like bfd_false but accepts one or more arguments. (bfd_true_any): Likewise. (bfd_nullvoidptr_any): Likewise. (bfd_0_any): Likewise. (bfd_0u_any): Likewise. (bfd_0l_any): Likewise. (_bfd_n1_any): Likewise. (bfd_void_any): Likewise. * libbfd.h (extern): Regenerate * aout-target.h (MY_bfd_is_target_special_symbol): Use vararg based dummy function. * aout-tic30.c (tic30_aout_set_arch_mach): Likewise. * binary.c (binary_get_symbol_info): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Likewise. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coffcode.h (coff_set_alignment_hook): Likewise. (symname_in_debug_hook): Likewise. (bfd_coff_backend_data bigobj_swap_table): Likewise. * elf-m10300.c (elf_backend_omit_section_dynsym): Likewise. * elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise. * elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise. * elf32-metag.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score7.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise. * elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise. * elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise. * elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise. * elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise. * elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise. (bfd_elfNN_bfd_make_debug_symbol): Likewise. (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. (bfd_elfNN_bfd_set_private_flags): Likewise. (bfd_elfNN_bfd_is_target_special_symbol): Likewise. (elf_backend_init_index_section): Likewise. (elf_backend_allow_non_load_phdr): Likewise. * elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise. * i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise. * ieee.c (ieee_construct_extended_name_table): Likewise. (ieee_write_armap): Likewise. (ieee_write_ar_hdr): Likewise. (ieee_bfd_is_target_special_symbol): Likewise. * ihex.c (ihex_canonicalize_symtab): Likewise. (ihex_bfd_is_target_special_symbol): Likewise. * libaout.h (aout_32_bfd_is_target_special_symbol): Likewise. * libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise. (_bfd_ecoff_set_alignment_hook): Likewise. * mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise. * mmo.c (mmo_bfd_is_target_special_symbol): Likewise. * nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise. * oasys.c (oasys_construct_extended_name_table): Likewise. (oasys_write_armap): Likewise. (oasys_write_ar_hdr): Likewise. (oasys_bfd_is_target_special_symbol): Likewise. * pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise. * plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise. * ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise. * som.c (som_bfd_is_target_special_symbol): Likewise. * srec.c (srec_bfd_is_target_special_symbol): Likewise. * tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise. * verilog.c (verilog_bfd_is_target_special_symbol): Likewise. * versados.c (versados_bfd_is_target_special_symbol): Likewise. (versados_bfd_reloc_name_lookup): Likewise. * vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise. (vms_bfd_define_start_stop): Likewise. (alpha_vms_bfd_is_target_special_symbol): Likewise. * wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise. * xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise. * elf32-arc.c (get_replace_function): Assign replacement function to func pointer. * elf32-i370.c (i370_noop): Update prototype. gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant casts. (obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit. (obj_elf_vtable_inherit): New stub function that calls obj_elf_get_vtable_inherit. (obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry. (obj_elf_vtable_entry): New stub function that calls obj_elf_get_vtable_entry. * config/obj-elf.h (obj_elf_vtable_inherit): Update prototype. (obj_elf_vtable_entry) Likewise. (obj_elf_get_vtable_inherit) Likewise. (obj_elf_get_vtable_entry) Likewise. * config/tc-arm.c (md_pseudo_table): Remove now redundant cast. * config/tc-i386c (md_pseudo_table): Likewise. * config/tc-hppa.c (pa_vtable_entry): Call obj_elf_get_vtable_entry. (pa_vtable_inherit): Call obj_elf_get_vtable_inherit. * config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file with call to dwarf2_get_filename. * dwarf2dbg.c (dwarf2_directive_file): Rename to dwarf2_directive_filename. (dwarf2_directive_file): New stub function that calls dwarf2_directive_filename. * dwarf2dbg.h: Prototype dwarf2_directive_filename. opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning about truncation of printing.
2018-02-13 14:14:47 +01:00
2018-02-13 Nick Clifton <nickc@redhat.com>
PR 22823
* config/obj-elf.c (elf_pseudo_table): Remove now redundant
casts.
(obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit.
(obj_elf_vtable_inherit): New stub function that calls
obj_elf_get_vtable_inherit.
(obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry.
(obj_elf_vtable_entry): New stub function that calls
obj_elf_get_vtable_entry.
* config/obj-elf.h (obj_elf_vtable_inherit): Update prototype.
(obj_elf_vtable_entry) Likewise.
(obj_elf_get_vtable_inherit) Likewise.
(obj_elf_get_vtable_entry) Likewise.
* config/tc-arm.c (md_pseudo_table): Remove now redundant cast.
* config/tc-i386c (md_pseudo_table): Likewise.
* config/tc-hppa.c (pa_vtable_entry): Call
obj_elf_get_vtable_entry.
(pa_vtable_inherit): Call obj_elf_get_vtable_inherit.
* config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file
with call to dwarf2_get_filename.
* dwarf2dbg.c (dwarf2_directive_file): Rename to
dwarf2_directive_filename.
(dwarf2_directive_file): New stub function that calls
dwarf2_directive_filename.
* dwarf2dbg.h: Prototype dwarf2_directive_filename.
MIPS/GAS/test: Fix an n32 `.reginfo' size test failure Correct a commit 2d6dda71611b ("MIPS/BFD: Correctly report unsupported `.reginfo' section size") issue and avoid a GAS test failure: regexp_diff match failure regexp "^.*: Incorrect `\.reginfo' section size; expected 24, got 28$" line "../as-new: dump.o: Incorrect `.reginfo' section size; expected 24, got 32" FAIL: MIPS assembled .reginfo section size (n32) on MIPS targets other than bare-metal ones. The reason for this failure is section padding to alignment, done in `size_seg'. For n32 `.reginfo' the section alignment is set to 3, and therefore the section is padded to a multiple of 8, except for bare-metal targets, for which padding is unconditionally disabled in `md_section_align'. Use `--no-pad-sections' then to disable padding for all targets, so that the size of `.reginfo' is always the same, matching the message pattern. gas/ * testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to `as' flags.
2018-02-12 17:04:05 +01:00
2018-02-12 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to
`as' flags.
MIPS: Fix encoding for MIPSr6 sigrie instruction. The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12 15:50:42 +01:00
2018-02-12 Henry Wong <henry@stuffedcow.net>
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
Update Russian translation for the gas/ sub-directory.
2018-02-12 13:10:50 +01:00
2018-02-12 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
PR22819, powerpc gas "instruction address is not a multiple of 4" Checks for insn alignment were hopelessly confused when misaligned data starts a new frag. The real-world testcase happened to run out of frag space in the middle of emitting a trace-back table via something like: .byte 0 /* VERSION=0 */ .byte 9 /* LANG=C++ */ .byte 34 /* Bits on: has_tboff, fp_present */ .byte 64 /* Bits on: name_present */ .byte 128 /* Bits on: stores_bc, FP_SAVED=0 */ .byte 0 /* Bits on: GP_SAVED=0 */ .byte 2 /* FIXEDPARMS=2 */ .byte 1 /* FLOATPARMS=0, parmsonstk */ .long 0 .long 768 /* tb_offset: 0x300 */ .hword 45 /* Function name length: 45 */ .long 0x334e5a5f .long 0x31766f70 .long 0x65744932 .long 0x69746172 .long 0x7a5f6e6f .long 0x64504533 .long 0x5f534e50 .long 0x72463431 .long 0x61746361 .long 0x74535f6c .long 0x74637572 .byte 0x45 .byte 0 The trigger being those misaligned .long's output for the function name. A most horrible way to output a string, especially considering endian issues.. PR 22819 * config/tc-ppc.c (md_assemble): Rewrite insn alignment checking. (ppc_frag_check): Likewise. * testsuite/gas/ppc/misalign.d, * testsuite/gas/ppc/misalign.l, * testsuite/gas/ppc/misalign.s: New test. * testsuite/gas/ppc/misalign2.d, * testsuite/gas/ppc/misalign2.s: New test. * testsuite/gas/ppc/ppc.exp: Run them.
2018-02-08 00:48:59 +01:00
2018-02-08 Alan Modra <amodra@gmail.com>
PR 22819
* config/tc-ppc.c (md_assemble): Rewrite insn alignment checking.
(ppc_frag_check): Likewise.
* testsuite/gas/ppc/misalign.d,
* testsuite/gas/ppc/misalign.l,
* testsuite/gas/ppc/misalign.s: New test.
* testsuite/gas/ppc/misalign2.d,
* testsuite/gas/ppc/misalign2.s: New test.
* testsuite/gas/ppc/ppc.exp: Run them.
RISC-V/GAS: Correct an `expr' global shadowing error for pre-4.8 GCC Correct a commit f0531ed6a429 ("Compress loads/stores with implicit 0 offset.") regression and remove a `-Wshadow' compilation error: cc1: warnings being treated as errors .../gas/config/tc-riscv.c: In function 'riscv_handle_implicit_zero_offset': .../gas/config/tc-riscv.c:1194: error: declaration of 'expr' shadows a global declaration .../gas/expr.h:180: error: shadowed declaration is here make[4]: *** [tc-riscv.o] Error 1 which for versions of GCC before 4.8 prevents GAS for RISC-V targets from being built. See also GCC PR c/53066. gas/ * config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename `expr' parameter to `ep'.
2018-02-05 15:05:51 +01:00
2018-02-05 Maciej W. Rozycki <macro@mips.com>
* config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename
`expr' parameter to `ep'.
MIPS/BFD: Correctly report unsupported `.reginfo' section size Report an error when an unsupported `.reginfo' section size is found in `_bfd_mips_elf_section_processing', removing an assertion that triggers at elfxx-mips.c:7105 in GAS when assembling input like: .section .reginfo .word 0xdeadbeef and in `objcopy --rename-section' when renaming an incorrectly sized section to `.reginfo'. bfd/ * elfxx-mips.c (_bfd_mips_elf_section_processing): For SHT_MIPS_REGINFO sections don't assert the correct size and report an error instead. binutils/ * testsuite/binutils-all/mips/mips-reginfo.d: New test. * testsuite/binutils-all/mips/mips-reginfo-n32.d: New test. * testsuite/binutils-all/mips/mips-reginfo.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/reginfo-2.d: New test. * testsuite/gas/mips/reginfo-2-n32.d: New test. * testsuite/gas/mips/reginfo-2.l: New test stderr output. * testsuite/gas/mips/reginfo-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-02-05 15:00:21 +01:00
2018-02-05 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/reginfo-2.d: New test.
* testsuite/gas/mips/reginfo-2-n32.d: New test.
* testsuite/gas/mips/reginfo-2.l: New test stderr output.
* testsuite/gas/mips/reginfo-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Updated Brazillian portuguese and Russian translation
2018-02-05 14:09:15 +01:00
2018-02-05 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
PR22714, Assembler preprocessor loses track of \@ The PR22714 testcase is such that the input buffer processed by do_scrub_chars ends on this line 1: bug "Returning to usermode but unexpected PSR bits set?", \@ right at the backslash. (The line is part of a macro definition.) The next input buffer then starts with '@' which starts a comment on ARM, and the check for \@ fails due to to == tostart. Now it would be possible to simply access to[-1] in this particular case, but that's ugly, and to be absolutely safe from people deliberately trying to crash gas we'd need the read.c:read_a_source_file buffer passed to do_scrub_chars to have a single byte pad at the start. PR 22714 * app.c (last_char): New static var. (struct app_save): Add last_char field. (app_push, app_pop): Handle it. (do_scrub_chars): Use last_char in test for "\@". Set last_char.
2018-01-31 04:04:18 +01:00
2018-01-31 Alan Modra <amodra@gmail.com>
PR 22714
* app.c (last_char): New static var.
(struct app_save): Add last_char field.
(app_push, app_pop): Handle it.
(do_scrub_chars): Use last_char in test for "\@". Set last_char.
Fix PR gas/22738 (.dc.a directive has wrong size on SPARC 64-bit). The .dc.a directive has wrong size (32 bits) on SPARC 64-bit because the assembler sets the correct BFD architecture only at the very end of the processing and it's too late for the directive. It's fixed by defining TARGET_MACH and making it return a sensible default value. gas/ * config/tc-sparc.h (sparc_mach): Declare. (TARGET_MACH): Define to above. * config/tc-sparc.c (sparc_mach): New function. (sparc_md_end): Minor tweak. ld/ * testsuite/ld-elf/pr22450.d: Remove reference to SPARC64.
2018-01-30 00:13:51 +01:00
2018-01-29 Eric Botcazou <ebotcazou@adacore.com>
PR gas/22738
* config/tc-sparc.h (sparc_mach): Declare.
(TARGET_MACH): Define to above.
* config/tc-sparc.c (sparc_mach): New function.
(sparc_md_end): Minor tweak.
Update Russian translation for the gas sub-directory
2018-01-29 14:51:47 +01:00
2018-01-29 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
MIPS/GAS: Correct `mips-*-windiss' target emulation configuration Fix a commit 0a44bf6950b3 ("mips-vxworks support"), <https://sourceware.org/ml/binutils/2006-03/msg00179.html>, regression and override the choice of the `vxworks' target environment introduced with commit ea3eed15006f ("Add generic vxworks GAS target."), <https://sourceware.org/ml/binutils/2005-01/msg00052.html>, for `mips-*-windiss' targets as they have not been converted to the VxWorks target format introduced with the former commit, removing a GAS target format selection failure: Assembler messages: Fatal error: selected target format 'elf32-bigmips-vxworks' unknown on any assembly attempt with `mips-windiss' and equivalent target configurations. gas/ * configure.tgt: Use generic emulation for `mips-*-windiss', overriding the blanket choice made for `*-*-windiss'.
2018-01-27 00:05:05 +01:00
2018-01-26 Maciej W. Rozycki <macro@mips.com>
* configure.tgt: Use generic emulation for `mips-*-windiss',
overriding the blanket choice made for `*-*-windiss'.
MIPS/GAS: Correct `mips-*-sysv4*' target emulation configuration Use `mips-*-sysv4*' rather than `mips-*-sysv4*MP*' to match the system type for System V Release 4 MIPS targets, removing a GAS target selection failure: Assembler messages: Fatal error: selected target format 'elf32-bigmips' unknown on any assembly attempt with `mips-sysv4' and equivalent target configurations. These would typically be called `mips-sni-sysv4' (Sinix) vs `mips-dde-sysv4.2MP' (Supermax). This corrects commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, making GAS target selection match commit dd745cfae548 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, and commit 3548145dcbf6 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which added support for these targets to BFD and LD respectively. gas/ * configure.tgt: Use `mips-*-sysv4*' rather than `mips-*-sysv4*MP*'.
2018-01-27 00:05:05 +01:00
2018-01-26 Maciej W. Rozycki <macro@mips.com>
* configure.tgt: Use `mips-*-sysv4*' rather than
`mips-*-sysv4*MP*'.
[GAS][AARCH64]Add group relocations to create PC-relative offset. This is a patch to add the gas support for group relocations to create a 16, 32, 48, or 64 bit PC-relative offset inline. The following relocations are added along with the test cases: BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. bfd/ 2018-01-24 Renlin Li <renlin.li@arm.com> * reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. gas/ 2018-01-24 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. (process_movw_reloc_info): Supports newly added MOVW_PREL relocations. (md_apply_fix): Likewise * testsuite/gas/aarch64/prel_g0.s: New. * testsuite/gas/aarch64/prel_g0.d: New. * testsuite/gas/aarch64/prel_g0_nc.s: New. * testsuite/gas/aarch64/prel_g0_nc.d: New. * testsuite/gas/aarch64/prel_g1.s: New. * testsuite/gas/aarch64/prel_g1.d: New. * testsuite/gas/aarch64/prel_g1_nc.s: New. * testsuite/gas/aarch64/prel_g1_nc.d: New. * testsuite/gas/aarch64/prel_g2.s: New. * testsuite/gas/aarch64/prel_g2.d: New. * testsuite/gas/aarch64/prel_g2_nc.s: New. * testsuite/gas/aarch64/prel_g2_nc.d: New. * testsuite/gas/aarch64/prel_g3.s: New. * testsuite/gas/aarch64/prel_g3.d: New.
2018-01-18 13:08:40 +01:00
2018-01-24 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
MIPS/GAS: Correct default ABI selection for `mips64*-ps2-elf*' Correct an issue with the `mips64*-ps2-elf*' target introduced with commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation 2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html> and make the n32 ABI the default for GAS, consistently with how BFD and LD are configured for this target. gas/ * configure.ac: Also set `mips_default_abi' to N32_ABI for `mips64*-ps2-elf*'. * configure: Regenerate.
2018-01-23 22:18:24 +01:00
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* configure.ac: Also set `mips_default_abi' to N32_ABI for
`mips64*-ps2-elf*'.
* configure: Regenerate.
MIPS/GAS: Remove a stale OPTION_COMPAT_ARCH_BASE option marker Complement commit 23fce1e31156 ("MIPS16 intermix test failure"), <https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and remove a stale option marker entry. gas/ * config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE enum value.
2018-01-23 20:01:35 +01:00
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE
enum value.
Enable Intel PCONFIG instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23 17:56:30 +01:00
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
Enable Intel WBNOINVD instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23 17:39:05 +01:00
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
MIPS/GAS: Correct `as --help' always reporting `o32' as the default ABI Remove an issue with `as --help' always reporting `o32' as the default ABI regardless of what the default actually is, originally caused by commit cac012d6d394 ("check mips abi x linker emulation compatibility"), <https://sourceware.org/ml/binutils/2003-05/msg00187.html> missing an update here. gas/ * config/tc-mips.c (md_show_usage): Correctly indicate the configuration-specific default ABI.
2018-01-23 15:51:22 +01:00
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (md_show_usage): Correctly indicate the
configuration-specific default ABI.
MIPS/GAS: Add missing `-mmips16e2'/`-mno-mips16e2' help text Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS bug and add missing help text for the `-mmips16e2' and `-mno-mips16e2' options added with said commit. gas/ * config/tc-mips.c (md_show_usage): Report `-mmips16e2' and `-mno-mips16e2' options.
2018-01-23 15:51:22 +01:00
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (md_show_usage): Report `-mmips16e2' and
`-mno-mips16e2' options.
GAS/doc: Correct `.set nomips16e2' directive description syntax gas/ * doc/c-mips.texi (MIPS ASE Instruction Generation Overrides): Correct syntax of the `.set nomips16e2' directive description.
2018-01-22 22:06:35 +01:00
2018-01-22 Maciej W. Rozycki <macro@mips.com>
* doc/c-mips.texi (MIPS ASE Instruction Generation Overrides):
Correct syntax of the `.set nomips16e2' directive description.
Fix the RX assembler so that it can handle escaped double quote characters, ie: \" PR 22737 * config/tc-rx.c (rx_start_line): Handle escaped double-quote character. * testsuite/gas/rx/pr22737.s: New test. * testsuite/gas/rx/pr22737.d: Likewise. * testsuite/gas/rx/rx.exp: Run the new test.
2018-01-22 15:31:10 +01:00
2018-01-22 Oleg Endo <olegendo@gcc.gnu.org>
PR 22737
* config/tc-rx.c (rx_start_line): Handle escaped double-quote character.
* testsuite/gas/rx/pr22737.s: New test.
* testsuite/gas/rx/pr22737.d: Likewise.
* testsuite/gas/rx/rx.exp: Run the new test.
[gas/ARM] Remove spurious comments Remove spurious comments after the definition of ToC and ToU. 2018-01-19 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (ToC macro): Remove spurious comment. (ToU macro): Likewise.
2018-01-19 15:17:24 +01:00
2018-01-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (ToC macro): Remove spurious comment.
(ToU macro): Likewise.
RISC-V: Fix bug in prior addi/c.nop patch. gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-17 23:04:16 +01:00
2018-01-17 Jim Wilson <jimw@sifive.com>
* config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
(riscv_ip) <'z'>: New.
Replace CET bit with IBT and SHSTK bits. The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-17 17:45:52 +01:00
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
Update translations for various binutils components. ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.
2018-01-16 13:45:44 +01:00
2018-01-16 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
RISC-V: Add support for addi that compresses to c.nop. gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15 23:53:44 +01:00
2018-01-15 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
[ARM] Add new macro for Thumb-only opcodes Armv8-M Security Extensions introduced some Thumb-only opcodes (eg. sg). These are defined using the TUE and TCE macros, setting the Arm execution state related fields to 0/NULL. This patch adds 2 new macros to avoid filling this field and clearly identify Thumb-only instructions. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (ToC): Define macro. (ToU): Likewise. (insns): Make use of above macros for new instructions introduced in Armv8-M.
2018-01-15 15:13:33 +01:00
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (ToC): Define macro.
(ToU): Likewise.
(insns): Make use of above macros for new instructions introduced in
Armv8-M.
[ARM] Enable conditional Armv8-M instructions Newly introduced instructions common to ARMv8-M Baseline and Mainline are currently all marked as unconditional. However, all instructions but sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually support conditional execution. This patch fixes the definition of these instructions accordingly. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm conditionally executable and reindent parameters. * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of aforementionned instructions.
2018-01-15 15:11:02 +01:00
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
[ARM] No IT usage deprecation for ARMv8-M Deprecations related to the use of the IT instruction introduced in Armv8-A do not apply to Armv8-M Baseline and mainline. However the warning logic do not distinguish between the various profiles and warn whenever the architecture version is 8. This patch adds a check to exclude M profile architectures from this warning. This works as expected when -march is specified on the command-line or a .arch/.cpu directive exist. However, in autodetection mode the CPU/architecture targeted is only known once the instructions have been all processed but this code is run when IT instruction is processed. It is therefore not possible to distinguish between Armv8-M and Armv8-A in that mode. The approach chosen here is not to warn in autodetection mode. The udf.d testcase that relied on that behavior to test deprecation warning for Armv8-A is therefore updated to explicitely pass -march=armv8-a. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M profile architecture or if in autodetection mode. Clarify that deprecation is for performance reason and concerns Armv8-A and Armv8-R. * testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning message. * testsuite/gas/arm/armv8-ar-it-bad.l: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise. * testsuite/gas/arm/udf.l: Likewise. * testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
2018-01-15 15:09:28 +01:00
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M
profile architecture or if in autodetection mode. Clarify that
deprecation is for performance reason and concerns Armv8-A and Armv8-R.
* testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning
message.
* testsuite/gas/arm/armv8-ar-it-bad.l: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise.
* testsuite/gas/arm/udf.l: Likewise.
* testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes
2018-01-15 13:09:11 +01:00
2018-01-15 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Update pot files
2018-01-13 14:56:48 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* po/gas.pot: Regenerated.
Bump version number to 2.30.51 bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2018-01-13 14:31:12 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
Add 2.30 markers to NEWS files. binutils/ * NEWS: Add marker for 2.30. gas/ * NEWS: Add marker for 2.30. ld/ * NEWS: Add marker for 2.30.
2018-01-13 14:20:55 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
Add note about 2.30 branch creation to changelogs
2018-01-13 14:26:38 +01:00
2.30 branch created.
Add 2.30 markers to NEWS files. binutils/ * NEWS: Add marker for 2.30. gas/ * NEWS: Add marker for 2.30. ld/ * NEWS: Add marker for 2.30.
2018-01-13 14:20:55 +01:00
* NEWS: Add marker for 2.30.
Fix compile time warning building aout targeted architectures. Occasionally I build an out-of-tree a.out target (m68k-amigaos). After a system upgrade which included a newer compiler (clang 4) the build produces warnings like this: warning: macro expansion producing 'defined' has undefined behavior [-Wexpansion-to-defined] This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC. Since it is in a header file, the warning triggers for several files. I am unsure what solution is preferable, thus I am suggesting two patches: a) keep the offending macro but define it explicitly to 0 and 1 b) replace the macro usage with its value where it is used. Either patch removes the warning for clang. I did not check with a recent GCC. * gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly define to 0 and 1. Remove a dangling reference to "AMD 29000" in a comment.
2018-01-12 14:12:17 +01:00
2018-01-12 Gunther Nikl <gnikl@users.sourceforge.net>
* gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly
define to 0 and 1. Remove a dangling reference to "AMD 29000"
in a comment.
Remove VL variants for 4FMAPS and 4VNNIW insns. AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-11 00:56:45 +01:00
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* testsuite/i386/avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/i386/avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/i386/avx512_4fmaps_vl.d: Likewise.
* testsuite/i386/avx512_4fmaps_vl.s: Likewise.
* testsuite/i386/avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/i386/avx512_4vnniw_vl.d: Likewise.
* testsuite/i386/avx512_4vnniw_vl.s: Likewise.
* testsuite/i386/i386.exp: Removed _vl tests for 4fmaps an 4vnniw
tests.
* testsuite/i386/x86-64-avx512_4fmaps_vl-intel.d: Removed.
* testsuite/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
gas tc-arm.c warning fix * config/tc-arm.c (aeabi_set_public_attributes): Avoid false positive "‘profile’ may be used uninitialized".
2018-01-11 00:04:58 +01:00
2018-01-11 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (aeabi_set_public_attributes): Avoid false
positive "‘profile’ may be used uninitialized".
x86: fix Disp8 handling for scalar AVX512_4FMAPS insns Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10 14:53:43 +01:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512_4fmaps.s,
testsuite/gas/i386/avx512_4fmaps_vl.s,
testsuite/gas/i386/x86-64-avx512_4fmaps.s,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Actually test
Disp8 forms (and the transition happening at the right
boundary).
* testsuite/gas/i386/avx512_4fmaps.d,
testsuite/gas/i386/avx512_4fmaps-intel.d,
testsuite/gas/i386/avx512_4fmaps_vl.d,
testsuite/gas/i386/avx512_4fmaps_vl-intel.d,
testsuite/gas/i386/x86-64-avx512_4fmaps.d,
testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Adjust
expectations.
x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-10 14:53:05 +01:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512bw.s,
testsuite/gas/i386/avx512bw_vl.s: Add VPCMP* tests with memory
operands.
* testsuite/gas/i386/avx512bw-intel.d,
testsuite/gas/i386/avx512bw.d,
testsuite/gas/i386/avx512bw_vl-intel.d.
testsuite/gas/i386/avx512bw_vl.d: Adjust expectations.
RISC-V: Disassemble x0 based addresses as 0. gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-10 01:40:06 +01:00
2018-01-09 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
[Arm] Add CSDB instruction CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09 15:15:00 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
Add support for the AArch64's CSDB instruction. CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-09 12:28:04 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB for hint 0x14.
x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08 13:36:59 +01:00
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22681
* testsuite/gas/i386/i386.exp: Run x86-64-movd and
x86-64-movd-intel.
* testsuite/gas/i386/x86-64-movd-intel.d: New file.
* testsuite/gas/i386/x86-64-movd.d: Likewise.
* testsuite/gas/i386/x86-64-movd.s: Likewise.
Add a description of the X86_64 assembler's .largcomm pseudo-op. PR 22553 * doc/c-i386.texi (i386-Directives): Document the .largecomm directive.
2018-01-08 10:29:17 +01:00
2018-01-08 Nick Clifton <nickc@redhat.com>
PR 22553
* doc/c-i386.texi (i386-Directives): Document the .largecomm
directive.
RISC-V: Add 2 missing privileged registers. gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.
2018-01-04 23:17:53 +01:00
2018-01-04 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
* testsuite/gas/riscv/priv-reg.d: Likewise.
Update year range in copyright notice of binutils files
2018-01-03 06:17:27 +01:00
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
Fix typo in do_mrs function in ARM assembler. PR 18119 * config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked version of ARM MRS instruction.
2018-01-02 13:13:17 +01:00
2018-01-02 Nick Clifton <nickc@redhat.com>
PR 18119
* config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked
version of ARM MRS instruction.
ChangeLog rotation
2018-01-03 06:15:17 +01:00
For older changes see ChangeLog-2017
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
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Copyright (C) 2018 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
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