Commit Graph

7221 Commits

Author SHA1 Message Date
Peter Bergner 11a0cf2ec0 Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1.  It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case.  I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue.  I also fixed the mftb and mfcr instructions
so they use the same mechanism.  This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

	* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
	(ppc_optional_operand_value): New inline function.

opcodes/
	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

gas/
	* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
	Allow for optional operands without insert functions.

gas/testsuite/
	* gas/ppc/power8.d: Fixup rfebb test results.
	* gas/ppc/a2.s: Fix invalid mfcr test.
	* gas/ppc/a2.d: Likewise.
2015-06-19 17:17:07 -05:00
Nick Clifton c12d2c9d48 Add support for using the ADR alias in Thumb mode against nearby symbols.
PR gas/18541
gas	* config/tc-arm.c (md_apply_fix): Add support for ADR in thumb
	mode against a nearby symbol.

tests	* gas/arm/thumb.s: Add test of ADR against a nearby symbol.
	* gas/arm/thumb.d: Update expected output.
	* gas/arm/thumb-eabi.d: Likewise.
2015-06-18 10:23:16 +01:00
Nick Clifton 75c1199967 Fix the computation of the addends for an ARM_TLS_LE32 reloc.
PR gas/18481
bfd	* elf32-arm.c (R_ARM_TLS_LE32): Set the special function to NULL.

gas	* config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32
	in the same case as BFD_RELOC_ARM_TLS_IS32.

tests	* gas/arm/tls.s: Add tests of the tpoff pseudo with a local
	symbol.
	* gas/arm/tls.d: Update expected output.
2015-06-18 10:18:42 +01:00
Nick Clifton 5fc177c895 Fix compile warnings building previous delta in a 32-bit environment.
* config/tc-arm.c (is_double_a_single): Make conditional upon the
	availablity of a 64-bit type.  Use this type for the argument and
	mantissa.
	(double_to_single): Likewise.
	* config/tc-arm.c (move_or_literal_pool): Use a 64-bit type for
	the constant value, if available.  Generate a 64-bit value from a
	bignum if supported.  Only perform the second optimization for
	PR 18500 if the 64-bit type is available.
2015-06-17 16:10:36 +01:00
Alessandro Marzocchi 1256987795 Add support for converting LDR Rx,=<imm> to MOV or MVN in Thumb2 mode.
PR gas/18499
gas	* config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
	to MOV.w or MVN.w for Thumb2.

tests	* gas/arm/thumb2_ldr_immediate_armv6.s: New test case.
	* gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly.
	* gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case.
	* gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
2015-06-17 13:50:52 +01:00
Alessandro Marzocchi ba592044bc Add support for converting VLDR <reg>,=<constant> to a VMOV instruction when appropriate.
PR gas/18500
gas	* config/tc-arm.c (is_double_a_single): New function.
	(double_to_single): New function.
	(move_or_literal_pool): Add support for	converting VLDR to VMOV.

tests	* gas/arm/vfpv2-ldr_immediate.s: New test case.
	* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
	* gas/arm/vfpv3-ldr_immediate.s: New test case.
	* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
	* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
	* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
2015-06-17 12:56:17 +01:00
Nicolas Pitre 451133cefa gas: section name substitution sequence
This patch adds the ability to automatically construct a section name
based on the prior section.

When gas is invoked with --sectname-subst, the occurrence of %S in a
section name will be substituted by the name of the current section. For
example:

	.macro exception_code
	.pushsection %S.exception
	[exception code here]
	.popsection
	.endm

	.text
	[code]
	exception_code
	[...]

	.section .init
	[init code]
	exception_code
	[...]

The first and second exception_code invocations create the
.text.exception and the .init.exception sections respectively.  This is
useful e.g. to discriminate between anciliary sections that are tied to
.init code and can be discarded at run time when initialization is over
vs anciliary sections tied to .text sections that need to stay resident.

	* as.c (show_usage): Document --sectname-subst.
	(parse_args): Add --sectname-subst.
	* as.h (flag_sectname_subst): New.
	* config/obj-elf.c (obj_elf_section_name): Add %S substitution.
	* doc/as.texinfo: Document it.
2015-06-17 08:52:00 +09:30
Matthew Wahab bdfa8b951b [AArch64] Support id_mmfr4 system register
2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
opcodes/
  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

gas/testsuite
  * sysreg.d: Add id_mmfr4_el1, update expected output.
  * sysreg.s: Add id_mmfr4_el1.
2015-06-16 14:17:34 +01:00
Renlin Li 87f5fbcc7a [AArch64] Gas add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 support
2015-06-15  Renlin Li <renlin.li@arm.com>
bfd/
    * reloc.c (BFD_RELOC_AARCH64_LD64_GOTOFF_LO15): New entry.
    * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
    BFD_RELOC_AARCH64_LD64_GOTOFF_LO15.
    * bfd-in2.h: Regenerate.
    * libbfd.h: Regenerate.

gas/
    * config/tc-aarch64.c (reloc_table): New relocation modifier.
    (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTOFF_LO15.
    (aarch64_force_relocation): Ditto

gas/testsuite/
    * gas/aarch64/reloc-insn.s: Update test
    * gas/aarch64/reloc-insn.d: Update expected result.
2015-06-15 11:07:37 +01:00
Mark Wielaard d025d5e5b5 gas: Don't use frag_align but use plain padding to align .debug_aranges.
out_debug_aranges uses frag_align to make sure the addresses start
out aligned. Using frag_align will call frag_var[_init], which will
end up calling TC_FRAG_INIT. On arm and aarch64 TC_FRAG_INIT will
generate a $d mapping symbol for the .debug_aranges to show that at
that point a sequence of data items starts.

Such a symbol pointing into a non-allocated debug section will confuse
eu-strip -g. And it seems inefficient and wrong in general to have
additional mapping symbols for debug sections, which won't contain
actual code in the first place.

Just keep track of the aranges header size and use plain padding to
align the addresses which avoids generating any mapping symbols on
aarch64 and arm.

Includes a testcase for aarch64 that PASS with this patch and shows
the extra $d mapping symbol in .debug_aranges before.

gas/ChangeLog

       * dwarf2dbg.c (out_header): Document EXPR->X_add_number value,
       out_debug_aranges depends on it.
       (out_debug_aranges): Track size of header to properly pad header
       for address alignment.

gas/testsuite/ChangeLog

       * gas/aarch64/dwarf.d: New.
       * gas/aarch64/dwarf.s: New.
2015-06-15 09:25:21 +02:00
John David Anglin 18c208b229 tc-hppa.c: Speed up search for last label 2015-06-11 18:50:39 -04:00
Nick Clifton f0e8c65e02 Fix RX GAS handling of integer bignums.
* config/tc-rx.c (rx_op): Correct handling of integer bignums.
2015-06-08 11:32:38 +01:00
Peter Bergner dc302c0061 Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.

opcodes/
	* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.

gas/testsuite/
	* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
	* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
	* gas/ppc/power4.d: Likewise.
2015-06-04 20:27:03 -05:00
Nick Clifton 239c0f4ceb Fix compile time warning for tc-h8300.c when using gcc 5+.
* config/tc-h8300.c (md_section_align): Fix compile time warning
	about left shifting a negative value.
2015-06-04 16:25:03 +01:00
Matthew Wahab 88f0ea342d [AArch64] Add support for ARMv8.1 command line option 2015-06-04 11:14:07 +01:00
Jiong Wang b968d18a6d [ARM] Use frag's thumb_mode information when available
2015-06-04  Renlin Li  <renlin.li@arm.com>

	* config/tc-arm.c (arm_init_frag): Use frag's thumb_mode information
	when available.
2015-06-04 09:36:35 +01:00
Matthew Wahab f277626b45 [ARM] Commit approaved testcases missed in previous commit
2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/arm/armv8-a+rdma.d: New.
	* gas/arm/armv8-a+rdma.s: New.
2015-06-03 10:55:29 +01:00
Matthew Wahab a5932920ef [ARM] Support for ARMv8.1 command line option
2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>

gas/
	* config/tc-arm.c (arm_archs): Add "armv8.1-a".
	* doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
	* NEWS: Mention ARMv8.1 support.

include/opcode/
	* arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
	(ARM_ARCH_V8_1A): New.
	(ARM_ARCH_V8_1A_FP): New.
	(ARM_ARCH_V8_1A_SIMD): New.
	(ARM_ARCH_V8_1A_CRYPTOV1): New.
	(ARM_FEATURE_CORE): New.
2015-06-03 10:03:50 +01:00
Matthew Wahab d6b4b13ed2 [ARM] Support for ARMv8.1 Adv.SIMD extension 2015-06-02 12:37:33 +01:00
Matthew Wahab ddfded2f7b [ARM] Add support for ARMv8.1 PAN extension 2015-06-02 12:30:38 +01:00
Matthew Wahab 9e1f0fa7f3 [AArch64] Support for ARMv8.1a Adv.SIMD instructions
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

gas/
  * config/tc-aarch64.c (aarch64_features): Add "rdma".
  * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".

gas/testsuite/
  * rdma-directive.d: New.
  * rdma.d: New.
  * rdma.s: New.

include/opcode/
  * aarch64.h (AARCH64_FEATURE_RDMA): New.

opcode/
  * aarch64-tbl.h (aarch64_feature_rdma): New.
  (RDMA): New.
  (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.
2015-06-02 12:20:00 +01:00
Matthew Wahab 290806fd94 [AArch64] Support for ARMv8.1a Limited Ordering Regions extension
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
include/
  * aarch64.h (AARCH64_FEATURE_LOR): New.

opcodes/
  * aarch64-tbl.h (aarch64_feature_lor): New.
  (LOR): New.
  (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  "stllrb", "stllrh".
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.

gas/
  * config/tc-aarch64.c (aarch64_features): Add "lor".
  * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
  architecture extensions.

gas/testsuite/
  * lor-directive.d: New.
  * lor.d: New.
  * lor.s: New.
2015-06-02 11:30:12 +01:00
Matthew Wahab 72ca8fad61 [AArch64][GAS] Add support for PAN architecture extension
2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
gas/
	* config/tc-aarch64.c (parse_sys_reg): New parameter.  Check
	target support.  Fix whitespace.
	(parse_operands): Update for parse_sys_reg changes.
	(aarch64_features): Add "pan".
	* doc/c-aarch64.texi (Aarch64 Extensions): Add "pan".

gas/testsuite/
	* pan-directive.d: New.
	* pan.d: New.
	* pan.s: New
2015-06-01 16:05:58 +01:00
Jiong Wang 3d715ce420 [AArch64] GAS support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
This patch add BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 support in Gas.

The relocation modifier
===
  :gotpage_lo14:symbol

2015-06-01 Jiong.Wang <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers.
  (md_apply_fix): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14.
  (aarch64_force_relocation): Ditto.

gas/testsuite/
  * gas/aarch64/ilp32-basic.s: New testcase.
  * gas/aarch64/ilp32-basic.d: Ditto.
2015-06-01 15:41:54 +01:00
Jiong Wang a921b5bd70 [AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
2015-06-01 Jiong.Wang <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers.
  (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
  (aarch64_force_relocation): Ditto.

gas/testsuite/
  * gas/aarch64/reloc-insn.s: New testcase.
  * gas/aarch64/reloc-insn.d: Ditto.
2015-06-01 10:22:15 +01:00
Jan Beulich 3a8547d2fb x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.

gas/testsuite/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512f.s: Adjust operand order for Intel syntax
	vcvt{,u}si2ss.
	* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
	syntax vcvt{,u}si2s{d,s}.

opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.
2015-06-01 09:51:28 +02:00
Jan Beulich 015c54d5a6 x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.

gas/testsuite/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
	* gas/i386/evex-lig256-intel.d: Likewise.
	* gas/i386/evex-lig512-intel.d: Likewise.
	* gas/i386/x86-64-avx512f-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig512-intel.d: Likewise.

opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.
2015-06-01 09:50:00 +02:00
Catherine Moore 2f0c68f23b Compact EH Support
The specification for the Compact EH format is available at:
https://github.com/MentorEmbedded/cxx-abi/blob/master/MIPSCompactEH.pdf

2015-05-28  Catherine Moore  <clm@codesourcery.com>
	    Bernd Schmidt <bernds@codesourcery.com>
	    Paul Brook <paul@codesourcery.com>

	bfd/
	* bfd-in2.h: Regenerated.
	* elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define.
	(COMPACT_EH_CANT_UNWIND_OPCODE): Define.
	(dwarf_eh_frame_hdr_info): Move dwarf-specific fields from
	eh_frame_hdr_info.
	(compact_eh_frame_hdr_info): Declare.
	(eh_frame_hdr_info):  Redeclare with union for dwarf-specific
	fields and compact-eh fields.
	(elf_backend_data): Add cant_unwind_opcode and compact_eh_encoding.
	(bfd_elf_section_data): Add eh_frame_entry_field.
	(elf_section_eh_frame_entry): Define.
	(bfd_elf_parse_eh_frame_entries): Declare.
	(_bfd_elf_parse_eh_frame_entry): Declare.
	(_bfd_elf_end_eh_frame_parsing): Declare.
	(_bfd_elf_write_section_eh_frame_entry): Declare.
	(_bfd_elf_eh_frame_entry_present): Declare.
	(_bfd_elf_section_for_symbol): Declare.
	* elf-eh-frame.c (bfd_elf_discard_eh_frame_entry): New function.
	(bfd_elf_record_eh_frame_entry): New function.
	(_bfd_elf_parse_eh_frame_entry): New function.
	(_bfd_elf_parse_eh_frame): Update hdr_info field references.
	(cmp_eh_frame_hdr): New function.
	(add_eh_frame_hdr_terminator): New function.
	(_bfd_elf_end_eh_frame_parsing): New function.
	(find_merged_cie): Update hdr_info field references.
	(_bfd_elf_discard_section_eh_frame): Likewise.
	(_bfd_elf_discard_section_eh_frame_hdr): Add Compact EH support.
	(_bfd_elf_eh_frame_entry_present): New function.
	(_bfd_elf_maybe_strip_eh_frame_hdr): Add Compact EH support.
	(_bfd_elf_write_section_eh_frame_entry): New function.
	(_bfd_elf_write_section_eh_frame): Update hdr_info field references.
	(_bfd_elf_fixup_eh_frame_hdr): New function.
	(write_compact_eh_frame_hdr): New function.
	(write_dwarf_eh_frame_hdr): New function.
	(_bfd_elf_write_section_eh_frame_hdr): Add Compact EH support.
	* elflink.c (_bfd_elf_section_for_symbol): New function.
	(elf_section_ignore_discarded_relocs): Add Compact EH support.
	(elf_link_input_bfd): Likewise.
	(bfd_elf_final_link): Likewise.
	(_bfd_elf_gc_mark): Likewise.
	(bfd_elf_parse_eh_frame_entries): New function.
	(bfd_elf_gc_sections): Add Compact EH support.
	(bfd_elf_discard_info): Likewise.
	* elfxx-mips.c: Include dwarf2.h.
	(_bfd_mips_elf_compact_eh_encoding): New function.
	(_bfd_mips_elf_cant_unwind_opcode): New function.
	* elfxx-mips.h (_bfd_mips_elf_compact_eh_encoding): Declare.
	(_bfd_mips_elf_cant_unwind_opcode): Declare.
	(elf_backend_compact_eh_encoding): Define.
	(elf_backend_cant_unwind_opcode): Define.
	* elfxx-target.h (elf_backend_compact_eh_encoding): Provide default.
	(elf_backend_cant_unwind_opcode): Provide default.
	(elf_backend_data elfNN_bed): Add elf_backend_compact_eh_encoding and
	elf_backend_cant_unwind_opcode.
	* section.c (SEC_INFO_TYPE_EH_FRAME_ENTRY): Add definition.

	gas/
	* config/tc-alpha.c (all_cfi_sections): Declare.
	(s_alpha_ent): Initialize all_cfi_sections.
	(alpha_elf_md_end): Invoke cfi_set_sections.
	* config/tc-mips.c (md_apply_fix):  Handle BFD_RELOC_NONE.
	(s_ehword): Use BFD_RELOC_32_PCREL.
	(mips_fix_adjustable): Handle BFD_RELOC_32_PCREL.
	(mips_cfi_reloc_for_encoding): New function.
	* tc-mips.h (DWARF2_FDE_RELOC_SIZE): Redefine.
	(DWARF2_FDE_RELOC_ENCODING): Define.
	(tc_cfi_reloc_for_encoding): Define.
	(mips_cfi_reloc_for_encoding): Define.
	(tc_compact_eh_opcode_stop): Define.
	(tc_compact_eh_opcode_pad): Define.
	* doc/as.texinfo: Document Compact EH extensions.
	* doc/internals.texi: Likewise.
	* dw2gencfi.c (EH_FRAME_LINKONCE): Redefine.
	(tc_cfi_reloc_for_encoding): Provide default.
	(compact_eh): Declare.
	(emit_expr_encoded): New function.
	(get_debugseg_name): Add Compact EH support.
	(alloc_debugseg_item): Likewise.
	(cfi_set_sections): New function.
	(dot_cfi_fde_data): New function.
	(dot_cfi_personality_id): New function.
	(dot_cfi_inline_lsda): New function.
	(cfi_pseudo_table): Add cfi_fde_data, cfi_personality_id,
	and cfi_inline_lsda.
	(dot_cfi_personality): Add Compact EH support.
	(dot_cfi_lsda): Likewise.
	(dot_cfi_sections): Likewise.
	(dot_cfi_startproc): Likewise.
	(get_cfi_seg): Likewise.
	(output_compact_unwind_data): New function.
	(output_cfi_insn): Add Compact EH support.
	(output_cie): Likewise.
	(output_fde): Likewise.
	(cfi_finish): Likewise.
	(cfi_emit_eh_header): New function.
	(output_eh_header): New function.
	* dw2gencfi.h (cfi_set_sections): Declare.
	(SUPPORT_COMPACT_EH): Define.
	(MULTIPLE_FRAME_SECTIONS): Define.
	New enumeration to describe the Compact EH header format.
	(fde_entry): Add new fields personality_id, eh_header_type, eh_data_size,
	eh_data, eh_loc and sections.
	(CFI_EMIT_eh_frame, CFI_EMIT_debug_frame, CFI_EMIT_target,
	CFI_EMIT_eh_frame_compact): Define.

2015-05-22  Catherine Moore  <clm@codesourcery.com>
	    Bernd Schmidt <bernds@codesourcery.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.

	* gas/mips/compact-eh-1.s: New file.
	* gas/mips/compact-eh-2.s: New file.
	* gas/mips/compact-eh-3.s: New file.
	* gas/mips/compact-eh-4.s: New file.
	* gas/mips/compact-eh-5.s: New file.
	* gas/mips/compact-eh-6.s: New file.
	* gas/mips/compact-eh-7.s: New file.
	* gas/mips/compact-eh-eb-1.d: New file.
	* gas/mips/compact-eh-eb-2.d: New file.
	* gas/mips/compact-eh-eb-3.d: New file.
	* gas/mips/compact-eh-eb-4.d: New file.
	* gas/mips/compact-eh-eb-5.d: New file.
	* gas/mips/compact-eh-eb-6.d: New file.
	* gas/mips/compact-eh-eb-7.d: New file.
	* gas/mips/compact-eh-el-1.d: New file.
	* gas/mips/compact-eh-el-2.d: New file.
	* gas/mips/compact-eh-el-3.d: New file.
	* gas/mips/compact-eh-el-4.d: New file.
	* gas/mips/compact-eh-el-5.d: New file.
	* gas/mips/compact-eh-el-6.d: New file.
	* gas/mips/compact-eh-el-7.d: New file.
	* gas/mips/compact-eh-err1.l: New file.
	* gas/mips/compact-eh-err1.s: New file.
	* gas/mips/compact-eh-err2.l: New file.
	* gas/mips/compact-eh-err2.s: New file.

2015-05-22  Catherine Moore  <clm@codesourcery.com>

	include/
	* bfdlink.h: Rename eh_frame_hdr to eh_frame_hdr_type.

2015-05-22  Catherine Moore  <clm@codesourcery.com>
	    Paul Brook <paul@codesourcery.com>

	ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_after_open):
	Add Compact EH support.
	* scripttempl/elf.sc: Handle .eh_frame_entry and .gnu_extab
	sections.

2015-05-22  Catherine Moore  <clm@codesourcery.com>

	ld/testsuite/
	* ld-mips-elf/compact-eh.ld: New linker script.
	* ld-mips-elf/compact-eh1.d: New.
	* ld-mips-elf/compact-eh1.s: New.
	* ld-mips-elf/compact-eh1a.s: New.
	* ld-mips-elf/compact-eh1b.s: New.
	* ld-mips-elf/compact-eh2.d: New.
	* ld-mips-elf/compact-eh2.s: New.
	* ld-mips-elf/compact-eh3.d: New.
	* ld-mips-elf/compact-eh3.s: New.
	* ld-mips-elf/compact-eh3a.s: New.
	* ld-mips-elf/compact-eh4.d: New.
	* ld-mips-elf/compact-eh5.d: New.
	* ld-mips-elf/compact-eh6.d: New.
	* ld-mips-elf/mips-elf.exp: Run new tests.
2015-05-28 15:21:17 -07:00
Max Filippov 4de0562a4c xtensa: fix gas segfault with --text-section-literals
When --text-section-literals is used and code in the .init or .fini
emits literal in the absence of .literal_position, xtensa_move_literals
segfaults.

Check that search_frag is non-NULL in the xtensa_move_literals and
report error otherwise.

2015-05-26  Max Filippov  <jcmvbkbc@gmail.com>
gas/
	* config/tc-xtensa.c (xtensa_move_literals): Check that
	search_frag is non-NULL. Report error if literal frag is not
	found.
2015-05-26 10:14:17 +03:00
Nick Clifton 29798047af Fixes: "gas/read.c:5087:12: error: left shift of negative"
PR gas/18446
	* read.c (output_big_sleb128): Use U suffix to prevent compile
	time warning.
2015-05-22 14:27:36 +01:00
Jiong Wang f09c556a25 [AArch64] Sort relocation case labels alphabetically
2015-05-19  Jiong. Wang  <jiong.wang@arm.com>

gas/
  * config/tc-aarch64.c (process_movw_reloc_info): Sort relocation case labels
  alphabetically.
  (md_apply_fix): Ditto.
  (aarch64_force_relocation): Ditto.
2015-05-20 10:48:29 +01:00
H.J. Lu 5db04b0965 Support AMD64/Intel ISAs in assembler/disassembler
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00
H.J. Lu 8dcea93252 Add -mshared option to x86 ELF assembler
This patch adds -mshared option to x86 ELF assembler.  By default,
assembler will optimize out non-PLT relocations against defined non-weak
global branch targets with default visibility.  The -mshared option tells
the assembler to generate code which may go into a shared library
where all non-weak global branch targets with default visibility can
be preempted.  The resulting code is slightly bigger.  This option
only affects the handling of branch instructions.

This Linux kernel patch is needed to create a working x86 Linux kernel if
it hasn't been applied:

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ae6588b..b91a00c 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -339,8 +339,8 @@ early_idt_handlers:
 	i = i + 1
 	.endr

-/* This is global to keep gas from relaxing the jumps */
-ENTRY(early_idt_handler)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(early_idt_handler)
 	cld

 	cmpl $2,(%rsp)		# X86_TRAP_NMI
--

gas/

	* config/tc-i386.c (shared): New.
	(OPTION_MSHARED): Likewise.
	(elf_symbol_resolved_in_segment_p): Add relocation argument.
	Check PLT relocations and shared.
	(md_estimate_size_before_relax): Pass fragP->fr_var to
	elf_symbol_resolved_in_segment_p.
	(md_longopts): Add -mshared.
	(md_show_usage): Likewise.
	(md_parse_option): Handle OPTION_MSHARED.
	* doc/c-i386.texi: Document -mshared.

gas/testsuite/

	* gas/i386/i386.exp: Don't run pcrel for ELF targets.  Run
	pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
	* gas/i386/pcrel-elf.d: New file.
	* gas/i386/relax-4.d: Likewise.
	* gas/i386/x86-64-relax-3.d: Likewise.
	* gas/i386/relax-3.d: Pass -mshared to assembler.  Updated.
	* gas/i386/x86-64-relax-2.d: Likewise.
	* gas/i386/relax-3.s: Add test for PLT relocation.
2015-05-15 03:30:53 -07:00
Peter Bergner 4bc0608a8b Fix some PPC assembler errors.
Remove the wait instructions for server processors, since they were never
implemented.  Also add the extra operands added to the tlbie and slbia
instructions with ISA 2.06 and ISA 2.05 respectively.

binutils/
	* MAINTAINERS: Add myself as PPC maintainer.

opcodes/
        * ppc-opc.c (IH) New define.
        (powerpc_opcodes) <wait>: Do not enable for POWER7.
        <tlbie>: Add RS operand for POWER7.
        <slbia>: Add IH operand for POWER6.

gas/testsuite/
        * gas/ppc/power4.d: Add a slbia test.
        * gas/ppc/power4.s: Likewise.
        * gas/ppc/power6.d: Add slbia and tlbie tests.
        * gas/ppc/power6.s: Likewise.
        * gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
        * gas/ppc/power7.s: Likewise.
2015-05-14 21:02:50 -05:00
H.J. Lu dab394de9e Don't add the zlib header to SHF_COMPRESSED section
In a SHF_COMPRESSED compressed section, the raw compressed data should
begin immediately after the compression header.  This patch removes the
extra zlib header from the SHF_COMPRESSED section.

bfd/

	* bfd.c (bfd_update_compression_header): Also write the zlib
	header if the SHF_COMPRESSED bit cleared..
	(bfd_check_compression_header): Return the uncompressed size.
	* compress.c (decompress_contents): Don't skip the zlib header.
	(bfd_compress_section_contents): Properly handle ELFCOMPRESS_ZLIB,
	which doesn't have the zlib header.
	(bfd_init_section_decompress_status): Likewise.
	(bfd_get_full_section_contents): Updated.
	(bfd_is_section_compressed): Likewise.
	(bfd_is_section_compressed_with_header): Return the uncompressed
	size.
	* elf.c (_bfd_elf_make_section_from_shdr): Updated.
	* bfd-in2.h: Regenerated.

binutils/

	* readelf.c (uncompress_section_contents): Add a parameter for
	uncompressed size.  Don't check the zlib header.
	(load_specific_debug_section): Updated.

binutils/testsuite/

	* binutils-all/compress.exp: Replace "$OBJDUMP -s -j .debug_info"
	with "$OBJDUMP -W".
	* binutils-all/libdw2-compressedgabi.out: Updated.

gas/

2015-05-14  H.J. Lu  <hongjiu.lu@intel.com>

	* write.c (compress_debug): Don't write the zlib header, which
	is handled by bfd_update_compression_header.
2015-05-14 16:02:08 -07:00
Max Filippov dc58915f3a xtensa: fix gas trampolines regression
Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline
selection results in regressions: when relaxable jump is little longer
than J_RANGE so that single trampoline makes two new jumps, one longer
than J_RANGE / 2 and one shorter, correct trampoline cannot be found.

Drop that condition.

2015-05-13  Max Filippov  <jcmvbkbc@gmail.com>
gas/
	* config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
	closer than J_RANGE / 2 to jump frag.

gas/testsuite/
	* gas/xtensa/trampoline.s: Add regression testcase.
2015-05-13 19:25:52 +03:00
H.J. Lu e69c76f4bf Revert "Add -mno-shared to x86 assembler"
This reverts commit 573cc2e57d.
2015-05-13 04:47:59 -07:00
H.J. Lu 31955f993d Add missing ChangeLog entries for PR binutis/18386 2015-05-13 04:33:45 -07:00
H.J. Lu 5197d47436 Default e_machine to EM_IAMCU for i?86-*-elfiamcu
This patch sets the default ELF output format of assembler and linker to
EM_IAMCU when binutils is configured to i?86-*-elfiamcu target.

gas/

	* configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target.
	* config/tc-i386.c (i386_mach): Support iamcu.
	(i386_target_format): Likewise.

ld/

	* configure.tgt: Support i[3-7]86-*-elfiamcu target.

ld/testsuite/

	* ld-i386/i386.exp (iamcu_tests): Run iamcu-4.
	* ld-i386/iamcu-4.d: New file.
2015-05-11 12:06:33 -07:00
H.J. Lu 814860358c Add Intel MCU support to gas
-march=iamcu must be passed to i386 assembler to generate Intel MCU object
file.

gas/

	* config/tc-i386.c (cpu_arch): Add iamcu.
	(i386_align_code): Handle PROCESSOR_IAMCU.
	(i386_arch): Likewise.
	(i386_mach): Likewise.
	(i386_target_format): Likewise.
	(valid_iamcu_cpu_flags): New function.
	(check_cpu_arch_compatible): Only allow Intel MCU instructions
	when targeting Intel MCU.
	(set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags
	are valid for Intel MCU.
	(md_parse_option): Likewise.
	* tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New.
	(processor_type): Add PROCESSOR_IAMCU.
	* doc/c-i386.texi: Document iamcu.

gas/testsuite/

	* gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1,
	iamcu-inval-2 and iamcu-inval-3.
	* gas/i386/iamcu-1.d: New file.
	* gas/i386/iamcu-1.s: Likewise.
	* gas/i386/iamcu-2.d: Likewise.
	* gas/i386/iamcu-2.s: Likewise.
	* gas/i386/iamcu-3.d: Likewise.
	* gas/i386/iamcu-3.s: Likewise.
	* gas/i386/iamcu-inval-1.l: Likewise.
	* gas/i386/iamcu-inval-1.s: Likewise.
	* gas/i386/iamcu-inval-2.l: Likewise.
	* gas/i386/iamcu-inval-2.s: Likewise.
	* gas/i386/iamcu-inval-3.l: Likewise.
	* gas/i386/iamcu-inval-3.s: Likewise.
2015-05-11 11:12:39 -07:00
H.J. Lu a72d2af2c7 Ignore 0x66 prefix for call/jmp/jcc in 64-bit mode
The operand size prefix (0x66) is ignored for 32-bit PC-relative call,
jmp and jcc in 64-bit mode.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-jump.
	* gas/i386/x86-64-branch.d: Updated.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch.s: Add tests for the operand size prefix
	with call, jmp and jb.
	* gas/i386/x86-64-jump.d: New file.
	* gas/i386/x86-64-jump.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Updated.
	* ld-x86-64/tlspic.dd: Likewise.

opcodes/

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.
2015-05-09 06:44:29 -07:00
Nick Clifton ae8714c271 Change ARM symbol name verification code so that it only triggers when the form "name = val" is used.
PR gas/18347
	* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
	* config/tc-arm.c (arm_tc_equal_in_insn): New function.  Move
	the symbol name checking code to here from...
	(md_undefined_symbo): ... here.
2015-05-08 17:28:26 +01:00
H.J. Lu 573cc2e57d Add -mno-shared to x86 assembler
On ELF target, the assembler normally generates code which can go into a
shared library where non-weak symbols can be preempted.  The -mno-shared
option tells the assembler to generate code not for a shared library,
where non-weak symbols won't be preempted.  The resulting code is slightly
smaller.  This option mainly affects the handling of branch instructions.

gas/

	* config/tc-i386.c (no_shared): New.
	(OPTION_MNO_SHARED): Likewise.
	(elf_symbol_resolved_in_segment_p): Check no_shared.
	(md_longopts): Add mno-shared.
	(md_parse_option): Handle OPTION_MNO_SHARED.
	(md_show_usage): Add -mno-shared.
	* doc/c-i386.texi: Document -mno-shared.

gas/testsuite/

	* gas/i386/i386.exp: Run relax-4 and x86-64-relax-3.
	* gas/i386/relax-4.d: New file.
	* gas/i386/x86-64-relax-3.d: Likewise.
2015-05-08 05:05:49 -07:00
H.J. Lu b084df0b8d Optimize branches to non-weak symbols with visibility
Branches to global non-weak symbols defined in the same segment with
non-default visibility can be optimized the same way as branches to
local symbols.

gas/

	* config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
	(md_estimate_size_before_relax): Use it.

gas/testsuite/

	* gas/i386/i386.exp: Run relax-3 and x86-64-relax-2.
	* gas/i386/relax-3.d: New file.
	* gas/i386/relax-3.s: Likewise.
	* gas/i386/x86-64-relax-2.d: Likewise.
2015-05-07 09:19:16 -07:00
Jose E. Marchesi 0d495746bb gas: typo in comment fixed.
gas/ChangeLog:

2015-05-06  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c: Typo in comment fixed.
2015-05-06 09:28:22 -07:00
Jose E. Marchesi 9e85c798e3 gas: added tests for the sparc natural instructions.
gas/ChangeLog:

2015-05-06  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/natural-32.d: Test ldn, ldna, stn, stna, slln, srln,
	sran, casn, casna and clrn.
	* gas/sparc/natural-32.s: Likewise.
	* gas/sparc/natural.s: Likewise.
	* gas/sparc/natural.d: Likewise.
2015-05-06 09:27:52 -07:00
Jose E. Marchesi f9911bebca gas: support for the sparc %ncc condition codes register.
gas/ChangeLog:

2015-05-06  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
	condition codes
	* doc/c-sparc.texi (Sparc-Regs): Document %ncc.

gas/testsuite/ChangeLog:

2015-05-06  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/natural.s: New file.
	* gas/sparc/natural-32.s: Likewise.
	* gas/sparc/natural.d: Likewise.
	* gas/sparc/natural-32.d: Likewise.
	* gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and
	natural-32.
2015-05-06 09:26:23 -07:00
Nick Clifton ed1fcdd119 Update GAS documentation to note that dollar local labels are only supported on some targets.
* doc/as.texinfo (Dollar Local Labels): Note that these are only
	supported on some targets.
2015-05-06 13:13:10 +01:00
Renlin Li 448eb63d72 [AArch64] Record instruction alignment for .inst directive
2015-05-06  Renlin Li  <renlin.li@arm.com>

  gas/
    * config/tc-aarch64.c (mapping_state): Recording alignment before exit.

  gas/testsuite/
    * gas/aarch64/codealign_1.s: New.
    * gas/aarch64/codealign_1.d: New.
2015-05-06 12:18:19 +01:00
Renlin Li c7ad08e6e5 [AARCH64] Positively emit symbols for alignment
2015-05-05  Renlin Li  <renlin.li@arm.com>

  gas/
    * config/tc-aarch64.c (aarch64_init_frag): Always generate mapping symbols.

  gas/testsuite/
    * gas/aarch64/mapping_5.d: New.
    * gas/aarch64/mapping_5.s: New.
    * gas/aarch64/mapping_6.d: New.
    * gas/aarch64/mapping_6.s: New.
2015-05-05 17:48:18 +01:00
Nick Clifton 837a17b36c Add support to the MSP430 linker for the automatic placement of code and data into either low or high memory regions.
gas	* config/tc-msp430.c (MAX_OP_LEN): Increase to 4096.
	(msp430_make_init_symbols): New function.
	(msp430_section): Call it.
	(msp430_frob_section): Likewise.

ld	* emulparams/msp430elf.sh (TEMPLATE_NAME): Change to msp430.
	* scripttempl/msp430.sc (.text): Add .lower.text and .either.text.
	(.data): Add .lower.data and .either.data.
	(.bss): Add .lower.bss and .either.bss.
	(.rodata): Add .lower.rodata and .either.rodata.
	* emultempl/msp430.em: New file.  Implements a new orphan
	placement algorithm that divides sections between lower and upper
	memory regions.
	* Makefile.am (emsp430elf.c): Depend upon msp430.em.
	*emsp430X.c): Likewise.
	* Makefine.in: Regenerate.
2015-05-05 13:38:00 +01:00
Max Filippov b76f99d702 xtensa: optimize trampolines relaxation
Currently every fixup in the current segment is checked when relaxing
trampoline frag. This is very expensive. Make a searchable array of
fixups pointing at potentially oversized jumps at the beginning of every
relaxation pass and only check subset of this cache in the reach of
single jump from the trampoline frag currently being relaxed.

Original profile:

% time    self  children    called     name
-----------------------------------------
        370.16  593.38 12283048/12283048     relax_segment
  98.4  370.16  593.38 12283048         xtensa_relax_frag
         58.91  269.26 2691463834/2699602236     xtensa_insnbuf_from_chars
         68.35   68.17 811266668/813338977     S_GET_VALUE
         36.85   29.51 2684369246/2685538060     xtensa_opcode_decode
         28.34    8.84 2684369246/2685538060     xtensa_format_get_slot
         12.39    5.94 2691463834/2699775044     xtensa_format_decode
          0.03    4.60 4101109/4101109     relax_frag_for_align
          0.18    1.76  994617/994617      relax_frag_immed
          0.07    0.09 24556277/24851220     new_logical_line
          0.06    0.00 12283048/14067410     as_where
          0.04    0.00 7094588/15460506     xtensa_format_num_slots
          0.00    0.00       1/712477      xtensa_insnbuf_alloc
-----------------------------------------

Same data, after optimization:

% time    self  children    called     name
-----------------------------------------
          0.51    7.47 12283048/12283048     relax_segment
  58.0    0.51    7.47 12283048         xtensa_relax_frag
          0.02    4.08 4101109/4101109     relax_frag_for_align
          0.18    1.39  994617/994617      relax_frag_immed
          0.01    0.98     555/555         xtensa_cache_relaxable_fixups
          0.21    0.25 7094588/16693271     xtensa_insnbuf_from_chars
          0.06    0.12 24556277/24851220     new_logical_line
          0.06    0.00 7094588/15460506     xtensa_format_num_slots
          0.02    0.04 7094588/16866079     xtensa_format_decode
          0.05    0.00 12283048/14067410     as_where
          0.00    0.00       1/712477      xtensa_insnbuf_alloc
          0.00    0.00   93808/93808       xtensa_find_first_cached_fixup
-----------------------------------------

2015-05-02  Max Filippov  <jcmvbkbc@gmail.com>
gas/
	* config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs.
	(struct cached_fixup, struct fixup_cache): New structures.
	(fixup_order, xtensa_make_cached_fixup),
	(xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups),
	(xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup),
	(xtensa_add_cached_fixup): New functions.
	(xtensa_relax_frag): Cache fixups pointing at potentially
	oversized jumps at the beginning of every relaxation pass. Only
	check subset of this cache in the reach of single jump from the
	trampoline frag currently being relaxed.
2015-05-05 07:57:33 +03:00
DJ Delorie d62de9aa69 Fix typos in previous patch.
* config/rl78-parse.y (MULU): Remove ISA_G14.
(MULH, DIVHU, DIVWU, MACHI, MACH): Update error strings.
2015-05-01 15:08:07 -04:00
H.J. Lu 00923338de Remove i386_elf_emit_arch_note
This x86 assembler patch:

https://sourceware.org/ml/binutils/2001-11/msg00344.html

generates a .note section for .arch directive so that GDB can tell which
architecture an i386 binary belongs:

https://sourceware.org/ml/binutils/2001-11/msg00271.html

However, x86 assembly code can have any instructions.  A .note section
doesn't help.  This patch removes it.

gas/

	* config/tc-i386.c (i386_elf_emit_arch_note): Removed.
	* config/tc-i386.h (md_end): Likewise.
	(i386_elf_emit_arch_note): Likewise.

gas/testsuite/

	* gas/i386/i386.exp: Run note.
	* gas/i386/note.d: New file.
	* gas/i386/note.s: Likewise.
2015-05-01 08:29:16 -07:00
H.J. Lu b633b7258d Support ix86-*-elf*
bfd/

	* config.bfd: Support i[3-7]86-*-elf*.

gas/

	* configure.tgt: Support i386-*-elf*.
2015-05-01 05:02:30 -07:00
DJ Delorie 0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 15:25:49 -04:00
H.J. Lu b49f93f699 Use "else if" on cpu_arch_isa
* config/tc-i386.c (i386_target_format): Use "else if" on
	cpu_arch_isa.
2015-04-30 08:36:17 -07:00
Nick Clifton 8b2d793ce5 GAS ARM: Warn if the user creates a symbol with the same name as an instruction.
PR gas/18347
gas	* config/tc-arm.c (md_undefined_symbol): Issue a warning message
	(if enabled) when the user creates a symbol with the same name as
	an ARM instruction.
	(flag_warn_syms): New static variable.
	(arm_opts): Add mwarn-syms and mno-warn-syms.
	* doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
	options.

tests	* gas/arm/pr18347.s: New file: Test case.
	* gas/arm/pr18347.l: New file: Expected assembler output.
	* gas/arm/pr18347.d: New file: Test driver.
2015-04-30 11:17:55 +01:00
Nick Clifton 7ce98c164e Adds documentation of GAS's .zero directive.
PR gas/18353
	* doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
2015-04-30 10:13:53 +01:00
Nick Clifton 99b2a2dd3c Fix an internal error in GAS when assembling a bogus piece of source code.
gas	PR 18256
	* config/tc-arm.c (encode_arm_cp_address): Issue an error message
	if the operand is neither a register nor a vector.

tests	* gas/arm/pr18256.s: New file: Test case.
	* gas/arm/pr18256.l: New file: Expected assembler output.
	* gas/arm/pr18256.d: New file: Test driver.
2015-04-29 17:09:05 +01:00
Nick Clifton 5d239759c0 Updates the description of GAS's .set directive, to note that for some targets a symbolic value can only be set once.
* doc/as.texinfo (Set): Note that a symbol cannot be set multiple
	times if the expression is not constant and the target uses linker
	relaxation.
2015-04-29 11:10:45 +01:00
Renlin Li f9c1b181a7 [ARM]Positively emit symbols for alignment
2015-04-28  Renlin Li  <renlin.li@arm.com>
  gas/
    * config/tc-arm.c (arm_init_frag): Always emit mapping symbols.

  gas/testsuite/
    * gas/arm/thumb2_vpool_be.d: Adjust the desired output.
    * gas/arm/vldconst_be.d: Ditto.
2015-04-28 17:10:26 +01:00
Nick Clifton da7119c99c Fix compile time warnings about a local variable being used before it is set.
PR 18313
	* cond.c (s_if): Stop compile time warning about stopc being used
	before it is set.
	(s_ifc): Likewise.
2015-04-28 11:22:57 +01:00
Peter Bergner 4fff86c517 opcodes/
* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

gas/testsuite/

	* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
	ordering change.
	* gas/ppc/a2.d: Likewise.
	* gas/ppc/476.d: Likewise.
	* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
	* gas/ppc/booke.d: Likewise.
	* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
	and waitimpl tests.
	* gas/ppc/power7.d: Likewise.
2015-04-27 11:06:54 -05:00
Renlin Li eb9d6cc91a [AArch64] Don't try to align insn in non-executale section
2015-04-27  Renlin Li  <renlin.li@arm.com>

  gas/
    * config/tc-aarch64.c (s_aarch64_inst): Don't align code for non-text
    section.
    (md_assemble): Likewise, move the align code outside the loop.
2015-04-27 11:36:12 +01:00
Andreas Krebbel 643f7afb0d S/390: z13 use GNU attribute to indicate vector ABI
bfd/
	* elf-s390-common.c (elf_s390_merge_obj_attributes): New function.
	* elf32-s390.c (elf32_s390_merge_private_bfd_data): Call
	elf_s390_merge_obj_attributes.
	* elf64-s390.c (elf64_s390_merge_private_bfd_data): New function.

binutils/
	* readelf.c (display_s390_gnu_attribute): New function.
	(process_s390_specific): New function.
	(process_arch_specific): Call process_s390_specific.

gas/
	* doc/as.texinfo: Document Tag_GNU_S390_ABI_Vector.

include/elf/
	* s390.h: Define Tag_GNU_S390_ABI_Vector.
2015-04-27 10:32:23 +02:00
Andreas Krebbel 3b78cfe103 S/390: Fixes for z13 instructions.
opcodes/
	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

gas/testsuite/
	* gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
	WFC.
  	* gas/s390/zarch-z13.s: Likewise.
2015-04-27 10:29:16 +02:00
Jim Wilson faade85139 gas thunderx support
gas/
* config/tc-aarch64.c (aarch64_cpus): Add CRC and CRYPTO features
for thunderx.
2015-04-24 13:44:20 -07:00
Richard Earnshaw 7a5c933c7c [ARM]: Don't tail-pad over-aligned functions to the alignment boundary.
2015-04/24  Richard Earnshaw  <rearnsha@arm.com>

	gas/
	* config/tc-arm.h (arm_min): New function.
	(SUB_SEGMENT_ALIGN): Define.

	gas/testsuite/
	* gas/arm/align64.d: Delete trailing padding NOPs.

	ld/testsuite/
	* ld-arm/armthumb-lib.d: Regenerate expected output.
	* ld-arm/armthumb-lib.d: Likewise.
	* ld-arm/armthumb-lib.sym: Likewise.
	* ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise.
	* ld-arm/cortex-a8-fix-b-rel-thumb.d: Likewise.
	* ld-arm/cortex-a8-fix-b.d: Likewise.
	* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: Likewise.
	* ld-arm/cortex-a8-fix-bcc.d: Likewise.
	* ld-arm/cortex-a8-fix-bl-rel-arm.d: Likewise.
	* ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise.
	* ld-arm/cortex-a8-fix-bl-rel-thumb.d: Likewise.
	* ld-arm/cortex-a8-fix-bl.d: Likewise.
	* ld-arm/cortex-a8-fix-blx-bcond.d: Likewise.
	* ld-arm/cortex-a8-fix-blx-rel-arm.d: Likewise.
	* ld-arm/cortex-a8-fix-blx-rel-thumb.d: Likewise.
	* ld-arm/cortex-a8-fix-blx.d: Likewise.
	* ld-arm/cortex-a8-fix-hdr.d: Likewise.
	* ld-arm/farcall-mixed-app-v5.d: Likewise.
	* ld-arm/farcall-mixed-app.d: Likewise.
	* ld-arm/farcall-mixed-lib-v4t.d: Likewise.
	* ld-arm/farcall-mixed-lib.d: Likewise.
	* ld-arm/mixed-app-v5.d: Likewise.
	* ld-arm/mixed-app.d: Likewise.
	* ld-arm/mixed-lib.d: Likewise.
2015-04-24 15:54:39 +01:00
Matthew Fortune ece794d9c4 Improve warning messages for la/dla
gas/

	* config/tc-mips.c (macro): State the recommended way of creating
	32-bit or 64-bit addresses.

gas/testsuite/

	* gas/mips/dla-warn.l: New file.
	* gas/mips/dla-warn.s: New file.
	* gas/mips/la-warn.l: New file.
	* gas/mips/la-warn.s: New file.
	* gas/mips/mips.exp: Run new tests.
2015-04-23 22:23:17 +01:00
Matthew Fortune 2ca4ff6d5b Fix r6-branch-constraints test when run with n64 as default ABI
gas/testsuite/

	* gas/mips/mips.exp: Require o32 for r6-branch-constraints.
2015-04-23 21:03:32 +01:00
Jan Beulich 04d824a468 x86: disambiguate disassembly of certain AVX512 insns
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.

gas/testsuite/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
	register, non-broadcast cases.
	* gas/i386/x86-64-avx512dq.d: Likewise.
	* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
	vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
	cases.
	* gas/i386/x86-64-avx512dq_vl.d: Likewise.
	* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
	vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
	cases.
	* gas/i386/x86-64-avx512f_vl.d: Likewise.

opcodes/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.
2015-04-23 16:42:40 +02:00
Jan Beulich af508cb92f x86: don't require operand size specification for AVX512 broadcasts
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory. That ambiguity, however, doesn't
apply when using broadcasts (the destination operand size can be
induced from the broadcast specifier).

gas/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (match_mem_size): Also allow no size
	specification when broadcasting.

gas/testsuite/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in
	some AT&T and all Intel cases.
	* gas/i386/x86-64-avx512dq.s: Likewise.
	* gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from
	vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel
	cases.
	* gas/i386/x86-64-avx512dq_vl.s: Likewise.
	* gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from
	vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel
	cases.
	* gas/i386/x86-64-avx512f_vl.s: Likewise.
2015-04-23 16:41:21 +02:00
H.J. Lu be59ad3d96 Don't hardcode offset of .shstrtab section
There is no requirement on placement of section name section, .shstrtab.
This patch removes hardcoded offsets of .shstrtab sections.

binutils/testsuite/

	* binutils-all/i386/compressed-1b.d: Don't hardcode offset of
	.shstrtab section.
	* binutils-all/i386/compressed-1c.d: Likewise.
	* binutils-all/readelf.s-64: Likewise.
	* binutils-all/x86-64/compressed-1b.d: Likewise.
	* binutils-all/x86-64/compressed-1c.d: Likewise.

gas/testsuite/

	* gas/i386/ilp32/x86-64-unwind.d: Don't hardcode offset of
	.shstrtab section.
	* gas/i386/x86-64-unwind.d: Likewise.
	* gas/ia64/alias-ilp32.d: Likewise.
	* gas/ia64/alias.d: Likewise.
	* gas/ia64/group-1.d: Likewise.
	* gas/ia64/group-2.d: Likewise.
	* gas/ia64/secname-ilp32.d: Likewise.
	* gas/ia64/secname.d: Likewise.
	* gas/ia64/unwind-ilp32.d: Likewise.
	* gas/ia64/unwind.d: Likewise.
	* gas/mmix/bspec-1.d: Likewise.
	* gas/mmix/byte-1.d: Likewise.
	* gas/mmix/loc-1.d: Likewise.
	* gas/mmix/loc-2.d: Likewise.
	* gas/mmix/loc-3.d: Likewise.
	* gas/mmix/loc-4.d: Likewise.
	* gas/mmix/loc-5.d: Likewise.
	* gas/tic6x/scomm-directive-4.d: Likewise.

ld/testsuite/

	* ld-mmix/bspec1.d: Don't hardcode offset of .shstrtab section.
	* ld-mmix/bspec2.d: Likewise.
	* ld-mmix/local1.d: Likewise.
	* ld-mmix/local3.d: Likewise.
	* ld-mmix/local5.d: Likewise.
	* ld-mmix/local7.d: Likewise.
	* ld-mmix/undef-3.d: Likewise.
	* ld-sh/sh64/crangerel1.rd: Likewise.
	* ld-sh/sh64/crangerel2.rd: Likewise.
	* ld-tic6x/common.d: Likewise.
	* ld-tic6x/shlib-1.rd: Likewise.
	* ld-tic6x/shlib-1b.rd: Likewise.
	* ld-tic6x/shlib-1r.rd: Likewise.
	* ld-tic6x/shlib-1rb.rd: Likewise.
	* ld-tic6x/shlib-app-1.rd: Likewise.
	* ld-tic6x/shlib-app-1b.rd: Likewise.
	* ld-tic6x/shlib-app-1r.rd: Likewise.
	* ld-tic6x/shlib-app-1rb.rd: Likewise.
	* ld-tic6x/shlib-noindex.rd: Likewise.
	* ld-tic6x/static-app-1.rd: Likewise.
	* ld-tic6x/static-app-1b.rd: Likewise.
	* ld-tic6x/static-app-1r.rd: Likewise.
	* ld-tic6x/static-app-1rb.rd: Likewise.
	* ld-x86-64/ilp32-4.d: Likewise.
	* ld-x86-64/split-by-file-nacl.rd: Likewise.
	* ld-x86-64/split-by-file.rd: Likewise.
2015-04-20 09:55:47 -07:00
H.J. Lu d3b47e2bd4 Silence texinfo 5.1 warnings
This patch silences texinfo 5.1 warnings by using @subsection and
sorting entries in Machine Dependencies menu.

	* doc/as.texinfo (Bundle directives): Shorten menu entry and
	use @subsection.
	(CFI directives): Use @subsection.
	(SH-Dependent, SH64-Dependent): Moved after SCORE-Dependent.
	* doc/c-i386.texi (i386-Mnemonics): Use @subsection.
2015-04-20 08:08:42 -07:00
Senthil Kumar Selvaraj ef7a936968 Fix avr compiler warning
declaration of "link" shadows a global declaration

	* config/tc-avr.c (create_record_for_frag): Rename link to
	prop_rec_link.
2015-04-17 21:01:28 +09:30
H.J. Lu f24bcbaa5a Handle invalid prefixes for rdrand and rdseed
This patch puts rdrand and rdseed in prefix_table so that invalid
prefixes for rdrand and rdseed are handled properly.

gas/testsuite/

	PR binutils/17898
	* gas/i386/prefix.s: Add rdrand/rdseed prefix tests.
	* gas/i386/prefix.d: Updated.

opcodes/

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
2015-04-15 09:57:55 -07:00
Renlin Li f0fba320ab [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15  Renlin Li  <renlin.li@arm.com>
opcodes/:
    * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
    use it for ssat and ssat16.
    (print_insn_thumb32): Add handle case for 'D' control code.

gas/testsuite/:
    * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
    * gas/arm/thumb32.d: Likewise.
2015-04-15 17:44:03 +01:00
H.J. Lu ea556d2590 Mention --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
binutils/

	* NEWS: Mention
	--compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].

gas/

	* NEWS: Mention
	--compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].

ld/

	* NEWS: Mention
	--compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].
2015-04-15 05:26:41 -07:00
H.J. Lu 0ce398f106 Add --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
This patch adds --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
to ld for ELF targets to support generating compressed DWARF debug
sections.  We always generate .zdebug_* section since section names have
been finalized and they can't be changed easily when compression is
being performed.

bfd/

	* bfd-in.h (compressed_debug_section_type): New.
	* compress.c (bfd_compress_section_contents): Add an argument
	for linker write compression and always generate .zdebug_*
	section when linking.
	(bfd_init_section_compress_status): Pass FALSE to
	bfd_compress_section_contents.
	(bfd_compress_section): New function.
	* elf.c (elf_fake_sections): For linking, set SEC_ELF_COMPRESS
	on DWARF debug sections if COMPRESS_DEBUG is set and rename
	section if COMPRESS_DEBUG_GABI_ZLIB isn't set.
	(assign_file_positions_for_non_load_sections): Set sh_offset
	to -1 if SEC_ELF_COMPRESS is set.
	(assign_file_positions_except_relocs): Likwise.
	(_bfd_elf_assign_file_positions_for_relocs): Renamed to ...
	(_bfd_elf_assign_file_positions_for_non_load): This.  Change
	return time to bfd_boolean.  Compress the section if
	SEC_ELF_COMPRESS is set.
	(_bfd_elf_write_object_contents): Updated.
	(_bfd_elf_set_section_contents): Write section contents to
	the buffer if SEC_ELF_COMPRESS is set.
	* merge.c: Include "elf-bfd.h".
	(sec_merge_emit): Add arguments for contents and offset.  Write
	to contents with offset if contents isn't NULL.
	(_bfd_write_merged_section): Write section contents to the
	buffer if SEC_ELF_COMPRESS is set.  Pass contents and
	output_offset to sec_merge_emit.
	* elflink.c (bfd_elf_final_link): Allocate the buffer for
	output section contents if SEC_ELF_COMPRESS is set.
	* section.c (SEC_ELF_COMPRESS): New.
	* bfd-in2.h: Regenerated.

gas/

	* as.h (compressed_debug_section_type): Removed.

include/

	* bfdlink.h (bfd_link_info): Add compress_debug.

ld/

	* ld.texinfo: Document --compress-debug-sections=.
	* ldmain.c (main): Set BFD_COMPRESS on output_bfd if
	COMPRESS_DEBUG is set.  Set BFD_COMPRESS_GABI on output_bfd
	for COMPRESS_DEBUG_GABI_ZLIB.
	* lexsup.c (elf_static_list_options): Add
	--compress-debug-sections=.
	* emultempl/elf32.em (OPTION_COMPRESS_DEBUG): New.
	(xtra_long): Add "compress-debug-sections".
	(gld${EMULATION_NAME}_handle_option): Handle
	OPTION_COMPRESS_DEBUG.

ld/testsuite/

	* ld-elf/compress.exp (build_tests): Add tests for
	--compress-debug-sections=.
	(run_tests): Likewise.
	Add additonal tests for --compress-debug-sections=.
	* ld-elf/gabiend.rt: New file.
	* ld-elf/gabinormal.rt: Likewise.
	* ld-elf/gnubegin.rS: Likewise.
	* ld-elf/gnunormal.rS: Likewise.
	* ld-elf/zlibbegin.rS: Likewise.
	* ld-elf/zlibnormal.rS: Likewise.
2015-04-14 22:01:38 -07:00
Nick Clifton 6ff71e7681 Adds support to the RL78 port for linker relaxation affecting .debug sections.
gas	* config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define.
	(TC_FORCE_RELOCATION_SUB_SAME): Define.
	(DWARF2_USE_FIXED_ADVANCE_PC): Define.

	* gas/lns/lns.exp: Add RL78 to list of targets using
	DW_LNS_fixed_advance_pc.

bfd	* elf32-rl78.c (RL78_OP_REL): New macro.
	(rl78_elf_howto_table): Use it for complex relocs.
	(get_symbol_value): Handle the cases when the info or status
	arguments are NULL.
	(get_romstart): Cache the status returned by get_symbol_value.
	(get_ramstart): Likewise.
	(RL78_STACK_PUSH): Generate an error message if the stack
	overflows.
	(RL78_STACK_POP): Likewise for underflows.
	(rl78_compute_complex_reloc): New function.  Contains the basic
	processing code for all RL78 complex relocs.
	(rl78_special_reloc): New function.  Provides special reloc
	handling for complex relocs.
	(rl78_elf_relocate_section): Use rl78_compute_complex_reloc.
	(rl78_offset_for_reloc): Likewise.

binutils* readelf.c (target_specific_reloc_handling): Add code to handle
	RL78 complex relocs.
2015-04-14 16:23:33 +01:00
Nick Clifton 080bb7bbe9 Add documentation about the interation of the ARM assembler's -EB option and the linker's --be8 option.
PR binutils/18198
	* ld.texinfo (--be8): Add a note about the interaction of this
	option with the assembler's -EB option.

	* doc/c-arm.texi (ARM Options): Add a note about the interaction of
	the -EB option with the linker's --be8 option.
2015-04-10 08:26:07 +01:00
Hans-Peter Nilsson 4b5708f5d9 doc/c-rx.texi: Fix markup typos in last change. 2015-04-09 21:09:02 +02:00
Nick Clifton 3525236c57 Add support to the RX toolchain to restrict the use of string instructions.
bfd	* elf32-rx.c (describe_flags): Report the settings of the string
	insn using bits.
	(rx_elf_merge_private_bfd_data): Handle merging of the string insn
	using bits.

bin	* readelf.c (get_machine_flags): Report the setting of the string
	insn using bits.

gas	* config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
	(md_longopts): Add -mno-allow-string-insns.
	(md_parse_option): Handle -mno-allow-string-insns.
	(md_show_usage): Mention -mno-allow-string-insns.
	(rx_note_string_insn_use): New function.  Produces an error
	message if a string insn is used when it is not allowed.
	* config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
	(SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
	* config/rx-defs.h (rx_note_string_insn_use): Prototype.
	* doc/c-rx.texi: Document -mno-allow-string-insns.

elf	* rx.h (E_FLAG_RX_SINSNS_SET): New bit in e_flags field.
	(E_FLAG_RX_SINSNS_YES): Likewise.
	(E_FLAG_RX_SINSNS_MASK): New define.
2015-04-09 12:48:37 +01:00
H.J. Lu 151411f8af Add SHF_COMPRESSED support to gas and objcopy
This patch adds --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}
options to gas and objcopy for ELF files. They control how DWARF debug
sections are compressed.  --compress-debug-sections=none is equivalent to
--nocompress-debug-sections.  --compress-debug-sections=zlib and
--compress-debug-sections=zlib-gnu are equivalent to
--compress-debug-sections.  --compress-debug-sections=zlib-gabi compresses
DWARF debug sections with SHF_COMPRESSED from the ELF ABI.  No linker
changes are required to support SHF_COMPRESSED.

bfd/

	* archive.c (_bfd_get_elt_at_filepos): Also copy BFD_COMPRESS_GABI
	bit.
	* bfd.c (bfd::flags): Increase size to 18 bits.
	(BFD_COMPRESS_GABI): New.
	(BFD_FLAGS_SAVED): Add BFD_COMPRESS_GABI.
	(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
	(bfd_update_compression_header): New fuction.
	(bfd_check_compression_header): Likewise.
	(bfd_get_compression_header_size): Likewise.
	(bfd_is_section_compressed_with_header): Likewise.
	* compress.c (MAX_COMPRESSION_HEADER_SIZE): New.
	(bfd_compress_section_contents): Return the uncompressed size if
	the full section contents is compressed successfully.  Support
	converting from/to .zdebug* sections.
	(bfd_get_full_section_contents): Call
	bfd_get_compression_header_size to get compression header size.
	(bfd_is_section_compressed): Renamed to ...
	(bfd_is_section_compressed_with_header): This.  Add a pointer
	argument to return compression header size.
	(bfd_is_section_compressed): Use it.
	(bfd_init_section_decompress_status): Call
	bfd_get_compression_header_size to get compression header size.
	Return FALSE if uncompressed section size is 0.
	* elf.c (_bfd_elf_make_section_from_shdr): Support converting
	from/to .zdebug* sections.
	* bfd-in2.h: Regenerated.

binutils/

	* objcopy.c (do_debug_sections): Add compress_zlib,
	compress_gnu_zlib and compress_gabi_zlib.
	(copy_options): Use optional_argument on compress-debug-sections.
	(copy_usage): Update --compress-debug-sections.
	(copy_file): Handle compress_zlib, compress_gnu_zlib and
	compress_gabi_zlib.
	(copy_main): Handle
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
	* doc/binutils.texi: Document
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.

binutils/testsuite/

	* compress.exp: Add tests for
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
	* binutils-all/dw2-3.rS: New file.
	* binutils-all/dw2-3.rt: Likewise.
	* binutils-all/libdw2-compressedgabi.out: Likewise.

gas/

	* as.c (show_usage): Update --compress-debug-sections.
	(std_longopts): Use optional_argument on compress-debug-sections.
	(parse_args): Handle
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
	* as.h (compressed_debug_section_type): New.
	(flag_compress_debug): Change type to compressed_debug_section_type.
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
	* write.c (compress_debug): Set BFD_COMPRESS_GABI for
	--compress-debug-sections=zlib-gabi.  Call
	bfd_get_compression_header_size to get compression header size.
	Don't rename section name for --compress-debug-sections=zlib-gabi.
	* config/tc-i386.c (compressed_debug_section_type): Set to
	COMPRESS_DEBUG_ZLIB.
	* doc/as.texinfo: Document
	--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.

gas/testsuite/

	* gas/i386/dw2-compressed-1.d: New file.
	* gas/i386/dw2-compressed-2.d: Likewise.
	* gas/i386/dw2-compressed-3.d: Likewise.
	* gas/i386/x86-64-dw2-compressed-2.d: Likewise.
	* gas/i386/i386.exp: Run dw2-compressed-2, dw2-compressed-1,
	dw2-compressed-3 and x86-64-dw2-compressed-2.

ld/testsuite/

	* ld-elf/compress.exp: Add a test for
	--compress-debug-sections=zlib-gabi.
	(build_tests): Add 2 tests for --compress-debug-sections=zlib-gabi.
	(run_tests): Likewise.
	Verify linker output with zlib-gabi compressed debug input.
	* ld-elf/compressed1a.d: New file.
	* ld-elf/compressed1b.d: Likewise.
	* ld-elf/compressed1c.d: Likewise.
2015-04-08 07:54:09 -07:00
Renlin Li a97902de74 [AArch64] use subseg_text_p to check .text
2015-04-07  Renlin Li  <renlin.li@arm.com>

gas/
  * config/tc-aarch64.c (mapping_state): Use subseg_text_p.
  (s_aarch64_inst): Likewise.
  (md_assemble): Likewise.
2015-04-07 18:10:33 +01:00
H.J. Lu dae148f3b9 Remove is_zlib_supported
Since zlib is always supported, there is no need for is_zlib_supported.

binutils/testsuite/

	* binutils-all/compress.exp: Remove is_zlib_supported check.
	* binutils-all/objdump.exp: Likewise.
	* binutils-all/readelf.exp (readelf_compressed_wa_test): Likewise.
	* lib/utils-lib.exp (run_dump_test): Likewise.
	* lib/binutils-common.exp (is_zlib_supported): Removed.

gas/testsuite/

	* lib/gas-defs.exp (run_dump_test): Remove is_zlib_supported check.

ld/testsuite/

	* ld-elf/compress.exp: Remove is_zlib_supported check.
	Fail if --compress-debug-sections doesn't work.
	* lib/ld-lib.exp (run_dump_test): Remove is_zlib_supported check.
2015-04-06 12:19:13 -07:00
H.J. Lu 4aa90cc007 Use bfd_putb64/bfd_getb64
bfd/

	* compress.c (get_uncompressed_size): Removed.
	(bfd_compress_section_contents): Use bfd_putb64 to write
	uncompressed section size.
	(bfd_init_section_decompress_status): Replace
	get_uncompressed_size with bfd_getb64.

gas/

	* write.c (compress_debug): Use bfd_putb64 to write uncompressed
	section size.
2015-04-06 09:02:52 -07:00
H.J. Lu 317974f683 Xfail the compressed debug sections
There is no need to generate compressed debug section if compressed
section size is the same as before compression.  We should xfail the
compressed debug section test if there are no compressed sections

binutils/testsuite/

	* binutils-all/compress.exp (compression_used): New.
	Xfail test if compression didn't make the section smaller.

gas/

2015-04-05  H.J. Lu  <hongjiu.lu@intel.com>

	* write.c (compress_debug): Don't write the zlib header if
	compressed section size is the same as before compression.
2015-04-05 08:15:35 -07:00
Nick Clifton f66adc4ead Second fix for microblaze gas port's ability to parse constants.
PR gas/18189
	* config/tc-microblaze.c (parse_imm): Use offsetT as the type for
	min and max parameters.  Sign extend values before testing.
2015-04-02 17:13:12 +01:00
Nick Clifton 03e080386e Fixes a bug in the microblaze assembler where it would not complain about constants larger than 32-bits.
PR gas/18189
	* config/tc-microblaze.c (parse_imm): Use offsetT as the type for
	min and max parameters.
2015-04-02 16:10:06 +01:00
Renlin Li c1baaddf88 [AArch64] Emit DATA_MAP in order within text section
2015-03-27  Renlin Li  <renlin.li@arm.com>

gas/
  * config/tc-aarch64.c (mapping_state): Emit MAP_DATA within text section in order.
  (mapping_state_2): Don't emit MAP_DATA here.
  (s_aarch64_inst): Align frag during state transition.
  (md_assemble): Likewise.
2015-04-02 14:59:45 +01:00
Ed Maste 726e626a7b Remove unused functions in tc-aarch64.c.
* config/tc-aarch64.c (set_error_kind): Delete.
	(set_error_message): Delete.
2015-04-02 14:44:59 +01:00
H.J. Lu 39f3de7c43 Regenerate configure in bfd/binutils/gas/gdb/gold
bfd/

	* configure: Regenerated.

binutils/

	* configure: Regenerated.

gas/

	* configure: Regenerated.

gdb/

	* Makefile.in (top_srcdir): New.
	* configure: Regenerated.

gold/

	* configure: Regenerated.
2015-04-02 05:45:03 -07:00
Evandro Menezes 2412d87834 [AArch64] Add support for the Samsung Exynos M1 processor
2015-03-26  Evandro Menezes  <e.menezes@samsung.com>

gas/
	* config/tc-aarch64.c: Add support for Samsung Exynos M1.
	* doc/c-aarch64.texi (-mcpu=): Add "exynos-m1".
2015-04-01 21:00:41 +00:00
Evandro Menezes 246496bb65 [ARM] Add support for the Samsung Exynos M1 processor
2015-03-26  Evandro Menezes  <e.menezes@samsung.com>

gas/
	* config/tc-arm.c: Add support for Samsung Exynos M1.
	* doc/c-arm.texi (-mcpu=): Add "exynos-m1".
2015-04-01 20:58:16 +00:00
H.J. Lu afa59b7900 Regenerate configure in bfd/binutils/gas/gdb
bfd/

2015-04-01  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

binutils/

2015-04-01  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

gas/

2015-04-01  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

gdb/

2015-04-01  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.
2015-04-01 04:55:48 -07:00
H.J. Lu 518a69099c Remove the last change on dw2-compress-1.d
The compressed .debug_info section is bigger than the original in 32-bit.
2015-03-31 08:20:55 -07:00
Ed Schouten 6036f48621 Add support for Nuxi CloudABI on x86-64
bfd/

	* config.bfd (targ_defvec): Set to x86_64_elf64_cloudabi_vec
	for x86_64-*-cloudabi*.
	* configure.ac: Handle x86_64_elf64_cloudabi_vec.
	* configure: Regenerated.
	* elf64-x86-64.c (TARGET_LITTLE_SYM): Support x86_64-*-cloudabi*.
	(TARGET_LITTLE_NAME): Likewise.
	(ELF_OSABI): Likewise.
	(elf64_bed): Likewise.
	* targets.c (x86_64_elf64_cloudabi_vec): New.
	(_bfd_target_vector): Add x86_64_elf64_cloudabi_vec.

gas/

	* configure.tgt (fmt): Set to elf for *-*-cloudabi*.

ld/

	* Makefile.am (ALL_64_EMULATION_SOURCES): Add
	eelf_x86_64_cloudabi.c.
	(eelf_x86_64_cloudabi.c): New.
	* configure.tgt (targ_emul): Set to elf_x86_64_cloudabi for
	x86_64-*-cloudabi*.
	* Makefile.in: Regenerated.
	* emulparams/elf_x86_64_cloudabi.sh: New file.
2015-03-31 08:11:08 -07:00
H.J. Lu 543b793377 Revert the AM_ZLIB change in gas
* configure.ac: Revert the AM_ZLIB change.
	* Makefile.in: Regenerated.
	* aclocal.m4: Likewise.
	* configure: Likewise.
2015-03-31 06:39:57 -07:00
H.J. Lu 0138187e9f Add --with-system-zlib in gas
This patch adds --with-system-zlib and remove --with-zlib in gas.

gas/

	* Makefile.am (ZLIBINC): New.
	(AM_CFLAGS): Add $(ZLIBINC).
	* as.c: (show_usage): Don't check HAVE_ZLIB_H.
	(parse_args): Likewise.
	* compress-debug.c: Don't check HAVE_ZLIB_H to include <zlib.h>.
	(compress_init): Don't check HAVE_ZLIB_H.
	(compress_data): Likewise.
	(compress_finish): Likewise.
	* configure.ac (AM_ZLIB): Removed.
	(zlibinc): New.  AC_SUBST.
	Add --with-system-zlib.
	* Makefile.in: Regenerated.
	* config.in: Likewise.
	* configure: Likewise.
	* doc/Makefile.in: Likewise.

gas/testsuite/

	* gas/i386/dw2-compress-1.d: Expect .zdebug_info.
2015-03-31 03:56:12 -07:00
H.J. Lu e04de5e3b5 Remove the unused cpu_flags_set
* config/tc-i386.c (cpu_flags_set): Removed.
2015-03-27 09:29:05 -07:00
Renlin Li bb383c6cf1 [AARCH64]Fix "align directive causes MAP_DATA symbol to be lost"
gas/ChangeLog:

2015-03-25  Renlin Li  <renlin.li@arm.com>

  * config/tc-aarch64.c (mapping_state): Remove first MAP_DATA emitting code.
  (mapping_state_2): Emit first MAP_DATA symbol here.
2015-03-25 12:33:07 +00:00
H.J. Lu b422eb499b Don't write the zlib header if not used
No need to write the zlib header if compression didn't make the section
smaller.

	PR gas/18087
	* write.c (compress_debug): Don't write the zlib header if
	compression didn't make the section smaller.
2015-03-24 19:06:22 -07:00
Terry Guo 823d25713d Extend arm_feature_set struct to provide more bits
gas/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (no_cpu_selected): Use new macro to compare
	features.
	(parse_psr): Likewise.
	(do_t_mrs): Likewise.
	(do_t_msr): Likewise.
	(static const arm_feature_set arm_ext_*): Defined with new
	macros.
	(static const arm_feature_set arm_cext_*): Likewise.
	(static const arm_feature_set fpu_fpa_ext_*): Likewise.
	(static const arm_feature_set fpu_vfp_ext_*): Likewise.
	(deprecated_coproc_regs): Likewise.
	(UL_BARRIER): Likewise.
	(barrier_opt_names): Likewise.
	(arm_cpus): Likewise.
	(arm_extensions): Likewise.

include/opcode/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm.h (arm_feature_set): Extended to provide more available
	* bits.
	(ARM_ANY): Updated to follow above new definition.
	(ARM_CPU_HAS_FEATURE): Likewise.
	(ARM_CPU_IS_ANY): Likewise.
	(ARM_MERGE_FEATURE_SETS): Likewise.
	(ARM_CLEAR_FEATURE): Likewise.
	(ARM_FEATURE): Likewise.
	(ARM_FEATURE_COPY): New macro.
	(ARM_FEATURE_EQUAL): Likewise.
	(ARM_FEATURE_ZERO): Likewise.
	(ARM_FEATURE_CORE_EQUAL): Likewise.
	(ARM_FEATURE_LOW): Likewise.
	(ARM_FEATURE_CORE_LOW): Likewise.
	(ARM_FEATURE_CORE_COPROC): Likewise.

opcodes/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.
2015-03-24 14:08:08 +08:00
H.J. Lu 80b8656cba Limit multi-byte nop instructions to 10 bytes
There is no performance advantage to use multi-byte nop instructions
greater than 10 bytes.  This patch limits multi-byte nop instructions
to 10 bytes.  Since there is only one way to encode multi-byte nop
instructions now, it also removed redundant nop tests.

gas/

	* config/tc-i386.c (i386_align_code): Limit multi-byte nop
	instructions to 10 bytes.

gas/testsuite/

	* gas/i386/i386.exp: Don't run nops-1-bdver1, nops-1-bdver2,
	nops-1-bdver3, nops-1-bdver4, nops-1-znver1, nops-1-btver1
	nops-1-btver2, x86-64-nops-1-nocona, x86-64-nops-1-bdver1,
	x86-64-nops-1-bdver2, x86-64-nops-1-bdver3, x86-64-nops-1-bdver4,
	x86-64-nops-1-znver1, x86-64-nops-1-btver1 nor
	x86-64-nops-1-btver2.
	* gas/i386/nops-1-core2.d: Updated.
	* gas/i386/nops-1-k8.d: Likewise.
	* gas/i386/nops-4a-i686.d: Likewise.
	* gas/i386/nops-5-i686.d: Likewise.
	* gas/i386/nops-5.d: Likewise.
	* gas/i386/nops-6.d: Likewise.
	* gas/i386/x86-64-nops-1-core2.d: Likewise.
	* gas/i386/x86-64-nops-1-g64.d: Likewise.
	* gas/i386/x86-64-nops-1-k8.d: Likewise.
	* gas/i386/x86-64-nops-1.d: Likewise.
	* gas/i386/x86-64-nops-2.d: Likewise.
	* gas/i386/x86-64-nops-3.d: Likewise.
	* gas/i386/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/x86-64-nops-4-k8.d: Likewise.
	* gas/i386/x86-64-nops-4.d: Likewise.
	* gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/x86-64-nops-5.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-3.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5.d: Likewise.
	* gas/i386/nops-1-bdver1.d: Removed.
	* gas/i386/nops-1-bdver2.d: Likewise.
	* gas/i386/nops-1-bdver3.d: Likewise.
	* gas/i386/nops-1-bdver4.d: Likewise.
	* gas/i386/nops-1-btver1.d: Likewise.
	* gas/i386/nops-1-btver2.d: Likewise.
	* gas/i386/nops-1-znver1.d: Likewise.
	* gas/i386/x86-64-nops-1-bdver1.d: Likewise.
	* gas/i386/x86-64-nops-1-bdver2.d: Likewise.
	* gas/i386/x86-64-nops-1-bdver3.d: Likewise.
	* gas/i386/x86-64-nops-1-bdver4.d: Likewise.
	* gas/i386/x86-64-nops-1-btver1.d: Likewise.
	* gas/i386/x86-64-nops-1-btver2.d: Likewise.
	* gas/i386/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/x86-64-nops-1-znver1.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
2015-03-20 04:49:39 -07:00
Nick Clifton 1740ba0cec Add support for G13 and G14 flag bits in RL78 ELF binaries.
inc	* rl78.h (E_FLAG_RL78_G10): Redefine.
	(E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13
	E_FLAG_RL78_G14): New flags.

bin	* readelf.c (get_machine_flags): Decode RL78's G13 and G14 flags.

gas	* config/tc-rl78.c (enum options): Add G13 and G14.
	(md_longopts): Add -mg13 and -mg14.
	(md_parse_option): Handle -mg13 and -mg14.
	(md_show_usage): List -mg13 and -mg14.
	* doc/c-rl78.texi: Add description of -mg13 and -mg14 options.

bfd	* elf32-rl78.c (rl78_cpu_name): New function.  Prints the name of
	the RL78 core based upon the flags.
	(rl78_elf_merge_private_bfd_data): Handle merging of G13 and G14
	flags.
	(rl78_elf_print_private_bfd_data): Use rl78_cpu_name.
	(elf32_rl78_machine): Always return bfd_mach_rl78.
2015-03-19 15:37:43 +00:00
Nick Clifton e2575e05e7 Fix building and testing dwarf debug section compression feature when zlib is not available.
PR gas/18087
gas/test	* gas/i386/dw2-compress-1.d: Allow the test to pass regardless of
	whether the .debug_info section was compressed on not.

bfd	* compress.c (bfd_compress_section_contents): Do not define this
	function if it is not used.
2015-03-19 12:14:56 +00:00
H.J. Lu d94077e27d Add a testcase for PR gas/18087
PR gas/18087
	* gas/i386/dw2-compress-1.d: Revert the last change.
	* gas/i386/dw2-compress-3.d: New.
	* gas/i386/dw2-compress-3.s: Likewise.
	* gas/i386/i386.exp: Run dw2-compress-3 for ELF targets.
2015-03-18 09:39:02 -07:00
Jon Turney 273a49858f Fix debug section compression so that it is only performed if it would make the section smaller.
PR binutils/18087
gas	* doc/as.texinfo: Note that when gas compresses debug sections the
	compression is only performed if it makes the section smaller.
	* write.c (compress_debug): Do not compress a debug section if
	doing so would make it larger.

tests	* gas/i386/dw2-compress-1.d: Do not expect the .debug_abbrev or
	.debug_info sections to be compressed.

binu	* doc/binutils.texi: Note that when objcopy compresses debug
	sections the compression is only performed if it makes the section
	smaller.

bfd	* coffgen.c (make_a_section_from_file): Only prepend a z to a
	debug section's name if the section was actually compressed.
	* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
	* compress.c (bfd_init_section_compress_status): Do not compress
	the section if doing so would make it bigger.  In such cases leave
	the section alone and return COMPRESS_SECTION_NONE.
2015-03-18 15:47:13 +00:00
Ganesh Gopalasubramanian 029f352261 Add znver1 processor 2015-03-17 21:49:15 +05:30
Nick Clifton b57dc16f06 Removes a #if 1 ... #endif accidentally left in the source code.
* dwarf2dbg.c (out_header): Remove spurious #if 1.
2015-03-16 11:17:52 +00:00
Andrew Bennett 6914869aa7 MIPS: Fix constraint issues with the R6 beqc and bnec instructions
opcodes/
	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

gas/testsuite/
	* gas/mips/mips.exp: Added branch constraints testcase.
	* gas/mips/r6-branch-constraints.s: New test.
	* gas/mips/r6-branch-constraints.l: New test.
2015-03-13 23:01:34 +00:00
Andrew Bennett 21e20815a2 Add support for MIPS R6 evp and dvp instructions.
opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

gas/testsuite/
	* gas/mips/r6.s: Add evp and dvp instructions.
	* gas/mips/r6.d: Likewise.
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.
2015-03-13 22:02:16 +00:00
Jiong Wang 4bf8c6e898 [AArch64] Don't warn on XZR/SP overlapping when it's in load/store
2015-03-13  Jiong Wang  <jiong.wang@arm.com>

gas/
   * config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg number 31.

gas/testsuite/
  * gas/aarch64/diagnostic.s: New testcases.
  * gas/aarch64/diagnostic.l: New error match.
2015-03-13 12:02:23 +00:00
Jiong Wang bc9706f823 [AArch64] Don't tail-pads sections to the alignment
2015-03-13  Jiong Wang  <jiong.wang@arm.com>

gas/
  * config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero.

gas/testsuite/
  * gas/aarch64/tail_padding.s: New testcase.
  * gas/aarch64/tail_padding.d: New expectation file.
2015-03-13 12:00:37 +00:00
Andrew Bennett 7ef0d2976a Add i6400 entry to the MIPS CPU table.
gas/

	* config/tc-mips.c (mips_cpu_info_table): Add i6400 entry.
	* doc/c-mips.texi: Document i6400 -march option.
2015-03-12 16:37:09 +00:00
Nick Clifton 93ef582deb Fixes a problem generating relocs for thumb function calls to local symbols defined in other sections.
PR gas/17444
	* config/tc-arm.h (MD_APPLY_SYM_VALUE): Pass the current segment
	to arm_apply_sym_value.  Update prototype.
	* config/tc-arm.c (arm_apply_sym_value): Add segment argument.
	Do not apply the value if the symbol is in a different segment to
	the current segment.
2015-03-12 15:58:37 +00:00
Alan Modra f728387b9a Fix powerpc gas abort on invalid instruction fixups
* config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups.
	(md_apply_fix): Report an error on data-only fixups used with insns.
2015-03-11 18:15:31 +10:30
Andreas Krebbel 6b1d7593a5 S/390: Add more IBM z13 instructions
opcodes/
2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

gas/testsuite/
2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/zarch-z13.d: Add more z13 instructions.
	* gas/s390/zarch-z13.s: Likewise.
2015-03-10 12:49:34 +01:00
Andreas Krebbel c683726541 S/390: Add check for length field operand
gas/
2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/config/tc-s390.c (md_gather_operands): Check for valid
	length field operands.
2015-03-10 12:49:34 +01:00
Michael Perkins 5e0d7f77b2 Fixes a bug in the ARM port of GAS when parsing inverted register lists.
* config/tc-arm.c (parse_operands): Fix bug setting writeback
	values for '^' on OP_REGLSTs.
	(do_push_pop): Add new writeback constraint.
2015-03-10 11:47:46 +00:00
Sterling Augustine 4e9aaefbd0 [ARM]Fix "align directive causes MAP_DATA symbol to be lost"
gas/
2015-03-10  Renlin Li  <renlin.li@arm.com>

	* config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code.
	(mapping_state_2): Emit first MAP_DATA symbol here.

gas/testsuite/
2015-03-05  Renlin Li  <renlin.li@arm.com>

	* gas/arm/dis-data.d: Adjust the desired output.
	* gas/arm/dis-data2.d: Ditto.
2015-03-10 11:34:50 +00:00
Jiong Wang c8f89a3423 [AARCH64] Remove Load/Store register (unscaled immediate) alias.
opcodes/ChangeLog:

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
         related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/testsuite/ChangeLog:

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output.
	* gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
	* gas/aarch64/reloc-insn.d: Likewise.
2015-03-10 11:27:56 +00:00
Jiong Wang a578ef7ed4 [AArch64] Set the minimum alignment on code segments
gas/
2015-03-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (mapping_state): Set minimum alignment for
	code sections.

gas/testsuite
2015-03-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/codealign.d: Add test for code section alignment.
	* gas/aarch64/codealign.s: New file.
2015-03-10 11:22:15 +00:00
Nick Clifton 73f43896e3 Fixes a bug building the ARM Linux kernel with a toolchain compiled with CPU_DEFAULT set.
PR gas/17852
	* config/tc-arm.c (md_begin): Ensure that selected_cpu is
	initialised when CPU_DEFAULT is defined.
2015-03-10 10:01:45 +00:00
Nick Clifton a26de52c63 Fixes a thinko in the implementation of the V850 -m8byte-align and -m4byte-align command line options.
* config/tc-v850.c (md_parse_option): Fix code to set or clear
	EF_RH850_DATA_ALIGN8 bit in ELF header, based upon the use of the
	-m8byte-align and -m4byte-align command line options.
2015-03-05 13:04:33 +00:00
Richard Sandiford e09ab7ac78 Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NC
bfd/
	PR gas/17843
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect
	R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	to be used with MOVK rather than MOVZ.

gas/
	PR gas/17843
	* config/tc-aarch64.c (process_movw_reloc_info): Allow
	R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	for MOVK.

gas/testsuite/
	PR gas/17843
	* gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
	R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	sequence.

ld/testsuite/
	PR gas/17843
	* ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test.
	* ld-aarch64/aarch64-elf.exp: Run it.
2015-03-04 09:09:05 +00:00
Alan Modra 9028d9432c Pad only text sections at end by default
gas/
	* write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at
	end to their alignment.
gas/testsuite/
	* gas/sparc/pcrel.d: Update for changed padding in data sections.
	* gas/sparc/pcrel64.d: Likewise.
ld/testsuite/
	* ld-sparc/gotop32.rd: Update for changed padding in data sections.
	* ld-sparc/gotop32.td: Likewise.
	* ld-sparc/gotop64.rd: Likewise.
	* ld-sparc/gotop64.td: Likewise.
	* ld-tilegx/external.s: Align .data.
	* ld-tilepro/external.s: Likewise.
2015-02-28 22:26:56 +10:30
Marcus Shawcroft 1ada945d05 [AArch64] Add support for :tlsdesc: and TLSDESC_LD_PREL19 2015-02-26 22:59:23 +00:00
Marcus Shawcroft 389b8029b6 [AArch64] Add support for :tlsdesc: and TLSDESC_ADR_PREL21 2015-02-26 22:59:16 +00:00
Marcus Shawcroft 3c12b05436 Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support. 2015-02-26 22:23:09 +00:00
Marcus Shawcroft 043bf05a3d Adding support for TLSIE_LD_GOTTREL_PREL19. 2015-02-26 22:23:09 +00:00
Marcus Shawcroft 74ad790c76 Adding ld_literal_type.
Extend the address modifier parsing to distinguish between the
modifers used in LDR literal and LDR register offset address modes.

The current parser incorrectly accepts the :got: modifier on a
register offset instruction resulting in silent corruption of the
output binary.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft 27228ca23e Adding test case for abuse of :got: in offset load
The :got: modifier is not meaningful in a register offset load store
instruction and should result in a diagnostic.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft 6f4a313ba4 Adding adr_type and prevent adr :got:
The current implementation of the :got: assembler modifier does not
distinguish the ADR and ADRP instruction.  The :got: modifier does not
make sense on and ADR instruction and should be error'd rather than
the current behavior of applying an inappropriate relocation to the
output and scrambling the underlying instruction silently.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft 3e29ed9f07 Add test case for ADR :got:foo
The modifier :got: does not make sense on an ADR instruction.  Add a
test case to ensure we gripe.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft 1db365dcdf Remove dead code. 2015-02-26 22:23:08 +00:00
Terry Guo 99654aaf36 [ARM]Update for Tag_ABI_HardFP_use per EABI doc
Updated how we merge and display this attribute per the latest
EABI documents.

bfd/ChangeLog
	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Update how we
	merge Tag_ABI_HardFP_use.

binutils/ChangeLog
	* readelf.c (arm_attr_tag_ABI_HardFP_use): Update how we
	display it.

ld/testsuite/ChangeLog
	* ld-arm/attr-merge-3.attr: Remove Tag_ABI_HardFP_use.
	* ld-arm/attr-merge-vfp-10.d: Likewise.
	* ld-arm/attr-merge-vfp-10r.d: Likewise.
	* ld-arm/attr-merge-vfp-12.d: Likewise.
	* ld-arm/attr-merge-vfp-12r.d: Likewise.
	* ld-arm/attr-merge-vfp-13.d: Likewise.
	* ld-arm/attr-merge-vfp-13r.d: Likewise.
	* ld-arm/attr-merge-vfp-14.d: Likewise.
	* ld-arm/attr-merge-vfp-14r.d: Likewise.
	* ld-arm/attr-merge-vfp-6.d: Likewise.
	* ld-arm/attr-merge-vfp-6r.d: Likewise.
	* ld-arm/attr-merge-vfp-7.d: Likewise.
	* ld-arm/attr-merge-vfp-7r.d: Likewise.
	* ld-arm/attr-merge-vfp-8.d: Likewise.
	* ld-arm/attr-merge-vfp-8r.d: Likewise.
2015-02-26 14:11:41 +08:00
Andrew Burgess 137c83d69f avr/objdump: Support dumping .avr.prop section.
Add support to objdump for dumping the .avr.prop section in a structured
way.

binutils/ChangeLog:

	* od-elf32_avr.c: Add elf32-avr.h include.
	(OPT_AVRPROP): Define.
	(options[]): Add 'avr-prop' entry.
	(elf32_avr_help): Add avr-prop help text.
	(elf32_avr_dump_avr_prop): New function.
	(elf32_avr_dump): Add check for avr-prop.

bfd/ChangeLog:

	* elf32-avr.h (struct avr_property_header): New strucure.
	(avr_elf32_load_property_records): Declare.
	(avr_elf32_property_record_name): Declare.
	* elf32-avr.c: Add bfd_stdint.h include.
	(retrieve_local_syms): New function.
	(get_elf_r_symndx_section): New function.
	(get_elf_r_symndx_offset): New function.
	(internal_reloc_compare): New function.
	(struct avr_find_section_data): New structure.
	(avr_is_section_for_address): New function.
	(avr_find_section_for_address): New function.
	(avr_elf32_load_records_from_section): New function.
	(avr_elf32_load_property_records): New function.
	(avr_elf32_property_record_name): New function.

gas/testsuite/ChangeLog:

	* gas/avr/avr-prop-1.d: New file.
	* gas/avr/avr-prop-1.s: New file.
2015-02-25 23:17:27 +00:00
Andrew Burgess fdd410ac7a avr/gas: Write out data to track .org/.align usage.
Adds support to the assembler to write out data for tracking the use of
.org and .align directives.  This data is collected within the assembler
and written out to a section ".avr.prop" (if there's anything to write
out).

This patch does not add any tests.  The next patch in this series will
add a better mechanism for visualising the contents of .avr.prop which
will make writing tests much easier.

This patch also does not make any use of this collected data, that will
also come along in a later patch; the intended consumer is the linker,
during linker relaxation this information will be used to ensure that
the .org and .align directives are honoured.

bfd/ChangeLog:

	* elf32-avr.h (AVR_PROPERTY_RECORD_SECTION_NAME): Define.
	(AVR_PROPERTY_RECORDS_VERSION): Define.
	(AVR_PROPERTY_SECTION_HEADER_SIZE): Define.
	(struct avr_property_record): New structure.

gas/ChangeLog:

	* config/tc-avr.c: Add elf32-avr.h include.
	(struct avr_property_record_link): New structure.
	(avr_output_property_section_header): New function.
	(avr_record_size): New function.
	(avr_output_property_record): New function.
	(avr_create_property_section): New function.
	(avr_handle_align): New function.
	(exclude_section_from_property_tables): New function.
	(create_record_for_frag): New function.
	(append_records_for_section): New function.
	(avr_create_and_fill_property_section): New function.
	(avr_post_relax_hook): New function.
	* config/tc-avr.h (md_post_relax_hook): Define.
	(avr_post_relax_hook): Declare.
	(HANDLE_ALIGN): Define.
	(avr_handle_align): Declare.
	(strut avr_frag_data): New structure.
	(TC_FRAG_TYPE): Define.
2015-02-25 23:15:02 +00:00
Oleg Endo ac99436572 [SH] Fix clrs, sets, pref insn arch memberships.
opcodes/
	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

gas/testsuite/
	* gas/sh/arch/arch.exp: Replace dead code to generate expected .s files
	with ...
	* gas/sh/arch/sh-opc-gen-as.pl: ... this new script.
	* gas/sh/arch/arch_expected.txt: Regenerate.
	* gas/sh/arch/sh-dsp.s: Likewise.
	* gas/sh/arch/sh-opc-gen-as.pl: Likewise.
	* gas/sh/arch/sh.s: Likewise.
	* gas/sh/arch/sh2.s: Likewise.
	* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise.
	* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise.
	* gas/sh/arch/sh2a-nofpu.s: Likewise.
	* gas/sh/arch/sh2a-or-sh3e.s: Likewise.
	* gas/sh/arch/sh2a-or-sh4.s: Likewise.
	* gas/sh/arch/sh2a.s: Likewise.
	* gas/sh/arch/sh2e.s: Likewise.
	* gas/sh/arch/sh3-dsp.s: Likewise.
	* gas/sh/arch/sh3-nommu.s: Likewise.
	* gas/sh/arch/sh3.s: Likewise.
	* gas/sh/arch/sh3e.s: Likewise.
	* gas/sh/arch/sh4-nofpu.s: Likewise.
	* gas/sh/arch/sh4-nommu-nofpu.s: Likewise.
	* gas/sh/arch/sh4.s: Likewise.
	* gas/sh/arch/sh4a-nofpu.s: Likewise.
	* gas/sh/arch/sh4a.s: Likewise.
	* gas/sh/arch/sh4al-dsp.s: Likewise.

ld/testsuite/
	* ld-sh/arch/arch_expected.txt: Regenerate.
	* ld-sh/arch/sh-dsp.s: Likewise.
	* ld-sh/arch/sh.s: Likewise.
	* ld-sh/arch/sh2.s: Likewise.
	* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise.
	* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise.
	* ld-sh/arch/sh2a-nofpu.s: Likewise.
	* ld-sh/arch/sh2a-or-sh3e.s: Likewise.
	* ld-sh/arch/sh2a-or-sh4.s: Likewise.
	* ld-sh/arch/sh2a.s: Likewise.
	* ld-sh/arch/sh2e.s: Likewise.
	* ld-sh/arch/sh3-dsp.s: Likewise.
	* ld-sh/arch/sh3-nommu.s: Likewise.
	* ld-sh/arch/sh3.s: Likewise.
	* ld-sh/arch/sh3e.s: Likewise.
	* ld-sh/arch/sh4-nofpu.s: Likewise.
	* ld-sh/arch/sh4-nommu-nofpu.s: Likewise.
	* ld-sh/arch/sh4.s: Likewise.
	* ld-sh/arch/sh4a-nofpu.s: Likewise.
	* ld-sh/arch/sh4a.s: Likewise.
	* ld-sh/arch/sh4al-dsp.s: Likewise.
2015-02-25 21:26:59 +01:00
Kyrylo Tkachov 4469186b99 [gas][ARM] Document supported ARMv8 cores.
2015-02-25  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/c-arm.texi (-mcpu=): Add cortex-a53, cortex-a57 and
	cortex-a72.
2015-02-25 13:40:08 +00:00
Nick Clifton 685080f210 Adds support for generating notes in V850 binaries.
bfd	* elf32-v850.c (v850_set_note): New function.  Creates a Renesas
	style note entry.
	(v850_elf_make_note_section): New function.  Creates a note
	section.
	(v850_elf_create_sections): New function.  Create a note section
	if one is not already present.
	(v850_elf_set_note): New function.  Adds a note to a bfd.
	(v850_elf_copy_private_bfd_data): New function.  Copies V850
	notes.
	(v850_elf_merge_notes): New function.  Merges V850 notes.
	(print_v850_note): New function.  Displays a V850 note.
	(v850_elf_print_notes): New function. Displays all notes attached
	to a bfd.
	(v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes.
	(v850_elf_print_private_bfd_data): Call v850_elf_print_notes.
	(v850_elf_fake_sections): Set the type of the V850 note section.
	* bfd-in.h (v850_elf_create_sections): Add prototype.
	(v850_elf_set_note): Add prototype.
	* bfd-in2.h: Regenerate.

binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine
	flags.
	(get_v850_section_type_name): New function.  Handles V850 special
	sections.
	(get_section_type_name): Add support for V850.
	(get_v850_elf_note_type): New function.  Returns the name of a
	V850 note.
	(print_v850_note): New function.  Prints a V850 note.
	(process_v850_notes): New function.  Prints V850 notes.
	(process_note_sections): Add support for V850.

binutils/testsute
	* binutils-all/objcopy.exp: Skip the strip-10 test for the V850.

gas	* config/tc-v850.c (soft_float): New variable.
	(v850_data_8): New variable.
	(md_show_usage): Add -msoft-float/-mhard-float.
	(md_parse_option): Likewise.
	(md_begin): Set the default value of soft_float.
	(v850_md_end): New function.  Creates a note section.
	* config/tc-v850.h (md_end): Define.
	* doc/c-v850.texi: Document -msoft-float/-mhard-float.

gas/testsuite
	* gas/elf/elf.exp: Add special version of the section2 test for
	the V850.
	* gas/elf/section2.e-v850: New file.

include/elf
	* v850.h (EF_RH850_SIMD): Delete deprecated flag.
	(EF_RH850_CACHE): Likewise.
	(EF_RH850_MMU): Likewise.
	(EF_RH850_DATA_ALIGN8): Likewise.
	(SHT_RENESAS_IOP): Fix typo in name.
	(SHT_RENESAS_INFO): Define.
	(V850_NOTE_SECNAME): Define.
	(SIZEOF_V850_NOTE): Define.
	(V850_NOTE_NAME): Define.
	(enum v850_notes): New enum.
	(NUM_V850_NOTES): Define.

ld/ChangeLog
2015-02-24  Nick Clifton  <nickc@redhat.com>

	* Makefile.am (ev850.c): Add dependency upon
	$(srcdir)/emultempl/v850elf.em.
	(ev850_rh850.c): Likewise.
	* Makefile.in: Regenerate.
	* emultempl/v850elf.em: New file.
	* emulparams/v850.sh (EXTRA_EM_FILE): Define.
	* emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define.
	* scripttempl/v850.sc: Add .note.renesas section.
	* scripttempl/v850_rh850.sc: Likewise.

ld/testsuite
	* ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
2015-02-24 17:54:09 +00:00
Yoshinori Sato 5518c738a4 Add support for the h8300-linux target.
ld	* Makefile.am: (ALL_EMULATION_SOURCES): Add new emulations.
	* Makefile.in: Regenerate.
	* configure.tgt: Add h8300-*-linux
	* emulparams/h8300elf_linux.sh: Add new emulation.
	* emulparams/h8300helf_linux.sh: Likewise.
	* emulparams/h8300self_linux.sh: Likewise.
	* emulparams/h8300sxelf_linux.sh: Likewise.

bfd	* config.bfd: Add h8300-*-linux.
	* configure.ac: Add h8300_elf32_linux_vec.
	* configure: Regenerate.
	* elf32-h8300.c: Likewise.
	* targets.c(_bfd_target_vector): Likewise.

gas	* config/tc-h8300.c (line_separater_chars): Add a version for
	h8300-linux that includes a separator.
	(default_mach): New variable.
	(md_main): Use it.
	(md_longopts): Add '--march' option.
	(md_parse_option): Parse the new option.
	* config/tc-h8300.h (TARGET_FORMAT): Add elf32-h8300-linux.
	* configure.tgt: Add h8300-*-linux
	* doc/c-h8300.texi: Document --march.
2015-02-23 17:04:53 +00:00
Nick Clifton 0f8f0c57ea Fixes the generation of dwarf line debug information for the msp430, even in the presence of function sections and linker garbage collection.
PR 17940
	* dwarf2dbg.c (out_header): When generating dwarf sections use
	real symbols not temps for the start and end symbols.
	* config/tc-msp430.h (TC_FORCE_RELOCATION_SUB_SAME): Also prevent
	adjustments to relocations in debug sections.
	(TC_LINKRELAX_FIXUP): Likewise.

	* elf32-msp430.c (msp430_elf_relax_delete_bytes): Adjust debug
	symbols at end of sections.  Adjust function sizes.
2015-02-23 14:53:02 +00:00
Alan Modra 5c9352f317 gas doc warning fixes
* doc/as.texinfo (Local Symbol Names): Don't use ':' in pxref.
	* doc/c-i386.texi: Reorder i386-Bugs after i386-Arch.
2015-02-19 14:14:51 +10:30
Jiong Wang aa31c464df [AArch64] Fix code formatting in the cpu-table
2015-02-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
2015-02-11 14:35:27 +00:00
Jiong Wang b19f47add0 [ARM] Add support for Cortex-A72
2015-02-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c: Add support for Cortex-A72.
2015-02-11 10:54:50 +00:00
Kyrylo Tkachov 5c3696f89f [ARM][gas] Use as_tsktsk instead of as_warn for deprecation messages.
* config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead
	of as_warn for deprecation messages.
	(encode_arm_addr_mode_2): Likewise.
	(check_obsolete): Likewise.
	(do_rd_rm_rn): Likewise.
	(do_co_reg): Likewise.
	(do_setend): Likewise.
	(do_t_mov_cmp): Likewise.
	(do_neon_ldr_str): Likewise.
	(opcode_lookup): Likewise.
	(if_fsm_post_encode): Likewise.
	(md_assemble): Likewise.

	* gas/arm/armv1.l: Remove 'Warning: ' from expected messages
	for deprecations.
	* gas/arm/armv8-a-bad.l: Likewise.
	* gas/arm/armv8-a-it-bad.l: Likewise.
	* gas/arm/depr-swp.l: Likewise.
	* gas/arm/ldsgeb.l: Likewise.
	* gas/arm/ldsgeh.l: Likewise.
	* gas/arm/thumb2_bad_reg.l: Likewise.
	* gas/arm/thumb32.l: Likewise.
	* gas/arm/udf.l: Likewise.
	* gas/arm/vstr-arm-bad.l: Likewise.
2015-02-09 11:20:30 +00:00