gas/testsuite/
PR binutils/13571
* gas/i386/i386.exp: Run i386-intel and x86_64-intel.
* gas/i386/i386-intel.d: New file.
* gas/i386/x86_64-intel.d: Likewise.
opcodes/
PR binutils/13571
* i386-dis.c (MOD_0FC3): New.
(PREFIX_0FC3): Renamed to ...
(PREFIX_MOD_0_0FC3): This.
(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
(prefix_table): Replace Ma with Ev on movntiS.
(mod_table): Add MOD_0FC3.
gas * config/tc-rl78.c (rl78_abs_sym): New local variable.
(md_begin): Initialise the new symbol.
(OPIMM): Define the value to be relative to the new symbol and not
the absolute section symbol.
ld * emulparams/elf32rl78.sh (OTHER_SECTIONS): Provide a value for
the _-rl78_abs__ symbol.
tests * gas/all/struct.d: Allow for extra symbols in the output.
* gas/macros/test1.d: Likewise.
* gas/elf/elf.exp: Add an rl78 machine.
* gas/elf/sections2e-rl78: New file.
tests * binutils-all/localize-hidden-1.d: Allow for extra symbols in the
output.
* binutils-all/strip-11.d: Skip for the RL78.
This fixes a segfault when macro definitions end on the last line of a
file, and that line isn't properly terminated with a newline. gas
used to throw away the last line in cases like this, whereas in other
cases gas added the missing newline. So I've also made gas
consistently provide a missing newline.
PR gas/18687
* input-scrub.c (input_scrub_next_buffer): Rearrange and simplify
loop. Don't drop lines at end of file lacking a newline, add a
newline instead. Ensure partial_size is zero whenever
partial_where is NULL. Adjust buffer size for extra char.
(input_scrub_push, input_scrub_begin): Adjust buffer size here too.
We used to generate abort messages like:
internal error, aborting at .../bfd/elf64-x86-64.c line 1554 in elf_x86_64_check_relocs
We can't cut and paste "file line ???" to GDB. This patch changes those
abort messages to
internal error, aborting at .../bfd/elf64-x86-64.c:1554 in elf_x86_64_check_relocs
so that we can cut and paste "file:???" to GDB.
bfd/
* bfd.c (_bfd_abort): Replace " line " with ":" in output
message.
gas/
* messages.c (as_assert): Replace " line " with ":" in output
message.
(as_abort): Likewise.
ld/
* ldmisc.c (ld_abort): Replace " line " with ":" in output
message.
opcodes * arm-dis.c (print_insn_coprocessor): Added support for quarter
float bitfield format.
(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
quarter float bitfield format.
tests * gas/arm/vfpv3-const-conv.d: Update expected result due to change
of comment for vmov reg,immediate with VFP coprocessor.
The default compression is gABI compliant now. This patch makes the
x86 Linux assembler default to gABI compliant.
* config/tc-i386.c (flag_compress_debug): Replace
COMPRESS_DEBUG_GNU_ZLIB with COMPRESS_DEBUG_GABI_ZLIB.
All programs in binutils+gdb git repo now support gABI compression
with the SHF_COMPRESSED bit. This patch makes the zlib-gabi option
as compression default for gas, gold, ld and objcopy, instead of the
zlib-gnu option whose outputs are incompatible with gABI.
binutils/
* objcopy.c (copy_file): Set BFD_COMPRESS_GABI if not
zlib-gnu.
* doc/binutils.texi: Change --compress-debug-sections and
--compress-debug-sections=zlib to zlib-gabi.
binutils/testsuite/
* binutils-all/compress.exp: Update.
gas/
* as.c (parse_args): Make --compress-debug-sections and
--compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* doc/as.texinfo: Change --compress-debug-sections and
--compress-debug-sections=zlib to zlib-gabi.
gold/
* compressed_output.cc (Output_compressed_section::set_final_data_size):
Make --compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* testsuite/Makefile.am (flagstest_compress_debug_sections.check):
Expect ".debug_.*" with the SHF_COMPRESSED bit, instead of
".zdebug_".
* testsuite/Makefile.in: Regenerated.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Make
--compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* ld.texinfo: Change --compress-debug-sections=zlib to zlib-gabi.
ld/testsuite/
* ld-elf/zlibbegin.rS: Updated to .debug_.* with the
SHF_COMPRESSED bit.
* ld-elf/zlibnormal.rS: Likewise.
When generating relocation (tc_gen_reloc) 32 bit relocation fixup
is changed to new 32 bit PC relative relocation if the fixup has pc-relative
flag set.
bfd/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf32-avr.c: Add 32 bit PC relative relocation for AVR target.
gas/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
32 bit PC relative and update offset if the fixup is pc-relative.
* config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
relocs.
gas/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* gas/avr/pc-relative-reloc.d: New test for 32 bit pc relative reloc.
* gas/avr/per-function-debugline.s: New test source.
include/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf/avr.h: Add new 32 bit PC relative relocation.
ld/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* ld-avr/gc-section-debugline.d: New test.
* ld-avr/per-function-debugline.s: Source for new test.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
This patch uses ELF strtab with GC and suffix merging support to create
ELF .strtab section. There is some small memory overhead to use ELF
strtab:
==14928== HEAP SUMMARY:
==14928== in use at exit: 3,276,318 bytes in 679 blocks
==14928== total heap usage: 1,544 allocs, 865 frees, 15,259,146 bytes allocated
vs.
==14936== HEAP SUMMARY:
==14936== in use at exit: 3,276,318 bytes in 679 blocks
==14936== total heap usage: 1,532 allocs, 853 frees, 15,026,402 bytes allocated
when running:
./ld-new -m elf_x86_64 -o tmpdir/ld-partial.o -r ldgram.o ldlex-wrapper.o lexsup.o ldlang.o mri.o ldctor.o ldmain.o plugin.o ldwrite.o ldexp.o ldemul.o ldver.o ldmisc.o ldfile.o ldcref.o eelf_x86_64.o eelf32_x86_64.o eelf_i386.o eelf_iamcu.o ei386linux.o eelf_l1om.o eelf_k1om.o ldbuildid.o
The results are
[32] .strtab STRTAB 0+ 3beff8 00407a 00 0 0 1
vs
[32] .strtab STRTAB 0+ 3beff8 0041d8 00 0 0 1
It reduces the .strtab size by 350 bytes, about 2%
Saving on libc.so from glibc is much more since libc.so has many alias
symbols with the same suffix. For x32 glibc,
[82] .strtab STRTAB 0+ 81b348 0159e7 00 0 0 1
vs
[82] .strtab STRTAB 0+ 81b8bc 019e72 00 0 0 1
It reduces the .strtab size by 17547 bytes, about 16%.
bfd/
PR gas/18451
* elf-bfd.h (elf_sym_strtab): New.
(elf_link_hash_table): Add strtabcount, strtabsize and
strtab.
(_bfd_elf_stringtab_init): Removed.
* elf.c (_bfd_elf_stringtab_init): Removed.
(_bfd_elf_compute_section_file_positions): Replace
bfd_strtab_hash/_bfd_elf_stringtab_init/_bfd_stringtab_free/
_bfd_stringtab_size with
elf_strtab_hash/_bfd_elf_strtab_init/_bfd_elf_strtab_free/
_bfd_elf_strtab_size. Use _bfd_elf_strtab_add,
_bfd_elf_strtab_finalize and _bfd_elf_strtab_offset to get
st_name.
(swap_out_syms): Likewise.
* elflink.c (elf_final_link_info): Replace bfd_strtab_hash
with elf_strtab_hash. Remove symbuf, symbuf_count,
symbuf_size and shndxbuf_size.
(elf_link_flush_output_syms): Removed.
(elf_link_output_sym): Renamed to ...
(elf_link_output_symstrtab): This. Replace _bfd_stringtab_add
with _bfd_elf_strtab_add. Don't flush symbols to the file nor
swap out symbols.
(elf_link_swap_symbols_out): New.
(elf_link_output_extsym): Replace elf_link_output_sym with
elf_link_output_symstrtab.
(elf_link_input_bfd): Likewise.
(elf_final_link_free): Replace _bfd_stringtab_free with
_bfd_elf_strtab_free. Remove symbuf.
(bfd_elf_final_link): Replace _bfd_elf_stringtab_init with
_bfd_elf_strtab_init. Don't set symbuf, symbuf_count,
symbuf_size nor shndxbuf_size. Initialize strtabsize and
strtab. Initialize symshndxbuf to -1 when number of sections
>= 64K. Replace elf_link_output_sym/elf_link_output_sym with
elf_link_output_symstrtab/elf_link_output_symstrtab. Don't
call elf_link_flush_output_syms. Call _bfd_elf_strtab_finalize
and elf_link_swap_symbols_out. Replace _bfd_stringtab_size
and _bfd_stringtab_emit with _bfd_elf_strtab_size and
_bfd_elf_strtab_emit.
gas/testsuite/
PR gas/18451
* gas/elf/elf.exp: Run strtab.
* gas/elf/strtab.d: New file.
* gas/elf/strtab.s: Likewise.
ld/testsuite/
PR gas/18451
* ld-elf/strtab.d: New file.
* ld-elf/strtab.s: Likewise.
Commit 2f0c68f23b added an extra @section
.cfi_lsda:
@subsection @code{.cfi_lsda @var{encoding} [, @var{exp}]}
+@section @code{.cfi_lsda @var{encoding} [, @var{exp}]}
@code{.cfi_lsda} defines LSDA and its encoding.
It shouldn't be there.
* doc/as.texinfo (.cfi_lsda): Remove the extra @section.
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC. Edmar added
support for this insruction varient here:
https://sourceware.org/ml/binutils/2012-02/msg00221.html
Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC. This patch changes the assembler to
error out on invalid and incompatible operand usage.
opcodes/
* ppc-opc.c (insert_ls): Test for invalid LS operands.
(insert_esync): New function.
(LS, WC): Use insert_ls.
(ESYNC): Use insert_esync.
gas/testsuite/
* gas/ppc/e6500.s <sync>: Fix invalid test.
* gas/ppc/e6500.d: Likewise.
include * dis-asm.h (struct disassemble_info): Add stop_vma field.
binuti * objdump.c (disassemble_bytes): Set the stop_vma field in the
disassemble_info structure when disassembling code sections with
-d.
* doc/binutils.texi (objdump): Document the discrepancy between -d
and -D.
opcodes * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
requested region lies beyond it.
* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
looking for 32-bit insns.
* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
data.
* sh-dis.c (print_insn_sh): Likewise.
* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
blocks of instructions.
* vax-dis.c (print_insn_vax): Check that the requested address
does not clash with the stop_vma.
tests * gas/arm/backslash-at.s: Add extra .byte directives so that the
foo symbol does not appear to point half way through an
instruction.
* gas/arm/backslash-at.d: Update expected disassembly.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
PR gas/18541
gas * config/tc-arm.c (md_apply_fix): Add support for ADR in thumb
mode against a nearby symbol.
tests * gas/arm/thumb.s: Add test of ADR against a nearby symbol.
* gas/arm/thumb.d: Update expected output.
* gas/arm/thumb-eabi.d: Likewise.
PR gas/18481
bfd * elf32-arm.c (R_ARM_TLS_LE32): Set the special function to NULL.
gas * config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32
in the same case as BFD_RELOC_ARM_TLS_IS32.
tests * gas/arm/tls.s: Add tests of the tpoff pseudo with a local
symbol.
* gas/arm/tls.d: Update expected output.
* config/tc-arm.c (is_double_a_single): Make conditional upon the
availablity of a 64-bit type. Use this type for the argument and
mantissa.
(double_to_single): Likewise.
* config/tc-arm.c (move_or_literal_pool): Use a 64-bit type for
the constant value, if available. Generate a 64-bit value from a
bignum if supported. Only perform the second optimization for
PR 18500 if the 64-bit type is available.
PR gas/18499
gas * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
to MOV.w or MVN.w for Thumb2.
tests * gas/arm/thumb2_ldr_immediate_armv6.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly.
* gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
PR gas/18500
gas * config/tc-arm.c (is_double_a_single): New function.
(double_to_single): New function.
(move_or_literal_pool): Add support for converting VLDR to VMOV.
tests * gas/arm/vfpv2-ldr_immediate.s: New test case.
* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3-ldr_immediate.s: New test case.
* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
This patch adds the ability to automatically construct a section name
based on the prior section.
When gas is invoked with --sectname-subst, the occurrence of %S in a
section name will be substituted by the name of the current section. For
example:
.macro exception_code
.pushsection %S.exception
[exception code here]
.popsection
.endm
.text
[code]
exception_code
[...]
.section .init
[init code]
exception_code
[...]
The first and second exception_code invocations create the
.text.exception and the .init.exception sections respectively. This is
useful e.g. to discriminate between anciliary sections that are tied to
.init code and can be discarded at run time when initialization is over
vs anciliary sections tied to .text sections that need to stay resident.
* as.c (show_usage): Document --sectname-subst.
(parse_args): Add --sectname-subst.
* as.h (flag_sectname_subst): New.
* config/obj-elf.c (obj_elf_section_name): Add %S substitution.
* doc/as.texinfo: Document it.
out_debug_aranges uses frag_align to make sure the addresses start
out aligned. Using frag_align will call frag_var[_init], which will
end up calling TC_FRAG_INIT. On arm and aarch64 TC_FRAG_INIT will
generate a $d mapping symbol for the .debug_aranges to show that at
that point a sequence of data items starts.
Such a symbol pointing into a non-allocated debug section will confuse
eu-strip -g. And it seems inefficient and wrong in general to have
additional mapping symbols for debug sections, which won't contain
actual code in the first place.
Just keep track of the aranges header size and use plain padding to
align the addresses which avoids generating any mapping symbols on
aarch64 and arm.
Includes a testcase for aarch64 that PASS with this patch and shows
the extra $d mapping symbol in .debug_aranges before.
gas/ChangeLog
* dwarf2dbg.c (out_header): Document EXPR->X_add_number value,
out_debug_aranges depends on it.
(out_debug_aranges): Track size of header to properly pad header
for address alignment.
gas/testsuite/ChangeLog
* gas/aarch64/dwarf.d: New.
* gas/aarch64/dwarf.s: New.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.
opcodes/
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
gas/testsuite/
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
* gas/ppc/power4.d: Likewise.
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Swap rounding mode specifier and
general purpose register in Intel mode.
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
When --text-section-literals is used and code in the .init or .fini
emits literal in the absence of .literal_position, xtensa_move_literals
segfaults.
Check that search_frag is non-NULL in the xtensa_move_literals and
report error otherwise.
2015-05-26 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_move_literals): Check that
search_frag is non-NULL. Report error if literal frag is not
found.
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode. AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.
This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive
ISA, which is AMD64, is the default.
GDB can add an option, similar to
(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".
to select which ISA to disassemble.
binutils/
PR binutis/18386
* doc/binutils.texi: Document -Mamd64 and -Mintel64.
gas/
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
objdump for tlspic.dd and tlsgdesc.dd.
opcodes/
PR binutis/18386
* i386-dis.c: Add comments for '@'.
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
(enum x86_64_isa): New.
(isa64): Likewise.
(print_i386_disassembler_options): Add amd64 and intel64.
(print_insn): Handle amd64 and intel64.
(putop): Handle '@'.
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
* i386-opc.h (AMD64): New.
(CpuIntel64): Likewise.
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
This patch adds -mshared option to x86 ELF assembler. By default,
assembler will optimize out non-PLT relocations against defined non-weak
global branch targets with default visibility. The -mshared option tells
the assembler to generate code which may go into a shared library
where all non-weak global branch targets with default visibility can
be preempted. The resulting code is slightly bigger. This option
only affects the handling of branch instructions.
This Linux kernel patch is needed to create a working x86 Linux kernel if
it hasn't been applied:
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ae6588b..b91a00c 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -339,8 +339,8 @@ early_idt_handlers:
i = i + 1
.endr
-/* This is global to keep gas from relaxing the jumps */
-ENTRY(early_idt_handler)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(early_idt_handler)
cld
cmpl $2,(%rsp) # X86_TRAP_NMI
--
gas/
* config/tc-i386.c (shared): New.
(OPTION_MSHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Add relocation argument.
Check PLT relocations and shared.
(md_estimate_size_before_relax): Pass fragP->fr_var to
elf_symbol_resolved_in_segment_p.
(md_longopts): Add -mshared.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MSHARED.
* doc/c-i386.texi: Document -mshared.
gas/testsuite/
* gas/i386/i386.exp: Don't run pcrel for ELF targets. Run
pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
* gas/i386/pcrel-elf.d: New file.
* gas/i386/relax-4.d: Likewise.
* gas/i386/x86-64-relax-3.d: Likewise.
* gas/i386/relax-3.d: Pass -mshared to assembler. Updated.
* gas/i386/x86-64-relax-2.d: Likewise.
* gas/i386/relax-3.s: Add test for PLT relocation.
Remove the wait instructions for server processors, since they were never
implemented. Also add the extra operands added to the tlbie and slbia
instructions with ISA 2.06 and ISA 2.05 respectively.
binutils/
* MAINTAINERS: Add myself as PPC maintainer.
opcodes/
* ppc-opc.c (IH) New define.
(powerpc_opcodes) <wait>: Do not enable for POWER7.
<tlbie>: Add RS operand for POWER7.
<slbia>: Add IH operand for POWER6.
gas/testsuite/
* gas/ppc/power4.d: Add a slbia test.
* gas/ppc/power4.s: Likewise.
* gas/ppc/power6.d: Add slbia and tlbie tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
* gas/ppc/power7.s: Likewise.
In a SHF_COMPRESSED compressed section, the raw compressed data should
begin immediately after the compression header. This patch removes the
extra zlib header from the SHF_COMPRESSED section.
bfd/
* bfd.c (bfd_update_compression_header): Also write the zlib
header if the SHF_COMPRESSED bit cleared..
(bfd_check_compression_header): Return the uncompressed size.
* compress.c (decompress_contents): Don't skip the zlib header.
(bfd_compress_section_contents): Properly handle ELFCOMPRESS_ZLIB,
which doesn't have the zlib header.
(bfd_init_section_decompress_status): Likewise.
(bfd_get_full_section_contents): Updated.
(bfd_is_section_compressed): Likewise.
(bfd_is_section_compressed_with_header): Return the uncompressed
size.
* elf.c (_bfd_elf_make_section_from_shdr): Updated.
* bfd-in2.h: Regenerated.
binutils/
* readelf.c (uncompress_section_contents): Add a parameter for
uncompressed size. Don't check the zlib header.
(load_specific_debug_section): Updated.
binutils/testsuite/
* binutils-all/compress.exp: Replace "$OBJDUMP -s -j .debug_info"
with "$OBJDUMP -W".
* binutils-all/libdw2-compressedgabi.out: Updated.
gas/
2015-05-14 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Don't write the zlib header, which
is handled by bfd_update_compression_header.
Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline
selection results in regressions: when relaxable jump is little longer
than J_RANGE so that single trampoline makes two new jumps, one longer
than J_RANGE / 2 and one shorter, correct trampoline cannot be found.
Drop that condition.
2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
closer than J_RANGE / 2 to jump frag.
gas/testsuite/
* gas/xtensa/trampoline.s: Add regression testcase.
This patch sets the default ELF output format of assembler and linker to
EM_IAMCU when binutils is configured to i?86-*-elfiamcu target.
gas/
* configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target.
* config/tc-i386.c (i386_mach): Support iamcu.
(i386_target_format): Likewise.
ld/
* configure.tgt: Support i[3-7]86-*-elfiamcu target.
ld/testsuite/
* ld-i386/i386.exp (iamcu_tests): Run iamcu-4.
* ld-i386/iamcu-4.d: New file.
PR gas/18347
* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
* config/tc-arm.c (arm_tc_equal_in_insn): New function. Move
the symbol name checking code to here from...
(md_undefined_symbo): ... here.
On ELF target, the assembler normally generates code which can go into a
shared library where non-weak symbols can be preempted. The -mno-shared
option tells the assembler to generate code not for a shared library,
where non-weak symbols won't be preempted. The resulting code is slightly
smaller. This option mainly affects the handling of branch instructions.
gas/
* config/tc-i386.c (no_shared): New.
(OPTION_MNO_SHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Check no_shared.
(md_longopts): Add mno-shared.
(md_parse_option): Handle OPTION_MNO_SHARED.
(md_show_usage): Add -mno-shared.
* doc/c-i386.texi: Document -mno-shared.
gas/testsuite/
* gas/i386/i386.exp: Run relax-4 and x86-64-relax-3.
* gas/i386/relax-4.d: New file.
* gas/i386/x86-64-relax-3.d: Likewise.
Branches to global non-weak symbols defined in the same segment with
non-default visibility can be optimized the same way as branches to
local symbols.
gas/
* config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
(md_estimate_size_before_relax): Use it.
gas/testsuite/
* gas/i386/i386.exp: Run relax-3 and x86-64-relax-2.
* gas/i386/relax-3.d: New file.
* gas/i386/relax-3.s: Likewise.
* gas/i386/x86-64-relax-2.d: Likewise.
gas/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
condition codes
* doc/c-sparc.texi (Sparc-Regs): Document %ncc.
gas/testsuite/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural.s: New file.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.d: Likewise.
* gas/sparc/natural-32.d: Likewise.
* gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and
natural-32.
gas * config/tc-msp430.c (MAX_OP_LEN): Increase to 4096.
(msp430_make_init_symbols): New function.
(msp430_section): Call it.
(msp430_frob_section): Likewise.
ld * emulparams/msp430elf.sh (TEMPLATE_NAME): Change to msp430.
* scripttempl/msp430.sc (.text): Add .lower.text and .either.text.
(.data): Add .lower.data and .either.data.
(.bss): Add .lower.bss and .either.bss.
(.rodata): Add .lower.rodata and .either.rodata.
* emultempl/msp430.em: New file. Implements a new orphan
placement algorithm that divides sections between lower and upper
memory regions.
* Makefile.am (emsp430elf.c): Depend upon msp430.em.
*emsp430X.c): Likewise.
* Makefine.in: Regenerate.
Currently every fixup in the current segment is checked when relaxing
trampoline frag. This is very expensive. Make a searchable array of
fixups pointing at potentially oversized jumps at the beginning of every
relaxation pass and only check subset of this cache in the reach of
single jump from the trampoline frag currently being relaxed.
Original profile:
% time self children called name
-----------------------------------------
370.16 593.38 12283048/12283048 relax_segment
98.4 370.16 593.38 12283048 xtensa_relax_frag
58.91 269.26 2691463834/2699602236 xtensa_insnbuf_from_chars
68.35 68.17 811266668/813338977 S_GET_VALUE
36.85 29.51 2684369246/2685538060 xtensa_opcode_decode
28.34 8.84 2684369246/2685538060 xtensa_format_get_slot
12.39 5.94 2691463834/2699775044 xtensa_format_decode
0.03 4.60 4101109/4101109 relax_frag_for_align
0.18 1.76 994617/994617 relax_frag_immed
0.07 0.09 24556277/24851220 new_logical_line
0.06 0.00 12283048/14067410 as_where
0.04 0.00 7094588/15460506 xtensa_format_num_slots
0.00 0.00 1/712477 xtensa_insnbuf_alloc
-----------------------------------------
Same data, after optimization:
% time self children called name
-----------------------------------------
0.51 7.47 12283048/12283048 relax_segment
58.0 0.51 7.47 12283048 xtensa_relax_frag
0.02 4.08 4101109/4101109 relax_frag_for_align
0.18 1.39 994617/994617 relax_frag_immed
0.01 0.98 555/555 xtensa_cache_relaxable_fixups
0.21 0.25 7094588/16693271 xtensa_insnbuf_from_chars
0.06 0.12 24556277/24851220 new_logical_line
0.06 0.00 7094588/15460506 xtensa_format_num_slots
0.02 0.04 7094588/16866079 xtensa_format_decode
0.05 0.00 12283048/14067410 as_where
0.00 0.00 1/712477 xtensa_insnbuf_alloc
0.00 0.00 93808/93808 xtensa_find_first_cached_fixup
-----------------------------------------
2015-05-02 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs.
(struct cached_fixup, struct fixup_cache): New structures.
(fixup_order, xtensa_make_cached_fixup),
(xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups),
(xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup),
(xtensa_add_cached_fixup): New functions.
(xtensa_relax_frag): Cache fixups pointing at potentially
oversized jumps at the beginning of every relaxation pass. Only
check subset of this cache in the reach of single jump from the
trampoline frag currently being relaxed.
This x86 assembler patch:
https://sourceware.org/ml/binutils/2001-11/msg00344.html
generates a .note section for .arch directive so that GDB can tell which
architecture an i386 binary belongs:
https://sourceware.org/ml/binutils/2001-11/msg00271.html
However, x86 assembly code can have any instructions. A .note section
doesn't help. This patch removes it.
gas/
* config/tc-i386.c (i386_elf_emit_arch_note): Removed.
* config/tc-i386.h (md_end): Likewise.
(i386_elf_emit_arch_note): Likewise.
gas/testsuite/
* gas/i386/i386.exp: Run note.
* gas/i386/note.d: New file.
* gas/i386/note.s: Likewise.
PR gas/18347
gas * config/tc-arm.c (md_undefined_symbol): Issue a warning message
(if enabled) when the user creates a symbol with the same name as
an ARM instruction.
(flag_warn_syms): New static variable.
(arm_opts): Add mwarn-syms and mno-warn-syms.
* doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
options.
tests * gas/arm/pr18347.s: New file: Test case.
* gas/arm/pr18347.l: New file: Expected assembler output.
* gas/arm/pr18347.d: New file: Test driver.
gas PR 18256
* config/tc-arm.c (encode_arm_cp_address): Issue an error message
if the operand is neither a register nor a vector.
tests * gas/arm/pr18256.s: New file: Test case.
* gas/arm/pr18256.l: New file: Expected assembler output.
* gas/arm/pr18256.d: New file: Test driver.
* ppc-opc.c (DCBT_EO): New define.
(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
<lharx>: Likewise.
<stbcx.>: Likewise.
<sthcx.>: Likewise.
<waitrsv>: Do not enable for POWER7 and later.
<waitimpl>: Likewise.
<dcbt>: Default to the two operand form of the instruction for all
"old" cpus. For "new" cpus, use the operand ordering that matches
whether the cpu is server or embedded.
<dcbtst>: Likewise.
gas/testsuite/
* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
ordering change.
* gas/ppc/a2.d: Likewise.
* gas/ppc/476.d: Likewise.
* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
* gas/ppc/booke.d: Likewise.
* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
and waitimpl tests.
* gas/ppc/power7.d: Likewise.
gas/
* config/tc-mips.c (macro): State the recommended way of creating
32-bit or 64-bit addresses.
gas/testsuite/
* gas/mips/dla-warn.l: New file.
* gas/mips/dla-warn.s: New file.
* gas/mips/la-warn.l: New file.
* gas/mips/la-warn.s: New file.
* gas/mips/mips.exp: Run new tests.
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.
gas/testsuite/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
register, non-broadcast cases.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512f_vl.d: Likewise.
opcodes/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
(vfpclasspd, vfpclassps): Add %XZ.
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory. That ambiguity, however, doesn't
apply when using broadcasts (the destination operand size can be
induced from the broadcast specifier).
gas/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size): Also allow no size
specification when broadcasting.
gas/testsuite/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in
some AT&T and all Intel cases.
* gas/i386/x86-64-avx512dq.s: Likewise.
* gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512dq_vl.s: Likewise.
* gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512f_vl.s: Likewise.
This patch silences texinfo 5.1 warnings by using @subsection and
sorting entries in Machine Dependencies menu.
* doc/as.texinfo (Bundle directives): Shorten menu entry and
use @subsection.
(CFI directives): Use @subsection.
(SH-Dependent, SH64-Dependent): Moved after SCORE-Dependent.
* doc/c-i386.texi (i386-Mnemonics): Use @subsection.
This patch puts rdrand and rdseed in prefix_table so that invalid
prefixes for rdrand and rdseed are handled properly.
gas/testsuite/
PR binutils/17898
* gas/i386/prefix.s: Add rdrand/rdseed prefix tests.
* gas/i386/prefix.d: Updated.
opcodes/
PR binutils/17898
* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
(PREFIX_MOD_0_0FC7_REG_6): This.
(PREFIX_MOD_3_0FC7_REG_6): New.
(PREFIX_MOD_3_0FC7_REG_7): Likewise.
(prefix_table): Replace PREFIX_0FC7_REG_6 with
PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
PREFIX_MOD_3_0FC7_REG_7.
(mod_table): Replace PREFIX_0FC7_REG_6 with
PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
PREFIX_MOD_3_0FC7_REG_7.
2015-04-15 Renlin Li <renlin.li@arm.com>
opcodes/:
* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
use it for ssat and ssat16.
(print_insn_thumb32): Add handle case for 'D' control code.
gas/testsuite/:
* gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
* gas/arm/thumb32.d: Likewise.
This patch adds --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
to ld for ELF targets to support generating compressed DWARF debug
sections. We always generate .zdebug_* section since section names have
been finalized and they can't be changed easily when compression is
being performed.
bfd/
* bfd-in.h (compressed_debug_section_type): New.
* compress.c (bfd_compress_section_contents): Add an argument
for linker write compression and always generate .zdebug_*
section when linking.
(bfd_init_section_compress_status): Pass FALSE to
bfd_compress_section_contents.
(bfd_compress_section): New function.
* elf.c (elf_fake_sections): For linking, set SEC_ELF_COMPRESS
on DWARF debug sections if COMPRESS_DEBUG is set and rename
section if COMPRESS_DEBUG_GABI_ZLIB isn't set.
(assign_file_positions_for_non_load_sections): Set sh_offset
to -1 if SEC_ELF_COMPRESS is set.
(assign_file_positions_except_relocs): Likwise.
(_bfd_elf_assign_file_positions_for_relocs): Renamed to ...
(_bfd_elf_assign_file_positions_for_non_load): This. Change
return time to bfd_boolean. Compress the section if
SEC_ELF_COMPRESS is set.
(_bfd_elf_write_object_contents): Updated.
(_bfd_elf_set_section_contents): Write section contents to
the buffer if SEC_ELF_COMPRESS is set.
* merge.c: Include "elf-bfd.h".
(sec_merge_emit): Add arguments for contents and offset. Write
to contents with offset if contents isn't NULL.
(_bfd_write_merged_section): Write section contents to the
buffer if SEC_ELF_COMPRESS is set. Pass contents and
output_offset to sec_merge_emit.
* elflink.c (bfd_elf_final_link): Allocate the buffer for
output section contents if SEC_ELF_COMPRESS is set.
* section.c (SEC_ELF_COMPRESS): New.
* bfd-in2.h: Regenerated.
gas/
* as.h (compressed_debug_section_type): Removed.
include/
* bfdlink.h (bfd_link_info): Add compress_debug.
ld/
* ld.texinfo: Document --compress-debug-sections=.
* ldmain.c (main): Set BFD_COMPRESS on output_bfd if
COMPRESS_DEBUG is set. Set BFD_COMPRESS_GABI on output_bfd
for COMPRESS_DEBUG_GABI_ZLIB.
* lexsup.c (elf_static_list_options): Add
--compress-debug-sections=.
* emultempl/elf32.em (OPTION_COMPRESS_DEBUG): New.
(xtra_long): Add "compress-debug-sections".
(gld${EMULATION_NAME}_handle_option): Handle
OPTION_COMPRESS_DEBUG.
ld/testsuite/
* ld-elf/compress.exp (build_tests): Add tests for
--compress-debug-sections=.
(run_tests): Likewise.
Add additonal tests for --compress-debug-sections=.
* ld-elf/gabiend.rt: New file.
* ld-elf/gabinormal.rt: Likewise.
* ld-elf/gnubegin.rS: Likewise.
* ld-elf/gnunormal.rS: Likewise.
* ld-elf/zlibbegin.rS: Likewise.
* ld-elf/zlibnormal.rS: Likewise.
gas * config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define.
(TC_FORCE_RELOCATION_SUB_SAME): Define.
(DWARF2_USE_FIXED_ADVANCE_PC): Define.
* gas/lns/lns.exp: Add RL78 to list of targets using
DW_LNS_fixed_advance_pc.
bfd * elf32-rl78.c (RL78_OP_REL): New macro.
(rl78_elf_howto_table): Use it for complex relocs.
(get_symbol_value): Handle the cases when the info or status
arguments are NULL.
(get_romstart): Cache the status returned by get_symbol_value.
(get_ramstart): Likewise.
(RL78_STACK_PUSH): Generate an error message if the stack
overflows.
(RL78_STACK_POP): Likewise for underflows.
(rl78_compute_complex_reloc): New function. Contains the basic
processing code for all RL78 complex relocs.
(rl78_special_reloc): New function. Provides special reloc
handling for complex relocs.
(rl78_elf_relocate_section): Use rl78_compute_complex_reloc.
(rl78_offset_for_reloc): Likewise.
binutils* readelf.c (target_specific_reloc_handling): Add code to handle
RL78 complex relocs.
PR binutils/18198
* ld.texinfo (--be8): Add a note about the interaction of this
option with the assembler's -EB option.
* doc/c-arm.texi (ARM Options): Add a note about the interaction of
the -EB option with the linker's --be8 option.
bfd * elf32-rx.c (describe_flags): Report the settings of the string
insn using bits.
(rx_elf_merge_private_bfd_data): Handle merging of the string insn
using bits.
bin * readelf.c (get_machine_flags): Report the setting of the string
insn using bits.
gas * config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
(md_longopts): Add -mno-allow-string-insns.
(md_parse_option): Handle -mno-allow-string-insns.
(md_show_usage): Mention -mno-allow-string-insns.
(rx_note_string_insn_use): New function. Produces an error
message if a string insn is used when it is not allowed.
* config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
(SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
* config/rx-defs.h (rx_note_string_insn_use): Prototype.
* doc/c-rx.texi: Document -mno-allow-string-insns.
elf * rx.h (E_FLAG_RX_SINSNS_SET): New bit in e_flags field.
(E_FLAG_RX_SINSNS_YES): Likewise.
(E_FLAG_RX_SINSNS_MASK): New define.
This patch adds --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}
options to gas and objcopy for ELF files. They control how DWARF debug
sections are compressed. --compress-debug-sections=none is equivalent to
--nocompress-debug-sections. --compress-debug-sections=zlib and
--compress-debug-sections=zlib-gnu are equivalent to
--compress-debug-sections. --compress-debug-sections=zlib-gabi compresses
DWARF debug sections with SHF_COMPRESSED from the ELF ABI. No linker
changes are required to support SHF_COMPRESSED.
bfd/
* archive.c (_bfd_get_elt_at_filepos): Also copy BFD_COMPRESS_GABI
bit.
* bfd.c (bfd::flags): Increase size to 18 bits.
(BFD_COMPRESS_GABI): New.
(BFD_FLAGS_SAVED): Add BFD_COMPRESS_GABI.
(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
(bfd_update_compression_header): New fuction.
(bfd_check_compression_header): Likewise.
(bfd_get_compression_header_size): Likewise.
(bfd_is_section_compressed_with_header): Likewise.
* compress.c (MAX_COMPRESSION_HEADER_SIZE): New.
(bfd_compress_section_contents): Return the uncompressed size if
the full section contents is compressed successfully. Support
converting from/to .zdebug* sections.
(bfd_get_full_section_contents): Call
bfd_get_compression_header_size to get compression header size.
(bfd_is_section_compressed): Renamed to ...
(bfd_is_section_compressed_with_header): This. Add a pointer
argument to return compression header size.
(bfd_is_section_compressed): Use it.
(bfd_init_section_decompress_status): Call
bfd_get_compression_header_size to get compression header size.
Return FALSE if uncompressed section size is 0.
* elf.c (_bfd_elf_make_section_from_shdr): Support converting
from/to .zdebug* sections.
* bfd-in2.h: Regenerated.
binutils/
* objcopy.c (do_debug_sections): Add compress_zlib,
compress_gnu_zlib and compress_gabi_zlib.
(copy_options): Use optional_argument on compress-debug-sections.
(copy_usage): Update --compress-debug-sections.
(copy_file): Handle compress_zlib, compress_gnu_zlib and
compress_gabi_zlib.
(copy_main): Handle
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* doc/binutils.texi: Document
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
binutils/testsuite/
* compress.exp: Add tests for
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* binutils-all/dw2-3.rS: New file.
* binutils-all/dw2-3.rt: Likewise.
* binutils-all/libdw2-compressedgabi.out: Likewise.
gas/
* as.c (show_usage): Update --compress-debug-sections.
(std_longopts): Use optional_argument on compress-debug-sections.
(parse_args): Handle
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* as.h (compressed_debug_section_type): New.
(flag_compress_debug): Change type to compressed_debug_section_type.
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* write.c (compress_debug): Set BFD_COMPRESS_GABI for
--compress-debug-sections=zlib-gabi. Call
bfd_get_compression_header_size to get compression header size.
Don't rename section name for --compress-debug-sections=zlib-gabi.
* config/tc-i386.c (compressed_debug_section_type): Set to
COMPRESS_DEBUG_ZLIB.
* doc/as.texinfo: Document
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
gas/testsuite/
* gas/i386/dw2-compressed-1.d: New file.
* gas/i386/dw2-compressed-2.d: Likewise.
* gas/i386/dw2-compressed-3.d: Likewise.
* gas/i386/x86-64-dw2-compressed-2.d: Likewise.
* gas/i386/i386.exp: Run dw2-compressed-2, dw2-compressed-1,
dw2-compressed-3 and x86-64-dw2-compressed-2.
ld/testsuite/
* ld-elf/compress.exp: Add a test for
--compress-debug-sections=zlib-gabi.
(build_tests): Add 2 tests for --compress-debug-sections=zlib-gabi.
(run_tests): Likewise.
Verify linker output with zlib-gabi compressed debug input.
* ld-elf/compressed1a.d: New file.
* ld-elf/compressed1b.d: Likewise.
* ld-elf/compressed1c.d: Likewise.
There is no need to generate compressed debug section if compressed
section size is the same as before compression. We should xfail the
compressed debug section test if there are no compressed sections
binutils/testsuite/
* binutils-all/compress.exp (compression_used): New.
Xfail test if compression didn't make the section smaller.
gas/
2015-04-05 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Don't write the zlib header if
compressed section size is the same as before compression.
2015-03-27 Renlin Li <renlin.li@arm.com>
gas/
* config/tc-aarch64.c (mapping_state): Emit MAP_DATA within text section in order.
(mapping_state_2): Don't emit MAP_DATA here.
(s_aarch64_inst): Align frag during state transition.
(md_assemble): Likewise.
gas/ChangeLog:
2015-03-25 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (mapping_state): Remove first MAP_DATA emitting code.
(mapping_state_2): Emit first MAP_DATA symbol here.
No need to write the zlib header if compression didn't make the section
smaller.
PR gas/18087
* write.c (compress_debug): Don't write the zlib header if
compression didn't make the section smaller.
inc * rl78.h (E_FLAG_RL78_G10): Redefine.
(E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13
E_FLAG_RL78_G14): New flags.
bin * readelf.c (get_machine_flags): Decode RL78's G13 and G14 flags.
gas * config/tc-rl78.c (enum options): Add G13 and G14.
(md_longopts): Add -mg13 and -mg14.
(md_parse_option): Handle -mg13 and -mg14.
(md_show_usage): List -mg13 and -mg14.
* doc/c-rl78.texi: Add description of -mg13 and -mg14 options.
bfd * elf32-rl78.c (rl78_cpu_name): New function. Prints the name of
the RL78 core based upon the flags.
(rl78_elf_merge_private_bfd_data): Handle merging of G13 and G14
flags.
(rl78_elf_print_private_bfd_data): Use rl78_cpu_name.
(elf32_rl78_machine): Always return bfd_mach_rl78.
PR gas/18087
gas/test * gas/i386/dw2-compress-1.d: Allow the test to pass regardless of
whether the .debug_info section was compressed on not.
bfd * compress.c (bfd_compress_section_contents): Do not define this
function if it is not used.
PR binutils/18087
gas * doc/as.texinfo: Note that when gas compresses debug sections the
compression is only performed if it makes the section smaller.
* write.c (compress_debug): Do not compress a debug section if
doing so would make it larger.
tests * gas/i386/dw2-compress-1.d: Do not expect the .debug_abbrev or
.debug_info sections to be compressed.
binu * doc/binutils.texi: Note that when objcopy compresses debug
sections the compression is only performed if it makes the section
smaller.
bfd * coffgen.c (make_a_section_from_file): Only prepend a z to a
debug section's name if the section was actually compressed.
* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
* compress.c (bfd_init_section_compress_status): Do not compress
the section if doing so would make it bigger. In such cases leave
the section alone and return COMPRESS_SECTION_NONE.
Nick Clifton