1999-02-22 17:47:59 +01:00
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/* Definitions of target machine for GNU compiler, for ARM.
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2001-01-01 21:35:36 +01:00
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Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2005-01-14 14:58:40 +01:00
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2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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1991-12-06 03:11:44 +01:00
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Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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1995-02-22 00:21:14 +01:00
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and Martin Simmons (@harleqn.co.uk).
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arm.c (typedef minipool_node): Renamed from pool_node.
* arm.c (typedef minipool_node): Renamed from pool_node.
(minipool_vector, minipool_size, minipool_vector_label): Similarly.
(add_minipool_constant): New function.
(dump_minipool): New function.
(find_barrier): Remove special case for getting the insn size of
an insn that references the constant pool.
(minipool_fixup): New structure.
(push_minipool_barrier): New function.
(push_minipool_fix): New function.
(note_invalid_constants): New function.
(add_pool_constant, dump_table, fixit, broken_move): Delete.
(arm_reorg): Rewrite code to fix up the constant pool into a
series of mini-pools embedded in the insn stream.
(arm_output_epilogue): New function, made mainly from the body
of output_func_epilogue.
(output_func_epilogue): Move insn generation part of epilogue code
to arm_output_epilogue.
* arm.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY): Delete.
* arm.md (pool_range): New attribute.
(zero_extendqidi2): Add attribute pool_range.
(zero_extend_hisi_insn, load_extendqisi, extendhisi_insn,
extendqihi_insn, extendqisi_insn, movdi, movsi_insn, pic_load_addr,
pic_load_addr_based_insn, movhi_insn_arch4, movhi_insn_littleend,
movhi_insn_bigend, loadhi_si_bigend, movsf_hard_insn, movsf_soft_insn,
movdf_hard_insn, movdf_soft_insn, movxf_hard_insn): Likewise.
(epilogue): New expand.
(epilogue_insn): New insn. Call arm_output_epilogue.
* arm.c (arm_poke_function_name): Undo change of July 17. Tidy up.
* arm.h (TARGET_SWITCHES): Add missing doc string for TARGET_DEFAULT.
From-SVN: r28499
1999-08-04 15:40:10 +02:00
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More major hacks by Richard Earnshaw (rearnsha@arm.com)
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1999-07-17 15:44:35 +02:00
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Minor hacks by Nick Clifton (nickc@cygnus.com)
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2003-02-10 17:33:09 +01:00
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This file is part of GCC.
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1991-12-06 03:11:44 +01:00
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2003-02-10 17:33:09 +01:00
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 2, or (at your
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option) any later version.
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1991-12-06 03:11:44 +01:00
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2003-02-10 17:33:09 +01:00
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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1991-12-06 03:11:44 +01:00
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2003-02-10 17:33:09 +01:00
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA. */
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1991-12-06 03:11:44 +01:00
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2001-05-26 03:31:47 +02:00
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#ifndef GCC_ARM_H
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#define GCC_ARM_H
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1998-10-27 12:13:39 +01:00
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alias.c, [...]: Fix comment typos.
* alias.c, c-common.h, c-incpath.c, c-incpath.h, expr.c,
fold-const.c, gimplify.c, params.h, tree-data-ref.c,
tree-if-conv.c, tree-nested.c, tree-outof-ssa.c,
tree-ssa-dom.c, tree-vectorizer.c, tree.def, config/darwin.c,
config/freebsd-spec.h, config/arm/arm.h,
config/h8300/h8300.md, config/i386/i386.md,
config/i386/predicates.md, config/i386/sse.md,
config/ia64/ia64.c, config/ip2k/ip2k.c, config/s390/s390.c,
config/vax/vax.md: Fix comment typos. Follow spelling
conventions.
From-SVN: r94112
2005-01-23 16:05:49 +01:00
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/* The architecture define. */
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2004-04-30 14:13:49 +02:00
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extern char arm_arch_name[];
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arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
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/* Target CPU builtins. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Define __arm__ even when in thumb mode, for \
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consistency with armcc. */ \
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builtin_define ("__arm__"); \
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arm.h (TARGET_APCS_32): Delete.
* arm.h (TARGET_APCS_32): Delete.
(TARGET_MMU_TRAPS): Delete.
(TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never
define __APCS_26__.
(CPP_SPEC): Remove checking of -mapcs-{26,32}.
(ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete.
(TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches.
(prog_mode_type): Delete.
(PROMOTE_MODE): Always promote unsigned for HImode.
(SECONDARY_INPUT_RELOAD_CLASS): Simplify.
(MASK_RETURN_ADDR): Simplify.
* arm.c (arm_prgmode): Delete.
(arm_override_options, arm_gen_rotated_half_load): Simplify.
(print_multi_reg, output_return_instruction): Simplify.
(arm_output_epilogue, arm_final_prescan_insn): Simplify.
(arm_return_addr): Simplify.
* arm.md (prog_mode): Delete.
(conds): Simplify.
(zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify.
(rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete.
(loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete.
(loadhi_shiftpredec): Delete.
(peephole for post-increment on HImode load): Delete.
* arm/crtn.asm: (FUNC_END): Simplify.
* arm/lib1funcs.asm: Remove APCS-26 return macros.
* arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h
* arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h
* arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and
MULTILIB_DEFAULTS as required.
* arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe
* arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB
variables as required.
* doc/invoke.texi (ARM Options): Remove obsolete flags.
From-SVN: r81881
2004-05-15 14:41:35 +02:00
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builtin_define ("__APCS_32__"); \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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if (TARGET_THUMB) \
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arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
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builtin_define ("__thumb__"); \
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\
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if (TARGET_BIG_END) \
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{ \
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builtin_define ("__ARMEB__"); \
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if (TARGET_THUMB) \
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builtin_define ("__THUMBEB__"); \
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if (TARGET_LITTLE_WORDS) \
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builtin_define ("__ARMWEL__"); \
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} \
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else \
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{ \
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builtin_define ("__ARMEL__"); \
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if (TARGET_THUMB) \
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builtin_define ("__THUMBEL__"); \
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} \
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\
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if (TARGET_SOFT_FLOAT) \
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builtin_define ("__SOFTFP__"); \
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\
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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|
if (TARGET_VFP) \
|
2002-09-05 18:54:57 +02:00
|
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|
builtin_define ("__VFP_FP__"); \
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\
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arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
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/* Add a define for interworking. \
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Needed when building libgcc.a. */ \
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2004-07-09 11:30:46 +02:00
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if (arm_cpp_interwork) \
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arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
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builtin_define ("__THUMB_INTERWORK__"); \
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\
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builtin_assert ("cpu=arm"); \
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builtin_assert ("machine=arm"); \
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2004-04-30 14:13:49 +02:00
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\
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builtin_define (arm_arch_name); \
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if (arm_arch_cirrus) \
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builtin_define ("__MAVERICK__"); \
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if (arm_arch_xscale) \
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builtin_define ("__XSCALE__"); \
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if (arm_arch_iwmmxt) \
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builtin_define ("__IWMMXT__"); \
|
2004-06-25 15:48:51 +02:00
|
|
|
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if (TARGET_AAPCS_BASED) \
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builtin_define ("__ARM_EABI__"); \
|
arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
|
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} while (0)
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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|
|
/* The various ARM cores. */
|
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|
enum processor_type
|
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{
|
2004-09-01 14:49:30 +02:00
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#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
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IDENT,
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#include "arm-cores.def"
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#undef ARM_CORE
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/* Used to indicate that no processor has been specified. */
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arm_none
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};
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2004-04-30 14:13:49 +02:00
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enum target_cpus
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{
|
2004-09-01 14:49:30 +02:00
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#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
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TARGET_CPU_##IDENT,
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2004-04-30 14:13:49 +02:00
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#include "arm-cores.def"
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#undef ARM_CORE
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TARGET_CPU_generic
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};
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
/* The processor for which instructions should be scheduled. */
|
|
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|
|
extern enum processor_type arm_tune;
|
|
|
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|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
typedef enum arm_cond_code
|
1996-02-27 14:15:13 +01:00
|
|
|
|
{
|
|
|
|
|
ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
|
|
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|
|
ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
|
2000-04-08 16:29:53 +02:00
|
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|
|
}
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|
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arm_cc;
|
1999-07-17 15:44:35 +02:00
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|
2000-04-08 16:29:53 +02:00
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|
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extern arm_cc arm_current_cc;
|
1993-10-03 17:33:02 +01:00
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|
|
2000-04-08 16:29:53 +02:00
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|
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#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
|
1996-02-27 14:15:13 +01:00
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1999-07-17 15:44:35 +02:00
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extern int arm_target_label;
|
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|
|
extern int arm_ccfsm_state;
|
2002-06-04 09:11:05 +02:00
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|
extern GTY(()) rtx arm_target_insn;
|
2000-04-08 16:29:53 +02:00
|
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|
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/* Define the information needed to generate branch insns. This is
|
2002-06-04 09:11:05 +02:00
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stored from the compare operation. */
|
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extern GTY(()) rtx arm_compare_op0;
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|
extern GTY(()) rtx arm_compare_op1;
|
2000-04-08 16:29:53 +02:00
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|
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/* The label of the current constant pool. */
|
2002-06-04 09:11:05 +02:00
|
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|
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extern rtx pool_vector_label;
|
2000-04-08 16:29:53 +02:00
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|
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/* Set to 1 when a return insn is output, this means that the epilogue
|
2003-12-25 16:17:37 +01:00
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is not needed. */
|
2000-04-08 16:29:53 +02:00
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extern int return_used_this_function;
|
2002-06-04 09:11:05 +02:00
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/* Used to produce AOF syntax assembler. */
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extern GTY(()) rtx aof_pic_label;
|
1991-12-06 03:11:44 +01:00
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2003-12-25 16:17:37 +01:00
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/* Just in case configure has failed to define anything. */
|
1997-05-09 00:17:34 +02:00
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#ifndef TARGET_CPU_DEFAULT
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#define TARGET_CPU_DEFAULT TARGET_CPU_generic
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#endif
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2001-12-13 01:27:30 +01:00
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#undef CPP_SPEC
|
2004-04-30 14:13:49 +02:00
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#define CPP_SPEC "%(subtarget_cpp_spec) \
|
arm.h (TARGET_CPU_CPP_BUILTINS): Define.
config:
* arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define.
(CPP_SPEC): Update.
(CPP_APCS_PC_SPEC, CPP_APCS_PC_DEFAULT_SPEC,
CPP_FLOAT_SPEC, CPP_FLOAT_DEFAULT_SPEC, CPP_ENDIAN_SPEC,
CPP_ENDIAN_DEFAULT_SPEC, CPP_INTERWORK_DEFAULT_SPEC,
CPP_INTERWORK_SPEC, CPP_PREDEFINES): Remove.
(EXTRA_SPECS): Update.
* arm/conix-elf.h, arm/linux-elf.h, arm/netbsd.h, arm/riscix.h,
arm/riscix1-1.h, arm/rtems-elf.h, arm/semiaof.h, arm/unknown-elf.h,
arm/unknown-elf-oabi.h, arm/vxarm.h: Remove CPP_PREDEFINES and
define TARGET_OS_CPP_BUILTINS if necessary.
From-SVN: r53463
2002-05-14 19:35:50 +02:00
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%{msoft-float:%{mhard-float: \
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%e-msoft-float and -mhard_float may not be used together}} \
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%{mbig-endian:%{mlittle-endian: \
|
|
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|
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%e-mbig-endian and -mlittle-endian may not be used together}}"
|
1997-05-09 00:17:34 +02:00
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2001-09-14 12:19:30 +02:00
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#ifndef CC1_SPEC
|
1999-02-25 11:57:17 +01:00
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#define CC1_SPEC ""
|
2001-09-14 12:19:30 +02:00
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#endif
|
1997-05-09 00:17:34 +02:00
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/* This macro defines names of additional specifications to put in the specs
|
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that can be used in various specifications like CC1_SPEC. Its definition
|
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is an initializer with a subgrouping for each command option.
|
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Each subgrouping contains a string constant, that defines the
|
2003-02-10 17:33:09 +01:00
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specification name, and a string constant that used by the GCC driver
|
1997-05-09 00:17:34 +02:00
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program.
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Do not define this macro if it does not need to do anything. */
|
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|
#define EXTRA_SPECS \
|
1997-07-30 14:54:05 +02:00
|
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|
|
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
|
1997-05-09 00:17:34 +02:00
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SUBTARGET_EXTRA_SPECS
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2000-02-11 23:39:49 +01:00
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|
#ifndef SUBTARGET_EXTRA_SPECS
|
1997-05-09 00:17:34 +02:00
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|
|
#define SUBTARGET_EXTRA_SPECS
|
2000-02-11 23:39:49 +01:00
|
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|
#endif
|
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|
1999-07-17 15:44:35 +02:00
|
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|
|
#ifndef SUBTARGET_CPP_SPEC
|
1997-07-30 14:54:05 +02:00
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#define SUBTARGET_CPP_SPEC ""
|
1999-07-17 15:44:35 +02:00
|
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|
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#endif
|
1991-12-06 03:11:44 +01:00
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/* Run-time Target Specification. */
|
1993-10-03 17:33:02 +01:00
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|
#ifndef TARGET_VERSION
|
1999-07-17 15:44:35 +02:00
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|
#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
|
1993-10-03 17:33:02 +01:00
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|
|
#endif
|
1991-12-06 03:11:44 +01:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
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2004-08-24 13:32:53 +02:00
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/* Use hardware floating point instructions. */
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#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
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/* Use hardware floating point calling convention. */
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#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
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#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
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#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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#define TARGET_IWMMXT (arm_arch_iwmmxt)
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#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
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config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
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#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
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2000-04-08 16:29:53 +02:00
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#define TARGET_ARM (! TARGET_THUMB)
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#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
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config.gcc (arm*-wince-pe*, [...]): Add arm/pe.opt to $extra_options.
* config.gcc (arm*-wince-pe*, arm-*-pe*, strongarm-*-pe): Add
arm/pe.opt to $extra_options.
* config/arm/arm.h (target_flags, target_fpu_name, target_fpe_name)
(target_float_abi_name, target_float_switch, target_abi_name)
(ARM_FLAG_APCS_FRAME, ARM_FLAG_POKE, ARM_FLAG_FPE, ARM_FLAG_APCS_STACK)
(ARM_FLAG_APCS_FLOAT, ARM_FLAG_APCS_REENT, ARM_FLAG_BIG_END)
(ARM_FLAG_INTERWORK, ARM_FLAG_LITTLE_WORDS, ARM_FLAG_NO_SCHED_PRO)
(ARM_FLAG_ABORT_NORETURN, ARM_FLAG_SINGLE_PIC_BASE)
(ARM_FLAG_LONG_CALLS, ARM_FLAG_THUMB, THUMB_FLAG_BACKTRACE)
(THUMB_FLAG_LEAF_BACKTRACE, THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
(THUMB_FLAG_CALLER_SUPER_INTERWORKING, CIRRUS_FIX_INVALID_INSNS)
(TARGET_APCS_FRAME, TARGET_POKE_FUNCTION_NAME, TARGET_FPE)
(TARGET_APCS_STACK, TARGET_APCS_FLOAT, TARGET_APCS_REENT)
(TARGET_BIG_END, TARGET_INTERWORK, TARGET_LITTLE_WORDS)
(TARGET_NO_SCHED_PRO, TARGET_ABORT_NORETURN, TARGET_SINGLE_PIC_BASE)
(TARGET_LONG_CALLS, TARGET_THUMB, TARGET_CALLER_INTERWORKING)
(TARGET_CIRRUS_FIX_INVALID_INSNS, SUBTARGET_SWITCHES, TARGET_SWITCHES)
(TARGET_OPTIONS, arm_cpu_select, arm_select, structure_size_string)
(arm_pic_register_string): Delete.
(TARGET_BACKTRACE): Redefine using TARGET_TPCS_LEAF_FRAME and
TARGET_TPCS_FRAME.
(TARGET_DEFAULT, CONDITIONAL_REGISTER_USAGE): Update mask names.
* config/arm/coff.h (TARGET_DEFAULT): Likewise.
* config/arm/elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd.h (TARGET_DEFAULT): Likewise.
* config/arm/semi.h (TARGET_DEFAULT): Likewise.
* config/arm/uclinux-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/wince-pe.h (TARGET_DEFAULT): Likewise.
* config/arm/pe.h (TARGET_DEFAULT): Likewise.
(TARGET_FLAG_NOP_FUN, TARGET_NOP_FUN_DLLIMPORT): Delete.
(SUBTARGET_SWITCHES): Delete.
* config/arm/arm.c (target_float_switch): Delete.
(arm_cpu_select): Moved from config/arm/arm.h.
(target_fpu_name, target_fpe_name, target_float_abi_name)
(target_abi_name, structure_size_string, arm_pic_register_string)
(arm_select): Make static.
(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
(arm_handle_option): New function.
(arm_override_options): Update target_flags checks for new mask names.
Remove target_float_switch code.
(arm_expand_prologue, thumb_expand_prologue): Check
!TARGET_SCHED_PROLOG instead of TARGET_NO_SCHED_PRO.
* config/arm/arm.opt, config/arm/pe.opt: New files.
From-SVN: r99265
2005-05-05 14:09:00 +02:00
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#define TARGET_BACKTRACE (leaf_function_p () \
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? TARGET_TPCS_LEAF_FRAME \
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: TARGET_TPCS_FRAME)
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2004-05-06 01:11:55 +02:00
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#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
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2004-05-10 15:39:20 +02:00
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#define TARGET_AAPCS_BASED \
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(arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
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1995-03-10 20:08:13 +01:00
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2004-08-11 04:50:14 +02:00
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/* True iff the full BPABI is being used. If TARGET_BPABI is true,
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then TARGET_AAPCS_BASED must be true -- but the converse does not
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hold. TARGET_BPABI implies the use of the BPABI runtime library,
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etc., in addition to just the AAPCS calling conventions. */
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#ifndef TARGET_BPABI
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#define TARGET_BPABI false
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2004-08-24 02:30:52 +02:00
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#endif
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2004-08-11 04:50:14 +02:00
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config.gcc: Reorganize --with-cpu logic.
* config.gcc: Reorganize --with-cpu logic. Set
configure_default_options according to the default CPU, --with-cpu,
--with-arch, --with-tune, --with-schedule, --with-abi, and
--with-float. Check for legal values of various options.
* configure.in: Define configure_default_options in configargs.h.
* configure: Regenerated.
* config/mips/mips.h (TARGET_DEFAULT_ARCH_P)
(TARGET_DEFAULT_FLOAT_P): New macros.
* gcc.c (do_option_spec): New function.
(struct default_spec, option_default_specs): New.
(main): Call do_option_spec.
* config/alpha/alpha.h, config/arm/arm.h, config/i386/i386.h,
config/mips/mips.h, config/pa/pa.h, config/rs6000/rs6000.h,
config/sparc/sparc.h (OPTION_DEFAULT_SPECS): Define.
* doc/install.texi: Update --with-cpu documentation. Mention
--with-arch, --with-schedule, --with-tune, --with-abi, and
--with-float.
* doc/tm.texi (Driver): Document OPTION_DEFAULT_SPECS.
From-SVN: r67457
2003-06-04 19:50:44 +02:00
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/* Support for a compile-time default CPU, et cetera. The rules are:
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--with-arch is ignored if -march or -mcpu are specified.
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--with-cpu is ignored if -march or -mcpu are specified, and is overridden
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by --with-arch.
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--with-tune is ignored if -mtune or -mcpu are specified (but not affected
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by -march).
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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--with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
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specified.
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config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
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--with-fpu is ignored if -mfpu is specified.
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--with-abi is ignored is -mabi is specified. */
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config.gcc: Reorganize --with-cpu logic.
* config.gcc: Reorganize --with-cpu logic. Set
configure_default_options according to the default CPU, --with-cpu,
--with-arch, --with-tune, --with-schedule, --with-abi, and
--with-float. Check for legal values of various options.
* configure.in: Define configure_default_options in configargs.h.
* configure: Regenerated.
* config/mips/mips.h (TARGET_DEFAULT_ARCH_P)
(TARGET_DEFAULT_FLOAT_P): New macros.
* gcc.c (do_option_spec): New function.
(struct default_spec, option_default_specs): New.
(main): Call do_option_spec.
* config/alpha/alpha.h, config/arm/arm.h, config/i386/i386.h,
config/mips/mips.h, config/pa/pa.h, config/rs6000/rs6000.h,
config/sparc/sparc.h (OPTION_DEFAULT_SPECS): Define.
* doc/install.texi: Update --with-cpu documentation. Mention
--with-arch, --with-schedule, --with-tune, --with-abi, and
--with-float.
* doc/tm.texi (Driver): Document OPTION_DEFAULT_SPECS.
From-SVN: r67457
2003-06-04 19:50:44 +02:00
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#define OPTION_DEFAULT_SPECS \
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{"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
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{"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
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{"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
{"float", \
|
|
|
|
|
"%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
{"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
|
|
|
|
|
{"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
|
config.gcc: Reorganize --with-cpu logic.
* config.gcc: Reorganize --with-cpu logic. Set
configure_default_options according to the default CPU, --with-cpu,
--with-arch, --with-tune, --with-schedule, --with-abi, and
--with-float. Check for legal values of various options.
* configure.in: Define configure_default_options in configargs.h.
* configure: Regenerated.
* config/mips/mips.h (TARGET_DEFAULT_ARCH_P)
(TARGET_DEFAULT_FLOAT_P): New macros.
* gcc.c (do_option_spec): New function.
(struct default_spec, option_default_specs): New.
(main): Call do_option_spec.
* config/alpha/alpha.h, config/arm/arm.h, config/i386/i386.h,
config/mips/mips.h, config/pa/pa.h, config/rs6000/rs6000.h,
config/sparc/sparc.h (OPTION_DEFAULT_SPECS): Define.
* doc/install.texi: Update --with-cpu documentation. Mention
--with-arch, --with-schedule, --with-tune, --with-abi, and
--with-float.
* doc/tm.texi (Driver): Document OPTION_DEFAULT_SPECS.
From-SVN: r67457
2003-06-04 19:50:44 +02:00
|
|
|
|
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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/* Which floating point model to use. */
|
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|
enum arm_fp_model
|
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{
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ARM_FP_MODEL_UNKNOWN,
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/* FPA model (Hardware or software). */
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ARM_FP_MODEL_FPA,
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/* Cirrus Maverick floating point model. */
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ARM_FP_MODEL_MAVERICK,
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/* VFP floating point model. */
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ARM_FP_MODEL_VFP
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};
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extern enum arm_fp_model arm_fp_model;
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/* Which floating point hardware is available. Also update
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fp_model_for_fpu in arm.c when adding entries to this list. */
|
2003-03-10 18:53:19 +01:00
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|
enum fputype
|
1994-06-27 17:24:36 +02:00
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{
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* No FP hardware. */
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FPUTYPE_NONE,
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2003-03-10 18:53:19 +01:00
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/* Full FPA support. */
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FPUTYPE_FPA,
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/* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
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FPUTYPE_FPA_EMU2,
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/* Emulated FPA hardware, Issue 3 emulator. */
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FPUTYPE_FPA_EMU3,
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/* Cirrus Maverick floating point co-processor. */
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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FPUTYPE_MAVERICK,
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/* VFP. */
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FPUTYPE_VFP
|
1994-06-27 17:24:36 +02:00
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};
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/* Recast the floating point class to be the floating point attribute. */
|
2003-03-10 18:53:19 +01:00
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#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
|
1994-06-27 17:24:36 +02:00
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1997-07-16 16:54:40 +02:00
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/* What type of floating point to tune for */
|
2003-03-10 18:53:19 +01:00
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extern enum fputype arm_fpu_tune;
|
1994-06-27 17:24:36 +02:00
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1997-07-16 16:54:40 +02:00
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/* What type of floating point instructions are available */
|
2003-03-10 18:53:19 +01:00
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extern enum fputype arm_fpu_arch;
|
1997-07-16 16:54:40 +02:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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enum float_abi_type
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{
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ARM_FLOAT_ABI_SOFT,
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ARM_FLOAT_ABI_SOFTFP,
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ARM_FLOAT_ABI_HARD
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};
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extern enum float_abi_type arm_float_abi;
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2004-11-18 16:59:48 +01:00
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#ifndef TARGET_DEFAULT_FLOAT_ABI
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#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
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#endif
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config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
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/* Which ABI to use. */
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enum arm_abi_type
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{
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ARM_ABI_APCS,
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ARM_ABI_ATPCS,
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ARM_ABI_AAPCS,
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ARM_ABI_IWMMXT
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};
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extern enum arm_abi_type arm_abi;
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#ifndef ARM_DEFAULT_ABI
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#define ARM_DEFAULT_ABI ARM_ABI_APCS
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#endif
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
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|
extern int arm_arch3m;
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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|
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
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extern int arm_arch4;
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2004-06-25 12:42:21 +02:00
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/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
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extern int arm_arch4t;
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
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1999-07-05 10:44:36 +02:00
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extern int arm_arch5;
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
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2001-01-08 16:33:06 +01:00
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extern int arm_arch5e;
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
|
|
|
|
|
extern int arm_arch6;
|
|
|
|
|
|
1999-02-22 17:47:59 +01:00
|
|
|
|
/* Nonzero if this chip can benefit from load scheduling. */
|
|
|
|
|
extern int arm_ld_sched;
|
|
|
|
|
|
2000-05-06 20:13:35 +02:00
|
|
|
|
/* Nonzero if generating thumb code. */
|
|
|
|
|
extern int thumb_code;
|
|
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|
|
|
1999-02-22 17:47:59 +01:00
|
|
|
|
/* Nonzero if this chip is a StrongARM. */
|
arm.c (FL_WBUF): Define.
* arm.c (FL_WBUF): Define.
(arm_tune_strongarm): Renamed from arm_is_strong. All uses changed.
(arm_is_6_or_7): Delete.
(arm_tune_wbuf): New.
(arm_override_options): Set arm_tune_wbuf.
* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
(arm_is_6_or_7): Delete declaration.
(arm_tune_wbuf): New declartion.
* arm.md (is_strongarm): Derive from arm_tune_strongarm.
(model_wbuf): Derive from arm_tune_wbuf.
* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
(arm740t): Mark CPUs as having a write buffer.
From-SVN: r97894
2005-04-09 14:03:54 +02:00
|
|
|
|
extern int arm_tune_strongarm;
|
1999-02-22 17:47:59 +01:00
|
|
|
|
|
2003-02-10 12:45:26 +01:00
|
|
|
|
/* Nonzero if this chip is a Cirrus variant. */
|
2004-04-30 14:13:49 +02:00
|
|
|
|
extern int arm_arch_cirrus;
|
2003-02-10 12:45:26 +01:00
|
|
|
|
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
|
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|
|
extern int arm_arch_iwmmxt;
|
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|
2000-12-04 01:23:35 +01:00
|
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|
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/* Nonzero if this chip is an XScale. */
|
2003-05-15 20:38:21 +02:00
|
|
|
|
extern int arm_arch_xscale;
|
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|
|
arm.c (FL_WBUF): Define.
* arm.c (FL_WBUF): Define.
(arm_tune_strongarm): Renamed from arm_is_strong. All uses changed.
(arm_is_6_or_7): Delete.
(arm_tune_wbuf): New.
(arm_override_options): Set arm_tune_wbuf.
* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
(arm_is_6_or_7): Delete declaration.
(arm_tune_wbuf): New declartion.
* arm.md (is_strongarm): Derive from arm_tune_strongarm.
(model_wbuf): Derive from arm_tune_wbuf.
* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
(arm740t): Mark CPUs as having a write buffer.
From-SVN: r97894
2005-04-09 14:03:54 +02:00
|
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|
|
/* Nonzero if tuning for XScale. */
|
2003-05-15 20:38:21 +02:00
|
|
|
|
extern int arm_tune_xscale;
|
2000-12-04 01:23:35 +01:00
|
|
|
|
|
arm.c (FL_WBUF): Define.
* arm.c (FL_WBUF): Define.
(arm_tune_strongarm): Renamed from arm_is_strong. All uses changed.
(arm_is_6_or_7): Delete.
(arm_tune_wbuf): New.
(arm_override_options): Set arm_tune_wbuf.
* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
(arm_is_6_or_7): Delete declaration.
(arm_tune_wbuf): New declartion.
* arm.md (is_strongarm): Derive from arm_tune_strongarm.
(model_wbuf): Derive from arm_tune_wbuf.
* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
(arm740t): Mark CPUs as having a write buffer.
From-SVN: r97894
2005-04-09 14:03:54 +02:00
|
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|
|
/* Nonzero if tuning for stores via the write buffer. */
|
|
|
|
|
extern int arm_tune_wbuf;
|
1999-02-22 17:47:59 +01:00
|
|
|
|
|
2004-07-09 11:30:46 +02:00
|
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|
|
/* Nonzero if we should define __THUMB_INTERWORK__ in the
|
2004-08-24 02:30:52 +02:00
|
|
|
|
preprocessor.
|
2004-07-09 11:30:46 +02:00
|
|
|
|
XXX This is a bit of a hack, it's intended to help work around
|
|
|
|
|
problems in GLD which doesn't understand that armv5t code is
|
|
|
|
|
interworking clean. */
|
|
|
|
|
extern int arm_cpp_interwork;
|
|
|
|
|
|
1994-10-02 16:10:27 +01:00
|
|
|
|
#ifndef TARGET_DEFAULT
|
config.gcc (arm*-wince-pe*, [...]): Add arm/pe.opt to $extra_options.
* config.gcc (arm*-wince-pe*, arm-*-pe*, strongarm-*-pe): Add
arm/pe.opt to $extra_options.
* config/arm/arm.h (target_flags, target_fpu_name, target_fpe_name)
(target_float_abi_name, target_float_switch, target_abi_name)
(ARM_FLAG_APCS_FRAME, ARM_FLAG_POKE, ARM_FLAG_FPE, ARM_FLAG_APCS_STACK)
(ARM_FLAG_APCS_FLOAT, ARM_FLAG_APCS_REENT, ARM_FLAG_BIG_END)
(ARM_FLAG_INTERWORK, ARM_FLAG_LITTLE_WORDS, ARM_FLAG_NO_SCHED_PRO)
(ARM_FLAG_ABORT_NORETURN, ARM_FLAG_SINGLE_PIC_BASE)
(ARM_FLAG_LONG_CALLS, ARM_FLAG_THUMB, THUMB_FLAG_BACKTRACE)
(THUMB_FLAG_LEAF_BACKTRACE, THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
(THUMB_FLAG_CALLER_SUPER_INTERWORKING, CIRRUS_FIX_INVALID_INSNS)
(TARGET_APCS_FRAME, TARGET_POKE_FUNCTION_NAME, TARGET_FPE)
(TARGET_APCS_STACK, TARGET_APCS_FLOAT, TARGET_APCS_REENT)
(TARGET_BIG_END, TARGET_INTERWORK, TARGET_LITTLE_WORDS)
(TARGET_NO_SCHED_PRO, TARGET_ABORT_NORETURN, TARGET_SINGLE_PIC_BASE)
(TARGET_LONG_CALLS, TARGET_THUMB, TARGET_CALLER_INTERWORKING)
(TARGET_CIRRUS_FIX_INVALID_INSNS, SUBTARGET_SWITCHES, TARGET_SWITCHES)
(TARGET_OPTIONS, arm_cpu_select, arm_select, structure_size_string)
(arm_pic_register_string): Delete.
(TARGET_BACKTRACE): Redefine using TARGET_TPCS_LEAF_FRAME and
TARGET_TPCS_FRAME.
(TARGET_DEFAULT, CONDITIONAL_REGISTER_USAGE): Update mask names.
* config/arm/coff.h (TARGET_DEFAULT): Likewise.
* config/arm/elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd.h (TARGET_DEFAULT): Likewise.
* config/arm/semi.h (TARGET_DEFAULT): Likewise.
* config/arm/uclinux-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/wince-pe.h (TARGET_DEFAULT): Likewise.
* config/arm/pe.h (TARGET_DEFAULT): Likewise.
(TARGET_FLAG_NOP_FUN, TARGET_NOP_FUN_DLLIMPORT): Delete.
(SUBTARGET_SWITCHES): Delete.
* config/arm/arm.c (target_float_switch): Delete.
(arm_cpu_select): Moved from config/arm/arm.h.
(target_fpu_name, target_fpe_name, target_float_abi_name)
(target_abi_name, structure_size_string, arm_pic_register_string)
(arm_select): Make static.
(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
(arm_handle_option): New function.
(arm_override_options): Update target_flags checks for new mask names.
Remove target_float_switch code.
(arm_expand_prologue, thumb_expand_prologue): Check
!TARGET_SCHED_PROLOG instead of TARGET_NO_SCHED_PRO.
* config/arm/arm.opt, config/arm/pe.opt: New files.
From-SVN: r99265
2005-05-05 14:09:00 +02:00
|
|
|
|
#define TARGET_DEFAULT (MASK_APCS_FRAME)
|
1994-10-02 16:10:27 +01:00
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
/* The frame pointer register used in gcc has nothing to do with debugging;
|
|
|
|
|
that is controlled by the APCS-FRAME option. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define CAN_DEBUG_WITHOUT_FP
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
#define OVERRIDE_OPTIONS arm_override_options ()
|
1999-05-08 11:40:05 +02:00
|
|
|
|
|
|
|
|
|
/* Nonzero if PIC code requires explicit qualifiers to generate
|
|
|
|
|
PLT and GOT relocs rather than the assembler doing so implicitly.
|
1999-07-23 15:19:49 +02:00
|
|
|
|
Subtargets can override these if required. */
|
|
|
|
|
#ifndef NEED_GOT_RELOC
|
|
|
|
|
#define NEED_GOT_RELOC 0
|
|
|
|
|
#endif
|
|
|
|
|
#ifndef NEED_PLT_RELOC
|
|
|
|
|
#define NEED_PLT_RELOC 0
|
1999-05-22 11:07:33 +02:00
|
|
|
|
#endif
|
1999-05-26 03:29:10 +02:00
|
|
|
|
|
|
|
|
|
/* Nonzero if we need to refer to the GOT with a PC-relative
|
|
|
|
|
offset. In other words, generate
|
|
|
|
|
|
2004-08-24 02:30:52 +02:00
|
|
|
|
.word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
|
1999-05-26 03:29:10 +02:00
|
|
|
|
|
|
|
|
|
rather than
|
|
|
|
|
|
|
|
|
|
.word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
|
|
|
|
|
|
2004-08-24 02:30:52 +02:00
|
|
|
|
The default is true, which matches NetBSD. Subtargets can
|
1999-05-26 03:29:10 +02:00
|
|
|
|
override this if required. */
|
|
|
|
|
#ifndef GOT_PCREL
|
|
|
|
|
#define GOT_PCREL 1
|
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Target machine storage Layout. */
|
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
|
|
|
|
/* Define this macro if it is advisable to hold scalars in registers
|
|
|
|
|
in a wider mode than that declared by the program. In such cases,
|
|
|
|
|
the value is constrained to be within the bounds of the declared
|
|
|
|
|
type, but kept valid in the wider mode. The signedness of the
|
|
|
|
|
extension may differ from that of the type. */
|
|
|
|
|
|
|
|
|
|
/* It is far faster to zero extend chars than to sign extend them */
|
|
|
|
|
|
1999-07-17 15:44:35 +02:00
|
|
|
|
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
1994-10-02 16:10:27 +01:00
|
|
|
|
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
|
|
|
|
&& GET_MODE_SIZE (MODE) < 4) \
|
|
|
|
|
{ \
|
|
|
|
|
if (MODE == QImode) \
|
|
|
|
|
UNSIGNEDP = 1; \
|
|
|
|
|
else if (MODE == HImode) \
|
arm.h (TARGET_APCS_32): Delete.
* arm.h (TARGET_APCS_32): Delete.
(TARGET_MMU_TRAPS): Delete.
(TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never
define __APCS_26__.
(CPP_SPEC): Remove checking of -mapcs-{26,32}.
(ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete.
(TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches.
(prog_mode_type): Delete.
(PROMOTE_MODE): Always promote unsigned for HImode.
(SECONDARY_INPUT_RELOAD_CLASS): Simplify.
(MASK_RETURN_ADDR): Simplify.
* arm.c (arm_prgmode): Delete.
(arm_override_options, arm_gen_rotated_half_load): Simplify.
(print_multi_reg, output_return_instruction): Simplify.
(arm_output_epilogue, arm_final_prescan_insn): Simplify.
(arm_return_addr): Simplify.
* arm.md (prog_mode): Delete.
(conds): Simplify.
(zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify.
(rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete.
(loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete.
(loadhi_shiftpredec): Delete.
(peephole for post-increment on HImode load): Delete.
* arm/crtn.asm: (FUNC_END): Simplify.
* arm/lib1funcs.asm: Remove APCS-26 return macros.
* arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h
* arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h
* arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and
MULTILIB_DEFAULTS as required.
* arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe
* arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB
variables as required.
* doc/invoke.texi (ARM Options): Remove obsolete flags.
From-SVN: r81881
2004-05-15 14:41:35 +02:00
|
|
|
|
UNSIGNEDP = 1; \
|
1994-10-02 16:10:27 +01:00
|
|
|
|
(MODE) = SImode; \
|
1993-10-03 17:33:02 +01:00
|
|
|
|
}
|
|
|
|
|
|
2004-04-08 20:26:09 +02:00
|
|
|
|
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
|
2005-04-26 18:30:37 +02:00
|
|
|
|
if ((GET_MODE_CLASS (MODE) == MODE_INT \
|
|
|
|
|
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
|
|
|
|
|
&& GET_MODE_SIZE (MODE) < 4) \
|
|
|
|
|
(MODE) = SImode; \
|
2004-04-08 20:26:09 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Define this if most significant bit is lowest numbered
|
|
|
|
|
in instructions that operate on numbered bit-fields. */
|
|
|
|
|
#define BITS_BIG_ENDIAN 0
|
|
|
|
|
|
2004-08-24 02:30:52 +02:00
|
|
|
|
/* Define this if most significant byte of a word is the lowest numbered.
|
1995-03-10 20:08:13 +01:00
|
|
|
|
Most ARM processors are run in little endian mode, so that is the default.
|
|
|
|
|
If you want to have it run-time selectable, change the definition in a
|
|
|
|
|
cover file to be TARGET_BIG_ENDIAN. */
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Define this if most significant word of a multiword number is the lowest
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
numbered.
|
|
|
|
|
This is always false, even when in big-endian mode. */
|
1996-02-12 17:51:37 +01:00
|
|
|
|
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
|
|
|
|
|
|
|
|
|
|
/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
|
|
|
|
|
on processor pre-defineds when compiling libgcc2.c. */
|
|
|
|
|
#if defined(__ARMEB__) && !defined(__ARMWEL__)
|
|
|
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 1
|
|
|
|
|
#else
|
|
|
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 0
|
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
/* Define this if most significant word of doubles is the lowest numbered.
|
2003-02-26 12:26:37 +01:00
|
|
|
|
The rules are different based on whether or not we use FPA-format,
|
|
|
|
|
VFP-format or some other floating point co-processor's format doubles. */
|
2002-09-05 18:54:57 +02:00
|
|
|
|
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
|
1993-10-19 22:40:59 +01:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
#define UNITS_PER_WORD 4
|
|
|
|
|
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
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/* True if natural alignment is used for doubleword types. */
|
2004-05-10 15:39:20 +02:00
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#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
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config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
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#define DOUBLEWORD_ALIGNMENT 64
|
1991-12-06 03:11:44 +01:00
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|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
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#define PARM_BOUNDARY 32
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
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#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
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|
#define PREFERRED_STACK_BOUNDARY \
|
|
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|
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(arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
|
2002-11-07 19:32:00 +01:00
|
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|
1991-12-06 03:11:44 +01:00
|
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|
#define FUNCTION_BOUNDARY 32
|
|
|
|
|
|
2001-05-12 16:58:47 +02:00
|
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/* The lowest bit is used to indicate Thumb-mode functions, so the
|
|
|
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|
vbit must go into the delta field of pointers to member
|
|
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|
|
functions. */
|
|
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|
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
|
|
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|
1991-12-06 03:11:44 +01:00
|
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|
#define EMPTY_FIELD_BOUNDARY 32
|
|
|
|
|
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
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|
|
#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
|
2003-06-25 20:49:51 +02:00
|
|
|
|
/* XXX Blah -- this macro is used directly by libobjc. Since it
|
|
|
|
|
supports no vector modes, cut out the complexity and fall back
|
|
|
|
|
on BIGGEST_FIELD_ALIGNMENT. */
|
|
|
|
|
#ifdef IN_TARGET_LIBS
|
2003-06-30 15:17:38 +02:00
|
|
|
|
#define BIGGEST_FIELD_ALIGNMENT 64
|
2003-06-25 20:49:51 +02:00
|
|
|
|
#endif
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* Make strings word-aligned so strcpy from constants will be faster. */
|
2003-10-19 03:01:46 +02:00
|
|
|
|
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
2000-12-04 01:23:35 +01:00
|
|
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
((TREE_CODE (EXP) == STRING_CST \
|
|
|
|
|
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
|
|
|
|
|
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
1999-10-28 11:28:04 +02:00
|
|
|
|
/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
|
|
|
|
|
value set in previous versions of this toolchain was 8, which produces more
|
|
|
|
|
compact structures. The command line option -mstructure_size_boundary=<n>
|
alpha.md, [...]: Fix spelling errors.
* config/alpha/alpha.md, config/arm/arm.c, config/arm/arm.h,
config/d30v/d30v.h, config/fr30/fr30.c, config/i370/x-oe,
config/i386/i386.c, config/i386/i386-interix.h,
config/i386/i386.md, config/i386/i386.h, config/i386/sco5.h,
config/i860/i860.h, config/i860/i860.md, config/m68k/aux-exit.c,
config/m68k/m68k.c, config/mcore/mcore.c, config/mips/mips.md,
config/ns32k/ns32k.h, config/pa/pa.c, config/rs6000/rs6000.c,
config/sparc/sparc.c, config/m68hc11/m68hc11.c,
config/cris/cris.c, config/cris/cris.h, config/s390/s390.c,
config/s390/s390.h, config/stormy16/stormy16.h, doc/tm.texi: Fix
spelling errors.
From-SVN: r46582
2001-10-28 14:22:02 +01:00
|
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|
|
can be used to change this value. For compatibility with the ARM SDK
|
1999-10-28 11:28:04 +02:00
|
|
|
|
however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
0020D) page 2-20 says "Structures are aligned on word boundaries".
|
|
|
|
|
The AAPCS specifies a value of 8. */
|
1999-10-27 20:31:35 +02:00
|
|
|
|
#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
|
|
|
|
|
extern int arm_structure_size_boundary;
|
1999-10-28 11:28:04 +02:00
|
|
|
|
|
2002-09-14 17:51:45 +02:00
|
|
|
|
/* This is the value used to initialize arm_structure_size_boundary. If a
|
1999-10-28 11:28:04 +02:00
|
|
|
|
particular arm target wants to change the default value it should change
|
2003-01-31 03:20:48 +01:00
|
|
|
|
the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
|
1999-10-28 11:28:04 +02:00
|
|
|
|
for an example of this. */
|
|
|
|
|
#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
|
|
|
|
|
#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
|
1998-10-27 12:13:39 +01:00
|
|
|
|
#endif
|
1998-10-27 16:15:11 +01:00
|
|
|
|
|
2002-09-18 01:10:04 +02:00
|
|
|
|
/* Nonzero if move instructions will actually fail to work
|
1993-10-03 17:33:02 +01:00
|
|
|
|
when given unaligned data. */
|
1991-12-06 03:11:44 +01:00
|
|
|
|
#define STRICT_ALIGNMENT 1
|
2004-05-10 15:39:20 +02:00
|
|
|
|
|
|
|
|
|
/* wchar_t is unsigned under the AAPCS. */
|
|
|
|
|
#ifndef WCHAR_TYPE
|
|
|
|
|
#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
|
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|
|
|
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|
|
#define WCHAR_TYPE_SIZE BITS_PER_WORD
|
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|
|
|
#endif
|
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|
|
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|
|
#ifndef SIZE_TYPE
|
|
|
|
|
#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
|
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|
|
|
#endif
|
2004-05-13 13:25:49 +02:00
|
|
|
|
|
|
|
|
|
/* AAPCS requires that structure alignment is affected by bitfields. */
|
|
|
|
|
#ifndef PCC_BITFIELD_TYPE_MATTERS
|
|
|
|
|
#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
|
|
|
|
|
#endif
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Standard register usage. */
|
|
|
|
|
|
|
|
|
|
/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
|
|
|
|
|
(S - saved over call).
|
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|
|
|
|
|
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|
|
r0 * argument word/integer result
|
|
|
|
|
r1-r3 argument word
|
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|
|
|
|
|
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|
|
r4-r8 S register variable
|
|
|
|
|
r9 S (rfp) register variable (real frame pointer)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1999-02-22 17:47:59 +01:00
|
|
|
|
r10 F S (sl) stack limit (used by -mapcs-stack-check)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
r11 F S (fp) argument pointer
|
|
|
|
|
r12 (ip) temp workspace
|
|
|
|
|
r13 F S (sp) lower end of current stack frame
|
|
|
|
|
r14 (lr) link address/workspace
|
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|
|
|
r15 F (pc) program counter
|
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|
|
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|
|
f0 floating point result
|
|
|
|
|
f1-f3 floating point scratch
|
|
|
|
|
|
|
|
|
|
f4-f7 S floating point variable
|
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
cc This is NOT a real register, but is used internally
|
|
|
|
|
to represent things that use or set the condition
|
|
|
|
|
codes.
|
|
|
|
|
sfp This isn't either. It is used during rtl generation
|
|
|
|
|
since the offset between the frame pointer and the
|
|
|
|
|
auto's isn't known until after register allocation.
|
|
|
|
|
afp Nor this, we only need this because of non-local
|
|
|
|
|
goto. Without it fp appears to be used and the
|
|
|
|
|
elimination code won't get rid of sfp. It tracks
|
|
|
|
|
fp exactly at all times.
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
*: See CONDITIONAL_REGISTER_USAGE */
|
|
|
|
|
|
2003-02-10 12:45:26 +01:00
|
|
|
|
/*
|
|
|
|
|
mvf0 Cirrus floating point result
|
|
|
|
|
mvf1-mvf3 Cirrus floating point scratch
|
|
|
|
|
mvf4-mvf15 S Cirrus floating point variable. */
|
|
|
|
|
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* s0-s15 VFP scratch (aka d0-d7).
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s16-s31 S VFP variable (aka d8-d15).
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vfpcc Not a real register. Represents the VFP condition
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code flags. */
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1993-10-03 17:33:02 +01:00
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/* The stack backtrace structure is as follows:
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fp points to here: | save code pointer | [fp]
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| return link value | [fp, #-4]
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| return sp value | [fp, #-8]
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| return fp value | [fp, #-12]
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[| saved r10 value |]
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[| saved r9 value |]
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[| saved r8 value |]
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[| saved r7 value |]
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[| saved r6 value |]
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[| saved r5 value |]
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[| saved r4 value |]
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[| saved r3 value |]
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[| saved r2 value |]
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[| saved r1 value |]
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[| saved r0 value |]
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[| saved f7 value |] three words
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[| saved f6 value |] three words
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[| saved f5 value |] three words
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[| saved f4 value |] three words
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r0-r3 are not normally saved in a C function. */
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1991-12-06 03:11:44 +01:00
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator. */
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define FIXED_REGISTERS \
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{ \
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0,0,0,0,0,0,0,0, \
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0,0,0,0,0,1,0,1, \
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0,0,0,0,0,0,0,0, \
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2003-02-10 12:45:26 +01:00
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1,1,1, \
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1,1,1,1,1,1,1,1, \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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1,1,1,1,1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1,1,1,1,1,1,1,1, \
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1 \
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1991-12-06 03:11:44 +01:00
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}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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registers that can be used without being saved.
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The latter must include the registers where values are returned
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and the register where structure-value addresses are passed.
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1993-10-03 17:33:02 +01:00
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Aside from that, you can include as many other registers as you like.
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2004-08-24 02:30:52 +02:00
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The CC is not preserved over function calls on the ARM 6, so it is
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2003-12-25 16:17:37 +01:00
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easier to assume this for all. SFP is preserved, since FP is. */
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1991-12-06 03:11:44 +01:00
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#define CALL_USED_REGISTERS \
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{ \
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1,1,1,1,0,0,0,0, \
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2000-04-08 16:29:53 +02:00
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0,0,0,0,1,1,1,1, \
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1993-10-03 17:33:02 +01:00
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1,1,1,1,0,0,0,0, \
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1,1,1, \
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1,1,1,1,1,1,1,1, \
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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1 \
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}
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1999-02-25 11:20:21 +01:00
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#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
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#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
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#endif
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#define CONDITIONAL_REGISTER_USAGE \
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{ \
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int regno; \
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\
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
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2000-04-08 16:29:53 +02:00
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{ \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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for (regno = FIRST_FPA_REGNUM; \
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regno <= LAST_FPA_REGNUM; ++regno) \
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2000-04-08 16:29:53 +02:00
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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} \
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2003-02-10 12:45:26 +01:00
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\
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arm.c (arm_rtx_costs_1, [...]): Adjust costs for comparing a constant with small negative numbers and add...
* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for
comparing a constant with small negative numbers and add costing
for constants in conjunction with AND.
(note_invalid_constants): Tidy previous change.
(thumb_cmp_operand): Tidy.
(thumb_cmpneg_operand): New function.
* arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing
for size.
(FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define.
(PREDICATE_CODES): Add thumb_cmpneg_operand.
* arm.md (cbranchsi4): Convert to define_expand. Handle comparison
with a negative constant.
(cbranchsi4_insn): Matcher for cbranchsi4.
(cbranchsi4_scratch): Similar, but a scratch is available for
handling negative constants.
(movsi_cbranchsi4): New pattern.
(tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch
and use the TST instruction.
(andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1)
(addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing
cannot see high regs or memory alternatives.
(bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns.
From-SVN: r72885
2003-10-24 11:25:30 +02:00
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if (TARGET_THUMB && optimize_size) \
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{ \
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/* When optimizing for size, it's better not to use \
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the HI regs, because of the overhead of stacking \
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2003-12-25 16:17:37 +01:00
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them. */ \
|
arm.c (arm_rtx_costs_1, [...]): Adjust costs for comparing a constant with small negative numbers and add...
* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for
comparing a constant with small negative numbers and add costing
for constants in conjunction with AND.
(note_invalid_constants): Tidy previous change.
(thumb_cmp_operand): Tidy.
(thumb_cmpneg_operand): New function.
* arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing
for size.
(FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define.
(PREDICATE_CODES): Add thumb_cmpneg_operand.
* arm.md (cbranchsi4): Convert to define_expand. Handle comparison
with a negative constant.
(cbranchsi4_insn): Matcher for cbranchsi4.
(cbranchsi4_scratch): Similar, but a scratch is available for
handling negative constants.
(movsi_cbranchsi4): New pattern.
(tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch
and use the TST instruction.
(andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1)
(addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing
cannot see high regs or memory alternatives.
(bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns.
From-SVN: r72885
2003-10-24 11:25:30 +02:00
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for (regno = FIRST_HI_REGNUM; \
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regno <= LAST_HI_REGNUM; ++regno) \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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} \
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\
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2003-10-31 22:42:23 +01:00
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/* The link register can be clobbered by any branch insn, \
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but we have no way to track that at present, so mark \
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it as unavailable. */ \
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if (TARGET_THUMB) \
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fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
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\
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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if (TARGET_ARM && TARGET_HARD_FLOAT) \
|
2003-02-10 12:45:26 +01:00
|
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{ \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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if (TARGET_MAVERICK) \
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2003-02-10 12:45:26 +01:00
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{ \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
for (regno = FIRST_FPA_REGNUM; \
|
|
|
|
|
regno <= LAST_FPA_REGNUM; ++ regno) \
|
|
|
|
|
fixed_regs[regno] = call_used_regs[regno] = 1; \
|
|
|
|
|
for (regno = FIRST_CIRRUS_FP_REGNUM; \
|
|
|
|
|
regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
|
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[regno] = 0; \
|
|
|
|
|
call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
if (TARGET_VFP) \
|
|
|
|
|
{ \
|
|
|
|
|
for (regno = FIRST_VFP_REGNUM; \
|
|
|
|
|
regno <= LAST_VFP_REGNUM; ++ regno) \
|
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[regno] = 0; \
|
|
|
|
|
call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
|
|
|
|
|
} \
|
2003-02-10 12:45:26 +01:00
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
\
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
if (TARGET_REALLY_IWMMXT) \
|
|
|
|
|
{ \
|
|
|
|
|
regno = FIRST_IWMMXT_GR_REGNUM; \
|
|
|
|
|
/* The 2002/10/09 revision of the XScale ABI has wCG0 \
|
|
|
|
|
and wCG1 as call-preserved registers. The 2002/11/21 \
|
|
|
|
|
revision changed this so that all wCG registers are \
|
|
|
|
|
scratch registers. */ \
|
|
|
|
|
for (regno = FIRST_IWMMXT_GR_REGNUM; \
|
|
|
|
|
regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
|
2005-03-15 18:45:55 +01:00
|
|
|
|
fixed_regs[regno] = 0; \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
/* The XScale ABI has wR0 - wR9 as scratch registers, \
|
|
|
|
|
the rest as call-preserved registers. */ \
|
|
|
|
|
for (regno = FIRST_IWMMXT_REGNUM; \
|
|
|
|
|
regno <= LAST_IWMMXT_REGNUM; ++ regno) \
|
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[regno] = 0; \
|
|
|
|
|
call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
\
|
2003-01-16 16:13:33 +01:00
|
|
|
|
if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
|
|
|
|
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
|
|
|
|
} \
|
|
|
|
|
else if (TARGET_APCS_STACK) \
|
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[10] = 1; \
|
|
|
|
|
call_used_regs[10] = 1; \
|
|
|
|
|
} \
|
2004-10-14 09:37:11 +02:00
|
|
|
|
/* -mcaller-super-interworking reserves r11 for calls to \
|
|
|
|
|
_interwork_r11_call_via_rN(). Making the register global \
|
|
|
|
|
is an easy way of ensuring that it remains valid for all \
|
|
|
|
|
calls. */ \
|
2005-04-27 20:33:37 +02:00
|
|
|
|
if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
|
config.gcc (arm*-wince-pe*, [...]): Add arm/pe.opt to $extra_options.
* config.gcc (arm*-wince-pe*, arm-*-pe*, strongarm-*-pe): Add
arm/pe.opt to $extra_options.
* config/arm/arm.h (target_flags, target_fpu_name, target_fpe_name)
(target_float_abi_name, target_float_switch, target_abi_name)
(ARM_FLAG_APCS_FRAME, ARM_FLAG_POKE, ARM_FLAG_FPE, ARM_FLAG_APCS_STACK)
(ARM_FLAG_APCS_FLOAT, ARM_FLAG_APCS_REENT, ARM_FLAG_BIG_END)
(ARM_FLAG_INTERWORK, ARM_FLAG_LITTLE_WORDS, ARM_FLAG_NO_SCHED_PRO)
(ARM_FLAG_ABORT_NORETURN, ARM_FLAG_SINGLE_PIC_BASE)
(ARM_FLAG_LONG_CALLS, ARM_FLAG_THUMB, THUMB_FLAG_BACKTRACE)
(THUMB_FLAG_LEAF_BACKTRACE, THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
(THUMB_FLAG_CALLER_SUPER_INTERWORKING, CIRRUS_FIX_INVALID_INSNS)
(TARGET_APCS_FRAME, TARGET_POKE_FUNCTION_NAME, TARGET_FPE)
(TARGET_APCS_STACK, TARGET_APCS_FLOAT, TARGET_APCS_REENT)
(TARGET_BIG_END, TARGET_INTERWORK, TARGET_LITTLE_WORDS)
(TARGET_NO_SCHED_PRO, TARGET_ABORT_NORETURN, TARGET_SINGLE_PIC_BASE)
(TARGET_LONG_CALLS, TARGET_THUMB, TARGET_CALLER_INTERWORKING)
(TARGET_CIRRUS_FIX_INVALID_INSNS, SUBTARGET_SWITCHES, TARGET_SWITCHES)
(TARGET_OPTIONS, arm_cpu_select, arm_select, structure_size_string)
(arm_pic_register_string): Delete.
(TARGET_BACKTRACE): Redefine using TARGET_TPCS_LEAF_FRAME and
TARGET_TPCS_FRAME.
(TARGET_DEFAULT, CONDITIONAL_REGISTER_USAGE): Update mask names.
* config/arm/coff.h (TARGET_DEFAULT): Likewise.
* config/arm/elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/netbsd.h (TARGET_DEFAULT): Likewise.
* config/arm/semi.h (TARGET_DEFAULT): Likewise.
* config/arm/uclinux-elf.h (TARGET_DEFAULT): Likewise.
* config/arm/wince-pe.h (TARGET_DEFAULT): Likewise.
* config/arm/pe.h (TARGET_DEFAULT): Likewise.
(TARGET_FLAG_NOP_FUN, TARGET_NOP_FUN_DLLIMPORT): Delete.
(SUBTARGET_SWITCHES): Delete.
* config/arm/arm.c (target_float_switch): Delete.
(arm_cpu_select): Moved from config/arm/arm.h.
(target_fpu_name, target_fpe_name, target_float_abi_name)
(target_abi_name, structure_size_string, arm_pic_register_string)
(arm_select): Make static.
(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
(arm_handle_option): New function.
(arm_override_options): Update target_flags checks for new mask names.
Remove target_float_switch code.
(arm_expand_prologue, thumb_expand_prologue): Check
!TARGET_SCHED_PROLOG instead of TARGET_NO_SCHED_PRO.
* config/arm/arm.opt, config/arm/pe.opt: New files.
From-SVN: r99265
2005-05-05 14:09:00 +02:00
|
|
|
|
|| TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
{ \
|
|
|
|
|
fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
|
|
|
|
call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
2004-10-14 09:37:11 +02:00
|
|
|
|
if (TARGET_CALLER_INTERWORKING) \
|
|
|
|
|
global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
} \
|
|
|
|
|
SUBTARGET_CONDITIONAL_REGISTER_USAGE \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
}
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
2003-01-31 03:20:48 +01:00
|
|
|
|
/* These are a couple of extensions to the formats accepted
|
1999-07-26 12:59:55 +02:00
|
|
|
|
by asm_fprintf:
|
|
|
|
|
%@ prints out ASM_COMMENT_START
|
|
|
|
|
%r prints out REGISTER_PREFIX reg_names[arg] */
|
|
|
|
|
#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
|
|
|
|
|
case '@': \
|
|
|
|
|
fputs (ASM_COMMENT_START, FILE); \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
|
|
|
|
case 'r': \
|
|
|
|
|
fputs (REGISTER_PREFIX, FILE); \
|
|
|
|
|
fputs (reg_names [va_arg (ARGS, int)], FILE); \
|
|
|
|
|
break;
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Round X up to the nearest word. */
|
2003-01-16 16:22:54 +01:00
|
|
|
|
#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
1999-07-17 15:44:35 +02:00
|
|
|
|
/* Convert fron bytes to ints. */
|
2002-07-17 11:54:11 +02:00
|
|
|
|
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
1999-07-17 15:44:35 +02:00
|
|
|
|
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* The number of (integer) registers required to hold a quantity of type MODE.
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Also used for VFP registers. */
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2002-07-17 11:54:11 +02:00
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#define ARM_NUM_REGS(MODE) \
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ARM_NUM_INTS (GET_MODE_SIZE (MODE))
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1999-07-17 15:44:35 +02:00
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/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
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2002-07-17 11:54:11 +02:00
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#define ARM_NUM_REGS2(MODE, TYPE) \
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ARM_NUM_INTS ((MODE) == BLKmode ? \
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2000-04-08 16:29:53 +02:00
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int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
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1999-07-17 15:44:35 +02:00
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/* The number of (integer) argument register available. */
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2000-04-08 16:29:53 +02:00
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#define NUM_ARG_REGS 4
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1999-07-17 15:44:35 +02:00
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2003-07-02 01:26:43 +02:00
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/* Return the register number of the N'th (integer) argument. */
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2000-04-08 16:29:53 +02:00
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#define ARG_REGISTER(N) (N - 1)
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1999-07-17 15:44:35 +02:00
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2000-04-08 16:29:53 +02:00
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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1991-12-06 03:11:44 +01:00
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2000-04-08 16:29:53 +02:00
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/* The number of the last argument register. */
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#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
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1991-12-06 03:11:44 +01:00
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arm.c (arm_rtx_costs_1, [...]): Adjust costs for comparing a constant with small negative numbers and add...
* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for
comparing a constant with small negative numbers and add costing
for constants in conjunction with AND.
(note_invalid_constants): Tidy previous change.
(thumb_cmp_operand): Tidy.
(thumb_cmpneg_operand): New function.
* arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing
for size.
(FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define.
(PREDICATE_CODES): Add thumb_cmpneg_operand.
* arm.md (cbranchsi4): Convert to define_expand. Handle comparison
with a negative constant.
(cbranchsi4_insn): Matcher for cbranchsi4.
(cbranchsi4_scratch): Similar, but a scratch is available for
handling negative constants.
(movsi_cbranchsi4): New pattern.
(tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch
and use the TST instruction.
(andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1)
(addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing
cannot see high regs or memory alternatives.
(bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns.
From-SVN: r72885
2003-10-24 11:25:30 +02:00
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/* The numbers of the Thumb register ranges. */
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#define FIRST_LO_REGNUM 0
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2000-12-08 20:25:33 +01:00
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#define LAST_LO_REGNUM 7
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arm.c (arm_rtx_costs_1, [...]): Adjust costs for comparing a constant with small negative numbers and add...
* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for
comparing a constant with small negative numbers and add costing
for constants in conjunction with AND.
(note_invalid_constants): Tidy previous change.
(thumb_cmp_operand): Tidy.
(thumb_cmpneg_operand): New function.
* arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing
for size.
(FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define.
(PREDICATE_CODES): Add thumb_cmpneg_operand.
* arm.md (cbranchsi4): Convert to define_expand. Handle comparison
with a negative constant.
(cbranchsi4_insn): Matcher for cbranchsi4.
(cbranchsi4_scratch): Similar, but a scratch is available for
handling negative constants.
(movsi_cbranchsi4): New pattern.
(tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch
and use the TST instruction.
(andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1)
(addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing
cannot see high regs or memory alternatives.
(bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns.
From-SVN: r72885
2003-10-24 11:25:30 +02:00
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#define FIRST_HI_REGNUM 8
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#define LAST_HI_REGNUM 11
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2000-12-08 20:25:33 +01:00
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arm-protos.h (arm_set_return_address, [...]): Add prototypes.
* config/arm/arm-protos.h (arm_set_return_address,
thumb_set_return_address): Add prototypes.
* config/arm/arm.h (ARM_FT_EXCEPTION_HANDLER): Remove.
* config/arm/arm.c (arm_compute_func_type,
use_return_insn, arm_compute_save_reg0_reg12_mask,
arm_compute_save_reg_mask, arm_output_function_prologue,
arm_output_epilogue): Replace ARM_FT_EXCEPTION_HANDLER with
current_function_calls_eh_return.
(thumb_exit, thumb_pushpop, thumb_unexpanded_epilogue): Replace
old eh code.
(arm_set_return_address, thumb_set_return_address): New functions.
* config/arm/arm.h (MUST_USE_SJLJ_EXCEPTIONS, DWARF2_UNWIND_INFO,
ARM_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX): Define.
* config/arm/arm.md (VUNSPEC_EH_RETURN): Add.
(epilogue): Use the stackadj register.
(eh_return, arm_eh_return, thumb_eh_return): New pattern.
From-SVN: r85757
2004-08-10 18:22:47 +02:00
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/* We use sjlj exceptions for backwards compatibility. */
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#define MUST_USE_SJLJ_EXCEPTIONS 1
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/* We can generate DWARF2 Unwind info, even though we don't use it. */
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#define DWARF2_UNWIND_INFO 1
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2004-08-24 02:30:52 +02:00
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arm-protos.h (arm_set_return_address, [...]): Add prototypes.
* config/arm/arm-protos.h (arm_set_return_address,
thumb_set_return_address): Add prototypes.
* config/arm/arm.h (ARM_FT_EXCEPTION_HANDLER): Remove.
* config/arm/arm.c (arm_compute_func_type,
use_return_insn, arm_compute_save_reg0_reg12_mask,
arm_compute_save_reg_mask, arm_output_function_prologue,
arm_output_epilogue): Replace ARM_FT_EXCEPTION_HANDLER with
current_function_calls_eh_return.
(thumb_exit, thumb_pushpop, thumb_unexpanded_epilogue): Replace
old eh code.
(arm_set_return_address, thumb_set_return_address): New functions.
* config/arm/arm.h (MUST_USE_SJLJ_EXCEPTIONS, DWARF2_UNWIND_INFO,
ARM_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX): Define.
* config/arm/arm.md (VUNSPEC_EH_RETURN): Add.
(epilogue): Use the stackadj register.
(eh_return, arm_eh_return, thumb_eh_return): New pattern.
From-SVN: r85757
2004-08-10 18:22:47 +02:00
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/* Use r0 and r1 to pass exception handling information. */
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#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
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2000-12-08 20:25:33 +01:00
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/* The register that holds the return address in exception handlers. */
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arm-protos.h (arm_set_return_address, [...]): Add prototypes.
* config/arm/arm-protos.h (arm_set_return_address,
thumb_set_return_address): Add prototypes.
* config/arm/arm.h (ARM_FT_EXCEPTION_HANDLER): Remove.
* config/arm/arm.c (arm_compute_func_type,
use_return_insn, arm_compute_save_reg0_reg12_mask,
arm_compute_save_reg_mask, arm_output_function_prologue,
arm_output_epilogue): Replace ARM_FT_EXCEPTION_HANDLER with
current_function_calls_eh_return.
(thumb_exit, thumb_pushpop, thumb_unexpanded_epilogue): Replace
old eh code.
(arm_set_return_address, thumb_set_return_address): New functions.
* config/arm/arm.h (MUST_USE_SJLJ_EXCEPTIONS, DWARF2_UNWIND_INFO,
ARM_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX): Define.
* config/arm/arm.md (VUNSPEC_EH_RETURN): Add.
(epilogue): Use the stackadj register.
(eh_return, arm_eh_return, thumb_eh_return): New pattern.
From-SVN: r85757
2004-08-10 18:22:47 +02:00
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#define ARM_EH_STACKADJ_REGNUM 2
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#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
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1991-12-06 03:11:44 +01:00
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2000-04-08 16:29:53 +02:00
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/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
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as an invisible last argument (possible since varargs don't exist in
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Pascal), so the following is not true. */
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2000-11-16 20:23:15 +01:00
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#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
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1991-12-06 03:11:44 +01:00
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2000-04-08 16:29:53 +02:00
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/* Define this to be where the real frame pointer is if it is not possible to
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work out the offset between the frame pointer and the automatic variables
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until after register allocation has taken place. FRAME_POINTER_REGNUM
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should point to a special register that we will make sure is eliminated.
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For the Thumb we have another problem. The TPCS defines the frame pointer
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2003-01-31 03:20:48 +01:00
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as r11, and GCC believes that it is always possible to use the frame pointer
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2000-04-08 16:29:53 +02:00
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as base register for addressing purposes. (See comments in
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find_reloads_address()). But - the Thumb does not allow high registers,
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including r11, to be used as base address registers. Hence our problem.
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The solution used here, and in the old thumb port is to use r7 instead of
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r11 as the hard frame pointer and to have special code to generate
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backtrace structures on the stack (if required to do so via a command line
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2003-01-31 03:20:48 +01:00
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option) using r11. This is the only 'user visible' use of r11 as a frame
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2000-04-08 16:29:53 +02:00
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pointer. */
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#define ARM_HARD_FRAME_POINTER_REGNUM 11
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#define THUMB_HARD_FRAME_POINTER_REGNUM 7
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1991-12-06 03:11:44 +01:00
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2001-01-08 16:33:06 +01:00
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#define HARD_FRAME_POINTER_REGNUM \
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(TARGET_ARM \
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? ARM_HARD_FRAME_POINTER_REGNUM \
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: THUMB_HARD_FRAME_POINTER_REGNUM)
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2000-04-08 16:29:53 +02:00
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2001-01-08 16:33:06 +01:00
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#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
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2000-04-08 16:29:53 +02:00
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2001-01-08 16:33:06 +01:00
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM SP_REGNUM
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2000-04-08 16:29:53 +02:00
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/* ARM floating pointer registers. */
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define FIRST_FPA_REGNUM 16
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#define LAST_FPA_REGNUM 23
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2005-03-29 05:00:27 +02:00
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#define IS_FPA_REGNUM(REGNUM) \
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(((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
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2000-04-08 16:29:53 +02:00
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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#define FIRST_IWMMXT_GR_REGNUM 43
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#define LAST_IWMMXT_GR_REGNUM 46
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#define FIRST_IWMMXT_REGNUM 47
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#define LAST_IWMMXT_REGNUM 62
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#define IS_IWMMXT_REGNUM(REGNUM) \
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(((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
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#define IS_IWMMXT_GR_REGNUM(REGNUM) \
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(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
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1991-12-06 03:11:44 +01:00
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/* Base register for access to local variables of the function. */
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1993-10-03 17:33:02 +01:00
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#define FRAME_POINTER_REGNUM 25
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2000-04-08 16:29:53 +02:00
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 26
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1999-07-05 10:44:36 +02:00
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2003-02-10 12:45:26 +01:00
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#define FIRST_CIRRUS_FP_REGNUM 27
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#define LAST_CIRRUS_FP_REGNUM 42
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#define IS_CIRRUS_REGNUM(REGNUM) \
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(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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#define FIRST_VFP_REGNUM 63
|
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#define LAST_VFP_REGNUM 94
|
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|
#define IS_VFP_REGNUM(REGNUM) \
|
|
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|
(((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
|
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2003-03-12 13:38:35 +01:00
|
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/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
|
|
|
|
|
/* + 16 Cirrus registers take us up to 43. */
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
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|
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* VFP adds 32 + 1 more. */
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#define FIRST_PSEUDO_REGISTER 96
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1999-07-05 10:44:36 +02:00
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2005-03-29 05:00:27 +02:00
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#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
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1991-12-06 03:11:44 +01:00
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/* Value should be nonzero if functions must have frame pointers.
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Zero means the frame pointer need not be set up (and parms may be accessed
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2004-08-24 02:30:52 +02:00
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via the stack pointer) in functions that seem suitable.
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1993-10-03 17:33:02 +01:00
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If we have to have a frame pointer we might as well make use of it.
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APCS says that the frame pointer does not need to be pushed in leaf
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1998-10-27 16:15:11 +01:00
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functions, or simple tail call functions. */
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2001-06-24 11:46:02 +02:00
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#define FRAME_POINTER_REQUIRED \
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(current_function_has_nonlocal_label \
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2000-04-08 16:29:53 +02:00
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|| (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
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1991-12-06 03:11:44 +01:00
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2000-04-08 16:29:53 +02:00
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/* Return number of consecutive hard regs needed starting at reg REGNO
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to hold something of mode MODE.
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers.
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1991-12-06 03:11:44 +01:00
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2003-03-08 17:23:20 +01:00
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On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
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2000-04-08 16:29:53 +02:00
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mode. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((TARGET_ARM \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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&& REGNO >= FIRST_FPA_REGNUM \
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&& REGNO != FRAME_POINTER_REGNUM \
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&& REGNO != ARG_POINTER_REGNUM) \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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&& !IS_VFP_REGNUM (REGNO) \
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2002-07-17 11:54:11 +02:00
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? 1 : ARM_NUM_REGS (MODE))
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2002-01-22 18:35:27 +01:00
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/* Return true if REGNO is suitable for holding a quantity of type MODE. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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arm_hard_regno_mode_ok ((REGNO), (MODE))
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/* Value is 1 if it is a good idea to tie two pseudo registers
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when one has mode MODE1 and one has mode MODE2.
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If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
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for any hard reg, then this must be 0 for correct output. */
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#define MODES_TIEABLE_P(MODE1, MODE2) \
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(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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#define VALID_IWMMXT_REG_MODE(MODE) \
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2004-08-24 02:30:52 +02:00
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(arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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1991-12-06 03:11:44 +01:00
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/* The order in which register should be allocated. It is good to use ip
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1993-10-03 17:33:02 +01:00
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since no saving is required (though calls clobber it) and it never contains
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function parameters. It is quite good to use lr since other calls may
|
2004-08-24 02:30:52 +02:00
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clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
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1993-10-03 17:33:02 +01:00
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least likely to contain a function parameter; in addition results are
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2000-04-08 16:29:53 +02:00
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returned in r0. */
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define REG_ALLOC_ORDER \
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{ \
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1998-06-25 11:55:35 +02:00
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3, 2, 1, 0, 12, 14, 4, 5, \
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6, 7, 8, 10, 9, 11, 13, 15, \
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1993-10-03 17:33:02 +01:00
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16, 17, 18, 19, 20, 21, 22, 23, \
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27, 28, 29, 30, 31, 32, 33, 34, \
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35, 36, 37, 38, 39, 40, 41, 42, \
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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1991-12-06 03:11:44 +01:00
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}
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2002-02-20 22:39:56 +01:00
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/* Interrupt functions can only use registers that have already been
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saved by the prologue, even if they would normally be
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call-clobbered. */
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#define HARD_REGNO_RENAME_OK(SRC, DST) \
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(! IS_INTERRUPT (cfun->machine->func_type) || \
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regs_ever_live[DST])
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/* Register and constant classes. */
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2003-03-08 17:23:20 +01:00
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/* Register classes: used to be simple, just all ARM regs or all FPA regs
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ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.3, ChangeLog.5, ChangeLog, alias.c,
cfgbuild.c, expmed.c, expr.c, final.c, flow.c, fold-const.c,
function.c, config/alpha/alpha.md, config/alpha/vms-ld.c,
config/arm/arm.c, config/arm/arm.h, config/c4x/libgcc.S,
config/i370/i370.c, config/i386/i386.c,
config/i386/i386-interix.h, config/i386/i386.md,
config/i386/i386.h, config/i386/netbsd-elf.h, config/ia64/ia64.c,
config/m32r/m32r-protos.h, config/mcore/mcore.h,
config/rs6000/rs6000.h, config/sparc/linux64.h,
config/sparc/sparc.c, config/v850/v850-protos.h,
config/cris/cris.h, config/s390/s390.md, config/elfos.h: Fix
spelling errors.
From-SVN: r47815
2001-12-09 21:13:19 +01:00
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Now that the Thumb is involved it has become more complicated. */
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enum reg_class
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{
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NO_REGS,
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FPA_REGS,
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CIRRUS_REGS,
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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VFP_REGS,
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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IWMMXT_GR_REGS,
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IWMMXT_REGS,
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2000-04-08 16:29:53 +02:00
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LO_REGS,
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STACK_REG,
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BASE_REGS,
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HI_REGS,
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CC_REG,
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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VFPCC_REG,
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1991-12-06 03:11:44 +01:00
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GENERAL_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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2003-12-25 16:17:37 +01:00
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/* Give names of register classes as strings for dump file. */
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1991-12-06 03:11:44 +01:00
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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2003-03-08 17:23:20 +01:00
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"FPA_REGS", \
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2003-02-10 12:45:26 +01:00
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"CIRRUS_REGS", \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
"VFP_REGS", \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
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"IWMMXT_GR_REGS", \
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"IWMMXT_REGS", \
|
2000-04-08 16:29:53 +02:00
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"LO_REGS", \
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"STACK_REG", \
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"BASE_REGS", \
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"HI_REGS", \
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"CC_REG", \
|
2004-02-05 07:11:05 +01:00
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"VFPCC_REG", \
|
1991-12-06 03:11:44 +01:00
|
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"GENERAL_REGS", \
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"ALL_REGS", \
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}
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/* Define which registers fit in which classes.
|
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This is an initializer for a vector of HARD_REG_SET
|
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of length N_REG_CLASSES. */
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
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{ 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
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{ 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
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|
{ 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
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{ 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
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{ 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
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{ 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
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{ 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
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{ 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
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{ 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
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{ 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
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{ 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
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{ 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
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{ 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
|
1991-12-06 03:11:44 +01:00
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}
|
2002-01-22 18:35:27 +01:00
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1991-12-06 03:11:44 +01:00
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/* The same information, inverted:
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Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array. */
|
2000-04-08 16:29:53 +02:00
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#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
|
1991-12-06 03:11:44 +01:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* FPA registers can't do subreg as all values are reformatted to internal
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alpha.c, [...]: Fix comment typos.
* config/alpha/alpha.c, config/arc/arc.c,
config/arm/arm-cores.def, config/arm/arm.c, config/arm/arm.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/arm926ejs.md, config/arm/vfp.md, config/avr/avr.c,
config/c4x/c4x.c, config/cris/cris.c, config/frv/frv.md,
config/i386/i386.c, config/i386/i386.h, config/i386/i386.md,
config/ia64/ia64.c, config/ia64/unwind-ia64.c,
config/iq2000/iq2000.c, config/m32r/m32r.c,
config/mips/mips.c, config/mmix/mmix.c, config/mmix/mmix.h,
config/ns32k/ns32k.c, config/pa/pa.c, config/pdp11/pdp11.c,
config/rs6000/darwin-ldouble.c, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/sparc/sparc.c,
config/vax/vax.c: Fix comment typos. Follow spelling
conventions.
From-SVN: r77267
2004-02-04 20:46:25 +01:00
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precision. VFP registers may only be accessed in the mode they
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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were set. */
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2003-06-14 17:54:02 +02:00
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#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
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|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
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: 0)
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2003-06-14 17:54:02 +02:00
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2004-04-08 21:02:24 +02:00
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/* We need to define this for LO_REGS on thumb. Otherwise we can end up
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using r0-r4 for function arguments, r7 for the stack frame and don't
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have enough left over to do doubleword arithmetic. */
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#define CLASS_LIKELY_SPILLED_P(CLASS) \
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((TARGET_THUMB && (CLASS) == LO_REGS) \
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|| (CLASS) == CC_REG)
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2004-08-24 02:30:52 +02:00
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1991-12-06 03:11:44 +01:00
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/* The class value for index registers, and the one for base regs. */
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2000-04-08 16:29:53 +02:00
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#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
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2002-09-30 13:18:38 +02:00
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#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
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2000-04-08 16:29:53 +02:00
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2002-09-30 13:18:38 +02:00
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|
|
/* For the Thumb the high registers cannot be used as base registers
|
2003-01-31 03:20:48 +01:00
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|
|
when addressing quantities in QI or HI mode; if we don't know the
|
2004-10-12 21:28:56 +02:00
|
|
|
|
mode, then we must be conservative. */
|
2001-12-17 17:46:11 +01:00
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|
|
|
#define MODE_BASE_REG_CLASS(MODE) \
|
2002-09-30 13:18:38 +02:00
|
|
|
|
(TARGET_ARM ? GENERAL_REGS : \
|
2004-10-12 21:28:56 +02:00
|
|
|
|
(((MODE) == SImode) ? BASE_REGS : LO_REGS))
|
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/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
|
|
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instead of BASE_REGS. */
|
|
|
|
|
#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
|
2001-12-17 17:46:11 +01:00
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2000-04-08 16:29:53 +02:00
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/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
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|
registers explicitly used in the rtl to be used as spill registers
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|
but prevents the compiler from extending the lifetime of these
|
2003-12-25 16:17:37 +01:00
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registers. */
|
2000-04-08 16:29:53 +02:00
|
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#define SMALL_REGISTER_CLASSES TARGET_THUMB
|
1991-12-06 03:11:44 +01:00
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/* Get reg_class from a letter such as appears in the machine description.
|
2003-03-08 17:23:20 +01:00
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We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
|
2000-04-08 16:29:53 +02:00
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|
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|
ARM, but several more letters for the Thumb. */
|
|
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|
#define REG_CLASS_FROM_LETTER(C) \
|
2003-03-08 17:23:20 +01:00
|
|
|
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( (C) == 'f' ? FPA_REGS \
|
2003-02-10 12:45:26 +01:00
|
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|
|
: (C) == 'v' ? CIRRUS_REGS \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
: (C) == 'w' ? VFP_REGS \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
: (C) == 'y' ? IWMMXT_REGS \
|
|
|
|
|
: (C) == 'z' ? IWMMXT_GR_REGS \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
: (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
|
|
|
|
|
: TARGET_ARM ? NO_REGS \
|
|
|
|
|
: (C) == 'h' ? HI_REGS \
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|
|
|
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: (C) == 'b' ? BASE_REGS \
|
|
|
|
|
: (C) == 'k' ? STACK_REG \
|
|
|
|
|
: (C) == 'c' ? CC_REG \
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|
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: NO_REGS)
|
1991-12-06 03:11:44 +01:00
|
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|
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/* The letters I, J, K, L and M in a register constraint string
|
|
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can be used to stand for particular ranges of immediate operands.
|
|
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|
This macro defines what the ranges are.
|
|
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|
C is the letter, and VALUE is a constant value.
|
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Return 1 if VALUE is in the range specified by C.
|
1992-03-14 06:17:01 +01:00
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I: immediate arithmetic operand (i.e. 8 bits shifted as required).
|
2004-08-24 02:30:52 +02:00
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J: valid indexing constants.
|
1994-06-03 15:17:55 +02:00
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K: ~value ok in rhs argument of data operand.
|
2004-08-24 02:30:52 +02:00
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L: -value ok in rhs argument of data operand.
|
1994-06-23 18:02:41 +02:00
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M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
|
2000-04-08 16:29:53 +02:00
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#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
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1994-06-03 15:17:55 +02:00
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((C) == 'I' ? const_ok_for_arm (VALUE) : \
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(C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
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(C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
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1994-06-23 18:02:41 +02:00
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(C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
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(C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
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|| (((VALUE) & ((VALUE) - 1)) == 0)) \
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: 0)
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1993-10-03 17:33:02 +01:00
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2000-04-08 16:29:53 +02:00
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#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
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((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
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(C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
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(C) == 'K' ? thumb_shiftable_const (VAL) : \
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(C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
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(C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
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&& ((VAL) & 3) == 0) : \
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(C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
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(C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
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: 0)
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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(TARGET_ARM ? \
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CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
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2004-08-24 02:30:52 +02:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
/* Constant letter 'G' for the FP immediate constants.
|
2000-04-08 16:29:53 +02:00
|
|
|
|
'H' means the same constant negated. */
|
|
|
|
|
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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((C) == 'G' ? arm_const_double_rtx (X) : \
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2003-03-08 17:23:20 +01:00
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(C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
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#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
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(TARGET_ARM ? \
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CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
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/* For the ARM, `Q' means that this is a memory operand that is just
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an offset from a register.
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1993-10-03 17:33:02 +01:00
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`S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
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address. This means that the symbol is in the text segment and can be
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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accessed without using a load.
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2004-11-20 12:21:55 +01:00
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'D' Prefixes a number of const_double operands where:
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'Da' is a constant that takes two ARM insns to load.
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'Db' takes three ARM insns.
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'Dc' takes four ARM insns, if we allow that in this compilation.
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2004-03-14 01:23:03 +01:00
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'U' Prefixes an extended memory constraint where:
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2004-08-24 02:30:52 +02:00
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'Uv' is an address valid for VFP load/store insns.
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'Uy' is an address valid for iwmmxt load/store insns.
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2004-03-14 01:23:03 +01:00
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'Uq' is an address valid for ldrsb. */
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1993-10-03 17:33:02 +01:00
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2004-11-20 12:21:55 +01:00
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#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
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2005-04-07 13:24:11 +02:00
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(((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
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|| GET_CODE (OP) == CONST_INT \
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|| GET_CODE (OP) == CONST_VECTOR) \
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2004-11-20 12:21:55 +01:00
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&& (((STR)[1] == 'a' \
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&& arm_const_double_inline_cost (OP) == 2) \
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|| ((STR)[1] == 'b' \
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&& arm_const_double_inline_cost (OP) == 3) \
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|| ((STR)[1] == 'c' \
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&& arm_const_double_inline_cost (OP) == 4 \
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&& !(optimize_size || arm_ld_sched)))) : \
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((C) == 'Q') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == REG) : \
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((C) == 'R') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
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&& CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
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((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
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((C) == 'T') ? cirrus_memory_offset (OP) : \
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2004-05-06 01:11:55 +02:00
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((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
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((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
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2004-11-20 12:21:55 +01:00
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((C) == 'U' && (STR)[1] == 'q') \
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? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
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: 0)
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2004-03-13 12:19:23 +01:00
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#define CONSTRAINT_LEN(C,STR) \
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2004-11-20 12:21:55 +01:00
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(((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
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1993-10-03 17:33:02 +01:00
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2000-04-08 16:29:53 +02:00
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#define EXTRA_CONSTRAINT_THUMB(X, C) \
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((C) == 'Q' ? (GET_CODE (X) == MEM \
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&& GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
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2004-03-13 12:19:23 +01:00
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#define EXTRA_CONSTRAINT_STR(X, C, STR) \
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(TARGET_ARM \
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? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
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: EXTRA_CONSTRAINT_THUMB (X, C))
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1991-12-06 03:11:44 +01:00
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
|
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|
1991-12-06 03:11:44 +01:00
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/* Given an rtx X being reloaded into a reg required to be
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in class CLASS, return the class of reg to actually use.
|
2000-04-08 16:29:53 +02:00
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In general this is just CLASS, but for the Thumb we prefer
|
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a LO_REGS class or a subset. */
|
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#define PREFERRED_RELOAD_CLASS(X, CLASS) \
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(TARGET_ARM ? (CLASS) : \
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((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
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|
|
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/* Must leave BASE_REGS reloads alone */
|
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|
#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
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((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
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? ((true_regnum (X) == -1 ? LO_REGS \
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: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
|
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: NO_REGS)) \
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: NO_REGS)
|
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#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
2004-06-23 12:39:50 +02:00
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((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
|
2000-04-08 16:29:53 +02:00
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? ((true_regnum (X) == -1 ? LO_REGS \
|
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: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
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: NO_REGS)) \
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: NO_REGS)
|
1991-12-06 03:11:44 +01:00
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1993-10-03 17:33:02 +01:00
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/* Return the register class of a scratch register needed to copy IN into
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or out of a register in CLASS in MODE. If it can be done directly,
|
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NO_REGS is returned. */
|
2000-04-08 16:29:53 +02:00
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#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Restrict which direct reloads are allowed for VFP regs. */ \
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((TARGET_VFP && TARGET_HARD_FLOAT \
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&& (CLASS) == VFP_REGS) \
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? vfp_secondary_reload_class (MODE, X) \
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: TARGET_ARM \
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? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
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2000-04-08 16:29:53 +02:00
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? GENERAL_REGS : NO_REGS) \
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: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
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2004-08-24 02:30:52 +02:00
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2003-12-25 16:17:37 +01:00
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/* If we need to load shorts byte-at-a-time, then we need a scratch. */
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2000-04-08 16:29:53 +02:00
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#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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/* Restrict which direct reloads are allowed for VFP regs. */ \
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((TARGET_VFP && TARGET_HARD_FLOAT \
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&& (CLASS) == VFP_REGS) \
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? vfp_secondary_reload_class (MODE, X) : \
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2003-02-10 12:45:26 +01:00
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/* Cannot load constants into Cirrus registers. */ \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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(TARGET_MAVERICK && TARGET_HARD_FLOAT \
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2003-02-10 12:45:26 +01:00
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&& (CLASS) == CIRRUS_REGS \
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&& (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
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? GENERAL_REGS : \
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2000-04-08 16:29:53 +02:00
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(TARGET_ARM ? \
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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(((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
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&& CONSTANT_P (X)) \
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? GENERAL_REGS : \
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arm.h (TARGET_APCS_32): Delete.
* arm.h (TARGET_APCS_32): Delete.
(TARGET_MMU_TRAPS): Delete.
(TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never
define __APCS_26__.
(CPP_SPEC): Remove checking of -mapcs-{26,32}.
(ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete.
(TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches.
(prog_mode_type): Delete.
(PROMOTE_MODE): Always promote unsigned for HImode.
(SECONDARY_INPUT_RELOAD_CLASS): Simplify.
(MASK_RETURN_ADDR): Simplify.
* arm.c (arm_prgmode): Delete.
(arm_override_options, arm_gen_rotated_half_load): Simplify.
(print_multi_reg, output_return_instruction): Simplify.
(arm_output_epilogue, arm_final_prescan_insn): Simplify.
(arm_return_addr): Simplify.
* arm.md (prog_mode): Delete.
(conds): Simplify.
(zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify.
(rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete.
(loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete.
(loadhi_shiftpredec): Delete.
(peephole for post-increment on HImode load): Delete.
* arm/crtn.asm: (FUNC_END): Simplify.
* arm/lib1funcs.asm: Remove APCS-26 return macros.
* arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h
* arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h
* arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and
MULTILIB_DEFAULTS as required.
* arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe
* arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB
variables as required.
* doc/invoke.texi (ARM Options): Remove obsolete flags.
From-SVN: r81881
2004-05-15 14:41:35 +02:00
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(((MODE) == HImode && ! arm_arch4 \
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2000-04-08 16:29:53 +02:00
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&& (GET_CODE (X) == MEM \
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|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
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&& true_regnum (X) == -1))) \
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? GENERAL_REGS : NO_REGS) \
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2003-02-10 12:45:26 +01:00
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: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
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1994-10-02 16:10:27 +01:00
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1998-04-08 08:19:00 +02:00
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/* Try a machine-dependent way of reloading an illegitimate address
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operand. If we find one, push the reload and jump to WIN. This
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macro is used in only one place: `find_reloads_address' in reload.c.
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For the ARM, we wish to handle large displacements off a base
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register by splitting the addend across a MOV and the mem insn.
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2000-04-08 16:29:53 +02:00
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This can cut the number of reloads needed. */
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#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
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do \
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{ \
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if (GET_CODE (X) == PLUS \
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&& GET_CODE (XEXP (X, 0)) == REG \
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&& REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
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&& REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
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&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
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{ \
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HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
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HOST_WIDE_INT low, high; \
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\
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2004-06-21 15:32:09 +02:00
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if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
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2000-04-08 16:29:53 +02:00
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low = ((val & 0xf) ^ 0x8) - 0x8; \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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|
|
else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
|
2003-02-10 12:45:26 +01:00
|
|
|
|
/* Need to be careful, -256 is not a valid offset. */ \
|
|
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|
|
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
|
2000-04-08 16:29:53 +02:00
|
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|
else if (MODE == SImode \
|
2004-06-21 15:32:09 +02:00
|
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|| (MODE == SFmode && TARGET_SOFT_FLOAT) \
|
2000-04-08 16:29:53 +02:00
|
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|
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|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
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|
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|
/* Need to be careful, -4096 is not a valid offset. */ \
|
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|
|
|
low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
|
|
|
|
|
else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
|
|
|
|
|
/* Need to be careful, -256 is not a valid offset. */ \
|
|
|
|
|
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
|
|
|
|
|
else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPA) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Need to be careful, -1024 is not a valid offset. */ \
|
|
|
|
|
low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
|
|
|
|
|
else \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
2001-10-22 21:36:24 +02:00
|
|
|
|
high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
|
|
|
|
|
^ (unsigned HOST_WIDE_INT) 0x80000000) \
|
|
|
|
|
- (unsigned HOST_WIDE_INT) 0x80000000); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Check for overflow or zero */ \
|
|
|
|
|
if (low == 0 || high == 0 || (high + low != val)) \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
|
|
|
|
/* Reload the high part into a base reg; leave the low part \
|
|
|
|
|
in the mem. */ \
|
|
|
|
|
X = gen_rtx_PLUS (GET_MODE (X), \
|
|
|
|
|
gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
|
|
|
|
|
GEN_INT (high)), \
|
|
|
|
|
GEN_INT (low)); \
|
2001-05-04 17:06:41 +02:00
|
|
|
|
push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
|
2002-01-12 12:18:08 +01:00
|
|
|
|
MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
|
|
|
|
|
VOIDmode, 0, 0, OPNUM, TYPE); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
goto WIN; \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
1999-07-05 10:44:36 +02:00
|
|
|
|
while (0)
|
1998-04-08 08:19:00 +02:00
|
|
|
|
|
2003-06-25 20:49:51 +02:00
|
|
|
|
/* XXX If an HImode FP+large_offset address is converted to an HImode
|
2000-04-08 16:29:53 +02:00
|
|
|
|
SP+large_offset address, then reload won't know how to fix it. It sees
|
|
|
|
|
only that SP isn't valid for HImode, and so reloads the SP into an index
|
|
|
|
|
register, but the resulting address is still invalid because the offset
|
|
|
|
|
is too big. We fix it here instead by reloading the entire address. */
|
|
|
|
|
/* We could probably achieve better results by defining PROMOTE_MODE to help
|
|
|
|
|
cope with the variances between the Thumb's signed and unsigned byte and
|
|
|
|
|
halfword load instructions. */
|
|
|
|
|
#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
|
|
|
|
|
{ \
|
|
|
|
|
if (GET_CODE (X) == PLUS \
|
|
|
|
|
&& GET_MODE_SIZE (MODE) < 4 \
|
|
|
|
|
&& GET_CODE (XEXP (X, 0)) == REG \
|
|
|
|
|
&& XEXP (X, 0) == stack_pointer_rtx \
|
|
|
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
2003-01-23 19:10:46 +01:00
|
|
|
|
&& ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
{ \
|
|
|
|
|
rtx orig_X = X; \
|
|
|
|
|
X = copy_rtx (X); \
|
2001-05-04 17:06:41 +02:00
|
|
|
|
push_reload (orig_X, NULL_RTX, &X, NULL, \
|
2002-01-12 12:18:08 +01:00
|
|
|
|
MODE_BASE_REG_CLASS (MODE), \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
|
|
|
|
|
goto WIN; \
|
|
|
|
|
} \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
|
|
|
|
|
else \
|
|
|
|
|
THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Return the maximum number of consecutive registers
|
|
|
|
|
needed to represent mode MODE in a register of class CLASS.
|
2003-03-08 17:23:20 +01:00
|
|
|
|
ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
|
1991-12-06 03:11:44 +01:00
|
|
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
2003-03-08 17:23:20 +01:00
|
|
|
|
(((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
|
2003-02-10 12:45:26 +01:00
|
|
|
|
|
|
|
|
|
/* If defined, gives a class of registers that cannot be used as the
|
|
|
|
|
operand of a SUBREG that changes the mode of the object illegally. */
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2003-03-08 17:23:20 +01:00
|
|
|
|
/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
|
2001-01-01 21:35:36 +01:00
|
|
|
|
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
(TARGET_ARM ? \
|
2003-03-08 17:23:20 +01:00
|
|
|
|
((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
|
|
|
|
|
(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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(FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
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(FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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(FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
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(FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
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(FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
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2003-02-10 12:45:26 +01:00
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(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
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(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
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2) \
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2000-04-08 16:29:53 +02:00
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: \
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((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
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1991-12-06 03:11:44 +01:00
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/* Stack layout; function entry, exit and calling. */
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/* Define this if pushing a word on the stack
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makes the stack pointer a smaller address. */
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#define STACK_GROWS_DOWNWARD 1
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/* Define this if the nominal address of the stack frame
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is at the high-address end of the local variables;
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that is, each additional local variable allocated
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goes at a more negative offset in the frame. */
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#define FRAME_GROWS_DOWNWARD 1
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2004-10-14 09:37:11 +02:00
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/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
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When present, it is one word in size, and sits at the top of the frame,
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between the soft frame pointer and either r7 or r11.
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We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
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and only then if some outgoing arguments are passed on the stack. It would
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be tempting to also check whether the stack arguments are passed by indirect
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calls, but there seems to be no reason in principle why a post-reload pass
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couldn't convert a direct call into an indirect one. */
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#define CALLER_INTERWORKING_SLOT_SIZE \
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(TARGET_CALLER_INTERWORKING \
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&& current_function_outgoing_args_size != 0 \
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? UNITS_PER_WORD : 0)
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1991-12-06 03:11:44 +01:00
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/* Offset within stack frame to start allocating local variables at.
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If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
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first local allocated. Otherwise, it is the offset to the BEGINNING
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of the first local allocated. */
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#define STARTING_FRAME_OFFSET 0
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/* If we generate an insn to push BYTES bytes,
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this says how many the stack pointer really advances by. */
|
2000-04-08 16:29:53 +02:00
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/* The push insns do not do this rounding implicitly.
|
2003-12-25 16:17:37 +01:00
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So don't define this. */
|
2003-01-16 16:22:54 +01:00
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/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
|
1997-12-19 17:43:29 +01:00
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/* Define this if the maximum size of all the outgoing args is to be
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accumulated and pushed during the prologue. The amount can be
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found in the variable current_function_outgoing_args_size. */
|
1999-07-17 15:44:35 +02:00
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#define ACCUMULATE_OUTGOING_ARGS 1
|
1991-12-06 03:11:44 +01:00
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/* Offset of first parameter from the argument pointer register value. */
|
2000-04-08 16:29:53 +02:00
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#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
|
1991-12-06 03:11:44 +01:00
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/* Value is the number of byte of arguments automatically
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popped when returning from a subroutine call.
|
1995-02-22 00:21:14 +01:00
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FUNDECL is the declaration node of the function (as a tree),
|
1991-12-06 03:11:44 +01:00
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FUNTYPE is the data type of the function (as a tree),
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or for a library call it is an identifier node for the subroutine name.
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SIZE is the number of bytes of arguments passed on the stack.
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On the ARM, the caller does not pop any of its arguments that were passed
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on the stack. */
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1999-07-17 15:44:35 +02:00
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#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
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1991-12-06 03:11:44 +01:00
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/* Define how to find the value returned by a library function
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assuming the value has mode MODE. */
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#define LIBCALL_VALUE(MODE) \
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2004-08-24 13:32:53 +02:00
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(TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
|
|
|
|
? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
|
2004-08-24 13:32:53 +02:00
|
|
|
|
: TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
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2003-02-10 12:45:26 +01:00
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? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
|
2004-08-24 02:30:52 +02:00
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: TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
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config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
|
2000-04-08 16:29:53 +02:00
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: gen_rtx_REG (MODE, ARG_REGISTER (1)))
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1991-12-06 03:11:44 +01:00
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1999-07-17 15:44:35 +02:00
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/* Define how to find the value returned by a function.
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VALTYPE is the data type of the value (as a tree).
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If the precise function being called is known, FUNC is its FUNCTION_DECL;
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otherwise, FUNC is 0. */
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2000-04-08 16:29:53 +02:00
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#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
2004-04-08 20:26:09 +02:00
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arm_function_value (VALTYPE, FUNC);
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1999-07-17 15:44:35 +02:00
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1991-12-06 03:11:44 +01:00
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/* 1 if N is a possible register number for a function value.
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On the ARM, only r0 and f0 can return results. */
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2003-02-10 12:45:26 +01:00
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/* On a Cirrus chip, mvf0 can return results. */
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1991-12-06 03:11:44 +01:00
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#define FUNCTION_VALUE_REGNO_P(REGNO) \
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2000-04-08 16:29:53 +02:00
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((REGNO) == ARG_REGISTER (1) \
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backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
|| (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
|
2004-08-24 13:32:53 +02:00
|
|
|
|
&& TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
|| ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
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|| (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
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2004-08-24 13:32:53 +02:00
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&& TARGET_HARD_FLOAT_ABI && TARGET_FPA))
|
1991-12-06 03:11:44 +01:00
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2005-02-16 22:57:10 +01:00
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/* Amount of memory needed for an untyped call to save all possible return
|
|
|
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registers. */
|
|
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#define APPLY_RESULT_SIZE arm_apply_result_size()
|
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(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
/* How large values are returned */
|
|
|
|
|
/* A C expression which can inhibit the returning of certain function values
|
2003-12-25 16:17:37 +01:00
|
|
|
|
in registers, based on the type of value. */
|
1999-02-22 17:47:59 +01:00
|
|
|
|
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
|
|
|
|
|
/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
|
|
|
|
|
values must be in memory. On the ARM, they need only do so if larger
|
2003-12-25 16:17:37 +01:00
|
|
|
|
than a word, or if they contain elements offset from zero in the struct. */
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Flags for the call/call_value rtl operations set up by function_arg. */
|
|
|
|
|
#define CALL_NORMAL 0x00000000 /* No special processing. */
|
|
|
|
|
#define CALL_LONG 0x00000001 /* Always call indirect. */
|
|
|
|
|
#define CALL_SHORT 0x00000002 /* Never call indirect. */
|
|
|
|
|
|
2000-12-08 20:25:33 +01:00
|
|
|
|
/* These bits describe the different types of function supported
|
darwin-c.c, [...]: Fix comment typos.
* config/darwin-c.c, config/arc/arc.c, config/arc/arc.md,
config/arm/README-interworking, config/arm/arm-cores.def,
config/arm/arm.c, config/arm/arm.h, config/arm/pe.c,
config/arm/vfp.md, config/c4x/c4x.c, config/c4x/c4x.h,
config/cris/cris.c, config/cris/cris.h, config/fr30/fr30.c,
config/fr30/fr30.h, config/fr30/fr30.md, config/frv/frv.c,
config/frv/frv.md, config/i386/winnt.c,
config/ia64/unwind-ia64.c, config/iq2000/iq2000.c,
config/iq2000/iq2000.h, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.md, config/m68k/m68k.c,
config/mcore/mcore.c, config/mips/mips.h,
config/mn10300/mn10300.md, config/pa/pa.c,
config/pa/pa64-regs.h, config/pdp11/pdp11.c,
config/rs6000/rs6000.c, config/sh/symbian.c,
config/sparc/sparc.h: Fix comment typos. Follow spelling
conventions.
From-SVN: r87706
2004-09-18 21:19:40 +02:00
|
|
|
|
by the ARM backend. They are exclusive. i.e. a function cannot be both a
|
2000-12-08 20:25:33 +01:00
|
|
|
|
normal function and an interworked function, for example. Knowing the
|
|
|
|
|
type of a function is important for determining its prologue and
|
|
|
|
|
epilogue sequences.
|
|
|
|
|
Note value 7 is currently unassigned. Also note that the interrupt
|
|
|
|
|
function types all have bit 2 set, so that they can be tested for easily.
|
|
|
|
|
Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
|
2002-09-14 17:51:45 +02:00
|
|
|
|
machine_function structure is initialized (to zero) func_type will
|
2000-12-08 20:25:33 +01:00
|
|
|
|
default to unknown. This will force the first use of arm_current_func_type
|
|
|
|
|
to call arm_compute_func_type. */
|
|
|
|
|
#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
|
|
|
|
|
#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
|
|
|
|
|
#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
|
|
|
|
|
#define ARM_FT_ISR 4 /* An interrupt service routine. */
|
|
|
|
|
#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
|
|
|
|
|
#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
|
|
|
|
|
|
|
|
|
|
#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
|
|
|
|
|
|
|
|
|
|
/* In addition functions can have several type modifiers,
|
|
|
|
|
outlined by these bit masks: */
|
|
|
|
|
#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
|
|
|
|
|
#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
|
|
|
|
|
#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
|
2003-12-25 16:17:37 +01:00
|
|
|
|
#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
|
2000-12-08 20:25:33 +01:00
|
|
|
|
|
|
|
|
|
/* Some macros to test these flags. */
|
|
|
|
|
#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
|
|
|
|
|
#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
|
|
|
|
|
#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
|
|
|
|
|
#define IS_NAKED(t) (t & ARM_FT_NAKED)
|
|
|
|
|
#define IS_NESTED(t) (t & ARM_FT_NESTED)
|
|
|
|
|
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
|
|
|
|
|
/* Structure used to hold the function stack frame layout. Offsets are
|
|
|
|
|
relative to the stack pointer on function entry. Positive offsets are
|
|
|
|
|
in the direction of stack growth.
|
|
|
|
|
Only soft_frame is used in thumb mode. */
|
|
|
|
|
|
|
|
|
|
typedef struct arm_stack_offsets GTY(())
|
|
|
|
|
{
|
|
|
|
|
int saved_args; /* ARG_POINTER_REGNUM. */
|
|
|
|
|
int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
|
|
|
|
|
int saved_regs;
|
|
|
|
|
int soft_frame; /* FRAME_POINTER_REGNUM. */
|
|
|
|
|
int outgoing_args; /* STACK_POINTER_REGNUM. */
|
|
|
|
|
}
|
|
|
|
|
arm_stack_offsets;
|
|
|
|
|
|
2000-12-08 20:25:33 +01:00
|
|
|
|
/* A C structure for machine-specific, per-function data.
|
|
|
|
|
This is added to the cfun structure. */
|
2002-06-04 09:11:05 +02:00
|
|
|
|
typedef struct machine_function GTY(())
|
2000-04-08 16:29:53 +02:00
|
|
|
|
{
|
2003-01-31 03:20:48 +01:00
|
|
|
|
/* Additional stack adjustment in __builtin_eh_throw. */
|
2002-06-04 09:11:05 +02:00
|
|
|
|
rtx eh_epilogue_sp_ofs;
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Records if LR has to be saved for far jumps. */
|
|
|
|
|
int far_jump_used;
|
|
|
|
|
/* Records if ARG_POINTER was ever live. */
|
|
|
|
|
int arg_pointer_live;
|
2000-12-22 19:22:03 +01:00
|
|
|
|
/* Records if the save of LR has been eliminated. */
|
|
|
|
|
int lr_save_eliminated;
|
2002-11-07 19:32:00 +01:00
|
|
|
|
/* The size of the stack frame. Only valid after reload. */
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
arm_stack_offsets stack_offsets;
|
2000-12-08 20:25:33 +01:00
|
|
|
|
/* Records the type of the current function. */
|
|
|
|
|
unsigned long func_type;
|
2002-02-04 21:23:07 +01:00
|
|
|
|
/* Record if the function has a variable argument list. */
|
|
|
|
|
int uses_anonymous_args;
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
/* Records if sibcalls are blocked because an argument
|
|
|
|
|
register is needed to preserve stack alignment. */
|
|
|
|
|
int sibcall_blocked;
|
2005-01-14 14:58:40 +01:00
|
|
|
|
/* Labels for per-function Thumb call-via stubs. One per potential calling
|
2005-04-01 17:59:09 +02:00
|
|
|
|
register. We can never call via LR or PC. We can call via SP if a
|
|
|
|
|
trampoline happens to be on the top of the stack. */
|
|
|
|
|
rtx call_via[14];
|
2000-12-08 20:25:33 +01:00
|
|
|
|
}
|
|
|
|
|
machine_function;
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
2005-01-14 14:58:40 +01:00
|
|
|
|
/* As in the machine_function, a global set of call-via labels, for code
|
|
|
|
|
that is in text_section(). */
|
2005-04-01 17:59:09 +02:00
|
|
|
|
extern GTY(()) rtx thumb_call_via_label[14];
|
2005-01-14 14:58:40 +01:00
|
|
|
|
|
2000-02-09 21:00:29 +01:00
|
|
|
|
/* A C type for declaring a variable that is used as the first argument of
|
|
|
|
|
`FUNCTION_ARG' and other related values. For some target machines, the
|
|
|
|
|
type `int' suffices and can hold the number of bytes of argument so far. */
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* This is the number of registers of arguments scanned so far. */
|
2000-02-09 21:00:29 +01:00
|
|
|
|
int nregs;
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
/* This is the number of iWMMXt register arguments scanned so far. */
|
|
|
|
|
int iwmmxt_nregs;
|
|
|
|
|
int named_count;
|
|
|
|
|
int nargs;
|
2003-12-25 16:17:37 +01:00
|
|
|
|
/* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
|
2000-02-09 21:00:29 +01:00
|
|
|
|
int call_cookie;
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
int can_split;
|
2000-04-08 16:29:53 +02:00
|
|
|
|
} CUMULATIVE_ARGS;
|
2000-02-09 21:00:29 +01:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Define where to put the arguments to a function.
|
|
|
|
|
Value is zero to push the argument on the stack,
|
|
|
|
|
or a hard register in which to store the argument.
|
|
|
|
|
|
|
|
|
|
MODE is the argument's machine mode.
|
|
|
|
|
TYPE is the data type of the argument (as a tree).
|
|
|
|
|
This is null for libcalls where that information may
|
|
|
|
|
not be available.
|
|
|
|
|
CUM is a variable of type CUMULATIVE_ARGS which gives info about
|
|
|
|
|
the preceding args and about the function being called.
|
|
|
|
|
NAMED is nonzero if this argument is a named parameter
|
|
|
|
|
(otherwise it is an extra parameter matching an ellipsis).
|
|
|
|
|
|
|
|
|
|
On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
|
|
|
|
|
other arguments are passed on the stack. If (NAMED == 0) (which happens
|
2004-01-26 17:35:44 +01:00
|
|
|
|
only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
|
|
|
|
|
defined), say it is passed in the stack (function_prologue will
|
|
|
|
|
indeed make it pass in the stack if necessary). */
|
2000-02-09 21:00:29 +01:00
|
|
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
|
|
|
|
arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2005-04-26 18:30:37 +02:00
|
|
|
|
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
|
|
|
|
|
(arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
|
|
|
|
|
|
|
|
|
|
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
|
|
|
|
|
(arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
|
|
|
|
|
|
|
|
|
|
/* For AAPCS, padding should never be below the argument. For other ABIs,
|
|
|
|
|
* mimic the default. */
|
|
|
|
|
#define PAD_VARARGS_DOWN \
|
|
|
|
|
((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
|
|
|
|
for a call to a function whose data type is FNTYPE.
|
|
|
|
|
For a library call, FNTYPE is 0.
|
|
|
|
|
On the ARM, the offset starts at 0. */
|
tm.texi (INIT_CUMULATIVE_ARGS): Update doco.
* doc/tm.texi (INIT_CUMULATIVE_ARGS): Update doco.
* calls.c (expand_call): Pass n_named_args to INIT_CUMULATIVE_ARGS.
(emit_library_call_value_1): Likewise pass nargs.
* expr.c (block_move_libcall_safe_for_call_parm): Pass 3 here.
* function.c (assign_parms): Pass -1 to INIT_CUMULATIVE_ARGS.
* config/rs6000/rs6000.c (init_cumulative_args): Use n_named_args
parameter instead of scanning TYPE_ARGS_TYPES to count args.
* config/rs6000/rs6000-protos.h (init_cumulative_args): Update
prototype.
* config/rs6000/rs6000.h (INIT_CUMULATIVE_ARGS): Pass extra arg.
(INIT_CUMULATIVE_INCOMING_ARGS): Set extra arg to 1000.
(INIT_CUMULATIVE_LIBCALL_ARGS): Set extra arg to 0.
* config/sh/sh.c (sh_output_mi_thunk): Pass 1 as n_named_args to
INIT_CUMULATIVE_ARGS.
* config/alpha/alpha.h (INIT_CUMULATIVE_ARGS): Update.
* config/alpha/unicosmk.h, config/alpha/vms.h, config/arc/arc.h,
config/arm/arm.h, config/avr/avr.h, config/c4x/c4x.h,
config/cris/cris.h, config/fr30/fr30.h, config/frv/frv.h,
config/h8300/h8300.h, config/i386/i386.h, config/i860/i860.h,
config/ia64/ia64.h, config/ip2k/ip2k.h, config/iq2000/iq2000.h,
config/iq2000/iq2000.c, config/m32r/m32r.h, config/m68hc11/m68hc11.h,
config/m68k/m68k.h, config/mcore/mcore.h, config/mips/mips.h,
config/mmix/mmix.h, config/mn10300/mn10300.h, config/ns32k/ns32k.h,
config/pa/pa.h, config/pdp11/pdp11.h config/s390/s390.h,
config/sh/sh.h, config/sparc/sparc.h, config/stormy16/stormy16.h,
config/v850/v850.h, config/vax/vax.h, config/xtensa/xtensa.h: Likewise.
From-SVN: r77380
2004-02-06 07:18:36 +01:00
|
|
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
2003-02-19 19:03:11 +01:00
|
|
|
|
arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Update the data in CUM to advance over an argument
|
|
|
|
|
of mode MODE and data type TYPE.
|
|
|
|
|
(TYPE is null for libcalls where that information may not be available.) */
|
1999-07-17 15:44:35 +02:00
|
|
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
(CUM).nargs += 1; \
|
2004-08-24 02:30:52 +02:00
|
|
|
|
if (arm_vector_mode_supported_p (MODE) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
&& (CUM).named_count > (CUM).nargs) \
|
|
|
|
|
(CUM).iwmmxt_nregs += 1; \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
else \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
(CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
/* If defined, a C expression that gives the alignment boundary, in bits, of an
|
|
|
|
|
argument with the specified mode and type. If it is not defined,
|
|
|
|
|
`PARM_BOUNDARY' is used for all arguments. */
|
|
|
|
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
|
|
|
|
|
? DOUBLEWORD_ALIGNMENT \
|
|
|
|
|
: PARM_BOUNDARY )
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* 1 if N is a possible register number for function argument passing.
|
|
|
|
|
On the ARM, r0-r3 are used to pass args. */
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
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|
|
|
(IN_RANGE ((REGNO), 0, 3) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
|| (TARGET_IWMMXT_ABI \
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|
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|
&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
|
1991-12-06 03:11:44 +01:00
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|
2000-08-15 17:14:06 +02:00
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1999-05-05 09:46:43 +02:00
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/* If your target environment doesn't prefix user functions with an
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underscore, you may wish to re-define this to prevent any conflicts.
|
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|
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e.g. AOF may prefix mcount with an underscore. */
|
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|
#ifndef ARM_MCOUNT_NAME
|
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#define ARM_MCOUNT_NAME "*mcount"
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|
#endif
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/* Call the function profiler with a given profile label. The Acorn
|
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|
compiler puts this BEFORE the prolog but gcc puts it afterwards.
|
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|
On the ARM the full profile code will look like:
|
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.data
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LP1
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.word 0
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.text
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mov ip, lr
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bl mcount
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.word LP1
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profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
|
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|
will output the .text section.
|
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|
The ``mov ip,lr'' seems like a good idea to stick with cc convention.
|
2002-09-24 18:51:33 +02:00
|
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|
``prof'' doesn't seem to mind about this!
|
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Note - this version of the code is designed to work in both ARM and
|
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|
Thumb modes. */
|
2001-09-14 12:19:30 +02:00
|
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|
|
#ifndef ARM_FUNCTION_PROFILER
|
2000-04-08 16:29:53 +02:00
|
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|
|
#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
|
1999-07-17 15:44:35 +02:00
|
|
|
|
{ \
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|
char temp[20]; \
|
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|
|
rtx sym; \
|
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|
|
\
|
1999-07-26 12:59:55 +02:00
|
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|
asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
|
2000-04-08 16:29:53 +02:00
|
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|
|
IP_REGNUM, LR_REGNUM); \
|
1999-07-17 15:44:35 +02:00
|
|
|
|
assemble_name (STREAM, ARM_MCOUNT_NAME); \
|
|
|
|
|
fputc ('\n', STREAM); \
|
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|
|
ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
|
arm.c, [...]: Replace "gen_rtx (FOO, " with "gen_rtx_FOO (".
* config/arm/arm.c, config/arm/arm.h, config/arm/arm.md,
config/arm/linux-gas.h, config/arm/netbsd-elf.h,
config/arm/netbsd.h, config/arm/pe.c, config/avr/avr.c,
config/avr/avr.h, config/avr/avr.md, config/c4x/c4x.h,
config/cris/cris.h, config/fr30/fr30.h, config/frv/frv.c,
config/frv/frv.h, config/ip2k/ip2k.c, config/iq2000/iq2000.c,
config/iq2000/iq2000.h, config/m32r/m32r.c,
config/m68hc11/m68hc11.c, config/m68hc11/m68hc11.h,
config/m68hc11/m68hc11.md, config/m68k/m68k.md,
config/mcore/mcore.c, config/mcore/mcore.h,
config/mcore/mcore.md, config/mips/mips.c,
config/ns32k/ns32k.h, config/ns32k/ns32k.md,
config/rs6000/rs6000.c, config/s390/s390.c,
config/s390/s390.md, config/sparc/sparc.c, config/v850/v850.c,
config/xtensa/xtensa.h, config/xtensa/xtensa.md: Replace
"gen_rtx (FOO, " with "gen_rtx_FOO (".
From-SVN: r77080
2004-02-01 22:21:45 +01:00
|
|
|
|
sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
|
target.h (asm_out.byte_op, [...]): New fields.
* target.h (asm_out.byte_op, asm_out.aligned_op, asm_out.unaligned_op,
asm_out.integer): New fields.
* target-def.h (TARGET_ASM_BYTE_OP, TARGET_ASM_ALIGNED_[HSDT]I_OP,
TARGET_ASM_UNALIGNED_[HSDT]I_OP, TARGET_ASM_INTEGER): New initialisers.
(TARGET_ASM_ALIGNED_INT_OP, TARGET_ASM_UNALIGNED_INT_OP): Collect
the individual initialisers together.
(TARGET_ASM_OUT): Add the new initialisers.
* output.h (assemble_integer): Return bool.
(integer_asm_op): Declare.
(default_assemble_integer): Declare.
(assemble_aligned_integer): New interface to assemble_integer.
* varasm.c (integer_asm_op): New function to select pseudo-op.
(default_assemble_integer): Default implementation of asm_out.integer.
(assemble_integer): Use the new target hook. Split objects into
words or bytes if the target hook fails. Return bool.
* doc/tm.texi (ASM_OUTPUT_CHAR, ASM_OUTPUT_BYTE, ASM_OUTPUT_SHORT,
ASM_OUTPUT_INT, ASM_OUTPUT_DOUBLE_INT, ASM_OUTPUT_QUADRUPLE_INT,
UNALIGNED_SHORT_ASM_OP, UNALIGNED_INT_ASM_OP,
UNALIGNED_DOUBLE_INT_ASM_OP): Undocument.
Document new target hooks.
* defaults.h (ASM_OUTPUT_ADDR_VEC_ELT): Use integer_asm_op.
* dwarf2asm.c (unaligned_integer_asm_op): Remove.
(dw2_assemble_integer): New.
(dw2_asm_output_data, dw2_asm_output_delta, dw2_asm_output_offset,
dw2_asm_output_pcrel, dw2_asm_output_addr, dw2_asm_output_addr_rtx,
dw2_asm_output_encoded_addr_rtx): Use it.
(dw2_asm_output_nstring): Use assemble_integer for the null terminator.
(dw2_asm_output_data_uleb128, dw2_asm_output_data_sleb128): Use
integer_asm_op to get the byte pseudo-op. Use assemble_integer
if it returns NULL.
* dwarf2asm.h (dw2_assemble_integer): Declare.
* dwarfout.c: Include dwarf2asm.h. Use dwarf2 functions for the
default implementation of most macros.
(output_unsigned_leb128): Use dw2_asm_output_data.
(output_signed_leb128, dwarfout_source_line): Likewise.
(output_reg_number): Use dw2_assemble_integer.
(generate_macinfo_entry): Separate the type and offset arguments.
Use assemble_integer to write the value.
(dwarfout_start_source_file): Update generate_macinfo_entry usage.
(dwarfout_end_source_file, dwarfout_define, dwarfout_undef): Likewise.
* final.c (output_addr_const): Don't put brackets round a subtracted
symbol value or ".".
* halfpic.c (half_pic_finish): Use assemble_aligned_integer.
* config/1750a/1750a.c (assemble_integer_1750a): New,
* config/alpha/alpha.h (literal_section): Avoid ASM_OUTPUT_INT.
* config/arc/arc.c (arc_assemble_integer): New.
* config/arc/arc.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/arm/arm.c (arm_poke_function_name): Likewise.
(arm_assemble_integer): New, extracted from...
* config/arm/arm.h (OUTPUT_INT_ADDR_CONST): ...here, now removed.
(ARM_TRAMPOLINE_TEMPLATE, ARM_FUNCTION_PROFILER): Avoid ASM_OUTPUT_INT.
(ARM_FUNCTION_PROFILER): Likewise.
* config/avr/avr-protos.h (asm_output_byte): Remove.
(asm_output_char, asm_output_short): Remove.
* config/avr/avr.c (avr_assemble_integer): New.
(asm_output_byte, asm_output_char, asm_output_short): Remove.
* config/clipper/clipper.h (ASM_LONG): Remove.
* config/dsp16xx/dsp16xx-protos.h (asm_output_long): Remove.
* config/dsp16xx/dsp16xx.c (asm_output_long): Remove.
* config/elxsi/elxsi.c (elxsi_assemble_integer): New.
* config/i370/i370.c (i370_hlasm_assemble_integer): New.
* config/i370/i370.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_SHORT.
(ASM_BYTE, ASM_SHORT, ASM_LONG): Delete.
* config/i386/att.h, (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i386/linux.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Use
ASM_LONG instead of UNALIGNED_INT_ASM_OP.
* config/i386/sco5.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Likewise.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i386/sysv4.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Use
ASM_LONG instead of UNALIGNED_INT_ASM_OP.
* config/i860/fx2800.h (ASM_FILE_END): Avoid ASM_LONG.
* config/i860/i860.c (i860_output_function_epilogue): Likewise.
* config/i860/i860.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
(ASM_SHORT, ASM_LONG): Undefine.
* config/i860/paragon.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i860/sysv3.h (ASM_OUTPUT_ASCII): Likewise.
* config/i960/i960.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/ia64/ia64.c (ia64_assemble_integer): New.
* config/ia64/ia64.h (ASM_OUTPUT_DWARF_OFFSET): Use integer_asm_op.
(ASM_OUTPUT_DWARF_PCREL): Likewise.
* config/m68hc11/m68hc11.h (ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_VEC_ELT): Avoid ASM_LONG.
(ASM_SHORT, ASM_LONG): Remove.
* config/m68k/m68k.h (INT_OP_GROUP): New macro.
(INT_OP_STANDARD, INT_OP_DOT_WORD, INT_OP_NO_DOT, INT_OP_DC): New
macros, the allowed values for INT_OP_GROUP.
* config/m68k/amix.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP
* config/m68k/atari.h (ASM_OUTPUT_ASCII): Likewise
* config/m68k/m68kelf.h (ASM_OUTPUT_ASCII): Likewise
* config/m68k/auxas.h (BYTE_ASM_OP, WORD_ASM_OP, LONG_ASM_OP): Remove.
(INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m68k/dpx2.h (ASM_LONG): Undefine.
(INT_OP_GROUP): Define to INT_OP_DC.
* config/m68k/dpx2g.h (ASM_LONG): Undefine.
* config/m68k/hp320.h (INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m68k/lynx.h (ASM_LONG): Undefine.
* config/m68k/dpx2g.h (ASM_LONG): Undefine.
* config/m68k/m68kelf.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/m68k/m68kv4.h (ASM_OUTPUT_ASCII): Likewise.
(TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_*.
* config/m68k/mot3300.h (INT_OP_GROUP): Define to INT_OP_STANDARD
for GAS and INT_OP_NO_DOT otherwise.
(ASM_CHAR, ASM_BYTE, ASM_SHORT, ASM_LONG): Remove.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Avoid ASM_LONG.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/m68k/sgs.h (BYTE_ASM_OP, WORD_ASM_OP, LONG_ASM_OP): Remove.
(INT_OP_GROUP): Define to INT_OP_STANDARD.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Avoid LONG_ASM_OP.
(ASM_OUTPUT_ASCII): Avoid BYTE_ASM_OP.
* config/m68k/tower-as.h (ASM_LONG): Remove.
(INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m88k/m88k.c (output_tdesc): Avoid ASM_LONG.
* config/m88k/m88k.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
(ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT): Avoid ASM_LONG.
* config/mips/iris5.h (TARGET_IRIX5): Define.
* config/mips/mips.c (mips_assemble_integer): New.
* config/mips/sni-svr4.h (ASM_LONG): Undefine.
* config/mmix/mmix-protos.h (mmix_asm_output_double_int): Remove.
* config/mmix/mmix.c (mmix_assemble_integer): New.
(mmix_asm_output_double_int): Remove.
(mmix_print_operand): Call mmix_output_octa directly.
* config/mmix/mmix.h (ASM_LONG): Remove.
* config/ns32k/ns32k.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/pa/pa.c (pa_assemble_integer): New.
(pa_override_options): Only use aligned DI ops on 64-bit targets.
Only use the unaligned ops if TARGET_GAS.
* config/pdp11/pdp11.c (pdp11_assemble_integer): New.
* config/pdp11/pdp11.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_SHORT.
* config/pj/pj.h (ASM_LONG): Undefine.
* config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Undefine.
* config/rs6000/rs6000.c (rs6000_assemble_integer): New, mostly
extracted from ASM_OUTPUT_INT in sysv4.h. Use in_text_section()
and in_toc_section() rather than the in_section variable.
(rs6000_override_options): Only use DI ops when TARGET_POWERPC64.
* config/rs6000/sysv4.h (TOC_SECTION_FUNCTION): Add in_toc_section().
(RELOCATABLE_NEEDS_FIXUP): Define.
* config/rs6000/xcoff.h (DOUBLE_INT_ASM_OP): Change space to tab.
* config/s390/linux.h (ASM_SHORT, ASM_LONG, ASM_QUAD): Remove.
(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Use integer_asm_op
to get the word directive.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/s390/s390.c (s390_assemble_integer): New.
* config/s390/s390.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY): Use
integer_asm_op to get the word directive.
* config/sparc/sol2.h (ASM_SHORT, ASM_LONG): Remove.
* config/sparc/sparc-protos.h (output_double_int): Remove.
* config/sparc/sparc.c (output_double_int): Move to...
(sparc_assemble_integer): ...this new function.
(sparc_override_options): Only use .uaxword if TARGET_ARCH64.
* config/sparc/sparc.h (ASM_SHORT, ASM_LONG, ASM_LONGLONG): Remove.
* config/sparc/sysv4.h (ASM_LONG): Remove.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT): Avoid
ASM_LONG.
* config/vax/vax.h (TRAMPOLINE_TEMPLATE): Use assemble_aligned_integer.
* config/we32k/we32k.h (TRAMPOLINE_TEMPLATE): Likewise.
* config/1750a/1750a.c, config/a29k/a29k.c, config/alpha/alpha.c,
config/arc/arc.c, config/arm/arm.c, config/avr/avr.c, config/c4x/c4x.c,
config/clipper/clipper.c, config/convex/convex.c, config/cris/cris.c,
config/d30v/d30v.c, config/dsp16xx/dsp16xx.c, config/elxsi/elxsi.c,
config/fr30/fr30.c, config/h8300/h8300.c, config/i370/i370.c,
config/i386/i386.c, config/i860/i860.c, config/i960/i960.c,
config/ia64/ia64.c, config/m32r/m32r.c, config/m68hc11/m68hc11.c,
config/m68k/m68k.c, config/m88k/m88k.c, config/mips/mips.c,
config/mmix/mmix.c, config/mn10200/mn10200.c, config/mn10300/mn10300.c,
config/ns32k/ns32k.c, config/pa/pa.c, config/pdp11/pdp11.c,
config/sh/sh.c, config/sparc/sparc.c, config/stormy16/stormy16.c,
config/v850/v850.c, config/vax/vax.c, config/we32k/we32k.c
(TARGET_ASM_BYTE_OP, TARGET_ASM_ALIGNED_HI_OP,
TARGET_ASM_ALIGNED_SI_OP, TARGET_ASM_ALIGNED_DI_OP,
TARGET_ASM_UNALIGNED_HI_OP, TARGET_ASM_UNALIGNED_SI_OP,
TARGET_ASM_UNALIGNED_DI_OP, TARGET_ASM_INTEGER): Redefine as
appropriate.
* config/defaults.h, config/darwin.h, config/elfos.h, config/svr3.h,
config/1750a/1750a.h, config/a29k/a29k.h, config/alpha/alpha.h,
config/arc/arc.h, config/arm/arm.h, config/avr/avr.h, config/c4x/c4x.h,
config/clipper/clipper.h, config/convex/convex.h, config/cris/cris.h,
config/d30v/d30v.h, config/dsp16xx/dsp16xx.h, config/elxsi/elxsi.h,
config/fr30/fr30.h, config/h8300/h8300.h, config/i370/i370.h,
config/i386/bsd.h, config/i386/djgpp.h, config/i386/i386.h,
config/i386/sco5.h, config/i386/sol2.h, config/i386/sun386.h,
config/i860/i860.h, config/i960/i960.h, config/ia64/ia64.h,
config/m32r/m32r.h, config/m68hc11/m68hc11.h, config/m68k/auxas.h,
config/m68k/dpx2.h, config/m68k/hp320.h, config/m68k/m68k.h,
config/m68k/mot3300.h, config/m68k/sgs.h, config/m68k/tower-as.h,
config/m88k/m88k.h, config/mcore/mcore-elf.h, config/mcore/mcore.h,
config/mips/iris5.h, config/mips/iris6.h, config/mips/mips.h,
config/mmix/mmix.h, config/mn10200/mn10200.h, config/mn10300/mn10300.h
config/ns32k/encore.h, config/ns32k/ns32k.h, config/pa/pa-64.h,
config/pa/pa.h, config/pdp11/pdp11.h, config/pj/pj.h,
config/romp/romp.h, config/rs6000/linux64.h, config/rs6000/rs6000.h,
config/rs6000/sysv4.h, config/rs6000/xcoff.h, config/s390/linux.h,
config/sh/sh.h, config/sparc/linux64.h, config/sparc/sol2.h,
config/sparc/sp64-elf.h, config/sparc/sparc.h, config/sparc/sysv4.h,
config/stormy16/stormy16.h, config/v850/v850.h, config/vax/vax.h,
config/we32k/we32k.h (ASM_OUTPUT_CHAR, ASM_OUTPUT_BYTE, ASM_BYTE_OP,
ASM_BYTE, ASM_OUTPUT_SHORT, ASM_OUTPUT_INT, ASM_OUTPUT_DOUBLE_INT,
UNALIGNED_SHORT_ASM_OP, UNALIGNED_INT_ASM_OP,
UNALIGNED_DOUBLE_INT_ASM_OP): Undefine, where defined.
From-SVN: r48101
2001-12-17 16:05:40 +01:00
|
|
|
|
assemble_aligned_integer (UNITS_PER_WORD, sym); \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
}
|
2001-09-14 12:19:30 +02:00
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
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|
2002-09-24 18:51:33 +02:00
|
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|
|
#ifdef THUMB_FUNCTION_PROFILER
|
2000-04-08 16:29:53 +02:00
|
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|
|
#define FUNCTION_PROFILER(STREAM, LABELNO) \
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|
if (TARGET_ARM) \
|
|
|
|
|
ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
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|
else \
|
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|
THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
|
2002-09-24 18:51:33 +02:00
|
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|
#else
|
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|
#define FUNCTION_PROFILER(STREAM, LABELNO) \
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ARM_FUNCTION_PROFILER (STREAM, LABELNO)
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|
#endif
|
2000-04-08 16:29:53 +02:00
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|
1991-12-06 03:11:44 +01:00
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|
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
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|
the stack pointer does not matter. The value is tested only in
|
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|
functions that have frame pointers.
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No definition is equivalent to always zero.
|
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|
On the ARM, the function epilogue recovers the stack pointer from the
|
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|
frame. */
|
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|
#define EXIT_IGNORE_STACK 1
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|
2001-01-08 15:32:53 +01:00
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|
#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
|
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|
1991-12-06 03:11:44 +01:00
|
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|
/* Determine if the epilogue should be output as RTL.
|
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|
|
|
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
|
2000-04-08 16:29:53 +02:00
|
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|
|
#define USE_RETURN_INSN(ISCOND) \
|
2003-11-20 12:44:19 +01:00
|
|
|
|
(TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
|
1993-10-03 17:33:02 +01:00
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|
/* Definitions for register eliminations.
|
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This is an array of structures. Each structure initializes one pair
|
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|
of eliminable registers. The "from" register number is given first,
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followed by "to". Eliminations of the same "from" register are listed
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|
in order of preference.
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|
We have two registers that can be eliminated on the ARM. First, the
|
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|
arg pointer register can often be eliminated in favor of the stack
|
|
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|
|
pointer register. Secondly, the pseudo frame pointer register can always
|
|
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|
|
be eliminated; it is replaced with either the stack or the real frame
|
2000-04-08 16:29:53 +02:00
|
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|
|
pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
|
ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.3, ChangeLog.5, ChangeLog, alias.c,
cfgbuild.c, expmed.c, expr.c, final.c, flow.c, fold-const.c,
function.c, config/alpha/alpha.md, config/alpha/vms-ld.c,
config/arm/arm.c, config/arm/arm.h, config/c4x/libgcc.S,
config/i370/i370.c, config/i386/i386.c,
config/i386/i386-interix.h, config/i386/i386.md,
config/i386/i386.h, config/i386/netbsd-elf.h, config/ia64/ia64.c,
config/m32r/m32r-protos.h, config/mcore/mcore.h,
config/rs6000/rs6000.h, config/sparc/linux64.h,
config/sparc/sparc.c, config/v850/v850-protos.h,
config/cris/cris.h, config/s390/s390.md, config/elfos.h: Fix
spelling errors.
From-SVN: r47815
2001-12-09 21:13:19 +01:00
|
|
|
|
because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define ELIMINABLE_REGS \
|
|
|
|
|
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
|
|
|
|
|
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
|
|
|
|
|
{ ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
|
|
|
|
|
{ ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
|
|
|
|
|
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
|
|
|
|
|
{ FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
|
|
|
|
|
{ FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Given FROM and TO register numbers, say whether this elimination is
|
|
|
|
|
allowed. Frame pointer elimination is automatically handled.
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
|
|
|
|
All eliminations are permissible. Note that ARG_POINTER_REGNUM and
|
1995-08-28 12:54:22 +02:00
|
|
|
|
HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
|
1993-10-03 17:33:02 +01:00
|
|
|
|
pointer, we must eliminate FRAME_POINTER_REGNUM into
|
2000-04-08 16:29:53 +02:00
|
|
|
|
HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
|
|
|
|
|
ARG_POINTER_REGNUM. */
|
|
|
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
|
|
|
|
(((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
|
|
|
|
|
((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
|
|
|
|
|
((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
|
|
|
|
|
((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
|
|
|
|
|
1)
|
2002-08-08 13:08:34 +02:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Define the offset between two registers, one to be eliminated, and the
|
|
|
|
|
other its replacement, at the start of a routine. */
|
|
|
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
|
|
|
|
if (TARGET_ARM) \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
(OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
else \
|
config.gcc: Add --with-abi=
* config.gcc <arm>: Add --with-abi=
* config/arm/arm-protos.h (arm_get_frame_size, thumb_get_frame_size,
thumb_far_jump_used): Remove prototypes.
(arm_needs_doubleword_align): Add prototype.
(thumb_compute_initial_elimination_offset): Ditto.
* config/arm/arm.c (arm_get_frame_offsets): New function.
(use_return_insn, output_return_instruction, arm_output_epilogue,
arm_output_function_epilogue, arm_compute_initial_elimination_offset,
arm_expand_prologue, thumb_expand_epilogue): Use it.
(arm_abi, target_abi_name, all_arm_abis): New variables.
(arm_override_options): Set them. Set structure padding for AAPCS.
(arm_return_in_memory): Update ABI check.
(arm_init_cumulative_args): Initialize can_split.
(arm_needs_doubleword_align): New function.
(arm_function_arg): Don't split args after pushing to stack. Handle
doubleword/even reg alignment.
(arm_va_arg): Handle all doubleword aligned args.
(add_minpoolforward ref, dump_minpool, push_minpool_fix): Align based
on ABI, not CPU.
(arm_compute_save_reg0_reg12_mask): Fix comment.
(thumb_get_frame_size, thumb_get_frame_size): Remove.
(thumb_jump_far_used_p): Remove superfluous argument. Return save
value for alignment.
(thumb_unexpanded_epilogue, thumb_output_function_prologue): Change
to match.
(thumb_compute_initial_elimination_offset): New function.
(thumb_expand_prologue): Use arm_get_frame_offsets. Remove
unneccessary rounding.
* config/arm/arm.h (target_abi_name): Declare.
(ARM_DOUBLEWORD_ALIGN, DOUBLEWORD_ALIGNMENT, TARGET_IWMMXT_ABI,
arm_abi_type, ARM_DEFAULT_ABI): Define.
(ARM_FLAG_ATPCS): Remove.
(TARGET_OPTIONS, OPTION_DEFAULT_SPECS): Add -mabi=.
(BIGGEST_ALIGNMENT, PREFERRED_STACK_BOUNDARY, STACK_BOUNDARY): Use it.
(ADJUST_FIELD_ALIGN, DATA_ALIGNMENT, LOCAL_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT): Remove.
(LIBCALL_VALUE, FUNCTION_VALUE_REGNO_P, FUNCTION_ARG_REGNO_P):
Contitionalize on ABI, not CPU.
(struct arm_stack_offsets): Define.
(struct machine_function): Add stack_offsets. Remove frame_size.
(FUNCTION_ARG_PARTIAL_NREGS): Don't split if previous args have been
pushed.
(FUNCTION_ARG_ADVANCE, FUNCTION_ARG_BOUNDARY): Handle general
doubleword alignment.
(THUMB_INITIAL_ELIMINATION_OFFSET,
ARM_INITIAL_ELIMINATION_OFFSET): Remove.
(INITIAL_ELIMINATION_OFFSET): Call functions directly.
* config/arm/arm.md (align_8): Enable for all targets.
* config/arm/netbsd-elf.h (TARGET_DEFAULT): Remove TARGET_ATPCS.
(ARM_DEFAULT_ABI): Define.
* doc/invoke.texi <ARM>: Document -mabi=. Update documentation for
-mstructure-size-boundary.
From-SVN: r79921
2004-03-24 18:20:16 +01:00
|
|
|
|
(OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Special case handling of the location of arguments passed on the stack. */
|
|
|
|
|
#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
/* Initialize data used by insn expanders. This is called from insn_emit,
|
|
|
|
|
once for every function before code is generated. */
|
|
|
|
|
#define INIT_EXPANDERS arm_init_expanders ()
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Output assembler code for a block containing the constant parts
|
|
|
|
|
of a trampoline, leaving space for the variable parts.
|
|
|
|
|
|
|
|
|
|
On the ARM, (if r8 is the static chain regnum, and remembering that
|
|
|
|
|
referencing pc adds an offset of 8) the trampoline looks like:
|
|
|
|
|
ldr r8, [pc, #0]
|
|
|
|
|
ldr pc, [pc]
|
|
|
|
|
.word static chain value
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
.word function's address
|
2003-06-25 20:49:51 +02:00
|
|
|
|
XXX FIXME: When the trampoline returns, r8 will be clobbered. */
|
target.h (asm_out.byte_op, [...]): New fields.
* target.h (asm_out.byte_op, asm_out.aligned_op, asm_out.unaligned_op,
asm_out.integer): New fields.
* target-def.h (TARGET_ASM_BYTE_OP, TARGET_ASM_ALIGNED_[HSDT]I_OP,
TARGET_ASM_UNALIGNED_[HSDT]I_OP, TARGET_ASM_INTEGER): New initialisers.
(TARGET_ASM_ALIGNED_INT_OP, TARGET_ASM_UNALIGNED_INT_OP): Collect
the individual initialisers together.
(TARGET_ASM_OUT): Add the new initialisers.
* output.h (assemble_integer): Return bool.
(integer_asm_op): Declare.
(default_assemble_integer): Declare.
(assemble_aligned_integer): New interface to assemble_integer.
* varasm.c (integer_asm_op): New function to select pseudo-op.
(default_assemble_integer): Default implementation of asm_out.integer.
(assemble_integer): Use the new target hook. Split objects into
words or bytes if the target hook fails. Return bool.
* doc/tm.texi (ASM_OUTPUT_CHAR, ASM_OUTPUT_BYTE, ASM_OUTPUT_SHORT,
ASM_OUTPUT_INT, ASM_OUTPUT_DOUBLE_INT, ASM_OUTPUT_QUADRUPLE_INT,
UNALIGNED_SHORT_ASM_OP, UNALIGNED_INT_ASM_OP,
UNALIGNED_DOUBLE_INT_ASM_OP): Undocument.
Document new target hooks.
* defaults.h (ASM_OUTPUT_ADDR_VEC_ELT): Use integer_asm_op.
* dwarf2asm.c (unaligned_integer_asm_op): Remove.
(dw2_assemble_integer): New.
(dw2_asm_output_data, dw2_asm_output_delta, dw2_asm_output_offset,
dw2_asm_output_pcrel, dw2_asm_output_addr, dw2_asm_output_addr_rtx,
dw2_asm_output_encoded_addr_rtx): Use it.
(dw2_asm_output_nstring): Use assemble_integer for the null terminator.
(dw2_asm_output_data_uleb128, dw2_asm_output_data_sleb128): Use
integer_asm_op to get the byte pseudo-op. Use assemble_integer
if it returns NULL.
* dwarf2asm.h (dw2_assemble_integer): Declare.
* dwarfout.c: Include dwarf2asm.h. Use dwarf2 functions for the
default implementation of most macros.
(output_unsigned_leb128): Use dw2_asm_output_data.
(output_signed_leb128, dwarfout_source_line): Likewise.
(output_reg_number): Use dw2_assemble_integer.
(generate_macinfo_entry): Separate the type and offset arguments.
Use assemble_integer to write the value.
(dwarfout_start_source_file): Update generate_macinfo_entry usage.
(dwarfout_end_source_file, dwarfout_define, dwarfout_undef): Likewise.
* final.c (output_addr_const): Don't put brackets round a subtracted
symbol value or ".".
* halfpic.c (half_pic_finish): Use assemble_aligned_integer.
* config/1750a/1750a.c (assemble_integer_1750a): New,
* config/alpha/alpha.h (literal_section): Avoid ASM_OUTPUT_INT.
* config/arc/arc.c (arc_assemble_integer): New.
* config/arc/arc.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/arm/arm.c (arm_poke_function_name): Likewise.
(arm_assemble_integer): New, extracted from...
* config/arm/arm.h (OUTPUT_INT_ADDR_CONST): ...here, now removed.
(ARM_TRAMPOLINE_TEMPLATE, ARM_FUNCTION_PROFILER): Avoid ASM_OUTPUT_INT.
(ARM_FUNCTION_PROFILER): Likewise.
* config/avr/avr-protos.h (asm_output_byte): Remove.
(asm_output_char, asm_output_short): Remove.
* config/avr/avr.c (avr_assemble_integer): New.
(asm_output_byte, asm_output_char, asm_output_short): Remove.
* config/clipper/clipper.h (ASM_LONG): Remove.
* config/dsp16xx/dsp16xx-protos.h (asm_output_long): Remove.
* config/dsp16xx/dsp16xx.c (asm_output_long): Remove.
* config/elxsi/elxsi.c (elxsi_assemble_integer): New.
* config/i370/i370.c (i370_hlasm_assemble_integer): New.
* config/i370/i370.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_SHORT.
(ASM_BYTE, ASM_SHORT, ASM_LONG): Delete.
* config/i386/att.h, (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i386/linux.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Use
ASM_LONG instead of UNALIGNED_INT_ASM_OP.
* config/i386/sco5.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Likewise.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i386/sysv4.h (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Use
ASM_LONG instead of UNALIGNED_INT_ASM_OP.
* config/i860/fx2800.h (ASM_FILE_END): Avoid ASM_LONG.
* config/i860/i860.c (i860_output_function_epilogue): Likewise.
* config/i860/i860.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
(ASM_SHORT, ASM_LONG): Undefine.
* config/i860/paragon.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/i860/sysv3.h (ASM_OUTPUT_ASCII): Likewise.
* config/i960/i960.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/ia64/ia64.c (ia64_assemble_integer): New.
* config/ia64/ia64.h (ASM_OUTPUT_DWARF_OFFSET): Use integer_asm_op.
(ASM_OUTPUT_DWARF_PCREL): Likewise.
* config/m68hc11/m68hc11.h (ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_VEC_ELT): Avoid ASM_LONG.
(ASM_SHORT, ASM_LONG): Remove.
* config/m68k/m68k.h (INT_OP_GROUP): New macro.
(INT_OP_STANDARD, INT_OP_DOT_WORD, INT_OP_NO_DOT, INT_OP_DC): New
macros, the allowed values for INT_OP_GROUP.
* config/m68k/amix.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP
* config/m68k/atari.h (ASM_OUTPUT_ASCII): Likewise
* config/m68k/m68kelf.h (ASM_OUTPUT_ASCII): Likewise
* config/m68k/auxas.h (BYTE_ASM_OP, WORD_ASM_OP, LONG_ASM_OP): Remove.
(INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m68k/dpx2.h (ASM_LONG): Undefine.
(INT_OP_GROUP): Define to INT_OP_DC.
* config/m68k/dpx2g.h (ASM_LONG): Undefine.
* config/m68k/hp320.h (INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m68k/lynx.h (ASM_LONG): Undefine.
* config/m68k/dpx2g.h (ASM_LONG): Undefine.
* config/m68k/m68kelf.h (ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/m68k/m68kv4.h (ASM_OUTPUT_ASCII): Likewise.
(TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_*.
* config/m68k/mot3300.h (INT_OP_GROUP): Define to INT_OP_STANDARD
for GAS and INT_OP_NO_DOT otherwise.
(ASM_CHAR, ASM_BYTE, ASM_SHORT, ASM_LONG): Remove.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Avoid ASM_LONG.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/m68k/sgs.h (BYTE_ASM_OP, WORD_ASM_OP, LONG_ASM_OP): Remove.
(INT_OP_GROUP): Define to INT_OP_STANDARD.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT,
ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Avoid LONG_ASM_OP.
(ASM_OUTPUT_ASCII): Avoid BYTE_ASM_OP.
* config/m68k/tower-as.h (ASM_LONG): Remove.
(INT_OP_GROUP): Define to INT_OP_NO_DOT.
* config/m88k/m88k.c (output_tdesc): Avoid ASM_LONG.
* config/m88k/m88k.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
(ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT): Avoid ASM_LONG.
* config/mips/iris5.h (TARGET_IRIX5): Define.
* config/mips/mips.c (mips_assemble_integer): New.
* config/mips/sni-svr4.h (ASM_LONG): Undefine.
* config/mmix/mmix-protos.h (mmix_asm_output_double_int): Remove.
* config/mmix/mmix.c (mmix_assemble_integer): New.
(mmix_asm_output_double_int): Remove.
(mmix_print_operand): Call mmix_output_octa directly.
* config/mmix/mmix.h (ASM_LONG): Remove.
* config/ns32k/ns32k.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_INT.
* config/pa/pa.c (pa_assemble_integer): New.
(pa_override_options): Only use aligned DI ops on 64-bit targets.
Only use the unaligned ops if TARGET_GAS.
* config/pdp11/pdp11.c (pdp11_assemble_integer): New.
* config/pdp11/pdp11.h (TRAMPOLINE_TEMPLATE): Avoid ASM_OUTPUT_SHORT.
* config/pj/pj.h (ASM_LONG): Undefine.
* config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Undefine.
* config/rs6000/rs6000.c (rs6000_assemble_integer): New, mostly
extracted from ASM_OUTPUT_INT in sysv4.h. Use in_text_section()
and in_toc_section() rather than the in_section variable.
(rs6000_override_options): Only use DI ops when TARGET_POWERPC64.
* config/rs6000/sysv4.h (TOC_SECTION_FUNCTION): Add in_toc_section().
(RELOCATABLE_NEEDS_FIXUP): Define.
* config/rs6000/xcoff.h (DOUBLE_INT_ASM_OP): Change space to tab.
* config/s390/linux.h (ASM_SHORT, ASM_LONG, ASM_QUAD): Remove.
(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Use integer_asm_op
to get the word directive.
(ASM_OUTPUT_ASCII): Avoid ASM_BYTE_OP.
* config/s390/s390.c (s390_assemble_integer): New.
* config/s390/s390.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY): Use
integer_asm_op to get the word directive.
* config/sparc/sol2.h (ASM_SHORT, ASM_LONG): Remove.
* config/sparc/sparc-protos.h (output_double_int): Remove.
* config/sparc/sparc.c (output_double_int): Move to...
(sparc_assemble_integer): ...this new function.
(sparc_override_options): Only use .uaxword if TARGET_ARCH64.
* config/sparc/sparc.h (ASM_SHORT, ASM_LONG, ASM_LONGLONG): Remove.
* config/sparc/sysv4.h (ASM_LONG): Remove.
(ASM_OUTPUT_LONG_DOUBLE, ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT): Avoid
ASM_LONG.
* config/vax/vax.h (TRAMPOLINE_TEMPLATE): Use assemble_aligned_integer.
* config/we32k/we32k.h (TRAMPOLINE_TEMPLATE): Likewise.
* config/1750a/1750a.c, config/a29k/a29k.c, config/alpha/alpha.c,
config/arc/arc.c, config/arm/arm.c, config/avr/avr.c, config/c4x/c4x.c,
config/clipper/clipper.c, config/convex/convex.c, config/cris/cris.c,
config/d30v/d30v.c, config/dsp16xx/dsp16xx.c, config/elxsi/elxsi.c,
config/fr30/fr30.c, config/h8300/h8300.c, config/i370/i370.c,
config/i386/i386.c, config/i860/i860.c, config/i960/i960.c,
config/ia64/ia64.c, config/m32r/m32r.c, config/m68hc11/m68hc11.c,
config/m68k/m68k.c, config/m88k/m88k.c, config/mips/mips.c,
config/mmix/mmix.c, config/mn10200/mn10200.c, config/mn10300/mn10300.c,
config/ns32k/ns32k.c, config/pa/pa.c, config/pdp11/pdp11.c,
config/sh/sh.c, config/sparc/sparc.c, config/stormy16/stormy16.c,
config/v850/v850.c, config/vax/vax.c, config/we32k/we32k.c
(TARGET_ASM_BYTE_OP, TARGET_ASM_ALIGNED_HI_OP,
TARGET_ASM_ALIGNED_SI_OP, TARGET_ASM_ALIGNED_DI_OP,
TARGET_ASM_UNALIGNED_HI_OP, TARGET_ASM_UNALIGNED_SI_OP,
TARGET_ASM_UNALIGNED_DI_OP, TARGET_ASM_INTEGER): Redefine as
appropriate.
* config/defaults.h, config/darwin.h, config/elfos.h, config/svr3.h,
config/1750a/1750a.h, config/a29k/a29k.h, config/alpha/alpha.h,
config/arc/arc.h, config/arm/arm.h, config/avr/avr.h, config/c4x/c4x.h,
config/clipper/clipper.h, config/convex/convex.h, config/cris/cris.h,
config/d30v/d30v.h, config/dsp16xx/dsp16xx.h, config/elxsi/elxsi.h,
config/fr30/fr30.h, config/h8300/h8300.h, config/i370/i370.h,
config/i386/bsd.h, config/i386/djgpp.h, config/i386/i386.h,
config/i386/sco5.h, config/i386/sol2.h, config/i386/sun386.h,
config/i860/i860.h, config/i960/i960.h, config/ia64/ia64.h,
config/m32r/m32r.h, config/m68hc11/m68hc11.h, config/m68k/auxas.h,
config/m68k/dpx2.h, config/m68k/hp320.h, config/m68k/m68k.h,
config/m68k/mot3300.h, config/m68k/sgs.h, config/m68k/tower-as.h,
config/m88k/m88k.h, config/mcore/mcore-elf.h, config/mcore/mcore.h,
config/mips/iris5.h, config/mips/iris6.h, config/mips/mips.h,
config/mmix/mmix.h, config/mn10200/mn10200.h, config/mn10300/mn10300.h
config/ns32k/encore.h, config/ns32k/ns32k.h, config/pa/pa-64.h,
config/pa/pa.h, config/pdp11/pdp11.h, config/pj/pj.h,
config/romp/romp.h, config/rs6000/linux64.h, config/rs6000/rs6000.h,
config/rs6000/sysv4.h, config/rs6000/xcoff.h, config/s390/linux.h,
config/sh/sh.h, config/sparc/linux64.h, config/sparc/sol2.h,
config/sparc/sp64-elf.h, config/sparc/sparc.h, config/sparc/sysv4.h,
config/stormy16/stormy16.h, config/v850/v850.h, config/vax/vax.h,
config/we32k/we32k.h (ASM_OUTPUT_CHAR, ASM_OUTPUT_BYTE, ASM_BYTE_OP,
ASM_BYTE, ASM_OUTPUT_SHORT, ASM_OUTPUT_INT, ASM_OUTPUT_DOUBLE_INT,
UNALIGNED_SHORT_ASM_OP, UNALIGNED_INT_ASM_OP,
UNALIGNED_DOUBLE_INT_ASM_OP): Undefine, where defined.
From-SVN: r48101
2001-12-17 16:05:40 +01:00
|
|
|
|
#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
|
|
|
|
|
{ \
|
|
|
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
|
|
|
|
|
STATIC_CHAIN_REGNUM, PC_REGNUM); \
|
|
|
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
|
|
|
|
|
PC_REGNUM, PC_REGNUM); \
|
|
|
|
|
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
|
|
|
|
|
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* On the Thumb we always switch into ARM mode to execute the trampoline.
|
|
|
|
|
Why - because it is easier. This code will always be branched to via
|
|
|
|
|
a BX instruction and since the compiler magically generates the address
|
|
|
|
|
of the function the linker has no opportunity to ensure that the
|
|
|
|
|
bottom bit is set. Thus the processor will be in ARM mode when it
|
|
|
|
|
reaches this code. So we duplicate the ARM trampoline code and add
|
|
|
|
|
a switch into Thumb mode as well. */
|
|
|
|
|
#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
|
|
|
|
|
{ \
|
|
|
|
|
fprintf (FILE, "\t.code 32\n"); \
|
|
|
|
|
fprintf (FILE, ".Ltrampoline_start:\n"); \
|
|
|
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
|
|
|
|
|
STATIC_CHAIN_REGNUM, PC_REGNUM); \
|
|
|
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
|
|
|
|
|
IP_REGNUM, PC_REGNUM); \
|
|
|
|
|
asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
|
|
|
|
|
IP_REGNUM, IP_REGNUM); \
|
|
|
|
|
asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
|
|
|
|
|
fprintf (FILE, "\t.word\t0\n"); \
|
|
|
|
|
fprintf (FILE, "\t.word\t0\n"); \
|
|
|
|
|
fprintf (FILE, "\t.code 16\n"); \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
}
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define TRAMPOLINE_TEMPLATE(FILE) \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
ARM_TRAMPOLINE_TEMPLATE (FILE) \
|
|
|
|
|
else \
|
|
|
|
|
THUMB_TRAMPOLINE_TEMPLATE (FILE)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Length in units of the trampoline for entering a nested function. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2002-01-15 21:20:24 +01:00
|
|
|
|
/* Alignment required for a trampoline in bits. */
|
|
|
|
|
#define TRAMPOLINE_ALIGNMENT 32
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2005-05-01 17:28:53 +02:00
|
|
|
|
/* Call __clear_cache after setting up the trampoline unless this is a nop. */
|
|
|
|
|
#ifdef CLEAR_INSN_CACHE
|
|
|
|
|
#define ARM_EMIT_TRAMPOLINE_CACHE_CLEAR(TRAMP) \
|
|
|
|
|
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
|
|
|
|
|
0, VOIDmode, 2, TRAMP, Pmode, \
|
|
|
|
|
plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);
|
|
|
|
|
#else
|
|
|
|
|
#define ARM_EMIT_TRAMPOLINE_CACHE_CLEAR(TRAMP) do {} while (0)
|
|
|
|
|
#endif
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Emit RTL insns to initialize the variable parts of a trampoline.
|
|
|
|
|
FNADDR is an RTX for the address of the function's pure code.
|
|
|
|
|
CXT is an RTX for the static chain value for the function. */
|
2004-01-14 18:51:31 +01:00
|
|
|
|
#ifndef INITIALIZE_TRAMPOLINE
|
|
|
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
|
|
|
|
{ \
|
|
|
|
|
emit_move_insn (gen_rtx_MEM (SImode, \
|
|
|
|
|
plus_constant (TRAMP, \
|
|
|
|
|
TARGET_ARM ? 8 : 16)), \
|
|
|
|
|
CXT); \
|
|
|
|
|
emit_move_insn (gen_rtx_MEM (SImode, \
|
|
|
|
|
plus_constant (TRAMP, \
|
|
|
|
|
TARGET_ARM ? 12 : 20)), \
|
|
|
|
|
FNADDR); \
|
2005-05-01 17:28:53 +02:00
|
|
|
|
ARM_EMIT_TRAMPOLINE_CACHE_CLEAR (TRAMP); \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
}
|
2004-01-14 18:51:31 +01:00
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Addressing modes, and classification of registers for them. */
|
2003-01-15 16:51:11 +01:00
|
|
|
|
#define HAVE_POST_INCREMENT 1
|
|
|
|
|
#define HAVE_PRE_INCREMENT TARGET_ARM
|
|
|
|
|
#define HAVE_POST_DECREMENT TARGET_ARM
|
|
|
|
|
#define HAVE_PRE_DECREMENT TARGET_ARM
|
|
|
|
|
#define HAVE_PRE_MODIFY_DISP TARGET_ARM
|
|
|
|
|
#define HAVE_POST_MODIFY_DISP TARGET_ARM
|
|
|
|
|
#define HAVE_PRE_MODIFY_REG TARGET_ARM
|
|
|
|
|
#define HAVE_POST_MODIFY_REG TARGET_ARM
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Macros to check register numbers against specific register classes. */
|
|
|
|
|
|
|
|
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
|
|
|
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
|
|
|
|
or a pseudo reg currently allocated to a suitable hard reg.
|
|
|
|
|
Since they use reg_renumber, they are safe only once reg_renumber
|
2003-12-25 16:17:37 +01:00
|
|
|
|
has been allocated, which happens in local-alloc.c. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define TEST_REGNO(R, TEST, VALUE) \
|
|
|
|
|
((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
|
|
|
|
|
|
|
|
|
|
/* On the ARM, don't allow the pc to be used. */
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
|
|
|
|
|
(TEST_REGNO (REGNO, <, PC_REGNUM) \
|
|
|
|
|
|| TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
|
|
|
|
|
|| TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
|
|
|
|
|
|
|
|
|
|
#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
|
|
|
|
(TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
|
|
|
|
|
|| (GET_MODE_SIZE (MODE) >= 4 \
|
|
|
|
|
&& TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
|
|
|
|
|
|
|
|
|
|
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
|
|
|
|
(TARGET_THUMB \
|
|
|
|
|
? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
|
|
|
|
|
: ARM_REGNO_OK_FOR_BASE_P (REGNO))
|
|
|
|
|
|
2004-10-12 21:28:56 +02:00
|
|
|
|
/* Nonzero if X can be the base register in a reg+reg addressing mode.
|
|
|
|
|
For Thumb, we can not use SP + reg, so reject SP. */
|
|
|
|
|
#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
|
|
|
|
|
REGNO_OK_FOR_INDEX_P (X)
|
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
/* For ARM code, we don't care about the mode, but for Thumb, the index
|
|
|
|
|
must be suitable for use in a QImode load. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
|
|
|
|
REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Maximum number of registers that can appear in a valid memory address.
|
2003-12-25 16:17:37 +01:00
|
|
|
|
Shifts in addresses can't be by a register. */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
#define MAX_REGS_PER_ADDRESS 2
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Recognize any constant value that is a valid address. */
|
|
|
|
|
/* XXX We can address any constant, eventually... */
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
|
|
|
|
|
#ifdef AOF_ASSEMBLER
|
|
|
|
|
|
|
|
|
|
#define CONSTANT_ADDRESS_P(X) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
(GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
|
|
|
|
|
#else
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
1994-06-01 19:10:50 +02:00
|
|
|
|
#define CONSTANT_ADDRESS_P(X) \
|
|
|
|
|
(GET_CODE (X) == SYMBOL_REF \
|
|
|
|
|
&& (CONSTANT_POOL_ADDRESS_P (X) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|| (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
(CPP_SPEC): Add defines for the cpu type, hard or soft floating point, and the APCS PC size.
(CPP_SPEC): Add defines for the cpu type, hard or soft floating
point, and the APCS PC size.
(TARGET_*): Restructure.
(ARM_FLAG_*): Many new definitions for different target options, not
all of which are supported yet.
(TARGET_SWITCHES): Use the ARM_FLAG_* definitions instead of explicit
numbers.
(prog_mode_type): New enum.
(floating_point_type): Split emulated floating point into FP_SOFT[23].
(OVERRIDE_OPTIONS): Call arm_override_options.
(ARM_CPU_NAME): Default to NULL if not defined by a subtarget.
(BYTES_BIG_ENDIAN): Can now be set as a compilation option.
(RETURN_IN_MEMORY, DEFAULT_PCC_STRUCT_RETURN): New definitions.
(GO_IF_LEGITIMATE_OFFSET): Use different HImode offsets if compiling
for an architecture 4 target. The offsets for floating point
constants are the same as for integers if compiling TARGET_SOFT_FLOAT
(GO_IF_LEGITIMATE_ADDRESS): Don't allow PRE_INC and POST_DEC if
the size is more than 4 bytes. Restrict the range offsets for DImode;
likewise for DFmode when TARGET_SOFT_FLOAT.
(LEGITIMIZE_ADDRESS): Use symbol_mentioned_p, not LEGITIMATE_CONSTANT_P
to determine if a constant address might be better in a register.
Handle DFmode addresses in the same way as DImode if TARGET_SOFT_FLOAT.
(LOAD_EXTEND_OP): If arm_arch4, then HImode also zero-extends.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to handle floating
point constants any more, since arm_reorg will deal with them.
(LEGITIMATE_CONSTANT_P): Is now anything that doesn't contain a
LABEL.
(GO_IF_LEGITIMATE_ADDRESS): Recognize addresses expressions generated
by arm_reorg, but only after reload has completed.
(MACHINE_DEPENDENT_REORG): Define.
(ASM_OUTPUT_SPECIAL_POOL_ENTRY): There should be nothing left in
the pool, even if it might look like it.
(most assembler-specific defines): Move to arm/aout.h.
(CONSTANT_ADDRESS_P): Can't directly access constant strings when
generating assembler for ARMASM.
(ENCODE_SECTION_INFO): Don't define if generating ARMASM assembler.
(ASM_OUTPUT_INTERNAL_LABEL): Generalize, so that it can be used
with all targeted assemblers.
(ASM_OUTPUT_LABEL): Call arm_asm_output_label.
From-SVN: r10681
1995-12-06 12:46:16 +01:00
|
|
|
|
#endif /* AOF_ASSEMBLER */
|
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
|
|
|
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
|
|
|
|
|
|
|
|
|
|
On the ARM, allow any integer (invalid ones are removed later by insn
|
|
|
|
|
patterns), nice doubles and symbol_refs which refer to the function's
|
2000-04-08 16:29:53 +02:00
|
|
|
|
constant pool XXX.
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
2000-02-09 21:00:29 +01:00
|
|
|
|
When generating pic allow anything. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
|
|
|
|
|
|
|
|
|
|
#define THUMB_LEGITIMATE_CONSTANT_P(X) \
|
|
|
|
|
( GET_CODE (X) == CONST_INT \
|
|
|
|
|
|| GET_CODE (X) == CONST_DOUBLE \
|
2002-02-19 23:23:56 +01:00
|
|
|
|
|| CONSTANT_ADDRESS_P (X) \
|
|
|
|
|
|| flag_pic)
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
|
|
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
|
|
|
|
(TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
|
|
|
|
|
|
2000-02-29 02:42:52 +01:00
|
|
|
|
/* Special characters prefixed to function names
|
|
|
|
|
in order to encode attribute like information.
|
|
|
|
|
Note, '@' and '*' have already been taken. */
|
|
|
|
|
#define SHORT_CALL_FLAG_CHAR '^'
|
|
|
|
|
#define LONG_CALL_FLAG_CHAR '#'
|
|
|
|
|
|
|
|
|
|
#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
|
|
|
|
|
(*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
|
|
|
|
|
|
|
|
|
|
#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
|
|
|
|
|
(*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
|
|
|
|
|
|
|
|
|
|
#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
|
|
|
|
|
#define SUBTARGET_NAME_ENCODING_LENGTHS
|
|
|
|
|
#endif
|
|
|
|
|
|
2003-01-31 03:20:48 +01:00
|
|
|
|
/* This is a C fragment for the inside of a switch statement.
|
2000-02-29 02:42:52 +01:00
|
|
|
|
Each case label should return the number of characters to
|
|
|
|
|
be stripped from the start of a function's name, if that
|
|
|
|
|
name starts with the indicated character. */
|
|
|
|
|
#define ARM_NAME_ENCODING_LENGTHS \
|
|
|
|
|
case SHORT_CALL_FLAG_CHAR: return 1; \
|
|
|
|
|
case LONG_CALL_FLAG_CHAR: return 1; \
|
2000-04-09 22:13:21 +02:00
|
|
|
|
case '*': return 1; \
|
2004-08-24 02:30:52 +02:00
|
|
|
|
SUBTARGET_NAME_ENCODING_LENGTHS
|
2000-02-29 02:42:52 +01:00
|
|
|
|
|
|
|
|
|
/* This is how to output a reference to a user-level label named NAME.
|
|
|
|
|
`assemble_name' uses this. */
|
2000-04-11 05:08:01 +02:00
|
|
|
|
#undef ASM_OUTPUT_LABELREF
|
2000-02-29 02:42:52 +01:00
|
|
|
|
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
|
2002-08-30 13:26:53 +02:00
|
|
|
|
arm_asm_output_labelref (FILE, NAME)
|
2000-02-29 02:42:52 +01:00
|
|
|
|
|
2005-04-29 16:09:45 +02:00
|
|
|
|
/* The EABI specifies that constructors should go in .init_array.
|
|
|
|
|
Other targets use .ctors for compatibility. */
|
2005-04-29 16:22:10 +02:00
|
|
|
|
#ifndef ARM_EABI_CTORS_SECTION_OP
|
2005-04-29 16:09:45 +02:00
|
|
|
|
#define ARM_EABI_CTORS_SECTION_OP \
|
|
|
|
|
"\t.section\t.init_array,\"aw\",%init_array"
|
2005-04-29 16:22:10 +02:00
|
|
|
|
#endif
|
|
|
|
|
#ifndef ARM_EABI_DTORS_SECTION_OP
|
2005-04-29 16:09:45 +02:00
|
|
|
|
#define ARM_EABI_DTORS_SECTION_OP \
|
|
|
|
|
"\t.section\t.fini_array,\"aw\",%fini_array"
|
2005-04-29 16:22:10 +02:00
|
|
|
|
#endif
|
2005-04-29 16:09:45 +02:00
|
|
|
|
#define ARM_CTORS_SECTION_OP \
|
|
|
|
|
"\t.section\t.ctors,\"aw\",%progbits"
|
|
|
|
|
#define ARM_DTORS_SECTION_OP \
|
|
|
|
|
"\t.section\t.dtors,\"aw\",%progbits"
|
|
|
|
|
|
|
|
|
|
/* Define CTORS_SECTION_ASM_OP. */
|
|
|
|
|
#undef CTORS_SECTION_ASM_OP
|
|
|
|
|
#undef DTORS_SECTION_ASM_OP
|
|
|
|
|
#ifndef IN_LIBGCC2
|
|
|
|
|
# define CTORS_SECTION_ASM_OP \
|
|
|
|
|
(TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
|
|
|
|
|
# define DTORS_SECTION_ASM_OP \
|
|
|
|
|
(TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
|
|
|
|
|
#else /* !defined (IN_LIBGCC2) */
|
|
|
|
|
/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
|
|
|
|
|
so we cannot use the definition above. */
|
|
|
|
|
# ifdef __ARM_EABI__
|
|
|
|
|
/* The .ctors section is not part of the EABI, so we do not define
|
|
|
|
|
CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
|
|
|
|
|
from trying to use it. We do define it when doing normal
|
|
|
|
|
compilation, as .init_array can be used instead of .ctors. */
|
|
|
|
|
/* There is no need to emit begin or end markers when using
|
|
|
|
|
init_array; the dynamic linker will compute the size of the
|
|
|
|
|
array itself based on special symbols created by the static
|
|
|
|
|
linker. However, we do need to arrange to set up
|
|
|
|
|
exception-handling here. */
|
|
|
|
|
# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
|
|
|
|
|
# define CTOR_LIST_END /* empty */
|
|
|
|
|
# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
|
|
|
|
|
# define DTOR_LIST_END /* empty */
|
|
|
|
|
# else /* !defined (__ARM_EABI__) */
|
|
|
|
|
# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
|
|
|
|
|
# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
|
|
|
|
|
# endif /* !defined (__ARM_EABI__) */
|
|
|
|
|
#endif /* !defined (IN_LIBCC2) */
|
|
|
|
|
|
2005-04-12 08:33:48 +02:00
|
|
|
|
/* True if the operating system can merge entities with vague linkage
|
|
|
|
|
(e.g., symbols in COMDAT group) during dynamic linking. */
|
|
|
|
|
#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
|
|
|
|
|
#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
|
|
|
|
|
#endif
|
|
|
|
|
|
2004-08-11 09:48:13 +02:00
|
|
|
|
/* Set the short-call flag for any function compiled in the current
|
|
|
|
|
compilation unit. We skip this for functions with the section
|
darwin.c, [...]: Fix comment typos.
* config/darwin.c, config/alpha/alpha.h, config/arm/arm.c,
config/arm/arm.h, config/arm/arm.md, config/arm/bpabi.h,
config/arm/predicates.md, config/frv/frv.c, config/frv/frv.md,
config/h8300/h8300.md, config/i386/gmm_malloc.h,
config/ia64/ia64.md, config/ip2k/libgcc.S,
config/mips/mips-ps-3d.md, config/mips/mips.c,
config/rs6000/rs6000.c, config/s390/s390.c,
config/sh/symbian.c: Fix comment typos.
From-SVN: r87295
2004-09-10 13:55:21 +02:00
|
|
|
|
attribute when long-calls are in effect as this tells the compiler
|
2004-08-11 09:48:13 +02:00
|
|
|
|
that the section might be placed a long way from the caller.
|
|
|
|
|
See arm_is_longcall_p() for more information. */
|
2000-02-29 02:42:52 +01:00
|
|
|
|
#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
|
2004-08-11 09:48:13 +02:00
|
|
|
|
if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
|
|
|
|
|
arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
|
2000-02-29 02:42:52 +01:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
|
|
|
|
and check its validity for a certain class.
|
|
|
|
|
We have two alternate definitions for each of them.
|
|
|
|
|
The usual definition accepts all pseudo regs; the other rejects
|
|
|
|
|
them unless they have been allocated suitable hard regs.
|
|
|
|
|
The symbol REG_OK_STRICT causes the latter definition to be used. */
|
|
|
|
|
#ifndef REG_OK_STRICT
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define ARM_REG_OK_FOR_BASE_P(X) \
|
|
|
|
|
(REGNO (X) <= LAST_ARM_REGNUM \
|
|
|
|
|
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|
|
|
|
|
|| REGNO (X) == FRAME_POINTER_REGNUM \
|
|
|
|
|
|| REGNO (X) == ARG_POINTER_REGNUM)
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
|
|
(REGNO (X) <= LAST_LO_REGNUM \
|
|
|
|
|
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|
|
|
|
|
|| (GET_MODE_SIZE (MODE) >= 4 \
|
|
|
|
|
&& (REGNO (X) == STACK_POINTER_REGNUM \
|
|
|
|
|
|| (X) == hard_frame_pointer_rtx \
|
|
|
|
|
|| (X) == arg_pointer_rtx)))
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2003-01-23 19:10:46 +01:00
|
|
|
|
#define REG_STRICT_P 0
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#else /* REG_OK_STRICT */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define ARM_REG_OK_FOR_BASE_P(X) \
|
|
|
|
|
ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
|
|
THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2003-01-23 19:10:46 +01:00
|
|
|
|
#define REG_STRICT_P 1
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#endif /* REG_OK_STRICT */
|
2000-12-02 18:10:29 +01:00
|
|
|
|
|
|
|
|
|
/* Now define some helpers in terms of the above. */
|
|
|
|
|
|
|
|
|
|
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
|
|
(TARGET_THUMB \
|
|
|
|
|
? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
|
|
|
|
|
: ARM_REG_OK_FOR_BASE_P (X))
|
|
|
|
|
|
|
|
|
|
#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
|
|
|
|
|
|
|
|
|
|
/* For Thumb, a valid index register is anything that can be used in
|
|
|
|
|
a byte load instruction. */
|
|
|
|
|
#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
|
|
|
|
|
|
|
|
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
|
|
|
|
or if it is a pseudo reg. On the Thumb, the stack pointer
|
|
|
|
|
is not suitable. */
|
|
|
|
|
#define REG_OK_FOR_INDEX_P(X) \
|
|
|
|
|
(TARGET_THUMB \
|
|
|
|
|
? THUMB_REG_OK_FOR_INDEX_P (X) \
|
|
|
|
|
: ARM_REG_OK_FOR_INDEX_P (X))
|
|
|
|
|
|
2004-10-12 21:28:56 +02:00
|
|
|
|
/* Nonzero if X can be the base register in a reg+reg addressing mode.
|
|
|
|
|
For Thumb, we can not use SP + reg, so reject SP. */
|
|
|
|
|
#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
|
|
|
|
|
REG_OK_FOR_INDEX_P (X)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
|
|
|
|
that is a valid memory address for an instruction.
|
|
|
|
|
The MODE argument is the machine mode for the MEM expression
|
2003-01-23 19:10:46 +01:00
|
|
|
|
that wants to use this address. */
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define ARM_BASE_REGISTER_RTX_P(X) \
|
|
|
|
|
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2000-12-02 18:10:29 +01:00
|
|
|
|
#define ARM_INDEX_REGISTER_RTX_P(X) \
|
|
|
|
|
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2003-01-23 19:10:46 +01:00
|
|
|
|
#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
|
|
|
|
|
{ \
|
2004-03-13 12:19:23 +01:00
|
|
|
|
if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
|
2003-01-23 19:10:46 +01:00
|
|
|
|
goto WIN; \
|
2003-01-22 17:01:43 +01:00
|
|
|
|
}
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
2003-01-23 19:10:46 +01:00
|
|
|
|
#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
|
|
|
|
|
{ \
|
|
|
|
|
if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
|
|
|
|
|
goto WIN; \
|
|
|
|
|
}
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
|
|
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
|
|
|
|
|
else /* if (TARGET_THUMB) */ \
|
2004-08-24 02:30:52 +02:00
|
|
|
|
THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
|
2003-01-23 19:10:46 +01:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Try machine-dependent ways of modifying an illegitimate address
|
2003-01-29 17:50:34 +01:00
|
|
|
|
to be legitimate. If we find one, return the new, valid address. */
|
|
|
|
|
#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
|
|
|
|
do { \
|
|
|
|
|
X = arm_legitimize_address (X, OLDX, MODE); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2004-02-25 18:03:27 +01:00
|
|
|
|
#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
|
|
|
|
do { \
|
|
|
|
|
X = thumb_legitimize_address (X, OLDX, MODE); \
|
2003-01-29 17:50:34 +01:00
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
|
|
|
|
do { \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
|
|
|
|
|
else \
|
|
|
|
|
THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
|
2004-02-25 18:03:27 +01:00
|
|
|
|
\
|
|
|
|
|
if (memory_address_p (MODE, X)) \
|
|
|
|
|
goto WIN; \
|
2003-01-29 17:50:34 +01:00
|
|
|
|
} while (0)
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Go to LABEL if ADDR (a legitimate address expression)
|
|
|
|
|
has an effect that depends on the machine mode it is used for. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
{ \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
|
|
|
|
|
|| GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
goto LABEL; \
|
|
|
|
|
}
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
|
|
|
|
/* Nothing helpful to do for the Thumb */
|
|
|
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
|
|
|
|
if (TARGET_ARM) \
|
2004-08-24 02:30:52 +02:00
|
|
|
|
ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Specify the machine mode that this machine uses
|
|
|
|
|
for the index in the tablejump instruction. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define CASE_VECTOR_MODE Pmode
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* signed 'char' is most compatible, but RISC OS wants it unsigned.
|
|
|
|
|
unsigned is probably best, but may break some code. */
|
|
|
|
|
#ifndef DEFAULT_SIGNED_CHAR
|
1994-06-23 18:02:41 +02:00
|
|
|
|
#define DEFAULT_SIGNED_CHAR 0
|
1991-12-06 03:11:44 +01:00
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Max number of bytes we can move from memory to memory
|
1992-09-06 23:37:08 +02:00
|
|
|
|
in one reasonably fast instruction. */
|
|
|
|
|
#define MOVE_MAX 4
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2000-12-04 01:23:35 +01:00
|
|
|
|
#undef MOVE_RATIO
|
2003-10-19 03:01:46 +02:00
|
|
|
|
#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
|
2000-12-04 01:23:35 +01:00
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* Define if operations between registers always perform the operation
|
|
|
|
|
on the full register even if a narrower mode is specified. */
|
|
|
|
|
#define WORD_REGISTER_OPERATIONS
|
|
|
|
|
|
|
|
|
|
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
|
|
|
|
|
will either zero-extend or sign-extend. The value of this macro should
|
|
|
|
|
be the code that says which one of the two operations is implicitly
|
rtl.def (NIL): Delete.
* rtl.def (NIL): Delete.
* read-rtl.c (read_rtx): Handle (nil) like (define_constants).
Tighten the syntax a little.
* cfgloop.h, combine.c, cse.c, loop-iv.c, postreload.c, reload.c
* config/alpha/alpha.c, config/alpha/alpha.h, config/arc/arc.h
* config/arm/arm.h, config/frv/frv.h, config/i386/i386.c
* config/i386/predicates.md, config/m32r/m32r.h
* config/m68hc11/m68hc11.c, config/mcore/mcore.h, config/mips/mips.c
* config/mmix/mmix.c, config/pa/pa.h, config/sh/sh.h
* config/sparc/sparc.h, doc/tm.texi:
Replace all occurrences of NIL with UNKNOWN.
From-SVN: r86193
2004-08-18 19:05:14 +02:00
|
|
|
|
done, UNKNOWN if none. */
|
1994-06-06 15:14:03 +02:00
|
|
|
|
#define LOAD_EXTEND_OP(MODE) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
(TARGET_THUMB ? ZERO_EXTEND : \
|
|
|
|
|
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
|
rtl.def (NIL): Delete.
* rtl.def (NIL): Delete.
* read-rtl.c (read_rtx): Handle (nil) like (define_constants).
Tighten the syntax a little.
* cfgloop.h, combine.c, cse.c, loop-iv.c, postreload.c, reload.c
* config/alpha/alpha.c, config/alpha/alpha.h, config/arc/arc.h
* config/arm/arm.h, config/frv/frv.h, config/i386/i386.c
* config/i386/predicates.md, config/m32r/m32r.h
* config/m68hc11/m68hc11.c, config/mcore/mcore.h, config/mips/mips.c
* config/mmix/mmix.c, config/pa/pa.h, config/sh/sh.h
* config/sparc/sparc.h, doc/tm.texi:
Replace all occurrences of NIL with UNKNOWN.
From-SVN: r86193
2004-08-18 19:05:14 +02:00
|
|
|
|
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Nonzero if access to memory by bytes is slow and undesirable. */
|
|
|
|
|
#define SLOW_BYTE_ACCESS 0
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1991-12-06 03:11:44 +01:00
|
|
|
|
/* Immediate shift counts are truncated by the output routines (or was it
|
|
|
|
|
the assembler?). Shift counts in a register are truncated by ARM. Note
|
|
|
|
|
that the native compiler puts too large (> 32) immediate shift counts
|
|
|
|
|
into a register and shifts by the register, letting the ARM decide what
|
|
|
|
|
to do instead of doing that itself. */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
|
|
|
|
|
code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
|
|
|
|
|
On the arm, Y in a register is used modulo 256 for the shift. Only for
|
2003-12-25 16:17:37 +01:00
|
|
|
|
rotates is modulo 32 used. */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* #define SHIFT_COUNT_TRUNCATED 1 */
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* All integers have the same format so truncation is easy. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Calling from registers is a massive pain. */
|
|
|
|
|
#define NO_FUNCTION_CSE 1
|
|
|
|
|
|
|
|
|
|
/* The machine modes of pointers and functions */
|
|
|
|
|
#define Pmode SImode
|
|
|
|
|
#define FUNCTION_MODE Pmode
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define ARM_FRAME_RTX(X) \
|
|
|
|
|
( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
|
1994-06-23 18:02:41 +02:00
|
|
|
|
|| (X) == arg_pointer_rtx)
|
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* Moves to and from memory are quite expensive */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define MEMORY_MOVE_COST(M, CLASS, IN) \
|
|
|
|
|
(TARGET_ARM ? 10 : \
|
|
|
|
|
((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
|
|
|
|
|
* (CLASS == LO_REGS ? 1 : 2)))
|
2004-08-24 02:30:52 +02:00
|
|
|
|
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* Try to generate sequences that don't involve branches, we can then use
|
|
|
|
|
conditional instructions */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define BRANCH_COST \
|
|
|
|
|
(TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
|
1997-05-09 00:17:34 +02:00
|
|
|
|
|
|
|
|
|
/* Position Independent Code. */
|
|
|
|
|
/* We decide which register to use based on the compilation options and
|
|
|
|
|
the assembler in use; this is more general than the APCS restriction of
|
|
|
|
|
using sb (r9) all the time. */
|
|
|
|
|
extern int arm_pic_register;
|
|
|
|
|
|
|
|
|
|
/* The register number of the register used to address a table of static
|
|
|
|
|
data addresses in memory. */
|
|
|
|
|
#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
|
|
|
|
|
|
1999-02-22 17:47:59 +01:00
|
|
|
|
/* We can't directly access anything that contains a symbol,
|
|
|
|
|
nor can we indirect via the constant pool. */
|
2000-02-09 21:00:29 +01:00
|
|
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
2002-07-16 17:39:22 +02:00
|
|
|
|
(!(symbol_mentioned_p (X) \
|
|
|
|
|
|| label_mentioned_p (X) \
|
|
|
|
|
|| (GET_CODE (X) == SYMBOL_REF \
|
|
|
|
|
&& CONSTANT_POOL_ADDRESS_P (X) \
|
|
|
|
|
&& (symbol_mentioned_p (get_pool_constant (X)) \
|
|
|
|
|
|| label_mentioned_p (get_pool_constant (X))))))
|
|
|
|
|
|
1999-05-22 11:40:04 +02:00
|
|
|
|
/* We need to know when we are making a constant pool; this determines
|
|
|
|
|
whether data needs to be in the GOT or can be referenced via a GOT
|
|
|
|
|
offset. */
|
|
|
|
|
extern int making_const_table;
|
2000-02-09 21:00:29 +01:00
|
|
|
|
|
2000-02-29 02:42:52 +01:00
|
|
|
|
/* Handle pragmas for compatibility with Intel's compilers. */
|
2003-01-01 13:27:02 +01:00
|
|
|
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
|
|
|
|
c_register_pragma (0, "long_calls", arm_pr_long_calls); \
|
|
|
|
|
c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
|
|
|
|
|
c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
|
c-pragma.h: Define HANDLE_GENERIC_PRAGMAS if REGISTER_TARGET_PRAGMAS is defined.
* c-pragma.h: Define HANDLE_GENERIC_PRAGMAS if
REGISTER_TARGET_PRAGMAS is defined. Duplicate some
definitions from cpplib.h.
* cpplib.h: Don't typedef struct cpp_reader if c-pragma.h has
already done it.
* tm.texi: Document HANDLE_PRAGMA as no longer supported. Add
documentation for REGISTER_TARGET_PRAGMAS.
* c-lex.c: Include cpplib.h before c-pragma.h. Define a
default-pragma callback to implement -Wunknown-pragmas if
USE_CPPLIB.
* c-parse.in: Move all includes to top of file.
* c-pragma.c: Include cpplib.h before c-pragma.h. Include
tm_p.h.
(dispatch_pragma): Put the namespace in the -Wunknown-pragmas
warning.
(init_pragma): If REGISTER_TARGET_PRAGMAS is defined, call it.
* arm.h, arm-protos.h, arm.c,
c4x.h, c4x-protos.h, c4x.c,
h8300.h, h8300-protos.h, h8300.c,
i370.h, i370-protos.h, i370.c,
i960.h, i960-protos.h, i960.c,
sh.h, sh-protos.h, sh.c,
v850.h, v850-protos.h, v850.c: Convert HANDLE_PRAGMA-based
pragmata scheme to use REGISTER_TARGET_PRAGMAS instead.
* d30v.h: Don't mention HANDLE_PRAGMA in comment. Add
multiple include guard.
* i370.md (untyped_call): Use GEN_CALL.
(umodsi3): Remove unused variable.
* sh/elf.h: Don't undef HANDLE_SYSV_PRAGMA.
* v850.c (output_move_single, output_move_double): Constify
return value.
(print_operand): Constify a char *.
* v850.h (struct small_memory_info): Constify name member.
From-SVN: r36249
2000-09-08 00:24:34 +02:00
|
|
|
|
} while (0)
|
|
|
|
|
|
2003-12-25 16:17:37 +01:00
|
|
|
|
/* Condition code information. */
|
1993-10-03 17:33:02 +01:00
|
|
|
|
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
|
Makefile.in (MACHMODE_H): Add @extra_modes_file@.
* Makefile.in (MACHMODE_H): Add @extra_modes_file@.
* configure.in: If $srcdir/config/${cpu_type}/${cpu_type}-modes.def
exists, substitute its pathname as @extra_modes_file@, define
EXTRA_MODES_FILE to be an appropriate string to #include it
with, and define EXTRA_CC_MODES to 1.
* machmode.def: Update comments. Include EXTRA_MODES_FILE if
it's defined. Get rid of redundancy in calling sequence for
CC; don't use it to define CCmode, to avoid a warning.
* libgcc2.c: Include symcat.h for the sake of machmode.def.
* arc-modes.def, arm-modes.def, c4x-modes.def, i386-modes.def,
i960-modes.def, ia64-modes.def, m88k-modes.def, mmix-modes.def,
pa-modes.def, pdp11-modes.def, rs6000-modes.def, sparc-modes.def:
New files.
* arc.h, arm.h, c4x.h, i386.h, i960.h, ia64.h, m88k.h, mmix.h,
pa.h, pdp11.h, rs6000.h, sparc.h: Don't define EXTRA_CC_MODES.
* doc/sourcebuild.texi, doc/tm.texi: Document new scheme for
defining extra CC modes.
From-SVN: r54478
2002-06-11 00:35:56 +02:00
|
|
|
|
return the mode to be used for the comparison. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
|
|
|
|
#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
|
1993-10-03 17:33:02 +01:00
|
|
|
|
|
2004-08-30 00:18:25 +02:00
|
|
|
|
#define REVERSIBLE_CC_MODE(MODE) 1
|
|
|
|
|
|
|
|
|
|
#define REVERSE_CONDITION(CODE,MODE) \
|
|
|
|
|
(((MODE) == CCFPmode || (MODE) == CCFPEmode) \
|
|
|
|
|
? reverse_condition_maybe_unordered (code) \
|
|
|
|
|
: reverse_condition (code))
|
1994-06-01 19:10:50 +02:00
|
|
|
|
|
1999-07-05 10:44:36 +02:00
|
|
|
|
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
|
|
|
|
|
do \
|
|
|
|
|
{ \
|
|
|
|
|
if (GET_CODE (OP1) == CONST_INT \
|
|
|
|
|
&& ! (const_ok_for_arm (INTVAL (OP1)) \
|
|
|
|
|
|| (const_ok_for_arm (- INTVAL (OP1))))) \
|
|
|
|
|
{ \
|
|
|
|
|
rtx const_op = OP1; \
|
|
|
|
|
CODE = arm_canonicalize_comparison ((CODE), &const_op); \
|
|
|
|
|
OP1 = const_op; \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
while (0)
|
1996-05-04 18:13:28 +02:00
|
|
|
|
|
2003-02-05 23:37:54 +01:00
|
|
|
|
/* The arm5 clz instruction returns 32. */
|
|
|
|
|
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#undef ASM_APP_OFF
|
|
|
|
|
#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Output a push or a pop instruction (only used when profiling). */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
|
2003-09-24 11:06:32 +02:00
|
|
|
|
do \
|
|
|
|
|
{ \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
|
|
|
|
|
STACK_POINTER_REGNUM, REGNO); \
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else \
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asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
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} while (0)
|
2000-04-08 16:29:53 +02:00
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#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
|
2003-09-24 11:06:32 +02:00
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do \
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{ \
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if (TARGET_ARM) \
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asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
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STACK_POINTER_REGNUM, REGNO); \
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else \
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asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
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} while (0)
|
2000-04-08 16:29:53 +02:00
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/* This is how to output a label which precedes a jumptable. Since
|
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Thumb instructions are 2 bytes, we may need explicit alignment here. */
|
2001-09-14 12:19:30 +02:00
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#undef ASM_OUTPUT_CASE_LABEL
|
2000-04-08 16:29:53 +02:00
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#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
|
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do \
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{ \
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|
if (TARGET_THUMB) \
|
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ASM_OUTPUT_ALIGN (FILE, 2); \
|
2003-09-24 11:06:32 +02:00
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(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
|
2000-04-08 16:29:53 +02:00
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} \
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while (0)
|
1991-12-06 03:11:44 +01:00
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1999-07-17 15:44:35 +02:00
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#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
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do \
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{ \
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2000-04-08 16:29:53 +02:00
|
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if (TARGET_THUMB) \
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{ \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
|
if (is_called_in_ARM_mode (DECL) \
|
|
|
|
|
|| current_function_is_thunk) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
fprintf (STREAM, "\t.code 32\n") ; \
|
|
|
|
|
else \
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
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fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
|
2000-04-08 16:29:53 +02:00
|
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} \
|
1999-07-17 15:44:35 +02:00
|
|
|
|
if (TARGET_POKE_FUNCTION_NAME) \
|
2000-03-29 21:15:36 +02:00
|
|
|
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arm_poke_function_name (STREAM, (char *) NAME); \
|
1999-07-17 15:44:35 +02:00
|
|
|
|
} \
|
|
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while (0)
|
1991-12-06 03:11:44 +01:00
|
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2000-04-08 16:29:53 +02:00
|
|
|
|
/* For aliases of functions we use .thumb_set instead. */
|
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|
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
|
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do \
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{ \
|
2001-10-19 21:42:46 +02:00
|
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const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
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const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
|
2000-04-08 16:29:53 +02:00
|
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\
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|
|
if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
|
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|
|
|
{ \
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|
|
|
|
fprintf (FILE, "\t.thumb_set "); \
|
|
|
|
|
assemble_name (FILE, LABEL1); \
|
|
|
|
|
fprintf (FILE, ","); \
|
|
|
|
|
assemble_name (FILE, LABEL2); \
|
|
|
|
|
fprintf (FILE, "\n"); \
|
|
|
|
|
} \
|
|
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else \
|
|
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|
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ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
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|
|
} \
|
|
|
|
|
while (0)
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2001-04-26 17:37:02 +02:00
|
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|
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
|
|
|
|
|
/* To support -falign-* switches we need to use .p2align so
|
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|
|
that alignment directives in code sections will be padded
|
|
|
|
|
with no-op instructions, rather than zeroes. */
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
|
2001-04-26 17:37:02 +02:00
|
|
|
|
if ((LOG) != 0) \
|
|
|
|
|
{ \
|
|
|
|
|
if ((MAX_SKIP) == 0) \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
|
2001-04-26 17:37:02 +02:00
|
|
|
|
else \
|
|
|
|
|
fprintf ((FILE), "\t.p2align %d,,%d\n", \
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
(int) (LOG), (int) (MAX_SKIP)); \
|
2001-04-26 17:37:02 +02:00
|
|
|
|
}
|
|
|
|
|
#endif
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Only perform branch elimination (by making instructions conditional) if
|
2003-06-15 09:51:35 +02:00
|
|
|
|
we're optimizing. Otherwise it's of no use anyway. */
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
|
|
|
|
|
if (TARGET_ARM && optimize) \
|
|
|
|
|
arm_final_prescan_insn (INSN); \
|
|
|
|
|
else if (TARGET_THUMB) \
|
|
|
|
|
thumb_final_prescan_insn (INSN)
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
1994-06-02 20:41:52 +02:00
|
|
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
(CODE == '@' || CODE == '|' \
|
|
|
|
|
|| (TARGET_ARM && (CODE == '?')) \
|
|
|
|
|
|| (TARGET_THUMB && (CODE == '_')))
|
1999-07-17 15:44:35 +02:00
|
|
|
|
|
1994-06-02 20:41:52 +02:00
|
|
|
|
/* Output an operand of an instruction. */
|
1991-12-06 03:11:44 +01:00
|
|
|
|
#define PRINT_OPERAND(STREAM, X, CODE) \
|
1994-06-02 20:41:52 +02:00
|
|
|
|
arm_print_operand (STREAM, X, CODE)
|
|
|
|
|
|
2001-06-24 11:46:02 +02:00
|
|
|
|
#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
|
|
|
|
|
(HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
|
2001-10-22 21:36:24 +02:00
|
|
|
|
: ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
|
|
|
|
|
((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
|
|
|
|
|
? ((~ (unsigned HOST_WIDE_INT) 0) \
|
|
|
|
|
& ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
|
1994-06-02 20:41:52 +02:00
|
|
|
|
: 0))))
|
1991-12-06 03:11:44 +01:00
|
|
|
|
|
|
|
|
|
/* Output the address of an operand. */
|
2003-01-15 16:51:11 +01:00
|
|
|
|
#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
|
|
|
|
|
{ \
|
|
|
|
|
int is_minus = GET_CODE (X) == MINUS; \
|
|
|
|
|
\
|
|
|
|
|
if (GET_CODE (X) == REG) \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
|
|
|
|
|
else if (GET_CODE (X) == PLUS || is_minus) \
|
|
|
|
|
{ \
|
|
|
|
|
rtx base = XEXP (X, 0); \
|
|
|
|
|
rtx index = XEXP (X, 1); \
|
|
|
|
|
HOST_WIDE_INT offset = 0; \
|
|
|
|
|
if (GET_CODE (base) != REG) \
|
|
|
|
|
{ \
|
2003-12-25 16:17:37 +01:00
|
|
|
|
/* Ensure that BASE is a register. */ \
|
|
|
|
|
/* (one of them must be). */ \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
rtx temp = base; \
|
|
|
|
|
base = index; \
|
|
|
|
|
index = temp; \
|
|
|
|
|
} \
|
|
|
|
|
switch (GET_CODE (index)) \
|
|
|
|
|
{ \
|
|
|
|
|
case CONST_INT: \
|
|
|
|
|
offset = INTVAL (index); \
|
|
|
|
|
if (is_minus) \
|
|
|
|
|
offset = -offset; \
|
2003-06-04 23:18:48 +02:00
|
|
|
|
asm_fprintf (STREAM, "[%r, #%wd]", \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
REGNO (base), offset); \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
|
|
|
|
case REG: \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, %s%r]", \
|
|
|
|
|
REGNO (base), is_minus ? "-" : "", \
|
|
|
|
|
REGNO (index)); \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
|
|
|
|
case MULT: \
|
|
|
|
|
case ASHIFTRT: \
|
|
|
|
|
case LSHIFTRT: \
|
|
|
|
|
case ASHIFT: \
|
|
|
|
|
case ROTATERT: \
|
|
|
|
|
{ \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, %s%r", \
|
|
|
|
|
REGNO (base), is_minus ? "-" : "", \
|
|
|
|
|
REGNO (XEXP (index, 0))); \
|
|
|
|
|
arm_print_operand (STREAM, index, 'S'); \
|
|
|
|
|
fputs ("]", STREAM); \
|
|
|
|
|
break; \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
default: \
|
arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and gcc_unreachable as appropriate.
* config/arm/arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and
gcc_unreachable as appropriate.
(THUMB_PRINT_OPERAND_ADDRESS): Likewise.
* config/arm/arm.c (arm_override_options, arm_compute_func_type,
use_return_insn, const_ok_for_op, arm_gen_constant,
arm_canonicalize_comparison, legitimize_pic_address,
thumb_find_work_register, arm_load_pic_register, arm_rtx_costs_1,
arm_cirrus_insn_p, cirrus_reorg, minmax_code,
load_multiple_sequence, emit_ldm_seq, store_multiple_sequence,
emit_stm_seq, arm_gen_movmemqi, arm_select_dominance_cc_mode,
arm_select_cc_mode, arm_reload_in_hi, arm_reload_out_hi,
move_minipool_fix_forward_ref, move_minipool_fix_backward_ref,
dump_minipool, create_fix_barrier, push_minipool_fix, arm_reorg,
fp_immediate_constant, fp_const_from_val, vfp_output_fstmx,
output_call, output_mov_long_double_fpa_from_arm,
output_mov_long_double_arm_from_fpa,
output_mov_double_fpa_from_arm, output_mov_double_arm_from_fpa,
output_move_double, arithmetic_instr, shift_op, int_log2,
output_return_instruction, arm_output_function_prologue,
arm_output_epilogue, arm_output_function_epilogue,
emit_multi_reg_push, arm_get_frame_offsets,
arm_compute_initial_elimination_offset, arm_expand_prologue,
arm_print_operand, arm_assemble_integer, get_arm_condition_code,
arm_final_prescan_insn, arm_init_iwmmxt_builtins,
arm_expand_binop_builtin, thumb_pushpop, thumb_far_jump_used_p,
thumb_compute_initial_elimination_offset,
thumb_output_function_prologue, thumb_load_double_from_address,
thumb_output_move_mem_multiple, thumb_reload_out_hi,
arm_emit_vector_const, arm_dbx_register_number): Likewise.
* config/arm/pe.c (arm_mark_dllexport, arm_mark_dllimport): Likewise.
* config/arm/arm.md (thumb_extendhisi2,
*thumb_extendhisi2_insn_v6, *thumb_extendqisi2,
*thumb_extendqisi2_v6, movhi, *thumb_movhi_insn,
thumb_movhi_clobber, movqi, *arm_buneq, *arm_bltgt,
*arm_buneq_reversed, *arm_bltgt_reversed, suneq, sltgt): Likewise.
* config/arm/cirrus.md (*cirrus_arm_movdi,
*cirrus_movdf_hard_insn): Likewise.
* config/arm/vfp.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
From-SVN: r98850
2005-04-27 18:09:03 +02:00
|
|
|
|
gcc_unreachable (); \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
|
|
|
|
|
|| GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
|
|
|
|
|
{ \
|
|
|
|
|
extern enum machine_mode output_memory_reference_mode; \
|
|
|
|
|
\
|
arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and gcc_unreachable as appropriate.
* config/arm/arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and
gcc_unreachable as appropriate.
(THUMB_PRINT_OPERAND_ADDRESS): Likewise.
* config/arm/arm.c (arm_override_options, arm_compute_func_type,
use_return_insn, const_ok_for_op, arm_gen_constant,
arm_canonicalize_comparison, legitimize_pic_address,
thumb_find_work_register, arm_load_pic_register, arm_rtx_costs_1,
arm_cirrus_insn_p, cirrus_reorg, minmax_code,
load_multiple_sequence, emit_ldm_seq, store_multiple_sequence,
emit_stm_seq, arm_gen_movmemqi, arm_select_dominance_cc_mode,
arm_select_cc_mode, arm_reload_in_hi, arm_reload_out_hi,
move_minipool_fix_forward_ref, move_minipool_fix_backward_ref,
dump_minipool, create_fix_barrier, push_minipool_fix, arm_reorg,
fp_immediate_constant, fp_const_from_val, vfp_output_fstmx,
output_call, output_mov_long_double_fpa_from_arm,
output_mov_long_double_arm_from_fpa,
output_mov_double_fpa_from_arm, output_mov_double_arm_from_fpa,
output_move_double, arithmetic_instr, shift_op, int_log2,
output_return_instruction, arm_output_function_prologue,
arm_output_epilogue, arm_output_function_epilogue,
emit_multi_reg_push, arm_get_frame_offsets,
arm_compute_initial_elimination_offset, arm_expand_prologue,
arm_print_operand, arm_assemble_integer, get_arm_condition_code,
arm_final_prescan_insn, arm_init_iwmmxt_builtins,
arm_expand_binop_builtin, thumb_pushpop, thumb_far_jump_used_p,
thumb_compute_initial_elimination_offset,
thumb_output_function_prologue, thumb_load_double_from_address,
thumb_output_move_mem_multiple, thumb_reload_out_hi,
arm_emit_vector_const, arm_dbx_register_number): Likewise.
* config/arm/pe.c (arm_mark_dllexport, arm_mark_dllimport): Likewise.
* config/arm/arm.md (thumb_extendhisi2,
*thumb_extendhisi2_insn_v6, *thumb_extendqisi2,
*thumb_extendqisi2_v6, movhi, *thumb_movhi_insn,
thumb_movhi_clobber, movqi, *arm_buneq, *arm_bltgt,
*arm_buneq_reversed, *arm_bltgt_reversed, suneq, sltgt): Likewise.
* config/arm/cirrus.md (*cirrus_arm_movdi,
*cirrus_movdf_hard_insn): Likewise.
* config/arm/vfp.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
From-SVN: r98850
2005-04-27 18:09:03 +02:00
|
|
|
|
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
\
|
|
|
|
|
if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, #%s%d]!", \
|
|
|
|
|
REGNO (XEXP (X, 0)), \
|
|
|
|
|
GET_CODE (X) == PRE_DEC ? "-" : "", \
|
|
|
|
|
GET_MODE_SIZE (output_memory_reference_mode)); \
|
|
|
|
|
else \
|
|
|
|
|
asm_fprintf (STREAM, "[%r], #%s%d", \
|
|
|
|
|
REGNO (XEXP (X, 0)), \
|
|
|
|
|
GET_CODE (X) == POST_DEC ? "-" : "", \
|
|
|
|
|
GET_MODE_SIZE (output_memory_reference_mode)); \
|
|
|
|
|
} \
|
|
|
|
|
else if (GET_CODE (X) == PRE_MODIFY) \
|
|
|
|
|
{ \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
|
|
|
|
|
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
|
2003-06-04 23:18:48 +02:00
|
|
|
|
asm_fprintf (STREAM, "#%wd]!", \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
INTVAL (XEXP (XEXP (X, 1), 1))); \
|
|
|
|
|
else \
|
|
|
|
|
asm_fprintf (STREAM, "%r]!", \
|
|
|
|
|
REGNO (XEXP (XEXP (X, 1), 1))); \
|
|
|
|
|
} \
|
|
|
|
|
else if (GET_CODE (X) == POST_MODIFY) \
|
|
|
|
|
{ \
|
|
|
|
|
asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
|
|
|
|
|
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
|
2003-06-04 23:18:48 +02:00
|
|
|
|
asm_fprintf (STREAM, "#%wd", \
|
2003-01-15 16:51:11 +01:00
|
|
|
|
INTVAL (XEXP (XEXP (X, 1), 1))); \
|
|
|
|
|
else \
|
|
|
|
|
asm_fprintf (STREAM, "%r", \
|
|
|
|
|
REGNO (XEXP (XEXP (X, 1), 1))); \
|
|
|
|
|
} \
|
|
|
|
|
else output_addr_const (STREAM, X); \
|
1991-12-06 03:11:44 +01:00
|
|
|
|
}
|
1996-05-04 18:13:28 +02:00
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
|
|
|
|
|
{ \
|
|
|
|
|
if (GET_CODE (X) == REG) \
|
|
|
|
|
asm_fprintf (STREAM, "[%r]", REGNO (X)); \
|
|
|
|
|
else if (GET_CODE (X) == POST_INC) \
|
|
|
|
|
asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
|
|
|
|
|
else if (GET_CODE (X) == PLUS) \
|
|
|
|
|
{ \
|
arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and gcc_unreachable as appropriate.
* config/arm/arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and
gcc_unreachable as appropriate.
(THUMB_PRINT_OPERAND_ADDRESS): Likewise.
* config/arm/arm.c (arm_override_options, arm_compute_func_type,
use_return_insn, const_ok_for_op, arm_gen_constant,
arm_canonicalize_comparison, legitimize_pic_address,
thumb_find_work_register, arm_load_pic_register, arm_rtx_costs_1,
arm_cirrus_insn_p, cirrus_reorg, minmax_code,
load_multiple_sequence, emit_ldm_seq, store_multiple_sequence,
emit_stm_seq, arm_gen_movmemqi, arm_select_dominance_cc_mode,
arm_select_cc_mode, arm_reload_in_hi, arm_reload_out_hi,
move_minipool_fix_forward_ref, move_minipool_fix_backward_ref,
dump_minipool, create_fix_barrier, push_minipool_fix, arm_reorg,
fp_immediate_constant, fp_const_from_val, vfp_output_fstmx,
output_call, output_mov_long_double_fpa_from_arm,
output_mov_long_double_arm_from_fpa,
output_mov_double_fpa_from_arm, output_mov_double_arm_from_fpa,
output_move_double, arithmetic_instr, shift_op, int_log2,
output_return_instruction, arm_output_function_prologue,
arm_output_epilogue, arm_output_function_epilogue,
emit_multi_reg_push, arm_get_frame_offsets,
arm_compute_initial_elimination_offset, arm_expand_prologue,
arm_print_operand, arm_assemble_integer, get_arm_condition_code,
arm_final_prescan_insn, arm_init_iwmmxt_builtins,
arm_expand_binop_builtin, thumb_pushpop, thumb_far_jump_used_p,
thumb_compute_initial_elimination_offset,
thumb_output_function_prologue, thumb_load_double_from_address,
thumb_output_move_mem_multiple, thumb_reload_out_hi,
arm_emit_vector_const, arm_dbx_register_number): Likewise.
* config/arm/pe.c (arm_mark_dllexport, arm_mark_dllimport): Likewise.
* config/arm/arm.md (thumb_extendhisi2,
*thumb_extendhisi2_insn_v6, *thumb_extendqisi2,
*thumb_extendqisi2_v6, movhi, *thumb_movhi_insn,
thumb_movhi_clobber, movqi, *arm_buneq, *arm_bltgt,
*arm_buneq_reversed, *arm_bltgt_reversed, suneq, sltgt): Likewise.
* config/arm/cirrus.md (*cirrus_arm_movdi,
*cirrus_movdf_hard_insn): Likewise.
* config/arm/vfp.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
From-SVN: r98850
2005-04-27 18:09:03 +02:00
|
|
|
|
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
|
2003-06-09 13:27:37 +02:00
|
|
|
|
asm_fprintf (STREAM, "[%r, #%wd]", \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
REGNO (XEXP (X, 0)), \
|
2003-06-09 13:27:37 +02:00
|
|
|
|
INTVAL (XEXP (X, 1))); \
|
2000-04-08 16:29:53 +02:00
|
|
|
|
else \
|
|
|
|
|
asm_fprintf (STREAM, "[%r, %r]", \
|
|
|
|
|
REGNO (XEXP (X, 0)), \
|
|
|
|
|
REGNO (XEXP (X, 1))); \
|
|
|
|
|
} \
|
|
|
|
|
else \
|
|
|
|
|
output_addr_const (STREAM, X); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
|
|
|
|
|
if (TARGET_ARM) \
|
|
|
|
|
ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
|
|
|
|
|
else \
|
|
|
|
|
THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
|
|
|
|
|
#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
|
|
|
|
|
if (GET_CODE (X) != CONST_VECTOR \
|
|
|
|
|
|| ! arm_emit_vector_const (FILE, X)) \
|
|
|
|
|
goto FAIL;
|
|
|
|
|
|
1996-08-15 22:00:54 +02:00
|
|
|
|
/* A C expression whose value is RTL representing the value of the return
|
|
|
|
|
address for the frame COUNT steps up from the current frame. */
|
|
|
|
|
|
2000-04-08 16:29:53 +02:00
|
|
|
|
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
|
|
|
|
arm_return_addr (COUNT, FRAME)
|
|
|
|
|
|
2004-08-24 02:30:52 +02:00
|
|
|
|
/* Mask of the bits in the PC that contain the real return address
|
2000-04-08 16:29:53 +02:00
|
|
|
|
when running in 26-bit mode. */
|
|
|
|
|
#define RETURN_ADDR_MASK26 (0x03fffffc)
|
1996-08-15 22:00:54 +02:00
|
|
|
|
|
2000-03-23 01:29:55 +01:00
|
|
|
|
/* Pick up the return address upon entry to a procedure. Used for
|
|
|
|
|
dwarf2 unwind information. This also enables the table driven
|
|
|
|
|
mechanism. */
|
|
|
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
|
|
|
|
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
|
|
|
|
|
|
1996-07-26 19:59:49 +02:00
|
|
|
|
/* Used to mask out junk bits from the return address, such as
|
|
|
|
|
processor state, interrupt status, condition codes and the like. */
|
|
|
|
|
#define MASK_RETURN_ADDR \
|
|
|
|
|
/* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
|
|
|
|
|
in 26 bit mode, the condition codes must be masked out of the \
|
|
|
|
|
return address. This does not apply to ARM6 and later processors \
|
|
|
|
|
when running in 32 bit mode. */ \
|
arm.h (TARGET_APCS_32): Delete.
* arm.h (TARGET_APCS_32): Delete.
(TARGET_MMU_TRAPS): Delete.
(TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never
define __APCS_26__.
(CPP_SPEC): Remove checking of -mapcs-{26,32}.
(ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete.
(TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches.
(prog_mode_type): Delete.
(PROMOTE_MODE): Always promote unsigned for HImode.
(SECONDARY_INPUT_RELOAD_CLASS): Simplify.
(MASK_RETURN_ADDR): Simplify.
* arm.c (arm_prgmode): Delete.
(arm_override_options, arm_gen_rotated_half_load): Simplify.
(print_multi_reg, output_return_instruction): Simplify.
(arm_output_epilogue, arm_final_prescan_insn): Simplify.
(arm_return_addr): Simplify.
* arm.md (prog_mode): Delete.
(conds): Simplify.
(zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify.
(rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete.
(loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete.
(loadhi_shiftpredec): Delete.
(peephole for post-increment on HImode load): Delete.
* arm/crtn.asm: (FUNC_END): Simplify.
* arm/lib1funcs.asm: Remove APCS-26 return macros.
* arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h
* arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h
* arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and
MULTILIB_DEFAULTS as required.
* arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe
* arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB
variables as required.
* doc/invoke.texi (ARM Options): Remove obsolete flags.
From-SVN: r81881
2004-05-15 14:41:35 +02:00
|
|
|
|
((arm_arch4 || TARGET_THUMB) \
|
|
|
|
|
? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
|
2002-09-06 16:54:48 +02:00
|
|
|
|
: arm_gen_return_addr_mask ())
|
2000-04-08 16:29:53 +02:00
|
|
|
|
|
|
|
|
|
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
|
|
|
|
enum arm_builtins
|
|
|
|
|
{
|
|
|
|
|
ARM_BUILTIN_GETWCX,
|
|
|
|
|
ARM_BUILTIN_SETWCX,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WZERO,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WAVG2BR,
|
|
|
|
|
ARM_BUILTIN_WAVG2HR,
|
|
|
|
|
ARM_BUILTIN_WAVG2B,
|
|
|
|
|
ARM_BUILTIN_WAVG2H,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WACCB,
|
|
|
|
|
ARM_BUILTIN_WACCH,
|
|
|
|
|
ARM_BUILTIN_WACCW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WMACS,
|
|
|
|
|
ARM_BUILTIN_WMACSZ,
|
|
|
|
|
ARM_BUILTIN_WMACU,
|
|
|
|
|
ARM_BUILTIN_WMACUZ,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WSADB,
|
|
|
|
|
ARM_BUILTIN_WSADBZ,
|
|
|
|
|
ARM_BUILTIN_WSADH,
|
|
|
|
|
ARM_BUILTIN_WSADHZ,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WALIGN,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_TMIA,
|
|
|
|
|
ARM_BUILTIN_TMIAPH,
|
|
|
|
|
ARM_BUILTIN_TMIABB,
|
|
|
|
|
ARM_BUILTIN_TMIABT,
|
|
|
|
|
ARM_BUILTIN_TMIATB,
|
|
|
|
|
ARM_BUILTIN_TMIATT,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_TMOVMSKB,
|
|
|
|
|
ARM_BUILTIN_TMOVMSKH,
|
|
|
|
|
ARM_BUILTIN_TMOVMSKW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_TBCSTB,
|
|
|
|
|
ARM_BUILTIN_TBCSTH,
|
|
|
|
|
ARM_BUILTIN_TBCSTW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WMADDS,
|
|
|
|
|
ARM_BUILTIN_WMADDU,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WPACKHSS,
|
|
|
|
|
ARM_BUILTIN_WPACKWSS,
|
|
|
|
|
ARM_BUILTIN_WPACKDSS,
|
|
|
|
|
ARM_BUILTIN_WPACKHUS,
|
|
|
|
|
ARM_BUILTIN_WPACKWUS,
|
|
|
|
|
ARM_BUILTIN_WPACKDUS,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WADDB,
|
|
|
|
|
ARM_BUILTIN_WADDH,
|
|
|
|
|
ARM_BUILTIN_WADDW,
|
|
|
|
|
ARM_BUILTIN_WADDSSB,
|
|
|
|
|
ARM_BUILTIN_WADDSSH,
|
|
|
|
|
ARM_BUILTIN_WADDSSW,
|
|
|
|
|
ARM_BUILTIN_WADDUSB,
|
|
|
|
|
ARM_BUILTIN_WADDUSH,
|
|
|
|
|
ARM_BUILTIN_WADDUSW,
|
|
|
|
|
ARM_BUILTIN_WSUBB,
|
|
|
|
|
ARM_BUILTIN_WSUBH,
|
|
|
|
|
ARM_BUILTIN_WSUBW,
|
|
|
|
|
ARM_BUILTIN_WSUBSSB,
|
|
|
|
|
ARM_BUILTIN_WSUBSSH,
|
|
|
|
|
ARM_BUILTIN_WSUBSSW,
|
|
|
|
|
ARM_BUILTIN_WSUBUSB,
|
|
|
|
|
ARM_BUILTIN_WSUBUSH,
|
|
|
|
|
ARM_BUILTIN_WSUBUSW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WAND,
|
|
|
|
|
ARM_BUILTIN_WANDN,
|
|
|
|
|
ARM_BUILTIN_WOR,
|
|
|
|
|
ARM_BUILTIN_WXOR,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WCMPEQB,
|
|
|
|
|
ARM_BUILTIN_WCMPEQH,
|
|
|
|
|
ARM_BUILTIN_WCMPEQW,
|
|
|
|
|
ARM_BUILTIN_WCMPGTUB,
|
|
|
|
|
ARM_BUILTIN_WCMPGTUH,
|
|
|
|
|
ARM_BUILTIN_WCMPGTUW,
|
|
|
|
|
ARM_BUILTIN_WCMPGTSB,
|
|
|
|
|
ARM_BUILTIN_WCMPGTSH,
|
|
|
|
|
ARM_BUILTIN_WCMPGTSW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_TEXTRMSB,
|
|
|
|
|
ARM_BUILTIN_TEXTRMSH,
|
|
|
|
|
ARM_BUILTIN_TEXTRMSW,
|
|
|
|
|
ARM_BUILTIN_TEXTRMUB,
|
|
|
|
|
ARM_BUILTIN_TEXTRMUH,
|
|
|
|
|
ARM_BUILTIN_TEXTRMUW,
|
|
|
|
|
ARM_BUILTIN_TINSRB,
|
|
|
|
|
ARM_BUILTIN_TINSRH,
|
|
|
|
|
ARM_BUILTIN_TINSRW,
|
|
|
|
|
|
|
|
|
|
ARM_BUILTIN_WMAXSW,
|
|
|
|
|
ARM_BUILTIN_WMAXSH,
|
|
|
|
|
ARM_BUILTIN_WMAXSB,
|
|
|
|
|
ARM_BUILTIN_WMAXUW,
|
|
|
|
|
ARM_BUILTIN_WMAXUH,
|
|
|
|
|
ARM_BUILTIN_WMAXUB,
|
|
|
|
|
ARM_BUILTIN_WMINSW,
|
|
|
|
|
ARM_BUILTIN_WMINSH,
|
|
|
|
|
ARM_BUILTIN_WMINSB,
|
|
|
|
|
ARM_BUILTIN_WMINUW,
|
|
|
|
|
ARM_BUILTIN_WMINUH,
|
|
|
|
|
ARM_BUILTIN_WMINUB,
|
|
|
|
|
|
2004-02-13 22:49:26 +01:00
|
|
|
|
ARM_BUILTIN_WMULUM,
|
|
|
|
|
ARM_BUILTIN_WMULSM,
|
config.gcc: Add an extra_header for ARM targets.
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
From-SVN: r68157
2003-06-18 18:36:13 +02:00
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ARM_BUILTIN_WMULUL,
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ARM_BUILTIN_PSADBH,
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ARM_BUILTIN_WSHUFH,
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ARM_BUILTIN_WSLLH,
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ARM_BUILTIN_WSLLW,
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ARM_BUILTIN_WSLLD,
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ARM_BUILTIN_WSRAH,
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ARM_BUILTIN_WSRAW,
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ARM_BUILTIN_WSRAD,
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ARM_BUILTIN_WSRLH,
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ARM_BUILTIN_WSRLW,
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ARM_BUILTIN_WSRLD,
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ARM_BUILTIN_WRORH,
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ARM_BUILTIN_WRORW,
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ARM_BUILTIN_WRORD,
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ARM_BUILTIN_WSLLHI,
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ARM_BUILTIN_WSLLWI,
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ARM_BUILTIN_WSLLDI,
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ARM_BUILTIN_WSRAHI,
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ARM_BUILTIN_WSRAWI,
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ARM_BUILTIN_WSRADI,
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ARM_BUILTIN_WSRLHI,
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ARM_BUILTIN_WSRLWI,
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ARM_BUILTIN_WSRLDI,
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ARM_BUILTIN_WRORHI,
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ARM_BUILTIN_WRORWI,
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ARM_BUILTIN_WRORDI,
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ARM_BUILTIN_WUNPCKIHB,
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ARM_BUILTIN_WUNPCKIHH,
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ARM_BUILTIN_WUNPCKIHW,
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ARM_BUILTIN_WUNPCKILB,
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ARM_BUILTIN_WUNPCKILH,
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ARM_BUILTIN_WUNPCKILW,
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ARM_BUILTIN_WUNPCKEHSB,
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ARM_BUILTIN_WUNPCKEHSH,
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ARM_BUILTIN_WUNPCKEHSW,
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ARM_BUILTIN_WUNPCKEHUB,
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ARM_BUILTIN_WUNPCKEHUH,
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ARM_BUILTIN_WUNPCKEHUW,
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ARM_BUILTIN_WUNPCKELSB,
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ARM_BUILTIN_WUNPCKELSH,
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ARM_BUILTIN_WUNPCKELSW,
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ARM_BUILTIN_WUNPCKELUB,
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ARM_BUILTIN_WUNPCKELUH,
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ARM_BUILTIN_WUNPCKELUW,
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ARM_BUILTIN_MAX
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};
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2001-05-26 03:31:47 +02:00
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#endif /* ! GCC_ARM_H */
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