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qemu-e2k/target/s390x/tcg/insn-data.h.inc

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s390x: Add some documentation in opcode list I find it really hard to grasp what each field in the opcode list means. Slowly walking through its semantics myself, I figured I'd write a small summary at the top of the file to make life easier for me and whoever looks at the file next. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:06:41 +02:00
/*
* Arguments to the opcode prototypes
*
* C(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC)
* D(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC, DATA)
s390x/tcg: support flags for instructions Storing flags for instructions allows us to efficiently verify certain properties at a central point. Examples might later be handling if AFP is disabled in CR0, we are not in problem state, or if vector instructions are disabled in CR0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:58 +02:00
* E(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC, DATA, FLAGS)
* F(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC, FLAGS)
s390x: Add some documentation in opcode list I find it really hard to grasp what each field in the opcode list means. Slowly walking through its semantics myself, I figured I'd write a small summary at the top of the file to make life easier for me and whoever looks at the file next. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:06:41 +02:00
*
* OPC = (op << 8) | op2 where op is the major, op2 the minor opcode
* NAME = name of the opcode, used internally
target/s390x: Rename insn-data/format.def -> insn-data/format.h.inc We use the .h.inc extension to include C headers. To be consistent with the rest of the codebase, rename the C headers using the .def extension. IDE/tools using our .editorconfig / .gitattributes will leverage this consistency. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221025235006.7215-3-philmd@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-10-26 01:50:05 +02:00
* FMT = format of the opcode (defined in insn-format.h.inc)
s390x: Add some documentation in opcode list I find it really hard to grasp what each field in the opcode list means. Slowly walking through its semantics myself, I figured I'd write a small summary at the top of the file to make life easier for me and whoever looks at the file next. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:06:41 +02:00
* FAC = facility the opcode is available in (defined in DisasFacility)
* I1 = func in1_xx fills o->in1
* I2 = func in2_xx fills o->in2
* P = func prep_xx initializes o->*out*
* W = func wout_xx writes o->*out* somewhere
* OP = func op_xx does the bulk of the operation
* CC = func cout_xx defines how cc should get set
* DATA = immediate argument to op_xx function
s390x/tcg: support flags for instructions Storing flags for instructions allows us to efficiently verify certain properties at a central point. Examples might later be handling if AFP is disabled in CR0, we are not in problem state, or if vector instructions are disabled in CR0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:58 +02:00
* FLAGS = categorize the type of instruction (e.g. for advanced checks)
s390x: Add some documentation in opcode list I find it really hard to grasp what each field in the opcode list means. Slowly walking through its semantics myself, I figured I'd write a small summary at the top of the file to make life easier for me and whoever looks at the file next. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:06:41 +02:00
*
* The helpers get called in order: I1, I2, P, OP, W, CC
*/
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* ADD */
C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
C(0xb9f8, ARK, RRF_a, DO, r2, r3, new, r1_32, add, adds32)
C(0x5a00, A, RX_a, Z, r1, m2_32s, new, r1_32, add, adds32)
C(0xe35a, AY, RXY_a, LD, r1, m2_32s, new, r1_32, add, adds32)
C(0xb908, AGR, RRE, Z, r1, r2, r1, 0, add, adds64)
C(0xb918, AGFR, RRE, Z, r1, r2_32s, r1, 0, add, adds64)
C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31a, ADBR, RRE, Z, f1, f2, new, f1, adb, f64, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb34a, AXBR, RRE, Z, x1, x2, new_x, x1, axb, f128, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1a, ADB, RXE, Z, f1, m2_64, new, f1, adb, f64, IF_BFP)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* ADD HIGH */
C(0xb9c8, AHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, adds32)
C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* ADD IMMEDIATE */
C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32)
s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1 The semantics of ASI/ASGI/ALSI/ALSGI changed. Let's implement them just like LOAD AND ADD, so they are atomic. Emulate old behavior. This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:01:59 +01:00
D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32)
C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEUQ)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* ADD IMMEDIATE HIGH */
C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
target-s390: Convert ADD HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 23:09:45 +02:00
/* ADD HALFWORD */
C(0x4a00, AH, RX_a, Z, r1, m2_16s, new, r1_32, add, adds32)
C(0xe37a, AHY, RXY_a, LD, r1, m2_16s, new, r1_32, add, adds32)
s390x/tcg: Implement ADD HALFWORD (AGH) Easy, just like ADD HALFWORD IMMEDIATE (AGHI). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:10 +02:00
C(0xe338, AGH, RXY_a, MIE2,r1, m2_16s, r1, 0, add, adds64)
target-s390: Convert ADD HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 23:09:45 +02:00
/* ADD HALFWORD IMMEDIATE */
C(0xa70a, AHI, RI_a, Z, r1, i2, new, r1_32, add, adds32)
C(0xa70b, AGHI, RI_a, Z, r1, i2, r1, 0, add, adds64)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* ADD LOGICAL */
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
C(0x1e00, ALR, RR_a, Z, r1_32u, r2_32u, new, r1_32, add, addu32)
C(0xb9fa, ALRK, RRF_a, DO, r2_32u, r3_32u, new, r1_32, add, addu32)
C(0x5e00, AL, RX_a, Z, r1_32u, m2_32u, new, r1_32, add, addu32)
C(0xe35e, ALY, RXY_a, LD, r1_32u, m2_32u, new, r1_32, add, addu32)
C(0xb90a, ALGR, RRE, Z, r1, r2, r1, 0, addu64, addu64)
C(0xb91a, ALGFR, RRE, Z, r1, r2_32u, r1, 0, addu64, addu64)
C(0xb9ea, ALGRK, RRF_a, DO, r2, r3, r1, 0, addu64, addu64)
C(0xe30a, ALG, RXY_a, Z, r1, m2_64, r1, 0, addu64, addu64)
C(0xe31a, ALGF, RXY_a, Z, r1, m2_32u, r1, 0, addu64, addu64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* ADD LOGICAL HIGH */
C(0xb9ca, ALHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, addu32)
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
C(0xb9da, ALHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, add, addu32)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* ADD LOGICAL IMMEDIATE */
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
C(0xc20b, ALFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, add, addu32)
C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, addu64, addu64)
target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 23:42:49 +02:00
/* ADD LOGICAL WITH SIGNED IMMEDIATE */
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_TEUL)
C(0xecda, ALHSIK, RIE_d, DO, r3_32u, i2_32u, new, r1_32, add, addu32)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_TEUQ)
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, addu64, addu64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */
target/s390x: Improve cc computation for ADD LOGICAL The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:53 +01:00
C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu32)
C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, 0)
target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW I'm resonably certain that the carry/borrow-out condition for both helpers was incorrect, failing to take into account the carry-in. Adding the new CC_OP codes also allows removing the awkward interface we used for the slb helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 03:52:33 +02:00
/* ADD LOGICAL WITH CARRY */
target/s390x: Improve ADD LOGICAL WITH CARRY Now that ADD LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ADDU and produce an output carry directly from ADD LOGICAL WITH CARRY. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:54 +01:00
C(0xb998, ALCR, RRE, Z, r1_32u, r2_32u, new, r1_32, addc32, addu32)
C(0xb988, ALCGR, RRE, Z, r1, r2, r1, 0, addc64, addu64)
C(0xe398, ALC, RXY_a, Z, r1_32u, m2_32u, new, r1_32, addc32, addu32)
C(0xe388, ALCG, RXY_a, Z, r1, m2_64, r1, 0, addc64, addu64)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
/* AND */
C(0x1400, NR, RR_a, Z, r1, r2, new, r1_32, and, nz32)
C(0xb9f4, NRK, RRF_a, DO, r2, r3, new, r1_32, and, nz32)
C(0x5400, N, RX_a, Z, r1, m2_32s, new, r1_32, and, nz32)
C(0xe354, NY, RXY_a, LD, r1, m2_32s, new, r1_32, and, nz32)
C(0xb980, NGR, RRE, Z, r1, r2, r1, 0, and, nz64)
C(0xb9e4, NGRK, RRF_a, DO, r2, r3, r1, 0, and, nz64)
C(0xe380, NG, RXY_a, Z, r1, m2_64, r1, 0, and, nz64)
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
C(0xd400, NC, SS_a, Z, la1, a2, 0, 0, nc, 0)
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 00:01:36 +02:00
/* AND IMMEDIATE */
D(0xc00a, NIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2020)
D(0xc00b, NILF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2000)
D(0xa504, NIHH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1030)
D(0xa505, NIHL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1020)
D(0xa506, NILH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1010)
D(0xa507, NILL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1000)
s390x/tcg: implement Interlocked-Access Facility 2 With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:02:00 +01:00
D(0x9400, NI, SI, Z, la1, i2_8u, new, 0, ni, nz64, MO_UB)
D(0xeb54, NIY, SIY, LD, la1, i2_8u, new, 0, ni, nz64, MO_UB)
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* AND WITH COMPLEMENT */
C(0xb9f5, NCRK, RRF_a, MIE3, r2, r3, new, r1_32, andc, nz32)
C(0xb9e5, NCGRK, RRF_a, MIE3, r2, r3, r1, 0, andc, nz64)
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
target/s390x: add BAL and BALR instructions These instructions are provided for compatibility purposes and are used only by old software, in the new code BAS and BASR are preferred. The difference between the old and new instruction exists only in the 24-bit mode. In addition, fix BAS polluting high 32 bits of the first operand in 24- and 31-bit addressing modes. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-3-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-21 04:50:59 +02:00
/* BRANCH AND LINK */
C(0x0500, BALR, RR_a, Z, 0, r2_nz, r1, 0, bal, 0)
C(0x4500, BAL, RX_a, Z, 0, a2, r1, 0, bal, 0)
target-s390: Convert BRANCH AND SAVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 20:38:19 +02:00
/* BRANCH AND SAVE */
C(0x0d00, BASR, RR_a, Z, 0, r2_nz, r1, 0, bas, 0)
C(0x4d00, BAS, RX_a, Z, 0, a2, r1, 0, bas, 0)
/* BRANCH RELATIVE AND SAVE */
C(0xa705, BRAS, RI_b, Z, 0, 0, r1, 0, basi, 0)
C(0xc005, BRASL, RIL_b, Z, 0, 0, r1, 0, basi, 0)
s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC) Just like BRANCH ON CONDITION - however the address is read from memory (always 8 bytes are read), we have to wrap the address manually. The address is read using current CPU DAT/address-space controls, just like ordinary data. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:14 +02:00
/* BRANCH INDIRECT ON CONDITION */
C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0)
target-s390: Convert BRANCH ON CONDITION Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-20 17:28:02 +02:00
/* BRANCH ON CONDITION */
C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0)
C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0)
/* BRANCH RELATIVE ON CONDITION */
C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0)
C(0xc004, BRCL, RIL_c, Z, 0, 0, 0, 0, bc, 0)
target-s390: Convert BRANCH ON COUNT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-20 23:22:58 +02:00
/* BRANCH ON COUNT */
C(0x0600, BCTR, RR_a, Z, 0, r2_nz, 0, 0, bct32, 0)
C(0xb946, BCTGR, RRE, Z, 0, r2_nz, 0, 0, bct64, 0)
C(0x4600, BCT, RX_a, Z, 0, a2, 0, 0, bct32, 0)
C(0xe346, BCTG, RXY_a, Z, 0, a2, 0, 0, bct64, 0)
/* BRANCH RELATIVE ON COUNT */
C(0xa706, BRCT, RI_b, Z, 0, 0, 0, 0, bct32, 0)
C(0xa707, BRCTG, RI_b, Z, 0, 0, 0, 0, bct64, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* BRANCH RELATIVE ON COUNT HIGH */
C(0xcc06, BRCTH, RIL_b, HW, 0, 0, 0, 0, bcth, 0)
target-s390: Implement BRANCH ON INDEX Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-29 21:57:55 +02:00
/* BRANCH ON INDEX */
D(0x8600, BXH, RS_a, Z, 0, a2, 0, 0, bx32, 0, 0)
D(0x8700, BXLE, RS_a, Z, 0, a2, 0, 0, bx32, 0, 1)
D(0xeb44, BXHG, RSY_a, Z, 0, a2, 0, 0, bx64, 0, 0)
D(0xeb45, BXLEG, RSY_a, Z, 0, a2, 0, 0, bx64, 0, 1)
/* BRANCH RELATIVE ON INDEX */
D(0x8400, BRXH, RSI, Z, 0, 0, 0, 0, bx32, 0, 0)
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
target/s390x: Implement execution-hint insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 02:05:50 +02:00
/* BRANCH PREDICTION PRELOAD */
/* ??? Format is SMI, but implemented as NOP, so we need no fields. */
C(0xc700, BPP, E, EH, 0, 0, 0, 0, 0, 0)
/* BRANCH PREDICTION RELATIVE PRELOAD */
/* ??? Format is MII, but implemented as NOP, so we need no fields. */
C(0xc500, BPRP, E, EH, 0, 0, 0, 0, 0, 0)
/* NEXT INSTRUCTION ACCESS INTENT */
/* ??? Format is IE, but implemented as NOP, so we need no fields. */
C(0xb2fa, NIAI, E, EH, 0, 0, 0, 0, 0, 0)
target-s390: Convert BRANCH AND SAVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 20:38:19 +02:00
target-s390: Convert CKSM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 20:38:12 +02:00
/* CHECKSUM */
C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0)
target-s390: Implement CPSDR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-01 23:13:52 +02:00
/* COPY SIGN */
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb372, CPSDR, RRF_b, FPSSH, f3, f2, new, f1, cps, 0, IF_AFP1 | IF_AFP2 | IF_AFP3)
target-s390: Implement CPSDR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-01 23:13:52 +02:00
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE */
C(0x1900, CR, RR_a, Z, r1_o, r2_o, 0, 0, 0, cmps32)
C(0x5900, C, RX_a, Z, r1_o, m2_32s, 0, 0, 0, cmps32)
C(0xe359, CY, RXY_a, LD, r1_o, m2_32s, 0, 0, 0, cmps32)
C(0xb920, CGR, RRE, Z, r1_o, r2_o, 0, 0, 0, cmps64)
C(0xb930, CGFR, RRE, Z, r1_o, r2_32s, 0, 0, 0, cmps64)
C(0xe320, CG, RXY_a, Z, r1_o, m2_64, 0, 0, 0, cmps64)
C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb319, CDBR, RRE, Z, f1, f2, 0, 0, cdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb349, CXBR, RRE, Z, x1, x2, 0, 0, cxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed19, CDB, RXE, Z, f1, m2_64, 0, 0, cdb, 0, IF_BFP)
target/s390x: implement COMPARE AND SIGNAL These functions differ from COMPARE by generating an exception for a QNaN input. Use the non quiet version of floatXX_compare. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-10-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:08 +02:00
/* COMPARE AND SIGNAL */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb318, KDBR, RRE, Z, f1, f2, 0, 0, kdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb348, KXBR, RRE, Z, x1, x2, 0, 0, kxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed18, KDB, RXE, Z, f1, m2_64, 0, 0, kdb, 0, IF_BFP)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE IMMEDIATE */
C(0xc20d, CFI, RIL_a, EI, r1, i2, 0, 0, 0, cmps32)
C(0xc20c, CGFI, RIL_a, EI, r1, i2, 0, 0, 0, cmps64)
target-s390: Implement COMPARE RELATIVE LONG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:54:00 +02:00
/* COMPARE RELATIVE LONG */
C(0xc60d, CRL, RIL_b, GIE, r1, mri2_32s, 0, 0, 0, cmps32)
C(0xc608, CGRL, RIL_b, GIE, r1, mri2_64, 0, 0, 0, cmps64)
C(0xc60c, CGFRL, RIL_b, GIE, r1, mri2_32s, 0, 0, 0, cmps64)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE HALFWORD */
C(0x4900, CH, RX_a, Z, r1_o, m2_16s, 0, 0, 0, cmps32)
C(0xe379, CHY, RXY_a, LD, r1_o, m2_16s, 0, 0, 0, cmps32)
C(0xe334, CGH, RXY_a, GIE, r1_o, m2_16s, 0, 0, 0, cmps64)
/* COMPARE HALFWORD IMMEDIATE */
C(0xa70e, CHI, RI_a, Z, r1_o, i2, 0, 0, 0, cmps32)
C(0xa70f, CGHI, RI_a, Z, r1_o, i2, 0, 0, 0, cmps64)
C(0xe554, CHHSI, SIL, GIE, m1_16s, i2, 0, 0, 0, cmps64)
C(0xe55c, CHSI, SIL, GIE, m1_32s, i2, 0, 0, 0, cmps64)
C(0xe558, CGHSI, SIL, GIE, m1_64, i2, 0, 0, 0, cmps64)
/* COMPARE HALFWORD RELATIVE LONG */
target/s390x: Fix emulation of C(G)HRL The second operand of COMPARE HALFWORD RELATIVE LONG is a signed halfword, it does not have the same size as the first operand. Fixes: a7e836d5eb ("target-s390: Convert COMPARE, COMPARE LOGICAL") Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230310114157.3024170-2-nsg@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-10 12:41:56 +01:00
C(0xc605, CHRL, RIL_b, GIE, r1_o, mri2_16s, 0, 0, 0, cmps32)
C(0xc604, CGHRL, RIL_b, GIE, r1_o, mri2_16s, 0, 0, 0, cmps64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* COMPARE HIGH */
C(0xb9cd, CHHR, RRE, HW, r1_sr32, r2_sr32, 0, 0, 0, cmps32)
C(0xb9dd, CHLR, RRE, HW, r1_sr32, r2_o, 0, 0, 0, cmps32)
C(0xe3cd, CHF, RXY_a, HW, r1_sr32, m2_32s, 0, 0, 0, cmps32)
/* COMPARE IMMEDIATE HIGH */
C(0xcc0d, CIH, RIL_a, HW, r1_sr32, i2, 0, 0, 0, cmps32)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE LOGICAL */
C(0x1500, CLR, RR_a, Z, r1, r2, 0, 0, 0, cmpu32)
C(0x5500, CL, RX_a, Z, r1, m2_32s, 0, 0, 0, cmpu32)
C(0xe355, CLY, RXY_a, LD, r1, m2_32s, 0, 0, 0, cmpu32)
C(0xb921, CLGR, RRE, Z, r1, r2, 0, 0, 0, cmpu64)
C(0xb931, CLGFR, RRE, Z, r1, r2_32u, 0, 0, 0, cmpu64)
C(0xe321, CLG, RXY_a, Z, r1, m2_64, 0, 0, 0, cmpu64)
C(0xe331, CLGF, RXY_a, Z, r1, m2_32u, 0, 0, 0, cmpu64)
target-s390: Convert CLC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 21:54:07 +02:00
C(0xd500, CLC, SS_a, Z, la1, a2, 0, 0, clc, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* COMPARE LOGICAL HIGH */
C(0xb9cf, CLHHR, RRE, HW, r1_sr32, r2_sr32, 0, 0, 0, cmpu32)
C(0xb9df, CLHLR, RRE, HW, r1_sr32, r2_o, 0, 0, 0, cmpu32)
C(0xe3cf, CLHF, RXY_a, HW, r1_sr32, m2_32s, 0, 0, 0, cmpu32)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE LOGICAL IMMEDIATE */
C(0xc20f, CLFI, RIL_a, EI, r1, i2, 0, 0, 0, cmpu32)
C(0xc20e, CLGFI, RIL_a, EI, r1, i2_32u, 0, 0, 0, cmpu64)
C(0x9500, CLI, SI, Z, m1_8u, i2_8u, 0, 0, 0, cmpu64)
C(0xeb55, CLIY, SIY, LD, m1_8u, i2_8u, 0, 0, 0, cmpu64)
C(0xe555, CLHHSI, SIL, GIE, m1_16u, i2_16u, 0, 0, 0, cmpu64)
C(0xe55d, CLFHSI, SIL, GIE, m1_32u, i2_16u, 0, 0, 0, cmpu64)
C(0xe559, CLGHSI, SIL, GIE, m1_64, i2_16u, 0, 0, 0, cmpu64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* COMPARE LOGICAL IMMEDIATE HIGH */
C(0xcc0f, CLIH, RIL_a, HW, r1_sr32, i2, 0, 0, 0, cmpu32)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
/* COMPARE LOGICAL RELATIVE LONG */
C(0xc60f, CLRL, RIL_b, GIE, r1_o, mri2_32u, 0, 0, 0, cmpu32)
C(0xc60a, CLGRL, RIL_b, GIE, r1_o, mri2_64, 0, 0, 0, cmpu64)
C(0xc60e, CLGFRL, RIL_b, GIE, r1_o, mri2_32u, 0, 0, 0, cmpu64)
C(0xc607, CLHRL, RIL_b, GIE, r1_o, mri2_16u, 0, 0, 0, cmpu32)
C(0xc606, CLGHRL, RIL_b, GIE, r1_o, mri2_16u, 0, 0, 0, cmpu64)
target/s390x: implement COMPARE LOGICAL LONG As CLCL and CLCLE mostly differ by their operands, use a common do_clcl helper. Another difference is that CLCL is not interruptible. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-19-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:17 +02:00
/* COMPARE LOGICAL LONG */
C(0x0f00, CLCL, RR_a, Z, 0, 0, 0, 0, clcl, 0)
target-s390: Convert CLCLE, MVCLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:24:25 +02:00
/* COMPARE LOGICAL LONG EXTENDED */
C(0xa900, CLCLE, RS_a, Z, 0, a2, 0, 0, clcle, 0)
target/s390x: implement COMPARE LOGICAL LONG UNICODE For that we need to make program_interrupt available to qemu-user. Fortunately there is almost nothing to change as both kvm_enabled and CONFIG_KVM evaluate to false in that case. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-22-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:20 +02:00
/* COMPARE LOGICAL LONG UNICODE */
C(0xeb8f, CLCLU, RSY_a, E2, 0, a2, 0, 0, clclu, 0)
target-s390: Convert CLM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:59:22 +02:00
/* COMPARE LOGICAL CHARACTERS UNDER MASK */
C(0xbd00, CLM, RS_b, Z, r1_o, a2, 0, 0, clm, 0)
C(0xeb21, CLMY, RSY_b, LD, r1_o, a2, 0, 0, clm, 0)
C(0xeb20, CLMH, RSY_b, Z, r1_sr32, a2, 0, 0, clm, 0)
target-s390: Convert CLST, MVST Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:20:53 +02:00
/* COMPARE LOGICAL STRING */
C(0xb25d, CLST, RRE, Z, r1_o, r2_o, 0, 0, clst, 0)
target-s390: Convert COMPARE, COMPARE LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 00:20:51 +02:00
target-s390: Implement COMPARE AND BRANCH Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 19:53:49 +02:00
/* COMPARE AND BRANCH */
D(0xecf6, CRB, RRS, GIE, r1_32s, r2_32s, 0, 0, cj, 0, 0)
D(0xece4, CGRB, RRS, GIE, r1_o, r2_o, 0, 0, cj, 0, 0)
D(0xec76, CRJ, RIE_b, GIE, r1_32s, r2_32s, 0, 0, cj, 0, 0)
D(0xec64, CGRJ, RIE_b, GIE, r1_o, r2_o, 0, 0, cj, 0, 0)
D(0xecfe, CIB, RIS, GIE, r1_32s, i2, 0, 0, cj, 0, 0)
D(0xecfc, CGIB, RIS, GIE, r1_o, i2, 0, 0, cj, 0, 0)
D(0xec7e, CIJ, RIE_c, GIE, r1_32s, i2, 0, 0, cj, 0, 0)
D(0xec7c, CGIJ, RIE_c, GIE, r1_o, i2, 0, 0, cj, 0, 0)
/* COMPARE LOGICAL AND BRANCH */
D(0xecf7, CLRB, RRS, GIE, r1_32u, r2_32u, 0, 0, cj, 0, 1)
D(0xece5, CLGRB, RRS, GIE, r1_o, r2_o, 0, 0, cj, 0, 1)
D(0xec77, CLRJ, RIE_b, GIE, r1_32u, r2_32u, 0, 0, cj, 0, 1)
D(0xec65, CLGRJ, RIE_b, GIE, r1_o, r2_o, 0, 0, cj, 0, 1)
D(0xecff, CLIB, RIS, GIE, r1_32u, i2_8u, 0, 0, cj, 0, 1)
D(0xecfd, CLGIB, RIS, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1)
D(0xec7f, CLIJ, RIE_c, GIE, r1_32u, i2_8u, 0, 0, cj, 0, 1)
D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1)
target-s390: Convert COMPARE AND SWAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:46:55 +02:00
/* COMPARE AND SWAP */
target/s390x: Use atomic operations for COMPARE SWAP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-01 01:39:01 +01:00
D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL)
D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_TEUQ)
target-s390: Convert COMPARE AND SWAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:46:55 +02:00
/* COMPARE DOUBLE AND SWAP */
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-11-09 03:54:35 +01:00
C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0)
target/s390x: Implement CSST Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-15 21:38:10 +02:00
/* COMPARE AND SWAP AND STORE */
C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0)
target-s390: Convert COMPARE AND SWAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:46:55 +02:00
target-s390: Implement COMPARE AND TRAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-06 02:32:54 +02:00
/* COMPARE AND TRAP */
D(0xb972, CRT, RRF_c, GIE, r1_32s, r2_32s, 0, 0, ct, 0, 0)
D(0xb960, CGRT, RRF_c, GIE, r1_o, r2_o, 0, 0, ct, 0, 0)
D(0xec72, CIT, RIE_a, GIE, r1_32s, i2, 0, 0, ct, 0, 0)
D(0xec70, CGIT, RIE_a, GIE, r1_o, i2, 0, 0, ct, 0, 0)
/* COMPARE LOGICAL AND TRAP */
D(0xb973, CLRT, RRF_c, GIE, r1_32u, r2_32u, 0, 0, ct, 0, 1)
D(0xb961, CLGRT, RRF_c, GIE, r1_o, r2_o, 0, 0, ct, 0, 1)
target-s390x: implement miscellaneous-instruction-extensions facility RISBGN is the same as RISBG, but without setting the condition code. CLT and CLGT are the same as CLRT and CLGRT, but using memory for the second operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:50 +02:00
D(0xeb23, CLT, RSY_b, MIE, r1_32u, m2_32u, 0, 0, ct, 0, 1)
D(0xeb2b, CLGT, RSY_b, MIE, r1_o, m2_64, 0, 0, ct, 0, 1)
target/s390x: Fix CLFIT and CLGIT immediate size I2 is 16 bits, not 32. Found by running valgrind's none/tests/s390x/traps. Fixes: 1c2687518235 ("target-s390: Implement COMPARE AND TRAP") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20220817161529.597414-1-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-08-17 18:15:29 +02:00
D(0xec73, CLFIT, RIE_a, GIE, r1_32u, i2_16u, 0, 0, ct, 0, 1)
D(0xec71, CLGIT, RIE_a, GIE, r1_o, i2_16u, 0, 0, ct, 0, 1)
target-s390: Implement COMPARE AND TRAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-06 02:32:54 +02:00
target-s390: Convert CONVERT TO DECIMAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 23:05:11 +02:00
/* CONVERT TO DECIMAL */
C(0x4e00, CVD, RX_a, Z, r1_o, a2, 0, 0, cvd, 0)
C(0xe326, CVDY, RXY_a, LD, r1_o, a2, 0, 0, cvd, 0)
target-s390: Convert CONVERT TO FIXED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 00:17:35 +02:00
/* CONVERT TO FIXED */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb399, CFDBR, RRF_e, Z, 0, f2, new, r1_32, cfdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb39a, CFXBR, RRF_e, Z, 0, x2, new, r1_32, cfxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb3a9, CGDBR, RRF_e, Z, 0, f2, r1, 0, cgdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb3aa, CGXBR, RRF_e, Z, 0, x2, r1, 0, cgxb, 0, IF_BFP)
target-s390: Convert CONVERT FROM FIXED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 06:08:22 +02:00
/* CONVERT FROM FIXED */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_x, x1, cxgb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, new, f1, cdgb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_x, x1, cxgb, 0, IF_BFP)
target-s390: Implement CONVERT TO LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-01 19:42:54 +02:00
/* CONVERT TO LOGICAL */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2, new, r1_32, clfxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2, r1, 0, clgdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2, r1, 0, clgxb, 0, IF_BFP)
target-s390: Implement CONVERT FROM LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-01 20:08:17 +02:00
/* CONVERT FROM LOGICAL */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_x, x1, cxlgb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, new, f1, cdlgb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_x, x1, cxlgb, 0, IF_BFP)
target-s390: Convert CONVERT TO DECIMAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 23:05:11 +02:00
target/s390x: Implement CONVERT UNICODE insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 04:13:16 +02:00
/* CONVERT UTF-8 TO UTF-16 */
D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12)
/* CONVERT UTF-8 TO UTF-32 */
D(0xb9b0, CU14, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 14)
/* CONVERT UTF-16 to UTF-8 */
D(0xb2a6, CU21, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 21)
/* CONVERT UTF-16 to UTF-32 */
D(0xb9b1, CU24, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 24)
/* CONVERT UTF-32 to UTF-8 */
D(0xb9b2, CU41, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 41)
/* CONVERT UTF-32 to UTF-16 */
D(0xb9b3, CU42, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 42)
target-s390: Convert DIVIDE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-20 23:02:02 +02:00
/* DIVIDE */
C(0x1d00, DR, RR_a, Z, r1_D32, r2_32s, new_P, r1_P32, divs32, 0)
C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, 0)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31d, DDBR, RRE, Z, f1, f2, new, f1, ddb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb34d, DXBR, RRE, Z, x1, x2, new_x, x1, dxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1d, DDB, RXE, Z, f1, m2_64, new, f1, ddb, 0, IF_BFP)
target-s390: Convert DIVIDE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-20 23:02:02 +02:00
/* DIVIDE LOGICAL */
C(0xb997, DLR, RRE, Z, r1_D32, r2_32u, new_P, r1_P32, divu32, 0)
C(0xe397, DL, RXY_a, Z, r1_D32, m2_32u, new_P, r1_P32, divu32, 0)
C(0xb987, DLGR, RRE, Z, 0, r2_o, r1_P, 0, divu64, 0)
C(0xe387, DLG, RXY_a, Z, 0, m2_64, r1_P, 0, divu64, 0)
/* DIVIDE SINGLE */
C(0xb90d, DSGR, RRE, Z, r1p1, r2, r1_P, 0, divs64, 0)
C(0xb91d, DSGFR, RRE, Z, r1p1, r2_32s, r1_P, 0, divs64, 0)
C(0xe30d, DSG, RXY_a, Z, r1p1, m2_64, r1_P, 0, divs64, 0)
C(0xe31d, DSGF, RXY_a, Z, r1p1, m2_32s, r1_P, 0, divs64, 0)
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
/* EXCLUSIVE OR */
C(0x1700, XR, RR_a, Z, r1, r2, new, r1_32, xor, nz32)
C(0xb9f7, XRK, RRF_a, DO, r2, r3, new, r1_32, xor, nz32)
C(0x5700, X, RX_a, Z, r1, m2_32s, new, r1_32, xor, nz32)
C(0xe357, XY, RXY_a, LD, r1, m2_32s, new, r1_32, xor, nz32)
C(0xb982, XGR, RRE, Z, r1, r2, r1, 0, xor, nz64)
C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64)
C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64)
target-s390: Optimize XC Notice XC with same address and convert that to store of zero. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-19 22:48:46 +02:00
C(0xd700, XC, SS_a, Z, 0, 0, 0, 0, xc, 0)
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 00:01:36 +02:00
/* EXCLUSIVE OR IMMEDIATE */
D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020)
D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000)
s390x/tcg: implement Interlocked-Access Facility 2 With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:02:00 +01:00
D(0x9700, XI, SI, Z, la1, i2_8u, new, 0, xi, nz64, MO_UB)
D(0xeb57, XIY, SIY, LD, la1, i2_8u, new, 0, xi, nz64, MO_UB)
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 00:01:36 +02:00
target-s390: Convert EXECUTE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 22:48:38 +02:00
/* EXECUTE */
target/s390x: Fix EXECUTE with R1==0 The PoO specifies that when R1==0, no ORing into the insn loaded from storage takes place. Load a zero for this case. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-05-24 20:56:15 +02:00
C(0x4400, EX, RX_a, Z, 0, a2, 0, 0, ex, 0)
target-s390: Convert EXECUTE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 22:48:38 +02:00
/* EXECUTE RELATIVE LONG */
target/s390x: Fix EXECUTE with R1==0 The PoO specifies that when R1==0, no ORing into the insn loaded from storage takes place. Load a zero for this case. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-05-24 20:56:15 +02:00
C(0xc600, EXRL, RIL_b, EE, 0, ri2, 0, 0, ex, 0)
target-s390: Convert EXECUTE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 22:48:38 +02:00
target-s390: Convert EAR, SAR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 20:54:04 +02:00
/* EXTRACT ACCESS */
C(0xb24f, EAR, RRE, Z, 0, 0, new, r1_32, ear, 0)
target-s390: Implement ECAG Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-21 00:34:34 +02:00
/* EXTRACT CPU ATTRIBUTE */
C(0xeb4c, ECAG, RSY_a, GIE, 0, a2, r1, 0, ecag, 0)
s390x/tcg: implement extract-CPU-time facility It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value. As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply reuse cpu_get_host_ticks() to produce some descending value. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:02:05 +01:00
/* EXTRACT CPU TIME */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xc801, ECTG, SSF, ECT, 0, 0, 0, 0, ectg, 0, IF_IO)
target-s390: Convert EFPC, STFPC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:09:05 +02:00
/* EXTRACT FPC */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb38c, EFPC, RRE, Z, 0, 0, new, r1_32, efpc, 0, IF_BFP)
target-s390: Implement EPSW Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-06 18:48:08 +02:00
/* EXTRACT PSW */
C(0xb98d, EPSW, RRE, Z, 0, 0, 0, 0, epsw, 0)
target-s390: Convert EFPC, STFPC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:09:05 +02:00
target-s390: Convert FLOGR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 16:39:11 +02:00
/* FIND LEFTMOST ONE */
C(0xb983, FLOGR, RRE, EI, 0, r2_o, r1_P, 0, flogr, 0)
target-s390: Convert INSERT CHARACTER Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 16:12:29 +02:00
/* INSERT CHARACTER */
C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0)
C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0)
target-s390: Convert INSERT CHARACTERS UNDER MASK Change the CC handling to be more like TEST UNDER MASK, with val & mask. This lets us handle ICMH much more like ICM. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 22:13:09 +02:00
/* INSERT CHARACTERS UNDER MASK */
D(0xbf00, ICM, RS_b, Z, 0, a2, r1, 0, icm, 0, 0)
D(0xeb81, ICMY, RSY_b, LD, 0, a2, r1, 0, icm, 0, 0)
D(0xeb80, ICMH, RSY_b, Z, 0, a2, r1, 0, icm, 0, 32)
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 00:01:36 +02:00
/* INSERT IMMEDIATE */
D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020)
D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000)
D(0xa500, IIHH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1030)
D(0xa501, IIHL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1020)
D(0xa502, IILH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1010)
D(0xa503, IILL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1000)
target-s390: Convert IPM Note that the previous placement of the PM field was incorrect. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:18:21 +02:00
/* INSERT PROGRAM MASK */
C(0xb222, IPM, RRE, Z, 0, 0, r1, 0, ipm, 0)
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
/* LOAD */
C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0, 0)
D(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0, 0)
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0)
C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
target/s390x: Handle LGRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:19 +01:00
D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0)
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0, 0)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
F(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_AFP1 | IF_AFP2)
F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1)
F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1_P, movx, 0, IF_AFP1)
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
/* LOAD IMMEDIATE */
C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0, MO_ALIGN)
target/s390x: Handle LGRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:19 +01:00
D(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN)
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0, MO_ALIGN)
target-s390: Convert LOAD ADDRESS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:57:07 +02:00
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
target-s390x: implement LAY and LAEY instructions This complete the general-instructions-extension facility, enable it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: remove facility bit] Signed-off-by: Alexander Graf <agraf@suse.de>
2015-05-25 01:47:31 +02:00
/* LOAD ADDRESS EXTENDED */
C(0x5100, LAE, RX_a, Z, 0, a2, 0, r1, mov2e, 0)
C(0xe375, LAEY, RXY_a, GIE, 0, a2, 0, r1, mov2e, 0)
target-s390: Convert LOAD ADDRESS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:57:07 +02:00
/* LOAD ADDRESS RELATIVE LONG */
C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0)
s390x: Add interlocked access facility 1 instructions We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:07:53 +02:00
/* LOAD AND ADD */
target/s390x: Use atomic operations for LOAD AND OP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-02 02:28:54 +01:00
D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_TESL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TEUQ)
s390x: Add interlocked access facility 1 instructions We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:07:53 +02:00
/* LOAD AND ADD LOGICAL */
target/s390x: Use atomic operations for LOAD AND OP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-02 02:28:54 +01:00
D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_TEUL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa, addu64, MO_TEUQ)
s390x: Add interlocked access facility 1 instructions We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:07:53 +02:00
/* LOAD AND AND */
target/s390x: Use atomic operations for LOAD AND OP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-02 02:28:54 +01:00
D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_TESL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEUQ)
s390x: Add interlocked access facility 1 instructions We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:07:53 +02:00
/* LOAD AND EXCLUSIVE OR */
target/s390x: Use atomic operations for LOAD AND OP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-02 02:28:54 +01:00
D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_TESL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEUQ)
s390x: Add interlocked access facility 1 instructions We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-08 03:07:53 +02:00
/* LOAD AND OR */
target/s390x: Use atomic operations for LOAD AND OP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-02 02:28:54 +01:00
D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_TESL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEUQ)
target-s390: Convert LOAD AND TEST Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 20:03:39 +02:00
/* LOAD AND TEST */
C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32)
C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64)
C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64, 0)
target/s390x: Handle LGRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:19 +01:00
D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0)
target/s390x: Handle LRL and LGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:20 +01:00
D(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64, 0)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP)
target-s390x: implement load-and-trap facility At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:51 +02:00
/* LOAD AND TRAP */
C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
target/s390x: Implement load-and-zero-rightmost-byte insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 01:47:51 +02:00
/* LOAD AND ZERO RIGHTMOST BYTE */
s390x/tcg: Fix opcode for lzrf Fix the opcode for Load and Zero Rightmost Byte (32). Fixes: c2a5c1d718ea ("target/s390x: Implement load-and-zero-rightmost-byte insns") Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Cc: qemu-stable@nongnu.org Message-Id: <20220914105750.767697-1-borntraeger@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-14 12:57:50 +02:00
C(0xe33b, LZRF, RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)
target/s390x: Implement load-and-zero-rightmost-byte insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 01:47:51 +02:00
C(0xe32a, LZRG, RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)
/* LOAD LOGICAL AND ZERO RIGHTMOST BYTE */
C(0xe33a, LLZRGF, RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD BYTE */
C(0xb926, LBR, RRE, EI, 0, r2_8s, 0, r1_32, mov2, 0)
C(0xb906, LGBR, RRE, EI, 0, r2_8s, 0, r1, mov2, 0)
C(0xe376, LB, RXY_a, LD, 0, a2, new, r1_32, ld8s, 0)
C(0xe377, LGB, RXY_a, LD, 0, a2, r1, 0, ld8s, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* LOAD BYTE HIGH */
C(0xe3c0, LBH, RXY_a, HW, 0, a2, new, r1_32h, ld8s, 0)
target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 20:38:37 +02:00
/* LOAD COMPLEMENT */
C(0x1300, LCR, RR_a, Z, 0, r2, new, r1_32, neg, neg32)
C(0xb903, LCGR, RRE, Z, 0, r2, r1, 0, neg, neg64)
C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb313, LCDBR, RRE, Z, 0, f2, new, f1, negf64, f64, IF_BFP)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 | IF_AFP2)
s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY Use a new CC helper to calculate the CC lazily if needed. While the PoP mentions that "A 32-bit unsigned binary integer" is placed into the first operand, there is no word telling that the other 32 bits (high part) are left untouched. Maybe the other 32-bit are unpredictable. So store 64 bit for now. Bit magic courtesy of Richard. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-8-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-25 21:03:18 +01:00
/* LOAD COUNT TO BLOCK BOUNDARY */
target/s390x: Fix LCBB overwriting the top 32 bits LCBB is supposed to overwrite only the bottom 32 bits, but QEMU erroneously overwrites the entire register. Fixes: 6d9303322ed9 ("s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY") Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230526181240.1425579-2-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-26 20:12:37 +02:00
C(0xe727, LCBB, RXE, V, la2, 0, new, r1_32, lcbb, 0)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD HALFWORD */
C(0xb927, LHR, RRE, EI, 0, r2_16s, 0, r1_32, mov2, 0)
C(0xb907, LGHR, RRE, EI, 0, r2_16s, 0, r1, mov2, 0)
C(0x4800, LH, RX_a, Z, 0, a2, new, r1_32, ld16s, 0)
C(0xe378, LHY, RXY_a, LD, 0, a2, new, r1_32, ld16s, 0)
C(0xe315, LGH, RXY_a, Z, 0, a2, r1, 0, ld16s, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* LOAD HALFWORD HIGH */
C(0xe3c4, LHH, RXY_a, HW, 0, a2, new, r1_32h, ld16s, 0)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD HALFWORD IMMEDIATE */
C(0xa708, LHI, RI_a, Z, 0, i2, 0, r1_32, mov2, 0)
C(0xa709, LGHI, RI_a, Z, 0, i2, 0, r1, mov2, 0)
/* LOAD HALFWORD RELATIVE LONG */
C(0xc405, LHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16s, 0)
C(0xc404, LGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16s, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* LOAD HIGH */
target/s390x: Handle LLGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:21 +01:00
D(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0, 0)
target-s390x: implement load-and-trap facility At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:51 +02:00
/* LOAG HIGH AND TRAP */
C(0xe3c8, LFHAT, RXY_a, LAT, 0, m2_32u, r1, 0, lfhat, 0)
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
/* LOAD LOGICAL */
C(0xb916, LLGFR, RRE, Z, 0, r2_32u, 0, r1, mov2, 0)
target/s390x: Handle LLGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:21 +01:00
D(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0, 0)
target-s390x: implement load-and-trap facility At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:51 +02:00
/* LOAD LOGICAL AND TRAP */
C(0xe39d, LLGFAT, RXY_a, LAT, 0, a2, r1, 0, llgfat, 0)
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
/* LOAD LOGICAL RELATIVE LONG */
target/s390x: Handle LLGFRL from non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:21 +01:00
D(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0, MO_ALIGN)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD LOGICAL CHARACTER */
C(0xb994, LLCR, RRE, EI, 0, r2_8u, 0, r1_32, mov2, 0)
C(0xb984, LLGCR, RRE, EI, 0, r2_8u, 0, r1, mov2, 0)
C(0xe394, LLC, RXY_a, EI, 0, a2, new, r1_32, ld8u, 0)
C(0xe390, LLGC, RXY_a, Z, 0, a2, r1, 0, ld8u, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* LOAD LOGICAL CHARACTER HIGH */
C(0xe3c2, LLCH, RXY_a, HW, 0, a2, new, r1_32h, ld8u, 0)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD LOGICAL HALFWORD */
C(0xb995, LLHR, RRE, EI, 0, r2_16u, 0, r1_32, mov2, 0)
C(0xb985, LLGHR, RRE, EI, 0, r2_16u, 0, r1, mov2, 0)
C(0xe395, LLH, RXY_a, EI, 0, a2, new, r1_32, ld16u, 0)
C(0xe391, LLGH, RXY_a, Z, 0, a2, r1, 0, ld16u, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* LOAD LOGICAL HALFWORD HIGH */
C(0xe3c6, LLHH, RXY_a, HW, 0, a2, new, r1_32h, ld16u, 0)
target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 19:27:29 +02:00
/* LOAD LOGICAL HALFWORD RELATIVE LONG */
C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
target-s390: Convert LOAD LOGICAL IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 20:20:33 +02:00
/* LOAD LOGICAL IMMEDATE */
D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)
D(0xa50d, LLIHL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 32)
D(0xa50e, LLILH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 16)
D(0xa50f, LLILL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 0)
target-s390: Convert LLGT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 00:59:19 +02:00
/* LOAD LOGICAL THIRTY ONE BITS */
C(0xb917, LLGTR, RRE, Z, 0, r2_o, r1, 0, llgt, 0)
C(0xe317, LLGT, RXY_a, Z, 0, m2_32u, r1, 0, llgt, 0)
target-s390x: implement load-and-trap facility At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:51 +02:00
/* LOAD LOGICAL THIRTY ONE BITS AND TRAP */
C(0xe39c, LLGTAT, RXY_a, LAT, 0, m2_32u, r1, 0, llgtat, 0)
target-s390: Implement LDGR, LGDR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:52:08 +02:00
/* LOAD FPR FROM GR */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb3c1, LDGR, RRE, FPRGR, 0, r2_o, 0, f1, mov2, 0, IF_AFP1)
target-s390: Implement LDGR, LGDR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:52:08 +02:00
/* LOAD GR FROM FPR */
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb3cd, LGDR, RRE, FPRGR, 0, f2, 0, r1, mov2, 0, IF_AFP2)
target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 20:38:37 +02:00
/* LOAD NEGATIVE */
C(0x1100, LNR, RR_a, Z, 0, r2_32s, new, r1_32, nabs, nabs32)
C(0xb901, LNGR, RRE, Z, 0, r2, r1, 0, nabs, nabs64)
C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb311, LNDBR, RRE, Z, 0, f2, new, f1, nabsf64, f64, IF_BFP)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1_P, nabsf128, f128, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb371, LNDFR, RRE, FPSSH, 0, f2, new, f1, nabsf64, 0, IF_AFP1 | IF_AFP2)
target-s390: Implement LOAD ON CONDITION Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:55:00 +02:00
/* LOAD ON CONDITION */
C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0)
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
target/s390x: Implement load-on-condition-2 insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 01:35:34 +02:00
/* LOAD HALFWORD IMMEDIATE ON CONDITION */
C(0xec42, LOCHI, RIE_g, LOC2, r1, i2, new, r1_32, loc, 0)
C(0xec46, LOCGHI, RIE_g, LOC2, r1, i2, r1, 0, loc, 0)
C(0xec4e, LOCHHI, RIE_g, LOC2, r1_sr32, i2, new, r1_32h, loc, 0)
/* LOAD HIGH ON CONDITION */
target/s390x: Fix LOCFHR taking the wrong half of R2 LOCFHR should write top-to-top, but QEMU erroneously writes bottom-to-top. Fixes: 45aa9aa3b773 ("target/s390x: Implement load-on-condition-2 insns") Cc: qemu-stable@nongnu.org Reported-by: Mikhail Mitskevich <mitskevichmn@gmail.com> Closes: https://gitlab.com/qemu-project/qemu/-/issues/1668 Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230526181240.1425579-4-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-26 20:12:39 +02:00
C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2_sr32, new, r1_32h, loc, 0)
target/s390x: Implement load-on-condition-2 insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 01:35:34 +02:00
C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0)
target/s390x: Implement LOAD PAIR DISJOINT Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Eric Bischoff <ebischoff@nerim.net> Message-Id: <20170228120134.7921-1-ebischoff@suse.com> [rth: Combine the two via insn->data; free the address temps.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-28 13:01:34 +01:00
/* LOAD PAIR DISJOINT */
D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ)
target/s390x: implement LOAD PAIR FROM QUADWORD Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170604202034.16615-2-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-04 22:20:32 +02:00
/* LOAD PAIR FROM QUADWORD */
target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ No need to roll our own, as this is now provided by tcg. This was the last use of retxl, so remove that too. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-20 00:47:06 +02:00
C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0)
target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 20:38:37 +02:00
/* LOAD POSITIVE */
C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32)
C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64)
C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb310, LPDBR, RRE, Z, 0, f2, new, f1, absf64, f64, IF_BFP)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1_P, absf128, f128, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb370, LPDFR, RRE, FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | IF_AFP2)
target-s390: Convert LOAD REVERSED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 00:35:40 +02:00
/* LOAD REVERSED */
C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0)
C(0xb90f, LRVGR, RRE, Z, 0, r2_o, r1, 0, rev64, 0)
C(0xe31f, LRVH, RXY_a, Z, 0, m2_16u, new, r1_16, rev16, 0)
C(0xe31e, LRV, RXY_a, Z, 0, m2_32u, new, r1_32, rev32, 0)
C(0xe30f, LRVG, RXY_a, Z, 0, m2_64, r1, 0, rev64, 0)
target-s390: Convert LOAD ZERO Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:14:24 +02:00
/* LOAD ZERO */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_AFP1)
F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_AFP1)
target/s390x: Copy wout_x1 to wout_x1_P Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-21 07:18:56 +02:00
F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1_P, zero2, 0, IF_AFP1)
target-s390: Convert LOAD, LOAD LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-17 18:45:53 +02:00
target-s390: Convert LFPC, SFPC Note that we were failing to set the rounding mode in fpu_status. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 16:44:43 +02:00
/* LOAD FPC */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP)
target-s390: Implement LOAD/SET FP AND SIGNAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-11 02:23:13 +02:00
/* LOAD FPC AND SIGNAL */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb2bd, LFAS, S, IEEEE_SIM, 0, m2_32u, 0, 0, sfas, 0, IF_DFP)
target-s390x: implement LOAD FP INTEGER instructions This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test in the gcc testsuite. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:46 +02:00
/* LOAD FP INTEGER */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb347, FIXBR, RRF_e, Z, 0, x2, new_x, x1, fixb, 0, IF_BFP)
target-s390: Convert LFPC, SFPC Note that we were failing to set the rounding mode in fpu_status. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 16:44:43 +02:00
target-s390: Convert FP ADD, COMPARE, LOAD TEST/ROUND/LENGTHENED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 19:48:20 +02:00
/* LOAD LENGTHENED */
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xb305, LXDBR, RRE, Z, 0, f2, new_x, x1, lxdb, 0, IF_BFP)
F(0xb306, LXEBR, RRE, Z, 0, e2, new_x, x1, lxeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed04, LDEB, RXE, Z, 0, m2_32u, new, f1, ldeb, 0, IF_BFP)
target/s390x: Use Int128 for returning float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Remove extraneous return_low128.
2022-10-20 02:15:49 +02:00
F(0xed05, LXDB, RXE, Z, 0, m2_64, new_x, x1, lxdb, 0, IF_BFP)
F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_x, x1, lxeb, 0, IF_BFP)
s390x/tcg: Fix LDER instruction format It's RRE, not RXE. Found by running valgrind's none/tests/s390x/bfp-2. Fixes: 86b59624c4aa ("s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP") Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230511134726.469651-1-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-11 15:47:26 +02:00
F(0xb324, LDER, RRE, Z, 0, e2, new, f1, lde, 0, IF_AFP1)
s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP Nice trick to load a 32 bit value into vector element 0 (32 bit element size) from memory, zeroing out element1. The short HFP to long HFP conversion really only is a shift. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-25 21:03:17 +01:00
F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1)
target-s390: Convert FP ADD, COMPARE, LOAD TEST/ROUND/LENGTHENED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 19:48:20 +02:00
/* LOAD ROUNDED */
s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED With the floating-point extension facility, LOAD ROUNDED has a rounding mode specification and the inexact-exception control (XxC). Handle them just like e.g. LOAD FP INTEGER. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18 13:27:08 +01:00
F(0xb344, LEDBR, RRF_e, Z, 0, f2, new, e1, ledb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb345, LDXBR, RRF_e, Z, 0, x2, new, f1, ldxb, 0, IF_BFP)
F(0xb346, LEXBR, RRF_e, Z, 0, x2, new, e1, lexb, 0, IF_BFP)
target-s390: Convert FP ADD, COMPARE, LOAD TEST/ROUND/LENGTHENED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 19:48:20 +02:00
target-s390: Convert LOAD, STORE MULTIPLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:49:37 +02:00
/* LOAD MULTIPLE */
C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0)
C(0xeb98, LMY, RSY_a, LD, 0, a2, 0, 0, lm32, 0)
C(0xeb04, LMG, RSY_a, Z, 0, a2, 0, 0, lm64, 0)
/* LOAD MULTIPLE HIGH */
C(0xeb96, LMH, RSY_a, Z, 0, a2, 0, 0, lmh, 0)
target-s390: Convert LAM, STAM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 18:38:22 +02:00
/* LOAD ACCESS MULTIPLE */
C(0x9a00, LAM, RS_a, Z, 0, a2, 0, 0, lam, 0)
C(0xeb9a, LAMY, RSY_a, LD, 0, a2, 0, 0, lam, 0)
target-s390: Convert LOAD, STORE MULTIPLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:49:37 +02:00
s390x/tcg: Implement MONITOR CALL Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-18 10:51:22 +02:00
/* MONITOR CALL */
C(0xaf00, MC, SI, Z, la1, 0, 0, 0, mc, 0)
target-s390: Convert MOVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 19:22:28 +02:00
/* MOVE */
target-s390: Convert MVC The code that was in gen_op_mvc was a bit confused wrt what lengths it wanted to handle. I also disbelieve that the inline memset is worthwhile. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:43:06 +02:00
C(0xd200, MVC, SS_a, Z, la1, a2, 0, 0, mvc, 0)
target-s390: Convert MOVE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 19:22:28 +02:00
C(0xe544, MVHHI, SIL, GIE, la1, i2, 0, m1_16, mov2, 0)
C(0xe54c, MVHI, SIL, GIE, la1, i2, 0, m1_32, mov2, 0)
C(0xe548, MVGHI, SIL, GIE, la1, i2, 0, m1_64, mov2, 0)
C(0x9200, MVI, SI, Z, la1, i2, 0, m1_8, mov2, 0)
C(0xeb52, MVIY, SIY, LD, la1, i2, 0, m1_8, mov2, 0)
target/s390x: implement MOVE INVERSE Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-11-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:09 +02:00
/* MOVE INVERSE */
C(0xe800, MVCIN, SS_a, Z, la1, a2, 0, 0, mvcin, 0)
target-s390: Convert MOVE LONG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:46:49 +02:00
/* MOVE LONG */
C(0x0e00, MVCL, RR_a, Z, 0, 0, 0, 0, mvcl, 0)
target-s390: Convert CLCLE, MVCLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:24:25 +02:00
/* MOVE LONG EXTENDED */
C(0xa800, MVCLE, RS_a, Z, 0, a2, 0, 0, mvcle, 0)
target/s390x: implement MOVE LONG UNICODE Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-23-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:21 +02:00
/* MOVE LONG UNICODE */
C(0xeb8e, MVCLU, RSY_a, E2, 0, a2, 0, 0, mvclu, 0)
target/s390x: implement MOVE NUMERICS Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-12-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:10 +02:00
/* MOVE NUMERICS */
C(0xd100, MVN, SS_a, Z, la1, a2, 0, 0, mvn, 0)
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* MOVE RIGHT TO LEFT */
C(0xe50a, MVCRL, SSE, MIE3, la1, a2, 0, 0, mvcrl, 0)
target-s390: Convert MVPG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:19:44 +02:00
/* MOVE PAGE */
target/s390x: Store r1/r2 for page-translation exceptions during MVPG The PoP states: When EDAT-1 does not apply, and a program interruption due to a page-translation exception is recognized by the MOVE PAGE instruction, the contents of the R1 field of the instruction are stored in bit positions 0-3 of location 162, and the contents of the R2 field are stored in bit positions 4-7. If [...] an ASCE-type, region-first-translation, region-second-translation, region-third-translation, or segment-translation exception was recognized, the contents of location 162 are unpredictable. So we have to write r1/r2 into the lowcore on page-translation exceptions. Simply handle all exceptions inside our mvpg helper now. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-15 09:54:49 +01:00
C(0xb254, MVPG, RRE, Z, 0, 0, 0, 0, mvpg, 0)
target-s390: Convert CLST, MVST Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:20:53 +02:00
/* MOVE STRING */
s390x/tcg: MVST: Fix storing back the addresses to registers 24 and 31-bit address space handling is wrong when it comes to storing back the addresses to the register. While at it, read gprs 0 implicitly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-09-05 14:13:51 +02:00
C(0xb255, MVST, RRE, Z, 0, 0, 0, 0, mvst, 0)
target/s390x: implement mvcos instruction This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction. Allow to enable it for the qemu cpu model using qemu-system-s390x ... -cpu qemu,mvcos=on ... This allows to boot linux kernel that uses it for uacccess. We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode. We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used. user mode will always see a PRIVILEDGED exception. This patch is based on an original patch by Miroslav Benes (thanks!). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170614133819.18480-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-14 15:38:19 +02:00
/* MOVE WITH OPTIONAL SPECIFICATION */
C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0)
target/s390x: implement MOVE WITH OFFSET Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-13-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:11 +02:00
/* MOVE WITH OFFSET */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
C(0xf100, MVO, SS_a, Z, la1, a2, 0, 0, mvo, 0)
target/s390x: implement MOVE ZONES Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-14-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:12 +02:00
/* MOVE ZONES */
C(0xd300, MVZ, SS_a, Z, la1, a2, 0, 0, mvz, 0)
target-s390: Convert MOVE LONG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:46:49 +02:00
target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:17:59 +02:00
/* MULTIPLY */
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
s390x/tcg: Implement MULTIPLY (MG, MGRK) Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:12 +02:00
C(0xb9ec, MGRK, RRF_a, MIE2,r3_o, r2_o, r1_P, 0, muls128, 0)
target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:17:59 +02:00
C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
C(0xe35c, MFY, RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
s390x/tcg: Implement MULTIPLY (MG, MGRK) Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:12 +02:00
C(0xe384, MG, RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31c, MDBR, RRE, Z, f1, f2, new, f1, mdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb34c, MXBR, RRE, Z, x1, x2, new_x, x1, mxb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb30c, MDEBR, RRE, Z, f1, e2, new, f1, mdeb, 0, IF_BFP)
target/s390x: Fix MXDB and MXDBR These instructions multiply 64 bits by 64 bits, not 128 bits by 64 bits. Reported-by: Tulio Magno Quites Machado Filho <tuliom@redhat.com> Fixes: 2b91240f95fd ("target/s390x: Use Int128 for passing float128") Cc: qemu-stable@nongnu.org Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2211472 Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230601223027.795501-2-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-02 00:30:26 +02:00
F(0xb307, MXDBR, RRE, Z, f1, f2, new_x, x1, mxdb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1c, MDB, RXE, Z, f1, m2_64, new, f1, mdb, 0, IF_BFP)
F(0xed0c, MDEB, RXE, Z, f1, m2_32u, new, f1, mdeb, 0, IF_BFP)
target/s390x: Fix MXDB and MXDBR These instructions multiply 64 bits by 64 bits, not 128 bits by 64 bits. Reported-by: Tulio Magno Quites Machado Filho <tuliom@redhat.com> Fixes: 2b91240f95fd ("target/s390x: Use Int128 for passing float128") Cc: qemu-stable@nongnu.org Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2211472 Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230601223027.795501-2-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-02 00:30:26 +02:00
F(0xed07, MXDB, RXE, Z, f1, m2_64, new_x, x1, mxdb, 0, IF_BFP)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
/* MULTIPLY HALFWORD */
C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
s390x/tcg: Implement MULTIPLY HALFWORD (MGH) Just like MULTIPLY HALFWORD IMMEDIATE (MGHI), only the second operand (signed 16 bit) comes from memory. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:13 +02:00
C(0xe33c, MGH, RXY_a, MIE2,r1_o, m2_16s, r1, 0, mul, 0)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
/* MULTIPLY HALFWORD IMMEDIATE */
C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0)
C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0)
target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:17:59 +02:00
/* MULTIPLY LOGICAL */
C(0xb996, MLR, RRE, Z, r1p1_32u, r2_32u, new, r1_D32, mul, 0)
C(0xe396, ML, RXY_a, Z, r1p1_32u, m2_32u, new, r1_D32, mul, 0)
target-s390: Convert 64-bit MULTIPLY LOGICAL Use a new "retxl" member of CPUS290XState to return the "eXtra Low" part of a 128-bit value. That said, this will get used when two independent values need returning (e.g. quotient+remainder) as well. At the same time, shuffle the elements of CPUS390XState to get this new space from existing padding in the structure. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:26:59 +02:00
C(0xb986, MLGR, RRE, Z, r1p1, r2_o, r1_P, 0, mul128, 0)
C(0xe386, MLG, RXY_a, Z, r1p1, m2_64, r1_P, 0, mul128, 0)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
/* MULTIPLY SINGLE */
C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0)
s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC) We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:15 +02:00
C(0xb9fd, MSRKC, RRF_a, MIE2,r3_32s, r2_32s, new, r1_32, mul, muls32)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0)
C(0xe351, MSY, RXY_a, LD, r1_o, m2_32s, new, r1_32, mul, 0)
s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC) We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:15 +02:00
C(0xe353, MSC, RXY_a, MIE2,r1_32s, m2_32s, new, r1_32, mul, muls32)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
C(0xb90c, MSGR, RRE, Z, r1_o, r2_o, r1, 0, mul, 0)
s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC) We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:15 +02:00
C(0xb9ed, MSGRKC, RRF_a, MIE2,r3_o, r2_o, new_P, out2_r1, muls128, muls64)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
C(0xb91c, MSGFR, RRE, Z, r1_o, r2_32s, r1, 0, mul, 0)
C(0xe30c, MSG, RXY_a, Z, r1_o, m2_64, r1, 0, mul, 0)
s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC) We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:15 +02:00
C(0xe383, MSGC, RXY_a, MIE2,r1_o, m2_64, new_P, out2_r1, muls128, muls64)
target-s390: Convert MULTIPLY HALFWORD, SINGLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-26 00:10:35 +02:00
C(0xe31c, MSGF, RXY_a, Z, r1_o, m2_32s, r1, 0, mul, 0)
/* MULTIPLY SINGLE IMMEDIATE */
C(0xc201, MSFI, RIL_a, GIE, r1_o, i2, new, r1_32, mul, 0)
C(0xc200, MSGFI, RIL_a, GIE, r1_o, i2, r1, 0, mul, 0)
target-s390: Convert MULTIPLY AND ADD, SUBTRACT Use the new float*_muladd interface to softfloat. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 21:30:12 +02:00
/* MULTIPLY AND ADD */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb30e, MAEBR, RRD, Z, e1, e2, new, e1, maeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31e, MADBR, RRD, Z, f1, f2, new, f1, madb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed0e, MAEB, RXF, Z, e1, m2_32u, new, e1, maeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1e, MADB, RXF, Z, f1, m2_64, new, f1, madb, 0, IF_BFP)
target-s390: Convert MULTIPLY AND ADD, SUBTRACT Use the new float*_muladd interface to softfloat. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 21:30:12 +02:00
/* MULTIPLY AND SUBTRACT */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb30f, MSEBR, RRD, Z, e1, e2, new, e1, mseb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31f, MSDBR, RRD, Z, f1, f2, new, f1, msdb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed0f, MSEB, RXF, Z, e1, m2_32u, new, e1, mseb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1f, MSDB, RXF, Z, f1, m2_64, new, f1, msdb, 0, IF_BFP)
target-s390: Convert MULTIPLY AND ADD, SUBTRACT Use the new float*_muladd interface to softfloat. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 21:30:12 +02:00
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* NAND */
C(0xb974, NNRK, RRF_a, MIE3, r2, r3, new, r1_32, nand, nz32)
C(0xb964, NNGRK, RRF_a, MIE3, r2, r3, r1, 0, nand, nz64)
/* NOR */
C(0xb976, NORK, RRF_a, MIE3, r2, r3, new, r1_32, nor, nz32)
C(0xb966, NOGRK, RRF_a, MIE3, r2, r3, r1, 0, nor, nz64)
/* NOT EXCLUSIVE OR */
C(0xb977, NXRK, RRF_a, MIE3, r2, r3, new, r1_32, nxor, nz32)
C(0xb967, NXGRK, RRF_a, MIE3, r2, r3, r1, 0, nxor, nz64)
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
/* OR */
C(0x1600, OR, RR_a, Z, r1, r2, new, r1_32, or, nz32)
C(0xb9f6, ORK, RRF_a, DO, r2, r3, new, r1_32, or, nz32)
C(0x5600, O, RX_a, Z, r1, m2_32s, new, r1_32, or, nz32)
C(0xe356, OY, RXY_a, LD, r1, m2_32s, new, r1_32, or, nz32)
C(0xb981, OGR, RRE, Z, r1, r2, r1, 0, or, nz64)
C(0xb9e6, OGRK, RRF_a, DO, r2, r3, r1, 0, or, nz64)
C(0xe381, OG, RXY_a, Z, r1, m2_64, r1, 0, or, nz64)
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
C(0xd600, OC, SS_a, Z, la1, a2, 0, 0, oc, 0)
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 00:01:36 +02:00
/* OR IMMEDIATE */
D(0xc00c, OIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2020)
D(0xc00d, OILF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2000)
D(0xa508, OIHH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1030)
D(0xa509, OIHL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1020)
D(0xa50a, OILH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1010)
D(0xa50b, OILL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1000)
s390x/tcg: implement Interlocked-Access Facility 2 With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:02:00 +01:00
D(0x9600, OI, SI, Z, la1, i2_8u, new, 0, oi, nz64, MO_UB)
D(0xeb56, OIY, SIY, LD, la1, i2_8u, new, 0, oi, nz64, MO_UB)
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* OR WITH COMPLEMENT */
C(0xb975, OCRK, RRF_a, MIE3, r2, r3, new, r1_32, orc, nz32)
C(0xb965, OCGRK, RRF_a, MIE3, r2, r3, r1, 0, orc, nz64)
target-s390: Convert AND, OR, XOR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-02 01:28:39 +02:00
target/s390x: implement PACK Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-7-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:05 +02:00
/* PACK */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
C(0xf200, PACK, SS_a, Z, la1, a2, 0, 0, pack, 0)
target/s390x: implement PACK ASCII Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-24-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:22 +02:00
/* PACK ASCII */
C(0xe900, PKA, SS_f, E2, la1, a2, 0, 0, pka, 0)
target/s390x: implement PACK UNICODE Use a common helper with PACK ASCII as the differences are limited to the stride of the source operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-25-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:23 +02:00
/* PACK UNICODE */
C(0xe100, PKU, SS_f, E2, la1, a2, 0, 0, pku, 0)
target/s390x: implement PACK Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-7-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:05 +02:00
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* POPULATION COUNT */
C(0xb9e1, POPCNT, RRF_c, PC, 0, r2_o, r1, 0, popcnt, nz64)
target-s390: Implement PREFETCH Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 23:10:05 +02:00
/* PREFETCH */
/* Implemented as nops of course. */
C(0xe336, PFD, RXY_b, GIE, 0, 0, 0, 0, 0, 0)
C(0xc602, PFDRL, RIL_c, GIE, 0, 0, 0, 0, 0, 0)
target/s390x: Implement processor-assist insn Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 02:15:39 +02:00
/* PERFORM PROCESSOR ASSIST */
/* Implemented as nop of course. */
C(0xb2e8, PPA, RRF_c, PPA, 0, 0, 0, 0, 0, 0)
target-s390: Implement PREFETCH Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 23:10:05 +02:00
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
/* ROTATE LEFT SINGLE LOGICAL */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0xeb1d, RLL, RSY_a, Z, r3_o, sh, new, r1_32, rll32, 0)
C(0xeb1c, RLLG, RSY_a, Z, r3_o, sh, r1, 0, rll64, 0)
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
target-s390: Implement RISBG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 21:50:06 +02:00
/* ROTATE THEN INSERT SELECTED BITS */
C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64)
target-s390x: implement miscellaneous-instruction-extensions facility RISBGN is the same as RISBG, but without setting the condition code. CLT and CLGT are the same as CLRT and CLGRT, but using memory for the second operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:50 +02:00
C(0xec59, RISBGN, RIE_f, MIE, 0, r2, r1, 0, risbg, 0)
target-s390x: move a few instructions to the correct facility LY is part of the long-displacement facility. RISBHG and RISBLG are part of the high-word facility. STCMH is part of the z/Architecture. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-05-25 01:47:30 +02:00
C(0xec5d, RISBHG, RIE_f, HW, 0, r2, r1, 0, risbg, 0)
C(0xec51, RISBLG, RIE_f, HW, 0, r2, r1, 0, risbg, 0)
target-s390: Implement R[NOX]SBG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 22:54:13 +02:00
/* ROTATE_THEN <OP> SELECTED BITS */
C(0xec54, RNSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0)
C(0xec56, ROSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0)
C(0xec57, RXSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0)
target-s390: Implement RISBG Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-31 21:50:06 +02:00
target-s390: Convert SRST Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 23:27:42 +02:00
/* SEARCH STRING */
target/s390x: Tidy SRST Since we require all registers saved on input, read R0 from ENV instead of passing it manually. Recognize the specification exception when R0 contains incorrect data. Keep high bits of result registers unmodified when in 31 or 24-bit mode. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-18 20:26:38 +02:00
C(0xb25e, SRST, RRE, Z, 0, 0, 0, 0, srst, 0)
target/s390x: Implement SRSTU Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-18 20:31:24 +02:00
/* SEARCH STRING UNICODE */
C(0xb9be, SRSTU, RRE, ETF3, 0, 0, 0, 0, srstu, 0)
target-s390: Convert SRST Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 23:27:42 +02:00
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-23 23:31:14 +01:00
/* SELECT */
C(0xb9f0, SELR, RRF_a, MIE3, r3, r2, new, r1_32, loc, 0)
C(0xb9e3, SELGR, RRF_a, MIE3, r3, r2, r1, 0, loc, 0)
/* SELECT HIGH */
C(0xb9c0, SELFHR, RRF_a, MIE3, r3_sr32, r2_sr32, new, r1_32h, loc, 0)
target-s390: Convert EAR, SAR Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 20:54:04 +02:00
/* SET ACCESS */
C(0xb24e, SAR, RRE, Z, 0, r2_o, 0, 0, sar, 0)
target-s390: Implement SAM specification exception Also, these are user-mode instructions; allow their use in CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-06 18:31:37 +02:00
/* SET ADDRESSING MODE */
D(0x010c, SAM24, E, Z, 0, 0, 0, 0, sam, 0, 0)
D(0x010d, SAM31, E, Z, 0, 0, 0, 0, sam, 0, 1)
D(0x010e, SAM64, E, Z, 0, 0, 0, 0, sam, 0, 3)
target-s390: Convert LFPC, SFPC Note that we were failing to set the rounding mode in fpu_status. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 16:44:43 +02:00
/* SET FPC */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb384, SFPC, RRE, Z, 0, r1_o, 0, 0, sfpc, 0, IF_BFP)
target-s390: Implement LOAD/SET FP AND SIGNAL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-11 02:23:13 +02:00
/* SET FPC AND SIGNAL */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb385, SFASR, RRE, IEEEE_SIM, 0, r1_o, 0, 0, sfas, 0, IF_DFP)
target-s390: Implement SET ROUNDING MODE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-11 01:26:35 +02:00
/* SET BFP ROUNDING MODE */
s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18 13:27:04 +01:00
F(0xb299, SRNM, S, Z, la2, 0, 0, 0, srnm, 0, IF_BFP)
F(0xb2b8, SRNMB, S, FPE, la2, 0, 0, 0, srnmb, 0, IF_BFP)
target-s390: Implement SET ROUNDING MODE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-11 01:26:35 +02:00
/* SET DFP ROUNDING MODE */
s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18 13:27:04 +01:00
F(0xb2b9, SRNMT, S, DFPR, la2, 0, 0, 0, srnmt, 0, IF_DFP)
s390x/tcg: implement spm (SET PROGRAM MASK) Missing and is used inside Linux in the context of CPACF. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170920153016.3858-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-20 17:30:14 +02:00
/* SET PROGRAM MASK */
C(0x0400, SPM, RR_a, Z, r1, 0, 0, 0, spm, 0)
target-s390: Convert LFPC, SFPC Note that we were failing to set the rounding mode in fpu_status. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-24 16:44:43 +02:00
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
/* SHIFT LEFT SINGLE */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
D(0x8b00, SLA, RS_a, Z, r1, sh, new, r1_32, sla, 0, 31)
D(0xebdd, SLAK, RSY_a, DO, r3, sh, new, r1_32, sla, 0, 31)
D(0xeb0b, SLAG, RSY_a, Z, r3, sh, r1, 0, sla, 0, 63)
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
/* SHIFT LEFT SINGLE LOGICAL */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8900, SLL, RS_a, Z, r1_o, sh, new, r1_32, sll, 0)
C(0xebdf, SLLK, RSY_a, DO, r3_o, sh, new, r1_32, sll, 0)
C(0xeb0d, SLLG, RSY_a, Z, r3_o, sh, r1, 0, sll, 0)
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
/* SHIFT RIGHT SINGLE */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8a00, SRA, RS_a, Z, r1_32s, sh, new, r1_32, sra, s32)
C(0xebdc, SRAK, RSY_a, DO, r3_32s, sh, new, r1_32, sra, s32)
C(0xeb0a, SRAG, RSY_a, Z, r3_o, sh, r1, 0, sra, s64)
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
/* SHIFT RIGHT SINGLE LOGICAL */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8800, SRL, RS_a, Z, r1_32u, sh, new, r1_32, srl, 0)
C(0xebde, SRLK, RSY_a, DO, r3_32u, sh, new, r1_32, srl, 0)
C(0xeb0c, SRLG, RSY_a, Z, r3_o, sh, r1, 0, srl, 0)
target-s390: Convert SHIFT DOUBLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:22:23 +02:00
/* SHIFT LEFT DOUBLE */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
D(0x8f00, SLDA, RS_a, Z, r1_D32, sh, new, r1_D32, sla, 0, 63)
target-s390: Convert SHIFT DOUBLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:22:23 +02:00
/* SHIFT LEFT DOUBLE LOGICAL */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8d00, SLDL, RS_a, Z, r1_D32, sh, new, r1_D32, sll, 0)
target-s390: Convert SHIFT DOUBLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:22:23 +02:00
/* SHIFT RIGHT DOUBLE */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8e00, SRDA, RS_a, Z, r1_D32, sh, new, r1_D32, sra, s64)
target-s390: Convert SHIFT DOUBLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:22:23 +02:00
/* SHIFT RIGHT DOUBLE LOGICAL */
target/s390x: Fix shifting 32-bit values for more than 31 bits According to PoP, both 32- and 64-bit shifts use lowest 6 address bits. The current code special-cases 32-bit shifts to use only 5 bits, which is not correct. For example, shifting by 32 bits currently preserves the initial value, however, it's supposed zero it out instead. Fix by merging sh32 and sh64 and adapting CC calculation to shift values greater than 31. Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12 17:50:15 +01:00
C(0x8c00, SRDL, RS_a, Z, r1_D32, sh, new, r1_D32, srl, 0)
target-s390: Convert SHIFT, ROTATE SINGLE Note that we were missing the 32-bit SLA. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:15:19 +02:00
target-s390: Convert FP SQUARE ROOT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 23:33:03 +02:00
/* SQUARE ROOT */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb316, SQXBR, RRE, Z, 0, x2, new_x, x1, sqxb, 0, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP)
target-s390: Convert FP SQUARE ROOT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 23:33:03 +02:00
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
/* STORE */
target/s390x: Handle STRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-10-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:25 +01:00
D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
target/s390x: Handle STGRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-11-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:26 +01:00
D(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0, 0)
E(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
E(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
target/s390x: Handle STRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-10-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:25 +01:00
E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
E(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
/* STORE RELATIVE LONG */
target/s390x: Handle STRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-10-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:25 +01:00
D(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN)
target/s390x: Handle STGRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-11-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:26 +01:00
D(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0, MO_ALIGN)
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
C(0xe372, STCY, RXY_a, LD, r1_o, a2, 0, 0, st8, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* STORE CHARACTER HIGH */
C(0xe3c3, STCH, RXY_a, HW, r1_sr32, a2, 0, 0, st8, 0)
target-s390: Convert STCM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 00:11:53 +02:00
/* STORE CHARACTERS UNDER MASK */
D(0xbe00, STCM, RS_b, Z, r1_o, a2, 0, 0, stcm, 0, 0)
D(0xeb2d, STCMY, RSY_b, LD, r1_o, a2, 0, 0, stcm, 0, 0)
target-s390x: move a few instructions to the correct facility LY is part of the long-displacement facility. RISBHG and RISBLG are part of the high-word facility. STCMH is part of the z/Architecture. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-05-25 01:47:30 +02:00
D(0xeb2c, STCMH, RSY_b, Z, r1_o, a2, 0, 0, stcm, 0, 32)
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
/* STORE HALFWORD */
C(0x4000, STH, RX_a, Z, r1_o, a2, 0, 0, st16, 0)
C(0xe370, STHY, RXY_a, LD, r1_o, a2, 0, 0, st16, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* STORE HALFWORD HIGH */
C(0xe3c7, STHH, RXY_a, HW, r1_sr32, a2, 0, 0, st16, 0)
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
/* STORE HALFWORD RELATIVE LONG */
C(0xc407, STHRL, RIL_b, GIE, r1_o, ri2, 0, 0, st16, 0)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* STORE HIGH */
target/s390x: Handle STRL to non-aligned addresses Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-10-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-16 17:44:25 +01:00
D(0xe3cb, STFH, RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0, 0)
target-s390: Implement STORE ON CONDITION Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-01 18:45:20 +02:00
/* STORE ON CONDITION */
D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
target/s390x: Implement load-on-condition-2 insns Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-17 01:35:34 +02:00
/* STORE HIGH ON CONDITION */
D(0xebe1, STOCFH, RSY_b, LOC2, 0, 0, 0, 0, soc, 0, 2)
target-s390: Convert STORE REVERSED Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 00:52:55 +02:00
/* STORE REVERSED */
C(0xe33f, STRVH, RXY_a, Z, la2, r1_16u, new, m1_16, rev16, 0)
C(0xe33e, STRV, RXY_a, Z, la2, r1_32u, new, m1_32, rev32, 0)
C(0xe32f, STRVG, RXY_a, Z, la2, r1_o, new, m1_64, rev64, 0)
target-s390: Convert STORE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 01:00:08 +02:00
target/s390x: Implement STCK et al for CONFIG_USER_ONLY This is a non-privileged instruction that was only implemented for system mode. However, the stck instruction is used by glibc, so this was causing SIGILL for programs run under debian stretch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190212053044.29015-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-12 06:30:44 +01:00
/* STORE CLOCK */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb205, STCK, S, Z, la2, 0, new, m1_64, stck, 0, IF_IO)
F(0xb27c, STCKF, S, SCF, la2, 0, new, m1_64, stck, 0, IF_IO)
target/s390x: Implement STCK et al for CONFIG_USER_ONLY This is a non-privileged instruction that was only implemented for system mode. However, the stck instruction is used by glibc, so this was causing SIGILL for programs run under debian stretch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190212053044.29015-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-12 06:30:44 +01:00
/* STORE CLOCK EXTENDED */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb278, STCKE, S, Z, 0, a2, 0, 0, stcke, 0, IF_IO)
target/s390x: Implement STCK et al for CONFIG_USER_ONLY This is a non-privileged instruction that was only implemented for system mode. However, the stck instruction is used by glibc, so this was causing SIGILL for programs run under debian stretch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190212053044.29015-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-12 06:30:44 +01:00
target/s390x: Implement STORE FACILITIES LIST EXTENDED At the same time, improve STORE FACILITIES LIST so that we don't hard-code the list for all cpus. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-03-25 23:10:06 +01:00
/* STORE FACILITY LIST EXTENDED */
C(0xb2b0, STFLE, S, SFLE, 0, a2, 0, 0, stfle, 0)
target-s390: Convert EFPC, STFPC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:09:05 +02:00
/* STORE FPC */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb29c, STFPC, S, Z, 0, a2, new, m2_32, efpc, 0, IF_BFP)
target-s390: Convert EFPC, STFPC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:09:05 +02:00
target-s390: Convert LOAD, STORE MULTIPLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:49:37 +02:00
/* STORE MULTIPLE */
D(0x9000, STM, RS_a, Z, 0, a2, 0, 0, stm, 0, 4)
D(0xeb90, STMY, RSY_a, LD, 0, a2, 0, 0, stm, 0, 4)
D(0xeb24, STMG, RSY_a, Z, 0, a2, 0, 0, stm, 0, 8)
/* STORE MULTIPLE HIGH */
C(0xeb26, STMH, RSY_a, Z, 0, a2, 0, 0, stmh, 0)
target-s390: Convert LAM, STAM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 18:38:22 +02:00
/* STORE ACCESS MULTIPLE */
C(0x9b00, STAM, RS_a, Z, 0, a2, 0, 0, stam, 0)
C(0xeb9b, STAMY, RSY_a, LD, 0, a2, 0, 0, stam, 0)
target/s390x: implement STORE PAIR TO QUADWORD Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170604202034.16615-3-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-04 22:20:33 +02:00
/* STORE PAIR TO QUADWORD */
C(0xe38e, STPQ, RXY_a, Z, 0, a2, r1_P, 0, stpq, 0)
target-s390: Convert LOAD, STORE MULTIPLE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 18:49:37 +02:00
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* SUBTRACT */
C(0x1b00, SR, RR_a, Z, r1, r2, new, r1_32, sub, subs32)
C(0xb9f9, SRK, RRF_a, DO, r2, r3, new, r1_32, sub, subs32)
C(0x5b00, S, RX_a, Z, r1, m2_32s, new, r1_32, sub, subs32)
C(0xe35b, SY, RXY_a, LD, r1, m2_32s, new, r1_32, sub, subs32)
C(0xb909, SGR, RRE, Z, r1, r2, r1, 0, sub, subs64)
C(0xb919, SGFR, RRE, Z, r1, r2_32s, r1, 0, sub, subs64)
C(0xb9e9, SGRK, RRF_a, DO, r2, r3, r1, 0, sub, subs64)
C(0xe309, SG, RXY_a, Z, r1, m2_64, r1, 0, sub, subs64)
C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xb31b, SDBR, RRE, Z, f1, f2, new, f1, sdb, f64, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xb34b, SXBR, RRE, Z, x1, x2, new_x, x1, sxb, f128, IF_BFP)
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed1b, SDB, RXE, Z, f1, m2_64, new, f1, sdb, f64, IF_BFP)
target-s390: Implement SUBTRACT HALFWORD Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 23:46:42 +02:00
/* SUBTRACT HALFWORD */
C(0x4b00, SH, RX_a, Z, r1, m2_16s, new, r1_32, sub, subs32)
C(0xe37b, SHY, RXY_a, LD, r1, m2_16s, new, r1_32, sub, subs32)
s390x/tcg: Implement SUBTRACT HALFWORD (SGH) Easy to wire up. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:11 +02:00
C(0xe339, SGH, RXY_a, MIE2,r1, m2_16s, r1, 0, sub, subs64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* SUBTRACT HIGH */
C(0xb9c9, SHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, sub, subs32)
C(0xb9d9, SHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, sub, subs32)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* SUBTRACT LOGICAL */
target/s390x: Improve cc computation for SUBTRACT LOGICAL The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-4-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:55 +01:00
C(0x1f00, SLR, RR_a, Z, r1_32u, r2_32u, new, r1_32, sub, subu32)
C(0xb9fb, SLRK, RRF_a, DO, r2_32u, r3_32u, new, r1_32, sub, subu32)
C(0x5f00, SL, RX_a, Z, r1_32u, m2_32u, new, r1_32, sub, subu32)
C(0xe35f, SLY, RXY_a, LD, r1_32u, m2_32u, new, r1_32, sub, subu32)
C(0xb90b, SLGR, RRE, Z, r1, r2, r1, 0, subu64, subu64)
C(0xb91b, SLGFR, RRE, Z, r1, r2_32u, r1, 0, subu64, subu64)
C(0xb9eb, SLGRK, RRF_a, DO, r2, r3, r1, 0, subu64, subu64)
C(0xe30b, SLG, RXY_a, Z, r1, m2_64, r1, 0, subu64, subu64)
C(0xe31b, SLGF, RXY_a, Z, r1, m2_32u, r1, 0, subu64, subu64)
target-s390x: implement high-word facility Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:52 +02:00
/* SUBTRACT LOCICAL HIGH */
C(0xb9cb, SLHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, sub, subu32)
target/s390x: Improve cc computation for SUBTRACT LOGICAL The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-4-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:55 +01:00
C(0xb9db, SLHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, sub, subu32)
target-s390: Add format based disassassmbly infrastructure Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-16 02:16:22 +02:00
/* SUBTRACT LOGICAL IMMEDIATE */
target/s390x: Improve cc computation for SUBTRACT LOGICAL The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-4-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:55 +01:00
C(0xc205, SLFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, sub, subu32)
C(0xc204, SLGFI, RIL_a, EI, r1, i2_32u, r1, 0, subu64, subu64)
target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW I'm resonably certain that the carry/borrow-out condition for both helpers was incorrect, failing to take into account the carry-in. Adding the new CC_OP codes also allows removing the awkward interface we used for the slb helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-18 03:52:33 +02:00
/* SUBTRACT LOGICAL WITH BORROW */
target/s390x: Improve SUB LOGICAL WITH BORROW Now that SUB LOGICAL outputs borrow, we can use that as input directly. It also means we can re-use CC_OP_SUBU and produce an output borrow directly from SUB LOGICAL WITH BORROW. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-5-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-12-14 23:13:56 +01:00
C(0xb999, SLBR, RRE, Z, r1_32u, r2_32u, new, r1_32, subb32, subu32)
C(0xb989, SLBGR, RRE, Z, r1, r2, r1, 0, subb64, subu64)
C(0xe399, SLB, RXY_a, Z, r1_32u, m2_32u, new, r1_32, subb32, subu32)
C(0xe389, SLBG, RXY_a, Z, r1, m2_64, r1, 0, subb64, subu64)
target-s390: Convert TEST UNDER MASK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:20:58 +02:00
target-s390: Convert SUPERVISOR CALL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:41:05 +02:00
/* SUPERVISOR CALL */
C(0x0a00, SVC, I, Z, 0, 0, 0, 0, svc, 0)
target/s390x: implement TEST ADDRESSING MODE Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-6-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:04 +02:00
/* TEST ADDRESSING MODE */
C(0x010b, TAM, E, Z, 0, 0, 0, 0, tam, 0)
target/s390x: implement TEST AND SET Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-5-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:03 +02:00
/* TEST AND SET */
C(0x9300, TS, S, Z, 0, a2, 0, 0, ts, 0)
target-s390: Convert TEST DATA CLASS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 21:40:09 +02:00
/* TEST DATA CLASS */
s390x/tcg: add instruction flags for floating point instructions These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:02:59 +02:00
F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP)
s390x/tcg: Don't model FP registers as globals As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04 16:44:06 +01:00
F(0xed11, TCDB, RXE, Z, f1, a2, 0, 0, tcdb, 0, IF_BFP)
target/s390x: Use Int128 for passing float128 Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Fix SPEC_in1_x1.
2022-10-21 05:05:45 +02:00
F(0xed12, TCXB, RXE, Z, x1, a2, 0, 0, tcxb, 0, IF_BFP)
target-s390: Convert TEST DATA CLASS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 21:40:09 +02:00
target/s390x: implement TEST DECIMAL Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-28-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:26 +02:00
/* TEST DECIMAL */
C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0)
target-s390: Convert TEST UNDER MASK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:20:58 +02:00
/* TEST UNDER MASK */
C(0x9100, TM, SI, Z, m1_8u, i2_8u, 0, 0, 0, tm32)
C(0xeb51, TMY, SIY, LD, m1_8u, i2_8u, 0, 0, 0, tm32)
D(0xa702, TMHH, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 48)
D(0xa703, TMHL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 32)
D(0xa700, TMLH, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 16)
D(0xa701, TMLL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 0)
target-s390: Convert SET ADDRESSING MODE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:28:56 +02:00
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
/* TRANSLATE */
C(0xdc00, TR, SS_a, Z, la1, a2, 0, 0, tr, 0)
target-s390x: implement TRANSLATE AND TEST instruction It is part of the basic zArchitecture instructions. Allow it to be call from EXECUTE. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:47 +02:00
/* TRANSLATE AND TEST */
C(0xdd00, TRT, SS_a, Z, la1, a2, 0, 0, trt, 0)
target/s390x: Implement TRTR Drop TRT from the set of insns handled internally by EXECUTE. It's more important to adjust the existing helper to handle both TRT and TRTR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-18 20:45:47 +02:00
/* TRANSLATE AND TEST REVERSE */
C(0xd000, TRTR, SS_a, ETF3, la1, a2, 0, 0, trtr, 0)
target-s390x: implement TRANSLATE EXTENDED instruction It is part of the basic zArchitecture instructions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-03 23:09:48 +02:00
/* TRANSLATE EXTENDED */
C(0xb2a5, TRE, RRE, Z, 0, r2, r1_P, 0, tre, 0)
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
target/s390x: implement TRANSLATE ONE/TWO TO ONE/TWO Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-29-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:27 +02:00
/* TRANSLATE ONE TO ONE */
C(0xb993, TROO, RRF_c, E2, 0, 0, 0, 0, trXX, 0)
/* TRANSLATE ONE TO TWO */
C(0xb992, TROT, RRF_c, E2, 0, 0, 0, 0, trXX, 0)
/* TRANSLATE TWO TO ONE */
C(0xb991, TRTO, RRF_c, E2, 0, 0, 0, 0, trXX, 0)
/* TRANSLATE TWO TO TWO */
C(0xb990, TRTT, RRF_c, E2, 0, 0, 0, 0, trXX, 0)
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
/* UNPACK */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
C(0xf300, UNPK, SS_a, Z, la1, a2, 0, 0, unpk, 0)
target/s390x: implement UNPACK ASCII Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-26-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:24 +02:00
/* UNPACK ASCII */
C(0xea00, UNPKA, SS_a, E2, la1, a2, 0, 0, unpka, 0)
target/s390x: implement UNPACK UNICODE Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-27-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-01 00:01:25 +02:00
/* UNPACK UNICODE */
C(0xe200, UNPKU, SS_a, E2, la1, a2, 0, 0, unpku, 0)
target-s390: Convert NC, XC, OC, TR, UNPK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:54:19 +02:00
s390x/tcg: add basic MSA features The STFLE bits for the MSA (extension) facilities simply indicate that the respective instructions can be executed. The QUERY subfunction can then be used to identify which features exactly are available. Availability of subfunctions can also vary on real hardware. For now, we simply implement a CPU model without any available subfunctions except QUERY (which is always around). As all MSA functions behave quite similarly, we can use one translation handler for now. Prepare the code for implementation of actual subfunctions. At least MSA is helpful for now, as older Linux kernels require this facility when compiled for a z9 model. Allow to enable the facilities for the qemu cpu model. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170920153016.3858-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-20 17:30:16 +02:00
/* MSA Instructions */
D(0xb91e, KMAC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMAC)
D(0xb928, PCKMO, RRE, MSA3, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_PCKMO)
D(0xb92a, KMF, RRE, MSA4, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMF)
D(0xb92b, KMO, RRE, MSA4, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMO)
D(0xb92c, PCC, RRE, MSA4, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_PCC)
D(0xb92d, KMCTR, RRF_b, MSA4, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMCTR)
D(0xb92e, KM, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KM)
D(0xb92f, KMC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMC)
s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA) As with the other crypto functions, we only implement subcode 0 (query) and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-09-28 14:27:17 +02:00
D(0xb929, KMA, RRF_b, MSA8, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMA)
s390x/tcg: add basic MSA features The STFLE bits for the MSA (extension) facilities simply indicate that the respective instructions can be executed. The QUERY subfunction can then be used to identify which features exactly are available. Availability of subfunctions can also vary on real hardware. For now, we simply implement a CPU model without any available subfunctions except QUERY (which is always around). As all MSA functions behave quite similarly, we can use one translation handler for now. Prepare the code for implementation of actual subfunctions. At least MSA is helpful for now, as older Linux kernels require this facility when compiled for a z9 model. Allow to enable the facilities for the qemu cpu model. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170920153016.3858-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-20 17:30:16 +02:00
D(0xb93c, PPNO, RRE, MSA5, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_PPNO)
D(0xb93e, KIMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)
D(0xb93f, KLMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)
s390x/tcg: Implement VECTOR GATHER ELEMENT Let's start with a more involved one, but it is the first in the list of vector support instructions (introduced with the vector facility). Good thing is, we need a lot of basic infrastructure for this. Reading and writing vector elements as well as checking element validity. All vector instruction related translation functions will reside in translate_vx.inc.c, to be included in translate.c - similar to how other architectures handle it. While at it, directly add some documentation (which contains parts about things added in follow-up patches, but splitting this up does not make too much sense). Also add ES_* defines heavily used later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:11 +01:00
/* === Vector Support Instructions === */
s390x/tcg: Implement VECTOR BIT PERMUTE Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:22 +02:00
/* VECTOR BIT PERMUTE */
E(0xe785, VBPERM, VRR_c, VE, 0, 0, 0, 0, vbperm, 0, 0, IF_VEC)
s390x/tcg: Implement VECTOR GATHER ELEMENT Let's start with a more involved one, but it is the first in the list of vector support instructions (introduced with the vector facility). Good thing is, we need a lot of basic infrastructure for this. Reading and writing vector elements as well as checking element validity. All vector instruction related translation functions will reside in translate_vx.inc.c, to be included in translate.c - similar to how other architectures handle it. While at it, directly add some documentation (which contains parts about things added in follow-up patches, but splitting this up does not make too much sense). Also add ES_* defines heavily used later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:11 +01:00
/* VECTOR GATHER ELEMENT */
E(0xe713, VGEF, VRV, V, la2, 0, 0, 0, vge, 0, ES_32, IF_VEC)
E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)
s390x/tcg: Implement VECTOR GENERATE BYTE MASK Let's optimize it for the common cases (setting a vector to zero or all ones) - courtesy of Richard. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:12 +01:00
/* VECTOR GENERATE BYTE MASK */
F(0xe744, VGBM, VRI_a, V, 0, 0, 0, 0, vgbm, 0, IF_VEC)
s390x/tcg: Implement VECTOR GENERATE MASK Add gen_gvec_dupi() for handling duplication of immediates, so it can be reused later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:13 +01:00
/* VECTOR GENERATE MASK */
F(0xe746, VGM, VRI_b, V, 0, 0, 0, 0, vgm, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD When loading from memory, load both elements into temps first before modifying the target vector Loading with strange alingment from the end of the address space will not properly wrap, we can ignore that for now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:14 +01:00
/* VECTOR LOAD */
F(0xe706, VL, VRX, V, la2, 0, 0, 0, vl, 0, IF_VEC)
F(0xe756, VLR, VRR_a, V, 0, 0, 0, 0, vlr, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD AND REPLICATE We can use tcg_gen_gvec_dup_i64() to carry out the duplication. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:15 +01:00
/* VECTOR LOAD AND REPLICATE */
F(0xe705, VLREP, VRX, V, la2, 0, 0, 0, vlrep, 0, IF_VEC)
target/s390x: vxeh2: vector {load, store} byte reversed element Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-12-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:06 +02:00
/* VECTOR LOAD BYTE REVERSED ELEMENT */
E(0xe601, VLEBRH, VRX, VE2, la2, 0, 0, 0, vlebr, 0, ES_16, IF_VEC)
E(0xe603, VLEBRF, VRX, VE2, la2, 0, 0, 0, vlebr, 0, ES_32, IF_VEC)
E(0xe602, VLEBRG, VRX, VE2, la2, 0, 0, 0, vlebr, 0, ES_64, IF_VEC)
/* VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE */
F(0xe605, VLBRREP, VRX, VE2, la2, 0, 0, 0, vlbrrep, 0, IF_VEC)
/* VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO */
F(0xe604, VLLEBRZ, VRX, VE2, la2, 0, 0, 0, vllebrz, 0, IF_VEC)
target/s390x: vxeh2: vector {load, store} byte reversed elements Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-11-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:05 +02:00
/* VECTOR LOAD BYTE REVERSED ELEMENTS */
F(0xe606, VLBR, VRX, VE2, la2, 0, 0, 0, vlbr, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD ELEMENT Fairly easy, load with desired size and store it into the right element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:16 +01:00
/* VECTOR LOAD ELEMENT */
E(0xe700, VLEB, VRX, V, la2, 0, 0, 0, vle, 0, ES_8, IF_VEC)
E(0xe701, VLEH, VRX, V, la2, 0, 0, 0, vle, 0, ES_16, IF_VEC)
E(0xe703, VLEF, VRX, V, la2, 0, 0, 0, vle, 0, ES_32, IF_VEC)
E(0xe702, VLEG, VRX, V, la2, 0, 0, 0, vle, 0, ES_64, IF_VEC)
s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE Take care of properly sign-extending the immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:17 +01:00
/* VECTOR LOAD ELEMENT IMMEDIATE */
E(0xe740, VLEIB, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_8, IF_VEC)
E(0xe741, VLEIH, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_16, IF_VEC)
E(0xe743, VLEIF, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_32, IF_VEC)
E(0xe742, VLEIG, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)
target/s390x: vxeh2: vector {load, store} elements reversed Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-10-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:04 +02:00
/* VECTOR LOAD ELEMENTS REVERSED */
F(0xe607, VLER, VRX, VE2, la2, 0, 0, 0, vler, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT To avoid an helper, we have to do the actual calculation of the element address (offset in cpu_env + cpu_env) manually. Factor that out into get_vec_element_ptr_i64(). The same logic will be reused for "VECTOR LOAD VR ELEMENT FROM GR". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:18 +01:00
/* VECTOR LOAD GR FROM VR ELEMENT */
F(0xe721, VLGV, VRS_c, V, la2, 0, r1, 0, vlgv, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO Fairly easy, zero out the vector before we load the desired element. Load the element before touching the vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:19 +01:00
/* VECTOR LOAD LOGICAL ELEMENT AND ZERO */
F(0xe704, VLLEZ, VRX, V, la2, 0, 0, 0, vllez, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD MULTIPLE Try to load the last element first. Access to the first element will be checked afterwards. This way, we can guarantee that the vector is not modified before we checked for all possible exceptions. (16 vectors cannot cross more than two pages) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:20 +01:00
/* VECTOR LOAD MULTIPLE */
F(0xe736, VLM, VRS_a, V, la2, 0, 0, 0, vlm, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY Very similar to LOAD COUNT TO BLOCK BOUNDARY, but instead of only calculating, the actual vector is loaded. Use a temporary vector to not modify the real vector on exceptions. Initialize that one to zero, to not leak any data. Provide a fast path if we're loading a full vector. As we don't have gvec ool handlers for single vectors, just calculate the vector address manually. We can reuse the helper later on for VECTOR LOAD WITH LENGTH. In fact, we are going to name it "vll" right from the beginning, because that's a better match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:21 +01:00
/* VECTOR LOAD TO BLOCK BOUNDARY */
F(0xe707, VLBB, VRX, V, la2, 0, 0, 0, vlbb, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR Very similar to VECTOR LOAD GR FROM VR ELEMENT, just the opposite direction. Also provide a fast path in case we don't care about the register content. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:22 +01:00
/* VECTOR LOAD VR ELEMENT FROM GR */
F(0xe722, VLVG, VRS_b, V, la2, r3, 0, 0, vlvg, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT Fairly easy, just load from to gprs into a single vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:23 +01:00
/* VECTOR LOAD VR FROM GRS DISJOINT */
F(0xe762, VLVGP, VRR_f, V, r2, r3, 0, 0, vlvgp, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD WITH LENGTH We can reuse the helper introduced along with VECTOR LOAD TO BLOCK BOUNDARY. We just have to take care of converting the highest index into a length. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:24 +01:00
/* VECTOR LOAD WITH LENGTH */
F(0xe737, VLL, VRS_b, V, la2, r3_32u, 0, 0, vll, 0, IF_VEC)
s390x/tcg: Implement VECTOR MERGE (HIGH|LOW) We cannot use gvec expansion as source and destination elements are have different element numbers. So we'll expand using a fancy loop. Also, we have to take care of overlapping source and destination registers, therefore use a safe evaluation irder depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:25 +01:00
/* VECTOR MERGE HIGH */
F(0xe761, VMRH, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
/* VECTOR MERGE LOW */
F(0xe760, VMRL, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
s390x/tcg: Implement VECTOR PACK * This is a big one. Luckily we only have a limited set of such nasty instructions. We'll implement all variants with helpers, except when sources and the destination don't overlap for VECTOR PACK. Provide different helpers when the cc is to be modified. We'll return the cc then via env->cc_op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:26 +01:00
/* VECTOR PACK */
F(0xe794, VPK, VRR_c, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
/* VECTOR PACK SATURATE */
F(0xe797, VPKS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
/* VECTOR PACK LOGICAL SATURATE */
F(0xe795, VPKLS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
s390x/tcg: Implement VECTOR PERMUTE Take care of overlying inputs and outputs by using a temporary vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:27 +01:00
F(0xe78c, VPERM, VRR_e, V, 0, 0, 0, 0, vperm, 0, IF_VEC)
s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE Read the whole input before modifying the destination vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:28 +01:00
/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */
F(0xe784, VPDI, VRR_c, V, 0, 0, 0, 0, vpdi, 0, IF_VEC)
s390x/tcg: Implement VECTOR REPLICATE Replicate via the special gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:29 +01:00
/* VECTOR REPLICATE */
F(0xe74d, VREP, VRI_c, V, 0, 0, 0, 0, vrep, 0, IF_VEC)
s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE Like VECTOR REPLICATE, but the element to be replicated comes from an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:30 +01:00
/* VECTOR REPLICATE IMMEDIATE */
F(0xe745, VREPI, VRI_a, V, 0, 0, 0, 0, vrepi, 0, IF_VEC)
s390x/tcg: Implement VECTOR SCATTER ELEMENT Similar to VECTOR GATHER ELEMENT, but the other direction. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-25-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:31 +01:00
/* VECTOR SCATTER ELEMENT */
E(0xe71b, VSCEF, VRV, V, la2, 0, 0, 0, vsce, 0, ES_32, IF_VEC)
E(0xe71a, VSCEG, VRV, V, la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC)
s390x/tcg: Implement VECTOR SELECT Provide an implementation based on i64 and on real host vectors. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-26-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:32 +01:00
/* VECTOR SELECT */
F(0xe78d, VSEL, VRR_e, V, 0, 0, 0, 0, vsel, 0, IF_VEC)
s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD Load both elements signed and store them into the two 64 bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-27-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:33 +01:00
/* VECTOR SIGN EXTEND TO DOUBLEWORD */
F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC)
s390x/tcg: Implement VECTOR STORE Properly probe the whole access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-29-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:35 +01:00
/* VECTOR STORE */
F(0xe70e, VST, VRX, V, la2, 0, 0, 0, vst, 0, IF_VEC)
target/s390x: vxeh2: vector {load, store} byte reversed element Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-12-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:06 +02:00
/* VECTOR STORE BYTE REVERSED ELEMENT */
E(0xe609, VSTEBRH, VRX, VE2, la2, 0, 0, 0, vstebr, 0, ES_16, IF_VEC)
E(0xe60b, VSTEBRF, VRX, VE2, la2, 0, 0, 0, vstebr, 0, ES_32, IF_VEC)
E(0xe60a, VSTEBRG, VRX, VE2, la2, 0, 0, 0, vstebr, 0, ES_64, IF_VEC)
target/s390x: vxeh2: vector {load, store} byte reversed elements Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-11-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:05 +02:00
/* VECTOR STORE BYTE REVERSED ELEMENTS */
F(0xe60e, VSTBR, VRX, VE2, la2, 0, 0, 0, vstbr, 0, IF_VEC)
s390x/tcg: Implement VECTOR STORE ELEMENT As we only store one element, there is nothing to consider regarding exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-30-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:36 +01:00
/* VECTOR STORE ELEMENT */
E(0xe708, VSTEB, VRX, V, la2, 0, 0, 0, vste, 0, ES_8, IF_VEC)
E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)
E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)
E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)
target/s390x: vxeh2: vector {load, store} elements reversed Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-10-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:04 +02:00
/* VECTOR STORE ELEMENTS REVERSED */
F(0xe60f, VSTER, VRX, VE2, la2, 0, 0, 0, vster, 0, IF_VEC)
s390x/tcg: Implement VECTOR STORE MULTIPLE Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe write access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-31-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:37 +01:00
/* VECTOR STORE MULTIPLE */
F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC)
s390x/tcg: Implement VECTOR STORE WITH LENGTH Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction. Properly probe write access before modifying memory. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-32-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:38 +01:00
/* VECTOR STORE WITH LENGTH */
F(0xe73f, VSTL, VRS_b, V, la2, r3_32u, 0, 0, vstl, 0, IF_VEC)
s390x/tcg: Implement VECTOR UNPACK * Combine all variant in a single handler. As source and destination have different element sizes, we can't use gvec expansion. Expand manually. Also watch out for overlapping source and destination registers. Use a safe evaluation order depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-33-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:39 +01:00
/* VECTOR UNPACK HIGH */
F(0xe7d7, VUPH, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
/* VECTOR UNPACK LOGICAL HIGH */
F(0xe7d5, VUPLH, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
/* VECTOR UNPACK LOW */
F(0xe7d6, VUPL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
/* VECTOR UNPACK LOGICAL LOW */
F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
s390x/tcg: Implement VECTOR GATHER ELEMENT Let's start with a more involved one, but it is the first in the list of vector support instructions (introduced with the vector facility). Good thing is, we need a lot of basic infrastructure for this. Reading and writing vector elements as well as checking element validity. All vector instruction related translation functions will reside in translate_vx.inc.c, to be included in translate.c - similar to how other architectures handle it. While at it, directly add some documentation (which contains parts about things added in follow-up patches, but splitting this up does not make too much sense). Also add ES_* defines heavily used later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-07 13:15:11 +01:00
s390x/tcg: Implement VECTOR ADD Introduce two types of fancy new helpers that will be reused a couple of times 1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3 parameters, simplifying parameter passing 2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations using two 64 bit values per vector. Luckily, for VECTOR ADD we already have everything we need. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 23:08:40 +02:00
/* === Vector Integer Instructions === */
/* VECTOR ADD */
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
s390x/tcg: Implement VECTOR ADD COMPUTE CARRY 128-bit handling courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 23:15:30 +02:00
/* VECTOR ADD COMPUTE CARRY */
F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
s390x/tcg: Implement VECTOR ADD WITH CARRY Only slightly ugly, perform two additions. At least it is only supported for 128 bit elements. Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 23:22:57 +02:00
/* VECTOR ADD WITH CARRY */
F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only. Courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 23:25:46 +02:00
/* VECTOR ADD WITH CARRY COMPUTE CARRY */
F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT) Easy, as we can reuse existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-03-18 00:04:51 +01:00
/* VECTOR AND */
F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
/* VECTOR AND WITH COMPLEMENT */
F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
s390x/tcg: Implement VECTOR AVERAGE Handle 32/64-bit elements via gvec expansion and the 8/16 bits via ool helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 09:31:04 +02:00
/* VECTOR AVERAGE */
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
s390x/tcg: Implement VECTOR AVERAGE LOGICAL Similar to VECTOR AVERAGE but without sign extension. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 09:41:29 +02:00
/* VECTOR AVERAGE LOGICAL */
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
s390x/tcg: Implement VECTOR CHECKSUM Time to introduce read_vec_element_i32 and write_vec_element_i32. Take proper care of properly adding the carry. We can perform both additions including the carry via tcg_gen_add2_i32(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-03-20 23:18:59 +01:00
/* VECTOR CHECKSUM */
F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
s390x/tcg: Implement VECTOR ELEMENT COMPARE * Fairly easy to implement, we can make use of the existing CC helpers cmps64 and cmpu64 - we siply have to sign extend the elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 09:50:42 +02:00
/* VECTOR ELEMENT COMPARE */
F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
/* VECTOR ELEMENT COMPARE LOGICAL */
F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
s390x/tcg: Implement VECTOR COMPARE * To carry out the comparison, we can reuse the existing gvec comparison function. In case the CC is to be computed, save the result vector and compute the CC lazily. The result is a vector consisting of all 1's for elements that matched and 0's for elements that didn't match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 10:00:25 +02:00
/* VECTOR COMPARE EQUAL */
E(0xe7f8, VCEQ, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_EQ, IF_VEC)
/* VECTOR COMPARE HIGH */
E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
/* VECTOR COMPARE HIGH LOGICAL */
E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
s390x/tcg: Implement VECTOR COUNT LEADING ZEROS For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-04 14:37:17 +02:00
/* VECTOR COUNT LEADING ZEROS */
F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS Implement it similar to VECTOR COUNT LEADING ZEROS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-03-21 10:36:26 +01:00
/* VECTOR COUNT TRAILING ZEROS */
F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
s390x/tcg: Implement VECTOR EXCLUSIVE OR Easy, we can reuse an existing gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 10:07:35 +02:00
/* VECTOR EXCLUSIVE OR */
F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE) A galois field multiplication in field 2 is like binary multiplication, however instead of doing ordinary binary additions, xor's are performed. So no carries are considered. Implement all variants via helpers. s390_vec_sar() and s390_vec_shr() will be reused later on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:54:53 +02:00
/* VECTOR GALOIS FIELD MULTIPLY SUM */
F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD COMPLEMENT We can reuse an existing gvec helper for negating the values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 10:41:48 +02:00
/* VECTOR LOAD COMPLEMENT */
F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD POSITIVE Similar to VECTOR LOAD COMPLEMENT. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 10:43:39 +02:00
/* VECTOR LOAD POSITIVE */
F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL) Luckily, we already have gvec helpers for all four cases. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:49:12 +02:00
/* VECTOR MAXIMUM */
F(0xe7ff, VMX, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
/* VECTOR MAXIMUM LOGICAL */
F(0xe7fd, VMXL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
/* VECTOR MINIMUM */
F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
/* VECTOR MINIMUM LOGICAL */
F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
s390x/tcg: Implement VECTOR MULTIPLY AND ADD * Quite some variants to handle. At least handle some 32-bit element variants via gvec expansion (we could also handle 16/32-bit variants for ODD and EVEN easily via gvec expansion, but let's keep it simple for now). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:56:49 +02:00
/* VECTOR MULTIPLY AND ADD LOW */
F(0xe7aa, VMAL, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD HIGH */
F(0xe7ab, VMAH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD LOGICAL HIGH */
F(0xe7a9, VMALH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD EVEN */
F(0xe7ae, VMAE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD LOGICAL EVEN */
F(0xe7ac, VMALE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD ODD */
F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
s390x/tcg: Implement VECTOR MULTIPLY * Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND ADD *. At least for one variant we have a gvec helper we can reuse. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:58:46 +02:00
/* VECTOR MULTIPLY HIGH */
F(0xe7a3, VMH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL HIGH */
F(0xe7a1, VMLH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOW */
F(0xe7a2, VML, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY EVEN */
F(0xe7a6, VME, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL EVEN */
F(0xe7a4, VMLE, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY ODD */
F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL ODD */
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL Fortunately, we only need the Doubleword implementation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:23 +02:00
/* VECTOR MULTIPLY SUM LOGICAL */
F(0xe7b8, VMSL, VRR_d, VE, 0, 0, 0, 0, vmsl, 0, IF_VEC)
s390x/tcg: Implement VECTOR NAND Part of vector enhancements facility 1, but easy to implement. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:00:30 +02:00
/* VECTOR NAND */
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
s390x/tcg: Implement VECTOR NOR Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-05 15:52:09 +02:00
/* VECTOR NOR */
F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR Again, part of vector enhancement facility 1. The operation corresponds to an bitwise equality check. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:12:17 +02:00
/* VECTOR NOT EXCLUSIVE OR */
F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
s390x/tcg: Implement VECTOR OR Reuse a gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:12:42 +02:00
/* VECTOR OR */
F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
s390x/tcg: Implement VECTOR OR WITH COMPLEMENT Again, vector enhancements facility 1 material. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:14:29 +02:00
/* VECTOR OR WITH COMPLEMENT */
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
s390x/tcg: Implement VECTOR POPULATION COUNT Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:14:49 +02:00
/* VECTOR POPULATION COUNT */
F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:19:38 +02:00
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
target/s390x: Use tcg_gen_gvec_rotl{i,s,v} Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-04-20 18:50:54 +02:00
F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:27:29 +02:00
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
s390x/tcg: Implement VECTOR ELEMENT SHIFT We can use all the fancy new vector helpers implemented by Richard. One important thing to take care of is always to properly mask of unused bits from the shift count. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:59:30 +02:00
/* VECTOR ELEMENT SHIFT LEFT */
F(0xe770, VESLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe730, VESL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
F(0xe77a, VESRAV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe73a, VESRA, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-08 22:50:06 +02:00
/* VECTOR SHIFT LEFT */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-08 22:50:06 +02:00
/* VECTOR SHIFT LEFT BY BYTE */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, 1, IF_VEC)
target/s390x: vxeh2: vector shift double by bit Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220428094708.84835-9-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:03 +02:00
/* VECTOR SHIFT LEFT DOUBLE BY BIT */
E(0xe786, VSLD, VRI_d, VE2, 0, 0, 0, 0, vsld, 0, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE Inline expansion courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:39:23 +02:00
/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
target/s390x: vxeh2: vector shift double by bit Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220428094708.84835-9-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:03 +02:00
E(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsld, 0, 1, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:41:47 +02:00
/* VECTOR SHIFT RIGHT ARITHMETIC */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:41:47 +02:00
/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, 1, IF_VEC)
target/s390x: vxeh2: vector shift double by bit Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220428094708.84835-9-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:03 +02:00
/* VECTOR SHIFT RIGHT DOUBLE BY BIT */
F(0xe787, VSRD, VRI_d, VE2, 0, 0, 0, 0, vsrd, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:42:34 +02:00
/* VECTOR SHIFT RIGHT LOGICAL */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, 0, IF_VEC)
s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-11 11:42:34 +02:00
/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
target/s390x: vxeh2: Update for changes to vector shifts Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:02 +02:00
E(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, 1, IF_VEC)
s390x/tcg: Implement VECTOR SUBTRACT We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 21:37:24 +02:00
/* VECTOR SUBTRACT */
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:22:36 +02:00
/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION Fairly easy as only 128-bit handling is required. Simply perform the subtraction and then subtract the borrow. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:15:07 +02:00
/* VECTOR SUBTRACT WITH BORROW INDICATION */
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION Mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-09 23:26:47 +02:00
/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD Perform the calculations without a helper. Only 16 bit or 32 bit values have to be added. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:48:25 +02:00
/* VECTOR SUM ACROSS DOUBLEWORD */
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and using 128-bit calculations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:40:01 +02:00
/* VECTOR SUM ACROSS QUADWORD */
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
s390x/tcg: Implement VECTOR SUM ACROSS WORD Similar to VECTOR SUM ACROSS DOUBLEWORD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:45:35 +02:00
/* VECTOR SUM ACROSS WORD */
F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
s390x/tcg: Implement VECTOR TEST UNDER MASK Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 22:55:16 +02:00
/* VECTOR TEST UNDER MASK */
F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
s390x/tcg: Implement VECTOR ADD Introduce two types of fancy new helpers that will be reused a couple of times 1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3 parameters, simplifying parameter passing 2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations using two 64 bit values per vector. Luckily, for VECTOR ADD we already have everything we need. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-04-10 23:08:40 +02:00
s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUAL Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-23 15:09:49 +02:00
/* === Vector String Instructions === */
/* VECTOR FIND ANY ELEMENT EQUAL */
F(0xe782, VFAE, VRR_b, V, 0, 0, 0, 0, vfae, 0, IF_VEC)
s390x/tcg: Implement VECTOR FIND ELEMENT EQUAL Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-24 11:25:58 +02:00
/* VECTOR FIND ELEMENT EQUAL */
F(0xe780, VFEE, VRR_b, V, 0, 0, 0, 0, vfee, 0, IF_VEC)
s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUAL Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-24 11:26:45 +02:00
/* VECTOR FIND ELEMENT NOT EQUAL */
F(0xe781, VFENE, VRR_b, V, 0, 0, 0, 0, vfene, 0, IF_VEC)
s390x/tcg: Implement VECTOR ISOLATE STRING Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-24 11:27:56 +02:00
/* VECTOR ISOLATE STRING */
F(0xe75c, VISTR, VRR_a, V, 0, 0, 0, 0, vistr, 0, IF_VEC)
s390x/tcg: Implement VECTOR STRING RANGE COMPARE Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-24 11:23:49 +02:00
/* VECTOR STRING RANGE COMPARE */
F(0xe78a, VSTRC, VRR_d, V, 0, 0, 0, 0, vstrc, 0, IF_VEC)
target/s390x: vxeh2: vector string search Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-7-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-28 11:47:01 +02:00
/* VECTOR STRING SEARCH */
F(0xe78b, VSTRS, VRR_d, VE2, 0, 0, 0, 0, vstrs, 0, IF_VEC)
s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUAL Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-23 15:09:49 +02:00
s390x/tcg: Implement VECTOR FP ADD 1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:21:21 +02:00
/* === Vector Floating-Point Instructions */
/* VECTOR FP ADD */
F(0xe7e3, VFA, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:30:56 +02:00
/* VECTOR FP COMPARE SCALAR */
F(0xe7cb, WFC, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
/* VECTOR FP COMPARE AND SIGNAL SCALAR */
F(0xe7ca, WFK, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:35:08 +02:00
/* VECTOR FP COMPARE EQUAL */
F(0xe7e8, VFCE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
/* VECTOR FP COMPARE HIGH */
F(0xe7eb, VFCH, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
/* VECTOR FP COMPARE HIGH OR EQUAL */
F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT 1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:42:05 +02:00
/* VECTOR FP CONVERT FROM FIXED 64-BIT */
F(0xe7c3, VCDG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:47:20 +02:00
/* VECTOR FP CONVERT FROM LOGICAL 64-BIT */
F(0xe7c1, VCDLG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:49:52 +02:00
/* VECTOR FP CONVERT TO FIXED 64-BIT */
F(0xe7c2, VCGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:51:23 +02:00
/* VECTOR FP CONVERT TO LOGICAL 64-BIT */
F(0xe7c0, VCLGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP DIVIDE We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:54:33 +02:00
/* VECTOR FP DIVIDE */
F(0xe7e5, VFD, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
s390x/tcg: Implement VECTOR LOAD FP INTEGER We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:57:10 +02:00
/* VECTOR LOAD FP INTEGER */
F(0xe7c7, VFI, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED) Let's use the correct name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:13 +02:00
/* VECTOR FP LOAD LENGTHENED */
s390x/tcg: Implement VECTOR LOAD LENGTHENED Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:02:09 +02:00
F(0xe7c4, VFLL, VRR_a, V, 0, 0, 0, 0, vfll, 0, IF_VEC)
s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED) Let's use the correct name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:13 +02:00
/* VECTOR FP LOAD ROUNDED */
s390x/tcg: Implement VECTOR LOAD ROUNDED We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:06:42 +02:00
F(0xe7c5, VFLR, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) For IEEE functions, we can reuse the softfloat implementations. For the other functions, implement it generically for 32bit/64bit/128bit - carefully taking care of all weird special cases according to the tables defined in the PoP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:34 +02:00
/* VECTOR FP MAXIMUM */
F(0xe7ef, VFMAX, VRR_c, VE, 0, 0, 0, 0, vfmax, 0, IF_VEC)
/* VECTOR FP MINIMUM */
F(0xe7ee, VFMIN, VRR_c, VE, 0, 0, 0, 0, vfmax, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP MULTIPLY Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:09:33 +02:00
/* VECTOR FP MULTIPLY */
F(0xe7e7, VFM, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:17:09 +02:00
/* VECTOR FP MULTIPLY AND ADD */
F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
/* VECTOR FP MULTIPLY AND SUBTRACT */
F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-08 11:23:33 +02:00
/* VECTOR FP NEGATIVE MULTIPLY AND ADD */
F(0xe79f, VFNMA, VRR_e, VE, 0, 0, 0, 0, vfma, 0, IF_VEC)
/* VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT */
F(0xe79e, VFNMS, VRR_e, VE, 0, 0, 0, 0, vfma, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:18:57 +02:00
/* VECTOR FP PERFORM SIGN OPERATION */
F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP SQUARE ROOT Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:22:35 +02:00
/* VECTOR FP SQUARE ROOT */
F(0xe7ce, VFSQ, VRR_a, V, 0, 0, 0, 0, vfsq, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP SUBTRACT Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:25:34 +02:00
/* VECTOR FP SUBTRACT */
F(0xe7e2, VFS, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE We can reuse float64_dcmask(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 22:27:21 +02:00
/* VECTOR FP TEST DATA CLASS IMMEDIATE */
F(0xe74a, VFTCI, VRI_e, V, 0, 0, 0, 0, vftci, 0, IF_VEC)
s390x/tcg: Implement VECTOR FP ADD 1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-29 21:21:21 +02:00
target-s390: Convert SET ADDRESSING MODE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:28:56 +02:00
#ifndef CONFIG_USER_ONLY
target-s390: Convert CSP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:57:18 +02:00
/* COMPARE AND SWAP AND PURGE */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEUQ, IF_PRIV)
target-s390: Convert DIAGNOSE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 23:41:36 +02:00
/* DIAGNOSE (KVM hypercall) */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0, IF_PRIV | IF_IO)
target-s390: Convert ISKE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:13:38 +02:00
/* INSERT STORAGE KEY EXTENDED */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0, IF_PRIV)
target/s390x: Implement idte instruction Let's keep it very simple for now and flush the complete tlb, we currently can't find the right entries in our tlb, we would have to store the used tables for each element. As we now fully implement the DAT-enhancement facility, we can allow to enable it for the qemu CPU model. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170622094151.28633-4-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-22 11:41:51 +02:00
/* INVALIDATE DAT TABLE ENTRY */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0, IF_PRIV)
target-s390: Convert IPTE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 01:25:28 +02:00
/* INVALIDATE PAGE TABLE ENTRY */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0, IF_PRIV)
target-s390: Convert LCTL, STCTL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:17:58 +02:00
/* LOAD CONTROL */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb700, LCTL, RS_a, Z, 0, a2, 0, 0, lctl, 0, IF_PRIV)
F(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0, IF_PRIV)
target/s390x: Implement LOAD PROGRAM PARAMETER Linux arch/s390/kernel/head(64).S uses LPP instruction if it is available in facilities list provided by stfl/stfle instruction. This is the case of newer z/System generations and their qemu definition. The description of LPP is at http://www-01.ibm.com/support/docview.wss?uid=isg26fcd1cc32246f4c8852574ce0044734a Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Miroslav Benes <mbenes@suse.cz> Message-Id: <20170227085353.20787-1-mbenes@suse.cz> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-27 09:53:53 +01:00
/* LOAD PROGRAM PARAMETER */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb280, LPP, S, LPP, 0, m2_64, 0, 0, lpp, 0, IF_PRIV)
target-s390: Convert LOAD PSW Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 23:33:36 +02:00
/* LOAD PSW */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0, IF_PRIV)
target-s390: Convert LPSWE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 20:04:48 +02:00
/* LOAD PSW EXTENDED */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb2b2, LPSWE, S, Z, 0, a2, 0, 0, lpswe, 0, IF_PRIV)
target-s390: Convert LRA Note that truncating the store to r1 based on PSW_MASK_64 is incorrect. We always modify the entire register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 22:15:10 +02:00
/* LOAD REAL ADDRESS */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV)
F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV)
F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV)
target-s390: Implement LURA, LURAG, STURG Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-20 22:04:28 +02:00
/* LOAD USING REAL ADDRESS */
s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x" Using get_address() with register identifiers comming from an "r" field is wrong: if the "r" field designates "r0", we don't read the content and instead assume 0 - which should only be applied when the register was specified via "b" or "x". PoP 5-11 "Operand-Address Generation": "A zero in any of the B1, B2, X2, B3, or B4 fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the intermediate sum, regardless of the contents of general register 0. A displacement of zero has no special significance." This BUG became visible for CSPG as generated by LLVM-12 in the upstream Linux kernel (v5.11-rc2), used while creating the linear mapping in vmem_map_init(): Trying to store to address 0 results in a Low Address Protection exception. Debugging this was more complicated than it could have been: The program interrupt handler in the kernel will try to crash the kernel: doing so, it will enable DAT. As the linear mapping is not created yet (asce=0), we run into an addressing exception while tring to walk non-existant DAT tables, resulting in a program exception loop. This allows for booting upstream Linux kernels compiled by clang-12. Most of these cases seem to be broken forever. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-11 17:38:43 +01:00
E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_TEUL, IF_PRIV)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_TEUQ, IF_PRIV)
target-s390: Convert MVCP, MVCS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 22:00:27 +02:00
/* MOVE TO PRIMARY */
target/s390x: The MVCP and MVCS instructions are not privileged The "MOVE TO PRIMARY/SECONDARY" instructions can also be called from problem state. We just should properly check whether the secondary-space access key is valid here, too, and inject a privileged program exception if it is invalid. Message-Id: <20221205125852.81848-1-thuth@redhat.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-12-05 13:58:52 +01:00
C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0)
target-s390: Convert MVCP, MVCS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 22:00:27 +02:00
/* MOVE TO SECONDARY */
target/s390x: The MVCP and MVCS instructions are not privileged The "MOVE TO PRIMARY/SECONDARY" instructions can also be called from problem state. We just should properly check whether the secondary-space access key is valid here, too, and inject a privileged program exception if it is invalid. Message-Id: <20221205125852.81848-1-thuth@redhat.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-12-05 13:58:52 +01:00
C(0xdb00, MVCS, SS_d, Z, la1, a2, 0, 0, mvcs, 0)
target-s390: Convert PTLB Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:59:26 +02:00
/* PURGE TLB */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb20d, PTLB, S, Z, 0, 0, 0, 0, ptlb, 0, IF_PRIV)
target-s390: Convert RRBE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:22:13 +02:00
/* RESET REFERENCE BIT EXTENDED */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb22a, RRBE, RRE, Z, 0, r2_o, 0, 0, rrbe, 0, IF_PRIV)
target-s390: Convert SERVC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 20:12:40 +02:00
/* SERVICE CALL LOGICAL PROCESSOR (PV hypercall) */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb220, SERVC, RRE, Z, r1_o, r2_o, 0, 0, servc, 0, IF_PRIV | IF_IO)
target-s390: Convert SACF Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 19:17:16 +02:00
/* SET ADDRESS SPACE CONTROL FAST */
target/s390x/tcg: Fix and improve the SACF instruction The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be used from problem space, too. Just the switching to the home address space is privileged and should still generate a privilege exception. This bug is e.g. causing programs like Java that use the "getcpu" vdso kernel function to crash (see https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=990417#26 ). While we're at it, also check if DAT is not enabled. In that case the instruction is supposed to generate a special operation exception. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/655 Message-Id: <20221201184443.136355-1-thuth@redhat.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-12-01 19:44:43 +01:00
C(0xb279, SACF, S, Z, 0, a2, 0, 0, sacf, 0)
target-s390: Convert SCK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:20:49 +02:00
/* SET CLOCK */
s390x: sck: load into a temporary not into in1 We previously loaded into in1, but in1 is not filled during disassembly and hence always zero. This leads to an assertion failure: qemu-system-s390x: /home/nrb/qemu/include/tcg/tcg.h:654: temp_idx: Assertion `n >= 0 && n < tcg_ctx->nb_temps' failed.` Instead, use in2_la2_m64a to load from storage into in2 and pass that to the helper, which matches what we already do for SCKC. This fixes the SCK test I sent here under TCG: <https://www.spinics.net/lists/kvm/msg265169.html> Fixes: 9dc67537 ("s390x/tcg: implement SET CLOCK ") Suggested-by: David Hildenbrand <david@redhat.com> Signed-off-by: Nico Boehr <nrb@linux.ibm.com> Message-Id: <20220126084201.774457-1-nrb@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-26 09:42:01 +01:00
F(0xb204, SCK, S, Z, 0, m2_64a, 0, 0, sck, 0, IF_PRIV | IF_IO)
target-s390: Convert SCKC, STCKC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:36:58 +02:00
/* SET CLOCK COMPARATOR */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb206, SCKC, S, Z, 0, m2_64a, 0, 0, sckc, 0, IF_PRIV | IF_IO)
s390x/tcg: implement SET CLOCK PROGRAMMABLE FIELD Needed for machine check handling inside Linux (when restoring registers). Except for SIGP and machine checks, we don't make use of the register yet. Sufficient for now. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-08 17:01:56 +01:00
/* SET CLOCK PROGRAMMABLE FIELD */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0x0107, SCKPF, E, Z, 0, 0, 0, 0, sckpf, 0, IF_PRIV)
target-s390: Convert SPT, STPT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:47:26 +02:00
/* SET CPU TIMER */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb208, SPT, S, Z, 0, m2_64a, 0, 0, spt, 0, IF_PRIV | IF_IO)
target-s390: Convert SPX, STPX Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 01:11:32 +02:00
/* SET PREFIX */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb210, SPX, S, Z, 0, m2_32ua, 0, 0, spx, 0, IF_PRIV)
target-s390: Convert SPKA Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:55:34 +02:00
/* SET PSW KEY FROM ADDRESS */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb20a, SPKA, S, Z, 0, a2, 0, 0, spka, 0, IF_PRIV)
target-s390: Convert SSKE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:18:01 +02:00
/* SET STORAGE KEY EXTENDED */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb22b, SSKE, RRF_c, Z, r1_o, r2_o, 0, 0, sske, 0, IF_PRIV)
target-s390: Convert SET SYSTEM MASK Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 23:12:50 +02:00
/* SET SYSTEM MASK */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0x8000, SSM, S, Z, 0, m2_8u, 0, 0, ssm, 0, IF_PRIV)
target-s390: Convert SIGP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 22:52:23 +02:00
/* SIGNAL PROCESSOR */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xae00, SIGP, RS_a, Z, 0, a2, 0, 0, sigp, 0, IF_PRIV | IF_IO)
target-s390: Convert SCKC, STCKC Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:36:58 +02:00
/* STORE CLOCK COMPARATOR */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb207, STCKC, S, Z, la2, 0, new, m1_64a, stckc, 0, IF_PRIV)
target-s390: Convert LCTL, STCTL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 23:17:58 +02:00
/* STORE CONTROL */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0, IF_PRIV)
F(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0, IF_PRIV)
target-s390: Convert STAP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 01:18:33 +02:00
/* STORE CPU ADDRESS */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb212, STAP, S, Z, la2, 0, new, m1_16a, stap, 0, IF_PRIV)
target-s390: Convert STIDP Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-05 19:21:47 +02:00
/* STORE CPU ID */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb202, STIDP, S, Z, la2, 0, new, m1_64a, stidp, 0, IF_PRIV)
target-s390: Convert SPT, STPT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 00:47:26 +02:00
/* STORE CPU TIMER */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb209, STPT, S, Z, la2, 0, new, m1_64a, stpt, 0, IF_PRIV | IF_IO)
target-s390: Convert STFL Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 19:58:59 +02:00
/* STORE FACILITY LIST */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb2b1, STFL, S, Z, 0, 0, 0, 0, stfl, 0, IF_PRIV)
target-s390: Convert SPX, STPX Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-25 01:11:32 +02:00
/* STORE PREFIX */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb211, STPX, S, Z, la2, 0, new, m1_32a, stpx, 0, IF_PRIV)
target-s390: Convert STSI Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 19:43:38 +02:00
/* STORE SYSTEM INFORMATION */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb27d, STSI, S, Z, 0, a2, 0, 0, stsi, 0, IF_PRIV)
target-s390: Convert STNSM, STOSM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:08:40 +02:00
/* STORE THEN AND SYSTEM MASK */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xac00, STNSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV)
target-s390: Convert STNSM, STOSM Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-22 20:08:40 +02:00
/* STORE THEN OR SYSTEM MASK */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV)
target-s390: Convert STURA Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:45:38 +02:00
/* STORE USING REAL ADDRESS */
s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x" Using get_address() with register identifiers comming from an "r" field is wrong: if the "r" field designates "r0", we don't read the content and instead assume 0 - which should only be applied when the register was specified via "b" or "x". PoP 5-11 "Operand-Address Generation": "A zero in any of the B1, B2, X2, B3, or B4 fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the intermediate sum, regardless of the contents of general register 0. A displacement of zero has no special significance." This BUG became visible for CSPG as generated by LLVM-12 in the upstream Linux kernel (v5.11-rc2), used while creating the linear mapping in vmem_map_init(): Trying to store to address 0 results in a Low Address Protection exception. Debugging this was more complicated than it could have been: The program interrupt handler in the kernel will try to crash the kernel: doing so, it will enable DAT. As the linear mapping is not created yet (asce=0), we run into an addressing exception while tring to walk non-existant DAT tables, resulting in a program exception loop. This allows for booting upstream Linux kernels compiled by clang-12. Most of these cases seem to be broken forever. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-11 17:38:43 +01:00
E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUL, IF_PRIV)
exec/memop: Adding signedness to quad definitions Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-06 22:00:51 +01:00
E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUQ, IF_PRIV)
target/s390x: Add support for the TEST BLOCK instruction TEST BLOCK was likely once used to execute basic memory tests, but nowadays it's just a (slow) way to clear a page. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1495128400-23759-1-git-send-email-thuth@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-05-18 19:26:40 +02:00
/* TEST BLOCK */
s390x/tcg: handle privileged instructions via flags Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-27 15:03:01 +02:00
F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV)
target-s390: Convert TPROT Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-23 00:15:59 +02:00
/* TEST PROTECTION */
C(0xe501, TPROT, SSE, Z, la1, a2, 0, 0, tprot, 0)
target-s390: Convert subchannel instructions While we're at it, list all of the chapter 14 subchannel insns. Which is easy since all merely need indicate non-operation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:36:20 +02:00
target-s390x: wire up I/O instructions in TCG mode The code handling the I/O instructions for KVM decodes the instruction itself. In TCG mode also pass the full instruction word to the helpers. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-15 17:57:09 +02:00
/* CCW I/O Instructions */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb276, XSCH, S, Z, 0, 0, 0, 0, xsch, 0, IF_PRIV | IF_IO)
F(0xb230, CSCH, S, Z, 0, 0, 0, 0, csch, 0, IF_PRIV | IF_IO)
F(0xb231, HSCH, S, Z, 0, 0, 0, 0, hsch, 0, IF_PRIV | IF_IO)
F(0xb232, MSCH, S, Z, 0, insn, 0, 0, msch, 0, IF_PRIV | IF_IO)
F(0xb23b, RCHP, S, Z, 0, 0, 0, 0, rchp, 0, IF_PRIV | IF_IO)
F(0xb238, RSCH, S, Z, 0, 0, 0, 0, rsch, 0, IF_PRIV | IF_IO)
F(0xb237, SAL, S, Z, 0, 0, 0, 0, sal, 0, IF_PRIV | IF_IO)
F(0xb23c, SCHM, S, Z, 0, insn, 0, 0, schm, 0, IF_PRIV | IF_IO)
F(0xb274, SIGA, S, Z, 0, 0, 0, 0, siga, 0, IF_PRIV | IF_IO)
F(0xb23a, STCPS, S, Z, 0, 0, 0, 0, stcps, 0, IF_PRIV | IF_IO)
F(0xb233, SSCH, S, Z, 0, insn, 0, 0, ssch, 0, IF_PRIV | IF_IO)
F(0xb239, STCRW, S, Z, 0, insn, 0, 0, stcrw, 0, IF_PRIV | IF_IO)
F(0xb234, STSCH, S, Z, 0, insn, 0, 0, stsch, 0, IF_PRIV | IF_IO)
F(0xb236, TPI , S, Z, la2, 0, 0, 0, tpi, 0, IF_PRIV | IF_IO)
F(0xb235, TSCH, S, Z, 0, insn, 0, 0, tsch, 0, IF_PRIV | IF_IO)
target-s390: Convert subchannel instructions While we're at it, list all of the chapter 14 subchannel insns. Which is easy since all merely need indicate non-operation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-27 18:36:20 +02:00
/* ??? Not listed in PoO ninth edition, but there's a linux driver that
uses it: "A CHSC subchannel is usually present on LPAR only." */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xb25f, CHSC, RRE, Z, 0, insn, 0, 0, chsc, 0, IF_PRIV | IF_IO)
s390x/tcg: wire up pci instructions On s390x, pci support is implemented via a set of instructions (no mmio). Unfortunately, none of them are documented in the PoP; the code is based upon the existing implementation for KVM and the Linux zpci driver. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-11-16 10:09:53 +01:00
/* zPCI Instructions */
/* None of these instructions are documented in the PoP, so this is all
based upon target/s390x/kvm.c and Linux code and likely incomplete */
target/s390x: fix execution with icount This patch adds some gen_io_start() calls to allow execution of s390x targets in icount mode with -smp 1. It enables deterministic timers and record/replay features. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <160455551747.32240.17074484658979970129.stgit@pasha-ThinkPad-X280> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-11-05 06:51:57 +01:00
F(0xebd0, PCISTB, RSY_a, PCI, la2, 0, 0, 0, pcistb, 0, IF_PRIV | IF_IO)
F(0xebd1, SIC, RSY_a, AIS, r1, r3, 0, 0, sic, 0, IF_PRIV | IF_IO)
F(0xb9a0, CLP, RRF_c, PCI, 0, 0, 0, 0, clp, 0, IF_PRIV | IF_IO)
F(0xb9d0, PCISTG, RRE, PCI, 0, 0, 0, 0, pcistg, 0, IF_PRIV | IF_IO)
F(0xb9d2, PCILG, RRE, PCI, 0, 0, 0, 0, pcilg, 0, IF_PRIV | IF_IO)
F(0xb9d3, RPCIT, RRE, PCI, 0, 0, 0, 0, rpcit, 0, IF_PRIV | IF_IO)
F(0xe3d0, MPCIFC, RXY_a, PCI, la2, 0, 0, 0, mpcifc, 0, IF_PRIV | IF_IO)
F(0xe3d4, STPCIFC, RXY_a, PCI, la2, 0, 0, 0, stpcifc, 0, IF_PRIV | IF_IO)
s390x/tcg: wire up pci instructions On s390x, pci support is implemented via a set of instructions (no mmio). Unfortunately, none of them are documented in the PoP; the code is based upon the existing implementation for KVM and the Linux zpci driver. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-11-16 10:09:53 +01:00
target-s390: Convert SET ADDRESSING MODE Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-08-21 01:28:56 +02:00
#endif /* CONFIG_USER_ONLY */
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