Commit Graph

375 Commits

Author SHA1 Message Date
Stefan Weil 5cbdb3a34b Replace Qemu by QEMU in comments
The official spelling is QEMU.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07 14:00:45 +00:00
Thomas Huth cd6e932014 PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.

Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15 13:12:11 +01:00
Andreas Färber 9349b4f9fd Rename CPUState -> CPUArchState
Scripted conversion:
  for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
    sed -i "s/CPUState/CPUArchState/g" $file
  done

All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:27 +01:00
Andreas Färber 1328c2bf21 target-ppc: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc]
  sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Alexander Graf fc0b2c0f1a PPC: 405: Use proper CPU reset
On ppc405ep there is a register that allows for software to reset the
core, but not the whole system. Implement this reset using a reset
interrupt.

This gets rid of a bunch of #if 0'ed code.

Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-03-14 22:20:24 +01:00
Alexander Graf 3f9f6a5082 PPC: Add CPU feature for processor control
We're soon going to implement processor control features. Add the
feature flag, so we're well prepared.

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02 02:47:47 +01:00
Alexander Graf 58e00a2432 PPC: E500: Add doorbell defines
We're going to introduce doorbell instructions (called processor
control in the spec) soon. Add some defines for easier patch
readability later.

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02 02:47:47 +01:00
Alexander Graf 0ef654e3fc PPC: E500: Add some more excp vectors
Our EXCP list is getting outdated. By now, 3 new exception vectors have
been introduced. Update the list so we have everything at one place.

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02 02:47:46 +01:00
Alexander Graf 3f162d119e PPC: booke206: Check for TLB overrun
Our internal helpers to fetch TLB entries were not able to tell us
that an entry doesn't even exist. Pass an error out if we hit such
a case to not accidently pass beyond the TLB array.

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02 02:47:46 +01:00
Alexander Graf a1ef618a37 PPC: booke: add tlbnps handling
When using MAV 2.0 TLB registers, we have another range of TLB registers
available to read the supported page sizes from.

Add SPR definitions for those and add a helper function that we can use
to receive such a bitmap even when using MAV 1.0.

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02 02:47:46 +01:00
Alexander Graf e9205258ac PPC: Add IVOR 38-42
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06
from 38 - 42.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-02-02 02:47:45 +01:00
Dong Xu Wang 4abf79a428 fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-02 10:50:57 +00:00
David Gibson 02d4eae4b0 ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU.  A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG.  So far, these are only
used to handle the case of -cpu host because a KVM guest can use
the instructions when the host CPU supports them.

However, it's a mild layering violation to simply not include those
bits in the CPU descriptions for those CPUs that do support them,
just because we can't handle them in TCG.  This patch corrects the
situation, so that the instruction bits _are_ shown correctly in the
cpu spec table, but are masked out from the cpu state in the non-KVM
case.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-31 02:57:56 +01:00
David Gibson a7342588c0 pseries: Correct vmx/dfp handling in both KVM and TCG cases
Currently, when KVM is enabled, the pseries machine checks if the host
CPU supports VMX, VSX and/or DFP instructions and advertises
accordingly in the guest device tree.  It does this regardless of what
CPU is selected on the command line.  On the other hand, when in TCG
mode, it never advertises any of these facilities, even basic VMX
(Altivec) which is supported in TCG.

Now that we have a -cpu host option for ppc, it is fairly
straightforward to fix both problems.  This patch changes the -cpu
host code to override the basic cpu spec derived from the PVR with
information queried from the host avout VMX, VSX and DFP capability.
The pseries code then uses the instruction availability advertised in
the cpu state to set the guest device tree correctly for both the KVM
and TCG cases.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30 20:03:26 +01:00
Alexander Graf 8b242eba64 PPC: Bump qemu-system-ppc to 64-bit physical address space
Some 32-bit PPC CPUs can use up to 36 bit of physical address space.
Treat them accordingly in the qemu-system-ppc binary type.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30 20:03:17 +01:00
David Gibson a1e985833c ppc: First cut implementation of -cpu host
For convenience with kvm, x86 allows the user to specify -cpu host on the
qemu command line, which means make the guest cpu the same as the host
cpu.  This patch implements the same option for ppc targets.

For now, this just read the host PVR (Processor Version Register) and
selects one of our existing CPU specs based on it.  This means that the
option will not work if the host cpu is not supported by TCG, even if that
wouldn't matter for use under kvm.

In future, we can extend this in future to override parts of the cpu spec
based on information obtained from the host (via /proc/cpuinfo, the host
device tree, or explicit KVM calls).  That will let us handle cases where
the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated
CPU.  With appropriate annotation of the CPU specs we'll also then be able
to use host cpus under kvm even when there isn't a matching full TCG model.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30 17:11:54 +01:00
Fabien Chouteau ddd1055b07 PPC: booke timers
While working on the emulation of the freescale p2010 (e500v2) I realized that
there's no implementation of booke's timers features. Currently mpc8544 uses
ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for
example booke uses different SPR).

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06 09:48:09 +02:00
David Gibson 697ab89278 Implement POWER7's CFAR in TCG
This patch implements support for the CFAR SPR on POWER7 (Come From
Address Register), which snapshots the PC value at the time of a branch or
an rfid.  The latest powerpc-next kernel also catches it and can show it in
xmon or in the signal frames.

This works well enough to let recent kernels boot (which otherwise oops
on the CFAR access).  It hasn't been tested enough to be confident that the
CFAR values are actually accurate, but one thing at a time.

Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06 09:48:04 +02:00
Scott Wood 2bd9543cd3 ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
This definition is backward compatible with MAV=1.0 as long as
the guest does not set reserved bits in MAS1/MAS4.

Also, fix the shift in booke206_tlb_to_page_size -- it's the base
that should be able to hold a 4G page size, not the shift count.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06 09:48:04 +02:00
Scott Wood bebabbc7aa ppc: booke206: add "info tlb" support
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06 09:48:04 +02:00
Scott Wood 93dd5e852c kvm: ppc: booke206: use MMU API
Share the TLB array with KVM.  This allows us to set the initial TLB
both on initial boot and reset, is useful for debugging, and could
eventually be used to support migration.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06 09:48:04 +02:00
Alexander Graf 542df9bfb7 PPC: E500: Add ESR bit definitions
The BookE spec specifies a number of ESR bits. Add defines for them
so we can use them later on.

Reported-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-23 22:24:40 +02:00
Blue Swirl 97b348e7d2 Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:32:01 +00:00
Peter Maydell f5fc40bb81 target-alpha, target-ppc: Remove unnecessary setjmp.h include
Remove the include of setjmp.h from the cpu.h of target-alpha
and target-ppc. This is unnecessary because cpu-defs.h already
includes this header; this change brings these two targets
into line with all the rest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-12 21:01:20 +00:00
Blue Swirl 3b88670664 Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
* 'ppc-next' of git://repo.or.cz/qemu/agraf:
  PPC: move TLBs to their own arrays
  PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
  PPC: E500: Use MAS registers instead of internal TLB representation
  PPC: Only set lower 32bits with mtmsr
  PPC: update openbios firmware
  PPC: mpc8544ds: Add hypervisor node
  PPC: calculate kernel,initrd,cmdline locations dynamically
  target-ppc: Handle memory-forced I/O controller access
  PPC: E500: Implement reboot controller
2011-07-01 21:12:50 +00:00
Blue Swirl f081c76ccf Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:31 +00:00
Alexander Graf 1c53acccee PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types and
allocated that union. While it's a waste of memory (and cache) to allocate
TLB information for a TLB type with much information when you only need
little, it also inflicts another issue.

With the new KVM API, we can now share the TLB between KVM and qemu, but
for that to work we need to have both be in the same layout. We can't just
stretch it over to fit some internal different TLB representation.

Hence this patch moves all TLB types to their own array, allowing us to only
address and allocate exactly the boundaries required for the specific TLB
type at hand.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17 02:58:37 +02:00
Alexander Graf d1e256fe47 PPC: E500: Use MAS registers instead of internal TLB representation
The natural format for e500 cores to do TLB manipulation with are the MAS
registers. Instead of converting them into some internal representation
and back again when the guest reads them, we can just keep the data
identical to the way the guest passed it to us.

The main advantage of this approach is that we're getting closer to being
able to share MMU data with KVM using shared memory, so that we don't need
to copy lots of MMU data back and forth all the time. For this to work
however, another patch is required that gets rid of the TLB union, as that
destroys our memory layout that needs to be identical with the kernel one.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17 02:58:34 +02:00
Stefan Weil 6d42fb313b w32: Fix compilation and replace non-portable usage of ulong
ulong is undefined for w32 (and maybe other) compilations.
Replace it by uintptr_t (which also fixes compilation for w64
and is a better choice for pointer to integer conversions).

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-20 17:56:03 +02:00
Aurelien Jarno 091959defe Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
* 'ppc-next' of git://repo.or.cz/qemu/agraf:
  PPC: Qdev'ify e500 pci
  PPC MPC7544DS: Use new TLB helper function
  PPC: Implement e500 (FSL) MMU
  PPC: Add another 64 bits to instruction feature mask
  PPC: Add GS MSR definition
  PPC: Make MPC8544DS emulation work w/o KVM
  PPC: Make MPC8544DS obey -cpu switch
  Fix off-by-one error in sizing pSeries hcall table
  ppc64: Fix out-of-tree builds
  kvm: ppc: warn user on PAGE_SIZE mismatch
  kvm: ppc: detect old headers
  monitor: add PPC BookE SPRs
  kvm: ppc: fixes for KVM_SET_SREGS on init
  ppc64: Don't try to build sPAPR RTAS on Darwin
  Place pseries vty devices at addresses more similar to existing machines
  Make pSeries 'model' property more closely resemble real hardware
  pseries: Increase maximum CPUs to 256
2011-05-14 16:54:59 +02:00
Alexander Graf 01662f3e51 PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12 00:24:51 +02:00
Alexander Graf a5858d7af0 PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.

This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of something.

The easiest solution that came to my mind was to simply add another 64 bits
that we can also match on. Since the comparison is only done on start of the
qemu process to generate an internal opcode calling table, we should be fine
on any performance penalties here.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12 00:24:51 +02:00
Alexander Graf 71afeb6165 PPC: Add GS MSR definition
The BookE specification defines MSR bit 28 as Guest State. Add it
to the list of MSR macros.

Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12 00:24:51 +02:00
Scott Wood 90dc881222 monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),
and display them in "info registers".

Also get CR and PID from the existing KVM_GET_REGS.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09 22:31:37 +02:00
Stefan Weil 5b46d07d07 Fix typo in comment (embeded -> embedded)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08 10:02:16 +01:00
David Gibson ed120055c7 Implement PAPR VPA functions for pSeries shared processor partitions
Shared-processor partitions are those where a CPU is time-sliced between
partitions, rather than being permanently dedicated to a single
partition.  qemu emulated partitions, since they are just scheduled with
the qemu user process, behave mostly like shared processor partitions.

In order to better support shared processor partitions (splpar), PAPR
defines the "VPA" (Virtual Processor Area), a shared memory communication
channel between the hypervisor and partitions.  There are also two
additional shared memory communication areas for specialized purposes
associated with the VPA.

A VPA is not essential for operating an splpar, though it can be necessary
for obtaining accurate performance measurements in the presence of
runtime partition switching.

Most importantly, however, the VPA is a prerequisite for PAPR's H_CEDE,
hypercall, which allows a partition OS to give up it's shared processor
timeslices to other partitions when idle.

This patch implements the VPA and H_CEDE hypercalls in qemu.  We don't
implement any of the more advanced statistics which can be communicated
through the VPA.  However, this is enough to make normal pSeries kernels
do an effective power-save idle on an emulated pSeries, significantly
reducing the host load of a qemu emulated pSeries running an idle guest OS.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:57 +02:00
David Gibson f43e35255c Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full system
partitions, the guest does not have direct access to the hardware page
table.  Instead, the pagetable exists in hypervisor memory, and the guest
must manipulate it with hypercalls.

However, our current pSeries emulation more closely resembles the old
style where the guest must set up and handle the pagetables itself.  This
patch converts it to act like a modern partition.

This involves two things: first, the hash translation path is modified to
permit the has table to be stored externally to the emulated machine's
RAM.  The pSeries machine init code configures the CPUs to use this mode.

Secondly, we emulate the PAPR hypercalls for manipulating the external
hashed page table.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson 9d52e9079d Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu.  It's far
from perfect - it's missing a number of POWER7 features so far, including
any support for VSX or decimal floating point instructions.  However, it's
close enough to boot a kernel with the POWER7 PVR.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson cdaee00633 Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used on
powerpc MMUs were 256MB in size.  This was the only option on all hash
page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page
table based cpus.  However, newer 64-bit cpus also permit 1TB segments

This patch adds support for 1TB segment translation to the qemu code.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson 256cebe5d1 Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()
has a mix of common and 32 or 64 bit specific code.  However the
division is not done terribly well which results in a lot of messy code
flipping between common and divided paths.

This patch improves the organization, consolidating several divided paths
into one.  This in turn allows simplification of some code in
get_segment(), removing a number of ugly interim variables.

This new factorization will also make it easier to add support for the 1T
segments added in newer CPUs.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson fda6a0ecc6 Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash.  However it doesn't
(quite) get the hash value for the ppc hashed page table.  Instead it
gets the hash shifted - effectively the offset of the hash bucket within
the hash page table.

As well, as being different to the normal use of plain "hash" in the
architecture documentation, this usage necessitates some awkward 32/64
dependent masks and shifts which clutter up the path in get_segment().

This patch alters the code to use raw hash values through get_segment()
including storing raw hashes instead of pte group offsets in the ctx
structure.  This cleans up the path noticeably.

This does necessitate 32/64 dependent shifts when the hash values are
taken out of the ctx structure and used, but those paths already have
32/64 bit variants so this is less awkward than it was in get_segment().

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson bb593904c1 Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation
path.  But because the encodings of the size for 32-bit and 64-bit are
different this makes for a confusing branch on the MMU type with a bunch
of curly shifts and masks in the middle of the translate path.

This patch cleans things up by moving the interpretation on SDR1 into the
helper function handling the write to the register.  This leaves a simple
pre-sanitized base address and mask for the hash table in the CPUState
structure which is easier to work with in the translation path.

This makes the translation path more readable.  It addresses the FIXME
comment currently in the mtsdr1 helper, by validating the SDR1 value during
interpretation.  Finally it opens the way for emulating a pSeries-style
partition where the hash table used for translation is not mapped into
the guests's RAM.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:55 +02:00
David Gibson eaabeef268 Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results
truncated to 32-bits when the CPU is in 32-bit mode.  This is not
normal for powerpc - generally arithmetic instructions on a 64-bit
powerpc cpu will generate full 64 bit results, it's just that only the
low 32 bits will be significant for condition codes.

This patch corrects this nit, which actually simplifies the code slightly.

In addition, this patch implements the popcntw and popcntd
instructions added in POWER7, in preparation for allowing POWER7 as an
emulated CPU.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
David Gibson efdef95fee Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer.  Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions
which read SLB entries back into registers.  Because these are
only occasionally used in guests (mostly for debugging) we get
away with it.

However, given the recent SLB cleanups, it becomes quite easy to
implement these, and thereby allow, amongst other things, a guest
Linux to use xmon's command to dump the SLB.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
David Gibson d569956eaf Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.

qemu currently has stub implementations of hypervisor mode.  That
is, the outline is there to allow qemu to run a PowerPC hypervisor
under emulation.  There are a number of details missing so this
won't actually work at present, but the idea is there.

What there is no provision at all, is for qemu to instead emulate
the hypervisor itself.  That is to have hypercalls trap into qemu
and their result be emulated from qemu, rather than running
hypervisor code within the emulated system.

Hypervisor hardware aware KVM implementations are in the works and
it would  be useful for debugging and development to also allow
full emulation of the same para-virtualized guests as such a KVM.

Therefore, this patch adds a hook which will allow a machine to
set up emulation of hypervisor calls.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
David Gibson 81762d6dd0 Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'.  While the layout in these fields does match the
description of the SLB in the architecture document, it is not
convenient either for looking up the SLB, or for emulating the
slbmte instruction.

This patch, therefore, reorganizes the SLB entry structure to be
divided in the the "ESID related" and "VSID related" fields as
they are divided in instructions accessing the SLB.

In addition to making the code smaller and more readable, this will
make it easier to implement for the 1TB segments used in more
recent PowerPC chips.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01 18:34:54 +02:00
Stefan Weil 9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Blue Swirl ae0bfb79aa ppc: remove video.x
Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.

Remove video.x MoL hacks.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13 18:38:07 +00:00
Edgar E. Iglesias 2c50e26efd powerpc: Add a virtex5 ml507 refdesign board
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2010-09-30 18:53:30 +02:00
Edgar E. Iglesias a586e548fb powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-24 22:01:20 +02:00
Paolo Bonzini a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini 10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Paul Brook 3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Richard Henderson 5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Nathan Froyd e6bba2ef49 target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position.  Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.

Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27 16:10:49 +01:00
Alexander Graf 73b01960b4 PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 16:03:03 +01:00
Aurelien Jarno b711de9565 PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBL
should return a 64-bit value on 64 bit implementations.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 13:52:08 +01:00
Alexander Graf e3ea652962 PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using
two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.

On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full
64 bits as return value. If we only take the lower ones, fine. But Linux
wants to see all 64 bits or it breaks.

This patch makes PPC64 Linux work even after TB crossed the 32-bit boundary,
which usually happened a few seconds after bootup.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-21 13:42:37 +01:00
Blue Swirl d84bda46de PPC: rename cpu_ppc_reset to cpu_reset for consistency
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:36:04 +00:00
Aurelien Jarno cb2dbfc351 target-ppc: move often used CPU fields at the top of the structure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 00:14:05 +02:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Nathan Froyd 0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Blue Swirl b11ebf64b6 Replace REGX with PRIx64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:54:37 +00:00
Blue Swirl 90e189ece1 Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:13:18 +00:00
Blue Swirl 636aa20056 Replace always_inline with inline
We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 09:06:54 +00:00
Nathan Froyd 4425265beb target-ppc: add exceptions for conditional stores
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd 18b21a2f83 target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed.  It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd 174c80d516 target-ppc: add cpu_set_tls
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd d11f69b201 target-ppc: fix cpu_clone_regs
We only need to make sure that the clone syscall looks like it
succeeded, not clobber 60% of the register set.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:40 +04:00
Blue Swirl 8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Paul Brook 1ad2134f91 Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.

Remove and poison various target specific macros to avoid bogus target
dependencies creeping back in.

Big/Little endian is not handled because devices should not know or care
about this to start with.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-19 16:17:58 +01:00
Nathan Froyd c29b735c50 target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-05-16 01:36:08 +04:00
Blue Swirl fc1c67bc2a Fix PPC reset 2009-04-28 18:00:30 +00:00
blueswir1 7f70c93716 Make the ELF loader aware of backwards compatibility
Most 64 bit architectures I'm aware of support running 32 bit code
of the same architecture as well.

So x86_64 can run i386 code easily and ppc64 can run ppc code.

Unfortunately, the current checks are pretty strict. So you can only
load e.g. an x86_64 elf binary on qemu-system-x86_64, but no i386 one.

This can get really annoying. I first encountered this issue with
my multiboot patch, where qemu-system-x86_64 was unable to load an
i386 elf binary because the elf loader rejected it.

The same thing happened again on PPC64 now. The firmware we're loading
is a PPC32 elf binary, as it's shared with PPC32. But the platform is
PPC64.

Right now there is a hack for this in the ppc cpu.h definition, that
simply sets the type to PPC32 in system emulation mode. While that
works fine for the firmware, it's no good if you also want to load a
PPC64 kernel with -kernel.

So in order to solve this mess, I figured the easiest way is to make
the elf loader aware of platforms that are backwards compatible. For
now I was only sure that x86_64 does i386 and ppc64 does ppc32, but
maybe there are other combinations too.

This patch is a prerequisite for having a working -kernel option on
PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6855 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 21:16:24 +00:00
blueswir1 8eee0af947 Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled
easily, but for now it's safer to leave that off I guess (970fx doesn't
have bridge mode AFAIK).

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:57:42 +00:00
blueswir1 5b5aba4f14 Implement large pages
The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6748 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:51:18 +00:00
blueswir1 f6b868fc58 Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later.

This is required for Linux to run on PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:50:01 +00:00
pbrook c276471991 The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
aurel32 9fdc60bf55 kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02 16:42:32 +00:00
blueswir1 3a616592a1 Load 32 bit ELF BIOS images also on PPC64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6554 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-08 12:50:56 +00:00
aurel32 fbd265b681 Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:51 +00:00
aurel32 0f6fbcbccd Add f field to ppc_avr_t
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6505 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:43 +00:00
aurel32 fad6cb1a56 Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:05:52 +00:00
aurel32 6fa724a34a Add vscr access macros.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6158 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-03 14:04:11 +00:00
aurel32 2231ef1084 target-ppc: fix type of spe_acc.
ACC is a 64-bit register and needs to be specified as such regardless of
the target.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6090 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-18 22:43:25 +00:00
aurel32 ab5f265daa target-ppc: add signed fields to ppc_avr_t.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6042 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 07:03:06 +00:00
aurel32 9322057384 target-ppc: remove remaining warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:33 +00:00
aurel32 45d827d2d7 target-ppc: convert SPR accesses to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 13:40:29 +00:00
aurel32 8983da70c4 target-ppc: remove dead code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 22:01:01 +00:00
aurel32 74d37793f4 target-ppc: convert SLB/TLB instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 21:46:17 +00:00
aurel32 2cbd949d7a Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:09 +00:00
aurel32 01a4afeb99 target-ppc: convert POWER2 load/store instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27 19:30:56 +00:00
aurel32 6a6ae23f3c target-ppc: convert SPE load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27 19:30:47 +00:00
aurel32 fe1e5c53fd target-ppc: convert altivec load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-24 08:47:21 +00:00
aurel32 af12906f77 target-ppc: convert fp ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19 16:10:23 +00:00
aliguori 6b9175478e Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori 622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
aurel32 57951c2742 target-ppc: convert most SPE integer instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-10 11:10:23 +00:00
aurel32 4870167d04 target-ppc: fix tcg fatal error on i386 host
It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.

Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5648 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-08 08:57:45 +00:00
aurel32 8d71247eaa target-ppc: xer access prototypes no more used & implemented
Revision 5500 of the qemu repository removed all code using
ppc_load_xer & ppc_store_xer as well as their implementation.

Another patch fixes it's usage in kvm-userspace for powerpc, but I think
that header can now be cleaned up, therefore this patch to qemu-devel.

Signed-off-by: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5589 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:53:59 +00:00
aurel32 e1571908a2 target-ppc: convert crf related instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:31:14 +00:00
aurel32 3d7b417e13 target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:28:46 +00:00
blueswir1 b55266b5a2 Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20 08:07:15 +00:00
aurel32 47e4661cc4 ppc: Convert CRF moves to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:06:47 +00:00
aurel32 bd7d9a6d7b ppc: cleanup register types
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:26:09 +00:00
aurel32 f78fb44e82 ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:25:47 +00:00
pbrook 9656f324d2 Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 20:01:19 +00:00
pbrook b3c7724cbc Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 16:31:04 +00:00
pbrook 2e70f6efa8 Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
pbrook f8ed7070ea Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:54:15 +00:00
pbrook 6e68e076e7 Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:22:15 +00:00
bellard 9133e39b84 Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 10:08:06 +00:00
bellard ce5232c5c2 moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 17:14:10 +00:00
aurel32 f9320410e1 PPC: fix definition of msr_spe
(Tristan Gingold)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4361 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 14:58:15 +00:00
j_mayer e9b34b3741 Cleanup: remove useless TARGET_GPR_BITS definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3799 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-10 08:13:09 +00:00
j_mayer 4e7774427d Fix PowerPC 74xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-10 07:40:16 +00:00
j_mayer 6b542af760 Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24 02:03:55 +00:00
j_mayer 69facb7897 Revert foolish patch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23 22:16:59 +00:00
pbrook 9b605b9eae Fix ppc32 register dumps on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23 17:33:12 +00:00
j_mayer bd928ebafe Fix PowerPC 7xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-21 13:08:23 +00:00
j_mayer 082c6681b6 Remove shared macro used to define PowerPC implementations instructions sets:
tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 13:22:47 +00:00
j_mayer add78955b0 PowerPC 620 MMU do not have the same exact behavior as standard
64 bits PowerPC ones.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 11:41:10 +00:00
j_mayer 4018bae916 New PowerPC CPU flag to define the decrementer and time-base source clock.
Use it to properly initialize the clock for the PreP target.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 01:48:12 +00:00
j_mayer 4c1b1bfe30 Improve PowerPC instructions set dump.
Remove meaningless define from cpu.h
Misc cleanups.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 23:14:53 +00:00
j_mayer 80d11f4467 Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
  thus providing a way of testing their implementation specific instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 23:02:20 +00:00
j_mayer b4095fed95 Define Freescale cores specific MMU model, exceptions and input bus.
(but do not provide any actual implementation).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 22:42:36 +00:00
j_mayer a4f30719a8 PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
Remove TARGET_PPC64 dependency and add code provision to be able
  to define a fake 32 bits CPU with hypervisor feature support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 21:14:09 +00:00
j_mayer 7820dbf3f0 Make the PowerPC MMU model, exception model and input bus model
typedefed enums.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 02:16:14 +00:00
j_mayer 7b62a95504 Add missing definition for number of input pins for the PowerPC 970 bus.
Use proper INPUT_NB definitions to allocate PowerPC input pins structure,
  fixing a buffer overflow in the 6xx bus case.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 02:04:00 +00:00
j_mayer b172c56a6d Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 01:37:44 +00:00
j_mayer 7863667f35 Always make PowerPC hypervisor mode memory accesses and instructions
available for full system emulation, then removing all #if TARGET_PPC64H
  from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
  in target-ppc/translate.c.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3654 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-16 14:11:28 +00:00
j_mayer 57c26279c7 Fix PowerPC targets compilation on 32 bits hosts:
now that the SPE extension is available for all targets,
 we always need to have some 64 bits temporary registers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14 18:45:52 +00:00
j_mayer 65d6c0f33c PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 23:29:14 +00:00
j_mayer 3cd7d1ddbb Allow use of SPE extension by all PowerPC targets,
adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
  and 36 bits physical address space.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 01:56:18 +00:00
j_mayer ee4e83ed8d Allow selection of PowerPC CPU giving a PVR.
Remove unused pvr_mask field from CPU definition.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 23:51:02 +00:00
bellard aaed909a49 added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
j_mayer 056401eae6 PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3524 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-04 02:55:33 +00:00
j_mayer faadf50e29 PowerPC MMU and exception fixes:
* PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
  later PowerPC implementation.
* Bugfix in BATs check: must not stop after 4 BATs when more are provided.
* Enable POWER 'rac' instruction.
* Fix exception prefix for all supported PowerPC implementations.
* Fix exceptions, MMU model and bus model for PowerPC 601 & 620.
* Enable PowerPC 620 as it could mostly boot a PreP target.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3518 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03 13:37:12 +00:00
j_mayer 7c58044c0a Fix PowerPC FPSCR update and floating-point exception generation
in most useful cases.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 17:54:30 +00:00
j_mayer cd346349b4 Add PowerPC power-management state check callback.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3441 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 23:27:04 +00:00
j_mayer 0411a97258 Gprof prooved the PowerPC emulation spent too much time in MSR load and store
routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code.
Allow entering halt mode as the result of a rfi instruction.
Add a new helper_regs.h file to avoid duplication of special registers
 manipulation routines (currently XER and MSR).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3436 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 21:35:50 +00:00
j_mayer b227a8e9aa Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC 64 MMU.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 10:21:20 +00:00
j_mayer d68f13063b Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.
Avoid hardcoding PowerPC interrupts definitions to ease updates.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3393 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 09:27:16 +00:00
j_mayer a13d7523cb There is no need of a specific MMU model for PowerPC 601.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 09:14:08 +00:00
j_mayer 6ebbf39000 Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 07:07:08 +00:00
j_mayer c732abe222 Unify '-cpu ?' option.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-12 06:47:46 +00:00
j_mayer 25ba3a6812 Remove synonymous in PowerPC MSR bits definitions.
Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3354 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 02:58:07 +00:00
j_mayer a9d9eb8fd4 Implement PowerPC Altivec load & stores, used by Apple firmware for memcpy.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 18:19:26 +00:00
j_mayer b33c17e12d PowerPC target coding style fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 17:30:34 +00:00
j_mayer f2e63a42c9 Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 15:43:50 +00:00
j_mayer d26bfc9a1b Add MSR bits signification per PowerPC implementation flags (to be continued).
As a side effect, single step and branch step are available again.
Remove irrelevant MSR bits definitions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 14:41:00 +00:00
j_mayer 12de9a396a Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
  emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces.
Temporary hack to make PowerPC 970 boot from ROM instead of RAM.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3335 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-05 22:06:02 +00:00
j_mayer 65f9ee8d67 Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3333 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-05 13:11:25 +00:00
j_mayer d63001d114 Make PowerPC cache line size implementation dependant.
Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-04 00:51:58 +00:00
j_mayer 00af685fc9 We never have to export ppc_set_irq.
Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-03 01:05:39 +00:00
j_mayer a97fed52e5 Fix reproductible crash: call cpu_loop_exit from micro-op, not from helper.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3311 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-01 21:49:57 +00:00
j_mayer daf4f96ece Avoid op helpers that would just call helpers for TLB & SLB management:
call the helpers directly from the micro-ops.
Avoid duplicated code for tlbsx. implementation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3302 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-01 01:51:12 +00:00
j_mayer 4e290a0b71 Share input pins and internal interrupt controller between all PowerPC 40x.
Fix critical input interrupt generation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-01 01:27:10 +00:00
j_mayer be147d0879 * Update OEA environment, following the PowerPC 2.04 specification:
- New mtmsr/mtmsrd form that just update RI and EE bits
- New hrfid, lq and stq instructions
- Add support for supervisor and hypervisor modes process priority update
- Code provision for hypervisor SPR accesses
* Actually implement the wait instruction
* Bugfixes (missing RETURN in micro-op / missing #ifdef)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3289 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30 13:03:23 +00:00
j_mayer bfa1e5cf0a XER is to be treated as a 64 bits register on 64 bits implementations,
according to the PowerPC 2.04 specification.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3279 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30 00:50:23 +00:00
j_mayer a062e36c58 Implement the PowerPC alternate time-base, following the 2.04 specification.
Share most code with the time-base management routines.
Remove time-base write routines from user-mode emulation environments.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3277 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30 00:38:38 +00:00
j_mayer 58a7d32872 Code provision for hypervisor timers resources,
as described in PowerPC 2.04 specification.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3264 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29 13:21:37 +00:00
j_mayer e1833e1f96 Rework PowerPC exceptions model to make it more versatile:
* don't use exception vectors as the exception number.
  Use vectors numbers as defined in the PowerPC embedded specification instead
  and extend this model to cover all emulated PowerPC variants exceptions.
* add some missing exceptions definitions, from PowerPC 2.04 specification
  and actual PowerPC implementations.
* add code provision for hypervisor exceptions handling.
* define exception vectors and prefix in CPUPPCState to emulate BookE exception
  vectors without any hacks.
* define per CPU model valid exception vectors.
* handle all known exceptions in user-mode only emulations.
* fix hardware interrupts priorities in most cases.
* change RET_EXCP macros name into GEN_EXCP as they don't return.
* do not stop translation on most instructions that are not defined as
  context-synchronizing in PowerPC specification.
* fix PowerPC 64 jump targets and link register update when in 32 bits mode.
* Fix PowerPC 464 and 464F definitions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3261 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29 13:06:16 +00:00
j_mayer 237c0af017 Define the proper bfd_mach to be used by the disassembler for each
PowerPC emulated CPU.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3257 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29 12:01:46 +00:00
ths 198a74de4c Move get_sp_from_cpustate from cpu.h to target_signal.h.
Enable sigaltstack processing for more architectures.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 16:44:32 +00:00
ths a04e134ad1 linux-user sigaltstack() syscall, by Thayne Harbaugh.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 13:57:58 +00:00
j_mayer a750fc0b91 Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-26 23:54:22 +00:00
j_mayer 2662a059aa More PowerPC definitions, from POWER 2.04 specifications and misc sources.
Check that at least instructions set and SPRs are correct for
 PowerPC 401, 403, 405 and 440 cores.
Implement PowerPC 401 MMU model (real-mode only).
Improve INSNs and SPRs dump to ease parse with standard shell tools.
Add more precise status for most PowerPC cores families.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3201 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-21 05:50:37 +00:00
j_mayer 4296f45902 Make CPU hflags be a masked version of the PowerPC MSR.
As a side effect, avoid potential bits shadowing in TB flags on 64 bits BookE.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3199 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-21 05:23:26 +00:00
j_mayer cbecba264b Move likely and unlikely macros in a common place (Aurelien Jarno).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3192 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-20 09:44:48 +00:00
j_mayer 71c8b8fd7b TARGET_FMT_lu may also be useful.
Fix compilation warnings.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3190 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-19 05:46:03 +00:00
j_mayer 8b67546f65 More PowerPC target cleanups:
- remove unuseful historical macros and definitions
- fix comments (bugs and cosmetics)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3185 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-19 04:34:09 +00:00
j_mayer d9d7210c7d Fix PowerPC 32 emulation on 64 bits hosts:
we can use 64 bits registers but not pretend page is 1kB long
As it seems most Linux programs assume page-size is 4kB, never allow
1kB pages for user-mode only emulation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3182 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-18 11:17:30 +00:00
j_mayer 3608160206 Coding style fixes in PowerPC related code (no functional change):
- avoid useless blanks at EOL.
- avoid tabs.
- fix wrapping lines on 80 chars terminals.
- add missing ';' at macros EOL to avoid confusing auto-identers.
- fix identation.
- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3178 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17 08:21:54 +00:00
ths 5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
ths 3c4c9f9f51 Fix PPCEMB for 32bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162
2007-07-11 10:36:47 +00:00
ths 0cfec834c5 Spelling fixes, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3009 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-23 16:02:43 +00:00
ths 9467d44c4d Move target-specific defines to the target directories.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-03 21:02:38 +00:00
j_mayer 35cdaad645 Code provision for new PowerPC embedded target support with:
- 1 kB page size
- 64 bits GPR
- 64 bits physical address space
- SPE extension support.
Change TARGET_PPCSPE into TARGET_PPCEMB


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-24 06:50:21 +00:00
j_mayer c294fc587a Improve PowerPC 405 MMU model / share more code for other embedded targets
support.
Fix PowerPC 405 MSR mask.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2717 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-24 06:44:14 +00:00
j_mayer 8ecc791352 Add callbacks to allow dynamic change of PowerPC clocks (to be improved)
Fix embedded PowerPC watchdog and timers
Fix PowerPC 405 SPR
Add generic PowerPC 405 core instanciation code + resets support.
Implement simple peripherals shared by most PowerPC 405 implementations
PowerPC 405 EC & EP microcontrollers preliminary support


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2690 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-16 20:09:45 +00:00
j_mayer c55e9aefa7 PowerPC 4xx software driven TLB fixes + debug traces.
Add code provision for more MMU models support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2683 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-16 09:21:46 +00:00
j_mayer 0a032cbec6 Add reset callbacks for PowerPC CPU.
Move cpu_ppc_init, cpu_ppc_close, cpu_ppc_reset and ppc_tlb_invalidate
into helper.c as they are to be called from outside of the translated code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2682 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-16 08:56:52 +00:00
j_mayer d0dfae6e91 Add bus model (or input pins) into PowerPC CPU flags.
Add PowerPC 970 bus and exceptions model.
Add code provision for PowerPC 970 instanciation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2680 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-16 07:34:39 +00:00
j_mayer e96efcfcb1 Fix miscellaneous display warnings for PowerPC & alpha targets
and parallel CFI flash driver.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-14 12:17:09 +00:00
j_mayer 24be5ae3a0 Add PowerPC 405 input pins (IRQ, resets, ...) model.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2654 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-12 21:24:29 +00:00
j_mayer 2e719ba347 Embedded PowerPC Device Control Registers infrastructure.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2653 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-12 21:11:03 +00:00
j_mayer e9df014c0b Implement embedded IRQ controller for PowerPC 6xx/740 & 750.
Fix PowerPC external interrupt input handling and lowering.
Fix OpenPIC output pins management.
Fix multiples bugs in OpenPIC IRQ management.
Fix OpenPIC CPU(s) reset function.
Fix Mac99 machine to properly route OpenPIC outputs to the PowerPC input pins.
Fix PREP machine to properly route i8259 output to the PowerPC external
  interrupt pin.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2647 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 22:45:36 +00:00
pbrook d537cf6c86 Unify IRQ handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 18:14:41 +00:00
j_mayer 1d0a48fb92 As embedded PowerPC TLB model is very different from PowerPC 6xx ones,
define ppc_tlb_t as an union of the two.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2553 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-31 11:10:49 +00:00
j_mayer 363be49c86 Fix / update PowerPC BookE definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2543 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 10:07:33 +00:00
j_mayer 4710357290 New model for PowerPC CPU hardware interrupt events:
move all PowerPC specific code into target-ppc/helper.c to avoid polluting
the common code in cpu-exec.c. This makes implementation of new features
(ie embedded PowerPC timers, critical interrupts, ...) easier.
This also avoid hardcoding the IRQ callback in the OpenPIC controller,
making it more easily reusable and allowing cascading.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2542 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 09:38:04 +00:00
j_mayer de270b3c7c Solaris host compilation fix by Shaddy Baddah.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2541 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-28 20:43:46 +00:00
j_mayer 426613dbf8 Add missing PowerPC 64 instructions
PowerPC 64 fixes.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2530 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23 09:45:27 +00:00
j_mayer 1b9eb036b9 Fix debug printf: we need different macros for target_ulong prints
and GPR ones, as the lengths can be different.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2529 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23 09:40:22 +00:00
j_mayer 51789c410b PowerPC improvments:
- add missing 64 bits rotate instructions
- safely define TARGET_PPCSPE when 64 bits registers are used
  a separate target will be needed to use it in 32 bits mode on 32 bits hosts.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2527 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-22 22:41:50 +00:00
j_mayer 0487d6a8b4 PowerPC 2.03 SPE extension - first pass.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2519 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-20 22:11:31 +00:00
j_mayer d9bce9d99f Make it safe to use 64 bits GPR and/or 64 bits host registers.
For "symetry", add 64 bits versions of all modified functions.
As a side effect, add a lot of code provision for PowerPC 64 support.
Move overflow and carry checks in common routines for simple cases.
Add isel and popcntb instructions from PowerPC 2.03 specification.
Remove remaining micro-operations helpers prototypes from op.c.
Fix XER_BC field to be 7 bits long.
Add power management support for PowerPC 603 & 604.
Fix compilation warnings.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2482 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-17 14:02:15 +00:00
j_mayer 76a66253e5 Great PowerPC emulation code resynchronisation and improvments:
- Add status file to make regression tracking easier
- Move all micro-operations helpers definitions into a separate header:
  should never be seen outside of op.c
- Update copyrights
- Add new / missing PowerPC CPU definitions
- Add definitions for PowerPC BookE
- Add support for PowerPC 6xx/7xx software driven TLBs
  Allow use of PowerPC 603 as an example
- Add preliminary code for POWER, POWER2, PowerPC 403, 405, 440, 601, 602
  and BookE support
- Avoid compiling priviledged only resources support for user-mode emulation
- Remove unused helpers / micro-ops / dead code
- Add instructions usage statistics dump: useful to figure which instructions
  need strong optimizations.
- Micro-operation fixes:
  * add missing RETURN in some micro-ops
  * fix prototypes
  * use softfloat routines for all floating-point operations
  * fix tlbie instruction
  * move some huge micro-operations into helpers
- emulation fixes:
  * fix inverted opcodes for fcmpo / fcmpu
  * condition register update is always to be done after the whole
    instruction has completed
  * add missing NIP updates when calling helpers that may generate an
    exception
- optimizations and improvments:
  * optimize very often used instructions (li, mr, rlwixx...)
  * remove specific micro-ops for rarely used instructions
  * add routines for addresses computations to avoid bugs due to multiple
    different implementations
  * fix TB linking: do not reset T0 at the end of every TB.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2473 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-07 08:32:30 +00:00