2003-02-11 20:34:11 +01:00
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@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
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MAINTAINERS (c4x port): Remove.
* MAINTAINERS (c4x port): Remove.
contrib:
* paranoia.cc (main): Remove handling of c4x_single and
c4x_extended formats.
gcc:
* config/c4x: Remove directory.
* config.gcc (crx-*, mt-*): Mark obsolete.
(c4x-*, tic4x-*, c4x-*-rtems*, tic4x-*-rtems*, c4x-*, tic4x-*,
h8300-*-rtemscoff*, ns32k-*-netbsdelf*, ns32k-*-netbsd*,
sh-*-rtemscoff*): Remove cases.
* defaults.h (C4X_FLOAT_FORMAT): Remove.
* real.c (encode_c4x_single, decode_c4x_single,
encode_c4x_extended, decode_c4x_extended, c4x_single_format,
c4x_extended_format): Remove.
* real.h (c4x_single_format, c4x_extended_format): Remove.
* doc/extend.texi (interrupt, naked): Remove mention of attributes
on C4x.
(Pragmas): Remove comment about c4x pragmas.
* doc/install.texi (c4x): Remove target-specific instructions.
* doc/invoke.texi (TMS320C3x/C4x Options): Remove.
* doc/md.texi (Machine Constraints): Remove C4x documentation.
* doc/tm.texi (MEMBER_TYPE_FORCES_BLK, c_register_pragma): Do not
refer to C4x source files as examples.
(C4X_FLOAT_FORMAT): Remove documentation.
gcc/testsuite:
* gcc.dg/builtin-inf-1.c, gcc.dg/compare6.c, gcc.dg/sibcall-3.c,
gcc.dg/sibcall-4.c, gcc.dg/torture/builtin-attr-1.c: Don't handle
c4x-*-* targets.
libgcc:
* config.host (tic4x-*-*, c4x-*-rtems*, tic4x-*-rtems*, c4x-*,
tic4x-*, h8300-*-rtemscoff*, ns32k-*-netbsdelf*, ns32k-*-netbsd*,
sh-*-rtemscoff*): Remove cases.
From-SVN: r131835
2008-01-25 21:49:04 +01:00
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@c 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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1997-03-25 20:26:08 +01:00
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@c This is part of the GCC manual.
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@c For copying conditions, see the file gcc.texi.
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@ifset INTERNALS
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@node Machine Desc
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@chapter Machine Descriptions
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@cindex machine descriptions
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A machine description has two parts: a file of instruction patterns
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(@file{.md} file) and a C header file of macro definitions.
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The @file{.md} file for a target machine contains a pattern for each
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instruction that the target machine supports (or at least each instruction
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that is worth telling the compiler about). It may also contain comments.
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A semicolon causes the rest of the line to be a comment, unless the semicolon
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is inside a quoted string.
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See the next chapter for information on the C header file.
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@menu
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2000-12-04 18:23:34 +01:00
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* Overview:: How the machine description is used.
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1997-03-25 20:26:08 +01:00
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* Patterns:: How to write instruction patterns.
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* Example:: An explained example of a @code{define_insn} pattern.
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* RTL Template:: The RTL template defines what insns match a pattern.
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* Output Template:: The output template says how to make assembler code
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from such an insn.
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* Output Statement:: For more generality, write C code to output
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the assembler code.
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genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
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* Predicates:: Controlling what kinds of operands can be used
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for an insn.
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* Constraints:: Fine-tuning operand selection.
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1997-03-25 20:26:08 +01:00
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* Standard Names:: Names mark patterns to use for code generation.
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* Pattern Ordering:: When the order of patterns makes a difference.
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* Dependent Patterns:: Having one pattern may make you need another.
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* Jump Patterns:: Special considerations for patterns for jump insns.
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2000-12-21 23:08:17 +01:00
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* Looping Patterns:: How to define patterns for special looping insns.
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1997-03-25 20:26:08 +01:00
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* Insn Canonicalizations::Canonicalization of Instructions
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* Expander Definitions::Generating a sequence of several RTL insns
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1999-10-02 20:07:49 +02:00
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for a standard operation.
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* Insn Splitting:: Splitting Instructions into Multiple Instructions.
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2001-11-14 21:17:08 +01:00
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* Including Patterns:: Including Patterns in Machine Descriptions.
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1999-10-02 20:07:49 +02:00
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* Peephole Definitions::Defining machine-specific peephole optimizations.
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1997-03-25 20:26:08 +01:00
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* Insn Attributes:: Specifying the value of attributes for generated insns.
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rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
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* Conditional Execution::Generating @code{define_insn} patterns for
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predication.
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2000-11-22 02:22:02 +01:00
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* Constant Definitions::Defining symbolic constants that can be used in the
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md file.
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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* Iterators:: Using iterators to generate patterns from a template.
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1997-03-25 20:26:08 +01:00
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@end menu
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2000-12-04 18:23:34 +01:00
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@node Overview
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@section Overview of How the Machine Description is Used
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There are three main conversions that happen in the compiler:
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@enumerate
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@item
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The front end reads the source code and builds a parse tree.
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@item
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The parse tree is used to generate an RTL insn list based on named
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instruction patterns.
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@item
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The insn list is matched against the RTL templates to produce assembler
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code.
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@end enumerate
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For the generate pass, only the names of the insns matter, from either a
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named @code{define_insn} or a @code{define_expand}. The compiler will
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choose the pattern with the right name and apply the operands according
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to the documentation later in this chapter, without regard for the RTL
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template or operand constraints. Note that the names the compiler looks
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2001-06-11 22:52:30 +02:00
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for are hard-coded in the compiler---it will ignore unnamed patterns and
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2000-12-04 18:23:34 +01:00
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patterns with names it doesn't know about, but if you don't provide a
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named pattern it needs, it will abort.
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If a @code{define_insn} is used, the template given is inserted into the
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insn list. If a @code{define_expand} is used, one of three things
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happens, based on the condition logic. The condition logic may manually
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create new insns for the insn list, say via @code{emit_insn()}, and
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2001-07-03 02:46:05 +02:00
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invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
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2000-12-04 18:23:34 +01:00
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compiler to use an alternate way of performing that task. If it invokes
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neither @code{DONE} nor @code{FAIL}, the template given in the pattern
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is inserted, as if the @code{define_expand} were a @code{define_insn}.
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Once the insn list is generated, various optimization passes convert,
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replace, and rearrange the insns in the insn list. This is where the
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@code{define_split} and @code{define_peephole} patterns get used, for
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example.
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Finally, the insn list's RTL is matched up with the RTL templates in the
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@code{define_insn} patterns, and those patterns are used to emit the
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final assembly code. For this purpose, each named @code{define_insn}
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acts like it's unnamed, since the names are ignored.
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1997-03-25 20:26:08 +01:00
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@node Patterns
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@section Everything about Instruction Patterns
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@cindex patterns
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@cindex instruction patterns
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@findex define_insn
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Each instruction pattern contains an incomplete RTL expression, with pieces
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to be filled in later, operand constraints that restrict how the pieces can
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be filled in, and an output pattern or C code to generate the assembler
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output, all wrapped up in a @code{define_insn} expression.
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A @code{define_insn} is an RTL expression containing four or five operands:
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@enumerate
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@item
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An optional name. The presence of a name indicate that this instruction
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pattern can perform a certain standard job for the RTL-generation
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pass of the compiler. This pass knows certain names and will use
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the instruction patterns with those names, if the names are defined
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in the machine description.
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The absence of a name is indicated by writing an empty string
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where the name should go. Nameless instruction patterns are never
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used for generating RTL code, but they may permit several simpler insns
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to be combined later on.
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Names that are not thus known and used in RTL-generation have no
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effect; they are equivalent to no name at all.
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2000-03-03 13:29:42 +01:00
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For the purpose of debugging the compiler, you may also specify a
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name beginning with the @samp{*} character. Such a name is used only
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for identifying the instruction in RTL dumps; it is entirely equivalent
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to having a nameless pattern for all other purposes.
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1997-03-25 20:26:08 +01:00
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@item
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The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
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RTL expressions which show what the instruction should look like. It is
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incomplete because it may contain @code{match_operand},
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@code{match_operator}, and @code{match_dup} expressions that stand for
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operands of the instruction.
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If the vector has only one element, that element is the template for the
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instruction pattern. If the vector has multiple elements, then the
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instruction pattern is a @code{parallel} expression containing the
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elements described.
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@item
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@cindex pattern conditions
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@cindex conditions, in patterns
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A condition. This is a string which contains a C expression that is
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the final test to decide whether an insn body matches this pattern.
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@cindex named patterns and conditions
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For a named pattern, the condition (if present) may not depend on
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the data in the insn being matched, but only the target-machine-type
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flags. The compiler needs to test these conditions during
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initialization in order to learn exactly which named instructions are
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available in a particular run.
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@findex operands
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For nameless patterns, the condition is applied only when matching an
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individual insn, and only after the insn has matched the pattern's
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recognition template. The insn's operands may be found in the vector
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2002-05-30 03:05:05 +02:00
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@code{operands}. For an insn where the condition has once matched, it
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can't be used to control register allocation, for example by excluding
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certain hard registers or hard register combinations.
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1997-03-25 20:26:08 +01:00
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@item
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The @dfn{output template}: a string that says how to output matching
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insns as assembler code. @samp{%} in this string specifies where
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to substitute the value of an operand. @xref{Output Template}.
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When simple substitution isn't general enough, you can specify a piece
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of C code to compute the output. @xref{Output Statement}.
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@item
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Optionally, a vector containing the values of attributes for insns matching
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this pattern. @xref{Insn Attributes}.
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@end enumerate
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@node Example
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@section Example of @code{define_insn}
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@cindex @code{define_insn} example
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Here is an actual example of an instruction pattern, for the 68000/68020.
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c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
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@smallexample
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1997-03-25 20:26:08 +01:00
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(define_insn "tstsi"
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[(set (cc0)
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(match_operand:SI 0 "general_operand" "rm"))]
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""
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"*
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2002-02-23 13:59:09 +01:00
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@{
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i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
|
1997-03-25 20:26:08 +01:00
|
|
|
return \"tstl %0\";
|
2002-02-23 13:59:09 +01:00
|
|
|
return \"cmpl #0,%0\";
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
@}")
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
This can also be written using braced strings:
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
(define_insn "tstsi"
|
|
|
|
[(set (cc0)
|
|
|
|
(match_operand:SI 0 "general_operand" "rm"))]
|
|
|
|
""
|
2002-02-23 13:59:09 +01:00
|
|
|
@{
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
|
|
|
|
return "tstl %0";
|
2002-02-23 13:59:09 +01:00
|
|
|
return "cmpl #0,%0";
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
@})
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
This is an instruction that sets the condition codes based on the value of
|
|
|
|
a general operand. It has no condition, so any insn whose RTL description
|
|
|
|
has the form shown may be handled according to this pattern. The name
|
|
|
|
@samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
|
|
|
|
pass that, when it is necessary to test such a value, an insn to do so
|
|
|
|
can be constructed using this pattern.
|
|
|
|
|
|
|
|
The output control string is a piece of C code which chooses which
|
|
|
|
output template to return based on the kind of operand and the specific
|
|
|
|
type of CPU for which code is being generated.
|
|
|
|
|
|
|
|
@samp{"rm"} is an operand constraint. Its meaning is explained below.
|
|
|
|
|
|
|
|
@node RTL Template
|
|
|
|
@section RTL Template
|
|
|
|
@cindex RTL insn template
|
|
|
|
@cindex generating insns
|
|
|
|
@cindex insns, generating
|
|
|
|
@cindex recognizing insns
|
|
|
|
@cindex insns, recognizing
|
|
|
|
|
|
|
|
The RTL template is used to define which insns match the particular pattern
|
|
|
|
and how to find their operands. For named patterns, the RTL template also
|
|
|
|
says how to construct an insn from specified operands.
|
|
|
|
|
|
|
|
Construction involves substituting specified operands into a copy of the
|
|
|
|
template. Matching involves determining the values that serve as the
|
|
|
|
operands in the insn being matched. Both of these activities are
|
|
|
|
controlled by special expression types that direct matching and
|
|
|
|
substitution of the operands.
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@findex match_operand
|
|
|
|
@item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
|
|
|
|
This expression is a placeholder for operand number @var{n} of
|
|
|
|
the insn. When constructing an insn, operand number @var{n}
|
|
|
|
will be substituted at this point. When matching an insn, whatever
|
|
|
|
appears at this position in the insn will be taken as operand
|
|
|
|
number @var{n}; but it must satisfy @var{predicate} or this instruction
|
|
|
|
pattern will not match at all.
|
|
|
|
|
|
|
|
Operand numbers must be chosen consecutively counting from zero in
|
|
|
|
each instruction pattern. There may be only one @code{match_operand}
|
|
|
|
expression in the pattern for each operand number. Usually operands
|
|
|
|
are numbered in the order of appearance in @code{match_operand}
|
1997-11-20 14:53:42 +01:00
|
|
|
expressions. In the case of a @code{define_expand}, any operand numbers
|
|
|
|
used only in @code{match_dup} expressions have higher values than all
|
|
|
|
other operand numbers.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
@var{predicate} is a string that is the name of a function that
|
|
|
|
accepts two arguments, an expression and a machine mode.
|
|
|
|
@xref{Predicates}. During matching, the function will be called with
|
|
|
|
the putative operand as the expression and @var{m} as the mode
|
|
|
|
argument (if @var{m} is not specified, @code{VOIDmode} will be used,
|
|
|
|
which normally causes @var{predicate} to accept any mode). If it
|
|
|
|
returns zero, this instruction pattern fails to match.
|
|
|
|
@var{predicate} may be an empty string; then it means no test is to be
|
|
|
|
done on the operand, so anything which occurs in this position is
|
|
|
|
valid.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
Most of the time, @var{predicate} will reject modes other than @var{m}---but
|
|
|
|
not always. For example, the predicate @code{address_operand} uses
|
|
|
|
@var{m} as the mode of memory ref that the address should be valid for.
|
|
|
|
Many predicates accept @code{const_int} nodes even though their mode is
|
|
|
|
@code{VOIDmode}.
|
|
|
|
|
|
|
|
@var{constraint} controls reloading and the choice of the best register
|
|
|
|
class to use for a value, as explained later (@pxref{Constraints}).
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
If the constraint would be an empty string, it can be omitted.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
People are often unclear on the difference between the constraint and the
|
|
|
|
predicate. The predicate helps decide whether a given insn matches the
|
|
|
|
pattern. The constraint plays no role in this decision; instead, it
|
|
|
|
controls various decisions in the case of an insn which does match.
|
|
|
|
|
|
|
|
@findex match_scratch
|
|
|
|
@item (match_scratch:@var{m} @var{n} @var{constraint})
|
|
|
|
This expression is also a placeholder for operand number @var{n}
|
|
|
|
and indicates that operand must be a @code{scratch} or @code{reg}
|
|
|
|
expression.
|
|
|
|
|
|
|
|
When matching patterns, this is equivalent to
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
but, when generating RTL, it produces a (@code{scratch}:@var{m})
|
|
|
|
expression.
|
|
|
|
|
|
|
|
If the last few expressions in a @code{parallel} are @code{clobber}
|
|
|
|
expressions whose operands are either a hard register or
|
|
|
|
@code{match_scratch}, the combiner can add or delete them when
|
|
|
|
necessary. @xref{Side Effects}.
|
|
|
|
|
|
|
|
@findex match_dup
|
|
|
|
@item (match_dup @var{n})
|
|
|
|
This expression is also a placeholder for operand number @var{n}.
|
|
|
|
It is used when the operand needs to appear more than once in the
|
|
|
|
insn.
|
|
|
|
|
|
|
|
In construction, @code{match_dup} acts just like @code{match_operand}:
|
|
|
|
the operand is substituted into the insn being constructed. But in
|
|
|
|
matching, @code{match_dup} behaves differently. It assumes that operand
|
|
|
|
number @var{n} has already been determined by a @code{match_operand}
|
|
|
|
appearing earlier in the recognition template, and it matches only an
|
|
|
|
identical-looking expression.
|
|
|
|
|
2000-12-04 18:23:34 +01:00
|
|
|
Note that @code{match_dup} should not be used to tell the compiler that
|
|
|
|
a particular register is being used for two operands (example:
|
|
|
|
@code{add} that adds one register to another; the second register is
|
|
|
|
both an input operand and the output operand). Use a matching
|
|
|
|
constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
|
|
|
|
operand is used in two places in the template, such as an instruction
|
|
|
|
that computes both a quotient and a remainder, where the opcode takes
|
|
|
|
two input operands but the RTL template has to refer to each of those
|
|
|
|
twice; once for the quotient pattern and once for the remainder pattern.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@findex match_operator
|
|
|
|
@item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
|
|
|
|
This pattern is a kind of placeholder for a variable RTL expression
|
|
|
|
code.
|
|
|
|
|
|
|
|
When constructing an insn, it stands for an RTL expression whose
|
|
|
|
expression code is taken from that of operand @var{n}, and whose
|
|
|
|
operands are constructed from the patterns @var{operands}.
|
|
|
|
|
|
|
|
When matching an expression, it matches an expression if the function
|
|
|
|
@var{predicate} returns nonzero on that expression @emph{and} the
|
|
|
|
patterns @var{operands} match the operands of the expression.
|
|
|
|
|
|
|
|
Suppose that the function @code{commutative_operator} is defined as
|
|
|
|
follows, to match any expression whose operator is one of the
|
|
|
|
commutative arithmetic operators of RTL and whose mode is @var{mode}:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
int
|
alias.c (rtx_equal_for_memref_p): Use predicates to test rtx classes and new rtx class codes...
2004-02-07 Paolo Bonzini <bonzini@gnu.org>
* alias.c (rtx_equal_for_memref_p): Use predicates
to test rtx classes and new rtx class codes, possibly
splitting conditionals that tested against '<' and 'o'.
* caller-save.c (save_call_clobbered_regs): Likewise.
* combine.c (contains_muldiv, find_split_point, subst,
combine_simplify_rtx, simplify_if_then_else,
simplify_set, simplify_logical, expand_compound_operation,
make_compound_operation, if_then_else_cond, known_cond,
apply_distributive_law, cached_nonzero_bits,
cached_num_sign_bit_copies, simplify_shift_const,
gen_binary, simplify_comparison, update_table_tick,
record_value_for_reg, get_lsat_value_validate): Likewise.
* cse.c (mention_regs, find_best_addr, find_comparison_args,
fold_rtx, cse_insn, invalidate_memory, cse_basic_block):
Likewise.
* emit-rtl.c (copy_insn_1): Likewise.
* expr.c (force_operand): Likewise.
* final.c (final_scan_insn, get_mem_expr_from_op): Likewise.
* flow.c (notice_stack_pointer_modification_1,
invalidate_mems_from_autoinc, ior_reg_cond, not_reg_cond,
and_reg_cond, elim_reg_cond): Likewise.
* function.c (update_epilogue_consts): Likewise.
* genattrtab.c (attr_rtx_1): Likewise.
* genopinit.c (gen_insn): Likewise.
* integrate.c (subst_constants): Likewise.
* jump.c (reversed_comparison_code_parts,
reversed_comparison_code, delete_related_insns,
rtx_renumbered_equal_p): Likewise.
* local-alloc.c (block_alloc): Likewise.
* loop.c (rtx_equal_for_prefetch_p, maybe_eliminate_biv,
canonicalize_condition): Likewise.
* loop-iv.c (simplify_using_conditions, iv_number_of_iterations):
Likewise.
* optabs.c (add_equal_node, expand_binop): Likewise.
* predict.c (estimate_probability): Likewise.
* ra-debug.c (ra_print_rtx_2op, ra_print_rtx): Likewise.
* recog.c (validate_replace_rtx_1, comparison_operator,
offsettable_address_p, constrain_operands): Likewise.
* reg-stack.c (swap_rtx_condition_1, subst_stack_regs_pat):
Likewise.
* regclass.c (scan_one_insn): Likewise.
* regmove.c (stable_and_no_regs_but_for_p): Likewise.
* regrename.c (kill_autoinc_value): Likewise.
* reload.c (find_reusable_reload, find_reloads,
reg_overlap_mentioned_for_reload_p): Likewise.
* reload1.c (gen_reload, delete_address_reloads_1): Likewise.
* rtl.c (copy_rtx): Likewise.
* rtl.h (CONSTANT_P, INSN_P): Likewise.
* rtlanal.c (commutative_operand_precedence): Likewise.
* sched-deps.c (conditions_mutex_p): Likewise.
* sched-rgn.c (is_cfg_nonregular): Likewise.
* simplify-rtx.c (simplify_gen_binary,
simplify_gen_relational, simplify_replace_rtx,
simplify_unary_operation, simplify_binary_operation,
simplify_ternary_operation, simplify_rtx): Likewise.
* unroll.c (reg_dead_after_loop): Likewise.
* config/alpha/alpha.c (alpha_swapped_comparison_operator,
print_operand): Likewise.
* config/arc/arc.c (proper_comparison_operator): Likewise.
* config/arm/arm.c (arm_arm_address_cost, arm_select_cc_mode):
Likewise.
* config/avr/avr.c (_reg_unused_after): Likewise.
* config/frv/frv.c (frv_ifcvt_modify_tests,
frv_ifcvt_modify_insn, frv_pack_insn): Likewise.
* config/i386/i386.c (ix86_comparison_operator,
ix86_carry_flag_operator, fcmov_comparison_operator,
arith_or_logical_operator, print_operand,
ix86_expand_binary_operator, ix86_binary_operator_ok):
Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (not_postinc_memory_operand,
ia64_print_operand, update_set_flags, errata_emit_nops):
Likewise.
* config/ia64/ia64.h (PREFERRED_RELOAD_CLASS,
CONSTRAINT_OK_FOR_S): Likewise.
* config/ip2k/ip2k.c (mdr_resequence_xy_yx,
mdr_try_move_dp_reload, ip2k_check_can_adjust_stack_ref,
ip2k_xexp_not_uses_reg_for_mem, ip2k_xexp_not_uses_reg_p,
ip2k_composite_xexp_not_uses_reg_p, ip2k_unary_operator):
Likewise.
* config/iq2000/iq2000.c (cmp_op, symbolic_expression_p,
eqne_comparison_operator, signed_comparison_operator):
Likewise.
* config/mips/mips.c (cmp_op, symbolic_expression_p):
Likewise.
* config/mmix/mmix (mmix_foldable_comparison_operator,
mmix_comparison_operator): Likewise.
* config/pa/pa.c (hppa_legitimize_address): Likewise.
* config/rs6000/rs6000.c (stmw_operation,
branch_comparison_operator, trap_comparison_operator,
ccr_bit): Likewise.
* config/rs6000/rs6000.h (SELECT_CC_MODE): Likewise.
* config/s390/s390.c (s390_alc_comparison,
s390_slb_comparison):L Likewise.
* config/sh/sh.c (gen_block_redirect, reg_unused_after):
Likewise.
* config/sparc/sparc.c (eq_or_neq, normal_comp_operator,
noov_compare_op, noov_compare64_op, v9_regcmp_op,
emit_hard_tfmode_operation, reg_unused_after)
* doc/md.texi, doc/rtl.texi: Likewise.
* ra-debug.c: Add 2004 to list of copyright years.
* unroll.c: Likewise.
* combine.c (simplify_logical): Remove dummy test,
(apply_distributive_law): Fix typo in comment.
GET_CODE (x) == AND so x is a commutative binary op.
* jump.c (delete_related_insns): simplify loop
condition, move testing of RTX codes inside the loop.
(rtx_renumbered_equal_p): do not use RTX_CODE.
* rtl.c (rtx_class): Declare as enum rtx_class.
* rtl.def (EQ, NE, UNEQ, LTGT, UNORDERED, ORDERED):
Move to RTX_COMM_COMPARE class.
(HIGH, SYMBOL_REF, LABEL_REF, CONST, CONST_INT, CONST_DOUBLE):
Move to RTX_CONST_OBJ class.
* rtl.h (enum rtx_class): New declaration,
(RTX_OBJ_MASK, RTX_OBJ_RESULT, RTX_COMPARE_MASK,
RTX_COMPARE_RESULT, RTX_ARITHMETIC_MASK, RTX_ARITHMETIC_RESULT,
RTX_BINARY_MASK, RTX_BINARY_RESULT, RTX_COMMUTATIVE_MASK,
RTX_COMMUTATIVE_RESULT, RTX_NON_COMMUTATIVE_RESULT,
RTX_EXPR_FIRST, RTX_EXPR_LAST, UNARY_P, BINARY_P,
ARITHMETIC_P, COMMUTATIVE_ARITHMETIC_P, COMPARISON_P,
SWAPPABLE_OPERANDS_P, NON_COMMUTATIVE_P, COMMUTATIVE_P,
OBJECT_P): New macros.
* config/sparc/sparc.c (noov_compare_op): Remove register
from parameter.
From-SVN: r78824
2004-03-03 09:35:33 +01:00
|
|
|
commutative_integer_operator (x, mode)
|
1997-03-25 20:26:08 +01:00
|
|
|
rtx x;
|
|
|
|
enum machine_mode mode;
|
|
|
|
@{
|
|
|
|
enum rtx_code code = GET_CODE (x);
|
|
|
|
if (GET_MODE (x) != mode)
|
|
|
|
return 0;
|
alias.c (rtx_equal_for_memref_p): Use predicates to test rtx classes and new rtx class codes...
2004-02-07 Paolo Bonzini <bonzini@gnu.org>
* alias.c (rtx_equal_for_memref_p): Use predicates
to test rtx classes and new rtx class codes, possibly
splitting conditionals that tested against '<' and 'o'.
* caller-save.c (save_call_clobbered_regs): Likewise.
* combine.c (contains_muldiv, find_split_point, subst,
combine_simplify_rtx, simplify_if_then_else,
simplify_set, simplify_logical, expand_compound_operation,
make_compound_operation, if_then_else_cond, known_cond,
apply_distributive_law, cached_nonzero_bits,
cached_num_sign_bit_copies, simplify_shift_const,
gen_binary, simplify_comparison, update_table_tick,
record_value_for_reg, get_lsat_value_validate): Likewise.
* cse.c (mention_regs, find_best_addr, find_comparison_args,
fold_rtx, cse_insn, invalidate_memory, cse_basic_block):
Likewise.
* emit-rtl.c (copy_insn_1): Likewise.
* expr.c (force_operand): Likewise.
* final.c (final_scan_insn, get_mem_expr_from_op): Likewise.
* flow.c (notice_stack_pointer_modification_1,
invalidate_mems_from_autoinc, ior_reg_cond, not_reg_cond,
and_reg_cond, elim_reg_cond): Likewise.
* function.c (update_epilogue_consts): Likewise.
* genattrtab.c (attr_rtx_1): Likewise.
* genopinit.c (gen_insn): Likewise.
* integrate.c (subst_constants): Likewise.
* jump.c (reversed_comparison_code_parts,
reversed_comparison_code, delete_related_insns,
rtx_renumbered_equal_p): Likewise.
* local-alloc.c (block_alloc): Likewise.
* loop.c (rtx_equal_for_prefetch_p, maybe_eliminate_biv,
canonicalize_condition): Likewise.
* loop-iv.c (simplify_using_conditions, iv_number_of_iterations):
Likewise.
* optabs.c (add_equal_node, expand_binop): Likewise.
* predict.c (estimate_probability): Likewise.
* ra-debug.c (ra_print_rtx_2op, ra_print_rtx): Likewise.
* recog.c (validate_replace_rtx_1, comparison_operator,
offsettable_address_p, constrain_operands): Likewise.
* reg-stack.c (swap_rtx_condition_1, subst_stack_regs_pat):
Likewise.
* regclass.c (scan_one_insn): Likewise.
* regmove.c (stable_and_no_regs_but_for_p): Likewise.
* regrename.c (kill_autoinc_value): Likewise.
* reload.c (find_reusable_reload, find_reloads,
reg_overlap_mentioned_for_reload_p): Likewise.
* reload1.c (gen_reload, delete_address_reloads_1): Likewise.
* rtl.c (copy_rtx): Likewise.
* rtl.h (CONSTANT_P, INSN_P): Likewise.
* rtlanal.c (commutative_operand_precedence): Likewise.
* sched-deps.c (conditions_mutex_p): Likewise.
* sched-rgn.c (is_cfg_nonregular): Likewise.
* simplify-rtx.c (simplify_gen_binary,
simplify_gen_relational, simplify_replace_rtx,
simplify_unary_operation, simplify_binary_operation,
simplify_ternary_operation, simplify_rtx): Likewise.
* unroll.c (reg_dead_after_loop): Likewise.
* config/alpha/alpha.c (alpha_swapped_comparison_operator,
print_operand): Likewise.
* config/arc/arc.c (proper_comparison_operator): Likewise.
* config/arm/arm.c (arm_arm_address_cost, arm_select_cc_mode):
Likewise.
* config/avr/avr.c (_reg_unused_after): Likewise.
* config/frv/frv.c (frv_ifcvt_modify_tests,
frv_ifcvt_modify_insn, frv_pack_insn): Likewise.
* config/i386/i386.c (ix86_comparison_operator,
ix86_carry_flag_operator, fcmov_comparison_operator,
arith_or_logical_operator, print_operand,
ix86_expand_binary_operator, ix86_binary_operator_ok):
Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (not_postinc_memory_operand,
ia64_print_operand, update_set_flags, errata_emit_nops):
Likewise.
* config/ia64/ia64.h (PREFERRED_RELOAD_CLASS,
CONSTRAINT_OK_FOR_S): Likewise.
* config/ip2k/ip2k.c (mdr_resequence_xy_yx,
mdr_try_move_dp_reload, ip2k_check_can_adjust_stack_ref,
ip2k_xexp_not_uses_reg_for_mem, ip2k_xexp_not_uses_reg_p,
ip2k_composite_xexp_not_uses_reg_p, ip2k_unary_operator):
Likewise.
* config/iq2000/iq2000.c (cmp_op, symbolic_expression_p,
eqne_comparison_operator, signed_comparison_operator):
Likewise.
* config/mips/mips.c (cmp_op, symbolic_expression_p):
Likewise.
* config/mmix/mmix (mmix_foldable_comparison_operator,
mmix_comparison_operator): Likewise.
* config/pa/pa.c (hppa_legitimize_address): Likewise.
* config/rs6000/rs6000.c (stmw_operation,
branch_comparison_operator, trap_comparison_operator,
ccr_bit): Likewise.
* config/rs6000/rs6000.h (SELECT_CC_MODE): Likewise.
* config/s390/s390.c (s390_alc_comparison,
s390_slb_comparison):L Likewise.
* config/sh/sh.c (gen_block_redirect, reg_unused_after):
Likewise.
* config/sparc/sparc.c (eq_or_neq, normal_comp_operator,
noov_compare_op, noov_compare64_op, v9_regcmp_op,
emit_hard_tfmode_operation, reg_unused_after)
* doc/md.texi, doc/rtl.texi: Likewise.
* ra-debug.c: Add 2004 to list of copyright years.
* unroll.c: Likewise.
* combine.c (simplify_logical): Remove dummy test,
(apply_distributive_law): Fix typo in comment.
GET_CODE (x) == AND so x is a commutative binary op.
* jump.c (delete_related_insns): simplify loop
condition, move testing of RTX codes inside the loop.
(rtx_renumbered_equal_p): do not use RTX_CODE.
* rtl.c (rtx_class): Declare as enum rtx_class.
* rtl.def (EQ, NE, UNEQ, LTGT, UNORDERED, ORDERED):
Move to RTX_COMM_COMPARE class.
(HIGH, SYMBOL_REF, LABEL_REF, CONST, CONST_INT, CONST_DOUBLE):
Move to RTX_CONST_OBJ class.
* rtl.h (enum rtx_class): New declaration,
(RTX_OBJ_MASK, RTX_OBJ_RESULT, RTX_COMPARE_MASK,
RTX_COMPARE_RESULT, RTX_ARITHMETIC_MASK, RTX_ARITHMETIC_RESULT,
RTX_BINARY_MASK, RTX_BINARY_RESULT, RTX_COMMUTATIVE_MASK,
RTX_COMMUTATIVE_RESULT, RTX_NON_COMMUTATIVE_RESULT,
RTX_EXPR_FIRST, RTX_EXPR_LAST, UNARY_P, BINARY_P,
ARITHMETIC_P, COMMUTATIVE_ARITHMETIC_P, COMPARISON_P,
SWAPPABLE_OPERANDS_P, NON_COMMUTATIVE_P, COMMUTATIVE_P,
OBJECT_P): New macros.
* config/sparc/sparc.c (noov_compare_op): Remove register
from parameter.
From-SVN: r78824
2004-03-03 09:35:33 +01:00
|
|
|
return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
|
1997-03-25 20:26:08 +01:00
|
|
|
|| code == EQ || code == NE);
|
|
|
|
@}
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Then the following pattern will match any RTL expression consisting
|
|
|
|
of a commutative operator applied to two general operands:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(match_operator:SI 3 "commutative_operator"
|
|
|
|
[(match_operand:SI 1 "general_operand" "g")
|
|
|
|
(match_operand:SI 2 "general_operand" "g")])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Here the vector @code{[@var{operands}@dots{}]} contains two patterns
|
|
|
|
because the expressions to be matched all contain two operands.
|
|
|
|
|
|
|
|
When this pattern does match, the two operands of the commutative
|
|
|
|
operator are recorded as operands 1 and 2 of the insn. (This is done
|
|
|
|
by the two instances of @code{match_operand}.) Operand 3 of the insn
|
|
|
|
will be the entire commutative expression: use @code{GET_CODE
|
|
|
|
(operands[3])} to see which commutative operator was used.
|
|
|
|
|
|
|
|
The machine mode @var{m} of @code{match_operator} works like that of
|
|
|
|
@code{match_operand}: it is passed as the second argument to the
|
|
|
|
predicate function, and that function is solely responsible for
|
|
|
|
deciding whether the expression to be matched ``has'' that mode.
|
|
|
|
|
|
|
|
When constructing an insn, argument 3 of the gen-function will specify
|
2001-06-27 02:04:39 +02:00
|
|
|
the operation (i.e.@: the expression code) for the expression to be
|
1997-03-25 20:26:08 +01:00
|
|
|
made. It should be an RTL expression, whose expression code is copied
|
|
|
|
into a new expression whose operands are arguments 1 and 2 of the
|
|
|
|
gen-function. The subexpressions of argument 3 are not used;
|
|
|
|
only its expression code matters.
|
|
|
|
|
|
|
|
When @code{match_operator} is used in a pattern for matching an insn,
|
|
|
|
it usually best if the operand number of the @code{match_operator}
|
|
|
|
is higher than that of the actual operands of the insn. This improves
|
|
|
|
register allocation because the register allocator often looks at
|
|
|
|
operands 1 and 2 of insns to see if it can do register tying.
|
|
|
|
|
|
|
|
There is no way to specify constraints in @code{match_operator}. The
|
|
|
|
operand of the insn which corresponds to the @code{match_operator}
|
|
|
|
never has any constraints because it is never reloaded as a whole.
|
|
|
|
However, if parts of its @var{operands} are matched by
|
|
|
|
@code{match_operand} patterns, those parts may have constraints of
|
|
|
|
their own.
|
|
|
|
|
|
|
|
@findex match_op_dup
|
|
|
|
@item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
|
|
|
|
Like @code{match_dup}, except that it applies to operators instead of
|
|
|
|
operands. When constructing an insn, operand number @var{n} will be
|
|
|
|
substituted at this point. But in matching, @code{match_op_dup} behaves
|
|
|
|
differently. It assumes that operand number @var{n} has already been
|
|
|
|
determined by a @code{match_operator} appearing earlier in the
|
|
|
|
recognition template, and it matches only an identical-looking
|
|
|
|
expression.
|
|
|
|
|
|
|
|
@findex match_parallel
|
|
|
|
@item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
|
|
|
|
This pattern is a placeholder for an insn that consists of a
|
|
|
|
@code{parallel} expression with a variable number of elements. This
|
|
|
|
expression should only appear at the top level of an insn pattern.
|
|
|
|
|
|
|
|
When constructing an insn, operand number @var{n} will be substituted at
|
|
|
|
this point. When matching an insn, it matches if the body of the insn
|
|
|
|
is a @code{parallel} expression with at least as many elements as the
|
|
|
|
vector of @var{subpat} expressions in the @code{match_parallel}, if each
|
|
|
|
@var{subpat} matches the corresponding element of the @code{parallel},
|
|
|
|
@emph{and} the function @var{predicate} returns nonzero on the
|
|
|
|
@code{parallel} that is the body of the insn. It is the responsibility
|
|
|
|
of the predicate to validate elements of the @code{parallel} beyond
|
2001-06-25 01:04:49 +02:00
|
|
|
those listed in the @code{match_parallel}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
A typical use of @code{match_parallel} is to match load and store
|
|
|
|
multiple expressions, which can contain a variable number of elements
|
|
|
|
in a @code{parallel}. For example,
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(match_parallel 0 "load_multiple_operation"
|
|
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
|
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
|
|
|
(use (reg:SI 179))
|
|
|
|
(clobber (reg:SI 179))])]
|
|
|
|
""
|
|
|
|
"loadm 0,0,%1,%2")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
This example comes from @file{a29k.md}. The function
|
2001-08-18 23:02:44 +02:00
|
|
|
@code{load_multiple_operation} is defined in @file{a29k.c} and checks
|
1997-03-25 20:26:08 +01:00
|
|
|
that subsequent elements in the @code{parallel} are the same as the
|
|
|
|
@code{set} in the pattern, except that they are referencing subsequent
|
|
|
|
registers and memory locations.
|
|
|
|
|
|
|
|
An insn that matches this pattern might look like:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(parallel
|
|
|
|
[(set (reg:SI 20) (mem:SI (reg:SI 100)))
|
|
|
|
(use (reg:SI 179))
|
|
|
|
(clobber (reg:SI 179))
|
|
|
|
(set (reg:SI 21)
|
|
|
|
(mem:SI (plus:SI (reg:SI 100)
|
|
|
|
(const_int 4))))
|
|
|
|
(set (reg:SI 22)
|
|
|
|
(mem:SI (plus:SI (reg:SI 100)
|
|
|
|
(const_int 8))))])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@findex match_par_dup
|
|
|
|
@item (match_par_dup @var{n} [@var{subpat}@dots{}])
|
|
|
|
Like @code{match_op_dup}, but for @code{match_parallel} instead of
|
|
|
|
@code{match_operator}.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@node Output Template
|
|
|
|
@section Output Templates and Operand Substitution
|
|
|
|
@cindex output templates
|
|
|
|
@cindex operand substitution
|
|
|
|
|
|
|
|
@cindex @samp{%} in template
|
|
|
|
@cindex percent sign
|
|
|
|
The @dfn{output template} is a string which specifies how to output the
|
|
|
|
assembler code for an instruction pattern. Most of the template is a
|
|
|
|
fixed string which is output literally. The character @samp{%} is used
|
|
|
|
to specify where to substitute an operand; it can also be used to
|
|
|
|
identify places where different variants of the assembler require
|
|
|
|
different syntax.
|
|
|
|
|
|
|
|
In the simplest case, a @samp{%} followed by a digit @var{n} says to output
|
|
|
|
operand @var{n} at that point in the string.
|
|
|
|
|
|
|
|
@samp{%} followed by a letter and a digit says to output an operand in an
|
|
|
|
alternate fashion. Four letters have standard, built-in meanings described
|
|
|
|
below. The machine description macro @code{PRINT_OPERAND} can define
|
|
|
|
additional letters with nonstandard meanings.
|
|
|
|
|
|
|
|
@samp{%c@var{digit}} can be used to substitute an operand that is a
|
|
|
|
constant value without the syntax that normally indicates an immediate
|
|
|
|
operand.
|
|
|
|
|
|
|
|
@samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
|
|
|
|
the constant is negated before printing.
|
|
|
|
|
|
|
|
@samp{%a@var{digit}} can be used to substitute an operand as if it were a
|
|
|
|
memory reference, with the actual operand treated as the address. This may
|
|
|
|
be useful when outputting a ``load address'' instruction, because often the
|
|
|
|
assembler syntax for such an instruction requires you to write the operand
|
|
|
|
as if it were a memory reference.
|
|
|
|
|
|
|
|
@samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
|
|
|
|
instruction.
|
|
|
|
|
|
|
|
@samp{%=} outputs a number which is unique to each instruction in the
|
|
|
|
entire compilation. This is useful for making local labels to be
|
|
|
|
referred to more than once in a single template that generates multiple
|
|
|
|
assembler instructions.
|
|
|
|
|
|
|
|
@samp{%} followed by a punctuation character specifies a substitution that
|
|
|
|
does not use an operand. Only one case is standard: @samp{%%} outputs a
|
|
|
|
@samp{%} into the assembler code. Other nonstandard cases can be
|
|
|
|
defined in the @code{PRINT_OPERAND} macro. You must also define
|
|
|
|
which punctuation characters are valid with the
|
|
|
|
@code{PRINT_OPERAND_PUNCT_VALID_P} macro.
|
|
|
|
|
|
|
|
@cindex \
|
|
|
|
@cindex backslash
|
|
|
|
The template may generate multiple assembler instructions. Write the text
|
|
|
|
for the instructions, with @samp{\;} between them.
|
|
|
|
|
|
|
|
@cindex matching operands
|
|
|
|
When the RTL contains two operands which are required by constraint to match
|
|
|
|
each other, the output template must refer only to the lower-numbered operand.
|
|
|
|
Matching operands are not always identical, and the rest of the compiler
|
|
|
|
arranges to put the proper RTL expression for printing into the lower-numbered
|
|
|
|
operand.
|
|
|
|
|
|
|
|
One use of nonstandard letters or punctuation following @samp{%} is to
|
|
|
|
distinguish between different assembler languages for the same machine; for
|
|
|
|
example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
|
|
|
|
requires periods in most opcode names, while MIT syntax does not. For
|
|
|
|
example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
|
|
|
|
syntax. The same file of patterns is used for both kinds of output syntax,
|
|
|
|
but the character sequence @samp{%.} is used in each place where Motorola
|
|
|
|
syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
|
|
|
|
defines the sequence to output a period; the macro for MIT syntax defines
|
|
|
|
it to do nothing.
|
|
|
|
|
|
|
|
@cindex @code{#} in template
|
|
|
|
As a special case, a template consisting of the single character @code{#}
|
|
|
|
instructs the compiler to first split the insn, and then output the
|
|
|
|
resulting instructions separately. This helps eliminate redundancy in the
|
|
|
|
output templates. If you have a @code{define_insn} that needs to emit
|
|
|
|
multiple assembler instructions, and there is an matching @code{define_split}
|
|
|
|
already defined, then you can simply use @code{#} as the output template
|
|
|
|
instead of writing an output template that emits the multiple assembler
|
|
|
|
instructions.
|
|
|
|
|
|
|
|
If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
|
|
|
|
of the form @samp{@{option0|option1|option2@}} in the templates. These
|
|
|
|
describe multiple variants of assembler language syntax.
|
|
|
|
@xref{Instruction Output}.
|
|
|
|
|
|
|
|
@node Output Statement
|
|
|
|
@section C Statements for Assembler Output
|
|
|
|
@cindex output statements
|
|
|
|
@cindex C statements for assembler output
|
|
|
|
@cindex generating assembler output
|
|
|
|
|
|
|
|
Often a single fixed template string cannot produce correct and efficient
|
|
|
|
assembler code for all the cases that are recognized by a single
|
|
|
|
instruction pattern. For example, the opcodes may depend on the kinds of
|
|
|
|
operands; or some unfortunate combinations of operands may require extra
|
|
|
|
machine instructions.
|
|
|
|
|
|
|
|
If the output control string starts with a @samp{@@}, then it is actually
|
|
|
|
a series of templates, each on a separate line. (Blank lines and
|
|
|
|
leading spaces and tabs are ignored.) The templates correspond to the
|
|
|
|
pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
|
|
|
|
if a target machine has a two-address add instruction @samp{addr} to add
|
|
|
|
into a register and another @samp{addm} to add a register to memory, you
|
|
|
|
might write this pattern:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "addsi3"
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
|
|
|
(plus:SI (match_operand:SI 1 "general_operand" "0,0")
|
|
|
|
(match_operand:SI 2 "general_operand" "g,r")))]
|
|
|
|
""
|
|
|
|
"@@
|
|
|
|
addr %2,%0
|
|
|
|
addm %2,%0")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@cindex @code{*} in template
|
|
|
|
@cindex asterisk in template
|
|
|
|
If the output control string starts with a @samp{*}, then it is not an
|
|
|
|
output template but rather a piece of C program that should compute a
|
|
|
|
template. It should execute a @code{return} statement to return the
|
|
|
|
template-string you want. Most such templates use C string literals, which
|
|
|
|
require doublequote characters to delimit them. To include these
|
|
|
|
doublequote characters in the string, prefix each one with @samp{\}.
|
|
|
|
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
If the output control string is written as a brace block instead of a
|
|
|
|
double-quoted string, it is automatically assumed to be C code. In that
|
|
|
|
case, it is not necessary to put in a leading asterisk, or to escape the
|
|
|
|
doublequotes surrounding C string literals.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
The operands may be found in the array @code{operands}, whose C data type
|
|
|
|
is @code{rtx []}.
|
|
|
|
|
|
|
|
It is very common to select different ways of generating assembler code
|
|
|
|
based on whether an immediate operand is within a certain range. Be
|
|
|
|
careful when doing this, because the result of @code{INTVAL} is an
|
|
|
|
integer on the host machine. If the host machine has more bits in an
|
|
|
|
@code{int} than the target machine has in the mode in which the constant
|
|
|
|
will be used, then some of the bits you get from @code{INTVAL} will be
|
|
|
|
superfluous. For proper results, you must carefully disregard the
|
|
|
|
values of those bits.
|
|
|
|
|
|
|
|
@findex output_asm_insn
|
|
|
|
It is possible to output an assembler instruction and then go on to output
|
|
|
|
or compute more of them, using the subroutine @code{output_asm_insn}. This
|
|
|
|
receives two arguments: a template-string and a vector of operands. The
|
|
|
|
vector may be @code{operands}, or it may be another array of @code{rtx}
|
|
|
|
that you declare locally and initialize yourself.
|
|
|
|
|
|
|
|
@findex which_alternative
|
|
|
|
When an insn pattern has multiple alternatives in its constraints, often
|
|
|
|
the appearance of the assembler code is determined mostly by which alternative
|
|
|
|
was matched. When this is so, the C code can test the variable
|
|
|
|
@code{which_alternative}, which is the ordinal number of the alternative
|
|
|
|
that was actually satisfied (0 for the first, 1 for the second alternative,
|
|
|
|
etc.).
|
|
|
|
|
|
|
|
For example, suppose there are two opcodes for storing zero, @samp{clrreg}
|
|
|
|
for registers and @samp{clrmem} for memory locations. Here is how
|
|
|
|
a pattern could use @code{which_alternative} to choose between them:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
|
|
|
(const_int 0))]
|
|
|
|
""
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
@{
|
1997-03-25 20:26:08 +01:00
|
|
|
return (which_alternative == 0
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
? "clrreg %0" : "clrmem %0");
|
|
|
|
@})
|
1997-03-25 20:26:08 +01:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The example above, where the assembler code to generate was
|
|
|
|
@emph{solely} determined by the alternative, could also have been specified
|
|
|
|
as follows, having the output control string start with a @samp{@@}:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
|
|
|
(const_int 0))]
|
|
|
|
""
|
|
|
|
"@@
|
|
|
|
clrreg %0
|
|
|
|
clrmem %0")
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
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@node Predicates
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@section Predicates
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@cindex predicates
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@cindex operand predicates
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@cindex operator predicates
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A predicate determines whether a @code{match_operand} or
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@code{match_operator} expression matches, and therefore whether the
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surrounding instruction pattern will be used for that combination of
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operands. GCC has a number of machine-independent predicates, and you
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can define machine-specific predicates as needed. By convention,
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predicates used with @code{match_operand} have names that end in
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@samp{_operand}, and those used with @code{match_operator} have names
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that end in @samp{_operator}.
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All predicates are Boolean functions (in the mathematical sense) of
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two arguments: the RTL expression that is being considered at that
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position in the instruction pattern, and the machine mode that the
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@code{match_operand} or @code{match_operator} specifies. In this
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section, the first argument is called @var{op} and the second argument
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@var{mode}. Predicates can be called from C as ordinary two-argument
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functions; this can be useful in output templates or other
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machine-specific code.
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Operand predicates can allow operands that are not actually acceptable
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to the hardware, as long as the constraints give reload the ability to
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fix them up (@pxref{Constraints}). However, GCC will usually generate
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better code if the predicates specify the requirements of the machine
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instructions as closely as possible. Reload cannot fix up operands
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that must be constants (``immediate operands''); you must use a
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predicate that allows only constants, or else enforce the requirement
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in the extra condition.
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@cindex predicates and machine modes
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@cindex normal predicates
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@cindex special predicates
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Most predicates handle their @var{mode} argument in a uniform manner.
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If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
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any mode. If @var{mode} is anything else, then @var{op} must have the
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same mode, unless @var{op} is a @code{CONST_INT} or integer
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@code{CONST_DOUBLE}. These RTL expressions always have
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@code{VOIDmode}, so it would be counterproductive to check that their
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mode matches. Instead, predicates that accept @code{CONST_INT} and/or
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integer @code{CONST_DOUBLE} check that the value stored in the
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constant will fit in the requested mode.
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Predicates with this behavior are called @dfn{normal}.
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@command{genrecog} can optimize the instruction recognizer based on
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knowledge of how normal predicates treat modes. It can also diagnose
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certain kinds of common errors in the use of normal predicates; for
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instance, it is almost always an error to use a normal predicate
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without specifying a mode.
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Predicates that do something different with their @var{mode} argument
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are called @dfn{special}. The generic predicates
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@code{address_operand} and @code{pmode_register_operand} are special
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predicates. @command{genrecog} does not do any optimizations or
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diagnosis when special predicates are used.
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@menu
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* Machine-Independent Predicates:: Predicates available to all back ends.
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* Defining Predicates:: How to write machine-specific predicate
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functions.
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@end menu
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@node Machine-Independent Predicates
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@subsection Machine-Independent Predicates
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@cindex machine-independent predicates
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@cindex generic predicates
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These are the generic predicates available to all back ends. They are
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defined in @file{recog.c}. The first category of predicates allow
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only constant, or @dfn{immediate}, operands.
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@defun immediate_operand
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This predicate allows any sort of constant that fits in @var{mode}.
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It is an appropriate choice for instructions that take operands that
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must be constant.
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@end defun
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@defun const_int_operand
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This predicate allows any @code{CONST_INT} expression that fits in
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@var{mode}. It is an appropriate choice for an immediate operand that
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does not allow a symbol or label.
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@end defun
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@defun const_double_operand
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This predicate accepts any @code{CONST_DOUBLE} expression that has
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exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
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accept @code{CONST_INT}. It is intended for immediate floating point
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constants.
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@end defun
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@noindent
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The second category of predicates allow only some kind of machine
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register.
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@defun register_operand
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This predicate allows any @code{REG} or @code{SUBREG} expression that
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is valid for @var{mode}. It is often suitable for arithmetic
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instruction operands on a RISC machine.
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@end defun
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@defun pmode_register_operand
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This is a slight variant on @code{register_operand} which works around
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a limitation in the machine-description reader.
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2004-09-17 15:57:03 +02:00
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@smallexample
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
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(match_operand @var{n} "pmode_register_operand" @var{constraint})
|
2004-09-17 15:57:03 +02:00
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@end smallexample
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
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|
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|
|
@noindent
|
|
|
|
means exactly what
|
|
|
|
|
2004-09-17 15:57:03 +02:00
|
|
|
@smallexample
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
(match_operand:P @var{n} "register_operand" @var{constraint})
|
2004-09-17 15:57:03 +02:00
|
|
|
@end smallexample
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
would mean, if the machine-description reader accepted @samp{:P}
|
|
|
|
mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
|
|
|
|
alias for some other mode, and might vary with machine-specific
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
options. @xref{Misc}.
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
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|
@end defun
|
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|
@defun scratch_operand
|
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|
|
This predicate allows hard registers and @code{SCRATCH} expressions,
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|
but not pseudo-registers. It is used internally by @code{match_scratch};
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|
it should not be used directly.
|
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|
|
@end defun
|
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@noindent
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|
The third category of predicates allow only some kind of memory reference.
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|
@defun memory_operand
|
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|
This predicate allows any valid reference to a quantity of mode
|
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|
|
@var{mode} in memory, as determined by the weak form of
|
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|
|
@code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
|
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|
|
@end defun
|
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@defun address_operand
|
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|
|
This predicate is a little unusual; it allows any operand that is a
|
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|
valid expression for the @emph{address} of a quantity of mode
|
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|
|
@var{mode}, again determined by the weak form of
|
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|
@code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
|
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|
@samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
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|
@code{memory_operand}, then @var{exp} is acceptable to
|
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|
|
@code{address_operand}. Note that @var{exp} does not necessarily have
|
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|
the mode @var{mode}.
|
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|
|
@end defun
|
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@defun indirect_operand
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|
This is a stricter form of @code{memory_operand} which allows only
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|
memory references with a @code{general_operand} as the address
|
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|
|
expression. New uses of this predicate are discouraged, because
|
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@code{general_operand} is very permissive, so it's hard to tell what
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|
an @code{indirect_operand} does or does not allow. If a target has
|
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|
different requirements for memory operands for different instructions,
|
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|
it is better to define target-specific predicates which enforce the
|
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|
hardware's requirements explicitly.
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@end defun
|
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@defun push_operand
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This predicate allows a memory reference suitable for pushing a value
|
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|
onto the stack. This will be a @code{MEM} which refers to
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@code{stack_pointer_rtx}, with a side-effect in its address expression
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|
(@pxref{Incdec}); which one is determined by the
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@code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
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|
@end defun
|
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@defun pop_operand
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|
This predicate allows a memory reference suitable for popping a value
|
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|
off the stack. Again, this will be a @code{MEM} referring to
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|
@code{stack_pointer_rtx}, with a side-effect in its address
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|
|
expression. However, this time @code{STACK_POP_CODE} is expected.
|
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|
@end defun
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@noindent
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|
The fourth category of predicates allow some combination of the above
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|
operands.
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@defun nonmemory_operand
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|
This predicate allows any immediate or register operand valid for @var{mode}.
|
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@end defun
|
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@defun nonimmediate_operand
|
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This predicate allows any register or memory operand valid for @var{mode}.
|
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|
@end defun
|
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@defun general_operand
|
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|
This predicate allows any immediate, register, or memory operand
|
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|
valid for @var{mode}.
|
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|
@end defun
|
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|
@noindent
|
|
|
|
Finally, there is one generic operator predicate.
|
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|
|
|
|
|
|
@defun comparison_operator
|
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|
This predicate matches any expression which performs an arithmetic
|
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|
|
comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
|
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|
|
expression code.
|
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|
|
@end defun
|
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@node Defining Predicates
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@subsection Defining Machine-Specific Predicates
|
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@cindex defining predicates
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@findex define_predicate
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@findex define_special_predicate
|
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|
|
|
|
Many machines have requirements for their operands that cannot be
|
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|
expressed precisely using the generic predicates. You can define
|
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|
|
additional predicates using @code{define_predicate} and
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@code{define_special_predicate} expressions. These expressions have
|
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three operands:
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@itemize @bullet
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@item
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|
The name of the predicate, as it will be referred to in
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@code{match_operand} or @code{match_operator} expressions.
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@item
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An RTL expression which evaluates to true if the predicate allows the
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|
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operand @var{op}, false if it does not. This expression can only use
|
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the following RTL codes:
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@table @code
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@item MATCH_OPERAND
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|
When written inside a predicate expression, a @code{MATCH_OPERAND}
|
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|
|
expression evaluates to true if the predicate it names would allow
|
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|
|
@var{op}. The operand number and constraint are ignored. Due to
|
|
|
|
limitations in @command{genrecog}, you can only refer to generic
|
|
|
|
predicates and predicates that have already been defined.
|
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|
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|
|
@item MATCH_CODE
|
2006-01-23 16:16:19 +01:00
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|
This expression evaluates to true if @var{op} or a specified
|
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|
|
subexpression of @var{op} has one of a given list of RTX codes.
|
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|
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The first operand of this expression is a string constant containing a
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|
comma-separated list of RTX code names (in lower case). These are the
|
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|
|
codes for which the @code{MATCH_CODE} will be true.
|
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The second operand is a string constant which indicates what
|
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|
|
subexpression of @var{op} to examine. If it is absent or the empty
|
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|
|
string, @var{op} itself is examined. Otherwise, the string constant
|
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|
|
must be a sequence of digits and/or lowercase letters. Each character
|
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|
|
indicates a subexpression to extract from the current expression; for
|
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|
|
the first character this is @var{op}, for the second and subsequent
|
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|
|
characters it is the result of the previous character. A digit
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|
@var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
|
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|
|
extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
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alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
|
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|
|
@code{MATCH_CODE} then examines the RTX code of the subexpression
|
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|
|
extracted by the complete string. It is not possible to extract
|
|
|
|
components of an @code{rtvec} that is not at position 0 within its RTX
|
|
|
|
object.
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
|
|
|
|
@item MATCH_TEST
|
|
|
|
This expression has one operand, a string constant containing a C
|
|
|
|
expression. The predicate's arguments, @var{op} and @var{mode}, are
|
|
|
|
available with those names in the C expression. The @code{MATCH_TEST}
|
|
|
|
evaluates to true if the C expression evaluates to a nonzero value.
|
|
|
|
@code{MATCH_TEST} expressions must not have side effects.
|
|
|
|
|
|
|
|
@item AND
|
|
|
|
@itemx IOR
|
|
|
|
@itemx NOT
|
|
|
|
@itemx IF_THEN_ELSE
|
|
|
|
The basic @samp{MATCH_} expressions can be combined using these
|
|
|
|
logical operators, which have the semantics of the C operators
|
2006-01-23 16:16:19 +01:00
|
|
|
@samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
|
|
|
|
in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
|
|
|
|
arbitrary number of arguments; this has exactly the same effect as
|
|
|
|
writing a chain of two-argument @code{AND} or @code{IOR} expressions.
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@item
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cfg.texi, doc/extend.texi, doc/gty.texi,
doc/install.texi, doc/invoke.texi, doc/md.texi, doc/passes.texi,
doc/rtl.texi, doc/tm.texi, doc/tree-ssa.texi: Remove trailing
whitespace.
From-SVN: r90100
2004-11-05 01:53:49 +01:00
|
|
|
An optional block of C code, which should execute
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
@samp{@w{return true}} if the predicate is found to match and
|
|
|
|
@samp{@w{return false}} if it does not. It must not have any side
|
|
|
|
effects. The predicate arguments, @var{op} and @var{mode}, are
|
|
|
|
available with those names.
|
|
|
|
|
|
|
|
If a code block is present in a predicate definition, then the RTL
|
|
|
|
expression must evaluate to true @emph{and} the code block must
|
|
|
|
execute @samp{@w{return true}} for the predicate to allow the operand.
|
|
|
|
The RTL expression is evaluated first; do not re-check anything in the
|
|
|
|
code block that was checked in the RTL expression.
|
|
|
|
@end itemize
|
|
|
|
|
|
|
|
The program @command{genrecog} scans @code{define_predicate} and
|
|
|
|
@code{define_special_predicate} expressions to determine which RTX
|
|
|
|
codes are possibly allowed. You should always make this explicit in
|
|
|
|
the RTL predicate expression, using @code{MATCH_OPERAND} and
|
|
|
|
@code{MATCH_CODE}.
|
|
|
|
|
|
|
|
Here is an example of a simple predicate definition, from the IA64
|
|
|
|
machine description:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
|
|
|
|
(define_predicate "small_addr_symbolic_operand"
|
|
|
|
(and (match_code "symbol_ref")
|
|
|
|
(match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
And here is another, showing the use of the C block.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
|
|
|
|
(define_predicate "gr_register_operand"
|
|
|
|
(match_operand 0 "register_operand")
|
|
|
|
@{
|
|
|
|
unsigned int regno;
|
|
|
|
if (GET_CODE (op) == SUBREG)
|
|
|
|
op = SUBREG_REG (op);
|
|
|
|
|
|
|
|
regno = REGNO (op);
|
|
|
|
return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
|
|
|
|
@})
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Predicates written with @code{define_predicate} automatically include
|
|
|
|
a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
|
|
|
|
mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
|
|
|
|
@code{CONST_DOUBLE}. They do @emph{not} check specifically for
|
|
|
|
integer @code{CONST_DOUBLE}, nor do they test that the value of either
|
|
|
|
kind of constant fits in the requested mode. This is because
|
|
|
|
target-specific predicates that take constants usually have to do more
|
|
|
|
stringent value checks anyway. If you need the exact same treatment
|
|
|
|
of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
|
|
|
|
provide, use a @code{MATCH_OPERAND} subexpression to call
|
|
|
|
@code{const_int_operand}, @code{const_double_operand}, or
|
|
|
|
@code{immediate_operand}.
|
|
|
|
|
|
|
|
Predicates written with @code{define_special_predicate} do not get any
|
|
|
|
automatic mode checks, and are treated as having special mode handling
|
|
|
|
by @command{genrecog}.
|
|
|
|
|
|
|
|
The program @command{genpreds} is responsible for generating code to
|
|
|
|
test predicates. It also writes a header file containing function
|
|
|
|
declarations for all machine-specific predicates. It is not necessary
|
|
|
|
to declare these predicates in @file{@var{cpu}-protos.h}.
|
1997-03-25 20:26:08 +01:00
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@c Most of this node appears by itself (in a different place) even
|
Separate user and internals manuals.
* Makefile.in (info, $(docdir)/gcc.info, dvi, gcc.dvi): Update
dependencies.
($(docdir)/gccint.info, gccint.dvi): New targets.
(maintainer-clean, install-info, uninstall): Update.
* doc/.cvsignore: Add gccint.info*.
* doc/include/gcc-common.texi: New file.
* doc/gcc.texi: Use it. Adjust to be a user-only manual. Put
copyright notice in a macro. Don't include ISBN unless FSFPRINT
is defined.
* doc/gccint.texi: New file.
* doc/configfiles.texi, doc/extend.texi, doc/invoke.texi,
doc/md.texi, doc/passes.texi, doc/tm.texi, doc/trouble.texi:
Update for separate user and internals manuals.
f:
* g77.texi, invoke.texi: Update links to GCC manual.
java:
* gcj.texi: Update link to GCC manual.
From-SVN: r48119
2001-12-17 20:20:05 +01:00
|
|
|
@c when the INTERNALS flag is clear. Passages that require the internals
|
|
|
|
@c manual's context are conditionalized to appear only in the internals manual.
|
1997-03-25 20:26:08 +01:00
|
|
|
@ifset INTERNALS
|
|
|
|
@node Constraints
|
|
|
|
@section Operand Constraints
|
|
|
|
@cindex operand constraints
|
|
|
|
@cindex constraints
|
|
|
|
|
genpreds.c: Add capability to generate predicate bodies as well as function prototypes.
* genpreds.c: Add capability to generate predicate bodies as
well as function prototypes. Write function prototypes for
the generic predicates too.
(process_define_predicate, write_tm_preds_h, write_insn_preds_c)
(write_predicate_subfunction, mark_mode_tests, add_mode_tests)
(write_match_code, write_predicate_expr, write_one_predicate_function)
(parse_option): New functions.
(output_predicate_decls): Delete.
(main): Read the machine description, process DEFINE_PREDICATE or
DEFINE_SPECIAL_PREDICATE patterns, write tm-preds.h or insn-preds.c
as appropriate.
* genrecog.c (struct decision_test): Replace index with
struct pred_data pointer.
(next_index): Remove, unused.
(pred_table, preds, special_mode_pred_table): Delete.
(compute_predicate_codes, process_define_predicate): New functions.
(validate_pattern, add_to_sequence, write_switch): Update for
new data structures.
(main): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
Check both error_count and have_error.
* gensupport.c (in_fname, first_predicate): New globals.
(define_pred_queue, define_pred_tail): New RTL-pattern queue.
(predicate_table, last_predicate, old_pred_table)
(old_special_pred_table): New statics.
(hash_struct_pred_data, eq_struct_pred_data, lookup_predicate)
(add_predicate, init_predicate_table): New functions.
(process_rtx): Handle DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE.
(init_md_reader_args_cb): Use the global in_fname. No need to zero
it or max_include_len. Call init_predicate_table.
(read_rtx): Run the predicate queue after the attribute queue
but before all the others.
* gensupport.h (in_fname, struct pred_data, first_predicate)
(lookup_predicate, add_predicate, FOR_ALL_PREDICATES): Declare.
* rtl.def (MATCH_CODE, MATCH_TEST, DEFINE_PREDICATE)
(DEFINE_SPECIAL_PREDICATE): New RTL codes.
* dummy-conditions.c: Don't include bconfig.h, system.h,
coretypes.h, tm.h, or system.h. Do include stddef.h.
Duplicate declaration of struct c_test from gensupport.h.
* Makefile.in (OBJS-common): Add insn-preds.o.
(STAGESTUFF, .PRECIOUS): Add insn-preds.c.
(insn-preds.c, insn-preds.o): New rules.
(s-preds): Also generate insn-preds.c.
(dummy-conditions.o, genpreds$(build_exeext), genpreds.o):
Update dependencies.
(print-rtl.o, print-rtl1.o): Correct dependencies.
* recog.h: Delete prototypes of predicate functions.
* doc/md.texi (Predicates): New section with complete
documentation of operand/operator predicates. Remove some
incomplete documentation of predicates from other places.
* doc/tm.texi (Misc): Move SPECIAL_MODE_PREDICATES next to
PREDICATE_CODES; indicate that both are deprecated in favor
of define_predicate/define_special_predicate.
* config/ia64/ia64.c: All predicate function definitions moved
to ia64.md, except
(small_addr_symbolic_operand, tls_symbolic_operand): Delete.
(ia64_expand_load_address, ia64_expand_move):
Check SYMBOL_REF_TLS_MODEL directly, don't use tls_symbolic_operand.
* config/ia64/ia64.md: All predicates now defined here.
(symbolic_operand): Is now a special predicate.
* config/ia64/ia64.h: Declare ia64_section_threshold.
(PREDICATE_CODES): Delete.
From-SVN: r85855
2004-08-12 09:49:00 +02:00
|
|
|
Each @code{match_operand} in an instruction pattern can specify
|
|
|
|
constraints for the operands allowed. The constraints allow you to
|
|
|
|
fine-tune matching within the set of operands allowed by the
|
|
|
|
predicate.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end ifset
|
|
|
|
@ifclear INTERNALS
|
|
|
|
@node Constraints
|
|
|
|
@section Constraints for @code{asm} Operands
|
|
|
|
@cindex operand constraints, @code{asm}
|
|
|
|
@cindex constraints, @code{asm}
|
|
|
|
@cindex @code{asm} constraints
|
|
|
|
|
|
|
|
Here are specific details on what constraint letters you can use with
|
|
|
|
@code{asm} operands.
|
|
|
|
@end ifclear
|
|
|
|
Constraints can say whether
|
|
|
|
an operand may be in a register, and which kinds of register; whether the
|
|
|
|
operand can be a memory reference, and which kinds of address; whether the
|
|
|
|
operand may be an immediate constant, and which possible values it may
|
|
|
|
have. Constraints can also require two operands to match.
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
@menu
|
|
|
|
* Simple Constraints:: Basic use of constraints.
|
|
|
|
* Multi-Alternative:: When an insn has two alternative constraint-patterns.
|
|
|
|
* Class Preferences:: Constraints guide which hard register to put things in.
|
|
|
|
* Modifiers:: More precise control over effects of constraints.
|
|
|
|
* Machine Constraints:: Existing constraints for some particular machines.
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
* Define Constraints:: How to define machine-specific constraints.
|
|
|
|
* C Constraint Interface:: How to test constraints from C code.
|
1997-03-25 20:26:08 +01:00
|
|
|
@end menu
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@ifclear INTERNALS
|
|
|
|
@menu
|
|
|
|
* Simple Constraints:: Basic use of constraints.
|
|
|
|
* Multi-Alternative:: When an insn has two alternative constraint-patterns.
|
|
|
|
* Modifiers:: More precise control over effects of constraints.
|
|
|
|
* Machine Constraints:: Special constraints for some particular machines.
|
|
|
|
@end menu
|
|
|
|
@end ifclear
|
|
|
|
|
|
|
|
@node Simple Constraints
|
|
|
|
@subsection Simple Constraints
|
|
|
|
@cindex simple constraints
|
|
|
|
|
|
|
|
The simplest kind of constraint is a string full of letters, each of
|
|
|
|
which describes one kind of operand that is permitted. Here are
|
|
|
|
the letters that are allowed:
|
|
|
|
|
|
|
|
@table @asis
|
2000-02-16 15:44:19 +01:00
|
|
|
@item whitespace
|
|
|
|
Whitespace characters are ignored and can be inserted at any position
|
|
|
|
except the first. This enables each alternative for different operands to
|
|
|
|
be visually aligned in the machine description even if they have different
|
|
|
|
number of constraints and modifiers.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @samp{m} in constraint
|
|
|
|
@cindex memory references in constraints
|
|
|
|
@item @samp{m}
|
|
|
|
A memory operand is allowed, with any kind of address that the machine
|
|
|
|
supports in general.
|
|
|
|
|
|
|
|
@cindex offsettable address
|
|
|
|
@cindex @samp{o} in constraint
|
|
|
|
@item @samp{o}
|
|
|
|
A memory operand is allowed, but only if the address is
|
|
|
|
@dfn{offsettable}. This means that adding a small integer (actually,
|
|
|
|
the width in bytes of the operand, as determined by its machine mode)
|
|
|
|
may be added to the address and the result is also a valid memory
|
|
|
|
address.
|
|
|
|
|
|
|
|
@cindex autoincrement/decrement addressing
|
|
|
|
For example, an address which is constant is offsettable; so is an
|
|
|
|
address that is the sum of a register and a constant (as long as a
|
|
|
|
slightly larger constant is also within the range of address-offsets
|
|
|
|
supported by the machine); but an autoincrement or autodecrement
|
|
|
|
address is not offsettable. More complicated indirect/indexed
|
|
|
|
addresses may or may not be offsettable depending on the other
|
|
|
|
addressing modes that the machine supports.
|
|
|
|
|
|
|
|
Note that in an output operand which can be matched by another
|
|
|
|
operand, the constraint letter @samp{o} is valid only when accompanied
|
|
|
|
by both @samp{<} (if the target machine has predecrement addressing)
|
|
|
|
and @samp{>} (if the target machine has preincrement addressing).
|
|
|
|
|
|
|
|
@cindex @samp{V} in constraint
|
|
|
|
@item @samp{V}
|
|
|
|
A memory operand that is not offsettable. In other words, anything that
|
|
|
|
would fit the @samp{m} constraint but not the @samp{o} constraint.
|
|
|
|
|
|
|
|
@cindex @samp{<} in constraint
|
|
|
|
@item @samp{<}
|
|
|
|
A memory operand with autodecrement addressing (either predecrement or
|
|
|
|
postdecrement) is allowed.
|
|
|
|
|
|
|
|
@cindex @samp{>} in constraint
|
|
|
|
@item @samp{>}
|
|
|
|
A memory operand with autoincrement addressing (either preincrement or
|
|
|
|
postincrement) is allowed.
|
|
|
|
|
|
|
|
@cindex @samp{r} in constraint
|
|
|
|
@cindex registers in constraints
|
|
|
|
@item @samp{r}
|
|
|
|
A register operand is allowed provided that it is in a general
|
|
|
|
register.
|
|
|
|
|
|
|
|
@cindex constants in constraints
|
|
|
|
@cindex @samp{i} in constraint
|
|
|
|
@item @samp{i}
|
|
|
|
An immediate integer operand (one with constant value) is allowed.
|
|
|
|
This includes symbolic constants whose values will be known only at
|
2004-03-16 04:54:33 +01:00
|
|
|
assembly time or later.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @samp{n} in constraint
|
|
|
|
@item @samp{n}
|
|
|
|
An immediate integer operand with a known numeric value is allowed.
|
|
|
|
Many systems cannot support assembly-time constants for operands less
|
|
|
|
than a word wide. Constraints for these operands should use @samp{n}
|
|
|
|
rather than @samp{i}.
|
|
|
|
|
|
|
|
@cindex @samp{I} in constraint
|
|
|
|
@item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
|
|
|
|
Other letters in the range @samp{I} through @samp{P} may be defined in
|
|
|
|
a machine-dependent fashion to permit immediate integer operands with
|
|
|
|
explicit integer values in specified ranges. For example, on the
|
|
|
|
68000, @samp{I} is defined to stand for the range of values 1 to 8.
|
|
|
|
This is the range permitted as a shift count in the shift
|
|
|
|
instructions.
|
|
|
|
|
|
|
|
@cindex @samp{E} in constraint
|
|
|
|
@item @samp{E}
|
|
|
|
An immediate floating operand (expression code @code{const_double}) is
|
|
|
|
allowed, but only if the target floating point format is the same as
|
|
|
|
that of the host machine (on which the compiler is running).
|
|
|
|
|
|
|
|
@cindex @samp{F} in constraint
|
|
|
|
@item @samp{F}
|
2002-07-23 22:51:00 +02:00
|
|
|
An immediate floating operand (expression code @code{const_double} or
|
|
|
|
@code{const_vector}) is allowed.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @samp{G} in constraint
|
|
|
|
@cindex @samp{H} in constraint
|
|
|
|
@item @samp{G}, @samp{H}
|
|
|
|
@samp{G} and @samp{H} may be defined in a machine-dependent fashion to
|
|
|
|
permit immediate floating operands in particular ranges of values.
|
|
|
|
|
|
|
|
@cindex @samp{s} in constraint
|
|
|
|
@item @samp{s}
|
|
|
|
An immediate integer operand whose value is not an explicit integer is
|
|
|
|
allowed.
|
|
|
|
|
|
|
|
This might appear strange; if an insn allows a constant operand with a
|
|
|
|
value not known at compile time, it certainly must allow any known
|
|
|
|
value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
|
|
|
|
better code to be generated.
|
|
|
|
|
|
|
|
For example, on the 68000 in a fullword instruction it is possible to
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
use an immediate operand; but if the immediate value is between @minus{}128
|
1997-03-25 20:26:08 +01:00
|
|
|
and 127, better code results from loading the value into a register and
|
|
|
|
using the register. This is because the load into the register can be
|
|
|
|
done with a @samp{moveq} instruction. We arrange for this to happen
|
|
|
|
by defining the letter @samp{K} to mean ``any integer outside the
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
|
1997-03-25 20:26:08 +01:00
|
|
|
constraints.
|
|
|
|
|
|
|
|
@cindex @samp{g} in constraint
|
|
|
|
@item @samp{g}
|
|
|
|
Any register, memory or immediate integer operand is allowed, except for
|
|
|
|
registers that are not general registers.
|
|
|
|
|
|
|
|
@cindex @samp{X} in constraint
|
|
|
|
@item @samp{X}
|
|
|
|
@ifset INTERNALS
|
|
|
|
Any operand whatsoever is allowed, even if it does not satisfy
|
|
|
|
@code{general_operand}. This is normally used in the constraint of
|
|
|
|
a @code{match_scratch} when certain alternatives will not actually
|
|
|
|
require a scratch register.
|
|
|
|
@end ifset
|
|
|
|
@ifclear INTERNALS
|
|
|
|
Any operand whatsoever is allowed.
|
|
|
|
@end ifclear
|
|
|
|
|
|
|
|
@cindex @samp{0} in constraint
|
|
|
|
@cindex digits in constraint
|
|
|
|
@item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
|
|
|
|
An operand that matches the specified operand number is allowed. If a
|
|
|
|
digit is used together with letters within the same alternative, the
|
|
|
|
digit should come last.
|
|
|
|
|
2001-10-11 09:07:30 +02:00
|
|
|
This number is allowed to be more than a single digit. If multiple
|
2002-12-17 17:47:45 +01:00
|
|
|
digits are encountered consecutively, they are interpreted as a single
|
2001-10-11 09:07:30 +02:00
|
|
|
decimal integer. There is scant chance for ambiguity, since to-date
|
|
|
|
it has never been desirable that @samp{10} be interpreted as matching
|
|
|
|
either operand 1 @emph{or} operand 0. Should this be desired, one
|
|
|
|
can use multiple alternatives instead.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex matching constraint
|
|
|
|
@cindex constraint, matching
|
|
|
|
This is called a @dfn{matching constraint} and what it really means is
|
|
|
|
that the assembler has only a single operand that fills two roles
|
|
|
|
@ifset INTERNALS
|
|
|
|
considered separate in the RTL insn. For example, an add insn has two
|
|
|
|
input operands and one output operand in the RTL, but on most CISC
|
|
|
|
@end ifset
|
|
|
|
@ifclear INTERNALS
|
|
|
|
which @code{asm} distinguishes. For example, an add instruction uses
|
|
|
|
two input operands and an output operand, but on most CISC
|
|
|
|
@end ifclear
|
|
|
|
machines an add instruction really has only two operands, one of them an
|
|
|
|
input-output operand:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
addl #35,r12
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Matching constraints are used in these circumstances.
|
|
|
|
More precisely, the two operands that match must include one input-only
|
|
|
|
operand and one output-only operand. Moreover, the digit must be a
|
|
|
|
smaller number than the number of the operand that uses it in the
|
|
|
|
constraint.
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
For operands to match in a particular case usually means that they
|
|
|
|
are identical-looking RTL expressions. But in a few special cases
|
|
|
|
specific kinds of dissimilarity are allowed. For example, @code{*x}
|
|
|
|
as an input operand will match @code{*x++} as an output operand.
|
|
|
|
For proper results in such cases, the output template should always
|
|
|
|
use the output-operand's number when printing the operand.
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@cindex load address instruction
|
|
|
|
@cindex push address instruction
|
|
|
|
@cindex address constraints
|
|
|
|
@cindex @samp{p} in constraint
|
|
|
|
@item @samp{p}
|
|
|
|
An operand that is a valid memory address is allowed. This is
|
|
|
|
for ``load address'' and ``push address'' instructions.
|
|
|
|
|
|
|
|
@findex address_operand
|
|
|
|
@samp{p} in the constraint must be accompanied by @code{address_operand}
|
|
|
|
as the predicate in the @code{match_operand}. This predicate interprets
|
|
|
|
the mode specified in the @code{match_operand} as the mode of the memory
|
|
|
|
reference for which the address would be valid.
|
|
|
|
|
2000-08-29 02:44:21 +02:00
|
|
|
@cindex other register constraints
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex extensible constraints
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
@item @var{other-letters}
|
2000-08-29 02:44:21 +02:00
|
|
|
Other letters can be defined in machine-dependent fashion to stand for
|
|
|
|
particular classes of registers or other arbitrary operand types.
|
|
|
|
@samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
|
|
|
|
for data, address and floating point registers.
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
In order to have valid assembler code, each operand must satisfy
|
|
|
|
its constraint. But a failure to do so does not prevent the pattern
|
|
|
|
from applying to an insn. Instead, it directs the compiler to modify
|
|
|
|
the code so that the constraint will be satisfied. Usually this is
|
|
|
|
done by copying an operand into a register.
|
|
|
|
|
|
|
|
Contrast, therefore, the two instruction patterns that follow:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r")
|
|
|
|
(plus:SI (match_dup 0)
|
|
|
|
(match_operand:SI 1 "general_operand" "r")))]
|
|
|
|
""
|
|
|
|
"@dots{}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
which has two operands, one of which must appear in two places, and
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r")
|
|
|
|
(plus:SI (match_operand:SI 1 "general_operand" "0")
|
|
|
|
(match_operand:SI 2 "general_operand" "r")))]
|
|
|
|
""
|
|
|
|
"@dots{}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
which has three operands, two of which are required by a constraint to be
|
|
|
|
identical. If we are considering an insn of the form
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(insn @var{n} @var{prev} @var{next}
|
|
|
|
(set (reg:SI 3)
|
|
|
|
(plus:SI (reg:SI 6) (reg:SI 109)))
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
the first pattern would not apply at all, because this insn does not
|
|
|
|
contain two identical subexpressions in the right place. The pattern would
|
2004-10-28 02:20:42 +02:00
|
|
|
say, ``That does not look like an add instruction; try other patterns''.
|
1997-03-25 20:26:08 +01:00
|
|
|
The second pattern would say, ``Yes, that's an add instruction, but there
|
2004-10-28 02:20:42 +02:00
|
|
|
is something wrong with it''. It would direct the reload pass of the
|
1997-03-25 20:26:08 +01:00
|
|
|
compiler to generate additional insns to make the constraint true. The
|
|
|
|
results might look like this:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(insn @var{n2} @var{prev} @var{n}
|
|
|
|
(set (reg:SI 3) (reg:SI 6))
|
|
|
|
@dots{})
|
|
|
|
|
|
|
|
(insn @var{n} @var{n2} @var{next}
|
|
|
|
(set (reg:SI 3)
|
|
|
|
(plus:SI (reg:SI 3) (reg:SI 109)))
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
It is up to you to make sure that each operand, in each pattern, has
|
|
|
|
constraints that can handle any RTL expression that could be present for
|
|
|
|
that operand. (When multiple alternatives are in use, each pattern must,
|
|
|
|
for each possible combination of operand expressions, have at least one
|
|
|
|
alternative which can handle that combination of operands.) The
|
|
|
|
constraints don't need to @emph{allow} any possible operand---when this is
|
|
|
|
the case, they do not constrain---but they must at least point the way to
|
|
|
|
reloading any possible operand so that it will fit.
|
|
|
|
|
|
|
|
@itemize @bullet
|
|
|
|
@item
|
|
|
|
If the constraint accepts whatever operands the predicate permits,
|
|
|
|
there is no problem: reloading is never necessary for this operand.
|
|
|
|
|
|
|
|
For example, an operand whose constraints permit everything except
|
|
|
|
registers is safe provided its predicate rejects registers.
|
|
|
|
|
|
|
|
An operand whose predicate accepts only constant values is safe
|
|
|
|
provided its constraints include the letter @samp{i}. If any possible
|
|
|
|
constant value is accepted, then nothing less than @samp{i} will do;
|
|
|
|
if the predicate is more selective, then the constraints may also be
|
|
|
|
more selective.
|
|
|
|
|
|
|
|
@item
|
|
|
|
Any operand expression can be reloaded by copying it into a register.
|
|
|
|
So if an operand's constraints allow some kind of register, it is
|
|
|
|
certain to be safe. It need not permit all classes of registers; the
|
|
|
|
compiler knows how to copy a register into another register of the
|
|
|
|
proper class in order to make an instruction valid.
|
|
|
|
|
|
|
|
@cindex nonoffsettable memory reference
|
|
|
|
@cindex memory reference, nonoffsettable
|
|
|
|
@item
|
|
|
|
A nonoffsettable memory reference can be reloaded by copying the
|
|
|
|
address into a register. So if the constraint uses the letter
|
|
|
|
@samp{o}, all memory references are taken care of.
|
|
|
|
|
|
|
|
@item
|
|
|
|
A constant operand can be reloaded by allocating space in memory to
|
|
|
|
hold it as preinitialized data. Then the memory reference can be used
|
|
|
|
in place of the constant. So if the constraint uses the letters
|
|
|
|
@samp{o} or @samp{m}, constant operands are not a problem.
|
|
|
|
|
|
|
|
@item
|
|
|
|
If the constraint permits a constant and a pseudo register used in an insn
|
|
|
|
was not allocated to a hard register and is equivalent to a constant,
|
|
|
|
the register will be replaced with the constant. If the predicate does
|
|
|
|
not permit a constant and the insn is re-recognized for some reason, the
|
|
|
|
compiler will crash. Thus the predicate must always recognize any
|
|
|
|
objects allowed by the constraint.
|
|
|
|
@end itemize
|
|
|
|
|
|
|
|
If the operand's predicate can recognize registers, but the constraint does
|
|
|
|
not permit them, it can make the compiler crash. When this operand happens
|
|
|
|
to be a register, the reload pass will be stymied, because it does not know
|
|
|
|
how to copy a register temporarily into memory.
|
|
|
|
|
|
|
|
If the predicate accepts a unary operator, the constraint applies to the
|
|
|
|
operand. For example, the MIPS processor at ISA level 3 supports an
|
|
|
|
instruction which adds two registers in @code{SImode} to produce a
|
|
|
|
@code{DImode} result, but only if the registers are correctly sign
|
|
|
|
extended. This predicate for the input operands accepts a
|
|
|
|
@code{sign_extend} of an @code{SImode} register. Write the constraint
|
|
|
|
to indicate the type of register that is required for the operand of the
|
|
|
|
@code{sign_extend}.
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@node Multi-Alternative
|
|
|
|
@subsection Multiple Alternative Constraints
|
|
|
|
@cindex multiple alternative constraints
|
|
|
|
|
|
|
|
Sometimes a single instruction has multiple alternative sets of possible
|
|
|
|
operands. For example, on the 68000, a logical-or instruction can combine
|
|
|
|
register or an immediate value into memory, or it can combine any kind of
|
|
|
|
operand into a register; but it cannot combine one memory location into
|
|
|
|
another.
|
|
|
|
|
|
|
|
These constraints are represented as multiple alternatives. An alternative
|
|
|
|
can be described by a series of letters for each operand. The overall
|
|
|
|
constraint for an operand is made from the letters for this operand
|
|
|
|
from the first alternative, a comma, the letters for this operand from
|
|
|
|
the second alternative, a comma, and so on until the last alternative.
|
|
|
|
@ifset INTERNALS
|
|
|
|
Here is how it is done for fullword logical-or on the 68000:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "iorsi3"
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=m,d")
|
|
|
|
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
|
|
|
|
(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
|
|
|
|
operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
|
|
|
|
2. The second alternative has @samp{d} (data register) for operand 0,
|
|
|
|
@samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
|
|
|
|
@samp{%} in the constraints apply to all the alternatives; their
|
|
|
|
meaning is explained in the next section (@pxref{Class Preferences}).
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
|
|
|
|
If all the operands fit any one alternative, the instruction is valid.
|
|
|
|
Otherwise, for each alternative, the compiler counts how many instructions
|
|
|
|
must be added to copy the operands so that that alternative applies.
|
|
|
|
The alternative requiring the least copying is chosen. If two alternatives
|
|
|
|
need the same amount of copying, the one that comes first is chosen.
|
|
|
|
These choices can be altered with the @samp{?} and @samp{!} characters:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@cindex @samp{?} in constraint
|
|
|
|
@cindex question mark
|
|
|
|
@item ?
|
|
|
|
Disparage slightly the alternative that the @samp{?} appears in,
|
|
|
|
as a choice when no alternative applies exactly. The compiler regards
|
|
|
|
this alternative as one unit more costly for each @samp{?} that appears
|
|
|
|
in it.
|
|
|
|
|
|
|
|
@cindex @samp{!} in constraint
|
|
|
|
@cindex exclamation point
|
|
|
|
@item !
|
|
|
|
Disparage severely the alternative that the @samp{!} appears in.
|
|
|
|
This alternative can still be used if it fits without reloading,
|
|
|
|
but if reloading is needed, some other alternative will be used.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
When an insn pattern has multiple alternatives in its constraints, often
|
|
|
|
the appearance of the assembler code is determined mostly by which
|
|
|
|
alternative was matched. When this is so, the C code for writing the
|
|
|
|
assembler code can use the variable @code{which_alternative}, which is
|
|
|
|
the ordinal number of the alternative that was actually satisfied (0 for
|
|
|
|
the first, 1 for the second alternative, etc.). @xref{Output Statement}.
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
@node Class Preferences
|
|
|
|
@subsection Register Class Preferences
|
|
|
|
@cindex class preference constraints
|
|
|
|
@cindex register class preference constraints
|
|
|
|
|
|
|
|
@cindex voting between constraint alternatives
|
|
|
|
The operand constraints have another function: they enable the compiler
|
|
|
|
to decide which kind of hardware register a pseudo register is best
|
|
|
|
allocated to. The compiler examines the constraints that apply to the
|
|
|
|
insns that use the pseudo register, looking for the machine-dependent
|
|
|
|
letters such as @samp{d} and @samp{a} that specify classes of registers.
|
|
|
|
The pseudo register is put in whichever class gets the most ``votes''.
|
|
|
|
The constraint letters @samp{g} and @samp{r} also vote: they vote in
|
|
|
|
favor of a general register. The machine description says which registers
|
|
|
|
are considered general.
|
|
|
|
|
|
|
|
Of course, on some machines all registers are equivalent, and no register
|
|
|
|
classes are defined. Then none of this complexity is relevant.
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@node Modifiers
|
|
|
|
@subsection Constraint Modifier Characters
|
|
|
|
@cindex modifiers in constraints
|
|
|
|
@cindex constraint modifier characters
|
|
|
|
|
|
|
|
@c prevent bad page break with this line
|
|
|
|
Here are constraint modifier characters.
|
|
|
|
|
|
|
|
@table @samp
|
|
|
|
@cindex @samp{=} in constraint
|
|
|
|
@item =
|
|
|
|
Means that this operand is write-only for this instruction: the previous
|
|
|
|
value is discarded and replaced by output data.
|
|
|
|
|
|
|
|
@cindex @samp{+} in constraint
|
|
|
|
@item +
|
|
|
|
Means that this operand is both read and written by the instruction.
|
|
|
|
|
|
|
|
When the compiler fixes up the operands to satisfy the constraints,
|
|
|
|
it needs to know which operands are inputs to the instruction and
|
|
|
|
which are outputs from it. @samp{=} identifies an output; @samp{+}
|
|
|
|
identifies an operand that is both input and output; all other operands
|
|
|
|
are assumed to be input only.
|
|
|
|
|
1999-09-07 07:49:18 +02:00
|
|
|
If you specify @samp{=} or @samp{+} in a constraint, you put it in the
|
|
|
|
first character of the constraint string.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @samp{&} in constraint
|
|
|
|
@cindex earlyclobber operand
|
|
|
|
@item &
|
|
|
|
Means (in a particular alternative) that this operand is an
|
|
|
|
@dfn{earlyclobber} operand, which is modified before the instruction is
|
|
|
|
finished using the input operands. Therefore, this operand may not lie
|
|
|
|
in a register that is used as an input operand or as part of any memory
|
|
|
|
address.
|
|
|
|
|
|
|
|
@samp{&} applies only to the alternative in which it is written. In
|
|
|
|
constraints with multiple alternatives, sometimes one alternative
|
|
|
|
requires @samp{&} while others do not. See, for example, the
|
|
|
|
@samp{movdf} insn of the 68000.
|
|
|
|
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
An input operand can be tied to an earlyclobber operand if its only
|
1997-03-25 20:26:08 +01:00
|
|
|
use as an input occurs before the early result is written. Adding
|
|
|
|
alternatives of this form often allows GCC to produce better code
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
when only some of the inputs can be affected by the earlyclobber.
|
c-tree.texi, [...]: Replace . at end of sentences preceded by a capital letter with @..
* doc/c-tree.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppinternals.texi, doc/extend.texi, doc/gcc.texi,
doc/gcov.texi, doc/install-old.texi, doc/install.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Replace
. at end of sentences preceded by a capital letter with @..
From-SVN: r43611
2001-06-27 17:04:16 +02:00
|
|
|
See, for example, the @samp{mulsi3} insn of the ARM@.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@samp{&} does not obviate the need to write @samp{=}.
|
|
|
|
|
|
|
|
@cindex @samp{%} in constraint
|
|
|
|
@item %
|
|
|
|
Declares the instruction to be commutative for this operand and the
|
|
|
|
following operand. This means that the compiler may interchange the
|
|
|
|
two operands if that is the cheapest way to make all operands fit the
|
|
|
|
constraints.
|
|
|
|
@ifset INTERNALS
|
|
|
|
This is often used in patterns for addition instructions
|
|
|
|
that really have only two operands: the result must go in one of the
|
|
|
|
arguments. Here for example, is how the 68000 halfword-add
|
|
|
|
instruction is defined:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "addhi3"
|
|
|
|
[(set (match_operand:HI 0 "general_operand" "=m,r")
|
|
|
|
(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
|
|
|
|
(match_operand:HI 2 "general_operand" "di,g")))]
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
@end ifset
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cpp.texi, doc/extend.texi,
doc/frontends.texi, doc/gcov.texi, doc/gty.texi, doc/install.texi,
doc/invoke.texi, doc/libgcc.texi, doc/md.texi, doc/rtl.texi,
doc/sourcebuild.texi, doc/standards.texi, doc/tm.texi,
doc/trouble.texi: Remove trailing whitespace.
From-SVN: r76098
2004-01-18 12:57:17 +01:00
|
|
|
GCC can only handle one commutative pair in an asm; if you use more,
|
2004-11-13 23:28:46 +01:00
|
|
|
the compiler may fail. Note that you need not use the modifier if
|
|
|
|
the two alternatives are strictly identical; this would only waste
|
2005-10-17 22:39:45 +02:00
|
|
|
time in the reload pass. The modifier is not operational after
|
|
|
|
register allocation, so the result of @code{define_peephole2}
|
|
|
|
and @code{define_split}s performed after reload cannot rely on
|
|
|
|
@samp{%} to make the intended insn match.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @samp{#} in constraint
|
|
|
|
@item #
|
|
|
|
Says that all following characters, up to the next comma, are to be
|
|
|
|
ignored as a constraint. They are significant only for choosing
|
|
|
|
register preferences.
|
|
|
|
|
|
|
|
@cindex @samp{*} in constraint
|
|
|
|
@item *
|
|
|
|
Says that the following character should be ignored when choosing
|
|
|
|
register preferences. @samp{*} has no effect on the meaning of the
|
|
|
|
constraint as a constraint, and no effect on reloading.
|
|
|
|
|
2002-01-14 00:23:40 +01:00
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
Here is an example: the 68000 has an instruction to sign-extend a
|
|
|
|
halfword in a data register, and can also sign-extend a value by
|
|
|
|
copying it into an address register. While either kind of register is
|
|
|
|
acceptable, the constraints on an address-register destination are
|
|
|
|
less strict, so it is best if register allocation makes an address
|
|
|
|
register its goal. Therefore, @samp{*} is used so that the @samp{d}
|
|
|
|
constraint letter (for data register) is ignored when computing
|
|
|
|
register preferences.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "extendhisi2"
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=*d,a")
|
|
|
|
(sign_extend:SI
|
|
|
|
(match_operand:HI 1 "general_operand" "0,g")))]
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
@end ifset
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@node Machine Constraints
|
|
|
|
@subsection Constraints for Particular Machines
|
|
|
|
@cindex machine specific constraints
|
|
|
|
@cindex constraints, machine specific
|
|
|
|
|
|
|
|
Whenever possible, you should use the general-purpose constraint letters
|
|
|
|
in @code{asm} arguments, since they will convey meaning more readily to
|
|
|
|
people reading your code. Failing that, use the constraint letters
|
|
|
|
that usually have very similar meanings across architectures. The most
|
|
|
|
commonly used constraints are @samp{m} and @samp{r} (for memory and
|
|
|
|
general-purpose registers respectively; @pxref{Simple Constraints}), and
|
|
|
|
@samp{I}, usually the letter indicating the most common
|
|
|
|
immediate-constant format.
|
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Each architecture defines additional constraints. These constraints
|
|
|
|
are used by the compiler itself for instruction generation, as well as
|
|
|
|
for @code{asm} statements; therefore, some of the constraints are not
|
|
|
|
particularly useful for @code{asm}. Here is a summary of some of the
|
|
|
|
machine-dependent constraints available on some particular machines;
|
|
|
|
it includes both constraints that are useful for @code{asm} and
|
|
|
|
constraints that aren't. The compiler source file mentioned in the
|
|
|
|
table heading for each architecture is the definitive reference for
|
|
|
|
the meanings of that architecture's constraints.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@table @emph
|
2006-02-26 20:32:37 +01:00
|
|
|
@item ARM family---@file{config/arm/arm.h}
|
1997-03-25 20:26:08 +01:00
|
|
|
@table @code
|
|
|
|
@item f
|
|
|
|
Floating-point register
|
|
|
|
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
@item w
|
|
|
|
VFP floating-point register
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item F
|
|
|
|
One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
|
|
|
|
or 10.0
|
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating-point constant that would satisfy the constraint @samp{F} if it
|
|
|
|
were negated
|
|
|
|
|
|
|
|
@item I
|
|
|
|
Integer that is valid as an immediate operand in a data processing
|
|
|
|
instruction. That is, an integer in the range 0 to 255 rotated by a
|
|
|
|
multiple of 2
|
|
|
|
|
|
|
|
@item J
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Integer in the range @minus{}4095 to 4095
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item K
|
|
|
|
Integer that satisfies constraint @samp{I} when inverted (ones complement)
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Integer that satisfies constraint @samp{I} when negated (twos complement)
|
|
|
|
|
|
|
|
@item M
|
|
|
|
Integer in the range 0 to 32
|
|
|
|
|
|
|
|
@item Q
|
|
|
|
A memory reference where the exact address is in a single register
|
|
|
|
(`@samp{m}' is preferable for @code{asm} statements)
|
|
|
|
|
|
|
|
@item R
|
|
|
|
An item in the constant pool
|
|
|
|
|
|
|
|
@item S
|
|
|
|
A symbol in the text segment of the current file
|
|
|
|
|
2004-03-13 12:19:23 +01:00
|
|
|
@item Uv
|
backport: re PR target/12476 (ARM/THUMB thunk calls broken)
Merge from csl-arm-branch.
2004-01-30 Paul Brook <paul@codesourcery.com>
* aof.h (REGISTER_NAMES): Add vfp reg names
(ADDITIONAL_REGISTER_NAMES): Ditto.
* aout.h (REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Ditto.
* arm-protos.h: Update/Add Prototypes.
* arm.c (init_fp_table): Rename from init_fpa_table. Update users.
Only allow 0.0 for VFP.
(fp_consts_inited): Rename from fpa_consts_inited. Update users.
(values_fp): Rename from values_fpa. Update Users.
(arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa.
Update users. Only check valid constants for this hardware.
(arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users.
Only allow consts for FPA.
(arm_float_add_operand): Rename from fpa_add_operand. Update users.
Only allow consts for FPA.
(use_return_insn): Check for saved VFP regs.
(arm_legitimate_address_p): Handle VFP DFmode addressing.
(arm_legitimize_address): Ditto.
(arm_general_register_operand): New function.
(vfp_mem_operand): New function.
(vfp_compare_operand): New function.
(vfp_secondary_reload_class): New function.
(arm_float_compare_operand): New function.
(vfp_print_multi): New function.
(vfp_output_fstmx): New function.
(vfp_emit_fstm): New function.
(arm_output_epilogue): Output VPF reg restore code.
(arm_expand_prologue): Output VFP reg save code.
(arm_print_operand): Add 'P'.
(arm_hard_regno_mode_ok): Return modes for VFP regs.
(arm_regno_class): Return classes for VFP regs.
(arm_compute_initial_elimination_offset): Include space for VFP regs.
(arm_get_frame_size): Ditto.
* arm.h (FIXED_REGISTERS): Add VFP regs.
(CALL_USED_REGISTERS): Ditto.
(CONDITIONAL_REGISTER_USAGE): Enable VFP regs.
(FIRST_VFP_REGNUM): Define.
(LAST_VFP_REGNUM): Define.
(IS_VFP_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Include VFP regs.
(HARD_REGNO_NREGS): Handle VFP regs.
(REG_ALLOC_ORDER): Add VFP regs.
(enum reg_class): Add VFP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs.
(REG_CLASS_FROM_LETTER): Add 'w'.
(EXTRA_CONSTRAINT_ARM): Add 'U'.
(EXTRA_MEMORY_CONSTRAINT): Define.
(SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs.
(SECONDARY_INPUT_RELOAD_CLASS): Ditto.
(REGISTER_MOVE_COST): Ditto.
(PREDICATE_CODES): Add arm_general_register_operand,
arm_float_compare_operand and vfp_compare_operand.
* arm.md (various): Rename as above.
(divsf3): Enable when TARGET_VFP.
(divdf3): Ditto.
(movdfcc): Ditto.
(sqrtsf2): Ditto.
(sqrtdf2): Ditto.
(arm_movdi): Disable when TARGET_VFP.
(arm_movsi_insn): Ditto.
(movsi): Only split with general regs.
(cmpsf): Use arm_float_compare_operand.
(push_fp_multi): Restrict to TARGET_FPA.
(vfp.md): Include.
* vfp.md: New file.
* fpa.md (various): Rename as above.
* doc/md.texi: Document ARM w and U constraints.
2004-01-15 Paul Brook <paul@codesourcery.com>
* config.gcc: Add with_fpu. Allow with-float=softfp.
* config/arm/arm.c (arm_override_options): Rename *-s to *s.
Break out of loop when we find a float-abi. Fix typo.
* config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu".
Set -mfloat-abi=.
* doc/install.texi: Document --with-fpu.
2003-01-14 Paul Brook <paul@codesourcery.com>
* config.gcc (with_arch): Add armv6.
* config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s.
* config/arm/arm.c (arm_overrride_options): Ditto.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
2004-01-07 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_emit_extendsi): Delete.
* arm-protos.h (arm_emit_extendsi): Delete.
* arm.md (zero_extendhisi2): Also handle zero-extension of
non-subregs.
(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
(thumb_zero_extendhisi2): Only match if not v6.
(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
(thumb_extendqisi2): Likewise.
(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
(arm_zero_extendhisi2addsi): Remove subreg. Add attributes.
(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
(arm_extendqisi2addsi): Likewise.
2003-12-31 Mark Mitchell <mark@codesourcery.com>
Revert this change:
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
* config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG
+ REG addressing modes.
2003-12-30 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept
CONSTANT_P_RTX.
2003-30-12 Paul Brook <paul@codesourcery.com>
* longlong.h: protect arm inlines with !defined (__thumb__)
2003-30-12 Paul Brook <paul@codesourcery.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__.
2003-12-30 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Fix typo in previous
change.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* builtins.c (expand_builtin_apply_args_1): Add pretend args size
to the virtual incoming args pointer for downward stacks.
2003-12-29 Paul Brook <paul@codesourcery.com>
* config/arm/arm-cores.def: Add cost function.
* config/arm/arm.c (arm_*_rtx_costs): New functions.
(arm_rtx_costs): Remove
(struct processors): Add rtx_costs field.
(all_cores, all_architectures): Ditto.
(arm_override_options): Set targetm.rtx_costs.
(thumb_rtx_costs): New function.
(arm_rtx_costs_1): Remove cases handled elsewhere.
* config/arm/arm.h (processor_type): Add COSTS parameter.
2003-12-29 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm.md (generic_sched): arm926 has its own scheduler.
(arm926ejs.md): Include it.
* config/arm/arm926ejs.md: New pipeline description.
2003-12-24 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_arch6j): New variable.
(arm_override_options): Set it.
(arm_emit_extendsi): New function.
* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
* config/arm/arm.h (arm_arch6j): Declare.
* config/arm/arm.md: Add sign/zero extend insns.
2003-12-23 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (all_architectures): Add armv6.
* doc/invoke.texi: Document it.
2003-12-19 Paul Brook <paul@codesourcery.com>
* config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify
insn patterns to match.
* config/arm/arm-generic.md: Ditto.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/amm/iwmmxt.md: Ditto.
* config/arm/arm1026ejs.md: Ditto.
* config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses
for 11_loadb.
2003-12-18 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare.
* config/arm/arm.c (arm_adjust_cost): Check shift cost for
TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
(arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
arm_no_early_mul_dep): Correctly deal with conditional execution,
parallels and single shift operations.
(arm_no_early_alu_shift_value_dep): Define.
* arm.md (attr type): Replace 'normal' with 'alu',
'alu_shift' and 'alu_shift_reg'.
(attr core_cycles): Adjust.
(*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
*shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
*not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
*cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
*arith_shiftsi_compare0_scratch, *sub_shiftsi,
*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
*if_shift_move, *if_move_shift, *if_shift_shift): Set type
attribute appropriately.
* config/arm/arm1026ejs.md (alu_op): Adjust.
(alu_shift_op, alu_shift_reg_op): New.
* config/arm/arm1136.md: Add better bypasses for early
registers. Remove load[234] and store[234] bypasses.
(11_alu_op): Adjust.
(11_alu_shift_op, 11_alu_shift_reg_op): New.
2003-12-15 Nathan Sidwell <nathan@codesourcery.com>
* config/arm/arm-protos.h (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare.
* config/arm/arm.c (arm_no_early_store_addr_dep,
arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define.
* config/arm/arm1026ejs.md: Add load-store bypass.
* config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles.
Add bypasses between instructions.
2003-12-10 Paul Brook <paul@codesourcery.com>
* config/arm/arm.c (arm_fpu_model): New variable.
(arm_fload_abi): New variable.
(target_fpe_name): Rename from target_fp_name.
(target_fpu_name): New variable.
(arm_is_cirrus): Remove.
(fpu_desc): New struct.
(all_fpus): Define.
(pf_model_for_fpu): Define.
(all_loat_abis): Define.
(arm_override_options): Set fp arch flags based on -mfpu=
and -float-abi=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(*): Use new TARGET_* flags.
* config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove.
(TARGET_HARD_FLOAT): No longer implies TARGET_FPA.
(TARGET_SOFT_FLOAT): Ditto.
(TARGET_SOFT_FLOAT_ABI): New.
(TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies
TARGET_HARD_FLOAT.
(TARGET_VFP): No longer implies TARGET_HARD_FLOAT.
(TARGET_OPTIONS): Add -mfpu=.
(FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM.
(LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM.
(arm_pf_model): Define.
(arm_float_abi_type): Define.
(fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE
* config/arm/arm.md: Use new TARGET_* flags.
* config/arm/cirrus.md: Ditto.
* config/arm/fpa.md: Ditto.
* config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=.
* config/arm/semi.h (ASM_SPEC): Ditto.
* config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp.
(FPUTYPE_DEFAULT): Set to VFP.
* doc/invoke.texi: Document -mfpu= and -mfloat-abi=.
2003-11-22 Phil Edwards <phil@codesourcery.com>
PR target/12476
* config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use
'bx' instead of 'b' to avoid branch range restrictions. Output
the thunk immediately before the thunked-to function.
* config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit
.thumb_func if a thunk is being generated. Emit .code 16 along
with .thumb_func if a thunk is not being generated.
2003-11-15 Nicolas Pitre <nico@cam.org>
* config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3,
arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns.
* config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3.
(lshrdi3_iwmmxt): Renamed from lshrdi3.
* config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly.
2003-11-12 Steve Woodford <scw@wasabisystems.com>
Ian Lance Taylor <ian@wasabisystems.com>
* config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new
code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__).
2003-11-05 Phil Edwards <phil@codesourcery.com>
* config/arm/arm.md (insn): Add new V6 instruction names.
(generic_sched): New attr.
* config/arm/arm-generic.md: Use generic_sched here.
* config/arm/arm1026ejs.md: Do not model fetch/issue/decode
stages of pipeline. Adjust latency counts accordingly.
* config/arm/arm1136jfs.md: New file.
2003-10-28 Mark Mitchell <mark@codesourcery.com>
* config/arm/arm.h (processor_type): New enumeration type.
(CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S,
ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores.
(CPP_CPU_ARCH_SPEC): Likewise.
* config/arm/arm.c (arm_tune): New variable.
(all_cores): Use cores.def.
(all_architectures): Add representative processor.
(arm_override_options): Restructure way in which tuning
information is deduced.
* arm.md: Update "insn" and "type" attributes throughout.
(insn): New attribute.
(type): Compute "mult" from "insn" attribute. Add load2,
load3, load4 alternatives.
(arm automaton): Move to arm-generic.md.
* config/arm/arm-cores.def: New file.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
From-SVN: r77171
2004-02-03 15:45:44 +01:00
|
|
|
A memory reference suitable for VFP load/store insns (reg+constant offset)
|
|
|
|
|
2004-05-06 01:11:55 +02:00
|
|
|
@item Uy
|
|
|
|
A memory reference suitable for iWMMXt load/store instructions.
|
|
|
|
|
2004-03-13 12:19:23 +01:00
|
|
|
@item Uq
|
2005-04-15 12:24:13 +02:00
|
|
|
A memory reference suitable for the ARMv4 ldrsb instruction.
|
2005-08-14 01:54:11 +02:00
|
|
|
@end table
|
2004-03-13 12:19:23 +01:00
|
|
|
|
2006-03-31 15:32:44 +02:00
|
|
|
@item AVR family---@file{config/avr/constraints.md}
|
2000-02-17 05:09:21 +01:00
|
|
|
@table @code
|
|
|
|
@item l
|
|
|
|
Registers from r0 to r15
|
|
|
|
|
|
|
|
@item a
|
|
|
|
Registers from r16 to r23
|
|
|
|
|
|
|
|
@item d
|
|
|
|
Registers from r16 to r31
|
|
|
|
|
|
|
|
@item w
|
2000-12-01 18:49:05 +01:00
|
|
|
Registers from r24 to r31. These registers can be used in @samp{adiw} command
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item e
|
2001-06-11 22:52:30 +02:00
|
|
|
Pointer register (r26--r31)
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item b
|
2001-06-11 22:52:30 +02:00
|
|
|
Base pointer register (r28--r31)
|
2000-02-17 05:09:21 +01:00
|
|
|
|
2000-12-01 18:49:05 +01:00
|
|
|
@item q
|
|
|
|
Stack pointer register (SPH:SPL)
|
|
|
|
|
2000-02-17 05:09:21 +01:00
|
|
|
@item t
|
|
|
|
Temporary register r0
|
|
|
|
|
|
|
|
@item x
|
|
|
|
Register pair X (r27:r26)
|
|
|
|
|
|
|
|
@item y
|
|
|
|
Register pair Y (r29:r28)
|
|
|
|
|
|
|
|
@item z
|
|
|
|
Register pair Z (r31:r30)
|
|
|
|
|
|
|
|
@item I
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constant greater than @minus{}1, less than 64
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item J
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constant greater than @minus{}64, less than 1
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item K
|
|
|
|
Constant integer 2
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Constant integer 0
|
|
|
|
|
|
|
|
@item M
|
|
|
|
Constant that fits in 8 bits
|
|
|
|
|
|
|
|
@item N
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constant integer @minus{}1
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item O
|
2000-12-01 18:49:05 +01:00
|
|
|
Constant integer 8, 16, or 24
|
2000-02-17 05:09:21 +01:00
|
|
|
|
|
|
|
@item P
|
|
|
|
Constant integer 1
|
|
|
|
|
|
|
|
@item G
|
|
|
|
A floating point constant 0.0
|
2007-07-07 21:55:12 +02:00
|
|
|
|
|
|
|
@item R
|
|
|
|
Integer constant in the range -6 @dots{} 5.
|
|
|
|
|
|
|
|
@item Q
|
|
|
|
A memory address based on Y or Z pointer with displacement.
|
2000-02-17 05:09:21 +01:00
|
|
|
@end table
|
2005-08-03 18:35:26 +02:00
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item CRX Architecture---@file{config/crx/crx.h}
|
2005-08-03 18:35:26 +02:00
|
|
|
@table @code
|
|
|
|
|
|
|
|
@item b
|
|
|
|
Registers from r0 to r14 (registers without stack pointer)
|
|
|
|
|
|
|
|
@item l
|
|
|
|
Register r16 (64-bit accumulator lo register)
|
|
|
|
|
|
|
|
@item h
|
|
|
|
Register r17 (64-bit accumulator hi register)
|
|
|
|
|
|
|
|
@item k
|
|
|
|
Register pair r16-r17. (64-bit accumulator lo-hi pair)
|
|
|
|
|
|
|
|
@item I
|
|
|
|
Constant that fits in 3 bits
|
|
|
|
|
|
|
|
@item J
|
|
|
|
Constant that fits in 4 bits
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Constant that fits in 5 bits
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
|
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating point constant that is legal for store immediate
|
|
|
|
@end table
|
2000-02-17 05:09:21 +01:00
|
|
|
|
2007-05-29 03:12:58 +02:00
|
|
|
@item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
|
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
General register 1
|
|
|
|
|
|
|
|
@item f
|
|
|
|
Floating point register
|
|
|
|
|
|
|
|
@item q
|
|
|
|
Shift amount register
|
|
|
|
|
|
|
|
@item x
|
|
|
|
Floating point register (deprecated)
|
|
|
|
|
|
|
|
@item y
|
|
|
|
Upper floating point register (32-bit), floating point register (64-bit)
|
|
|
|
|
|
|
|
@item Z
|
|
|
|
Any register
|
|
|
|
|
|
|
|
@item I
|
|
|
|
Signed 11-bit integer constant
|
|
|
|
|
|
|
|
@item J
|
|
|
|
Signed 14-bit integer constant
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Integer constant that can be deposited with a @code{zdepi} instruction
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Signed 5-bit integer constant
|
|
|
|
|
|
|
|
@item M
|
|
|
|
Integer constant 0
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Integer constant that can be loaded with a @code{ldil} instruction
|
|
|
|
|
|
|
|
@item O
|
|
|
|
Integer constant whose value plus one is a power of 2
|
|
|
|
|
|
|
|
@item P
|
|
|
|
Integer constant that can be used for @code{and} operations in @code{depi}
|
|
|
|
and @code{extru} instructions
|
|
|
|
|
|
|
|
@item S
|
|
|
|
Integer constant 31
|
|
|
|
|
|
|
|
@item U
|
|
|
|
Integer constant 63
|
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating-point constant 0.0
|
|
|
|
|
|
|
|
@item A
|
|
|
|
A @code{lo_sum} data-linkage-table memory operand
|
|
|
|
|
|
|
|
@item Q
|
|
|
|
A memory operand that can be used as the destination operand of an
|
|
|
|
integer store instruction
|
|
|
|
|
|
|
|
@item R
|
|
|
|
A scaled or unscaled indexed memory operand
|
|
|
|
|
|
|
|
@item T
|
|
|
|
A memory operand for floating-point loads and stores
|
|
|
|
|
|
|
|
@item W
|
|
|
|
A register indirect memory operand
|
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
|
1997-03-25 20:26:08 +01:00
|
|
|
@table @code
|
|
|
|
@item b
|
|
|
|
Address base register
|
|
|
|
|
|
|
|
@item f
|
|
|
|
Floating point register
|
|
|
|
|
2003-12-24 17:19:16 +01:00
|
|
|
@item v
|
|
|
|
Vector register
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item h
|
|
|
|
@samp{MQ}, @samp{CTR}, or @samp{LINK} register
|
|
|
|
|
|
|
|
@item q
|
|
|
|
@samp{MQ} register
|
|
|
|
|
|
|
|
@item c
|
|
|
|
@samp{CTR} register
|
|
|
|
|
|
|
|
@item l
|
|
|
|
@samp{LINK} register
|
|
|
|
|
|
|
|
@item x
|
|
|
|
@samp{CR} register (condition register) number 0
|
|
|
|
|
|
|
|
@item y
|
|
|
|
@samp{CR} register (condition register)
|
|
|
|
|
1998-09-14 13:11:07 +02:00
|
|
|
@item z
|
|
|
|
@samp{FPMEM} stack memory for FPR-GPR transfers
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item I
|
2001-04-28 10:54:31 +02:00
|
|
|
Signed 16-bit constant
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item J
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
|
1999-08-02 22:20:12 +02:00
|
|
|
@code{SImode} constants)
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item K
|
2001-04-28 10:54:31 +02:00
|
|
|
Unsigned 16-bit constant
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item L
|
2001-04-28 10:54:31 +02:00
|
|
|
Signed 16-bit constant shifted left 16 bits
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item M
|
|
|
|
Constant larger than 31
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Exact power of 2
|
|
|
|
|
|
|
|
@item O
|
|
|
|
Zero
|
|
|
|
|
|
|
|
@item P
|
2001-04-28 10:54:31 +02:00
|
|
|
Constant whose negation is a signed 16-bit constant
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating point constant that can be loaded into a register with one
|
|
|
|
instruction per word
|
|
|
|
|
2006-11-03 02:27:39 +01:00
|
|
|
@item H
|
|
|
|
Integer/Floating point constant that can be loaded into a register using
|
|
|
|
three instructions
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item Q
|
|
|
|
Memory operand that is an offset from a register (@samp{m} is preferable
|
|
|
|
for @code{asm} statements)
|
|
|
|
|
2006-11-03 02:27:39 +01:00
|
|
|
@item Z
|
|
|
|
Memory operand that is an indexed or indirect from a register (@samp{m} is
|
|
|
|
preferable for @code{asm} statements)
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item R
|
|
|
|
AIX TOC entry
|
|
|
|
|
2006-11-03 02:27:39 +01:00
|
|
|
@item a
|
|
|
|
Address operand that is an indexed or indirect from a register (@samp{p} is
|
|
|
|
preferable for @code{asm} statements)
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item S
|
1998-09-14 13:11:07 +02:00
|
|
|
Constant suitable as a 64-bit mask operand
|
1997-03-25 20:26:08 +01:00
|
|
|
|
1999-08-02 22:20:12 +02:00
|
|
|
@item T
|
|
|
|
Constant suitable as a 32-bit mask operand
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item U
|
|
|
|
System V Release 4 small data area reference
|
2006-11-03 02:27:39 +01:00
|
|
|
|
|
|
|
@item t
|
|
|
|
AND masks that can be performed by two rldic@{l, r@} instructions
|
|
|
|
|
|
|
|
@item W
|
|
|
|
Vector constant that does not require memory
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item MorphoTech family---@file{config/mt/mt.h}
|
2005-08-22 18:12:14 +02:00
|
|
|
@table @code
|
|
|
|
@item I
|
|
|
|
Constant for an arithmetic insn (16-bit signed integer).
|
|
|
|
|
|
|
|
@item J
|
|
|
|
The constant 0.
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Constant for a logical insn (16-bit zero-extended integer).
|
|
|
|
|
|
|
|
@item L
|
|
|
|
A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
|
|
|
|
bits are zero).
|
|
|
|
|
|
|
|
@item M
|
|
|
|
A constant that takes two words to load (i.e.@: not matched by
|
|
|
|
@code{I}, @code{K}, or @code{L}).
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Negative 16-bit constants other than -65536.
|
|
|
|
|
|
|
|
@item O
|
|
|
|
A 15-bit signed integer constant.
|
|
|
|
|
|
|
|
@item P
|
|
|
|
A positive 16-bit constant.
|
|
|
|
@end table
|
|
|
|
|
2006-03-22 08:23:00 +01:00
|
|
|
@item Intel 386---@file{config/i386/constraints.md}
|
1997-03-25 20:26:08 +01:00
|
|
|
@table @code
|
2001-03-14 22:40:22 +01:00
|
|
|
@item R
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Legacy register---the eight integer registers available on all
|
|
|
|
i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
|
|
|
|
@code{si}, @code{di}, @code{bp}, @code{sp}).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@item q
|
|
|
|
Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
|
|
|
|
@code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@item Q
|
|
|
|
Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
|
|
|
|
@code{c}, and @code{d}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@ifset INTERNALS
|
|
|
|
@item l
|
|
|
|
Any register that can be used as the index in a base+index memory
|
|
|
|
access: that is, any general register except the stack pointer.
|
|
|
|
@end ifset
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item a
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
The @code{a} register.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item b
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
The @code{b} register.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item c
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
The @code{c} register.
|
2002-10-29 20:41:35 +01:00
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item d
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
The @code{d} register.
|
|
|
|
|
|
|
|
@item S
|
|
|
|
The @code{si} register.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item D
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
The @code{di} register.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@item A
|
|
|
|
The @code{a} and @code{d} registers, as a pair (for instructions that
|
|
|
|
return half the result in one and half in the other).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@item f
|
|
|
|
Any 80387 floating-point (stack) register.
|
|
|
|
|
|
|
|
@item t
|
|
|
|
Top of 80387 floating-point stack (@code{%st(0)}).
|
|
|
|
|
|
|
|
@item u
|
|
|
|
Second from top of 80387 floating-point stack (@code{%st(1)}).
|
2001-04-27 21:35:03 +02:00
|
|
|
|
|
|
|
@item y
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Any MMX register.
|
|
|
|
|
|
|
|
@item x
|
|
|
|
Any SSE register.
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
|
|
|
@item Y
|
|
|
|
Any SSE2 register.
|
|
|
|
@end ifset
|
2001-04-27 21:35:03 +02:00
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item I
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item J
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item K
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Signed 8-bit integer constant.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item L
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item M
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
0, 1, 2, or 3 (shifts for the @code{lea} instruction).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item N
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
Unsigned 8-bit integer constant (for @code{in} and @code{out}
|
|
|
|
instructions).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@ifset INTERNALS
|
|
|
|
@item O
|
|
|
|
Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
|
|
|
|
@end ifset
|
|
|
|
|
|
|
|
@item G
|
|
|
|
Standard 80387 floating point constant.
|
|
|
|
|
|
|
|
@item C
|
|
|
|
Standard SSE floating point constant.
|
2001-03-14 22:40:22 +01:00
|
|
|
|
|
|
|
@item e
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
32-bit signed integer constant, or a symbolic reference known
|
|
|
|
to fit that range (for immediate operands in sign-extending x86-64
|
|
|
|
instructions).
|
|
|
|
|
|
|
|
@item Z
|
|
|
|
32-bit unsigned integer constant, or a symbolic reference known
|
|
|
|
to fit that range (for immediate operands in zero-extending x86-64
|
|
|
|
instructions).
|
2001-03-14 22:40:22 +01:00
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item Intel IA-64---@file{config/ia64/ia64.h}
|
2002-04-26 02:24:41 +02:00
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
General register @code{r0} to @code{r3} for @code{addl} instruction
|
|
|
|
|
|
|
|
@item b
|
|
|
|
Branch register
|
|
|
|
|
|
|
|
@item c
|
|
|
|
Predicate register (@samp{c} as in ``conditional'')
|
|
|
|
|
|
|
|
@item d
|
|
|
|
Application register residing in M-unit
|
|
|
|
|
|
|
|
@item e
|
|
|
|
Application register residing in I-unit
|
|
|
|
|
|
|
|
@item f
|
|
|
|
Floating-point register
|
|
|
|
|
|
|
|
@item m
|
|
|
|
Memory operand.
|
|
|
|
Remember that @samp{m} allows postincrement and postdecrement which
|
|
|
|
require printing with @samp{%Pn} on IA-64.
|
|
|
|
Use @samp{S} to disallow postincrement and postdecrement.
|
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating-point constant 0.0 or 1.0
|
|
|
|
|
|
|
|
@item I
|
|
|
|
14-bit signed integer constant
|
|
|
|
|
|
|
|
@item J
|
|
|
|
22-bit signed integer constant
|
|
|
|
|
|
|
|
@item K
|
|
|
|
8-bit signed integer constant for logical instructions
|
|
|
|
|
|
|
|
@item L
|
|
|
|
8-bit adjusted signed integer constant for compare pseudo-ops
|
|
|
|
|
|
|
|
@item M
|
|
|
|
6-bit unsigned integer constant for shift counts
|
|
|
|
|
|
|
|
@item N
|
|
|
|
9-bit signed integer constant for load and store postincrements
|
|
|
|
|
|
|
|
@item O
|
|
|
|
The constant zero
|
|
|
|
|
|
|
|
@item P
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
0 or @minus{}1 for @code{dep} instruction
|
2002-04-26 02:24:41 +02:00
|
|
|
|
|
|
|
@item Q
|
|
|
|
Non-volatile memory for floating-point loads and stores
|
|
|
|
|
|
|
|
@item R
|
|
|
|
Integer constant in the range 1 to 4 for @code{shladd} instruction
|
|
|
|
|
|
|
|
@item S
|
|
|
|
Memory operand except postincrement and postdecrement
|
|
|
|
@end table
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item FRV---@file{config/frv/frv.h}
|
2002-12-07 00:54:41 +01:00
|
|
|
@table @code
|
|
|
|
@item a
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item b
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item c
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
|
|
|
|
@code{icc0} to @code{icc3}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item d
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item e
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
Odd registers are excluded not in the class but through the use of a machine
|
|
|
|
mode larger than 4 bytes.
|
|
|
|
|
|
|
|
@item f
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item h
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
Odd registers are excluded not in the class but through the use of a machine
|
|
|
|
mode larger than 4 bytes.
|
|
|
|
|
|
|
|
@item l
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{LR_REG} (the @code{lr} register).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item q
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
|
|
|
the use of a machine mode larger than 8 bytes.
|
|
|
|
|
|
|
|
@item t
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item u
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item v
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item w
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item x
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
|
2002-12-07 00:54:41 +01:00
|
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
|
|
|
the use of a machine mode larger than 8 bytes.
|
|
|
|
|
|
|
|
@item z
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item A
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item B
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item C
|
2002-12-07 03:31:34 +01:00
|
|
|
Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item G
|
|
|
|
Floating point constant zero
|
|
|
|
|
|
|
|
@item I
|
|
|
|
6-bit signed integer constant
|
|
|
|
|
|
|
|
@item J
|
|
|
|
10-bit signed integer constant
|
|
|
|
|
|
|
|
@item L
|
|
|
|
16-bit signed integer constant
|
|
|
|
|
|
|
|
@item M
|
|
|
|
16-bit unsigned integer constant
|
|
|
|
|
|
|
|
@item N
|
2002-12-07 03:31:34 +01:00
|
|
|
12-bit signed integer constant that is negative---i.e.@: in the
|
|
|
|
range of @minus{}2048 to @minus{}1
|
2002-12-07 00:54:41 +01:00
|
|
|
|
|
|
|
@item O
|
|
|
|
Constant zero
|
|
|
|
|
|
|
|
@item P
|
2002-12-07 03:31:34 +01:00
|
|
|
12-bit signed integer constant that is greater than zero---i.e.@: in the
|
2002-12-07 00:54:41 +01:00
|
|
|
range of 1 to 2047.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item Blackfin family---@file{config/bfin/bfin.h}
|
2005-04-05 13:26:48 +02:00
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
P register
|
|
|
|
|
|
|
|
@item d
|
|
|
|
D register
|
|
|
|
|
|
|
|
@item z
|
|
|
|
A call clobbered P register.
|
|
|
|
|
2007-09-12 01:20:10 +02:00
|
|
|
@item q@var{n}
|
|
|
|
A single register. If @var{n} is in the range 0 to 7, the corresponding D
|
|
|
|
register. If it is @code{A}, then the register P0.
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
@item D
|
|
|
|
Even-numbered D register
|
|
|
|
|
|
|
|
@item W
|
|
|
|
Odd-numbered D register
|
|
|
|
|
|
|
|
@item e
|
|
|
|
Accumulator register.
|
|
|
|
|
|
|
|
@item A
|
|
|
|
Even-numbered accumulator register.
|
|
|
|
|
|
|
|
@item B
|
|
|
|
Odd-numbered accumulator register.
|
|
|
|
|
|
|
|
@item b
|
|
|
|
I register
|
|
|
|
|
2006-06-18 12:30:23 +02:00
|
|
|
@item v
|
2005-04-05 13:26:48 +02:00
|
|
|
B register
|
|
|
|
|
|
|
|
@item f
|
|
|
|
M register
|
|
|
|
|
|
|
|
@item c
|
|
|
|
Registers used for circular buffering, i.e. I, B, or L registers.
|
|
|
|
|
|
|
|
@item C
|
|
|
|
The CC register.
|
|
|
|
|
2006-06-18 12:30:23 +02:00
|
|
|
@item t
|
|
|
|
LT0 or LT1.
|
|
|
|
|
|
|
|
@item k
|
|
|
|
LC0 or LC1.
|
|
|
|
|
|
|
|
@item u
|
|
|
|
LB0 or LB1.
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
@item x
|
|
|
|
Any D, P, B, M, I or L register.
|
|
|
|
|
|
|
|
@item y
|
|
|
|
Additional registers typically used only in prologues and epilogues: RETS,
|
|
|
|
RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
|
|
|
|
|
|
|
|
@item w
|
|
|
|
Any register except accumulators or CC.
|
|
|
|
|
|
|
|
@item Ksh
|
|
|
|
Signed 16 bit integer (in the range -32768 to 32767)
|
|
|
|
|
|
|
|
@item Kuh
|
|
|
|
Unsigned 16 bit integer (in the range 0 to 65535)
|
|
|
|
|
|
|
|
@item Ks7
|
|
|
|
Signed 7 bit integer (in the range -64 to 63)
|
|
|
|
|
|
|
|
@item Ku7
|
|
|
|
Unsigned 7 bit integer (in the range 0 to 127)
|
|
|
|
|
|
|
|
@item Ku5
|
|
|
|
Unsigned 5 bit integer (in the range 0 to 31)
|
|
|
|
|
|
|
|
@item Ks4
|
|
|
|
Signed 4 bit integer (in the range -8 to 7)
|
|
|
|
|
|
|
|
@item Ks3
|
|
|
|
Signed 3 bit integer (in the range -3 to 4)
|
|
|
|
|
|
|
|
@item Ku3
|
|
|
|
Unsigned 3 bit integer (in the range 0 to 7)
|
|
|
|
|
|
|
|
@item P@var{n}
|
|
|
|
Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
@item PA
|
|
|
|
An integer equal to one of the MACFLAG_XXX constants that is suitable for
|
|
|
|
use with either accumulator.
|
|
|
|
|
|
|
|
@item PB
|
|
|
|
An integer equal to one of the MACFLAG_XXX constants that is suitable for
|
|
|
|
use only with accumulator A1.
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
@item M1
|
|
|
|
Constant 255.
|
|
|
|
|
|
|
|
@item M2
|
|
|
|
Constant 65535.
|
|
|
|
|
|
|
|
@item J
|
|
|
|
An integer constant with exactly a single bit set.
|
|
|
|
|
|
|
|
@item L
|
|
|
|
An integer constant with all bits set except exactly one.
|
|
|
|
|
|
|
|
@item H
|
|
|
|
|
|
|
|
@item Q
|
|
|
|
Any SYMBOL_REF.
|
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item M32C---@file{config/m32c/m32c.c}
|
|
|
|
@table @code
|
2005-07-21 01:27:02 +02:00
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@item Rsp
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@itemx Rfb
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@itemx Rsb
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@samp{$sp}, @samp{$fb}, @samp{$sb}.
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@item Rcr
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Any control register, when they're 16 bits wide (nothing if control
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registers are 24 bits wide)
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@item Rcl
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Any control register, when they're 24 bits wide.
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@item R0w
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@itemx R1w
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@itemx R2w
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@itemx R3w
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$r0, $r1, $r2, $r3.
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@item R02
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$r0 or $r2, or $r2r0 for 32 bit values.
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@item R13
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$r1 or $r3, or $r3r1 for 32 bit values.
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@item Rdi
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A register that can hold a 64 bit value.
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@item Rhl
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$r0 or $r1 (registers with addressable high/low bytes)
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@item R23
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$r2 or $r3
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@item Raa
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Address registers
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@item Raw
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Address registers when they're 16 bits wide.
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@item Ral
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Address registers when they're 24 bits wide.
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@item Rqi
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Registers that can hold QI values.
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@item Rad
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Registers that can be used with displacements ($a0, $a1, $sb).
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@item Rsi
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Registers that can hold 32 bit values.
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@item Rhi
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Registers that can hold 16 bit values.
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@item Rhc
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Registers chat can hold 16 bit values, including all control
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registers.
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@item Rra
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$r0 through R1, plus $a0 and $a1.
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@item Rfl
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The flags register.
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@item Rmm
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The memory-based pseudo-registers $mem0 through $mem15.
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@item Rpi
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Registers that can hold pointers (16 bit registers for r8c, m16c; 24
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bit registers for m32cm, m32c).
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@item Rpa
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Matches multiple registers in a PARALLEL to form a larger register.
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Used to match function return values.
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@item Is3
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-8 @dots{} 7
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@item IS1
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-128 @dots{} 127
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@item IS2
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-32768 @dots{} 32767
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@item IU2
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0 @dots{} 65535
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@item In4
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-8 @dots{} -1 or 1 @dots{} 8
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@item In5
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-16 @dots{} -1 or 1 @dots{} 16
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2006-01-13 04:34:40 +01:00
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@item In6
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-32 @dots{} -1 or 1 @dots{} 32
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2005-07-21 01:27:02 +02:00
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@item IM2
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-65536 @dots{} -1
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@item Ilb
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An 8 bit value with exactly one bit set.
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@item Ilw
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A 16 bit value with exactly one bit set.
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@item Sd
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The common src/dest memory addressing modes.
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@item Sa
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Memory addressed using $a0 or $a1.
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@item Si
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Memory addressed with immediate addresses.
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@item Ss
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Memory addressed using the stack pointer ($sp).
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@item Sf
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Memory addressed using the frame base register ($fb).
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@item Ss
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Memory addressed using the small base register ($sb).
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@item S1
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$r1h
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2006-02-26 20:32:37 +01:00
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@end table
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2005-07-21 01:27:02 +02:00
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2006-03-09 19:31:08 +01:00
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@item MIPS---@file{config/mips/constraints.md}
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2002-08-30 21:18:51 +02:00
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@table @code
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@item d
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2006-03-09 19:31:08 +01:00
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An address register. This is equivalent to @code{r} unless
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generating MIPS16 code.
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2002-08-30 21:18:51 +02:00
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@item f
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2006-03-09 19:31:08 +01:00
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A floating-point register (if available).
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2002-08-30 21:18:51 +02:00
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@item h
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2006-03-09 19:31:08 +01:00
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The @code{hi} register.
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2002-08-30 21:18:51 +02:00
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@item l
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2006-03-09 19:31:08 +01:00
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The @code{lo} register.
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2002-08-30 21:18:51 +02:00
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@item x
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2006-03-09 19:31:08 +01:00
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The @code{hi} and @code{lo} registers.
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@item c
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A register suitable for use in an indirect jump. This will always be
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@code{$25} for @option{-mabicalls}.
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2002-08-30 21:18:51 +02:00
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@item y
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2006-03-09 19:31:08 +01:00
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Equivalent to @code{r}; retained for backwards compatibility.
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2002-08-30 21:18:51 +02:00
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@item z
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2006-03-09 19:31:08 +01:00
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A floating-point condition code register.
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2002-08-30 21:18:51 +02:00
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@item I
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2006-03-09 19:31:08 +01:00
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A signed 16-bit constant (for arithmetic instructions).
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2002-08-30 21:18:51 +02:00
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@item J
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2006-03-09 19:31:08 +01:00
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Integer zero.
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2002-08-30 21:18:51 +02:00
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@item K
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2006-03-09 19:31:08 +01:00
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An unsigned 16-bit constant (for logic instructions).
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2002-08-30 21:18:51 +02:00
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@item L
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2006-03-09 19:31:08 +01:00
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A signed 32-bit constant in which the lower 16 bits are zero.
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Such constants can be loaded using @code{lui}.
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2002-08-30 21:18:51 +02:00
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@item M
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2006-03-09 19:31:08 +01:00
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A constant that cannot be loaded using @code{lui}, @code{addiu}
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or @code{ori}.
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2002-08-30 21:18:51 +02:00
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@item N
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2006-03-09 19:31:08 +01:00
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A constant in the range -65535 to -1 (inclusive).
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2002-08-30 21:18:51 +02:00
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@item O
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2006-03-09 19:31:08 +01:00
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A signed 15-bit constant.
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2002-08-30 21:18:51 +02:00
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@item P
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2006-03-09 19:31:08 +01:00
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A constant in the range 1 to 65535 (inclusive).
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2002-08-30 21:18:51 +02:00
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@item G
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2006-03-09 19:31:08 +01:00
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Floating-point zero.
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2002-08-30 21:18:51 +02:00
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@item R
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2006-03-09 19:31:08 +01:00
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An address that can be used in a non-macro load or store.
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2002-08-30 21:18:51 +02:00
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@end table
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predicates.md (movsi_const0_operand, [...]): New predicates.
* config/m68k/predicates.md (movsi_const0_operand,
non_symbolic_call_operand): New predicates.
* config/m68k/constraints.md: (Cs, Ci, C0, Cj, CQ, CW, CZ, CS, Ap, Ac):
New constraints.
* doc/md.texi (Constraints for Particular Machines: Motorola 680x0):
Document constraints N, O, P, R, S, T, Q, U, W, Cs, Ci, C0, Cj, CQ,
CW, CZ, CS, Ap and Ac.
* config/m68k/m68k.md (UNSPEC_IB): New constant.
(constraints.md): New include.
(cpu, type, type1, opx, opy, opx_type, opy_type, size, opx_access,
opx_mem, opy_mem, op_mem, guess, split): New attributes.
(movdf_internal): Name pattern. Fix to use alternatives. Add split.
Specify attributes.
(pushdi): Add split.
(tstsi_internal): Name pattern. Fix to use alternatives. Specify
attributes. Split tstsi_internal_68020_cf from it.
(tstsi_internal_68020_cf): New pattern.
(tsthi_internal, tstqi_internal): Name pattern. Specify attributes.
(tst<mode>_cf): Specify attributea.
(cmpsi_cf): Name pattern. Specify attributes.
(cmp<mode>_68881, cmp<mode>_cf): Specify type attribute.
(pushexthisi_const): Fix to use alternatives. Specify
attributes.
(movsi_const0): Split movsi_const0_68000_10 and movsi_const0_68040_60
from it. Fix to use alternatives. Specify attributes.
(movsi_const0_68040_10, movsi_const0_68040_60): New patterns.
(movsi_cf, movstrictqi_cf): Fix to use alternatives. Specify
attributes.
(movsf_cf_soft): Specify attributes.
(movdf_cf_soft): Add split.
(pushasi, zero_extendhisi2_cf, zero_extendqisi2_cfv4,
cfv4_extendhisi2, 68k_extendhisi2, extendqihi2, cfv4_extendqisi2,
68k_extendqisi2, truncdfsf2_cf): Specify attributes.
(truncdfsf2_68881): Name pattern. Specify attributes.
(floatsi<mode>2_cf, floathi<mode>2_68881, floathi<mode>2_cf,
floatqi<mode>2_68881, floatqi<mode>2_cf, ftrunc<mode>2_cf,
fix<mode>qi2_cf, fix<mode>hi2_cf, fix<mode>si2_cf, adddi_dishl32):
Specify attributes.
(addsi3_5200): Fix to use alternatives. Specify attributes.
Add splits.
(add<mode>3_cf, subdi_dishl32): Specify attributes.
(subsi3): Add alternative for subq.l. Specify attributes.
(sub<mode>3_cf, mulhi3, mulhisi3): Specify attributes.
(mulhisisi3_s, mulsi3_68020, mulsi3_cf): Name pattern. Specify
attributes.
(umulhisi3): Specify attributes.
(mulhisisi3_z): Name pattern. Specify attributes.
(fmul<mode>3_cf, div<mode>3_cf, negsi2_internal, negsi2_5200,
sqrt<mode>2_68881, clzsi2, one_cmplsi2_5200, subreghi1ashrdi_const32,
subregsi1ashrdi_const32, ashrsi3, subreg1lshrdi_const32, lshrsi3,
bsetmemqi): Specify attributes.
(bsetmemqi_ext): Name pattern. Specify attributes.
(bclrmemqi): Specify attributes.
(bclrmemqi_ext, scc, sls): Name pattern. Specify attributes.
(beq, bne, bgt, bgtu, blt, bltu, bge, bgeu, ble, bleu): Specify
attributes.
(beq2, bne2, bgt2, bgtu2, blt2, bltu2, bge2, bgeu2, ble2, bleu2): Name
pattern. Specify attributes.
(jump): Specify attributes.
(tablejump_internal): Name pattern. Specify attributes.
(call_value): Split into non_symbolic_call_value,
symbolic_call_value_jsr, symbolic_call_value_bsr. Fix to use
alternatives. Specify attributes.
(non_symbolic_call_value, symbolic_call_value_jsr,
symbolic_call_value_bsr): New patterns.
(nop, return, unlink, indirect_jump): Specify attributes.
(trap): Fix condition. Specify attributes.
(ib): New pattern.
* config/m68k/m68k.c (m68k_symbolic_call_var): New variable.
(override_options): Initialize it. Initialize m68k_sched_cpu.
(CONST_METHOD): Rename to M68K_CONST_METHOD, move to m68k.h.
(const_method): Make global, rename to m68k_const_method.
(const_int_cost, output_move_const_into_data_reg): Update.
(output_move_double): Parametrize to emit rtl code, rename to
handle_move_double.
(output_reg_adjust, emit_reg_adjust, output_compadr, output_movsi,
emit_movsi): New static functions.
(output_move_double): New function with semantics of old
output_move_double.
(m68k_emit_move_double): New function.
(m68k_sched_cpu): New variable.
(attr_op_type): New enum.
(sched_guess_p): New variable.
(sched_address_type, sched_operand_type, sched_attr_op_type):
New static functions.
(m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem): New functions.
(sched_branch_type): New static variable.
(m68k_sched_branch_type): New function.
* config/m68k/m68k.h (M68K_SYMBOLIC_CALL): New enum.
(m68k_symbolic_call_var): Declare.
(M68K_CONST_METHOD): Rename from CONST_METHOD. Move here from m68k.c.
(m68k_const_method, m68k_emit_move_double, m68k_sched_cpu,
m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem, m68k_sched_branch_type):
Declare.
From-SVN: r128377
2007-09-11 15:56:30 +02:00
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@item Motorola 680x0---@file{config/m68k/constraints.md}
|
1997-03-25 20:26:08 +01:00
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@table @code
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@item a
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Address register
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@item d
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Data register
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@item f
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68881 floating-point register, if available
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@item I
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Integer in the range 1 to 8
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@item J
|
2001-04-28 10:54:31 +02:00
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16-bit signed number
|
1997-03-25 20:26:08 +01:00
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|
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@item K
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Signed number whose magnitude is greater than 0x80
|
|
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@item L
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Integer in the range @minus{}8 to @minus{}1
|
1997-03-25 20:26:08 +01:00
|
|
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|
|
@item M
|
|
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|
Signed number whose magnitude is greater than 0x100
|
|
|
|
|
predicates.md (movsi_const0_operand, [...]): New predicates.
* config/m68k/predicates.md (movsi_const0_operand,
non_symbolic_call_operand): New predicates.
* config/m68k/constraints.md: (Cs, Ci, C0, Cj, CQ, CW, CZ, CS, Ap, Ac):
New constraints.
* doc/md.texi (Constraints for Particular Machines: Motorola 680x0):
Document constraints N, O, P, R, S, T, Q, U, W, Cs, Ci, C0, Cj, CQ,
CW, CZ, CS, Ap and Ac.
* config/m68k/m68k.md (UNSPEC_IB): New constant.
(constraints.md): New include.
(cpu, type, type1, opx, opy, opx_type, opy_type, size, opx_access,
opx_mem, opy_mem, op_mem, guess, split): New attributes.
(movdf_internal): Name pattern. Fix to use alternatives. Add split.
Specify attributes.
(pushdi): Add split.
(tstsi_internal): Name pattern. Fix to use alternatives. Specify
attributes. Split tstsi_internal_68020_cf from it.
(tstsi_internal_68020_cf): New pattern.
(tsthi_internal, tstqi_internal): Name pattern. Specify attributes.
(tst<mode>_cf): Specify attributea.
(cmpsi_cf): Name pattern. Specify attributes.
(cmp<mode>_68881, cmp<mode>_cf): Specify type attribute.
(pushexthisi_const): Fix to use alternatives. Specify
attributes.
(movsi_const0): Split movsi_const0_68000_10 and movsi_const0_68040_60
from it. Fix to use alternatives. Specify attributes.
(movsi_const0_68040_10, movsi_const0_68040_60): New patterns.
(movsi_cf, movstrictqi_cf): Fix to use alternatives. Specify
attributes.
(movsf_cf_soft): Specify attributes.
(movdf_cf_soft): Add split.
(pushasi, zero_extendhisi2_cf, zero_extendqisi2_cfv4,
cfv4_extendhisi2, 68k_extendhisi2, extendqihi2, cfv4_extendqisi2,
68k_extendqisi2, truncdfsf2_cf): Specify attributes.
(truncdfsf2_68881): Name pattern. Specify attributes.
(floatsi<mode>2_cf, floathi<mode>2_68881, floathi<mode>2_cf,
floatqi<mode>2_68881, floatqi<mode>2_cf, ftrunc<mode>2_cf,
fix<mode>qi2_cf, fix<mode>hi2_cf, fix<mode>si2_cf, adddi_dishl32):
Specify attributes.
(addsi3_5200): Fix to use alternatives. Specify attributes.
Add splits.
(add<mode>3_cf, subdi_dishl32): Specify attributes.
(subsi3): Add alternative for subq.l. Specify attributes.
(sub<mode>3_cf, mulhi3, mulhisi3): Specify attributes.
(mulhisisi3_s, mulsi3_68020, mulsi3_cf): Name pattern. Specify
attributes.
(umulhisi3): Specify attributes.
(mulhisisi3_z): Name pattern. Specify attributes.
(fmul<mode>3_cf, div<mode>3_cf, negsi2_internal, negsi2_5200,
sqrt<mode>2_68881, clzsi2, one_cmplsi2_5200, subreghi1ashrdi_const32,
subregsi1ashrdi_const32, ashrsi3, subreg1lshrdi_const32, lshrsi3,
bsetmemqi): Specify attributes.
(bsetmemqi_ext): Name pattern. Specify attributes.
(bclrmemqi): Specify attributes.
(bclrmemqi_ext, scc, sls): Name pattern. Specify attributes.
(beq, bne, bgt, bgtu, blt, bltu, bge, bgeu, ble, bleu): Specify
attributes.
(beq2, bne2, bgt2, bgtu2, blt2, bltu2, bge2, bgeu2, ble2, bleu2): Name
pattern. Specify attributes.
(jump): Specify attributes.
(tablejump_internal): Name pattern. Specify attributes.
(call_value): Split into non_symbolic_call_value,
symbolic_call_value_jsr, symbolic_call_value_bsr. Fix to use
alternatives. Specify attributes.
(non_symbolic_call_value, symbolic_call_value_jsr,
symbolic_call_value_bsr): New patterns.
(nop, return, unlink, indirect_jump): Specify attributes.
(trap): Fix condition. Specify attributes.
(ib): New pattern.
* config/m68k/m68k.c (m68k_symbolic_call_var): New variable.
(override_options): Initialize it. Initialize m68k_sched_cpu.
(CONST_METHOD): Rename to M68K_CONST_METHOD, move to m68k.h.
(const_method): Make global, rename to m68k_const_method.
(const_int_cost, output_move_const_into_data_reg): Update.
(output_move_double): Parametrize to emit rtl code, rename to
handle_move_double.
(output_reg_adjust, emit_reg_adjust, output_compadr, output_movsi,
emit_movsi): New static functions.
(output_move_double): New function with semantics of old
output_move_double.
(m68k_emit_move_double): New function.
(m68k_sched_cpu): New variable.
(attr_op_type): New enum.
(sched_guess_p): New variable.
(sched_address_type, sched_operand_type, sched_attr_op_type):
New static functions.
(m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem): New functions.
(sched_branch_type): New static variable.
(m68k_sched_branch_type): New function.
* config/m68k/m68k.h (M68K_SYMBOLIC_CALL): New enum.
(m68k_symbolic_call_var): Declare.
(M68K_CONST_METHOD): Rename from CONST_METHOD. Move here from m68k.c.
(m68k_const_method, m68k_emit_move_double, m68k_sched_cpu,
m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem, m68k_sched_branch_type):
Declare.
From-SVN: r128377
2007-09-11 15:56:30 +02:00
|
|
|
@item N
|
|
|
|
Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
|
|
|
|
|
|
|
|
@item O
|
|
|
|
16 (for rotate using swap)
|
|
|
|
|
|
|
|
@item P
|
|
|
|
Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
|
|
|
|
|
|
|
|
@item R
|
|
|
|
Numbers that mov3q can handle
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item G
|
|
|
|
Floating point constant that is not a 68881 constant
|
predicates.md (movsi_const0_operand, [...]): New predicates.
* config/m68k/predicates.md (movsi_const0_operand,
non_symbolic_call_operand): New predicates.
* config/m68k/constraints.md: (Cs, Ci, C0, Cj, CQ, CW, CZ, CS, Ap, Ac):
New constraints.
* doc/md.texi (Constraints for Particular Machines: Motorola 680x0):
Document constraints N, O, P, R, S, T, Q, U, W, Cs, Ci, C0, Cj, CQ,
CW, CZ, CS, Ap and Ac.
* config/m68k/m68k.md (UNSPEC_IB): New constant.
(constraints.md): New include.
(cpu, type, type1, opx, opy, opx_type, opy_type, size, opx_access,
opx_mem, opy_mem, op_mem, guess, split): New attributes.
(movdf_internal): Name pattern. Fix to use alternatives. Add split.
Specify attributes.
(pushdi): Add split.
(tstsi_internal): Name pattern. Fix to use alternatives. Specify
attributes. Split tstsi_internal_68020_cf from it.
(tstsi_internal_68020_cf): New pattern.
(tsthi_internal, tstqi_internal): Name pattern. Specify attributes.
(tst<mode>_cf): Specify attributea.
(cmpsi_cf): Name pattern. Specify attributes.
(cmp<mode>_68881, cmp<mode>_cf): Specify type attribute.
(pushexthisi_const): Fix to use alternatives. Specify
attributes.
(movsi_const0): Split movsi_const0_68000_10 and movsi_const0_68040_60
from it. Fix to use alternatives. Specify attributes.
(movsi_const0_68040_10, movsi_const0_68040_60): New patterns.
(movsi_cf, movstrictqi_cf): Fix to use alternatives. Specify
attributes.
(movsf_cf_soft): Specify attributes.
(movdf_cf_soft): Add split.
(pushasi, zero_extendhisi2_cf, zero_extendqisi2_cfv4,
cfv4_extendhisi2, 68k_extendhisi2, extendqihi2, cfv4_extendqisi2,
68k_extendqisi2, truncdfsf2_cf): Specify attributes.
(truncdfsf2_68881): Name pattern. Specify attributes.
(floatsi<mode>2_cf, floathi<mode>2_68881, floathi<mode>2_cf,
floatqi<mode>2_68881, floatqi<mode>2_cf, ftrunc<mode>2_cf,
fix<mode>qi2_cf, fix<mode>hi2_cf, fix<mode>si2_cf, adddi_dishl32):
Specify attributes.
(addsi3_5200): Fix to use alternatives. Specify attributes.
Add splits.
(add<mode>3_cf, subdi_dishl32): Specify attributes.
(subsi3): Add alternative for subq.l. Specify attributes.
(sub<mode>3_cf, mulhi3, mulhisi3): Specify attributes.
(mulhisisi3_s, mulsi3_68020, mulsi3_cf): Name pattern. Specify
attributes.
(umulhisi3): Specify attributes.
(mulhisisi3_z): Name pattern. Specify attributes.
(fmul<mode>3_cf, div<mode>3_cf, negsi2_internal, negsi2_5200,
sqrt<mode>2_68881, clzsi2, one_cmplsi2_5200, subreghi1ashrdi_const32,
subregsi1ashrdi_const32, ashrsi3, subreg1lshrdi_const32, lshrsi3,
bsetmemqi): Specify attributes.
(bsetmemqi_ext): Name pattern. Specify attributes.
(bclrmemqi): Specify attributes.
(bclrmemqi_ext, scc, sls): Name pattern. Specify attributes.
(beq, bne, bgt, bgtu, blt, bltu, bge, bgeu, ble, bleu): Specify
attributes.
(beq2, bne2, bgt2, bgtu2, blt2, bltu2, bge2, bgeu2, ble2, bleu2): Name
pattern. Specify attributes.
(jump): Specify attributes.
(tablejump_internal): Name pattern. Specify attributes.
(call_value): Split into non_symbolic_call_value,
symbolic_call_value_jsr, symbolic_call_value_bsr. Fix to use
alternatives. Specify attributes.
(non_symbolic_call_value, symbolic_call_value_jsr,
symbolic_call_value_bsr): New patterns.
(nop, return, unlink, indirect_jump): Specify attributes.
(trap): Fix condition. Specify attributes.
(ib): New pattern.
* config/m68k/m68k.c (m68k_symbolic_call_var): New variable.
(override_options): Initialize it. Initialize m68k_sched_cpu.
(CONST_METHOD): Rename to M68K_CONST_METHOD, move to m68k.h.
(const_method): Make global, rename to m68k_const_method.
(const_int_cost, output_move_const_into_data_reg): Update.
(output_move_double): Parametrize to emit rtl code, rename to
handle_move_double.
(output_reg_adjust, emit_reg_adjust, output_compadr, output_movsi,
emit_movsi): New static functions.
(output_move_double): New function with semantics of old
output_move_double.
(m68k_emit_move_double): New function.
(m68k_sched_cpu): New variable.
(attr_op_type): New enum.
(sched_guess_p): New variable.
(sched_address_type, sched_operand_type, sched_attr_op_type):
New static functions.
(m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem): New functions.
(sched_branch_type): New static variable.
(m68k_sched_branch_type): New function.
* config/m68k/m68k.h (M68K_SYMBOLIC_CALL): New enum.
(m68k_symbolic_call_var): Declare.
(M68K_CONST_METHOD): Rename from CONST_METHOD. Move here from m68k.c.
(m68k_const_method, m68k_emit_move_double, m68k_sched_cpu,
m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
m68k_sched_attr_size, m68k_sched_attr_op_mem, m68k_sched_branch_type):
Declare.
From-SVN: r128377
2007-09-11 15:56:30 +02:00
|
|
|
|
|
|
|
@item S
|
|
|
|
Operands that satisfy 'm' when -mpcrel is in effect
|
|
|
|
|
|
|
|
@item T
|
|
|
|
Operands that satisfy 's' when -mpcrel is not in effect
|
|
|
|
|
|
|
|
@item Q
|
|
|
|
Address register indirect addressing mode
|
|
|
|
|
|
|
|
@item U
|
|
|
|
Register offset addressing
|
|
|
|
|
|
|
|
@item W
|
|
|
|
const_call_operand
|
|
|
|
|
|
|
|
@item Cs
|
|
|
|
symbol_ref or const
|
|
|
|
|
|
|
|
@item Ci
|
|
|
|
const_int
|
|
|
|
|
|
|
|
@item C0
|
|
|
|
const_int 0
|
|
|
|
|
|
|
|
@item Cj
|
|
|
|
Range of signed numbers that don't fit in 16 bits
|
|
|
|
|
|
|
|
@item Cmvq
|
|
|
|
Integers valid for mvq
|
|
|
|
|
|
|
|
@item Capsw
|
|
|
|
Integers valid for a moveq followed by a swap
|
|
|
|
|
|
|
|
@item Cmvz
|
|
|
|
Integers valid for mvz
|
|
|
|
|
|
|
|
@item Cmvs
|
|
|
|
Integers valid for mvs
|
|
|
|
|
|
|
|
@item Ap
|
|
|
|
push_operand
|
|
|
|
|
|
|
|
@item Ac
|
|
|
|
Non-register operands allowed in clr
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
|
2000-09-13 21:23:35 +02:00
|
|
|
@table @code
|
|
|
|
@item a
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Register `a'
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item b
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Register `b'
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item d
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Register `d'
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item q
|
|
|
|
An 8-bit register
|
|
|
|
|
|
|
|
@item t
|
|
|
|
Temporary soft register _.tmp
|
|
|
|
|
|
|
|
@item u
|
|
|
|
A soft register _.d1 to _.d31
|
|
|
|
|
|
|
|
@item w
|
|
|
|
Stack pointer register
|
|
|
|
|
|
|
|
@item x
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Register `x'
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item y
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Register `y'
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item z
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
Pseudo register `z' (replaced by `x' or `y' at the end)
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item A
|
|
|
|
An address register: x, y or z
|
|
|
|
|
|
|
|
@item B
|
|
|
|
An address register: x or y
|
|
|
|
|
|
|
|
@item D
|
|
|
|
Register pair (x:d) to form a 32-bit value
|
|
|
|
|
|
|
|
@item L
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constants in the range @minus{}65536 to 65535
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item M
|
|
|
|
Constants whose 16-bit low part is zero
|
|
|
|
|
|
|
|
@item N
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constant integer 1 or @minus{}1
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@item O
|
|
|
|
Constant integer 16
|
|
|
|
|
|
|
|
@item P
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
Constants in the range @minus{}8 to 2
|
2000-09-13 21:23:35 +02:00
|
|
|
|
|
|
|
@end table
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@need 1000
|
2006-02-26 20:32:37 +01:00
|
|
|
@item SPARC---@file{config/sparc/sparc.h}
|
1997-03-25 20:26:08 +01:00
|
|
|
@table @code
|
|
|
|
@item f
|
2003-06-05 10:36:53 +02:00
|
|
|
Floating-point register on the SPARC-V8 architecture and
|
|
|
|
lower floating-point register on the SPARC-V9 architecture.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item e
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
Floating-point register. It is equivalent to @samp{f} on the
|
2003-06-05 10:36:53 +02:00
|
|
|
SPARC-V8 architecture and contains both lower and upper
|
|
|
|
floating-point registers on the SPARC-V9 architecture.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2003-05-31 09:53:13 +02:00
|
|
|
@item c
|
|
|
|
Floating-point condition code register.
|
|
|
|
|
|
|
|
@item d
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
Lower floating-point register. It is only valid on the SPARC-V9
|
2003-06-05 10:36:53 +02:00
|
|
|
architecture when the Visual Instruction Set is available.
|
2003-05-31 09:53:13 +02:00
|
|
|
|
|
|
|
@item b
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
Floating-point register. It is only valid on the SPARC-V9 architecture
|
2003-06-05 10:36:53 +02:00
|
|
|
when the Visual Instruction Set is available.
|
2003-05-31 09:53:13 +02:00
|
|
|
|
|
|
|
@item h
|
|
|
|
64-bit global or out register for the SPARC-V8+ architecture.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item I
|
2001-04-28 10:54:31 +02:00
|
|
|
Signed 13-bit constant
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item J
|
|
|
|
Zero
|
|
|
|
|
|
|
|
@item K
|
2001-04-28 10:54:31 +02:00
|
|
|
32-bit constant with the low 12 bits clear (a constant that can be
|
1997-03-25 20:26:08 +01:00
|
|
|
loaded with the @code{sethi} instruction)
|
|
|
|
|
2002-02-25 05:14:45 +01:00
|
|
|
@item L
|
|
|
|
A constant in the range supported by @code{movcc} instructions
|
|
|
|
|
|
|
|
@item M
|
|
|
|
A constant in the range supported by @code{movrcc} instructions
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Same as @samp{K}, except that it verifies that bits that are not in the
|
2002-06-27 19:19:06 +02:00
|
|
|
lower 32-bit range are all zero. Must be used instead of @samp{K} for
|
2002-02-25 05:14:45 +01:00
|
|
|
modes wider than @code{SImode}
|
|
|
|
|
2003-06-04 08:52:17 +02:00
|
|
|
@item O
|
|
|
|
The constant 4096
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item G
|
|
|
|
Floating-point zero
|
|
|
|
|
|
|
|
@item H
|
2001-04-28 10:54:31 +02:00
|
|
|
Signed 13-bit constant, sign-extended to 32 or 64 bits
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item Q
|
sparc.c (fp_sethi_p, [...]): New functions.
* config/sparc/sparc.c (fp_sethi_p, fp_mov_p, fp_high_losum_p):
New functions.
* config/sparc/sparc-protos.h: Add them.
* config/sparc/sparc.h: Add them to PREDICATE_CODES.
(EXTRA_CONSTRAINT_BASE): New macro, handling Q, R, and S
constraints which use those helpers.
(EXTRA_CONSTRAINT): Use this new macro.
* md.texi: Update sparc target constraints documentation.
* config/sparc/sparc.md (clear_sf, clear_sfp, movsf_const_intreg,
movsf_const_high, movsf_const_lo, movsf_insn): Delete.
(movsf_insn_novis_liveg0, movsf_insn_novis_noliveg0,
movsf_insn_vis, movsf_lo_sum, movsf_high): New patterns.
(movsf high/lo_sum split): Rework for new patterns.
(movsf expander): Allow storing fp_zero to memory if ! live_g0.
From-SVN: r30857
1999-12-10 13:08:51 +01:00
|
|
|
Floating-point constant whose integral representation can
|
|
|
|
be moved into an integer register using a single sethi
|
|
|
|
instruction
|
|
|
|
|
|
|
|
@item R
|
|
|
|
Floating-point constant whose integral representation can
|
|
|
|
be moved into an integer register using a single mov
|
|
|
|
instruction
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item S
|
sparc.c (fp_sethi_p, [...]): New functions.
* config/sparc/sparc.c (fp_sethi_p, fp_mov_p, fp_high_losum_p):
New functions.
* config/sparc/sparc-protos.h: Add them.
* config/sparc/sparc.h: Add them to PREDICATE_CODES.
(EXTRA_CONSTRAINT_BASE): New macro, handling Q, R, and S
constraints which use those helpers.
(EXTRA_CONSTRAINT): Use this new macro.
* md.texi: Update sparc target constraints documentation.
* config/sparc/sparc.md (clear_sf, clear_sfp, movsf_const_intreg,
movsf_const_high, movsf_const_lo, movsf_insn): Delete.
(movsf_insn_novis_liveg0, movsf_insn_novis_noliveg0,
movsf_insn_vis, movsf_lo_sum, movsf_high): New patterns.
(movsf high/lo_sum split): Rework for new patterns.
(movsf expander): Allow storing fp_zero to memory if ! live_g0.
From-SVN: r30857
1999-12-10 13:08:51 +01:00
|
|
|
Floating-point constant whose integral representation can
|
|
|
|
be moved into an integer register using a high/lo_sum
|
|
|
|
instruction sequence
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item T
|
|
|
|
Memory address aligned to an 8-byte boundary
|
|
|
|
|
|
|
|
@item U
|
|
|
|
Even register
|
1999-12-21 11:45:28 +01:00
|
|
|
|
re PR target/6082 (memory model wrong for FreeBSD/sparc64)
2002-04-08 David S. Miller <davem@redhat.com>
PR target/6082
* config/sparc/freebsd.h (SPARC_DEFAULT_CMODEL): Set to CM_MEDLOW
Make init_priority work on Sparc when using GNU ld.
* config/sparc/linux.h, config/sparc/linux64.h,
config/sparc/netbsd-elf.h, config/sparc/freebsd.h
(CTORS_SECTION_ASM_OP, DTORS_SECTION_ASM_OP): Undefine.
* config/sparc/sol2-gld.h: New file to do the same.
* config.gcc (sparc*-*-solaris2*): If gnu_ld=yes add
sparc/sol2-gld.h to tm_file.
PR optimization/4328
* config/sparc/sparc.h (EXTRA_CONSTRAINT): Add new constraint 'W'.
* doc/md.texi: Document it.
* config/sparc/sparc.md (movdi_insn_sp64_novis,
movdi_insn_sp64_vis, movdf_insn_sp32, movdf_insn_v9only_novis,
movdf_insn_v9only_vis, movdf_insn_sp64_novis,
movdf_insn_sp64_vis): Use it as MEM constraing with 'e' registers.
* config/sparc/sparc.c (mem_min_alignment): Fix comment.
From-SVN: r52031
2002-04-08 19:20:48 +02:00
|
|
|
@item W
|
2004-11-09 18:06:03 +01:00
|
|
|
Memory address for @samp{e} constraint registers
|
|
|
|
|
|
|
|
@item Y
|
|
|
|
Vector zero
|
re PR target/6082 (memory model wrong for FreeBSD/sparc64)
2002-04-08 David S. Miller <davem@redhat.com>
PR target/6082
* config/sparc/freebsd.h (SPARC_DEFAULT_CMODEL): Set to CM_MEDLOW
Make init_priority work on Sparc when using GNU ld.
* config/sparc/linux.h, config/sparc/linux64.h,
config/sparc/netbsd-elf.h, config/sparc/freebsd.h
(CTORS_SECTION_ASM_OP, DTORS_SECTION_ASM_OP): Undefine.
* config/sparc/sol2-gld.h: New file to do the same.
* config.gcc (sparc*-*-solaris2*): If gnu_ld=yes add
sparc/sol2-gld.h to tm_file.
PR optimization/4328
* config/sparc/sparc.h (EXTRA_CONSTRAINT): Add new constraint 'W'.
* doc/md.texi: Document it.
* config/sparc/sparc.md (movdi_insn_sp64_novis,
movdi_insn_sp64_vis, movdf_insn_sp32, movdf_insn_v9only_novis,
movdf_insn_v9only_vis, movdf_insn_sp64_novis,
movdf_insn_sp64_vis): Use it as MEM constraing with 'e' registers.
* config/sparc/sparc.c (mem_min_alignment): Fix comment.
From-SVN: r52031
2002-04-08 19:20:48 +02:00
|
|
|
|
1999-12-21 11:45:28 +01:00
|
|
|
@end table
|
|
|
|
|
2006-11-21 02:35:42 +01:00
|
|
|
@item SPU---@file{config/spu/spu.h}
|
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
|
|
|
|
|
|
|
|
@item c
|
|
|
|
An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
|
|
|
|
|
|
|
|
@item d
|
|
|
|
An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
|
|
|
|
|
|
|
|
@item f
|
|
|
|
An immediate which can be loaded with @code{fsmbi}.
|
|
|
|
|
|
|
|
@item A
|
|
|
|
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
|
|
|
|
|
|
|
|
@item B
|
|
|
|
An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
|
|
|
|
|
|
|
|
@item C
|
|
|
|
An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
|
|
|
|
|
|
|
|
@item D
|
|
|
|
An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
|
|
|
|
|
|
|
|
@item I
|
|
|
|
A constant in the range [-64, 63] for shift/rotate instructions.
|
|
|
|
|
|
|
|
@item J
|
|
|
|
An unsigned 7-bit constant for conversion/nop/channel instructions.
|
|
|
|
|
|
|
|
@item K
|
|
|
|
A signed 10-bit constant for most arithmetic instructions.
|
|
|
|
|
|
|
|
@item M
|
|
|
|
A signed 16 bit immediate for @code{stop}.
|
|
|
|
|
|
|
|
@item N
|
|
|
|
An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
|
|
|
|
|
|
|
|
@item O
|
|
|
|
An unsigned 7-bit constant whose 3 least significant bits are 0.
|
|
|
|
|
|
|
|
@item P
|
|
|
|
An unsigned 3-bit constant for 16-byte rotates and shifts
|
|
|
|
|
|
|
|
@item R
|
|
|
|
Call operand, reg, for indirect calls
|
|
|
|
|
|
|
|
@item S
|
|
|
|
Call operand, symbol, for relative calls.
|
|
|
|
|
|
|
|
@item T
|
|
|
|
Call operand, const_int, for absolute calls.
|
|
|
|
|
|
|
|
@item U
|
|
|
|
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
|
|
|
|
|
|
|
|
@item W
|
|
|
|
An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
|
|
|
|
|
|
|
|
@item Y
|
|
|
|
An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
|
|
|
|
|
|
|
|
@item Z
|
|
|
|
An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item S/390 and zSeries---@file{config/s390/s390.h}
|
2001-07-31 08:38:29 +02:00
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
Address register (general purpose register except r0)
|
|
|
|
|
2004-11-01 19:50:20 +01:00
|
|
|
@item c
|
|
|
|
Condition code register
|
|
|
|
|
2001-07-31 08:38:29 +02:00
|
|
|
@item d
|
|
|
|
Data register (arbitrary general purpose register)
|
|
|
|
|
|
|
|
@item f
|
|
|
|
Floating-point register
|
|
|
|
|
|
|
|
@item I
|
|
|
|
Unsigned 8-bit constant (0--255)
|
|
|
|
|
|
|
|
@item J
|
|
|
|
Unsigned 12-bit constant (0--4095)
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Signed 16-bit constant (@minus{}32768--32767)
|
|
|
|
|
|
|
|
@item L
|
s390.md ("tmdi_reg", [...]): Insns now use multiple letter constraints.
2003-11-30 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("tmdi_reg", "tmsi_reg", "*movdi_64", "*movdi_31",
"iordi3"): Insns now use multiple letter constraints.
("*movdi_lhi", "*movdi_lli", "*movdi_lay"): Insns deleted. They are now
covered by "*movdi_64".
("*movsi_lhi", "*movsi_lli", "*movsi_lay"): Insns deleted. They are now
covered by "*movsi_zarch" and "*movsi_esa".
("*movsi_zarch", "*movsi_!zarch"): New insns.
("*llgt_sisi_split", "*llgt_didi_split"): Insns deleted. Now covered
by "*andsi3_zarch" and "anddi3".
("*anddi3_ni"): Insn merged with "anddi3".
("*andsi3_ni"): Insn merged with "*andsi3_zarch".
("*andsi3_zarch", "*andsi3_esa"): New insns.
("*iordi3_oi"): Insn merged with "iordi3".
("*iorsi3_oi"): Insn merged with "*iorsi3_zarch".
("*iorsi3_zarch", "*iorsi3_esa"): New insns.
* config/s390/s390.c (s390_single_qi, s390_single_hi): Functions
merged to s390_single_part.
(s390_single_part): New function.
NOTE: Semantics have changed a bit. Now the value of the part must
be different from the others to get a non-negative return value.
(s390_extract_qi, s390_extract_hi): Functions merged to
s390_extract_part.
(s390_extract_part, s390_extra_constraint_str,
s390_const_ok_for_constraint_p): New functions. The L constraint got a
new meaning and the N constraint was added as a multiple letter
constraint.
(s390_extra_constraint): Function deleted.
(print_operand): New output modifier 'i' and 'j' added.
All uses of CONST_OK_FOR_LETTER_P were replaced by
CONST_OK_FOR_CONSTRAINT_P.
* config/s390/s390-protos.h: Function prototypes adapted.
* doc/md.texi: Documentation for new constraint letters added.
From-SVN: r74061
2003-11-30 16:51:36 +01:00
|
|
|
Value appropriate as displacement.
|
|
|
|
@table @code
|
|
|
|
@item (0..4095)
|
|
|
|
for short displacement
|
|
|
|
@item (-524288..524287)
|
|
|
|
for long displacement
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@item M
|
|
|
|
Constant integer with a value of 0x7fffffff.
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Multiple letter constraint followed by 4 parameter letters.
|
|
|
|
@table @code
|
|
|
|
@item 0..9:
|
|
|
|
number of the part counting from most to least significant
|
|
|
|
@item H,Q:
|
|
|
|
mode of the part
|
|
|
|
@item D,S,H:
|
|
|
|
mode of the containing operand
|
|
|
|
@item 0,F:
|
contrib.texi, [...]: Improve Texinfo formatting.
* doc/contrib.texi, doc/cpp.texi, doc/cppopts.texi,
doc/extend.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/sourcebuild.texi, doc/tm.texi: Improve Texinfo formatting.
From-SVN: r89725
2004-10-28 03:00:31 +02:00
|
|
|
value of the other parts (F---all bits set)
|
s390.md ("tmdi_reg", [...]): Insns now use multiple letter constraints.
2003-11-30 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("tmdi_reg", "tmsi_reg", "*movdi_64", "*movdi_31",
"iordi3"): Insns now use multiple letter constraints.
("*movdi_lhi", "*movdi_lli", "*movdi_lay"): Insns deleted. They are now
covered by "*movdi_64".
("*movsi_lhi", "*movsi_lli", "*movsi_lay"): Insns deleted. They are now
covered by "*movsi_zarch" and "*movsi_esa".
("*movsi_zarch", "*movsi_!zarch"): New insns.
("*llgt_sisi_split", "*llgt_didi_split"): Insns deleted. Now covered
by "*andsi3_zarch" and "anddi3".
("*anddi3_ni"): Insn merged with "anddi3".
("*andsi3_ni"): Insn merged with "*andsi3_zarch".
("*andsi3_zarch", "*andsi3_esa"): New insns.
("*iordi3_oi"): Insn merged with "iordi3".
("*iorsi3_oi"): Insn merged with "*iorsi3_zarch".
("*iorsi3_zarch", "*iorsi3_esa"): New insns.
* config/s390/s390.c (s390_single_qi, s390_single_hi): Functions
merged to s390_single_part.
(s390_single_part): New function.
NOTE: Semantics have changed a bit. Now the value of the part must
be different from the others to get a non-negative return value.
(s390_extract_qi, s390_extract_hi): Functions merged to
s390_extract_part.
(s390_extract_part, s390_extra_constraint_str,
s390_const_ok_for_constraint_p): New functions. The L constraint got a
new meaning and the N constraint was added as a multiple letter
constraint.
(s390_extra_constraint): Function deleted.
(print_operand): New output modifier 'i' and 'j' added.
All uses of CONST_OK_FOR_LETTER_P were replaced by
CONST_OK_FOR_CONSTRAINT_P.
* config/s390/s390-protos.h: Function prototypes adapted.
* doc/md.texi: Documentation for new constraint letters added.
From-SVN: r74061
2003-11-30 16:51:36 +01:00
|
|
|
@end table
|
|
|
|
The constraint matches if the specified part of a constant
|
|
|
|
has a value different from it's other parts.
|
2001-07-31 08:38:29 +02:00
|
|
|
|
|
|
|
@item Q
|
s390.md ("tmdi_reg", [...]): Insns now use multiple letter constraints.
2003-11-30 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("tmdi_reg", "tmsi_reg", "*movdi_64", "*movdi_31",
"iordi3"): Insns now use multiple letter constraints.
("*movdi_lhi", "*movdi_lli", "*movdi_lay"): Insns deleted. They are now
covered by "*movdi_64".
("*movsi_lhi", "*movsi_lli", "*movsi_lay"): Insns deleted. They are now
covered by "*movsi_zarch" and "*movsi_esa".
("*movsi_zarch", "*movsi_!zarch"): New insns.
("*llgt_sisi_split", "*llgt_didi_split"): Insns deleted. Now covered
by "*andsi3_zarch" and "anddi3".
("*anddi3_ni"): Insn merged with "anddi3".
("*andsi3_ni"): Insn merged with "*andsi3_zarch".
("*andsi3_zarch", "*andsi3_esa"): New insns.
("*iordi3_oi"): Insn merged with "iordi3".
("*iorsi3_oi"): Insn merged with "*iorsi3_zarch".
("*iorsi3_zarch", "*iorsi3_esa"): New insns.
* config/s390/s390.c (s390_single_qi, s390_single_hi): Functions
merged to s390_single_part.
(s390_single_part): New function.
NOTE: Semantics have changed a bit. Now the value of the part must
be different from the others to get a non-negative return value.
(s390_extract_qi, s390_extract_hi): Functions merged to
s390_extract_part.
(s390_extract_part, s390_extra_constraint_str,
s390_const_ok_for_constraint_p): New functions. The L constraint got a
new meaning and the N constraint was added as a multiple letter
constraint.
(s390_extra_constraint): Function deleted.
(print_operand): New output modifier 'i' and 'j' added.
All uses of CONST_OK_FOR_LETTER_P were replaced by
CONST_OK_FOR_CONSTRAINT_P.
* config/s390/s390-protos.h: Function prototypes adapted.
* doc/md.texi: Documentation for new constraint letters added.
From-SVN: r74061
2003-11-30 16:51:36 +01:00
|
|
|
Memory reference without index register and with short displacement.
|
|
|
|
|
|
|
|
@item R
|
|
|
|
Memory reference with index register and short displacement.
|
2001-07-31 08:38:29 +02:00
|
|
|
|
|
|
|
@item S
|
s390.md ("tmdi_reg", [...]): Insns now use multiple letter constraints.
2003-11-30 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("tmdi_reg", "tmsi_reg", "*movdi_64", "*movdi_31",
"iordi3"): Insns now use multiple letter constraints.
("*movdi_lhi", "*movdi_lli", "*movdi_lay"): Insns deleted. They are now
covered by "*movdi_64".
("*movsi_lhi", "*movsi_lli", "*movsi_lay"): Insns deleted. They are now
covered by "*movsi_zarch" and "*movsi_esa".
("*movsi_zarch", "*movsi_!zarch"): New insns.
("*llgt_sisi_split", "*llgt_didi_split"): Insns deleted. Now covered
by "*andsi3_zarch" and "anddi3".
("*anddi3_ni"): Insn merged with "anddi3".
("*andsi3_ni"): Insn merged with "*andsi3_zarch".
("*andsi3_zarch", "*andsi3_esa"): New insns.
("*iordi3_oi"): Insn merged with "iordi3".
("*iorsi3_oi"): Insn merged with "*iorsi3_zarch".
("*iorsi3_zarch", "*iorsi3_esa"): New insns.
* config/s390/s390.c (s390_single_qi, s390_single_hi): Functions
merged to s390_single_part.
(s390_single_part): New function.
NOTE: Semantics have changed a bit. Now the value of the part must
be different from the others to get a non-negative return value.
(s390_extract_qi, s390_extract_hi): Functions merged to
s390_extract_part.
(s390_extract_part, s390_extra_constraint_str,
s390_const_ok_for_constraint_p): New functions. The L constraint got a
new meaning and the N constraint was added as a multiple letter
constraint.
(s390_extra_constraint): Function deleted.
(print_operand): New output modifier 'i' and 'j' added.
All uses of CONST_OK_FOR_LETTER_P were replaced by
CONST_OK_FOR_CONSTRAINT_P.
* config/s390/s390-protos.h: Function prototypes adapted.
* doc/md.texi: Documentation for new constraint letters added.
From-SVN: r74061
2003-11-30 16:51:36 +01:00
|
|
|
Memory reference without index register but with long displacement.
|
|
|
|
|
|
|
|
@item T
|
|
|
|
Memory reference with index register and long displacement.
|
|
|
|
|
|
|
|
@item U
|
|
|
|
Pointer with short displacement.
|
|
|
|
|
|
|
|
@item W
|
|
|
|
Pointer with long displacement.
|
|
|
|
|
|
|
|
@item Y
|
|
|
|
Shift count operand.
|
2001-07-31 08:38:29 +02:00
|
|
|
|
|
|
|
@end table
|
|
|
|
|
2006-10-19 11:19:21 +02:00
|
|
|
@item Score family---@file{config/score/score.h}
|
|
|
|
@table @code
|
|
|
|
@item d
|
|
|
|
Registers from r0 to r32.
|
|
|
|
|
|
|
|
@item e
|
|
|
|
Registers from r0 to r16.
|
|
|
|
|
|
|
|
@item t
|
|
|
|
r8---r11 or r22---r27 registers.
|
|
|
|
|
|
|
|
@item h
|
|
|
|
hi register.
|
|
|
|
|
|
|
|
@item l
|
|
|
|
lo register.
|
|
|
|
|
|
|
|
@item x
|
|
|
|
hi + lo register.
|
|
|
|
|
|
|
|
@item q
|
|
|
|
cnt register.
|
|
|
|
|
|
|
|
@item y
|
|
|
|
lcb register.
|
|
|
|
|
|
|
|
@item z
|
|
|
|
scb register.
|
|
|
|
|
|
|
|
@item a
|
|
|
|
cnt + lcb + scb register.
|
|
|
|
|
|
|
|
@item c
|
|
|
|
cr0---cr15 register.
|
|
|
|
|
|
|
|
@item b
|
|
|
|
cp1 registers.
|
|
|
|
|
|
|
|
@item f
|
|
|
|
cp2 registers.
|
|
|
|
|
|
|
|
@item i
|
|
|
|
cp3 registers.
|
|
|
|
|
|
|
|
@item j
|
|
|
|
cp1 + cp2 + cp3 registers.
|
|
|
|
|
|
|
|
@item I
|
2007-04-04 03:49:10 +02:00
|
|
|
High 16-bit constant (32-bit constant with 16 LSBs zero).
|
2006-10-19 11:19:21 +02:00
|
|
|
|
|
|
|
@item J
|
|
|
|
Unsigned 5 bit integer (in the range 0 to 31).
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Unsigned 16 bit integer (in the range 0 to 65535).
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Signed 16 bit integer (in the range @minus{}32768 to 32767).
|
|
|
|
|
|
|
|
@item M
|
|
|
|
Unsigned 14 bit integer (in the range 0 to 16383).
|
|
|
|
|
|
|
|
@item N
|
|
|
|
Signed 14 bit integer (in the range @minus{}8192 to 8191).
|
|
|
|
|
|
|
|
@item Z
|
|
|
|
Any SYMBOL_REF.
|
|
|
|
@end table
|
|
|
|
|
2006-02-26 20:32:37 +01:00
|
|
|
@item Xstormy16---@file{config/stormy16/stormy16.h}
|
2002-01-14 00:23:40 +01:00
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
Register r0.
|
|
|
|
|
|
|
|
@item b
|
|
|
|
Register r1.
|
|
|
|
|
|
|
|
@item c
|
|
|
|
Register r2.
|
|
|
|
|
|
|
|
@item d
|
|
|
|
Register r8.
|
|
|
|
|
|
|
|
@item e
|
|
|
|
Registers r0 through r7.
|
|
|
|
|
|
|
|
@item t
|
|
|
|
Registers r0 and r1.
|
|
|
|
|
|
|
|
@item y
|
|
|
|
The carry register.
|
|
|
|
|
|
|
|
@item z
|
|
|
|
Registers r8 and r9.
|
|
|
|
|
|
|
|
@item I
|
|
|
|
A constant between 0 and 3 inclusive.
|
|
|
|
|
|
|
|
@item J
|
|
|
|
A constant that has exactly one bit set.
|
|
|
|
|
|
|
|
@item K
|
|
|
|
A constant that has exactly one bit clear.
|
|
|
|
|
|
|
|
@item L
|
|
|
|
A constant between 0 and 255 inclusive.
|
|
|
|
|
|
|
|
@item M
|
2002-01-14 20:26:00 +01:00
|
|
|
A constant between @minus{}255 and 0 inclusive.
|
2002-01-14 00:23:40 +01:00
|
|
|
|
|
|
|
@item N
|
2002-01-14 20:26:00 +01:00
|
|
|
A constant between @minus{}3 and 0 inclusive.
|
2002-01-14 00:23:40 +01:00
|
|
|
|
|
|
|
@item O
|
|
|
|
A constant between 1 and 4 inclusive.
|
|
|
|
|
|
|
|
@item P
|
2002-01-14 20:26:00 +01:00
|
|
|
A constant between @minus{}4 and @minus{}1 inclusive.
|
2002-01-14 00:23:40 +01:00
|
|
|
|
|
|
|
@item Q
|
|
|
|
A memory reference that is a stack push.
|
|
|
|
|
|
|
|
@item R
|
|
|
|
A memory reference that is a stack pop.
|
|
|
|
|
|
|
|
@item S
|
2003-06-23 18:01:42 +02:00
|
|
|
A memory reference that refers to a constant address of known value.
|
2002-01-14 00:23:40 +01:00
|
|
|
|
|
|
|
@item T
|
|
|
|
The register indicated by Rx (not implemented yet).
|
|
|
|
|
|
|
|
@item U
|
|
|
|
A constant that is not between 2 and 15 inclusive.
|
|
|
|
|
2003-06-10 21:40:47 +02:00
|
|
|
@item Z
|
|
|
|
The constant 0.
|
|
|
|
|
2002-01-14 00:23:40 +01:00
|
|
|
@end table
|
|
|
|
|
2006-11-21 22:49:26 +01:00
|
|
|
@item Xtensa---@file{config/xtensa/constraints.md}
|
2002-01-23 22:03:53 +01:00
|
|
|
@table @code
|
|
|
|
@item a
|
|
|
|
General-purpose 32-bit register
|
|
|
|
|
|
|
|
@item b
|
|
|
|
One-bit boolean register
|
|
|
|
|
|
|
|
@item A
|
|
|
|
MAC16 40-bit accumulator register
|
|
|
|
|
|
|
|
@item I
|
|
|
|
Signed 12-bit integer constant, for use in MOVI instructions
|
|
|
|
|
|
|
|
@item J
|
|
|
|
Signed 8-bit integer constant, for use in ADDI instructions
|
|
|
|
|
|
|
|
@item K
|
|
|
|
Integer constant valid for BccI instructions
|
|
|
|
|
|
|
|
@item L
|
|
|
|
Unsigned constant valid for BccUI instructions
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@ifset INTERNALS
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@node Define Constraints
|
|
|
|
@subsection Defining Machine-Specific Constraints
|
|
|
|
@cindex defining constraints
|
|
|
|
@cindex constraints, defining
|
|
|
|
|
|
|
|
Machine-specific constraints fall into two categories: register and
|
|
|
|
non-register constraints. Within the latter category, constraints
|
|
|
|
which allow subsets of all possible memory or address operands should
|
|
|
|
be specially marked, to give @code{reload} more information.
|
|
|
|
|
|
|
|
Machine-specific constraints can be given names of arbitrary length,
|
|
|
|
but they must be entirely composed of letters, digits, underscores
|
|
|
|
(@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
|
|
|
|
must begin with a letter or underscore.
|
|
|
|
|
|
|
|
In order to avoid ambiguity in operand constraint strings, no
|
|
|
|
constraint can have a name that begins with any other constraint's
|
|
|
|
name. For example, if @code{x} is defined as a constraint name,
|
|
|
|
@code{xy} may not be, and vice versa. As a consequence of this rule,
|
|
|
|
no constraint may begin with one of the generic constraint letters:
|
|
|
|
@samp{E F V X g i m n o p r s}.
|
|
|
|
|
|
|
|
Register constraints correspond directly to register classes.
|
|
|
|
@xref{Register Classes}. There is thus not much flexibility in their
|
|
|
|
definitions.
|
|
|
|
|
|
|
|
@deffn {MD Expression} define_register_constraint name regclass docstring
|
|
|
|
All three arguments are string constants.
|
|
|
|
@var{name} is the name of the constraint, as it will appear in
|
2007-04-03 10:31:27 +02:00
|
|
|
@code{match_operand} expressions. If @var{name} is a multi-letter
|
|
|
|
constraint its length shall be the same for all constraints starting
|
|
|
|
with the same letter. @var{regclass} can be either the
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
name of the corresponding register class (@pxref{Register Classes}),
|
|
|
|
or a C expression which evaluates to the appropriate register class.
|
|
|
|
If it is an expression, it must have no side effects, and it cannot
|
|
|
|
look at the operand. The usual use of expressions is to map some
|
|
|
|
register constraints to @code{NO_REGS} when the register class
|
|
|
|
is not available on a given subarchitecture.
|
|
|
|
|
|
|
|
@var{docstring} is a sentence documenting the meaning of the
|
|
|
|
constraint. Docstrings are explained further below.
|
|
|
|
@end deffn
|
|
|
|
|
|
|
|
Non-register constraints are more like predicates: the constraint
|
|
|
|
definition gives a Boolean expression which indicates whether the
|
|
|
|
constraint matches.
|
|
|
|
|
|
|
|
@deffn {MD Expression} define_constraint name docstring exp
|
|
|
|
The @var{name} and @var{docstring} arguments are the same as for
|
|
|
|
@code{define_register_constraint}, but note that the docstring comes
|
|
|
|
immediately after the name for these expressions. @var{exp} is an RTL
|
|
|
|
expression, obeying the same rules as the RTL expressions in predicate
|
|
|
|
definitions. @xref{Defining Predicates}, for details. If it
|
|
|
|
evaluates true, the constraint matches; if it evaluates false, it
|
|
|
|
doesn't. Constraint expressions should indicate which RTL codes they
|
|
|
|
might match, just like predicate expressions.
|
|
|
|
|
|
|
|
@code{match_test} C expressions have access to the
|
|
|
|
following variables:
|
|
|
|
|
|
|
|
@table @var
|
|
|
|
@item op
|
|
|
|
The RTL object defining the operand.
|
|
|
|
@item mode
|
|
|
|
The machine mode of @var{op}.
|
|
|
|
@item ival
|
|
|
|
@samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
|
|
|
|
@item hval
|
|
|
|
@samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
|
|
|
|
@code{const_double}.
|
|
|
|
@item lval
|
|
|
|
@samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
|
|
|
|
@code{const_double}.
|
|
|
|
@item rval
|
|
|
|
@samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
|
2006-02-28 07:04:09 +01:00
|
|
|
@code{const_double}.
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@end table
|
|
|
|
|
|
|
|
The @var{*val} variables should only be used once another piece of the
|
|
|
|
expression has verified that @var{op} is the appropriate kind of RTL
|
|
|
|
object.
|
|
|
|
@end deffn
|
|
|
|
|
|
|
|
Most non-register constraints should be defined with
|
|
|
|
@code{define_constraint}. The remaining two definition expressions
|
|
|
|
are only appropriate for constraints that should be handled specially
|
|
|
|
by @code{reload} if they fail to match.
|
|
|
|
|
|
|
|
@deffn {MD Expression} define_memory_constraint name docstring exp
|
|
|
|
Use this expression for constraints that match a subset of all memory
|
|
|
|
operands: that is, @code{reload} can make them match by converting the
|
|
|
|
operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
|
|
|
|
base register (from the register class specified by
|
|
|
|
@code{BASE_REG_CLASS}, @pxref{Register Classes}).
|
|
|
|
|
|
|
|
For example, on the S/390, some instructions do not accept arbitrary
|
|
|
|
memory references, but only those that do not make use of an index
|
|
|
|
register. The constraint letter @samp{Q} is defined to represent a
|
|
|
|
memory address of this type. If @samp{Q} is defined with
|
|
|
|
@code{define_memory_constraint}, a @samp{Q} constraint can handle any
|
|
|
|
memory operand, because @code{reload} knows it can simply copy the
|
|
|
|
memory address into a base register if required. This is analogous to
|
|
|
|
the way a @samp{o} constraint can handle any memory operand.
|
|
|
|
|
|
|
|
The syntax and semantics are otherwise identical to
|
|
|
|
@code{define_constraint}.
|
|
|
|
@end deffn
|
|
|
|
|
|
|
|
@deffn {MD Expression} define_address_constraint name docstring exp
|
|
|
|
Use this expression for constraints that match a subset of all address
|
|
|
|
operands: that is, @code{reload} can make the constraint match by
|
|
|
|
converting the operand to the form @samp{@w{(reg @var{X})}}, again
|
|
|
|
with @var{X} a base register.
|
|
|
|
|
|
|
|
Constraints defined with @code{define_address_constraint} can only be
|
|
|
|
used with the @code{address_operand} predicate, or machine-specific
|
|
|
|
predicates that work the same way. They are treated analogously to
|
|
|
|
the generic @samp{p} constraint.
|
|
|
|
|
|
|
|
The syntax and semantics are otherwise identical to
|
|
|
|
@code{define_constraint}.
|
|
|
|
@end deffn
|
|
|
|
|
|
|
|
For historical reasons, names beginning with the letters @samp{G H}
|
|
|
|
are reserved for constraints that match only @code{const_double}s, and
|
|
|
|
names beginning with the letters @samp{I J K L M N O P} are reserved
|
|
|
|
for constraints that match only @code{const_int}s. This may change in
|
|
|
|
the future. For the time being, constraints with these names must be
|
|
|
|
written in a stylized form, so that @code{genpreds} can tell you did
|
|
|
|
it correctly:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_constraint "[@var{GHIJKLMNOP}]@dots{}"
|
|
|
|
"@var{doc}@dots{}"
|
|
|
|
(and (match_code "const_int") ; @r{@code{const_double} for G/H}
|
|
|
|
@var{condition}@dots{})) ; @r{usually a @code{match_test}}
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
@c the semicolons line up in the formatted manual
|
|
|
|
|
|
|
|
It is fine to use names beginning with other letters for constraints
|
|
|
|
that match @code{const_double}s or @code{const_int}s.
|
|
|
|
|
|
|
|
Each docstring in a constraint definition should be one or more complete
|
|
|
|
sentences, marked up in Texinfo format. @emph{They are currently unused.}
|
|
|
|
In the future they will be copied into the GCC manual, in @ref{Machine
|
|
|
|
Constraints}, replacing the hand-maintained tables currently found in
|
|
|
|
that section. Also, in the future the compiler may use this to give
|
|
|
|
more helpful diagnostics when poor choice of @code{asm} constraints
|
|
|
|
causes a reload failure.
|
|
|
|
|
|
|
|
If you put the pseudo-Texinfo directive @samp{@@internal} at the
|
|
|
|
beginning of a docstring, then (in the future) it will appear only in
|
|
|
|
the internals manual's version of the machine-specific constraint tables.
|
|
|
|
Use this for constraints that should not appear in @code{asm} statements.
|
|
|
|
|
|
|
|
@node C Constraint Interface
|
|
|
|
@subsection Testing constraints from C
|
|
|
|
@cindex testing constraints
|
|
|
|
@cindex constraints, testing
|
|
|
|
|
|
|
|
It is occasionally useful to test a constraint from C code rather than
|
|
|
|
implicitly via the constraint string in a @code{match_operand}. The
|
|
|
|
generated file @file{tm_p.h} declares a few interfaces for working
|
|
|
|
with machine-specific constraints. None of these interfaces work with
|
|
|
|
the generic constraints described in @ref{Simple Constraints}. This
|
|
|
|
may change in the future.
|
|
|
|
|
|
|
|
@strong{Warning:} @file{tm_p.h} may declare other functions that
|
|
|
|
operate on constraints, besides the ones documented here. Do not use
|
|
|
|
those functions from machine-dependent code. They exist to implement
|
|
|
|
the old constraint interface that machine-independent components of
|
|
|
|
the compiler still expect. They will change or disappear in the
|
|
|
|
future.
|
|
|
|
|
|
|
|
Some valid constraint names are not valid C identifiers, so there is a
|
|
|
|
mangling scheme for referring to them from C@. Constraint names that
|
|
|
|
do not contain angle brackets or underscores are left unchanged.
|
|
|
|
Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
|
|
|
|
each @samp{>} with @samp{_g}. Here are some examples:
|
|
|
|
|
|
|
|
@c the @c's prevent double blank lines in the printed manual.
|
|
|
|
@example
|
|
|
|
@multitable {Original} {Mangled}
|
2006-03-01 05:43:47 +01:00
|
|
|
@item @strong{Original} @tab @strong{Mangled} @c
|
* rtl.def (define_constraint, define_register_constraint)
(define_memory_constraint, define_address_constraint): New MD forms.
* gensupport.c (process_rtx): Put define_constraint etc on the
predicate queue.
* genpreds.c (process_define_predicate): Adjust comment. Validate
the name, and call validate_exp to validate the expression.
(mark_mode_tests, write_extract_subexp): Can assume correct input.
(write_predicate_expr): Likewise. NAME argument no longer necessary;
all callers changed.
(validate_exp, needs_variable, struct constraint_data)
(constraints_by_letter_table, first_constraint, last_constraint_ptr)
(FOR_ALL_CONSTRAINTS, generic_constraint_letters, const_int_constraints)
(const_dbl_constraints, constraint_max_namelen)
(have_register_constraints, have_memory_constraints)
(have_address_constraints, have_address_constraints)
(have_extra_constraints, have_const_int_constraints)
(have_const_dbl_constraints, mangle, add_constraint)
(process_define_constraint, process_define_register_constraint)
(write_enum_constraint_num, write_lookup_constraint)
(write_insn_constraint_len, write_regclass_for_constraint)
(write_constraint_satisfied_p, write_insn_const_int_ok_for_constraint)
(write_insn_extra_memory_constraint)
(write_insn_extra_address_constraint)
(write_satisfies_constraint_fns): New.
(write_tm_preds_h): If we have new-style constraint definitions,
prototype the functions generated from them, and define the
old constraint interface (still used by generic code) in terms of
those functions.
(write_insn_preds_c): If we have new-style constraint definitions,
generate all relevant functions from those definitions.
(main): Handle define_constraint etc.
* genoutput.c (struct constraint_data, indep_constraints)
(mdep_constraint_letters, constraints_by_letter_table, note_constraint)
(mdep_constraint_len): New data structures and functions, defined
#ifdef USE_MD_CONSTRAINTS.
(check_constraint_len): Don't define #ifdef USE_MD_CONSTRAINTS.
(validate_insn_alternatives): If USE_MD_CONSTRAINTS is defined,
use new logic to validate operand constraints against constraint
definitions.
(main): Process define_constraint etc. if USE_MD_CONSTRAINTS is
defined.
* defaults.h: If none of the old-style constraint macros are
defined, define USE_MD_CONSTRAINTS; do not provide defaults for any
old-style macros; and poison REG_CLASS_FROM_LETTER,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, and
EXTRA_CONSTRAINT.
* recog.c (reg_fits_class_p): If cl is NO_REGS, return 0 immediately.
* doc/md.texi: Document new constraint-definition mechanism and the
C interface it provides. Remove references to old mechanism
elsewhere in the document.
(Machine Constraints): Use pathnames relative to gcc directory,
i.e. config/ARCH/FILE. Change i386 section to refer to
config/i386/predicates.md; update that section to match docstrings.
* doc/tm.texi: Move all documentation of the old constraint-
definition macros to their own section, clearly mark as obsolete.
* config/i386/predicates.md (R, q, Q, l, a, b, c, d, S, D, A, f, t)
(u, y, x, Y, I, J, K, L, M, N, O, G, C, e, Z): New constraint
definitions.
* config/i386/i386.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P)
(CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete.
* config/i386/i386.md (*movdf_nointeger): Remove stray 'H' from
constraint strings.
(splits and peepholes): Use satisfies_constraint_*.
* config/i386/i386.c (memory_address_length)
(ix86_attr_length_immediate_default): Use satisfies_constraint_*.
From-SVN: r111508
2006-02-28 04:28:18 +01:00
|
|
|
@item @code{x} @tab @code{x} @c
|
|
|
|
@item @code{P42x} @tab @code{P42x} @c
|
|
|
|
@item @code{P4_x} @tab @code{P4__x} @c
|
|
|
|
@item @code{P4>x} @tab @code{P4_gx} @c
|
|
|
|
@item @code{P4>>} @tab @code{P4_g_g} @c
|
|
|
|
@item @code{P4_g>} @tab @code{P4__g_g} @c
|
|
|
|
@end multitable
|
|
|
|
@end example
|
|
|
|
|
|
|
|
Throughout this section, the variable @var{c} is either a constraint
|
|
|
|
in the abstract sense, or a constant from @code{enum constraint_num};
|
|
|
|
the variable @var{m} is a mangled constraint name (usually as part of
|
|
|
|
a larger identifier).
|
|
|
|
|
|
|
|
@deftp Enum constraint_num
|
|
|
|
For each machine-specific constraint, there is a corresponding
|
|
|
|
enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
|
|
|
|
constraint. Functions that take an @code{enum constraint_num} as an
|
|
|
|
argument expect one of these constants.
|
|
|
|
|
|
|
|
Machine-independent constraints do not have associated constants.
|
|
|
|
This may change in the future.
|
|
|
|
@end deftp
|
|
|
|
|
|
|
|
@deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
|
|
|
|
For each machine-specific, non-register constraint @var{m}, there is
|
|
|
|
one of these functions; it returns @code{true} if @var{exp} satisfies the
|
|
|
|
constraint. These functions are only visible if @file{rtl.h} was included
|
|
|
|
before @file{tm_p.h}.
|
|
|
|
@end deftypefun
|
|
|
|
|
|
|
|
@deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
|
|
|
|
Like the @code{satisfies_constraint_@var{m}} functions, but the
|
|
|
|
constraint to test is given as an argument, @var{c}. If @var{c}
|
|
|
|
specifies a register constraint, this function will always return
|
|
|
|
@code{false}.
|
|
|
|
@end deftypefun
|
|
|
|
|
|
|
|
@deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
|
|
|
|
Returns the register class associated with @var{c}. If @var{c} is not
|
|
|
|
a register constraint, or those registers are not available for the
|
|
|
|
currently selected subtarget, returns @code{NO_REGS}.
|
|
|
|
@end deftypefun
|
|
|
|
|
|
|
|
Here is an example use of @code{satisfies_constraint_@var{m}}. In
|
|
|
|
peephole optimizations (@pxref{Peephole Definitions}), operand
|
|
|
|
constraint strings are ignored, so if there are relevant constraints,
|
|
|
|
they must be tested in the C condition. In the example, the
|
|
|
|
optimization is applied if operand 2 does @emph{not} satisfy the
|
|
|
|
@samp{K} constraint. (This is a simplified version of a peephole
|
|
|
|
definition from the i386 machine description.)
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole2
|
|
|
|
[(match_scratch:SI 3 "r")
|
|
|
|
(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
(mult:SI (match_operand:SI 1 "memory_operand" "")
|
|
|
|
(match_operand:SI 2 "immediate_operand" "")))]
|
|
|
|
|
|
|
|
"!satisfies_constraint_K (operands[2])"
|
|
|
|
|
|
|
|
[(set (match_dup 3) (match_dup 1))
|
|
|
|
(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
|
|
|
|
|
|
|
|
"")
|
|
|
|
@end smallexample
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Standard Names
|
|
|
|
@section Standard Pattern Names For Generation
|
|
|
|
@cindex standard pattern names
|
|
|
|
@cindex pattern names
|
|
|
|
@cindex names, pattern
|
|
|
|
|
|
|
|
Here is a table of the instruction names that are meaningful in the RTL
|
|
|
|
generation pass of the compiler. Giving one of these names to an
|
|
|
|
instruction pattern tells the RTL generation pass that it can use the
|
1998-02-19 01:04:36 +01:00
|
|
|
pattern to accomplish a certain task.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@table @asis
|
|
|
|
@cindex @code{mov@var{m}} instruction pattern
|
|
|
|
@item @samp{mov@var{m}}
|
2003-07-31 03:32:24 +02:00
|
|
|
Here @var{m} stands for a two-letter machine mode name, in lowercase.
|
1997-03-25 20:26:08 +01:00
|
|
|
This instruction pattern moves data with that machine mode from operand
|
|
|
|
1 to operand 0. For example, @samp{movsi} moves full-word data.
|
|
|
|
|
|
|
|
If operand 0 is a @code{subreg} with mode @var{m} of a register whose
|
|
|
|
own mode is wider than @var{m}, the effect of this instruction is
|
|
|
|
to store the specified value in the part of the register that corresponds
|
2001-10-25 20:25:08 +02:00
|
|
|
to mode @var{m}. Bits outside of @var{m}, but which are within the
|
|
|
|
same target word as the @code{subreg} are undefined. Bits which are
|
|
|
|
outside the target word are left unchanged.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
This class of patterns is special in several ways. First of all, each
|
2000-04-05 23:14:53 +02:00
|
|
|
of these names up to and including full word size @emph{must} be defined,
|
|
|
|
because there is no other way to copy a datum from one place to another.
|
|
|
|
If there are patterns accepting operands in larger modes,
|
|
|
|
@samp{mov@var{m}} must be defined for integer modes of those sizes.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
Second, these patterns are not used solely in the RTL generation pass.
|
|
|
|
Even the reload pass can generate move insns to copy values from stack
|
|
|
|
slots into temporary registers. When it does so, one of the operands is
|
|
|
|
a hard register and the other is an operand that can need to be reloaded
|
|
|
|
into a register.
|
|
|
|
|
|
|
|
@findex force_reg
|
|
|
|
Therefore, when given such a pair of operands, the pattern must generate
|
|
|
|
RTL which needs no reloading and needs no temporary registers---no
|
|
|
|
registers other than the operands. For example, if you support the
|
|
|
|
pattern with a @code{define_expand}, then in such a case the
|
|
|
|
@code{define_expand} mustn't call @code{force_reg} or any other such
|
|
|
|
function which might generate new pseudo registers.
|
|
|
|
|
|
|
|
This requirement exists even for subword modes on a RISC machine where
|
|
|
|
fetching those modes from memory normally requires several insns and
|
2001-02-03 03:12:16 +01:00
|
|
|
some temporary registers.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@findex change_address
|
|
|
|
During reload a memory reference with an invalid address may be passed
|
|
|
|
as an operand. Such an address will be replaced with a valid address
|
|
|
|
later in the reload pass. In this case, nothing may be done with the
|
|
|
|
address except to use it as it stands. If it is copied, it will not be
|
|
|
|
replaced with a valid address. No attempt should be made to make such
|
|
|
|
an address into a valid address and no routine (such as
|
|
|
|
@code{change_address}) that will do so may be called. Note that
|
|
|
|
@code{general_operand} will fail when applied to such an address.
|
|
|
|
|
|
|
|
@findex reload_in_progress
|
|
|
|
The global variable @code{reload_in_progress} (which must be explicitly
|
|
|
|
declared if required) can be used to determine whether such special
|
|
|
|
handling is required.
|
|
|
|
|
|
|
|
The variety of operands that have reloads depends on the rest of the
|
|
|
|
machine description, but typically on a RISC machine these can only be
|
|
|
|
pseudo registers that did not get hard registers, while on other
|
|
|
|
machines explicit memory references will get optional reloads.
|
|
|
|
|
|
|
|
If a scratch register is required to move an object to or from memory,
|
1998-11-25 11:31:24 +01:00
|
|
|
it can be allocated using @code{gen_reg_rtx} prior to life analysis.
|
|
|
|
|
2001-08-18 23:02:44 +02:00
|
|
|
If there are cases which need scratch registers during or after reload,
|
2005-11-24 19:55:53 +01:00
|
|
|
you must provide an appropriate secondary_reload target hook.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2007-07-12 00:57:51 +02:00
|
|
|
@findex can_create_pseudo_p
|
|
|
|
The macro @code{can_create_pseudo_p} can be used to determine if it
|
1998-11-25 11:31:24 +01:00
|
|
|
is unsafe to create new pseudo registers. If this variable is nonzero, then
|
|
|
|
it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
|
|
|
|
|
1997-12-07 01:31:01 +01:00
|
|
|
The constraints on a @samp{mov@var{m}} must permit moving any hard
|
1997-03-25 20:26:08 +01:00
|
|
|
register to any other hard register provided that
|
|
|
|
@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
|
|
|
|
@code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
|
|
|
|
|
1997-12-07 01:31:01 +01:00
|
|
|
It is obligatory to support floating point @samp{mov@var{m}}
|
1997-03-25 20:26:08 +01:00
|
|
|
instructions into and out of any registers that can hold fixed point
|
|
|
|
values, because unions and structures (which have modes @code{SImode} or
|
|
|
|
@code{DImode}) can be in those registers and they may have floating
|
|
|
|
point members.
|
|
|
|
|
1997-12-07 01:31:01 +01:00
|
|
|
There may also be a need to support fixed point @samp{mov@var{m}}
|
1997-03-25 20:26:08 +01:00
|
|
|
instructions in and out of floating point registers. Unfortunately, I
|
|
|
|
have forgotten why this was so, and I don't know whether it is still
|
|
|
|
true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
|
|
|
|
floating point registers, then the constraints of the fixed point
|
1997-12-07 01:31:01 +01:00
|
|
|
@samp{mov@var{m}} instructions must be designed to avoid ever trying to
|
1997-03-25 20:26:08 +01:00
|
|
|
reload into a floating point register.
|
|
|
|
|
|
|
|
@cindex @code{reload_in} instruction pattern
|
|
|
|
@cindex @code{reload_out} instruction pattern
|
|
|
|
@item @samp{reload_in@var{m}}
|
|
|
|
@itemx @samp{reload_out@var{m}}
|
2005-11-24 19:55:53 +01:00
|
|
|
These named patterns have been obsoleted by the target hook
|
|
|
|
@code{secondary_reload}.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
Like @samp{mov@var{m}}, but used when a scratch register is required to
|
|
|
|
move between operand 0 and operand 1. Operand 2 describes the scratch
|
|
|
|
register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
|
|
|
|
macro in @pxref{Register Classes}.
|
|
|
|
|
2001-07-18 23:34:15 +02:00
|
|
|
There are special restrictions on the form of the @code{match_operand}s
|
2002-02-23 13:59:09 +01:00
|
|
|
used in these patterns. First, only the predicate for the reload
|
2001-07-19 00:02:07 +02:00
|
|
|
operand is examined, i.e., @code{reload_in} examines operand 1, but not
|
|
|
|
the predicates for operand 0 or 2. Second, there may be only one
|
2001-07-18 23:34:15 +02:00
|
|
|
alternative in the constraints. Third, only a single register class
|
|
|
|
letter may be used for the constraint; subsequent constraint letters
|
|
|
|
are ignored. As a special exception, an empty constraint string
|
|
|
|
matches the @code{ALL_REGS} register class. This may relieve ports
|
|
|
|
of the burden of defining an @code{ALL_REGS} constraint letter just
|
|
|
|
for these patterns.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{movstrict@var{m}} instruction pattern
|
|
|
|
@item @samp{movstrict@var{m}}
|
|
|
|
Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
|
|
|
|
with mode @var{m} of a register whose natural mode is wider,
|
|
|
|
the @samp{movstrict@var{m}} instruction is guaranteed not to alter
|
|
|
|
any of the register except the part which belongs to mode @var{m}.
|
|
|
|
|
2004-12-23 08:58:41 +01:00
|
|
|
@cindex @code{movmisalign@var{m}} instruction pattern
|
|
|
|
@item @samp{movmisalign@var{m}}
|
|
|
|
This variant of a move pattern is designed to load or store a value
|
|
|
|
from a memory address that is not naturally aligned for its mode.
|
|
|
|
For a store, the memory will be in operand 0; for a load, the memory
|
|
|
|
will be in operand 1. The other operand is guaranteed not to be a
|
|
|
|
memory, so that it's easy to tell whether this is a load or store.
|
|
|
|
|
|
|
|
This pattern is used by the autovectorizer, and when expanding a
|
|
|
|
@code{MISALIGNED_INDIRECT_REF} expression.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{load_multiple} instruction pattern
|
|
|
|
@item @samp{load_multiple}
|
|
|
|
Load several consecutive memory locations into consecutive registers.
|
|
|
|
Operand 0 is the first of the consecutive registers, operand 1
|
|
|
|
is the first memory location, and operand 2 is a constant: the
|
|
|
|
number of consecutive registers.
|
|
|
|
|
|
|
|
Define this only if the target machine really has such an instruction;
|
|
|
|
do not define this if the most efficient way of loading consecutive
|
|
|
|
registers from memory is to do them one at a time.
|
|
|
|
|
|
|
|
On some machines, there are restrictions as to which consecutive
|
|
|
|
registers can be stored into memory, such as particular starting or
|
|
|
|
ending register numbers or only a range of valid counts. For those
|
|
|
|
machines, use a @code{define_expand} (@pxref{Expander Definitions})
|
|
|
|
and make the pattern fail if the restrictions are not met.
|
|
|
|
|
|
|
|
Write the generated insn as a @code{parallel} with elements being a
|
|
|
|
@code{set} of one register from the appropriate memory location (you may
|
|
|
|
also need @code{use} or @code{clobber} elements). Use a
|
|
|
|
@code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
|
install.texi: Remove i386-*-isc, i860-*-bsd, m68k-altos-sysv, m68k-isi-bsd, m68k-sony-bsd entries.
2002-12-23 Larin Hennessy <larin@science.oregonstate.edu>
* doc/install.texi: Remove i386-*-isc, i860-*-bsd,
m68k-altos-sysv, m68k-isi-bsd, m68k-sony-bsd entries.
* doc/invoke.texi: Remove AMD 29K, ARM RISC/iX, Clipper, Convex,
DG/UX entries.
* doc/md.texi: Remove AMD 29K entries.
* doc/trouble.texi: Remove Alliant, DG/UX, Iris 4.0.5F, GAS
1.38.1, NewsOS, RT PC, WE32K entries.
From-SVN: r60455
2002-12-24 00:02:49 +01:00
|
|
|
@file{rs6000.md} for examples of the use of this insn pattern.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @samp{store_multiple} instruction pattern
|
|
|
|
@item @samp{store_multiple}
|
|
|
|
Similar to @samp{load_multiple}, but store several consecutive registers
|
|
|
|
into consecutive memory locations. Operand 0 is the first of the
|
|
|
|
consecutive memory locations, operand 1 is the first register, and
|
|
|
|
operand 2 is a constant: the number of consecutive registers.
|
|
|
|
|
2004-04-03 19:25:47 +02:00
|
|
|
@cindex @code{vec_set@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_set@var{m}}
|
|
|
|
Set given field in the vector value. Operand 0 is the vector to modify,
|
|
|
|
operand 1 is new value of field and operand 2 specify the field index.
|
|
|
|
|
|
|
|
@cindex @code{vec_extract@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_extract@var{m}}
|
|
|
|
Extract given field from the vector value. Operand 1 is the vector, operand 2
|
|
|
|
specify field index and operand 0 place to store value into.
|
|
|
|
|
c-tree.texi: Document new tree codes.
* doc/c-tree.texi: Document new tree codes.
* doc/md.texi: Document new optabs.
* tree-pretty-print.c (dump_generic_node): Handle print of new tree
codes.
* optabs.c (optab_for_tree_code, init_optabs): Handle new optabs.
* optabs.h (optab_index): Add new.
(vec_extract_even_optab, vec_extract_odd_optab,
vec_interleave_high_optab, vec_interleave_low_optab): New optabs.
* genopinit.c (vec_extract_even_optab, vec_extract_odd_optab,
vec_interleave_high_optab, vec_interleave_low_optab): Initialize
new optabs.
* expr.c (expand_expr_real_1): Add implementation for new tree codes.
* tree-vectorizer.c (new_stmt_vec_info): Initialize new fields.
* tree-vectorizer.h (stmt_vec_info): Add new fields for interleaving
along with macros for their access.
* tree-data-ref.h (first_location_in_loop, data_reference): Update
comment.
* tree-vect-analyze.c (toplev.h): Include.
(vect_determine_vectorization_factor): Fix indentation.
(vect_insert_into_interleaving_chain,
vect_update_interleaving_chain, vect_equal_offsets): New functions.
(vect_analyze_data_ref_dependence): Add argument for interleaving
check. Check for interleaving if it's true.
(vect_check_dependences): New function.
(vect_analyze_data_ref_dependences): Call vect_check_dependences for
every ddr. Call vect_analyze_data_ref_dependence with new argument.
(vect_update_misalignment_for_peel): Update for interleaving.
(vect_verify_datarefs_alignment): Check only first data-ref for
interleaving.
(vect_enhance_data_refs_alignment): Update for interleaving. Check
only first data-ref for interleaving.
(vect_analyze_data_ref_access): Check interleaving, update
interleaving data.
(vect_analyze_data_refs): Call compute_data_dependences_for_loop
with different parameters.
* tree.def (VEC_EXTRACT_EVEN_EXPR, VEC_EXTRACT_ODD_EXPR,
VEC_INTERLEAVE_HIGH_EXPR, VEC_INTERLEAVE_LOW_EXPR): New tree codes.
* tree-inline.c (estimate_num_insns_1): Add cases for new codes.
* tree-vect-transform.c (vect_create_addr_base_for_vector_ref):
Update step in case of interleaving.
(vect_strided_store_supported, vect_permute_store_chain): New
functions.
(vectorizable_store): Handle strided stores.
(vect_strided_load_supported, vect_permute_load_chain,
vect_transform_strided_load): New functions.
(vectorizable_load): Handle strided loads.
(vect_transform_stmt): Add argument. Handle strided stores. Check
that vectorized stmt exists for patterns.
(vect_gen_niters_for_prolog_loop): Update calculation for
interleaving.
(vect_transform_loop): Remove stmt_vec_info for strided stores after
whole chain vectorization.
* config/rs6000/altivec.md (UNSPEC_EXTEVEN, UNSPEC_EXTODD,
UNSPEC_INTERHI, UNSPEC_INTERLO): New constants.
(vpkuhum_nomode, vpkuwum_nomode, vec_extract_even<mode>,
vec_extract_odd<mode>, altivec_vmrghsf, altivec_vmrglsf,
vec_interleave_high<mode>, vec_interleave_low<mode>): Implement.
From-SVN: r119088
2006-11-22 09:46:03 +01:00
|
|
|
@cindex @code{vec_extract_even@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_extract_even@var{m}}
|
|
|
|
Extract even elements from the input vectors (operand 1 and operand 2).
|
|
|
|
The even elements of operand 2 are concatenated to the even elements of operand
|
|
|
|
1 in their original order. The result is stored in operand 0.
|
|
|
|
The output and input vectors should have the same modes.
|
|
|
|
|
|
|
|
@cindex @code{vec_extract_odd@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_extract_odd@var{m}}
|
|
|
|
Extract odd elements from the input vectors (operand 1 and operand 2).
|
|
|
|
The odd elements of operand 2 are concatenated to the odd elements of operand
|
|
|
|
1 in their original order. The result is stored in operand 0.
|
|
|
|
The output and input vectors should have the same modes.
|
|
|
|
|
|
|
|
@cindex @code{vec_interleave_high@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_interleave_high@var{m}}
|
|
|
|
Merge high elements of the two input vectors into the output vector. The output
|
|
|
|
and input vectors should have the same modes (@code{N} elements). The high
|
|
|
|
@code{N/2} elements of the first input vector are interleaved with the high
|
|
|
|
@code{N/2} elements of the second input vector.
|
|
|
|
|
|
|
|
@cindex @code{vec_interleave_low@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_interleave_low@var{m}}
|
|
|
|
Merge low elements of the two input vectors into the output vector. The output
|
|
|
|
and input vectors should have the same modes (@code{N} elements). The low
|
|
|
|
@code{N/2} elements of the first input vector are interleaved with the low
|
|
|
|
@code{N/2} elements of the second input vector.
|
|
|
|
|
2004-04-03 19:25:47 +02:00
|
|
|
@cindex @code{vec_init@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_init@var{m}}
|
2004-05-12 01:35:57 +02:00
|
|
|
Initialize the vector to given values. Operand 0 is the vector to initialize
|
2004-04-03 19:25:47 +02:00
|
|
|
and operand 1 is parallel containing values for individual fields.
|
|
|
|
|
2005-10-06 02:05:33 +02:00
|
|
|
@cindex @code{push@var{m}1} instruction pattern
|
|
|
|
@item @samp{push@var{m}1}
|
2002-12-12 15:03:56 +01:00
|
|
|
Output a push instruction. Operand 0 is value to push. Used only when
|
2001-07-20 22:10:42 +02:00
|
|
|
@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
|
|
|
|
missing and in such case an @code{mov} expander is used instead, with a
|
2001-07-20 22:47:35 +02:00
|
|
|
@code{MEM} expression forming the push operation. The @code{mov} expander
|
2001-07-20 22:10:42 +02:00
|
|
|
method is deprecated.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{add@var{m}3} instruction pattern
|
|
|
|
@item @samp{add@var{m}3}
|
|
|
|
Add operand 2 and operand 1, storing the result in operand 0. All operands
|
|
|
|
must have mode @var{m}. This can be used even on two-address machines, by
|
|
|
|
means of constraints requiring operands 1 and 0 to be the same location.
|
|
|
|
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssadd@var{m}3} instruction pattern
|
|
|
|
@cindex @code{usadd@var{m}3} instruction pattern
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{sub@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
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@cindex @code{sssub@var{m}3} instruction pattern
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@cindex @code{ussub@var{m}3} instruction pattern
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1997-03-25 20:26:08 +01:00
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@cindex @code{mul@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssmul@var{m}3} instruction pattern
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|
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|
@cindex @code{usmul@var{m}3} instruction pattern
|
1997-03-25 20:26:08 +01:00
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@cindex @code{div@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssdiv@var{m}3} instruction pattern
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{udiv@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
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@cindex @code{usdiv@var{m}3} instruction pattern
|
1997-03-25 20:26:08 +01:00
|
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|
@cindex @code{mod@var{m}3} instruction pattern
|
|
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|
@cindex @code{umod@var{m}3} instruction pattern
|
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|
|
@cindex @code{umin@var{m}3} instruction pattern
|
|
|
|
@cindex @code{umax@var{m}3} instruction pattern
|
|
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|
@cindex @code{and@var{m}3} instruction pattern
|
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@cindex @code{ior@var{m}3} instruction pattern
|
|
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@cindex @code{xor@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
|
|
|
|
@item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
|
|
|
|
@item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
|
|
|
|
@itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
|
|
|
|
@itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
@itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
|
|
|
|
@itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
|
1997-03-25 20:26:08 +01:00
|
|
|
@itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
|
|
|
|
Similar, for other arithmetic operations.
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
|
2001-02-27 16:02:57 +01:00
|
|
|
@cindex @code{min@var{m}3} instruction pattern
|
|
|
|
@cindex @code{max@var{m}3} instruction pattern
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
@item @samp{smin@var{m}3}, @samp{smax@var{m}3}
|
|
|
|
Signed minimum and maximum operations. When used with floating point,
|
|
|
|
if both operands are zeros, or if either operand is @code{NaN}, then
|
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|
|
it is unspecified which of the two operands is returned as the result.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2005-08-10 18:18:17 +02:00
|
|
|
@cindex @code{reduc_smin_@var{m}} instruction pattern
|
|
|
|
@cindex @code{reduc_smax_@var{m}} instruction pattern
|
|
|
|
@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
|
|
|
|
Find the signed minimum/maximum of the elements of a vector. The vector is
|
2005-10-06 02:05:33 +02:00
|
|
|
operand 1, and the scalar result is stored in the least significant bits of
|
|
|
|
operand 0 (also a vector). The output and input vector should have the same
|
2005-08-10 18:18:17 +02:00
|
|
|
modes.
|
|
|
|
|
|
|
|
@cindex @code{reduc_umin_@var{m}} instruction pattern
|
|
|
|
@cindex @code{reduc_umax_@var{m}} instruction pattern
|
|
|
|
@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
|
|
|
|
Find the unsigned minimum/maximum of the elements of a vector. The vector is
|
2005-10-06 02:05:33 +02:00
|
|
|
operand 1, and the scalar result is stored in the least significant bits of
|
|
|
|
operand 0 (also a vector). The output and input vector should have the same
|
2005-08-10 18:18:17 +02:00
|
|
|
modes.
|
|
|
|
|
|
|
|
@cindex @code{reduc_splus_@var{m}} instruction pattern
|
|
|
|
@item @samp{reduc_splus_@var{m}}
|
2005-10-06 02:05:33 +02:00
|
|
|
Compute the sum of the signed elements of a vector. The vector is operand 1,
|
|
|
|
and the scalar result is stored in the least significant bits of operand 0
|
2005-08-10 18:18:17 +02:00
|
|
|
(also a vector). The output and input vector should have the same modes.
|
|
|
|
|
|
|
|
@cindex @code{reduc_uplus_@var{m}} instruction pattern
|
|
|
|
@item @samp{reduc_uplus_@var{m}}
|
2005-10-06 02:05:33 +02:00
|
|
|
Compute the sum of the unsigned elements of a vector. The vector is operand 1,
|
|
|
|
and the scalar result is stored in the least significant bits of operand 0
|
2005-08-10 18:18:17 +02:00
|
|
|
(also a vector). The output and input vector should have the same modes.
|
|
|
|
|
Makefile.in (tree-vect-patterns.o): Add rule for new file.
* Makefile.in (tree-vect-patterns.o): Add rule for new file.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Use
existing STMT_VINFO_VECTYPE if available.
(vect_mark_relevant): Add special handling for stmts that are
marked as STMT_VINFO_IN_PATTERN_P.
(vect_analyze_loop): Call vect_pattern_recog.
* tree-vectorizer.c (new_stmt_vec_info): Initialize new fields.
* tree-vectorizer.h (in_pattern_p, related_stmt): New fields in
stmt_info.
(STMT_VINFO_IN_PATTERN_P, STMT_VINFO_RELATED_STMT): New macros.
(vect_recog_func_ptr): New function-pointer type.
* tree-vect-patterns.c: New file.
(vect_recog_widen_sum_pattern, vect_recog_widen_mult_pattern):
(vect_recog_dot_prod_pattern, vect_pattern_recog):
(vect_pattern_recog_1): New functions.
(vect_pattern_recog_funcs): New array of function pointers.
* tree-vectorizer.h (ternary_op): New enum value.
* tree-vect-transform.c (vect_create_epilog_for_reduction): Added
declaration. Revised documentation. Removed redundant dump prints.
Removed redundant argument. Added support for reduction patterns.
(vectorizable_reduction): Added support for reduction patterns.
(vect_transform_stmt): Added support for patterns.
* expr.c (expand_expr_real_1): Added case for DOT_PROD_EXPR.
* genopinit.c (udot_prod_optab, sdot_prod_optab): Initialize.
* optabs.c (optab_for_tree_code): Added case for DOT_PROD_EXPR.
(expand_widen_pattern_expr): New function.
(init_optabs): Initialize new optabs udot_prod_optab,
sdot_prod_optab.
* optabs.h (OTI_sdot_prod, OTI_udot_prod): New.
(sdot_prod_optab, udot_prod_optab): Define new optabs.
(expand_widen_pattern_expr): New function declaration.
* tree.def (DOT_PROD_EXPR, WIDEN_SUM_EXPR, WIDEN_MULT_EXPR): New
tree-codes.
* tree-inline.c (estimate_num_insns_1): Added cases for new
tree-codes DOT_PROD_EXPR, WIDEN_SUM_EXPR, WIDEN_MULT_EXPR.
* tree-pretty-print.c (dump_generic_node): Likewise.
(op_prio): Likewise.
(op_symbol): Added cases for WIDEN_SUM_EXPR, WIDEN_MULT_EXPR.
* tree-ssa-operands.c (get_expr_operands): Added case for
DOT_PROD_EXPR.
* tree-vect-patterns.c (widened_name_p): New function.
(vect_recog_dot_prod_pattern): Added function implementation.
* tree-vect-transform.c (get_initial_def_for_reduction): Added
cases for DOT_PROD_EXPR, WIDEN_SUM_EXPR.
* config/rs6000/altivec.md (udot_prod<mode>, sdot_prodv8hi): New.
* config/i386/sse.md (sdot_prodv8hi, udot_prodv4si): New.
* expr.c (expand_expr_real_1): Added case for WIDEN_SUM_EXPR.
* genopinit.c (widen_ssum_optab, widen_usum_optab): Initialize.
* optabs.c (optab_for_tree_code): Added case for WIDEN_SUM_EXPR.
(init_optabs): Initialize new optabs widen_ssum_optab,
widen_usum_optab.
* optabs.h (OTI_widen_ssum, OTI_widen_usum): New.
(widen_ssum_optab, widen_usum_optab): Define new optabs.
* tree-vect-generic.c: (expand_vector_operations_1): Check type of
use instead of type of def.
* tree-vect-patterns.c (vect_recog_widen_sum_pattern): Added
function implementation.
* config/rs6000/altivec.md (widen_usum<mode>, widen_ssumv16qi,
widen_ssumv8hi): New.
* doc/tm.texi (ssum_widen, usum_widen, sdot_prod, udot_prod): New
patterns.
From-SVN: r109954
2006-01-19 11:24:00 +01:00
|
|
|
@cindex @code{sdot_prod@var{m}} instruction pattern
|
|
|
|
@item @samp{sdot_prod@var{m}}
|
|
|
|
@cindex @code{udot_prod@var{m}} instruction pattern
|
|
|
|
@item @samp{udot_prod@var{m}}
|
|
|
|
Compute the sum of the products of two signed/unsigned elements.
|
|
|
|
Operand 1 and operand 2 are of the same mode. Their product, which is of a
|
|
|
|
wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
|
|
|
|
wider than the mode of the product. The result is placed in operand 0, which
|
|
|
|
is of the same mode as operand 3.
|
|
|
|
|
|
|
|
@cindex @code{ssum_widen@var{m3}} instruction pattern
|
|
|
|
@item @samp{ssum_widen@var{m3}}
|
|
|
|
@cindex @code{usum_widen@var{m3}} instruction pattern
|
|
|
|
@item @samp{usum_widen@var{m3}}
|
|
|
|
Operands 0 and 2 are of the same mode, which is wider than the mode of
|
|
|
|
operand 1. Add operand 1 to operand 2 and place the widened result in
|
|
|
|
operand 0. (This is used express accumulation of elements into an accumulator
|
|
|
|
of a wider mode.)
|
|
|
|
|
2005-08-10 18:18:17 +02:00
|
|
|
@cindex @code{vec_shl_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_shr_@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
|
|
|
|
Whole vector left/right shift in bits.
|
|
|
|
Operand 1 is a vector to be shifted.
|
2005-10-06 02:05:33 +02:00
|
|
|
Operand 2 is an integer shift amount in bits.
|
2005-08-10 18:18:17 +02:00
|
|
|
Operand 0 is where the resulting shifted vector is stored.
|
|
|
|
The output and input vectors should have the same modes.
|
|
|
|
|
2007-04-22 20:45:06 +02:00
|
|
|
@cindex @code{vec_pack_trunc_@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_pack_trunc_@var{m}}
|
|
|
|
Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
|
|
|
|
are vectors of the same mode having N integral or floating point elements
|
|
|
|
of size S. Operand 0 is the resulting vector in which 2*N elements of
|
|
|
|
size N/2 are concatenated after narrowing them down using truncation.
|
|
|
|
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
@cindex @code{vec_pack_ssat_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_pack_usat_@var{m}} instruction pattern
|
2007-04-22 20:45:06 +02:00
|
|
|
@item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
|
|
|
|
Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
|
|
|
|
are vectors of the same mode having N integral elements of size S.
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
Operand 0 is the resulting vector in which the elements of the two input
|
2007-04-22 20:45:06 +02:00
|
|
|
vectors are concatenated after narrowing them down using signed/unsigned
|
|
|
|
saturating arithmetic.
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
|
re PR tree-optimization/24659 (Conversions are not vectorized)
PR tree-optimization/24659
* optabs.h (enum optab_index): Add OTI_vec_unpacks_float_hi,
OTI_vec_unpacks_float_lo, OTI_vec_unpacku_float_hi,
OTI_vec_unpacku_float_lo, OTI_vec_pack_sfix_trunc and
OTI_vec_pack_ufix_trunc.
(vec_unpacks_float_hi_optab): Define new macro.
(vec_unpacks_float_lo_optab): Ditto.
(vec_unpacku_float_hi_optab): Ditto.
(vec_unpacku_float_lo_optab): Ditto.
(vec_pack_sfix_trunc_optab): Ditto.
(vec_pack_ufix_trunc_optab): Ditto.
* genopinit.c (optabs): Implement vec_unpack[s|u]_[hi|lo]_optab
and vec_pack_[s|u]fix_trunc_optab using
vec_unpack[s|u]_[hi\lo]_* and vec_pack_[u|s]fix_trunc_* patterns
* tree-vectorizer.c (supportable_widening_operation): Handle
FLOAT_EXPR and CONVERT_EXPR. Update comment.
(supportable_narrowing_operation): New function.
* tree-vectorizer.h (supportable_narrowing_operation): Prototype.
* tree-vect-transform.c (vectorizable_conversion): Handle
(nunits_in == nunits_out / 2) and (nunits_out == nunits_in / 2) cases.
(vect_gen_widened_results_half): Move before vectorizable_conversion.
(vectorizable_type_demotion): Call supportable_narrowing_operation()
to check for target support.
* optabs.c (optab_for_tree_code) Return vec_unpack[s|u]_float_hi_optab
for VEC_UNPACK_FLOAT_HI_EXPR, vec_unpack[s|u]_float_lo_optab
for VEC_UNPACK_FLOAT_LO_EXPR and vec_pack_[u|s]fix_trunc_optab
for VEC_PACK_FIX_TRUNC_EXPR.
(expand_binop): Special case mode of the result for
vec_pack_[u|s]fix_trunc_optab.
(init_optabs): Initialize vec_unpack[s|u]_[hi|lo]_optab and
vec_pack_[u|s]fix_trunc_optab.
* tree.def (VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR,
VEC_PACK_FIX_TRUNC_EXPR): New tree codes.
* tree-pretty-print.c (dump_generic_node): Handle
VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR and
VEC_PACK_FIX_TRUNC_EXPR.
(op_prio): Ditto.
* expr.c (expand_expr_real_1): Ditto.
* tree-inline.c (estimate_num_insns_1): Ditto.
* tree-vect-generic.c (expand_vector_operations_1): Ditto.
* config/i386/sse.md (vec_unpacks_float_hi_v8hi): New expander.
(vec_unpacks_float_lo_v8hi): Ditto.
(vec_unpacku_float_hi_v8hi): Ditto.
(vec_unpacku_float_lo_v8hi): Ditto.
(vec_unpacks_float_hi_v4si): Ditto.
(vec_unpacks_float_lo_v4si): Ditto.
(vec_pack_sfix_trunc_v2df): Ditto.
* doc/c-tree.texi (Expression trees) [VEC_UNPACK_FLOAT_HI_EXPR]:
Document.
[VEC_UNPACK_FLOAT_LO_EXPR]: Ditto.
[VEC_PACK_FIX_TRUNC_EXPR]: Ditto.
* doc/md.texi (Standard Names) [vec_pack_sfix_trunc]: Document.
[vec_pack_ufix_trunc]: Ditto.
[vec_unpacks_float_hi]: Ditto.
[vec_unpacks_float_lo]: Ditto.
[vec_unpacku_float_hi]: Ditto.
[vec_unpacku_float_lo]: Ditto.
testsuite/ChangeLog:
PR tree-optimization/24659
* gcc.dg/vect/vect-floatint-conversion-2.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-1.c: Require vect_float,
not vect_int target.
* gcc.dg/vect/vect-intfloat-conversion-2.c: Require vect_float,
not vect_int target. Loop is vectorized for vect_intfloat_cvt
targets.
* gcc.dg/vect/vect-intfloat-conversion-3.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4a.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4b.c: New test.
From-SVN: r124784
2007-05-17 08:31:05 +02:00
|
|
|
@cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
|
|
|
|
@item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
|
|
|
|
Narrow, convert to signed/unsigned integral type and merge the elements
|
|
|
|
of two vectors. Operands 1 and 2 are vectors of the same mode having N
|
|
|
|
floating point elements of size S. Operand 0 is the resulting vector
|
|
|
|
in which 2*N elements of size N/2 are concatenated.
|
|
|
|
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
@cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
|
2007-04-22 20:45:06 +02:00
|
|
|
@item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
|
|
|
|
Extract and widen (promote) the high/low part of a vector of signed
|
|
|
|
integral or floating point elements. The input vector (operand 1) has N
|
|
|
|
elements of size S. Widen (promote) the high/low elements of the vector
|
|
|
|
using signed or floating point extension and place the resulting N/2
|
|
|
|
values of size 2*S in the output vector (operand 0).
|
|
|
|
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
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@cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
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@cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
|
2007-04-22 20:45:06 +02:00
|
|
|
@item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
|
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Extract and widen (promote) the high/low part of a vector of unsigned
|
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|
|
integral elements. The input vector (operand 1) has N elements of size S.
|
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|
Widen (promote) the high/low elements of the vector using zero extension and
|
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place the resulting N/2 values of size 2*S in the output vector (operand 0).
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
|
re PR tree-optimization/24659 (Conversions are not vectorized)
PR tree-optimization/24659
* optabs.h (enum optab_index): Add OTI_vec_unpacks_float_hi,
OTI_vec_unpacks_float_lo, OTI_vec_unpacku_float_hi,
OTI_vec_unpacku_float_lo, OTI_vec_pack_sfix_trunc and
OTI_vec_pack_ufix_trunc.
(vec_unpacks_float_hi_optab): Define new macro.
(vec_unpacks_float_lo_optab): Ditto.
(vec_unpacku_float_hi_optab): Ditto.
(vec_unpacku_float_lo_optab): Ditto.
(vec_pack_sfix_trunc_optab): Ditto.
(vec_pack_ufix_trunc_optab): Ditto.
* genopinit.c (optabs): Implement vec_unpack[s|u]_[hi|lo]_optab
and vec_pack_[s|u]fix_trunc_optab using
vec_unpack[s|u]_[hi\lo]_* and vec_pack_[u|s]fix_trunc_* patterns
* tree-vectorizer.c (supportable_widening_operation): Handle
FLOAT_EXPR and CONVERT_EXPR. Update comment.
(supportable_narrowing_operation): New function.
* tree-vectorizer.h (supportable_narrowing_operation): Prototype.
* tree-vect-transform.c (vectorizable_conversion): Handle
(nunits_in == nunits_out / 2) and (nunits_out == nunits_in / 2) cases.
(vect_gen_widened_results_half): Move before vectorizable_conversion.
(vectorizable_type_demotion): Call supportable_narrowing_operation()
to check for target support.
* optabs.c (optab_for_tree_code) Return vec_unpack[s|u]_float_hi_optab
for VEC_UNPACK_FLOAT_HI_EXPR, vec_unpack[s|u]_float_lo_optab
for VEC_UNPACK_FLOAT_LO_EXPR and vec_pack_[u|s]fix_trunc_optab
for VEC_PACK_FIX_TRUNC_EXPR.
(expand_binop): Special case mode of the result for
vec_pack_[u|s]fix_trunc_optab.
(init_optabs): Initialize vec_unpack[s|u]_[hi|lo]_optab and
vec_pack_[u|s]fix_trunc_optab.
* tree.def (VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR,
VEC_PACK_FIX_TRUNC_EXPR): New tree codes.
* tree-pretty-print.c (dump_generic_node): Handle
VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR and
VEC_PACK_FIX_TRUNC_EXPR.
(op_prio): Ditto.
* expr.c (expand_expr_real_1): Ditto.
* tree-inline.c (estimate_num_insns_1): Ditto.
* tree-vect-generic.c (expand_vector_operations_1): Ditto.
* config/i386/sse.md (vec_unpacks_float_hi_v8hi): New expander.
(vec_unpacks_float_lo_v8hi): Ditto.
(vec_unpacku_float_hi_v8hi): Ditto.
(vec_unpacku_float_lo_v8hi): Ditto.
(vec_unpacks_float_hi_v4si): Ditto.
(vec_unpacks_float_lo_v4si): Ditto.
(vec_pack_sfix_trunc_v2df): Ditto.
* doc/c-tree.texi (Expression trees) [VEC_UNPACK_FLOAT_HI_EXPR]:
Document.
[VEC_UNPACK_FLOAT_LO_EXPR]: Ditto.
[VEC_PACK_FIX_TRUNC_EXPR]: Ditto.
* doc/md.texi (Standard Names) [vec_pack_sfix_trunc]: Document.
[vec_pack_ufix_trunc]: Ditto.
[vec_unpacks_float_hi]: Ditto.
[vec_unpacks_float_lo]: Ditto.
[vec_unpacku_float_hi]: Ditto.
[vec_unpacku_float_lo]: Ditto.
testsuite/ChangeLog:
PR tree-optimization/24659
* gcc.dg/vect/vect-floatint-conversion-2.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-1.c: Require vect_float,
not vect_int target.
* gcc.dg/vect/vect-intfloat-conversion-2.c: Require vect_float,
not vect_int target. Loop is vectorized for vect_intfloat_cvt
targets.
* gcc.dg/vect/vect-intfloat-conversion-3.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4a.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4b.c: New test.
From-SVN: r124784
2007-05-17 08:31:05 +02:00
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@cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
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|
|
|
@cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
|
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@cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
|
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@item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
|
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@itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
|
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|
Extract, convert to floating point type and widen the high/low part of a
|
|
|
|
vector of signed/unsigned integral elements. The input vector (operand 1)
|
|
|
|
has N elements of size S. Convert the high/low elements of the vector using
|
|
|
|
floating point conversion and place the resulting N/2 values of size 2*S in
|
|
|
|
the output vector (operand 0).
|
|
|
|
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
|
|
|
@cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
|
|
|
|
@cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
|
re PR tree-optimization/24659 (Conversions are not vectorized)
PR tree-optimization/24659
* optabs.h (enum optab_index): Add OTI_vec_unpacks_float_hi,
OTI_vec_unpacks_float_lo, OTI_vec_unpacku_float_hi,
OTI_vec_unpacku_float_lo, OTI_vec_pack_sfix_trunc and
OTI_vec_pack_ufix_trunc.
(vec_unpacks_float_hi_optab): Define new macro.
(vec_unpacks_float_lo_optab): Ditto.
(vec_unpacku_float_hi_optab): Ditto.
(vec_unpacku_float_lo_optab): Ditto.
(vec_pack_sfix_trunc_optab): Ditto.
(vec_pack_ufix_trunc_optab): Ditto.
* genopinit.c (optabs): Implement vec_unpack[s|u]_[hi|lo]_optab
and vec_pack_[s|u]fix_trunc_optab using
vec_unpack[s|u]_[hi\lo]_* and vec_pack_[u|s]fix_trunc_* patterns
* tree-vectorizer.c (supportable_widening_operation): Handle
FLOAT_EXPR and CONVERT_EXPR. Update comment.
(supportable_narrowing_operation): New function.
* tree-vectorizer.h (supportable_narrowing_operation): Prototype.
* tree-vect-transform.c (vectorizable_conversion): Handle
(nunits_in == nunits_out / 2) and (nunits_out == nunits_in / 2) cases.
(vect_gen_widened_results_half): Move before vectorizable_conversion.
(vectorizable_type_demotion): Call supportable_narrowing_operation()
to check for target support.
* optabs.c (optab_for_tree_code) Return vec_unpack[s|u]_float_hi_optab
for VEC_UNPACK_FLOAT_HI_EXPR, vec_unpack[s|u]_float_lo_optab
for VEC_UNPACK_FLOAT_LO_EXPR and vec_pack_[u|s]fix_trunc_optab
for VEC_PACK_FIX_TRUNC_EXPR.
(expand_binop): Special case mode of the result for
vec_pack_[u|s]fix_trunc_optab.
(init_optabs): Initialize vec_unpack[s|u]_[hi|lo]_optab and
vec_pack_[u|s]fix_trunc_optab.
* tree.def (VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR,
VEC_PACK_FIX_TRUNC_EXPR): New tree codes.
* tree-pretty-print.c (dump_generic_node): Handle
VEC_UNPACK_FLOAT_HI_EXPR, VEC_UNPACK_FLOAT_LO_EXPR and
VEC_PACK_FIX_TRUNC_EXPR.
(op_prio): Ditto.
* expr.c (expand_expr_real_1): Ditto.
* tree-inline.c (estimate_num_insns_1): Ditto.
* tree-vect-generic.c (expand_vector_operations_1): Ditto.
* config/i386/sse.md (vec_unpacks_float_hi_v8hi): New expander.
(vec_unpacks_float_lo_v8hi): Ditto.
(vec_unpacku_float_hi_v8hi): Ditto.
(vec_unpacku_float_lo_v8hi): Ditto.
(vec_unpacks_float_hi_v4si): Ditto.
(vec_unpacks_float_lo_v4si): Ditto.
(vec_pack_sfix_trunc_v2df): Ditto.
* doc/c-tree.texi (Expression trees) [VEC_UNPACK_FLOAT_HI_EXPR]:
Document.
[VEC_UNPACK_FLOAT_LO_EXPR]: Ditto.
[VEC_PACK_FIX_TRUNC_EXPR]: Ditto.
* doc/md.texi (Standard Names) [vec_pack_sfix_trunc]: Document.
[vec_pack_ufix_trunc]: Ditto.
[vec_unpacks_float_hi]: Ditto.
[vec_unpacks_float_lo]: Ditto.
[vec_unpacku_float_hi]: Ditto.
[vec_unpacku_float_lo]: Ditto.
testsuite/ChangeLog:
PR tree-optimization/24659
* gcc.dg/vect/vect-floatint-conversion-2.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-1.c: Require vect_float,
not vect_int target.
* gcc.dg/vect/vect-intfloat-conversion-2.c: Require vect_float,
not vect_int target. Loop is vectorized for vect_intfloat_cvt
targets.
* gcc.dg/vect/vect-intfloat-conversion-3.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4a.c: New test.
* gcc.dg/vect/vect-intfloat-conversion-4b.c: New test.
From-SVN: r124784
2007-05-17 08:31:05 +02:00
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@item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
|
|
|
|
@itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
|
2007-04-22 20:45:06 +02:00
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Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
|
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|
are vectors with N signed/unsigned elements of size S. Multiply the high/low
|
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|
elements of the two vectors, and put the N/2 products of size 2*S in the
|
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output vector (operand 0).
|
[multiple changes]
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p): Take
enum argument instead of bool.
(vect_analyze_operations): Call vectorizable_type_promotion.
* tree-vectorizer.h (type_promotion_vec_info_type): New enum
stmt_vec_info_type value.
(supportable_widening_operation, vectorizable_type_promotion): New
function declarations.
* tree-vect-transform.c (vect_gen_widened_results_half): New function.
(vectorizable_type_promotion): New function.
(vect_transform_stmt): Call vectorizable_type_promotion.
* tree-vect-analyze.c (supportable_widening_operation): New function.
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Add implementation.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR):
(VEC_UNPACK_HI_EXPR, VEC_UNPACK_LO_EXPR): New tree-codes.
* tree-inline.c (estimate_num_insns_1): Add cases for above new
tree-codes.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
(init_optabs): Initialize new optabs.
* genopinit.c (vec_widen_umult_hi_optab, vec_widen_smult_hi_optab,
vec_widen_smult_hi_optab, vec_widen_smult_lo_optab,
vec_unpacks_hi_optab, vec_unpacks_lo_optab, vec_unpacku_hi_optab,
vec_unpacku_lo_optab): Initialize new optabs.
* optabs.h (OTI_vec_widen_umult_hi, OTI_vec_widen_umult_lo):
(OTI_vec_widen_smult_h, OTI_vec_widen_smult_lo, OTI_vec_unpacks_hi,
OTI_vec_unpacks_lo, OTI_vec_unpacku_hi, OTI_vec_unpacku_lo): New
optab indices.
(vec_widen_umult_hi_optab, vec_widen_umult_lo_optab):
(vec_widen_smult_hi_optab, vec_widen_smult_lo_optab):
(vec_unpacks_hi_optab, vec_unpacku_hi_optab, vec_unpacks_lo_optab):
(vec_unpacku_lo_optab): New optabs.
* doc/md.texi (vec_unpacks_hi, vec_unpacks_lo, vec_unpacku_hi):
(vec_unpacku_lo, vec_widen_umult_hi, vec_widen_umult_lo):
(vec_widen_smult_hi, vec_widen_smult_lo): New.
* doc/c-tree.texi (VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR):
(VEC_WIDEN_MULT_HI_EXPR, VEC_WIDEN_MULT_LO_EXPR, VEC_UNPACK_HI_EXPR):
(VEC_UNPACK_LO_EXPR, VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New.
* config/rs6000/altivec.md (UNSPEC_VMULWHUB, UNSPEC_VMULWLUB):
(UNSPEC_VMULWHSB, UNSPEC_VMULWLSB, UNSPEC_VMULWHUH, UNSPEC_VMULWLUH):
(UNSPEC_VMULWHSH, UNSPEC_VMULWLSH): New.
(UNSPEC_VPERMSI, UNSPEC_VPERMHI): New.
(vec_vperm_v8hiv4si, vec_vperm_v16qiv8hi): New patterns used to
implement the unsigned unpacking patterns.
(vec_unpacks_hi_v16qi, vec_unpacks_hi_v8hi, vec_unpacks_lo_v16qi):
(vec_unpacks_lo_v8hi): New signed unpacking patterns.
(vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi):
(vec_unpacku_lo_v8hi): New unsigned unpacking patterns.
(vec_widen_umult_hi_v16qi, vec_widen_umult_lo_v16qi):
(vec_widen_smult_hi_v16qi, vec_widen_smult_lo_v16qi):
(vec_widen_umult_hi_v8hi, vec_widen_umult_lo_v8hi):
(vec_widen_smult_hi_v8hi, vec_widen_smult_lo_v8hi): New widening
multiplication patterns.
* target.h (builtin_mul_widen_even, builtin_mul_widen_odd): New.
* target-def.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN):
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
* config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): New.
(rs6000_builtin_mul_widen_odd): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Defined.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Defined.
* tree-vectorizer.h (enum vect_relevant): New enum type.
(_stmt_vec_info): Field relevant chaned from bool to enum
vect_relevant.
(STMT_VINFO_RELEVANT_P): Updated.
(STMT_VINFO_RELEVANT): New.
* tree-vectorizer.c (new_stmt_vec_info): Use STMT_VINFO_RELEVANT
instead of STMT_VINFO_RELEVANT_P.
* tree-vect-analyze.c (vect_mark_relevant, vect_stmt_relevant_p):
Replace calls to STMT_VINFO_RELEVANT_P with STMT_VINFO_RELEVANT,
and boolean variable with enum vect_relevant.
(vect_mark_stmts_to_be_vectorized): Likewise + update documentation.
* doc/tm.texi (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): New.
(TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): New.
2006-11-08 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (vec_widen_umult_hi_v8hi,
vec_widen_umult_lo_v8hi): New.
(vec_widen_smult_hi_v4si, vec_widen_smult_lo_v4si,
vec_widen_umult_hi_v4si, vec_widen_umult_lo_v4si): New.
* config/i386/i386.c (ix86_expand_sse_unpack): New.
* config/i386/i386-protos.h (ix86_expand_sse_unpack): New.
* config/i386/sse.md (vec_unpacku_hi_v16qi, vec_unpacks_hi_v16qi,
vec_unpacku_lo_v16qi, vec_unpacks_lo_v16qi, vec_unpacku_hi_v8hi,
vec_unpacks_hi_v8hi, vec_unpacku_lo_v8hi, vec_unpacks_lo_v8hi,
vec_unpacku_hi_v4si, vec_unpacks_hi_v4si, vec_unpacku_lo_v4si,
vec_unpacks_lo_v4si): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_type_demotion): New function.
(vect_transform_stmt): Add case for type_demotion_vec_info_type.
(vect_analyze_operations): Call vectorizable_type_demotion.
* tree-vectorizer.h (type_demotion_vec_info_type): New enum
stmt_vec_info_type value.
(vectorizable_type_demotion): New function declaration.
* tree-vect-generic.c (expand_vector_operations_1): Consider correct
mode.
* tree.def (VEC_PACK_MOD_EXPR, VEC_PACK_SAT_EXPR): New tree-codes.
* expr.c (expand_expr_real_1): Add case for VEC_PACK_MOD_EXPR and
VEC_PACK_SAT_EXPR.
* tree-iniline.c (estimate_num_insns_1): Likewise.
* tree-pretty-print.c (dump_generic_node, op_prio): Likewise.
* optabs.c (optab_for_tree_code): Likewise.
* optabs.c (expand_binop): In case of vec_pack_*_optabs the mode
compared against the predicate of the result is not 'mode' (the input
to the function) but a mode with half the size of 'mode'.
(init_optab): Initialize new optabs.
* optabs.h (OTI_vec_pack_mod, OTI_vec_pack_ssat, OTI_vec_pack_usat):
New optab indices.
(vec_pack_mod_optab, vec_pack_ssat_optab, vec_pack_usat_optab): New
optabs.
* genopinit.c (vec_pack_mod_optab, vec_pack_ssat_optab):
(vec_pack_usat_optab): Initialize new optabs.
* doc/md.texi (vec_pack_mod, vec_pack_ssat, vec_pack_usat): New.
* config/rs6000/altivec.md (vec_pack_mod_v8hi, vec_pack_mod_v4si): New.
2006-11-08 Richard Henderson <rth@redehat.com>
* config/i386/sse.md (vec_pack_mod_v8hi, vec_pack_mod_v4si):
(vec_pack_mod_v2di, vec_interleave_highv16qi, vec_interleave_lowv16qi):
(vec_interleave_highv8hi, vec_interleave_lowv8hi):
(vec_interleave_highv4si, vec_interleave_lowv4si):
(vec_interleave_highv2di, vec_interleave_lowv2di): New.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_reduction): Support multiple
datatypes.
(vect_transform_stmt): Removed redundant code.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vectorizable_operation): Support multiple
datatypes.
2006-11-08 Dorit Nuzman <dorit@il.ibm.com>
* tree-vect-transform.c (vect_align_data_ref): Removed.
(vect_create_data_ref_ptr): Added additional argument - ptr_incr.
Updated function documentation. Return the increment stmt in ptr_incr.
(bump_vector_ptr): New function.
(vect_get_vec_def_for_stmt_copy): New function.
(vect_finish_stmt_generation): Create a stmt_info to newly created
vector stmts.
(vect_setup_realignment): Call vect_create_data_ref_ptr with additional
argument.
(vectorizable_reduction, vectorizable_assignment): Not supported yet if
VF is greater than the number of elements that can fit in one vector
word.
(vectorizable_operation, vectorizable_condition): Likewise.
(vectorizable_store, vectorizable_load): Support the case that the VF
is greater than the number of elements that can fit in one vector word.
(vect_transform_loop): Don't fail in case of multiple data-types.
* tree-vect-analyze.c (vect_determine_vectorization_factor): Don't fail
in case of multiple data-types; the smallest type determines the VF.
(vect_analyze_data_ref_dependence): Don't record datarefs as same_align
if they are of different sizes.
(vect_update_misalignment_for_peel): Compare misalignments in terms of
number of elements rather than number of bytes.
(vect_enhance_data_refs_alignment): Fix/Add dump printouts.
(vect_can_advance_ivs_p): Fix a dump printout
From-SVN: r118577
2006-11-08 08:32:44 +01:00
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1997-03-25 20:26:08 +01:00
|
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@cindex @code{mulhisi3} instruction pattern
|
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|
|
@item @samp{mulhisi3}
|
|
|
|
Multiply operands 1 and 2, which have mode @code{HImode}, and store
|
|
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a @code{SImode} product in operand 0.
|
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@cindex @code{mulqihi3} instruction pattern
|
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@cindex @code{mulsidi3} instruction pattern
|
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|
@item @samp{mulqihi3}, @samp{mulsidi3}
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|
Similar widening-multiplication instructions of other widths.
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@cindex @code{umulqihi3} instruction pattern
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|
@cindex @code{umulhisi3} instruction pattern
|
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|
@cindex @code{umulsidi3} instruction pattern
|
|
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|
@item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
|
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|
|
Similar widening-multiplication instructions that do unsigned
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|
|
|
multiplication.
|
|
|
|
|
2005-11-20 19:49:18 +01:00
|
|
|
@cindex @code{usmulqihi3} instruction pattern
|
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|
@cindex @code{usmulhisi3} instruction pattern
|
|
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|
@cindex @code{usmulsidi3} instruction pattern
|
|
|
|
@item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
|
|
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|
Similar widening-multiplication instructions that interpret the first
|
|
|
|
operand as unsigned and the second operand as signed, then do a signed
|
|
|
|
multiplication.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
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@cindex @code{smul@var{m}3_highpart} instruction pattern
|
1999-06-22 22:33:23 +02:00
|
|
|
@item @samp{smul@var{m}3_highpart}
|
1997-03-25 20:26:08 +01:00
|
|
|
Perform a signed multiplication of operands 1 and 2, which have mode
|
|
|
|
@var{m}, and store the most significant half of the product in operand 0.
|
|
|
|
The least significant half of the product is discarded.
|
|
|
|
|
|
|
|
@cindex @code{umul@var{m}3_highpart} instruction pattern
|
|
|
|
@item @samp{umul@var{m}3_highpart}
|
|
|
|
Similar, but the multiplication is unsigned.
|
|
|
|
|
2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk>
gcc/
2007-xx-xx Chao-ying Fu <fu@mips.com>
Richard Sandiford <richard@nildram.co.uk>
* doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document.
* optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes.
(smadd_widen_optab, umadd_widen_optab): Define.
* optabs.c (init_optabs): Initialize smadd_widen_optab and
umadd_widen_optab.
* genopinit.c (optabs): Fill in smadd_widen_optab and
umadd_widen_optab.
* expr.c (expand_expr_real_1): Try to use smadd_widen_optab
and umadd_widen_optab to implement multiply-add sequences.
* config/mips/mips.md (*<su>mul_acc_di): Rename to...
(<u>maddsidi4): ...this. Extend condition to include
GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint
of operand 0 to "ka" and use the three-operand form of madd<u>
for TARGET_DSPR2.
* config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert
to define_expands.
* config/mips/constraints.md (ka): New register constraint.
gcc/testsuite/
2007-xx-xx Richard Sandiford <richard@nildram.co.uk>
* gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c,
* gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c,
* gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c,
* gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests.
From-SVN: r124095
2007-04-24 07:51:57 +02:00
|
|
|
@cindex @code{madd@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{madd@var{m}@var{n}4}
|
|
|
|
Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
|
|
|
|
operand 3, and store the result in operand 0. Operands 1 and 2
|
|
|
|
have mode @var{m} and operands 0 and 3 have mode @var{n}.
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
Both modes must be integer or fixed-point modes and @var{n} must be twice
|
2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk>
gcc/
2007-xx-xx Chao-ying Fu <fu@mips.com>
Richard Sandiford <richard@nildram.co.uk>
* doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document.
* optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes.
(smadd_widen_optab, umadd_widen_optab): Define.
* optabs.c (init_optabs): Initialize smadd_widen_optab and
umadd_widen_optab.
* genopinit.c (optabs): Fill in smadd_widen_optab and
umadd_widen_optab.
* expr.c (expand_expr_real_1): Try to use smadd_widen_optab
and umadd_widen_optab to implement multiply-add sequences.
* config/mips/mips.md (*<su>mul_acc_di): Rename to...
(<u>maddsidi4): ...this. Extend condition to include
GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint
of operand 0 to "ka" and use the three-operand form of madd<u>
for TARGET_DSPR2.
* config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert
to define_expands.
* config/mips/constraints.md (ka): New register constraint.
gcc/testsuite/
2007-xx-xx Richard Sandiford <richard@nildram.co.uk>
* gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c,
* gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c,
* gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c,
* gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests.
From-SVN: r124095
2007-04-24 07:51:57 +02:00
|
|
|
the size of @var{m}.
|
|
|
|
|
|
|
|
In other words, @code{madd@var{m}@var{n}4} is like
|
|
|
|
@code{mul@var{m}@var{n}3} except that it also adds operand 3.
|
|
|
|
|
|
|
|
These instructions are not allowed to @code{FAIL}.
|
|
|
|
|
|
|
|
@cindex @code{umadd@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{umadd@var{m}@var{n}4}
|
|
|
|
Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
|
|
|
|
operands instead of sign-extending them.
|
|
|
|
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{ssmadd@var{m}@var{n}4}
|
|
|
|
Like @code{madd@var{m}@var{n}4}, but all involved operations must be
|
|
|
|
signed-saturating.
|
|
|
|
|
|
|
|
@cindex @code{usmadd@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{usmadd@var{m}@var{n}4}
|
|
|
|
Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
|
|
|
|
unsigned-saturating.
|
|
|
|
|
2007-05-09 00:51:14 +02:00
|
|
|
@cindex @code{msub@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{msub@var{m}@var{n}4}
|
|
|
|
Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
|
|
|
|
result from operand 3, and store the result in operand 0. Operands 1 and 2
|
|
|
|
have mode @var{m} and operands 0 and 3 have mode @var{n}.
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
Both modes must be integer or fixed-point modes and @var{n} must be twice
|
2007-05-09 00:51:14 +02:00
|
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|
the size of @var{m}.
|
|
|
|
|
|
|
|
In other words, @code{msub@var{m}@var{n}4} is like
|
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|
|
@code{mul@var{m}@var{n}3} except that it also subtracts the result
|
|
|
|
from operand 3.
|
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|
|
|
|
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|
These instructions are not allowed to @code{FAIL}.
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|
|
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@cindex @code{umsub@var{m}@var{n}4} instruction pattern
|
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|
@item @samp{umsub@var{m}@var{n}4}
|
|
|
|
Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
|
|
|
|
operands instead of sign-extending them.
|
|
|
|
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
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|
@cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{ssmsub@var{m}@var{n}4}
|
|
|
|
Like @code{msub@var{m}@var{n}4}, but all involved operations must be
|
|
|
|
signed-saturating.
|
|
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|
|
|
|
@cindex @code{usmsub@var{m}@var{n}4} instruction pattern
|
|
|
|
@item @samp{usmsub@var{m}@var{n}4}
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|
Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
|
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|
unsigned-saturating.
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|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{divmod@var{m}4} instruction pattern
|
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|
@item @samp{divmod@var{m}4}
|
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|
Signed division that produces both a quotient and a remainder.
|
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|
|
Operand 1 is divided by operand 2 to produce a quotient stored
|
|
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|
in operand 0 and a remainder stored in operand 3.
|
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|
For machines with an instruction that produces both a quotient and a
|
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|
remainder, provide a pattern for @samp{divmod@var{m}4} but do not
|
|
|
|
provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
|
|
|
|
allows optimization in the relatively common case when both the quotient
|
|
|
|
and remainder are computed.
|
|
|
|
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|
|
|
If an instruction that just produces a quotient or just a remainder
|
|
|
|
exists and is more efficient than the instruction that produces both,
|
|
|
|
write the output routine of @samp{divmod@var{m}4} to call
|
|
|
|
@code{find_reg_note} and look for a @code{REG_UNUSED} note on the
|
|
|
|
quotient or remainder and generate the appropriate instruction.
|
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|
@cindex @code{udivmod@var{m}4} instruction pattern
|
|
|
|
@item @samp{udivmod@var{m}4}
|
|
|
|
Similar, but does unsigned division.
|
|
|
|
|
2004-09-04 10:50:36 +02:00
|
|
|
@anchor{shift patterns}
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{ashl@var{m}3} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssashl@var{m}3} instruction pattern
|
|
|
|
@cindex @code{usashl@var{m}3} instruction pattern
|
|
|
|
@item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
|
1997-03-25 20:26:08 +01:00
|
|
|
Arithmetic-shift operand 1 left by a number of bits specified by operand
|
|
|
|
2, and store the result in operand 0. Here @var{m} is the mode of
|
|
|
|
operand 0 and operand 1; operand 2's mode is specified by the
|
|
|
|
instruction pattern, and the compiler will convert the operand to that
|
2004-09-04 10:50:36 +02:00
|
|
|
mode before generating the instruction. The meaning of out-of-range shift
|
|
|
|
counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
|
|
|
|
@xref{TARGET_SHIFT_TRUNCATION_MASK}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{ashr@var{m}3} instruction pattern
|
|
|
|
@cindex @code{lshr@var{m}3} instruction pattern
|
|
|
|
@cindex @code{rotl@var{m}3} instruction pattern
|
|
|
|
@cindex @code{rotr@var{m}3} instruction pattern
|
|
|
|
@item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
|
|
|
|
Other shift and rotate instructions, analogous to the
|
|
|
|
@code{ashl@var{m}3} instructions.
|
|
|
|
|
|
|
|
@cindex @code{neg@var{m}2} instruction pattern
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{ssneg@var{m}2} instruction pattern
|
|
|
|
@cindex @code{usneg@var{m}2} instruction pattern
|
|
|
|
@item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
|
1997-03-25 20:26:08 +01:00
|
|
|
Negate operand 1 and store the result in operand 0.
|
|
|
|
|
|
|
|
@cindex @code{abs@var{m}2} instruction pattern
|
|
|
|
@item @samp{abs@var{m}2}
|
|
|
|
Store the absolute value of operand 1 into operand 0.
|
|
|
|
|
|
|
|
@cindex @code{sqrt@var{m}2} instruction pattern
|
|
|
|
@item @samp{sqrt@var{m}2}
|
|
|
|
Store the square root of operand 1 into operand 0.
|
|
|
|
|
|
|
|
The @code{sqrt} built-in function of C always uses the mode which
|
2002-08-04 01:21:31 +02:00
|
|
|
corresponds to the C data type @code{double} and the @code{sqrtf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
optabs.h (enum optab_index): Rename OTI_drem to OTI_remainder.
* optabs.h (enum optab_index): Rename OTI_drem to OTI_remainder.
(remainder_optab): Define corresponding macro.
(drem_optab): Remove.
* optabs.c (init_optabs): Initialize remainder_optab. Remove
drem_optab initialization.
* genopinit.c (optabs): Implement remainder_optab using
remainder?f3 patterns. Remove drem_optab.
* builtins.c (expand_builtin_mathfn_2): Handle
BUILT_IN_REMAINDER{,F,L} using remainder_optab.
(expand_builtin): Expand BUILT_IN_REMAINDER{,F,L} using
expand_builtin_mathfn_2.
(expand_builtin) [BUILT_IN_FMOD, BUILT_IN_DREM]: Do not
depend on flag_unsafe_math_optimizations.
* config/i386/i386.md ("remaindersf3", "remainderdf3")
("remainderxf3"): Renamed from "drem{s,d,x}f3" expanders.
Do not depend on flag_unsafe_math_optimizations. Use
truncxf?f expander instead of truncxf?f_i387_noop.
("fpremxf4", "fprem1xf4"): Do not depend on
flag_unsafe_math_optimizations.
("fmodsf3", "fmoddf3", "fmodxf3"): Do not depend on
flag_unsafe_math_optimizations. Use truncxf?f expander
instead of truncxf?f_i387_noop.
* doc/md.texi (fmod, remainder): Document standard named pattern.
testsuite/ChangeLog:
* gcc.dg/builtins-40.c: Also check remainder(), remainderf()
and remainderl() built-in functions. Remove -ffast-math from
dg-options.
From-SVN: r118024
2006-10-25 08:36:49 +02:00
|
|
|
@cindex @code{fmod@var{m}3} instruction pattern
|
|
|
|
@item @samp{fmod@var{m}3}
|
|
|
|
Store the remainder of dividing operand 1 by operand 2 into
|
|
|
|
operand 0, rounded towards zero to an integer.
|
|
|
|
|
|
|
|
The @code{fmod} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{fmodf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{remainder@var{m}3} instruction pattern
|
|
|
|
@item @samp{remainder@var{m}3}
|
|
|
|
Store the remainder of dividing operand 1 by operand 2 into
|
|
|
|
operand 0, rounded to the nearest integer.
|
|
|
|
|
|
|
|
The @code{remainder} built-in function of C always uses the mode
|
|
|
|
which corresponds to the C data type @code{double} and the
|
|
|
|
@code{remainderf} built-in function uses the mode which corresponds
|
|
|
|
to the C data type @code{float}.
|
|
|
|
|
2002-08-04 01:21:31 +02:00
|
|
|
@cindex @code{cos@var{m}2} instruction pattern
|
|
|
|
@item @samp{cos@var{m}2}
|
|
|
|
Store the cosine of operand 1 into operand 0.
|
|
|
|
|
|
|
|
The @code{cos} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{cosf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{sin@var{m}2} instruction pattern
|
|
|
|
@item @samp{sin@var{m}2}
|
|
|
|
Store the sine of operand 1 into operand 0.
|
|
|
|
|
|
|
|
The @code{sin} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{sinf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{exp@var{m}2} instruction pattern
|
|
|
|
@item @samp{exp@var{m}2}
|
|
|
|
Store the exponential of operand 1 into operand 0.
|
|
|
|
|
|
|
|
The @code{exp} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{expf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{log@var{m}2} instruction pattern
|
|
|
|
@item @samp{log@var{m}2}
|
|
|
|
Store the natural logarithm of operand 1 into operand 0.
|
|
|
|
|
|
|
|
The @code{log} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{logf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2003-02-11 20:34:11 +01:00
|
|
|
@cindex @code{pow@var{m}3} instruction pattern
|
|
|
|
@item @samp{pow@var{m}3}
|
|
|
|
Store the value of operand 1 raised to the exponent operand 2
|
|
|
|
into operand 0.
|
|
|
|
|
|
|
|
The @code{pow} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{powf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{atan2@var{m}3} instruction pattern
|
|
|
|
@item @samp{atan2@var{m}3}
|
|
|
|
Store the arc tangent (inverse tangent) of operand 1 divided by
|
|
|
|
operand 2 into operand 0, using the signs of both arguments to
|
|
|
|
determine the quadrant of the result.
|
|
|
|
|
|
|
|
The @code{atan2} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{atan2f}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
2002-12-16 19:23:00 +01:00
|
|
|
@cindex @code{floor@var{m}2} instruction pattern
|
|
|
|
@item @samp{floor@var{m}2}
|
|
|
|
Store the largest integral value not greater than argument.
|
|
|
|
|
|
|
|
The @code{floor} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{floorf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
2005-06-18 17:21:19 +02:00
|
|
|
@cindex @code{btrunc@var{m}2} instruction pattern
|
|
|
|
@item @samp{btrunc@var{m}2}
|
2002-12-16 19:23:00 +01:00
|
|
|
Store the argument rounded to integer towards zero.
|
|
|
|
|
|
|
|
The @code{trunc} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{truncf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{round@var{m}2} instruction pattern
|
|
|
|
@item @samp{round@var{m}2}
|
|
|
|
Store the argument rounded to integer away from zero.
|
|
|
|
|
|
|
|
The @code{round} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{roundf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{ceil@var{m}2} instruction pattern
|
|
|
|
@item @samp{ceil@var{m}2}
|
|
|
|
Store the argument rounded to integer away from zero.
|
|
|
|
|
|
|
|
The @code{ceil} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{ceilf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
|
|
|
@cindex @code{nearbyint@var{m}2} instruction pattern
|
|
|
|
@item @samp{nearbyint@var{m}2}
|
|
|
|
Store the argument rounded according to the default rounding mode
|
|
|
|
|
|
|
|
The @code{nearbyint} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{nearbyintf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
2005-06-18 17:21:19 +02:00
|
|
|
@cindex @code{rint@var{m}2} instruction pattern
|
|
|
|
@item @samp{rint@var{m}2}
|
|
|
|
Store the argument rounded according to the default rounding mode and
|
|
|
|
raise the inexact exception when the result differs in value from
|
|
|
|
the argument
|
|
|
|
|
|
|
|
The @code{rint} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{rintf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
2006-10-25 15:01:14 +02:00
|
|
|
@cindex @code{lrint@var{m}@var{n}2}
|
|
|
|
@item @samp{lrint@var{m}@var{n}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as a signed number according to the current
|
|
|
|
rounding mode and store in operand 0 (which has mode @var{n}).
|
|
|
|
|
2006-10-28 13:30:41 +02:00
|
|
|
@cindex @code{lround@var{m}@var{n}2}
|
|
|
|
@item @samp{lround@var{m}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as a signed number rounding to nearest and away
|
|
|
|
from zero and store in operand 0 (which has mode @var{n}).
|
|
|
|
|
2006-10-29 16:18:24 +01:00
|
|
|
@cindex @code{lfloor@var{m}@var{n}2}
|
|
|
|
@item @samp{lfloor@var{m}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as a signed number rounding down and store in
|
|
|
|
operand 0 (which has mode @var{n}).
|
|
|
|
|
|
|
|
@cindex @code{lceil@var{m}@var{n}2}
|
|
|
|
@item @samp{lceil@var{m}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as a signed number rounding up and store in
|
|
|
|
operand 0 (which has mode @var{n}).
|
|
|
|
|
2005-11-11 18:59:54 +01:00
|
|
|
@cindex @code{copysign@var{m}3} instruction pattern
|
|
|
|
@item @samp{copysign@var{m}3}
|
|
|
|
Store a value with the magnitude of operand 1 and the sign of operand
|
|
|
|
2 into operand 0.
|
|
|
|
|
|
|
|
The @code{copysign} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{double} and the @code{copysignf}
|
|
|
|
built-in function uses the mode which corresponds to the C data
|
|
|
|
type @code{float}.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{ffs@var{m}2} instruction pattern
|
|
|
|
@item @samp{ffs@var{m}2}
|
|
|
|
Store into operand 0 one plus the index of the least significant 1-bit
|
|
|
|
of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
|
|
|
|
of operand 0; operand 1's mode is specified by the instruction
|
|
|
|
pattern, and the compiler will convert the operand to that mode before
|
|
|
|
generating the instruction.
|
|
|
|
|
|
|
|
The @code{ffs} built-in function of C always uses the mode which
|
|
|
|
corresponds to the C data type @code{int}.
|
|
|
|
|
[multiple changes]
2003-02-01 Richard Henderson <rth@redhat.com>
* optabs.c (expand_unop): Use word_mode for outmode of bit scaners.
* libgcc2.c (__ffsdi2, __clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2): Change
return type to Wtype.
* libgcc-std.ver (GCC_3.4): Fix inheritance.
* config/i386/i386.md (ffssi2): Use nonimmediate_operand for
expander input constraint.
2003-02-01 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de>
* optabs.h (optab_index): Add OTI_clz, OTI_ctz, OTI_popcount and
OTI_parity.
(clz_optab, ctz_optab, popcount_optab, parity_optab): New.
* optabs.c (widen_clz, expand_parity): New.
(expand_unop): Handle clz and parity. Hardcode SImode as outmode
for libcalls to clz, ctz, popcount, and parity.
(init_optabs): Init clz_optab, ctz_optab, popcount_optab and
parity_optab, and set up libfunc handlers.
* libgcc2.c (__clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2,
__popcount_tab): New.
* libgcc2.h: Declare them.
* libgcc-std.ver (GCC_3.4): Add new functions from libgcc2.c.
* genopinit.c (optabs): Add clz_optab, ctz_optab, popcount_optab
and parity_optab.
* builtin-types.def (BT_FN_INT_LONG, BT_FN_INT_LONGLONG): New.
* builtins.def (BUILT_IN_CLZ, BUILT_IN_CTZ, BUILT_IN_POPCOUNT,
BUILT_IN_PARITY, BUILT_IN_FFSL, BUILT_IN_CLZL, BUILT_IN_CTZL,
BUILT_IN_POPCOUNTL, BUILT_IN_PARITYL, BUILT_IN_FFSLL,
BUILT_IN_CLZLL, BUILT_IN_CTZLL, BUILT_IN_POPCOUNTLL,
BUILT_IN_PARITYLL): New.
* builtins.c (expand_builtin_unop): Rename from expand_builtin_ffs
and add optab argument.
(expand_builtin): Expand BUILT_IN_{FFS,CLZ,POPCOUNT,PARITY}*.
* tree.def (CLZ_EXPR, CTZ_EXPR, POPCOUNT_EXPR, PARITY_EXPR): New.
* expr.c (expand_expr): Handle them.
* fold-const.c (tree_expr_nonnegative_p): Likewise.
* rtl.def (CLZ, CTZ, POPCOUNT, PARITY): New.
* reload1.c (eliminate_regs): Handle them.
(elimination_effects): Likewise.
* function.c (instantiate_virtual_regs_1): Likewise
* genattrtab.c (check_attr_value): Likewise.
* simplify-rtx.c (simplify_unary_operation): Likewise.
* c-common.c (c_common_truthvalue_conversion): Handle POPCOUNT_EXPR.
* combine.c (combine_simplify_rtx): Handle POPCOUNT and PARITY.
(nonzero_bits): Handle CLZ, CTZ, POPCOUNT and PARITY.
* config/alpha/alpha.md (clzdi2, ctzdi2, popcountdi2): New.
* config/arm/arm.c (arm_init_builtins): Rename __builtin_clz to
__builtin_arm_clz.
* Makefile.in (LIB2FUNCS_1, LIB2FUNCS_2): Move...
* mklibgcc.in (lib2funcs): ...here and merge. Add new members.
* doc/extend.texi (Other Builtins): Add new builtins.
* doc/md.texi (Standard Names): Add new patterns.
From-SVN: r62252
2003-02-01 20:00:02 +01:00
|
|
|
@cindex @code{clz@var{m}2} instruction pattern
|
|
|
|
@item @samp{clz@var{m}2}
|
|
|
|
Store into operand 0 the number of leading 0-bits in @var{x}, starting
|
|
|
|
at the most significant bit position. If @var{x} is 0, the result is
|
|
|
|
undefined. @var{m} is the mode of operand 0; operand 1's mode is
|
|
|
|
specified by the instruction pattern, and the compiler will convert the
|
|
|
|
operand to that mode before generating the instruction.
|
|
|
|
|
|
|
|
@cindex @code{ctz@var{m}2} instruction pattern
|
|
|
|
@item @samp{ctz@var{m}2}
|
|
|
|
Store into operand 0 the number of trailing 0-bits in @var{x}, starting
|
|
|
|
at the least significant bit position. If @var{x} is 0, the result is
|
|
|
|
undefined. @var{m} is the mode of operand 0; operand 1's mode is
|
|
|
|
specified by the instruction pattern, and the compiler will convert the
|
|
|
|
operand to that mode before generating the instruction.
|
|
|
|
|
|
|
|
@cindex @code{popcount@var{m}2} instruction pattern
|
|
|
|
@item @samp{popcount@var{m}2}
|
|
|
|
Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
|
|
|
|
mode of operand 0; operand 1's mode is specified by the instruction
|
|
|
|
pattern, and the compiler will convert the operand to that mode before
|
|
|
|
generating the instruction.
|
|
|
|
|
|
|
|
@cindex @code{parity@var{m}2} instruction pattern
|
|
|
|
@item @samp{parity@var{m}2}
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
|
[multiple changes]
2003-02-01 Richard Henderson <rth@redhat.com>
* optabs.c (expand_unop): Use word_mode for outmode of bit scaners.
* libgcc2.c (__ffsdi2, __clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2): Change
return type to Wtype.
* libgcc-std.ver (GCC_3.4): Fix inheritance.
* config/i386/i386.md (ffssi2): Use nonimmediate_operand for
expander input constraint.
2003-02-01 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de>
* optabs.h (optab_index): Add OTI_clz, OTI_ctz, OTI_popcount and
OTI_parity.
(clz_optab, ctz_optab, popcount_optab, parity_optab): New.
* optabs.c (widen_clz, expand_parity): New.
(expand_unop): Handle clz and parity. Hardcode SImode as outmode
for libcalls to clz, ctz, popcount, and parity.
(init_optabs): Init clz_optab, ctz_optab, popcount_optab and
parity_optab, and set up libfunc handlers.
* libgcc2.c (__clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2,
__popcount_tab): New.
* libgcc2.h: Declare them.
* libgcc-std.ver (GCC_3.4): Add new functions from libgcc2.c.
* genopinit.c (optabs): Add clz_optab, ctz_optab, popcount_optab
and parity_optab.
* builtin-types.def (BT_FN_INT_LONG, BT_FN_INT_LONGLONG): New.
* builtins.def (BUILT_IN_CLZ, BUILT_IN_CTZ, BUILT_IN_POPCOUNT,
BUILT_IN_PARITY, BUILT_IN_FFSL, BUILT_IN_CLZL, BUILT_IN_CTZL,
BUILT_IN_POPCOUNTL, BUILT_IN_PARITYL, BUILT_IN_FFSLL,
BUILT_IN_CLZLL, BUILT_IN_CTZLL, BUILT_IN_POPCOUNTLL,
BUILT_IN_PARITYLL): New.
* builtins.c (expand_builtin_unop): Rename from expand_builtin_ffs
and add optab argument.
(expand_builtin): Expand BUILT_IN_{FFS,CLZ,POPCOUNT,PARITY}*.
* tree.def (CLZ_EXPR, CTZ_EXPR, POPCOUNT_EXPR, PARITY_EXPR): New.
* expr.c (expand_expr): Handle them.
* fold-const.c (tree_expr_nonnegative_p): Likewise.
* rtl.def (CLZ, CTZ, POPCOUNT, PARITY): New.
* reload1.c (eliminate_regs): Handle them.
(elimination_effects): Likewise.
* function.c (instantiate_virtual_regs_1): Likewise
* genattrtab.c (check_attr_value): Likewise.
* simplify-rtx.c (simplify_unary_operation): Likewise.
* c-common.c (c_common_truthvalue_conversion): Handle POPCOUNT_EXPR.
* combine.c (combine_simplify_rtx): Handle POPCOUNT and PARITY.
(nonzero_bits): Handle CLZ, CTZ, POPCOUNT and PARITY.
* config/alpha/alpha.md (clzdi2, ctzdi2, popcountdi2): New.
* config/arm/arm.c (arm_init_builtins): Rename __builtin_clz to
__builtin_arm_clz.
* Makefile.in (LIB2FUNCS_1, LIB2FUNCS_2): Move...
* mklibgcc.in (lib2funcs): ...here and merge. Add new members.
* doc/extend.texi (Other Builtins): Add new builtins.
* doc/md.texi (Standard Names): Add new patterns.
From-SVN: r62252
2003-02-01 20:00:02 +01:00
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in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
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is specified by the instruction pattern, and the compiler will convert
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the operand to that mode before generating the instruction.
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1997-03-25 20:26:08 +01:00
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@cindex @code{one_cmpl@var{m}2} instruction pattern
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@item @samp{one_cmpl@var{m}2}
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Store the bitwise-complement of operand 1 into operand 0.
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@cindex @code{cmp@var{m}} instruction pattern
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@item @samp{cmp@var{m}}
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Compare operand 0 and operand 1, and set the condition codes.
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The RTL pattern should look like this:
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@smallexample
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(set (cc0) (compare (match_operand:@var{m} 0 @dots{})
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(match_operand:@var{m} 1 @dots{})))
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@end smallexample
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@cindex @code{tst@var{m}} instruction pattern
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@item @samp{tst@var{m}}
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Compare operand 0 against zero, and set the condition codes.
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The RTL pattern should look like this:
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@smallexample
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(set (cc0) (match_operand:@var{m} 0 @dots{}))
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@end smallexample
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@samp{tst@var{m}} patterns should not be defined for machines that do
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not use @code{(cc0)}. Doing so would confuse the optimizer since it
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would no longer be clear which @code{set} operations were comparisons.
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The @samp{cmp@var{m}} patterns should be used instead.
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2004-07-07 21:25:01 +02:00
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@cindex @code{movmem@var{m}} instruction pattern
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@item @samp{movmem@var{m}}
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Introduce H8SX support.
* expr.c (expand_strcpy): Renamed and moved to...
* builtins.c (expand_movstr): ... here. Tweak.
(expand_builtin_strcpy): Adjust. Use movstr if len can't be
computed or has side effects.
(expand_builtin_stpcpy): Likewise. Use strcpy if return value is
unused, or if mempcpy fails. Adjust the return value in the
latter case. Use movstr if everything else fails.
* doc/md.texi (movstr): Document.
(movmemM, clrmemM): Fix explanation of memory block operands.
* config/h8300/h8300.md (stpcpy): Renamed to...
(movstr): ... this. Adjust.
2004-07-07 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md: Rename movstr*, except for movstrict*, to
movmem* and clrstr* to clrmem*.
2004-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_reg_class_from_letter): Map 'D' to
GENERAL_REGS, always.
(h8300_swap_into_er6, h8300_swap_into_er6): Handle the case of
getting the stack pointer as addr.
* config/h8300/h8300.h (PREDICATE_CODES): Remove constant rtxes
from general_operand_dst.
* config/h8300/h8300.md (movmd_internal_normal): New, normal-mode
variant of...
(movmd_internal): ... this. Add modes to operands. Disparage `D'
instead of requiring it to match only before reload.
(stpcpy_internal_normal): New, normal-mode variant of...
(stpcpy_internal): ... this. Add modes to operands. Disparage
`D' instead of requiring it to match only before reload.
* config/h8300/h8300-protos.h (h8300_legitimate_address_p): Add
mode argument.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Pass it to...
* config/h8300/h8300.c (h8300_legitimate_address_p): Pass it to
h8300_get_index.
* config/h8300/h8300.md (attr type): Add call.
(attr can_delay): If type is call, set it no.
(call, call_value): Set type to call.
2004-06-21 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md (logicalhi3_sn, logicalsi3_sn): New.
2004-06-16 Alexandre Oliva <aoliva@redhat.com>
* tree.c (get_narrower): Don't narrow integral types into
non-integral types.
* config/h8300/h8300.c (h8300_expand_epilogue): Initialize
frame_size *before* the first use.
* config/h8300/h8300.md (movstrictqi): Reintroduce post-increment
on input.
(peephole2): Don't widen instructions that push SP. Move
decrement of SP to the end of all stm-generating peepholes.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (insv): Prefer to use AND to clear a bitfield
and OR to set it to all ones.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (can_delay): Default to "no" for bit branches.
(call, call_value): Set can_delay to "no".
2003-07-22 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Make subreg check more robust.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*brabit): Remove.
* config/h8300/h8300.md (*brabc, *brabs): Remove mode from
zero_extract. Use bit_memory_operand as the predicate for
operand 1 and 'WU' as the constraint. Check the difference
between the base length and the final one when deciding which
type of branch to use.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Remove mode from operands 0 and 1.
Use convert_move to extend the result for TARGET_H8300SX. Check
for QImode memory references. Optimize the case where the
destination is a paradoxical subreg.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*movsf_h8sx): Add an r <- G alternative.
* config/h8300/h8300.md (andqi): Remove bclr from h8sx version.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md: Include mova.md
(length_table): Add mova and mova_zero.
* config/h8300/h8300.c (print_operand): Handle '%o'. Print a length
after all constant addresses for '%R', '%X', '%T' and '%S'.
(h8300_mova_length): New function.
(h8300_insn_length_from_table): Use it to handle mova and mova_zero.
* config/h8300/t-h8300 (mova.md): Generate from genmova.sh. Add to
dependencies for s-config, etc.
* config/h8300/gemova.sh: New file.
* config/h8300/mova.md: Generated.
2003-07-20 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_bitfield_length): New.
(nibble_operand): Adjust.
(h8300_binary_length): Handle conditional binary op.
(h8300_insn_length_from_table): Handle bitfield and bitbranch.
* config/h8300/h8300.h: Change constraints W# and Y# to P#>X and
P#<X, respectively. The original P is now IP4>X. Introduced P#>0
and P#<0, unused so far. W and Y are now prefixes to multi-letter
constraints. WU is introduced as a variant of U that requires a
mem, and is therefore considered an EXTRA_MEMORY_CONSTRAINT.
* config/h8300/h8300.md (attr type): Added bitbranch.
(attr length_table): Added bitfield and bitbranch.
(attr length): Compute bitbranch length.
(andqi): Separate pattern for H8300SX. Use bfld for loading the
least-significant bit of a byte.
(brabit, brabc, brabs): New.
(insv, extzv): Emit bfst and bfld on H8300SX.
(bfld, bfst, seq, sne): New.
(bstzhireg, cmpstz, bstz, bistz): New.
(cmpcondbset, condbset, cmpcondbclr, condbclr): New.
(cmpcondbsetreg, condbsetreg, cmpcondbclrreg, condbclrreg): New.
2003-07-11 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8sx_binary_memory_operator): New function.
(h8sx_unary_memory_operator): New function.
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Disable.
(PREDICATE_CODES): Add h8sx_{unary,binary}_memory_operator.
* config/h8300/h8300.md: Add peepholes to combine reloads and
arithmetic insns.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h830.md (cmpqi): Use 'i' rather than 'n' in constraints.
(*cmphi_h8300hs, *addqi3, *addhi3_h8sx, subhi3): Likewise.
(and?i, ior?i, xor?i): Likewise.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c: Move enums and prototypes to head of file.
Various whitespace fixes.
(h8300_constant_length): New function, split out from...
(h8300_displacement_size): ...here. Rename h8300_displacement_length.
(h8300_classify_operand): Use IN_RANGE.
(h8300_classify_operand): Use h8300_constant_length.
(h8300_short_move_mem_p): Tighten size check.
(h8sx_mergeable_memrefs_p): Tighten equality check.
2003-06-30 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Define __H8300SX__
for -msx.
* config/h8300/crti.asm: Use .h8300sx or .h8300sxn for -msx code.
* config/h8300/crtn.asm: Likewise.
* config/h8300/lib1funcs.asm: Likewise. Use 32-bit pointers
if __H8300SX__ is defined.
2003-06-27 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_get_index): Add mode parameter.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Update accordingly.
(GO_IF_MODE_DEPENDENT_ADDRESS): Treat POST_DEC, PRE_INC and indexed
addresses as mode-dependent.
* config/h8300/h8300.c (print_operand_address): Update call to
h8300_get_index.
(h8300_get_index): Take a mode argument. Rework to fix an
earlier misunderstanding.
2003-06-26 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (zero_extendqisi2): Force the source operand
into a register if TARGET_H8300SX.
(*zero_extendqisi2_h8300hs, *extendqisi2_h8300): Disable for
TARGET_H8300SX. Also disable related define_splits.
(*zero_extendqisi2_h8sx, *extendqisi2_h8sx): New patterns.
2003-06-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_rtx_costs): Add h8sx handling.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (OK_FOR_Z): New macro.
(EXTRA_CONSTRAINT_STR): Check it.
* config/h8300/h8300.c (h8300_classify_operand): Accept null
class arguments.
(h8300_insn_length_from_table): Handle LENGTH_TABLE_MOV_IMM4.
* config/h8300/h8300.md (length_table): Add mov_imm4.
(movqi, movhi): Add Z <- W4 alternatives to h8sx patterns.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* genattrtab.c (write_eligible_delay): Allow candidate_insn to
be a label.
* config/h8300/h8300.h (DELAY_SLOT_LENGTH): New macro.
* config/h8300/h8300.c (h8300_reorg): New function.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/h8300/h8300.md (length): Subtract the length of the
delay slot from (pc) when checking the range of forward branches.
(delay_slot, can_delay): New attributes.
(define_delay): Add bra/s handling.
(movmd_internal, return_h8sx, *return_1): Set can_delay to no.
(jump): Add delayed-branch handling.
2003-06-17 Richard Sandiford <rsandifo@redhat.com>
* expr.c (expand_strcpy): New function.
* builtins.c (expand_builtin_strcpy): Fall back on expand_strcpy.
(expand_builtin_stpcpy): Likewise.
* config/h8300/h8300-protos.h (h8sx_split_movmd): Remove.
(h8300_swap_into_er6, h8300_swap_out_of_er6): Declare.
* config/h8300/h8300.c (h8300_reg_class_from_letter): Tweak 'd'
handling to improve register allocation for -fno-omit-frame-pointer.
(h8sx_split_movmd): Delete, moving er6 handling into...
(h8300_swap_into_er6, h8300_swap_out_of_er6): ...these new functions.
* config/h8300/h8300.md (UNSPEC_STPCPY): New unspec constant.
(movmd): Add calls to copy_rtx.
(movmd_internal): In the second alternative, allow the initial and
final destination registers to be different . Update the splitter
accordingly. Call h8300_swap_into_er6 and h8300_swap_out_of_er6
instead of h8sx_split_movmd.
(stpcpy, movsd): New expanders.
(movsd_internal): New define_insn.
2003-06-13 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_reg_class_from_letter): Declare.
(h8sx_emit_movmd, h8sx_split_movmd): Declare.
* config/h8300/h8300.h (reg_class): Add COUNTER_REGS, SOURCE_REGS
and DESTINATION_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
(REGNO_REG_CLASS): Map er4, er5 and er6 to the new classes.
(REG_CLASS_FROM_LETTER): Use h8300_reg_class_from_letter.
(h8300_move_ratio): Declare.
(MOVE_RATIO): Use it.
* config/h8300/h8300.c (h8300_move_ratio): New variable.
(h8300_init_once): Initialize it.
(h8300_reg_class_from_letter): New function.
(print_operand): Add an 'm' prefix for printing ".b", ".w" or ".l".
(h8sx_emit_movmd, h8sx_split_movmd): New functions.
* config/h8300/h8300.md (UNSPEC_MOVMD): New unspec constant.
(COUNTER_REG, SOURCE_REG, DESTINATION_REG): New register constants.
(movstrsi, movmd): New expanders.
(movmd_internal): New insn.
2003-06-06 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Define.
2003-06-04 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxnelf for -msx -mn.
* config/h8300/h8300.c (asm_file_start): Use .h8300sxn likewise.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (nibble_operand): Fix warning.
* config/h8300/h8300.md (movstricthi): Set adjust_length to no.
(movsi_h8sx): Likewise here and the normal h8sx movhi pattern.
(movsf_h8300h): Disable for TARGET_H8300SX.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (PREDICATE_CODES): Add h8300_ldm_parallel,
h8300_stm_parallel and h8300_return_parallel.
* config/h8300/h8300.c (h8300_push_pop, h8300_stack_offset_p,
h8300_ldm_stm_regno, h8300_ldm_stm_parallel, h8300_ldm_parallel,
h8300_stm_parallel, h8300_return_parallel): New functions.
(h8300_expand_prologue): Don't enforce ldm/stm register alignment
if TARGET_H8300SX. Use h8300_push_pop.
(h8300_expand_epilogue): Likewise. Try to merge the return insn
and final pop when generating h8sx code. Always emit some form
of return insn.
* config/h8300/h8300.md: Don't enforce register alignment in
stm peepholes if TARGET_H8300SX.
(ldm_h8300s, stm_h8300s, return_h8sx): New patterns.
(ldm_h8300s_[234], stm_h8300_[234]): Disable.
(epilogue): Expect h8300_expand_epilogue to emit a return insn.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/t-h8300 (MULTILIB_OPTIONS): Add a -msx multilib.
(MULTILIB_DIRNAMES): Add a directory for it.
(MULTILIB_MATCHES): Delete.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* final.c (walk_alter_subreg): Handle addresses with subregs
inside a ZERO_EXTEND or AND.
* config/h8300/h8300-protos.h (h8300_get_index): Declare.
* config/h8300/h8300.h (INDEX_REG_CLASS): Set to GENERAL_REGS
if TARGET_H8300SX.
(GO_IF_LEGITIMATE_ADDRESS): Use h8300_get_index.
* config/h8300/h8300.c (print_operand_address): Handle @(dd,RnL.b),
@(dd,Rn.w) and @(dd,ERn.L).
(h8300_displacement_size): Take the whole address as argument.
(h8300_classify_operand, h8300_short_move_mem_p): Adjust accordingly.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (h8300_operands_match_p): Declare.
(h8sx_mergeable_memrefs_p): Declare.
* config/h8300/h8300.h (HAVE_POST_DECREMENT): Define to TARGET_H8300SX.
(HAVE_PRE_INCREMENT): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): Accept pre/post increment/decrement
addresses for TARGET_H8300SX,
* config/h8300/h8300.c (print_operand_address): Deal with PRE_INC
and POST_DEC.
(movb_length_table, movl_length_table): New tables.
(movw_length_table): Define to movb_length_table.
(h8300_displacement_size): New, split out from...
(h8300_classify_address): ...here. Handle pre/post inc/dec.
(h8300_short_immediate_length): Allow H8OP_MEM_COMPLEX operands.
(h8300_insn_length_from_table): Add cases for movb, movw and movl.
(h8sx_mergeable_memrefs_p, h8300_operands_match_p): New functions.
(output_plussi): Use add.l #xx:3,Rn and sub.l #xx:3,Rn for h8sx.
(compute_plussi_length, compute_plussi_cc): Update accordingly.
(h8sx_unary_shift_operator): Get the mode from the operator.
(binary_shift_operator): Likewise.
* config/h8300/h8300.md: If a peephole2 applies gen_lowpart to
a memory reference, check whether the reference is offsettable.
(length_table): Add movb, movw and movl.
(movqi): Add new h8sx pattern. Don't force one operand to be a
register when generating h8sx code.
(movhi, movsi, movsf): Likewise.
(movstrictqi): Use the length_table attribute.
(movstricthi): Likewise. Add h8sx alternative for mov.w #xx:3,Rn.
(addqi3): Split into a define_expand and define_insn. Don't accept
memory operands in the expander. Use h8300_operands_match_p to
check for matching operands in the define_insn.
(subqi3, negqi2, one_cmplqi2): Likewise.
(add[hs]i3): Don't accept memory operands in the expander. Likewise
in any patterns that are unused in h8sx code. In the h8sx patterns,
use h8300_operands_match_p to check whether operands match.
(sub[hs]i3, and[hi]3, ior[hs]i3, xor[hs]i3, neg[hsi]3,
one_cmpl[hs]i3): Likewise.
(andqi3, iorqi3, xorqi3): Likewise. Don't call fix_bit_operand
in the expander.
2003-05-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (expand_a_shift): Return a bool.
(h8300_insn_length_from_table): Add a second parameter.
(output_h8sx_shift): Declare.
* config/h8300/h8300.h (OK_FOR_W, OK_FOR_Y): New macros.
(EXTRA_CONSTRAINT): Replace with...
(EXTRA_CONSTRAINT_STR): ...this. Use OK_FOR_W and OK_FOR_Y.
(CONSTRAINT_LEN): Define, returning 2 for 'W' and 'Y'.
(PREDICATE_CODES): Add entries for h8sx_unary_shift_operator
and h8sx_binary_shift_operator.
* config/h8300/h8300.c (two_insn_adds_subs_operand): Return false
for TARGET_H8300SX.
(bit_operand): Replace use of EXTRA_CONSTRAINT with OK_FOR_U.
(bit_memory_operand, fix_bit_operand): Likewise.
(h8300_length_table_for_insn): Remove.
(h8300_classify_operand): Fix check for 16-bit operands in 32-bit
instructions.
(h8300_short_immediate_length, h8300_binary_length): New functions.
(h8300_insn_length_from_table): Add an opcodes parameter. Rework.
(output_plussi): Use sub to add negative constants.
(compute_plussi_length): Adjust accordingly.
(h8sx_single_shift_type): New enum.
(h8sx_single_shift, h8sx_unary_shift_operator,
h8sx_binary_shift_operator, output_h8sx_shift): New functions.
(expand_a_shift, expand_a_rotate): Emit nothing if the shift is a
single h8sx instruction. Return false in this case.
* config/h8300/h8300.md (length_table): Add short_immediate.
(length): Pass the operand array to h8300_insn_length_from_table.
(adjust_length): Assume "no" for insns with a length_table attribute.
(*cmphi_h8300hs, cmpsi): Add alternatives for #xx:3.
(*addhi3_h8300hs): Don't use for h8sx.
(*addhi3_h8sx): New pattern, with alternatives for add.w #xx:3
and sub.w #xx:3.
(ashl[qhs]i3, lshr[qhs]i3, ashr[qhs]i3, rotl[qhs]i3): Change operand
1's predicate to nonimmediate_operand. Only skip default expansion
if expand_a_shift or expand_a_rotate returns true. Add new patterns
for single h8sx shift instructions.
2003-05-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (nibble_operand): Split out of...
(reg_or_nibble_operand): ... this.
* config/h8300/h8300.h (PREDICATE_CODES): Added nibble_operand.
* config/h8300/h8300.md: (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Introduce expand, and introduce separate insns for
sign- or zero-extended REG and already-extended CONST_INT.
2003-05-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_unary_length): Fix miscounting.
* config/h8300/h8300.md (subqi3): Generalize for h8sx.
(subhi3): Likewise. Don't accept immediates for operand 1.
Remove the early clobber from second alternative of the h8300s pattern.
(subsi3): Generalize for h8sx. Force operand 2 into a register
on plain h8300 targets.
(subsi3_h8300): Use h8300_dst_operand for consistency with expander.
(subsi3_h8300h): Generalize for h8sx.
(one_cmplqi2, one_cmplhi2, one_cmplsi2): Likewise.
2003-05-19 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (reg_or_nibble_operand): New.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
(TARGET_H8300SXMUL): New.
(CONST_OK_FOR_P): New.
(CONST_OK_FOR_LETTER_P): Adjust.
* config/h8300/h8300.md (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Accept 4-bit immediate on H8SX.
(mulhi3, mulsi3, smulsi3_highpart, umulsi3_highpart): New.
(udivsi3, divhi3, udivsi3, divsi3): New.
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_insn_length_from_table): Declare.
* config/h8300/h8300.h (OK_FOR_Q): New macro.
(EXTRA_CONSTRAINT): Use it to check the 'Q' constraint.
(PREDICATE_CODES): Add h8300_src_operand and h8300_dst_operand.
Add ADDRESSOF to the bit_operand entry.
* config/h8300/h8300.c (h8300_dst_operand): New predicate.
(h8300_src_operand): Likewise.
(bit_operand): Check nonimmediate_operand rather than general_operand.
Accept any nonimmediate_operand in h8sx code.
(h8300_and_costs): Initialize operands[1].
(h8300_rtx_costs) <AND>: Return false if the operands aren't valid.
(h8300_operand_class): New enum.
(h8300_length_table): New typedef.
(addb_length_table, addw_length_table, addl_length_table,
logicl_length_table): New tables.
(logicb_length_table, logicw_length_table): New macros.
(h8300_classify_operand, h8300_length_from_table,
h8300_length_table_for_insn, h8300_unary_length,
h8300_insn_length_from_table): New functions.
(output_plussi): Only use adds and subs for register destinations.
Disable redundant clause.
(compute_plussi_cc): Likewise.
(compute_plussi_length): Likewise. Use h8300_length_from_table
to work out the length of an insn.
(output_logical_op): Only use narrower immediate instructions
if the destination is a register.
(compute_logical_op_cc): Likewise.
(compute_logical_op_length): Likewise. Use h8300_length_from_table.
(h8300_adjust_insn_length): Tighten check for reg<->mem moves.
* config/h8300/h8300.md (length_table): New attribute.
(length): When an instruction has a length_table attribute, use
h8300_insn_length_from_table to calculate its default length.
(cmpqi): Use h8300_dst_operand for the first operand and
h8300_src_operand for the second.
(cmphi, *cmphi_h8300hs, cmpsi, negqi2, neghi2, neghi2_h8300h, negsi2,
negsi2_h8300h, addqi3, addhi3, *addhi3_h8300, *addhi3_h8300hs, addsi3,
addsi_h8300, addsi_h8300h, andhi3, andsi3, iorhi3,
iorsi3, xorhi3, xorsi3): Likewise.
(andqi3): Use h8300_src_operand for operand 2. Adjust the condition
so that it allows any combination of operands for TARGET_H8300SX.
(iorqi3, xorqi3): Likewise.
(cmpqi): Use the length_table attribute.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, andqi3, iorqi3,
xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
(cmpqi): Add 'Q' constraint.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, addsi_h8300h, andqi3,
iorqi3, xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
2003-05-14 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (MASK_H8300SX): New macro.
(TARGET_H8300S): True for both -ms and -msx.
(TARGET_H8300SX): New macro.
(TARGET_SWITCHES): Add entries for -msx and -mno-sx.
* config/h8300/h8300.c (asm_file_start): Write .h8300sx for -msx.
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxelf for -msx.
* config/h8300/t-h8300 (MULTILIB_MATCHES): Use -ms multilibs for -msx.
[Temporary change.]
2003-02-28 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.h (SIZE_TYPE, PTRDIFF_TYPE): Use short with
16-bit pointers and 32-bit ints.
* config/h8300/h8300.h (LEGITIMATE_CONSTANT_P): Accept
CONST_DOUBLE with mode no wider than SImode.
* config/h8300/h8300.md (extendqisi2_h8300): Add constraints for
output operand.
2003-02-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (general_operand_src): Match CONSTANT_P_RTX
or SUBREG thereof.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
2003-02-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (dosize): Truncate sign * size to Pmode.
From-SVN: r84257
2004-07-08 05:40:34 +02:00
|
|
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Block move instruction. The destination and source blocks of memory
|
|
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are the first two operands, and both are @code{mem:BLK}s with an
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address in mode @code{Pmode}.
|
1998-04-04 15:32:39 +02:00
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1997-03-25 20:26:08 +01:00
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|
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The number of bytes to move is the third operand, in mode @var{m}.
|
1998-04-04 15:32:39 +02:00
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Usually, you specify @code{word_mode} for @var{m}. However, if you can
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generate better code knowing the range of valid lengths is smaller than
|
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those representable in a full word, you should provide a pattern with a
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mode corresponding to the range of values you can handle efficiently
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(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
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that appear negative) and also a pattern with @code{word_mode}.
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1997-03-25 20:26:08 +01:00
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The fourth operand is the known shared alignment of the source and
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destination, in the form of a @code{const_int} rtx. Thus, if the
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compiler knows that both source and destination are word-aligned,
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it may provide the value 4 for this operand.
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expr.c (emit_block_move_via_movmem, [...]): Add variant handling histograms; add wrapper.
* expr.c (emit_block_move_via_movmem, emit_block_move_via_libcall): Add
variant handling histograms; add wrapper.
(clear_storage_via_libcall): Export.
(emit_block_move_hints): Break out from ...; add histograms.
(emit_block_move): ... this one.
(clear_storage_hints): Break out from ...; add histograms.
(clear_storage): ... this one.
(set_storage_via_memset): Handle histogram.
* expr.h (emit_block_move_via_libcall, emit_block_move_hints): Declare.
(clear_storage_hints, clear_storage_via_libcall): Declare.
(set_storage_via_setmem): Update prototype.
* doc/md.texi (movmem, setmem): Document new arguments.
* value-prof.c (dump_histogram_value, tree_find_values_to_profile): Add
new histograms.
(stringop_block_profile): New global function.
(tree_stringops_values_to_profile): Profile block size and alignment.
* value-prof.h (enum hist_type): add HIST_TYPE_AVERAGE and
HIST_TYPE_IOR.
(struct profile_hooks): Add gen_average_profiler and gen_ior_profiler.
(stringop_block_profile): Declare.
* builtins.c: Include value-prof.h.
(expand_builtin_memcpy, expand_builtin_memset): Pass block profile.
* gcov-ui.h (GCOV_COUNTER_NAMES): Add new counter.
(GCOV_COUNTER_AVERAGE, GCOV_COUNTER_IOR): New constants.
(GCOV_COUNTERS, GCOV_LAST_VALUE_COUNTER): Update.
* profile.c (instrument_values): Add new counters.
* cfgexpand.c (expand_gimple_basic_block): Propagate histograms to
calls.
* tree-profile.c (tree_average_profiler_fn, tree_ior_profiler_fn): New.
(tree_init_edge_profiler): Build new profilers.
(tree_gen_average_profiler, tree_gen_ior_profiler): New.
(pass_tree_profile): Add dump.
(tree_profile_hooks): Update.
* Makefile.in (LIBGCOV): Add new constants.
* libgcov.c (__gcov_merge_ior, __gcov_average_profiler,
__gcov_ior_profiler): New.
* i386.md (movmem/setmem expanders): Add new optional arguments.
From-SVN: r121270
2007-01-28 20:38:39 +01:00
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Optional operands 5 and 6 specify expected alignment and size of block
|
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respectively. The expected alignment differs from alignment in operand 4
|
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in a way that the blocks are not required to be aligned according to it in
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all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
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2004-07-07 21:25:01 +02:00
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Descriptions of multiple @code{movmem@var{m}} patterns can only be
|
1998-02-02 10:33:14 +01:00
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beneficial if the patterns for smaller modes have fewer restrictions
|
1998-02-02 01:17:02 +01:00
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on their first, second and fourth operands. Note that the mode @var{m}
|
2004-07-07 21:25:01 +02:00
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in @code{movmem@var{m}} does not impose any restriction on the mode of
|
1998-02-02 01:17:02 +01:00
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individually moved data units in the block.
|
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1997-03-25 20:26:08 +01:00
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These patterns need not give special consideration to the possibility
|
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that the source and destination strings might overlap.
|
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Introduce H8SX support.
* expr.c (expand_strcpy): Renamed and moved to...
* builtins.c (expand_movstr): ... here. Tweak.
(expand_builtin_strcpy): Adjust. Use movstr if len can't be
computed or has side effects.
(expand_builtin_stpcpy): Likewise. Use strcpy if return value is
unused, or if mempcpy fails. Adjust the return value in the
latter case. Use movstr if everything else fails.
* doc/md.texi (movstr): Document.
(movmemM, clrmemM): Fix explanation of memory block operands.
* config/h8300/h8300.md (stpcpy): Renamed to...
(movstr): ... this. Adjust.
2004-07-07 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md: Rename movstr*, except for movstrict*, to
movmem* and clrstr* to clrmem*.
2004-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_reg_class_from_letter): Map 'D' to
GENERAL_REGS, always.
(h8300_swap_into_er6, h8300_swap_into_er6): Handle the case of
getting the stack pointer as addr.
* config/h8300/h8300.h (PREDICATE_CODES): Remove constant rtxes
from general_operand_dst.
* config/h8300/h8300.md (movmd_internal_normal): New, normal-mode
variant of...
(movmd_internal): ... this. Add modes to operands. Disparage `D'
instead of requiring it to match only before reload.
(stpcpy_internal_normal): New, normal-mode variant of...
(stpcpy_internal): ... this. Add modes to operands. Disparage
`D' instead of requiring it to match only before reload.
* config/h8300/h8300-protos.h (h8300_legitimate_address_p): Add
mode argument.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Pass it to...
* config/h8300/h8300.c (h8300_legitimate_address_p): Pass it to
h8300_get_index.
* config/h8300/h8300.md (attr type): Add call.
(attr can_delay): If type is call, set it no.
(call, call_value): Set type to call.
2004-06-21 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md (logicalhi3_sn, logicalsi3_sn): New.
2004-06-16 Alexandre Oliva <aoliva@redhat.com>
* tree.c (get_narrower): Don't narrow integral types into
non-integral types.
* config/h8300/h8300.c (h8300_expand_epilogue): Initialize
frame_size *before* the first use.
* config/h8300/h8300.md (movstrictqi): Reintroduce post-increment
on input.
(peephole2): Don't widen instructions that push SP. Move
decrement of SP to the end of all stm-generating peepholes.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (insv): Prefer to use AND to clear a bitfield
and OR to set it to all ones.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (can_delay): Default to "no" for bit branches.
(call, call_value): Set can_delay to "no".
2003-07-22 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Make subreg check more robust.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*brabit): Remove.
* config/h8300/h8300.md (*brabc, *brabs): Remove mode from
zero_extract. Use bit_memory_operand as the predicate for
operand 1 and 'WU' as the constraint. Check the difference
between the base length and the final one when deciding which
type of branch to use.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Remove mode from operands 0 and 1.
Use convert_move to extend the result for TARGET_H8300SX. Check
for QImode memory references. Optimize the case where the
destination is a paradoxical subreg.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*movsf_h8sx): Add an r <- G alternative.
* config/h8300/h8300.md (andqi): Remove bclr from h8sx version.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md: Include mova.md
(length_table): Add mova and mova_zero.
* config/h8300/h8300.c (print_operand): Handle '%o'. Print a length
after all constant addresses for '%R', '%X', '%T' and '%S'.
(h8300_mova_length): New function.
(h8300_insn_length_from_table): Use it to handle mova and mova_zero.
* config/h8300/t-h8300 (mova.md): Generate from genmova.sh. Add to
dependencies for s-config, etc.
* config/h8300/gemova.sh: New file.
* config/h8300/mova.md: Generated.
2003-07-20 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_bitfield_length): New.
(nibble_operand): Adjust.
(h8300_binary_length): Handle conditional binary op.
(h8300_insn_length_from_table): Handle bitfield and bitbranch.
* config/h8300/h8300.h: Change constraints W# and Y# to P#>X and
P#<X, respectively. The original P is now IP4>X. Introduced P#>0
and P#<0, unused so far. W and Y are now prefixes to multi-letter
constraints. WU is introduced as a variant of U that requires a
mem, and is therefore considered an EXTRA_MEMORY_CONSTRAINT.
* config/h8300/h8300.md (attr type): Added bitbranch.
(attr length_table): Added bitfield and bitbranch.
(attr length): Compute bitbranch length.
(andqi): Separate pattern for H8300SX. Use bfld for loading the
least-significant bit of a byte.
(brabit, brabc, brabs): New.
(insv, extzv): Emit bfst and bfld on H8300SX.
(bfld, bfst, seq, sne): New.
(bstzhireg, cmpstz, bstz, bistz): New.
(cmpcondbset, condbset, cmpcondbclr, condbclr): New.
(cmpcondbsetreg, condbsetreg, cmpcondbclrreg, condbclrreg): New.
2003-07-11 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8sx_binary_memory_operator): New function.
(h8sx_unary_memory_operator): New function.
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Disable.
(PREDICATE_CODES): Add h8sx_{unary,binary}_memory_operator.
* config/h8300/h8300.md: Add peepholes to combine reloads and
arithmetic insns.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h830.md (cmpqi): Use 'i' rather than 'n' in constraints.
(*cmphi_h8300hs, *addqi3, *addhi3_h8sx, subhi3): Likewise.
(and?i, ior?i, xor?i): Likewise.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c: Move enums and prototypes to head of file.
Various whitespace fixes.
(h8300_constant_length): New function, split out from...
(h8300_displacement_size): ...here. Rename h8300_displacement_length.
(h8300_classify_operand): Use IN_RANGE.
(h8300_classify_operand): Use h8300_constant_length.
(h8300_short_move_mem_p): Tighten size check.
(h8sx_mergeable_memrefs_p): Tighten equality check.
2003-06-30 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Define __H8300SX__
for -msx.
* config/h8300/crti.asm: Use .h8300sx or .h8300sxn for -msx code.
* config/h8300/crtn.asm: Likewise.
* config/h8300/lib1funcs.asm: Likewise. Use 32-bit pointers
if __H8300SX__ is defined.
2003-06-27 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_get_index): Add mode parameter.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Update accordingly.
(GO_IF_MODE_DEPENDENT_ADDRESS): Treat POST_DEC, PRE_INC and indexed
addresses as mode-dependent.
* config/h8300/h8300.c (print_operand_address): Update call to
h8300_get_index.
(h8300_get_index): Take a mode argument. Rework to fix an
earlier misunderstanding.
2003-06-26 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (zero_extendqisi2): Force the source operand
into a register if TARGET_H8300SX.
(*zero_extendqisi2_h8300hs, *extendqisi2_h8300): Disable for
TARGET_H8300SX. Also disable related define_splits.
(*zero_extendqisi2_h8sx, *extendqisi2_h8sx): New patterns.
2003-06-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_rtx_costs): Add h8sx handling.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (OK_FOR_Z): New macro.
(EXTRA_CONSTRAINT_STR): Check it.
* config/h8300/h8300.c (h8300_classify_operand): Accept null
class arguments.
(h8300_insn_length_from_table): Handle LENGTH_TABLE_MOV_IMM4.
* config/h8300/h8300.md (length_table): Add mov_imm4.
(movqi, movhi): Add Z <- W4 alternatives to h8sx patterns.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* genattrtab.c (write_eligible_delay): Allow candidate_insn to
be a label.
* config/h8300/h8300.h (DELAY_SLOT_LENGTH): New macro.
* config/h8300/h8300.c (h8300_reorg): New function.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/h8300/h8300.md (length): Subtract the length of the
delay slot from (pc) when checking the range of forward branches.
(delay_slot, can_delay): New attributes.
(define_delay): Add bra/s handling.
(movmd_internal, return_h8sx, *return_1): Set can_delay to no.
(jump): Add delayed-branch handling.
2003-06-17 Richard Sandiford <rsandifo@redhat.com>
* expr.c (expand_strcpy): New function.
* builtins.c (expand_builtin_strcpy): Fall back on expand_strcpy.
(expand_builtin_stpcpy): Likewise.
* config/h8300/h8300-protos.h (h8sx_split_movmd): Remove.
(h8300_swap_into_er6, h8300_swap_out_of_er6): Declare.
* config/h8300/h8300.c (h8300_reg_class_from_letter): Tweak 'd'
handling to improve register allocation for -fno-omit-frame-pointer.
(h8sx_split_movmd): Delete, moving er6 handling into...
(h8300_swap_into_er6, h8300_swap_out_of_er6): ...these new functions.
* config/h8300/h8300.md (UNSPEC_STPCPY): New unspec constant.
(movmd): Add calls to copy_rtx.
(movmd_internal): In the second alternative, allow the initial and
final destination registers to be different . Update the splitter
accordingly. Call h8300_swap_into_er6 and h8300_swap_out_of_er6
instead of h8sx_split_movmd.
(stpcpy, movsd): New expanders.
(movsd_internal): New define_insn.
2003-06-13 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_reg_class_from_letter): Declare.
(h8sx_emit_movmd, h8sx_split_movmd): Declare.
* config/h8300/h8300.h (reg_class): Add COUNTER_REGS, SOURCE_REGS
and DESTINATION_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
(REGNO_REG_CLASS): Map er4, er5 and er6 to the new classes.
(REG_CLASS_FROM_LETTER): Use h8300_reg_class_from_letter.
(h8300_move_ratio): Declare.
(MOVE_RATIO): Use it.
* config/h8300/h8300.c (h8300_move_ratio): New variable.
(h8300_init_once): Initialize it.
(h8300_reg_class_from_letter): New function.
(print_operand): Add an 'm' prefix for printing ".b", ".w" or ".l".
(h8sx_emit_movmd, h8sx_split_movmd): New functions.
* config/h8300/h8300.md (UNSPEC_MOVMD): New unspec constant.
(COUNTER_REG, SOURCE_REG, DESTINATION_REG): New register constants.
(movstrsi, movmd): New expanders.
(movmd_internal): New insn.
2003-06-06 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Define.
2003-06-04 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxnelf for -msx -mn.
* config/h8300/h8300.c (asm_file_start): Use .h8300sxn likewise.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (nibble_operand): Fix warning.
* config/h8300/h8300.md (movstricthi): Set adjust_length to no.
(movsi_h8sx): Likewise here and the normal h8sx movhi pattern.
(movsf_h8300h): Disable for TARGET_H8300SX.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (PREDICATE_CODES): Add h8300_ldm_parallel,
h8300_stm_parallel and h8300_return_parallel.
* config/h8300/h8300.c (h8300_push_pop, h8300_stack_offset_p,
h8300_ldm_stm_regno, h8300_ldm_stm_parallel, h8300_ldm_parallel,
h8300_stm_parallel, h8300_return_parallel): New functions.
(h8300_expand_prologue): Don't enforce ldm/stm register alignment
if TARGET_H8300SX. Use h8300_push_pop.
(h8300_expand_epilogue): Likewise. Try to merge the return insn
and final pop when generating h8sx code. Always emit some form
of return insn.
* config/h8300/h8300.md: Don't enforce register alignment in
stm peepholes if TARGET_H8300SX.
(ldm_h8300s, stm_h8300s, return_h8sx): New patterns.
(ldm_h8300s_[234], stm_h8300_[234]): Disable.
(epilogue): Expect h8300_expand_epilogue to emit a return insn.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/t-h8300 (MULTILIB_OPTIONS): Add a -msx multilib.
(MULTILIB_DIRNAMES): Add a directory for it.
(MULTILIB_MATCHES): Delete.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* final.c (walk_alter_subreg): Handle addresses with subregs
inside a ZERO_EXTEND or AND.
* config/h8300/h8300-protos.h (h8300_get_index): Declare.
* config/h8300/h8300.h (INDEX_REG_CLASS): Set to GENERAL_REGS
if TARGET_H8300SX.
(GO_IF_LEGITIMATE_ADDRESS): Use h8300_get_index.
* config/h8300/h8300.c (print_operand_address): Handle @(dd,RnL.b),
@(dd,Rn.w) and @(dd,ERn.L).
(h8300_displacement_size): Take the whole address as argument.
(h8300_classify_operand, h8300_short_move_mem_p): Adjust accordingly.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (h8300_operands_match_p): Declare.
(h8sx_mergeable_memrefs_p): Declare.
* config/h8300/h8300.h (HAVE_POST_DECREMENT): Define to TARGET_H8300SX.
(HAVE_PRE_INCREMENT): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): Accept pre/post increment/decrement
addresses for TARGET_H8300SX,
* config/h8300/h8300.c (print_operand_address): Deal with PRE_INC
and POST_DEC.
(movb_length_table, movl_length_table): New tables.
(movw_length_table): Define to movb_length_table.
(h8300_displacement_size): New, split out from...
(h8300_classify_address): ...here. Handle pre/post inc/dec.
(h8300_short_immediate_length): Allow H8OP_MEM_COMPLEX operands.
(h8300_insn_length_from_table): Add cases for movb, movw and movl.
(h8sx_mergeable_memrefs_p, h8300_operands_match_p): New functions.
(output_plussi): Use add.l #xx:3,Rn and sub.l #xx:3,Rn for h8sx.
(compute_plussi_length, compute_plussi_cc): Update accordingly.
(h8sx_unary_shift_operator): Get the mode from the operator.
(binary_shift_operator): Likewise.
* config/h8300/h8300.md: If a peephole2 applies gen_lowpart to
a memory reference, check whether the reference is offsettable.
(length_table): Add movb, movw and movl.
(movqi): Add new h8sx pattern. Don't force one operand to be a
register when generating h8sx code.
(movhi, movsi, movsf): Likewise.
(movstrictqi): Use the length_table attribute.
(movstricthi): Likewise. Add h8sx alternative for mov.w #xx:3,Rn.
(addqi3): Split into a define_expand and define_insn. Don't accept
memory operands in the expander. Use h8300_operands_match_p to
check for matching operands in the define_insn.
(subqi3, negqi2, one_cmplqi2): Likewise.
(add[hs]i3): Don't accept memory operands in the expander. Likewise
in any patterns that are unused in h8sx code. In the h8sx patterns,
use h8300_operands_match_p to check whether operands match.
(sub[hs]i3, and[hi]3, ior[hs]i3, xor[hs]i3, neg[hsi]3,
one_cmpl[hs]i3): Likewise.
(andqi3, iorqi3, xorqi3): Likewise. Don't call fix_bit_operand
in the expander.
2003-05-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (expand_a_shift): Return a bool.
(h8300_insn_length_from_table): Add a second parameter.
(output_h8sx_shift): Declare.
* config/h8300/h8300.h (OK_FOR_W, OK_FOR_Y): New macros.
(EXTRA_CONSTRAINT): Replace with...
(EXTRA_CONSTRAINT_STR): ...this. Use OK_FOR_W and OK_FOR_Y.
(CONSTRAINT_LEN): Define, returning 2 for 'W' and 'Y'.
(PREDICATE_CODES): Add entries for h8sx_unary_shift_operator
and h8sx_binary_shift_operator.
* config/h8300/h8300.c (two_insn_adds_subs_operand): Return false
for TARGET_H8300SX.
(bit_operand): Replace use of EXTRA_CONSTRAINT with OK_FOR_U.
(bit_memory_operand, fix_bit_operand): Likewise.
(h8300_length_table_for_insn): Remove.
(h8300_classify_operand): Fix check for 16-bit operands in 32-bit
instructions.
(h8300_short_immediate_length, h8300_binary_length): New functions.
(h8300_insn_length_from_table): Add an opcodes parameter. Rework.
(output_plussi): Use sub to add negative constants.
(compute_plussi_length): Adjust accordingly.
(h8sx_single_shift_type): New enum.
(h8sx_single_shift, h8sx_unary_shift_operator,
h8sx_binary_shift_operator, output_h8sx_shift): New functions.
(expand_a_shift, expand_a_rotate): Emit nothing if the shift is a
single h8sx instruction. Return false in this case.
* config/h8300/h8300.md (length_table): Add short_immediate.
(length): Pass the operand array to h8300_insn_length_from_table.
(adjust_length): Assume "no" for insns with a length_table attribute.
(*cmphi_h8300hs, cmpsi): Add alternatives for #xx:3.
(*addhi3_h8300hs): Don't use for h8sx.
(*addhi3_h8sx): New pattern, with alternatives for add.w #xx:3
and sub.w #xx:3.
(ashl[qhs]i3, lshr[qhs]i3, ashr[qhs]i3, rotl[qhs]i3): Change operand
1's predicate to nonimmediate_operand. Only skip default expansion
if expand_a_shift or expand_a_rotate returns true. Add new patterns
for single h8sx shift instructions.
2003-05-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (nibble_operand): Split out of...
(reg_or_nibble_operand): ... this.
* config/h8300/h8300.h (PREDICATE_CODES): Added nibble_operand.
* config/h8300/h8300.md: (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Introduce expand, and introduce separate insns for
sign- or zero-extended REG and already-extended CONST_INT.
2003-05-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_unary_length): Fix miscounting.
* config/h8300/h8300.md (subqi3): Generalize for h8sx.
(subhi3): Likewise. Don't accept immediates for operand 1.
Remove the early clobber from second alternative of the h8300s pattern.
(subsi3): Generalize for h8sx. Force operand 2 into a register
on plain h8300 targets.
(subsi3_h8300): Use h8300_dst_operand for consistency with expander.
(subsi3_h8300h): Generalize for h8sx.
(one_cmplqi2, one_cmplhi2, one_cmplsi2): Likewise.
2003-05-19 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (reg_or_nibble_operand): New.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
(TARGET_H8300SXMUL): New.
(CONST_OK_FOR_P): New.
(CONST_OK_FOR_LETTER_P): Adjust.
* config/h8300/h8300.md (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Accept 4-bit immediate on H8SX.
(mulhi3, mulsi3, smulsi3_highpart, umulsi3_highpart): New.
(udivsi3, divhi3, udivsi3, divsi3): New.
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_insn_length_from_table): Declare.
* config/h8300/h8300.h (OK_FOR_Q): New macro.
(EXTRA_CONSTRAINT): Use it to check the 'Q' constraint.
(PREDICATE_CODES): Add h8300_src_operand and h8300_dst_operand.
Add ADDRESSOF to the bit_operand entry.
* config/h8300/h8300.c (h8300_dst_operand): New predicate.
(h8300_src_operand): Likewise.
(bit_operand): Check nonimmediate_operand rather than general_operand.
Accept any nonimmediate_operand in h8sx code.
(h8300_and_costs): Initialize operands[1].
(h8300_rtx_costs) <AND>: Return false if the operands aren't valid.
(h8300_operand_class): New enum.
(h8300_length_table): New typedef.
(addb_length_table, addw_length_table, addl_length_table,
logicl_length_table): New tables.
(logicb_length_table, logicw_length_table): New macros.
(h8300_classify_operand, h8300_length_from_table,
h8300_length_table_for_insn, h8300_unary_length,
h8300_insn_length_from_table): New functions.
(output_plussi): Only use adds and subs for register destinations.
Disable redundant clause.
(compute_plussi_cc): Likewise.
(compute_plussi_length): Likewise. Use h8300_length_from_table
to work out the length of an insn.
(output_logical_op): Only use narrower immediate instructions
if the destination is a register.
(compute_logical_op_cc): Likewise.
(compute_logical_op_length): Likewise. Use h8300_length_from_table.
(h8300_adjust_insn_length): Tighten check for reg<->mem moves.
* config/h8300/h8300.md (length_table): New attribute.
(length): When an instruction has a length_table attribute, use
h8300_insn_length_from_table to calculate its default length.
(cmpqi): Use h8300_dst_operand for the first operand and
h8300_src_operand for the second.
(cmphi, *cmphi_h8300hs, cmpsi, negqi2, neghi2, neghi2_h8300h, negsi2,
negsi2_h8300h, addqi3, addhi3, *addhi3_h8300, *addhi3_h8300hs, addsi3,
addsi_h8300, addsi_h8300h, andhi3, andsi3, iorhi3,
iorsi3, xorhi3, xorsi3): Likewise.
(andqi3): Use h8300_src_operand for operand 2. Adjust the condition
so that it allows any combination of operands for TARGET_H8300SX.
(iorqi3, xorqi3): Likewise.
(cmpqi): Use the length_table attribute.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, andqi3, iorqi3,
xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
(cmpqi): Add 'Q' constraint.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, addsi_h8300h, andqi3,
iorqi3, xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
2003-05-14 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (MASK_H8300SX): New macro.
(TARGET_H8300S): True for both -ms and -msx.
(TARGET_H8300SX): New macro.
(TARGET_SWITCHES): Add entries for -msx and -mno-sx.
* config/h8300/h8300.c (asm_file_start): Write .h8300sx for -msx.
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxelf for -msx.
* config/h8300/t-h8300 (MULTILIB_MATCHES): Use -ms multilibs for -msx.
[Temporary change.]
2003-02-28 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.h (SIZE_TYPE, PTRDIFF_TYPE): Use short with
16-bit pointers and 32-bit ints.
* config/h8300/h8300.h (LEGITIMATE_CONSTANT_P): Accept
CONST_DOUBLE with mode no wider than SImode.
* config/h8300/h8300.md (extendqisi2_h8300): Add constraints for
output operand.
2003-02-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (general_operand_src): Match CONSTANT_P_RTX
or SUBREG thereof.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
2003-02-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (dosize): Truncate sign * size to Pmode.
From-SVN: r84257
2004-07-08 05:40:34 +02:00
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@cindex @code{movstr} instruction pattern
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@item @samp{movstr}
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String copy instruction, with @code{stpcpy} semantics. Operand 0 is
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an output operand in mode @code{Pmode}. The addresses of the
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destination and source strings are operands 1 and 2, and both are
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@code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
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the expansion of this pattern should store in operand 0 the address in
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which the @code{NUL} terminator was stored in the destination string.
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2005-06-28 21:56:23 +02:00
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@cindex @code{setmem@var{m}} instruction pattern
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@item @samp{setmem@var{m}}
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Block set instruction. The destination string is the first operand,
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Introduce H8SX support.
* expr.c (expand_strcpy): Renamed and moved to...
* builtins.c (expand_movstr): ... here. Tweak.
(expand_builtin_strcpy): Adjust. Use movstr if len can't be
computed or has side effects.
(expand_builtin_stpcpy): Likewise. Use strcpy if return value is
unused, or if mempcpy fails. Adjust the return value in the
latter case. Use movstr if everything else fails.
* doc/md.texi (movstr): Document.
(movmemM, clrmemM): Fix explanation of memory block operands.
* config/h8300/h8300.md (stpcpy): Renamed to...
(movstr): ... this. Adjust.
2004-07-07 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md: Rename movstr*, except for movstrict*, to
movmem* and clrstr* to clrmem*.
2004-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_reg_class_from_letter): Map 'D' to
GENERAL_REGS, always.
(h8300_swap_into_er6, h8300_swap_into_er6): Handle the case of
getting the stack pointer as addr.
* config/h8300/h8300.h (PREDICATE_CODES): Remove constant rtxes
from general_operand_dst.
* config/h8300/h8300.md (movmd_internal_normal): New, normal-mode
variant of...
(movmd_internal): ... this. Add modes to operands. Disparage `D'
instead of requiring it to match only before reload.
(stpcpy_internal_normal): New, normal-mode variant of...
(stpcpy_internal): ... this. Add modes to operands. Disparage
`D' instead of requiring it to match only before reload.
* config/h8300/h8300-protos.h (h8300_legitimate_address_p): Add
mode argument.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Pass it to...
* config/h8300/h8300.c (h8300_legitimate_address_p): Pass it to
h8300_get_index.
* config/h8300/h8300.md (attr type): Add call.
(attr can_delay): If type is call, set it no.
(call, call_value): Set type to call.
2004-06-21 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md (logicalhi3_sn, logicalsi3_sn): New.
2004-06-16 Alexandre Oliva <aoliva@redhat.com>
* tree.c (get_narrower): Don't narrow integral types into
non-integral types.
* config/h8300/h8300.c (h8300_expand_epilogue): Initialize
frame_size *before* the first use.
* config/h8300/h8300.md (movstrictqi): Reintroduce post-increment
on input.
(peephole2): Don't widen instructions that push SP. Move
decrement of SP to the end of all stm-generating peepholes.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (insv): Prefer to use AND to clear a bitfield
and OR to set it to all ones.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (can_delay): Default to "no" for bit branches.
(call, call_value): Set can_delay to "no".
2003-07-22 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Make subreg check more robust.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*brabit): Remove.
* config/h8300/h8300.md (*brabc, *brabs): Remove mode from
zero_extract. Use bit_memory_operand as the predicate for
operand 1 and 'WU' as the constraint. Check the difference
between the base length and the final one when deciding which
type of branch to use.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Remove mode from operands 0 and 1.
Use convert_move to extend the result for TARGET_H8300SX. Check
for QImode memory references. Optimize the case where the
destination is a paradoxical subreg.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*movsf_h8sx): Add an r <- G alternative.
* config/h8300/h8300.md (andqi): Remove bclr from h8sx version.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md: Include mova.md
(length_table): Add mova and mova_zero.
* config/h8300/h8300.c (print_operand): Handle '%o'. Print a length
after all constant addresses for '%R', '%X', '%T' and '%S'.
(h8300_mova_length): New function.
(h8300_insn_length_from_table): Use it to handle mova and mova_zero.
* config/h8300/t-h8300 (mova.md): Generate from genmova.sh. Add to
dependencies for s-config, etc.
* config/h8300/gemova.sh: New file.
* config/h8300/mova.md: Generated.
2003-07-20 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_bitfield_length): New.
(nibble_operand): Adjust.
(h8300_binary_length): Handle conditional binary op.
(h8300_insn_length_from_table): Handle bitfield and bitbranch.
* config/h8300/h8300.h: Change constraints W# and Y# to P#>X and
P#<X, respectively. The original P is now IP4>X. Introduced P#>0
and P#<0, unused so far. W and Y are now prefixes to multi-letter
constraints. WU is introduced as a variant of U that requires a
mem, and is therefore considered an EXTRA_MEMORY_CONSTRAINT.
* config/h8300/h8300.md (attr type): Added bitbranch.
(attr length_table): Added bitfield and bitbranch.
(attr length): Compute bitbranch length.
(andqi): Separate pattern for H8300SX. Use bfld for loading the
least-significant bit of a byte.
(brabit, brabc, brabs): New.
(insv, extzv): Emit bfst and bfld on H8300SX.
(bfld, bfst, seq, sne): New.
(bstzhireg, cmpstz, bstz, bistz): New.
(cmpcondbset, condbset, cmpcondbclr, condbclr): New.
(cmpcondbsetreg, condbsetreg, cmpcondbclrreg, condbclrreg): New.
2003-07-11 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8sx_binary_memory_operator): New function.
(h8sx_unary_memory_operator): New function.
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Disable.
(PREDICATE_CODES): Add h8sx_{unary,binary}_memory_operator.
* config/h8300/h8300.md: Add peepholes to combine reloads and
arithmetic insns.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h830.md (cmpqi): Use 'i' rather than 'n' in constraints.
(*cmphi_h8300hs, *addqi3, *addhi3_h8sx, subhi3): Likewise.
(and?i, ior?i, xor?i): Likewise.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c: Move enums and prototypes to head of file.
Various whitespace fixes.
(h8300_constant_length): New function, split out from...
(h8300_displacement_size): ...here. Rename h8300_displacement_length.
(h8300_classify_operand): Use IN_RANGE.
(h8300_classify_operand): Use h8300_constant_length.
(h8300_short_move_mem_p): Tighten size check.
(h8sx_mergeable_memrefs_p): Tighten equality check.
2003-06-30 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Define __H8300SX__
for -msx.
* config/h8300/crti.asm: Use .h8300sx or .h8300sxn for -msx code.
* config/h8300/crtn.asm: Likewise.
* config/h8300/lib1funcs.asm: Likewise. Use 32-bit pointers
if __H8300SX__ is defined.
2003-06-27 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_get_index): Add mode parameter.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Update accordingly.
(GO_IF_MODE_DEPENDENT_ADDRESS): Treat POST_DEC, PRE_INC and indexed
addresses as mode-dependent.
* config/h8300/h8300.c (print_operand_address): Update call to
h8300_get_index.
(h8300_get_index): Take a mode argument. Rework to fix an
earlier misunderstanding.
2003-06-26 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (zero_extendqisi2): Force the source operand
into a register if TARGET_H8300SX.
(*zero_extendqisi2_h8300hs, *extendqisi2_h8300): Disable for
TARGET_H8300SX. Also disable related define_splits.
(*zero_extendqisi2_h8sx, *extendqisi2_h8sx): New patterns.
2003-06-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_rtx_costs): Add h8sx handling.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (OK_FOR_Z): New macro.
(EXTRA_CONSTRAINT_STR): Check it.
* config/h8300/h8300.c (h8300_classify_operand): Accept null
class arguments.
(h8300_insn_length_from_table): Handle LENGTH_TABLE_MOV_IMM4.
* config/h8300/h8300.md (length_table): Add mov_imm4.
(movqi, movhi): Add Z <- W4 alternatives to h8sx patterns.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* genattrtab.c (write_eligible_delay): Allow candidate_insn to
be a label.
* config/h8300/h8300.h (DELAY_SLOT_LENGTH): New macro.
* config/h8300/h8300.c (h8300_reorg): New function.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/h8300/h8300.md (length): Subtract the length of the
delay slot from (pc) when checking the range of forward branches.
(delay_slot, can_delay): New attributes.
(define_delay): Add bra/s handling.
(movmd_internal, return_h8sx, *return_1): Set can_delay to no.
(jump): Add delayed-branch handling.
2003-06-17 Richard Sandiford <rsandifo@redhat.com>
* expr.c (expand_strcpy): New function.
* builtins.c (expand_builtin_strcpy): Fall back on expand_strcpy.
(expand_builtin_stpcpy): Likewise.
* config/h8300/h8300-protos.h (h8sx_split_movmd): Remove.
(h8300_swap_into_er6, h8300_swap_out_of_er6): Declare.
* config/h8300/h8300.c (h8300_reg_class_from_letter): Tweak 'd'
handling to improve register allocation for -fno-omit-frame-pointer.
(h8sx_split_movmd): Delete, moving er6 handling into...
(h8300_swap_into_er6, h8300_swap_out_of_er6): ...these new functions.
* config/h8300/h8300.md (UNSPEC_STPCPY): New unspec constant.
(movmd): Add calls to copy_rtx.
(movmd_internal): In the second alternative, allow the initial and
final destination registers to be different . Update the splitter
accordingly. Call h8300_swap_into_er6 and h8300_swap_out_of_er6
instead of h8sx_split_movmd.
(stpcpy, movsd): New expanders.
(movsd_internal): New define_insn.
2003-06-13 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_reg_class_from_letter): Declare.
(h8sx_emit_movmd, h8sx_split_movmd): Declare.
* config/h8300/h8300.h (reg_class): Add COUNTER_REGS, SOURCE_REGS
and DESTINATION_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
(REGNO_REG_CLASS): Map er4, er5 and er6 to the new classes.
(REG_CLASS_FROM_LETTER): Use h8300_reg_class_from_letter.
(h8300_move_ratio): Declare.
(MOVE_RATIO): Use it.
* config/h8300/h8300.c (h8300_move_ratio): New variable.
(h8300_init_once): Initialize it.
(h8300_reg_class_from_letter): New function.
(print_operand): Add an 'm' prefix for printing ".b", ".w" or ".l".
(h8sx_emit_movmd, h8sx_split_movmd): New functions.
* config/h8300/h8300.md (UNSPEC_MOVMD): New unspec constant.
(COUNTER_REG, SOURCE_REG, DESTINATION_REG): New register constants.
(movstrsi, movmd): New expanders.
(movmd_internal): New insn.
2003-06-06 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Define.
2003-06-04 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxnelf for -msx -mn.
* config/h8300/h8300.c (asm_file_start): Use .h8300sxn likewise.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (nibble_operand): Fix warning.
* config/h8300/h8300.md (movstricthi): Set adjust_length to no.
(movsi_h8sx): Likewise here and the normal h8sx movhi pattern.
(movsf_h8300h): Disable for TARGET_H8300SX.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (PREDICATE_CODES): Add h8300_ldm_parallel,
h8300_stm_parallel and h8300_return_parallel.
* config/h8300/h8300.c (h8300_push_pop, h8300_stack_offset_p,
h8300_ldm_stm_regno, h8300_ldm_stm_parallel, h8300_ldm_parallel,
h8300_stm_parallel, h8300_return_parallel): New functions.
(h8300_expand_prologue): Don't enforce ldm/stm register alignment
if TARGET_H8300SX. Use h8300_push_pop.
(h8300_expand_epilogue): Likewise. Try to merge the return insn
and final pop when generating h8sx code. Always emit some form
of return insn.
* config/h8300/h8300.md: Don't enforce register alignment in
stm peepholes if TARGET_H8300SX.
(ldm_h8300s, stm_h8300s, return_h8sx): New patterns.
(ldm_h8300s_[234], stm_h8300_[234]): Disable.
(epilogue): Expect h8300_expand_epilogue to emit a return insn.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/t-h8300 (MULTILIB_OPTIONS): Add a -msx multilib.
(MULTILIB_DIRNAMES): Add a directory for it.
(MULTILIB_MATCHES): Delete.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* final.c (walk_alter_subreg): Handle addresses with subregs
inside a ZERO_EXTEND or AND.
* config/h8300/h8300-protos.h (h8300_get_index): Declare.
* config/h8300/h8300.h (INDEX_REG_CLASS): Set to GENERAL_REGS
if TARGET_H8300SX.
(GO_IF_LEGITIMATE_ADDRESS): Use h8300_get_index.
* config/h8300/h8300.c (print_operand_address): Handle @(dd,RnL.b),
@(dd,Rn.w) and @(dd,ERn.L).
(h8300_displacement_size): Take the whole address as argument.
(h8300_classify_operand, h8300_short_move_mem_p): Adjust accordingly.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (h8300_operands_match_p): Declare.
(h8sx_mergeable_memrefs_p): Declare.
* config/h8300/h8300.h (HAVE_POST_DECREMENT): Define to TARGET_H8300SX.
(HAVE_PRE_INCREMENT): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): Accept pre/post increment/decrement
addresses for TARGET_H8300SX,
* config/h8300/h8300.c (print_operand_address): Deal with PRE_INC
and POST_DEC.
(movb_length_table, movl_length_table): New tables.
(movw_length_table): Define to movb_length_table.
(h8300_displacement_size): New, split out from...
(h8300_classify_address): ...here. Handle pre/post inc/dec.
(h8300_short_immediate_length): Allow H8OP_MEM_COMPLEX operands.
(h8300_insn_length_from_table): Add cases for movb, movw and movl.
(h8sx_mergeable_memrefs_p, h8300_operands_match_p): New functions.
(output_plussi): Use add.l #xx:3,Rn and sub.l #xx:3,Rn for h8sx.
(compute_plussi_length, compute_plussi_cc): Update accordingly.
(h8sx_unary_shift_operator): Get the mode from the operator.
(binary_shift_operator): Likewise.
* config/h8300/h8300.md: If a peephole2 applies gen_lowpart to
a memory reference, check whether the reference is offsettable.
(length_table): Add movb, movw and movl.
(movqi): Add new h8sx pattern. Don't force one operand to be a
register when generating h8sx code.
(movhi, movsi, movsf): Likewise.
(movstrictqi): Use the length_table attribute.
(movstricthi): Likewise. Add h8sx alternative for mov.w #xx:3,Rn.
(addqi3): Split into a define_expand and define_insn. Don't accept
memory operands in the expander. Use h8300_operands_match_p to
check for matching operands in the define_insn.
(subqi3, negqi2, one_cmplqi2): Likewise.
(add[hs]i3): Don't accept memory operands in the expander. Likewise
in any patterns that are unused in h8sx code. In the h8sx patterns,
use h8300_operands_match_p to check whether operands match.
(sub[hs]i3, and[hi]3, ior[hs]i3, xor[hs]i3, neg[hsi]3,
one_cmpl[hs]i3): Likewise.
(andqi3, iorqi3, xorqi3): Likewise. Don't call fix_bit_operand
in the expander.
2003-05-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (expand_a_shift): Return a bool.
(h8300_insn_length_from_table): Add a second parameter.
(output_h8sx_shift): Declare.
* config/h8300/h8300.h (OK_FOR_W, OK_FOR_Y): New macros.
(EXTRA_CONSTRAINT): Replace with...
(EXTRA_CONSTRAINT_STR): ...this. Use OK_FOR_W and OK_FOR_Y.
(CONSTRAINT_LEN): Define, returning 2 for 'W' and 'Y'.
(PREDICATE_CODES): Add entries for h8sx_unary_shift_operator
and h8sx_binary_shift_operator.
* config/h8300/h8300.c (two_insn_adds_subs_operand): Return false
for TARGET_H8300SX.
(bit_operand): Replace use of EXTRA_CONSTRAINT with OK_FOR_U.
(bit_memory_operand, fix_bit_operand): Likewise.
(h8300_length_table_for_insn): Remove.
(h8300_classify_operand): Fix check for 16-bit operands in 32-bit
instructions.
(h8300_short_immediate_length, h8300_binary_length): New functions.
(h8300_insn_length_from_table): Add an opcodes parameter. Rework.
(output_plussi): Use sub to add negative constants.
(compute_plussi_length): Adjust accordingly.
(h8sx_single_shift_type): New enum.
(h8sx_single_shift, h8sx_unary_shift_operator,
h8sx_binary_shift_operator, output_h8sx_shift): New functions.
(expand_a_shift, expand_a_rotate): Emit nothing if the shift is a
single h8sx instruction. Return false in this case.
* config/h8300/h8300.md (length_table): Add short_immediate.
(length): Pass the operand array to h8300_insn_length_from_table.
(adjust_length): Assume "no" for insns with a length_table attribute.
(*cmphi_h8300hs, cmpsi): Add alternatives for #xx:3.
(*addhi3_h8300hs): Don't use for h8sx.
(*addhi3_h8sx): New pattern, with alternatives for add.w #xx:3
and sub.w #xx:3.
(ashl[qhs]i3, lshr[qhs]i3, ashr[qhs]i3, rotl[qhs]i3): Change operand
1's predicate to nonimmediate_operand. Only skip default expansion
if expand_a_shift or expand_a_rotate returns true. Add new patterns
for single h8sx shift instructions.
2003-05-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (nibble_operand): Split out of...
(reg_or_nibble_operand): ... this.
* config/h8300/h8300.h (PREDICATE_CODES): Added nibble_operand.
* config/h8300/h8300.md: (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Introduce expand, and introduce separate insns for
sign- or zero-extended REG and already-extended CONST_INT.
2003-05-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_unary_length): Fix miscounting.
* config/h8300/h8300.md (subqi3): Generalize for h8sx.
(subhi3): Likewise. Don't accept immediates for operand 1.
Remove the early clobber from second alternative of the h8300s pattern.
(subsi3): Generalize for h8sx. Force operand 2 into a register
on plain h8300 targets.
(subsi3_h8300): Use h8300_dst_operand for consistency with expander.
(subsi3_h8300h): Generalize for h8sx.
(one_cmplqi2, one_cmplhi2, one_cmplsi2): Likewise.
2003-05-19 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (reg_or_nibble_operand): New.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
(TARGET_H8300SXMUL): New.
(CONST_OK_FOR_P): New.
(CONST_OK_FOR_LETTER_P): Adjust.
* config/h8300/h8300.md (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Accept 4-bit immediate on H8SX.
(mulhi3, mulsi3, smulsi3_highpart, umulsi3_highpart): New.
(udivsi3, divhi3, udivsi3, divsi3): New.
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_insn_length_from_table): Declare.
* config/h8300/h8300.h (OK_FOR_Q): New macro.
(EXTRA_CONSTRAINT): Use it to check the 'Q' constraint.
(PREDICATE_CODES): Add h8300_src_operand and h8300_dst_operand.
Add ADDRESSOF to the bit_operand entry.
* config/h8300/h8300.c (h8300_dst_operand): New predicate.
(h8300_src_operand): Likewise.
(bit_operand): Check nonimmediate_operand rather than general_operand.
Accept any nonimmediate_operand in h8sx code.
(h8300_and_costs): Initialize operands[1].
(h8300_rtx_costs) <AND>: Return false if the operands aren't valid.
(h8300_operand_class): New enum.
(h8300_length_table): New typedef.
(addb_length_table, addw_length_table, addl_length_table,
logicl_length_table): New tables.
(logicb_length_table, logicw_length_table): New macros.
(h8300_classify_operand, h8300_length_from_table,
h8300_length_table_for_insn, h8300_unary_length,
h8300_insn_length_from_table): New functions.
(output_plussi): Only use adds and subs for register destinations.
Disable redundant clause.
(compute_plussi_cc): Likewise.
(compute_plussi_length): Likewise. Use h8300_length_from_table
to work out the length of an insn.
(output_logical_op): Only use narrower immediate instructions
if the destination is a register.
(compute_logical_op_cc): Likewise.
(compute_logical_op_length): Likewise. Use h8300_length_from_table.
(h8300_adjust_insn_length): Tighten check for reg<->mem moves.
* config/h8300/h8300.md (length_table): New attribute.
(length): When an instruction has a length_table attribute, use
h8300_insn_length_from_table to calculate its default length.
(cmpqi): Use h8300_dst_operand for the first operand and
h8300_src_operand for the second.
(cmphi, *cmphi_h8300hs, cmpsi, negqi2, neghi2, neghi2_h8300h, negsi2,
negsi2_h8300h, addqi3, addhi3, *addhi3_h8300, *addhi3_h8300hs, addsi3,
addsi_h8300, addsi_h8300h, andhi3, andsi3, iorhi3,
iorsi3, xorhi3, xorsi3): Likewise.
(andqi3): Use h8300_src_operand for operand 2. Adjust the condition
so that it allows any combination of operands for TARGET_H8300SX.
(iorqi3, xorqi3): Likewise.
(cmpqi): Use the length_table attribute.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, andqi3, iorqi3,
xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
(cmpqi): Add 'Q' constraint.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, addsi_h8300h, andqi3,
iorqi3, xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
2003-05-14 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (MASK_H8300SX): New macro.
(TARGET_H8300S): True for both -ms and -msx.
(TARGET_H8300SX): New macro.
(TARGET_SWITCHES): Add entries for -msx and -mno-sx.
* config/h8300/h8300.c (asm_file_start): Write .h8300sx for -msx.
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxelf for -msx.
* config/h8300/t-h8300 (MULTILIB_MATCHES): Use -ms multilibs for -msx.
[Temporary change.]
2003-02-28 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.h (SIZE_TYPE, PTRDIFF_TYPE): Use short with
16-bit pointers and 32-bit ints.
* config/h8300/h8300.h (LEGITIMATE_CONSTANT_P): Accept
CONST_DOUBLE with mode no wider than SImode.
* config/h8300/h8300.md (extendqisi2_h8300): Add constraints for
output operand.
2003-02-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (general_operand_src): Match CONSTANT_P_RTX
or SUBREG thereof.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
2003-02-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (dosize): Truncate sign * size to Pmode.
From-SVN: r84257
2004-07-08 05:40:34 +02:00
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given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
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2005-06-28 21:56:23 +02:00
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number of bytes to set is the second operand, in mode @var{m}. The value to
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initialize the memory with is the third operand. Targets that only support the
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clearing of memory should reject any value that is not the constant 0. See
|
Introduce H8SX support.
* expr.c (expand_strcpy): Renamed and moved to...
* builtins.c (expand_movstr): ... here. Tweak.
(expand_builtin_strcpy): Adjust. Use movstr if len can't be
computed or has side effects.
(expand_builtin_stpcpy): Likewise. Use strcpy if return value is
unused, or if mempcpy fails. Adjust the return value in the
latter case. Use movstr if everything else fails.
* doc/md.texi (movstr): Document.
(movmemM, clrmemM): Fix explanation of memory block operands.
* config/h8300/h8300.md (stpcpy): Renamed to...
(movstr): ... this. Adjust.
2004-07-07 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md: Rename movstr*, except for movstrict*, to
movmem* and clrstr* to clrmem*.
2004-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_reg_class_from_letter): Map 'D' to
GENERAL_REGS, always.
(h8300_swap_into_er6, h8300_swap_into_er6): Handle the case of
getting the stack pointer as addr.
* config/h8300/h8300.h (PREDICATE_CODES): Remove constant rtxes
from general_operand_dst.
* config/h8300/h8300.md (movmd_internal_normal): New, normal-mode
variant of...
(movmd_internal): ... this. Add modes to operands. Disparage `D'
instead of requiring it to match only before reload.
(stpcpy_internal_normal): New, normal-mode variant of...
(stpcpy_internal): ... this. Add modes to operands. Disparage
`D' instead of requiring it to match only before reload.
* config/h8300/h8300-protos.h (h8300_legitimate_address_p): Add
mode argument.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Pass it to...
* config/h8300/h8300.c (h8300_legitimate_address_p): Pass it to
h8300_get_index.
* config/h8300/h8300.md (attr type): Add call.
(attr can_delay): If type is call, set it no.
(call, call_value): Set type to call.
2004-06-21 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.md (logicalhi3_sn, logicalsi3_sn): New.
2004-06-16 Alexandre Oliva <aoliva@redhat.com>
* tree.c (get_narrower): Don't narrow integral types into
non-integral types.
* config/h8300/h8300.c (h8300_expand_epilogue): Initialize
frame_size *before* the first use.
* config/h8300/h8300.md (movstrictqi): Reintroduce post-increment
on input.
(peephole2): Don't widen instructions that push SP. Move
decrement of SP to the end of all stm-generating peepholes.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (insv): Prefer to use AND to clear a bitfield
and OR to set it to all ones.
2003-07-24 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (can_delay): Default to "no" for bit branches.
(call, call_value): Set can_delay to "no".
2003-07-22 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Make subreg check more robust.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*brabit): Remove.
* config/h8300/h8300.md (*brabc, *brabs): Remove mode from
zero_extract. Use bit_memory_operand as the predicate for
operand 1 and 'WU' as the constraint. Check the difference
between the base length and the final one when deciding which
type of branch to use.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (extzv): Remove mode from operands 0 and 1.
Use convert_move to extend the result for TARGET_H8300SX. Check
for QImode memory references. Optimize the case where the
destination is a paradoxical subreg.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md (*movsf_h8sx): Add an r <- G alternative.
* config/h8300/h8300.md (andqi): Remove bclr from h8sx version.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.md: Include mova.md
(length_table): Add mova and mova_zero.
* config/h8300/h8300.c (print_operand): Handle '%o'. Print a length
after all constant addresses for '%R', '%X', '%T' and '%S'.
(h8300_mova_length): New function.
(h8300_insn_length_from_table): Use it to handle mova and mova_zero.
* config/h8300/t-h8300 (mova.md): Generate from genmova.sh. Add to
dependencies for s-config, etc.
* config/h8300/gemova.sh: New file.
* config/h8300/mova.md: Generated.
2003-07-20 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (h8300_bitfield_length): New.
(nibble_operand): Adjust.
(h8300_binary_length): Handle conditional binary op.
(h8300_insn_length_from_table): Handle bitfield and bitbranch.
* config/h8300/h8300.h: Change constraints W# and Y# to P#>X and
P#<X, respectively. The original P is now IP4>X. Introduced P#>0
and P#<0, unused so far. W and Y are now prefixes to multi-letter
constraints. WU is introduced as a variant of U that requires a
mem, and is therefore considered an EXTRA_MEMORY_CONSTRAINT.
* config/h8300/h8300.md (attr type): Added bitbranch.
(attr length_table): Added bitfield and bitbranch.
(attr length): Compute bitbranch length.
(andqi): Separate pattern for H8300SX. Use bfld for loading the
least-significant bit of a byte.
(brabit, brabc, brabs): New.
(insv, extzv): Emit bfst and bfld on H8300SX.
(bfld, bfst, seq, sne): New.
(bstzhireg, cmpstz, bstz, bistz): New.
(cmpcondbset, condbset, cmpcondbclr, condbclr): New.
(cmpcondbsetreg, condbsetreg, cmpcondbclrreg, condbclrreg): New.
2003-07-11 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8sx_binary_memory_operator): New function.
(h8sx_unary_memory_operator): New function.
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Disable.
(PREDICATE_CODES): Add h8sx_{unary,binary}_memory_operator.
* config/h8300/h8300.md: Add peepholes to combine reloads and
arithmetic insns.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h830.md (cmpqi): Use 'i' rather than 'n' in constraints.
(*cmphi_h8300hs, *addqi3, *addhi3_h8sx, subhi3): Likewise.
(and?i, ior?i, xor?i): Likewise.
2003-07-10 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c: Move enums and prototypes to head of file.
Various whitespace fixes.
(h8300_constant_length): New function, split out from...
(h8300_displacement_size): ...here. Rename h8300_displacement_length.
(h8300_classify_operand): Use IN_RANGE.
(h8300_classify_operand): Use h8300_constant_length.
(h8300_short_move_mem_p): Tighten size check.
(h8sx_mergeable_memrefs_p): Tighten equality check.
2003-06-30 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Define __H8300SX__
for -msx.
* config/h8300/crti.asm: Use .h8300sx or .h8300sxn for -msx code.
* config/h8300/crtn.asm: Likewise.
* config/h8300/lib1funcs.asm: Likewise. Use 32-bit pointers
if __H8300SX__ is defined.
2003-06-27 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_get_index): Add mode parameter.
* config/h8300/h8300.h (GO_IF_LEGITIMATE_ADDRESS): Update accordingly.
(GO_IF_MODE_DEPENDENT_ADDRESS): Treat POST_DEC, PRE_INC and indexed
addresses as mode-dependent.
* config/h8300/h8300.c (print_operand_address): Update call to
h8300_get_index.
(h8300_get_index): Take a mode argument. Rework to fix an
earlier misunderstanding.
2003-06-26 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (zero_extendqisi2): Force the source operand
into a register if TARGET_H8300SX.
(*zero_extendqisi2_h8300hs, *extendqisi2_h8300): Disable for
TARGET_H8300SX. Also disable related define_splits.
(*zero_extendqisi2_h8sx, *extendqisi2_h8sx): New patterns.
2003-06-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_rtx_costs): Add h8sx handling.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (OK_FOR_Z): New macro.
(EXTRA_CONSTRAINT_STR): Check it.
* config/h8300/h8300.c (h8300_classify_operand): Accept null
class arguments.
(h8300_insn_length_from_table): Handle LENGTH_TABLE_MOV_IMM4.
* config/h8300/h8300.md (length_table): Add mov_imm4.
(movqi, movhi): Add Z <- W4 alternatives to h8sx patterns.
2003-06-20 Richard Sandiford <rsandifo@redhat.com>
* genattrtab.c (write_eligible_delay): Allow candidate_insn to
be a label.
* config/h8300/h8300.h (DELAY_SLOT_LENGTH): New macro.
* config/h8300/h8300.c (h8300_reorg): New function.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/h8300/h8300.md (length): Subtract the length of the
delay slot from (pc) when checking the range of forward branches.
(delay_slot, can_delay): New attributes.
(define_delay): Add bra/s handling.
(movmd_internal, return_h8sx, *return_1): Set can_delay to no.
(jump): Add delayed-branch handling.
2003-06-17 Richard Sandiford <rsandifo@redhat.com>
* expr.c (expand_strcpy): New function.
* builtins.c (expand_builtin_strcpy): Fall back on expand_strcpy.
(expand_builtin_stpcpy): Likewise.
* config/h8300/h8300-protos.h (h8sx_split_movmd): Remove.
(h8300_swap_into_er6, h8300_swap_out_of_er6): Declare.
* config/h8300/h8300.c (h8300_reg_class_from_letter): Tweak 'd'
handling to improve register allocation for -fno-omit-frame-pointer.
(h8sx_split_movmd): Delete, moving er6 handling into...
(h8300_swap_into_er6, h8300_swap_out_of_er6): ...these new functions.
* config/h8300/h8300.md (UNSPEC_STPCPY): New unspec constant.
(movmd): Add calls to copy_rtx.
(movmd_internal): In the second alternative, allow the initial and
final destination registers to be different . Update the splitter
accordingly. Call h8300_swap_into_er6 and h8300_swap_out_of_er6
instead of h8sx_split_movmd.
(stpcpy, movsd): New expanders.
(movsd_internal): New define_insn.
2003-06-13 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_reg_class_from_letter): Declare.
(h8sx_emit_movmd, h8sx_split_movmd): Declare.
* config/h8300/h8300.h (reg_class): Add COUNTER_REGS, SOURCE_REGS
and DESTINATION_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
(REGNO_REG_CLASS): Map er4, er5 and er6 to the new classes.
(REG_CLASS_FROM_LETTER): Use h8300_reg_class_from_letter.
(h8300_move_ratio): Declare.
(MOVE_RATIO): Use it.
* config/h8300/h8300.c (h8300_move_ratio): New variable.
(h8300_init_once): Initialize it.
(h8300_reg_class_from_letter): New function.
(print_operand): Add an 'm' prefix for printing ".b", ".w" or ".l".
(h8sx_emit_movmd, h8sx_split_movmd): New functions.
* config/h8300/h8300.md (UNSPEC_MOVMD): New unspec constant.
(COUNTER_REG, SOURCE_REG, DESTINATION_REG): New register constants.
(movstrsi, movmd): New expanders.
(movmd_internal): New insn.
2003-06-06 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (EXTRA_MEMORY_CONSTRAINT): Define.
2003-06-04 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxnelf for -msx -mn.
* config/h8300/h8300.c (asm_file_start): Use .h8300sxn likewise.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (nibble_operand): Fix warning.
* config/h8300/h8300.md (movstricthi): Set adjust_length to no.
(movsi_h8sx): Likewise here and the normal h8sx movhi pattern.
(movsf_h8300h): Disable for TARGET_H8300SX.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (PREDICATE_CODES): Add h8300_ldm_parallel,
h8300_stm_parallel and h8300_return_parallel.
* config/h8300/h8300.c (h8300_push_pop, h8300_stack_offset_p,
h8300_ldm_stm_regno, h8300_ldm_stm_parallel, h8300_ldm_parallel,
h8300_stm_parallel, h8300_return_parallel): New functions.
(h8300_expand_prologue): Don't enforce ldm/stm register alignment
if TARGET_H8300SX. Use h8300_push_pop.
(h8300_expand_epilogue): Likewise. Try to merge the return insn
and final pop when generating h8sx code. Always emit some form
of return insn.
* config/h8300/h8300.md: Don't enforce register alignment in
stm peepholes if TARGET_H8300SX.
(ldm_h8300s, stm_h8300s, return_h8sx): New patterns.
(ldm_h8300s_[234], stm_h8300_[234]): Disable.
(epilogue): Expect h8300_expand_epilogue to emit a return insn.
2003-06-03 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/t-h8300 (MULTILIB_OPTIONS): Add a -msx multilib.
(MULTILIB_DIRNAMES): Add a directory for it.
(MULTILIB_MATCHES): Delete.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* final.c (walk_alter_subreg): Handle addresses with subregs
inside a ZERO_EXTEND or AND.
* config/h8300/h8300-protos.h (h8300_get_index): Declare.
* config/h8300/h8300.h (INDEX_REG_CLASS): Set to GENERAL_REGS
if TARGET_H8300SX.
(GO_IF_LEGITIMATE_ADDRESS): Use h8300_get_index.
* config/h8300/h8300.c (print_operand_address): Handle @(dd,RnL.b),
@(dd,Rn.w) and @(dd,ERn.L).
(h8300_displacement_size): Take the whole address as argument.
(h8300_classify_operand, h8300_short_move_mem_p): Adjust accordingly.
2003-05-28 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (h8300_operands_match_p): Declare.
(h8sx_mergeable_memrefs_p): Declare.
* config/h8300/h8300.h (HAVE_POST_DECREMENT): Define to TARGET_H8300SX.
(HAVE_PRE_INCREMENT): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): Accept pre/post increment/decrement
addresses for TARGET_H8300SX,
* config/h8300/h8300.c (print_operand_address): Deal with PRE_INC
and POST_DEC.
(movb_length_table, movl_length_table): New tables.
(movw_length_table): Define to movb_length_table.
(h8300_displacement_size): New, split out from...
(h8300_classify_address): ...here. Handle pre/post inc/dec.
(h8300_short_immediate_length): Allow H8OP_MEM_COMPLEX operands.
(h8300_insn_length_from_table): Add cases for movb, movw and movl.
(h8sx_mergeable_memrefs_p, h8300_operands_match_p): New functions.
(output_plussi): Use add.l #xx:3,Rn and sub.l #xx:3,Rn for h8sx.
(compute_plussi_length, compute_plussi_cc): Update accordingly.
(h8sx_unary_shift_operator): Get the mode from the operator.
(binary_shift_operator): Likewise.
* config/h8300/h8300.md: If a peephole2 applies gen_lowpart to
a memory reference, check whether the reference is offsettable.
(length_table): Add movb, movw and movl.
(movqi): Add new h8sx pattern. Don't force one operand to be a
register when generating h8sx code.
(movhi, movsi, movsf): Likewise.
(movstrictqi): Use the length_table attribute.
(movstricthi): Likewise. Add h8sx alternative for mov.w #xx:3,Rn.
(addqi3): Split into a define_expand and define_insn. Don't accept
memory operands in the expander. Use h8300_operands_match_p to
check for matching operands in the define_insn.
(subqi3, negqi2, one_cmplqi2): Likewise.
(add[hs]i3): Don't accept memory operands in the expander. Likewise
in any patterns that are unused in h8sx code. In the h8sx patterns,
use h8300_operands_match_p to check whether operands match.
(sub[hs]i3, and[hi]3, ior[hs]i3, xor[hs]i3, neg[hsi]3,
one_cmpl[hs]i3): Likewise.
(andqi3, iorqi3, xorqi3): Likewise. Don't call fix_bit_operand
in the expander.
2003-05-23 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (expand_a_shift): Return a bool.
(h8300_insn_length_from_table): Add a second parameter.
(output_h8sx_shift): Declare.
* config/h8300/h8300.h (OK_FOR_W, OK_FOR_Y): New macros.
(EXTRA_CONSTRAINT): Replace with...
(EXTRA_CONSTRAINT_STR): ...this. Use OK_FOR_W and OK_FOR_Y.
(CONSTRAINT_LEN): Define, returning 2 for 'W' and 'Y'.
(PREDICATE_CODES): Add entries for h8sx_unary_shift_operator
and h8sx_binary_shift_operator.
* config/h8300/h8300.c (two_insn_adds_subs_operand): Return false
for TARGET_H8300SX.
(bit_operand): Replace use of EXTRA_CONSTRAINT with OK_FOR_U.
(bit_memory_operand, fix_bit_operand): Likewise.
(h8300_length_table_for_insn): Remove.
(h8300_classify_operand): Fix check for 16-bit operands in 32-bit
instructions.
(h8300_short_immediate_length, h8300_binary_length): New functions.
(h8300_insn_length_from_table): Add an opcodes parameter. Rework.
(output_plussi): Use sub to add negative constants.
(compute_plussi_length): Adjust accordingly.
(h8sx_single_shift_type): New enum.
(h8sx_single_shift, h8sx_unary_shift_operator,
h8sx_binary_shift_operator, output_h8sx_shift): New functions.
(expand_a_shift, expand_a_rotate): Emit nothing if the shift is a
single h8sx instruction. Return false in this case.
* config/h8300/h8300.md (length_table): Add short_immediate.
(length): Pass the operand array to h8300_insn_length_from_table.
(adjust_length): Assume "no" for insns with a length_table attribute.
(*cmphi_h8300hs, cmpsi): Add alternatives for #xx:3.
(*addhi3_h8300hs): Don't use for h8sx.
(*addhi3_h8sx): New pattern, with alternatives for add.w #xx:3
and sub.w #xx:3.
(ashl[qhs]i3, lshr[qhs]i3, ashr[qhs]i3, rotl[qhs]i3): Change operand
1's predicate to nonimmediate_operand. Only skip default expansion
if expand_a_shift or expand_a_rotate returns true. Add new patterns
for single h8sx shift instructions.
2003-05-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (nibble_operand): Split out of...
(reg_or_nibble_operand): ... this.
* config/h8300/h8300.h (PREDICATE_CODES): Added nibble_operand.
* config/h8300/h8300.md: (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Introduce expand, and introduce separate insns for
sign- or zero-extended REG and already-extended CONST_INT.
2003-05-20 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.c (h8300_unary_length): Fix miscounting.
* config/h8300/h8300.md (subqi3): Generalize for h8sx.
(subhi3): Likewise. Don't accept immediates for operand 1.
Remove the early clobber from second alternative of the h8300s pattern.
(subsi3): Generalize for h8sx. Force operand 2 into a register
on plain h8300 targets.
(subsi3_h8300): Use h8300_dst_operand for consistency with expander.
(subsi3_h8300h): Generalize for h8sx.
(one_cmplqi2, one_cmplhi2, one_cmplsi2): Likewise.
2003-05-19 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (reg_or_nibble_operand): New.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
(TARGET_H8300SXMUL): New.
(CONST_OK_FOR_P): New.
(CONST_OK_FOR_LETTER_P): Adjust.
* config/h8300/h8300.md (mulqihi3, mulhisi3, umulqihi3,
umulhisi3): Accept 4-bit immediate on H8SX.
(mulhi3, mulsi3, smulsi3_highpart, umulsi3_highpart): New.
(udivsi3, divhi3, udivsi3, divsi3): New.
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300-protos.h (h8300_insn_length_from_table): Declare.
* config/h8300/h8300.h (OK_FOR_Q): New macro.
(EXTRA_CONSTRAINT): Use it to check the 'Q' constraint.
(PREDICATE_CODES): Add h8300_src_operand and h8300_dst_operand.
Add ADDRESSOF to the bit_operand entry.
* config/h8300/h8300.c (h8300_dst_operand): New predicate.
(h8300_src_operand): Likewise.
(bit_operand): Check nonimmediate_operand rather than general_operand.
Accept any nonimmediate_operand in h8sx code.
(h8300_and_costs): Initialize operands[1].
(h8300_rtx_costs) <AND>: Return false if the operands aren't valid.
(h8300_operand_class): New enum.
(h8300_length_table): New typedef.
(addb_length_table, addw_length_table, addl_length_table,
logicl_length_table): New tables.
(logicb_length_table, logicw_length_table): New macros.
(h8300_classify_operand, h8300_length_from_table,
h8300_length_table_for_insn, h8300_unary_length,
h8300_insn_length_from_table): New functions.
(output_plussi): Only use adds and subs for register destinations.
Disable redundant clause.
(compute_plussi_cc): Likewise.
(compute_plussi_length): Likewise. Use h8300_length_from_table
to work out the length of an insn.
(output_logical_op): Only use narrower immediate instructions
if the destination is a register.
(compute_logical_op_cc): Likewise.
(compute_logical_op_length): Likewise. Use h8300_length_from_table.
(h8300_adjust_insn_length): Tighten check for reg<->mem moves.
* config/h8300/h8300.md (length_table): New attribute.
(length): When an instruction has a length_table attribute, use
h8300_insn_length_from_table to calculate its default length.
(cmpqi): Use h8300_dst_operand for the first operand and
h8300_src_operand for the second.
(cmphi, *cmphi_h8300hs, cmpsi, negqi2, neghi2, neghi2_h8300h, negsi2,
negsi2_h8300h, addqi3, addhi3, *addhi3_h8300, *addhi3_h8300hs, addsi3,
addsi_h8300, addsi_h8300h, andhi3, andsi3, iorhi3,
iorsi3, xorhi3, xorsi3): Likewise.
(andqi3): Use h8300_src_operand for operand 2. Adjust the condition
so that it allows any combination of operands for TARGET_H8300SX.
(iorqi3, xorqi3): Likewise.
(cmpqi): Use the length_table attribute.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, andqi3, iorqi3,
xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
(cmpqi): Add 'Q' constraint.
(*cmphi_h8300hs, cmpsi, addqi, *addhi3_h8300hs, addsi_h8300h, andqi3,
iorqi3, xorqi3, negqi2, neghi2_h8300h, negsi2_h8300h): Likewise.
2003-05-14 Richard Sandiford <rsandifo@redhat.com>
* config/h8300/h8300.h (MASK_H8300SX): New macro.
(TARGET_H8300S): True for both -ms and -msx.
(TARGET_H8300SX): New macro.
(TARGET_SWITCHES): Add entries for -msx and -mno-sx.
* config/h8300/h8300.c (asm_file_start): Write .h8300sx for -msx.
* config/h8300/elf.h (LINK_SPEC): Use -m h8300sxelf for -msx.
* config/h8300/t-h8300 (MULTILIB_MATCHES): Use -ms multilibs for -msx.
[Temporary change.]
2003-02-28 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.h (SIZE_TYPE, PTRDIFF_TYPE): Use short with
16-bit pointers and 32-bit ints.
* config/h8300/h8300.h (LEGITIMATE_CONSTANT_P): Accept
CONST_DOUBLE with mode no wider than SImode.
* config/h8300/h8300.md (extendqisi2_h8300): Add constraints for
output operand.
2003-02-27 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (general_operand_src): Match CONSTANT_P_RTX
or SUBREG thereof.
* config/h8300/h8300.h (PREDICATE_CODES): Adjust.
2003-02-22 Alexandre Oliva <aoliva@redhat.com>
* config/h8300/h8300.c (dosize): Truncate sign * size to Pmode.
From-SVN: r84257
2004-07-08 05:40:34 +02:00
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|
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@samp{movmem@var{m}} for a discussion of the choice of mode.
|
1997-03-25 20:26:08 +01:00
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2005-06-28 21:56:23 +02:00
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The fourth operand is the known alignment of the destination, in the form
|
1997-03-25 20:26:08 +01:00
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of a @code{const_int} rtx. Thus, if the compiler knows that the
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destination is word-aligned, it may provide the value 4 for this
|
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operand.
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expr.c (emit_block_move_via_movmem, [...]): Add variant handling histograms; add wrapper.
* expr.c (emit_block_move_via_movmem, emit_block_move_via_libcall): Add
variant handling histograms; add wrapper.
(clear_storage_via_libcall): Export.
(emit_block_move_hints): Break out from ...; add histograms.
(emit_block_move): ... this one.
(clear_storage_hints): Break out from ...; add histograms.
(clear_storage): ... this one.
(set_storage_via_memset): Handle histogram.
* expr.h (emit_block_move_via_libcall, emit_block_move_hints): Declare.
(clear_storage_hints, clear_storage_via_libcall): Declare.
(set_storage_via_setmem): Update prototype.
* doc/md.texi (movmem, setmem): Document new arguments.
* value-prof.c (dump_histogram_value, tree_find_values_to_profile): Add
new histograms.
(stringop_block_profile): New global function.
(tree_stringops_values_to_profile): Profile block size and alignment.
* value-prof.h (enum hist_type): add HIST_TYPE_AVERAGE and
HIST_TYPE_IOR.
(struct profile_hooks): Add gen_average_profiler and gen_ior_profiler.
(stringop_block_profile): Declare.
* builtins.c: Include value-prof.h.
(expand_builtin_memcpy, expand_builtin_memset): Pass block profile.
* gcov-ui.h (GCOV_COUNTER_NAMES): Add new counter.
(GCOV_COUNTER_AVERAGE, GCOV_COUNTER_IOR): New constants.
(GCOV_COUNTERS, GCOV_LAST_VALUE_COUNTER): Update.
* profile.c (instrument_values): Add new counters.
* cfgexpand.c (expand_gimple_basic_block): Propagate histograms to
calls.
* tree-profile.c (tree_average_profiler_fn, tree_ior_profiler_fn): New.
(tree_init_edge_profiler): Build new profilers.
(tree_gen_average_profiler, tree_gen_ior_profiler): New.
(pass_tree_profile): Add dump.
(tree_profile_hooks): Update.
* Makefile.in (LIBGCOV): Add new constants.
* libgcov.c (__gcov_merge_ior, __gcov_average_profiler,
__gcov_ior_profiler): New.
* i386.md (movmem/setmem expanders): Add new optional arguments.
From-SVN: r121270
2007-01-28 20:38:39 +01:00
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Optional operands 5 and 6 specify expected alignment and size of block
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respectively. The expected alignment differs from alignment in operand 4
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in a way that the blocks are not required to be aligned according to it in
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all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
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2005-06-28 21:56:23 +02:00
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The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
|
1998-02-02 01:17:02 +01:00
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2005-07-12 11:20:21 +02:00
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@cindex @code{cmpstrn@var{m}} instruction pattern
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@item @samp{cmpstrn@var{m}}
|
2003-07-11 23:04:56 +02:00
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String compare instruction, with five operands. Operand 0 is the output;
|
1997-03-25 20:26:08 +01:00
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it has mode @var{m}. The remaining four operands are like the operands
|
2004-07-07 21:25:01 +02:00
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of @samp{movmem@var{m}}. The two memory blocks specified are compared
|
2003-04-26 22:44:30 +02:00
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byte by byte in lexicographic order starting at the beginning of each
|
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string. The instruction is not allowed to prefetch more than one byte
|
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at a time since either string may end in the first byte and reading past
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that may access an invalid page or segment and cause a fault. The
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effect of the instruction is to store a value in operand 0 whose sign
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indicates the result of the comparison.
|
1997-03-25 20:26:08 +01:00
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2005-07-12 11:20:21 +02:00
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@cindex @code{cmpstr@var{m}} instruction pattern
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@item @samp{cmpstr@var{m}}
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String compare instruction, without known maximum length. Operand 0 is the
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output; it has mode @var{m}. The second and third operand are the blocks of
|
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memory to be compared; both are @code{mem:BLK} with an address in mode
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@code{Pmode}.
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The fourth operand is the known shared alignment of the source and
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destination, in the form of a @code{const_int} rtx. Thus, if the
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compiler knows that both source and destination are word-aligned,
|
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it may provide the value 4 for this operand.
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The two memory blocks specified are compared byte by byte in lexicographic
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order starting at the beginning of each string. The instruction is not allowed
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|
|
|
to prefetch more than one byte at a time since either string may end in the
|
|
|
|
first byte and reading past that may access an invalid page or segment and
|
|
|
|
cause a fault. The effect of the instruction is to store a value in operand 0
|
|
|
|
whose sign indicates the result of the comparison.
|
|
|
|
|
2003-07-11 23:04:56 +02:00
|
|
|
@cindex @code{cmpmem@var{m}} instruction pattern
|
|
|
|
@item @samp{cmpmem@var{m}}
|
|
|
|
Block compare instruction, with five operands like the operands
|
|
|
|
of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
|
|
|
|
byte by byte in lexicographic order starting at the beginning of each
|
|
|
|
block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
|
|
|
|
any bytes in the two memory blocks. The effect of the instruction is
|
|
|
|
to store a value in operand 0 whose sign indicates the result of the
|
|
|
|
comparison.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{strlen@var{m}} instruction pattern
|
|
|
|
@item @samp{strlen@var{m}}
|
|
|
|
Compute the length of a string, with three operands.
|
|
|
|
Operand 0 is the result (of mode @var{m}), operand 1 is
|
|
|
|
a @code{mem} referring to the first character of the string,
|
|
|
|
operand 2 is the character to search for (normally zero),
|
|
|
|
and operand 3 is a constant describing the known alignment
|
|
|
|
of the beginning of the string.
|
|
|
|
|
|
|
|
@cindex @code{float@var{mn}2} instruction pattern
|
|
|
|
@item @samp{float@var{m}@var{n}2}
|
|
|
|
Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
|
|
|
|
floating point mode @var{n} and store in operand 0 (which has mode
|
|
|
|
@var{n}).
|
|
|
|
|
|
|
|
@cindex @code{floatuns@var{mn}2} instruction pattern
|
|
|
|
@item @samp{floatuns@var{m}@var{n}2}
|
|
|
|
Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
|
|
|
|
to floating point mode @var{n} and store in operand 0 (which has mode
|
|
|
|
@var{n}).
|
|
|
|
|
|
|
|
@cindex @code{fix@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fix@var{m}@var{n}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as a signed number and store in operand 0 (which
|
|
|
|
has mode @var{n}). This instruction's result is defined only when
|
|
|
|
the value of operand 1 is an integer.
|
|
|
|
|
2004-02-19 19:50:57 +01:00
|
|
|
If the machine description defines this pattern, it also needs to
|
|
|
|
define the @code{ftrunc} pattern.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{fixuns@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fixuns@var{m}@var{n}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
|
|
|
point mode @var{n} as an unsigned number and store in operand 0 (which
|
|
|
|
has mode @var{n}). This instruction's result is defined only when the
|
|
|
|
value of operand 1 is an integer.
|
|
|
|
|
|
|
|
@cindex @code{ftrunc@var{m}2} instruction pattern
|
|
|
|
@item @samp{ftrunc@var{m}2}
|
|
|
|
Convert operand 1 (valid for floating point mode @var{m}) to an
|
|
|
|
integer value, still represented in floating point mode @var{m}, and
|
|
|
|
store it in operand 0 (valid for floating point mode @var{m}).
|
|
|
|
|
|
|
|
@cindex @code{fix_trunc@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fix_trunc@var{m}@var{n}2}
|
|
|
|
Like @samp{fix@var{m}@var{n}2} but works for any floating point value
|
|
|
|
of mode @var{m} by converting the value to an integer.
|
|
|
|
|
|
|
|
@cindex @code{fixuns_trunc@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fixuns_trunc@var{m}@var{n}2}
|
|
|
|
Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
|
|
|
|
value of mode @var{m} by converting the value to an integer.
|
|
|
|
|
|
|
|
@cindex @code{trunc@var{mn}2} instruction pattern
|
|
|
|
@item @samp{trunc@var{m}@var{n}2}
|
|
|
|
Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
|
|
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
|
|
|
point or both floating point.
|
|
|
|
|
|
|
|
@cindex @code{extend@var{mn}2} instruction pattern
|
|
|
|
@item @samp{extend@var{m}@var{n}2}
|
|
|
|
Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
|
|
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
|
|
|
point or both floating point.
|
|
|
|
|
|
|
|
@cindex @code{zero_extend@var{mn}2} instruction pattern
|
|
|
|
@item @samp{zero_extend@var{m}@var{n}2}
|
|
|
|
Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
|
|
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
|
|
|
point.
|
|
|
|
|
stdfix.h: New file.
* ginclude/stdfix.h: New file.
* Makefile.in (USER_H): Add $(srcdir)/ginclude/stdfix.h.
(convert.o): Add dependence on fixed-value.h.
* c-convert.c (convert): Support FIXED_POINT_TYPE.
* c-cppbuiltin.c (builtin_define_fixed_point_constants): New function
to define fixed-point constants.
(c_cpp_builtins): Define fixed-point constants.
* convert.c (fixed-value.h): New include.
(convert_to_real): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_integer): Update comment to include fixed-point.
Support FIXED_POINT_TYPE.
(convert_to_complex): Support FIXED_POINT_TYPE.
(convert_to_fixed): New function.
* convert.h (convert_to_fixed): Declare.
* genopinit.c: Add comment about $Q for only fixed-point modes.
(optabs): Add fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab, add_optab, ssadd_optab, usadd_optab, sub_optab,
sssub_optab, ussub_optab, smul_optab, ssmul_optab, usmul_optab,
ssmadd_widen_optab, usmadd_widen_optab, ssdiv_optab, udiv_optab,
usdiv_optab, ssashl_optab, usashl_optab, neg_optab, ssneg_optab,
usneg_optab for fixed-point modes.
(gen_insn): Add force_fixed to track the $Q format for all fixed-point
modes.
* optabs.c (optab_for_tree_code): For *DIV_EXPR, LSHIFT_EXPR,
PLUS_EXPR, MINUS_EXPR, MULT_EXPR, NEGATE_EXPR, return signed or
unsigned saturation optabs, when type is saturating.
(shift_optab_p): Return true for SS_ASHIFT or US_ASHIFT.
(expand_fixed_convert): New function.
(gen_fixed_libfunc, gen_signed_fixed_libfunc,
gen_unsigned_fixed_libfunc, gen_int_fp_fixed_libfunc,
gen_int_fp_signed_fixed_libfunc, gen_int_fixed_libfunc,
gen_int_signed_fixed_libfunc, gen_int_unsigned_fixed_libfunc,
gen_fract_conv_libfunc, gen_fractuns_conv_libfunc,
gen_satfract_conv_libfunc, gen_satfractuns_conv_libfunc): New
functions.
(init_optabs): Initialize ssadd_optab, usadd_optab, sssub_optab,
ussub_optab, ssmul_optab, usmul_optab, ssmadd_widen_optab,
usmadd_widen_optab, ssmsub_widen_optab, usmsub_widen_optab,
ssdiv_optab, usdiv_optab, ssashl_optab, usashl_optab, ssneg_optab,
usneg_optab, fract_optab, fractuns_optab, satfract_optab,
satfractuns_optab.
Initialize fixed-point libraries, including add, ssadd, usadd, sub,
sssub, ussub, mul, ssmul, usmul, div, ssdiv, udiv, usdiv, ashl,
ssashl, usashl, ashr, lshr, neg, ssneg, usneg, cmp, fract, satfract,
fractuns, satfractuns.
* optabs.h (enum optab_index): Add OTI_ssadd, OTI_usadd, OTI_sssub,
OTI_ussub, OTI_ssmul, OTI_usmul, OTI_ssdiv, OTI_usdiv, OTI_ssneg,
OTI_usneg, OTI_ssashl, OTI_usashl, OTI_ssmadd_widen, OTI_usmadd_widen,
OTI_ssmsub_widen, OTI_usmsub_widen.
(ssadd_optab, usadd_optab, sssub_optab, ussub_optab, ssmul_optab,
usmul_optab, ssdiv_optab, usdiv_optab, ssneg_optab, usneg_optab,
ssashl_optab, usashl_optab, ssmadd_widen_optab, usmadd_widen_optab,
umsub_widen_optab, usmsub_widen_optab): Define.
(enum convert_optab_index): Add COI_fract, COI_fractuns, COI_satfract,
COI_satfractuns.
(fract_optab, fractuns_optab, satfract_optab, satfractuns_optab):
Define.
(expand_fixed_convert): Declare.
* expr.c (convert_move): Support the move of fixed-point modes.
(emit_move_insn_1): Handle fixed-point mode to move via integer.
(categorize_ctor_elements_1): Handle FIXED_CST.
(count_type_elements): Handle FIXED_POINT_TYPE.
(expand_expr_real_1): For VECTOR_CST, check MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
Support FIXED_CST.
For PLUS_EXPR and MINUS_EXPR, support saturating and non-saturating
multiply and add/subtract for fixed-point types.
For MULT_EXPR, *DIV_EXPR, *SHIFT_EXPR, if the mode if a fixed-point
mode, we jump to binop directly.
Support FIXED_CONVERT_EXPR.
(do_store_flag): Check FIXED_CST to put a constant second.
(vector_mode_valid_p): Handle MODE_VECTOR_FRACT,
MODE_VECTOR_UFRACT, MODE_VECTOR_ACCUM, MODE_VECTOR_UACCUM.
(const_vector_from_tree): Support FIXED_CST.
* doc/extend.texi (Fixed-Point): New node.
* doc/md.texi (ssadd, usadd, sssub, ussub, ssmul, usmul, ssdiv, usdiv,
ssmadd, usmadd, ssmsub, usmsub, ssashl, usashl, ssneg, usneg, fract,
satfract, fractuns, satfractuns): Document them.
From-SVN: r128218
2007-09-07 03:24:09 +02:00
|
|
|
@cindex @code{fract@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fract@var{m}@var{n}2}
|
|
|
|
Convert operand 1 of mode @var{m} to mode @var{n} and store in
|
|
|
|
operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
|
|
|
|
could be fixed-point to fixed-point, signed integer to fixed-point,
|
|
|
|
fixed-point to signed integer, floating-point to fixed-point,
|
|
|
|
or fixed-point to floating-point.
|
|
|
|
When overflows or underflows happen, the results are undefined.
|
|
|
|
|
|
|
|
@cindex @code{satfract@var{mn}2} instruction pattern
|
|
|
|
@item @samp{satfract@var{m}@var{n}2}
|
|
|
|
Convert operand 1 of mode @var{m} to mode @var{n} and store in
|
|
|
|
operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
|
|
|
|
could be fixed-point to fixed-point, signed integer to fixed-point,
|
|
|
|
or floating-point to fixed-point.
|
|
|
|
When overflows or underflows happen, the instruction saturates the
|
|
|
|
results to the maximum or the minimum.
|
|
|
|
|
|
|
|
@cindex @code{fractuns@var{mn}2} instruction pattern
|
|
|
|
@item @samp{fractuns@var{m}@var{n}2}
|
|
|
|
Convert operand 1 of mode @var{m} to mode @var{n} and store in
|
|
|
|
operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
|
|
|
|
could be unsigned integer to fixed-point, or
|
|
|
|
fixed-point to unsigned integer.
|
|
|
|
When overflows or underflows happen, the results are undefined.
|
|
|
|
|
|
|
|
@cindex @code{satfractuns@var{mn}2} instruction pattern
|
|
|
|
@item @samp{satfractuns@var{m}@var{n}2}
|
|
|
|
Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
|
|
|
|
@var{n} and store in operand 0 (which has mode @var{n}).
|
|
|
|
When overflows or underflows happen, the instruction saturates the
|
|
|
|
results to the maximum or the minimum.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{extv} instruction pattern
|
|
|
|
@item @samp{extv}
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
Extract a bit-field from operand 1 (a register or memory operand), where
|
1997-03-25 20:26:08 +01:00
|
|
|
operand 2 specifies the width in bits and operand 3 the starting bit,
|
|
|
|
and store it in operand 0. Operand 0 must have mode @code{word_mode}.
|
|
|
|
Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
|
|
|
|
@code{word_mode} is allowed only for registers. Operands 2 and 3 must
|
|
|
|
be valid for @code{word_mode}.
|
|
|
|
|
|
|
|
The RTL generation pass generates this instruction only with constants
|
2005-11-07 20:14:02 +01:00
|
|
|
for operands 2 and 3 and the constant is never zero for operand 2.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
The bit-field value is sign-extended to a full word integer
|
|
|
|
before it is stored in operand 0.
|
|
|
|
|
|
|
|
@cindex @code{extzv} instruction pattern
|
|
|
|
@item @samp{extzv}
|
|
|
|
Like @samp{extv} except that the bit-field value is zero-extended.
|
|
|
|
|
|
|
|
@cindex @code{insv} instruction pattern
|
|
|
|
@item @samp{insv}
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
Store operand 3 (which must be valid for @code{word_mode}) into a
|
|
|
|
bit-field in operand 0, where operand 1 specifies the width in bits and
|
1997-03-25 20:26:08 +01:00
|
|
|
operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
|
|
|
|
@code{word_mode}; often @code{word_mode} is allowed only for registers.
|
|
|
|
Operands 1 and 2 must be valid for @code{word_mode}.
|
|
|
|
|
|
|
|
The RTL generation pass generates this instruction only with constants
|
2005-11-07 20:14:02 +01:00
|
|
|
for operands 1 and 2 and the constant is never zero for operand 1.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{mov@var{mode}cc} instruction pattern
|
|
|
|
@item @samp{mov@var{mode}cc}
|
|
|
|
Conditionally move operand 2 or operand 3 into operand 0 according to the
|
|
|
|
comparison in operand 1. If the comparison is true, operand 2 is moved
|
|
|
|
into operand 0, otherwise operand 3 is moved.
|
|
|
|
|
|
|
|
The mode of the operands being compared need not be the same as the operands
|
|
|
|
being moved. Some machines, sparc64 for example, have instructions that
|
|
|
|
conditionally move an integer value based on the floating point condition
|
|
|
|
codes and vice versa.
|
|
|
|
|
|
|
|
If the machine does not have conditional move instructions, do not
|
|
|
|
define these patterns.
|
|
|
|
|
2003-01-07 22:09:21 +01:00
|
|
|
@cindex @code{add@var{mode}cc} instruction pattern
|
2003-07-08 08:44:00 +02:00
|
|
|
@item @samp{add@var{mode}cc}
|
2003-01-07 22:09:21 +01:00
|
|
|
Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
|
|
|
|
move operand 2 or (operands 2 + operand 3) into operand 0 according to the
|
|
|
|
comparison in operand 1. If the comparison is true, operand 2 is moved into
|
2003-07-08 08:44:00 +02:00
|
|
|
operand 0, otherwise (operand 2 + operand 3) is moved.
|
2003-01-07 22:09:21 +01:00
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{s@var{cond}} instruction pattern
|
|
|
|
@item @samp{s@var{cond}}
|
|
|
|
Store zero or nonzero in the operand according to the condition codes.
|
|
|
|
Value stored is nonzero iff the condition @var{cond} is true.
|
|
|
|
@var{cond} is the name of a comparison operation expression code, such
|
|
|
|
as @code{eq}, @code{lt} or @code{leu}.
|
|
|
|
|
|
|
|
You specify the mode that the operand must have when you write the
|
|
|
|
@code{match_operand} expression. The compiler automatically sees
|
|
|
|
which mode you have used and supplies an operand of that mode.
|
|
|
|
|
|
|
|
The value stored for a true condition must have 1 as its low bit, or
|
|
|
|
else must be negative. Otherwise the instruction is not suitable and
|
|
|
|
you should omit it from the machine description. You describe to the
|
|
|
|
compiler exactly which value is stored by defining the macro
|
|
|
|
@code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
|
|
|
|
found that can be used for all the @samp{s@var{cond}} patterns, you
|
|
|
|
should omit those operations from the machine description.
|
|
|
|
|
|
|
|
These operations may fail, but should do so only in relatively
|
|
|
|
uncommon cases; if they would fail for common cases involving
|
|
|
|
integer comparisons, it is best to omit these patterns.
|
|
|
|
|
|
|
|
If these operations are omitted, the compiler will usually generate code
|
|
|
|
that copies the constant one to the target and branches around an
|
|
|
|
assignment of zero to the target. If this code is more efficient than
|
|
|
|
the potential instructions used for the @samp{s@var{cond}} pattern
|
|
|
|
followed by those required to convert the result into a 1 or a zero in
|
|
|
|
@code{SImode}, you should omit the @samp{s@var{cond}} operations from
|
|
|
|
the machine description.
|
|
|
|
|
|
|
|
@cindex @code{b@var{cond}} instruction pattern
|
|
|
|
@item @samp{b@var{cond}}
|
|
|
|
Conditional branch instruction. Operand 0 is a @code{label_ref} that
|
|
|
|
refers to the label to jump to. Jump if the condition codes meet
|
|
|
|
condition @var{cond}.
|
|
|
|
|
|
|
|
Some machines do not follow the model assumed here where a comparison
|
|
|
|
instruction is followed by a conditional branch instruction. In that
|
|
|
|
case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
|
|
|
|
simply store the operands away and generate all the required insns in a
|
|
|
|
@code{define_expand} (@pxref{Expander Definitions}) for the conditional
|
|
|
|
branch operations. All calls to expand @samp{b@var{cond}} patterns are
|
|
|
|
immediately preceded by calls to expand either a @samp{cmp@var{m}}
|
|
|
|
pattern or a @samp{tst@var{m}} pattern.
|
|
|
|
|
|
|
|
Machines that use a pseudo register for the condition code value, or
|
|
|
|
where the mode used for the comparison depends on the condition being
|
1999-02-27 01:16:01 +01:00
|
|
|
tested, should also use the above mechanism. @xref{Jump Patterns}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
The above discussion also applies to the @samp{mov@var{mode}cc} and
|
|
|
|
@samp{s@var{cond}} patterns.
|
|
|
|
|
2004-03-03 05:22:08 +01:00
|
|
|
@cindex @code{cbranch@var{mode}4} instruction pattern
|
|
|
|
@item @samp{cbranch@var{mode}4}
|
|
|
|
Conditional branch instruction combined with a compare instruction.
|
|
|
|
Operand 0 is a comparison operator. Operand 1 and operand 2 are the
|
|
|
|
first and second operands of the comparison, respectively. Operand 3
|
|
|
|
is a @code{label_ref} that refers to the label to jump to.
|
|
|
|
|
2000-03-16 13:18:18 +01:00
|
|
|
@cindex @code{jump} instruction pattern
|
|
|
|
@item @samp{jump}
|
|
|
|
A jump inside a function; an unconditional branch. Operand 0 is the
|
|
|
|
@code{label_ref} of the label to jump to. This pattern name is mandatory
|
|
|
|
on all machines.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{call} instruction pattern
|
|
|
|
@item @samp{call}
|
|
|
|
Subroutine call instruction returning no value. Operand 0 is the
|
|
|
|
function to call; operand 1 is the number of bytes of arguments pushed
|
1998-05-06 01:18:02 +02:00
|
|
|
as a @code{const_int}; operand 2 is the number of registers used as
|
|
|
|
operands.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
On most machines, operand 2 is not actually stored into the RTL
|
|
|
|
pattern. It is supplied for the sake of some RISC machines which need
|
|
|
|
to put this information into the assembler code; they can put it in
|
|
|
|
the RTL instead of operand 1.
|
|
|
|
|
|
|
|
Operand 0 should be a @code{mem} RTX whose address is the address of the
|
|
|
|
function. Note, however, that this address can be a @code{symbol_ref}
|
|
|
|
expression even if it would not be a legitimate memory address on the
|
|
|
|
target machine. If it is also not a valid argument for a call
|
|
|
|
instruction, the pattern for this operation should be a
|
|
|
|
@code{define_expand} (@pxref{Expander Definitions}) that places the
|
|
|
|
address into a register and uses that register in the call instruction.
|
|
|
|
|
|
|
|
@cindex @code{call_value} instruction pattern
|
|
|
|
@item @samp{call_value}
|
|
|
|
Subroutine call instruction returning a value. Operand 0 is the hard
|
|
|
|
register in which the value is returned. There are three more
|
|
|
|
operands, the same as the three operands of the @samp{call}
|
|
|
|
instruction (but with numbers increased by one).
|
|
|
|
|
|
|
|
Subroutines that return @code{BLKmode} objects use the @samp{call}
|
|
|
|
insn.
|
|
|
|
|
|
|
|
@cindex @code{call_pop} instruction pattern
|
|
|
|
@cindex @code{call_value_pop} instruction pattern
|
|
|
|
@item @samp{call_pop}, @samp{call_value_pop}
|
|
|
|
Similar to @samp{call} and @samp{call_value}, except used if defined and
|
2001-10-10 01:11:55 +02:00
|
|
|
if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
|
1997-03-25 20:26:08 +01:00
|
|
|
that contains both the function call and a @code{set} to indicate the
|
|
|
|
adjustment made to the frame pointer.
|
|
|
|
|
2001-10-10 01:11:55 +02:00
|
|
|
For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
|
1997-03-25 20:26:08 +01:00
|
|
|
patterns increases the number of functions for which the frame pointer
|
|
|
|
can be eliminated, if desired.
|
|
|
|
|
|
|
|
@cindex @code{untyped_call} instruction pattern
|
|
|
|
@item @samp{untyped_call}
|
|
|
|
Subroutine call instruction returning a value of any type. Operand 0 is
|
|
|
|
the function to call; operand 1 is a memory location where the result of
|
|
|
|
calling the function is to be stored; operand 2 is a @code{parallel}
|
|
|
|
expression where each element is a @code{set} expression that indicates
|
|
|
|
the saving of a function return value into the result block.
|
|
|
|
|
|
|
|
This instruction pattern should be defined to support
|
|
|
|
@code{__builtin_apply} on machines where special instructions are needed
|
|
|
|
to call a subroutine with arbitrary arguments or to save the value
|
|
|
|
returned. This instruction pattern is required on machines that have
|
2001-06-27 02:04:39 +02:00
|
|
|
multiple registers that can hold a return value
|
|
|
|
(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{return} instruction pattern
|
|
|
|
@item @samp{return}
|
|
|
|
Subroutine return instruction. This instruction pattern name should be
|
|
|
|
defined only if a single instruction can do all the work of returning
|
|
|
|
from a function.
|
|
|
|
|
|
|
|
Like the @samp{mov@var{m}} patterns, this pattern is also used after the
|
|
|
|
RTL generation phase. In this case it is to support machines where
|
|
|
|
multiple instructions are usually needed to return from a function, but
|
|
|
|
some class of functions only requires one instruction to implement a
|
|
|
|
return. Normally, the applicable functions are those which do not need
|
|
|
|
to save any registers or allocate stack space.
|
|
|
|
|
|
|
|
@findex reload_completed
|
|
|
|
@findex leaf_function_p
|
|
|
|
For such machines, the condition specified in this pattern should only
|
2001-10-10 01:11:55 +02:00
|
|
|
be true when @code{reload_completed} is nonzero and the function's
|
1997-03-25 20:26:08 +01:00
|
|
|
epilogue would only be a single instruction. For machines with register
|
|
|
|
windows, the routine @code{leaf_function_p} may be used to determine if
|
|
|
|
a register window push is required.
|
|
|
|
|
|
|
|
Machines that have conditional return instructions should define patterns
|
|
|
|
such as
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(set (pc)
|
|
|
|
(if_then_else (match_operator
|
|
|
|
0 "comparison_operator"
|
|
|
|
[(cc0) (const_int 0)])
|
|
|
|
(return)
|
|
|
|
(pc)))]
|
|
|
|
"@var{condition}"
|
|
|
|
"@dots{}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
where @var{condition} would normally be the same condition specified on the
|
|
|
|
named @samp{return} pattern.
|
|
|
|
|
|
|
|
@cindex @code{untyped_return} instruction pattern
|
|
|
|
@item @samp{untyped_return}
|
|
|
|
Untyped subroutine return instruction. This instruction pattern should
|
|
|
|
be defined to support @code{__builtin_return} on machines where special
|
|
|
|
instructions are needed to return a value of any type.
|
|
|
|
|
|
|
|
Operand 0 is a memory location where the result of calling a function
|
|
|
|
with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
|
|
|
|
expression where each element is a @code{set} expression that indicates
|
|
|
|
the restoring of a function return value from the result block.
|
|
|
|
|
|
|
|
@cindex @code{nop} instruction pattern
|
|
|
|
@item @samp{nop}
|
|
|
|
No-op instruction. This instruction pattern name should always be defined
|
|
|
|
to output a no-op in assembler code. @code{(const_int 0)} will do as an
|
|
|
|
RTL pattern.
|
|
|
|
|
|
|
|
@cindex @code{indirect_jump} instruction pattern
|
|
|
|
@item @samp{indirect_jump}
|
|
|
|
An instruction to jump to an address which is operand zero.
|
|
|
|
This pattern name is mandatory on all machines.
|
|
|
|
|
|
|
|
@cindex @code{casesi} instruction pattern
|
|
|
|
@item @samp{casesi}
|
|
|
|
Instruction to jump through a dispatch table, including bounds checking.
|
|
|
|
This instruction takes five operands:
|
|
|
|
|
|
|
|
@enumerate
|
|
|
|
@item
|
|
|
|
The index to dispatch on, which has mode @code{SImode}.
|
|
|
|
|
|
|
|
@item
|
|
|
|
The lower bound for indices in the table, an integer constant.
|
|
|
|
|
|
|
|
@item
|
|
|
|
The total range of indices in the table---the largest index
|
|
|
|
minus the smallest one (both inclusive).
|
|
|
|
|
|
|
|
@item
|
|
|
|
A label that precedes the table itself.
|
|
|
|
|
|
|
|
@item
|
|
|
|
A label to jump to if the index has a value outside the bounds.
|
|
|
|
@end enumerate
|
|
|
|
|
|
|
|
The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
|
|
|
|
@code{jump_insn}. The number of elements in the table is one plus the
|
|
|
|
difference between the upper bound and the lower bound.
|
|
|
|
|
|
|
|
@cindex @code{tablejump} instruction pattern
|
|
|
|
@item @samp{tablejump}
|
|
|
|
Instruction to jump to a variable address. This is a low-level
|
|
|
|
capability which can be used to implement a dispatch table when there
|
|
|
|
is no @samp{casesi} pattern.
|
|
|
|
|
|
|
|
This pattern requires two operands: the address or offset, and a label
|
|
|
|
which should immediately precede the jump table. If the macro
|
1997-12-19 17:34:17 +01:00
|
|
|
@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
|
|
|
|
operand is an offset which counts from the address of the table; otherwise,
|
|
|
|
it is an absolute address to jump to. In either case, the first operand has
|
1997-03-25 20:26:08 +01:00
|
|
|
mode @code{Pmode}.
|
|
|
|
|
|
|
|
The @samp{tablejump} insn is always the last insn before the jump
|
|
|
|
table it uses. Its assembler code normally has no need to use the
|
|
|
|
second operand, but you should incorporate it in the RTL pattern so
|
|
|
|
that the jump optimizer will not delete the table as unreachable code.
|
|
|
|
|
2000-12-21 23:08:17 +01:00
|
|
|
|
|
|
|
@cindex @code{decrement_and_branch_until_zero} instruction pattern
|
|
|
|
@item @samp{decrement_and_branch_until_zero}
|
|
|
|
Conditional branch instruction that decrements a register and
|
2001-10-10 01:11:55 +02:00
|
|
|
jumps if the register is nonzero. Operand 0 is the register to
|
2000-12-21 23:08:17 +01:00
|
|
|
decrement and test; operand 1 is the label to jump to if the
|
2001-10-10 01:11:55 +02:00
|
|
|
register is nonzero. @xref{Looping Patterns}.
|
2000-12-21 23:08:17 +01:00
|
|
|
|
|
|
|
This optional instruction pattern is only used by the combiner,
|
|
|
|
typically for loops reversed by the loop optimizer when strength
|
|
|
|
reduction is enabled.
|
|
|
|
|
|
|
|
@cindex @code{doloop_end} instruction pattern
|
|
|
|
@item @samp{doloop_end}
|
|
|
|
Conditional branch instruction that decrements a register and jumps if
|
2001-10-10 01:11:55 +02:00
|
|
|
the register is nonzero. This instruction takes five operands: Operand
|
2000-12-21 23:08:17 +01:00
|
|
|
0 is the register to decrement and test; operand 1 is the number of loop
|
|
|
|
iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
|
|
|
|
determined until run-time; operand 2 is the actual or estimated maximum
|
|
|
|
number of iterations as a @code{const_int}; operand 3 is the number of
|
|
|
|
enclosed loops as a @code{const_int} (an innermost loop has a value of
|
2001-10-10 01:11:55 +02:00
|
|
|
1); operand 4 is the label to jump to if the register is nonzero.
|
2001-01-02 03:56:01 +01:00
|
|
|
@xref{Looping Patterns}.
|
2000-12-21 23:08:17 +01:00
|
|
|
|
|
|
|
This optional instruction pattern should be defined for machines with
|
|
|
|
low-overhead looping instructions as the loop optimizer will try to
|
|
|
|
modify suitable loops to utilize it. If nested low-overhead looping is
|
|
|
|
not supported, use a @code{define_expand} (@pxref{Expander Definitions})
|
|
|
|
and make the pattern fail if operand 3 is not @code{const1_rtx}.
|
|
|
|
Similarly, if the actual or estimated maximum number of iterations is
|
|
|
|
too large for this instruction, make it fail.
|
|
|
|
|
|
|
|
@cindex @code{doloop_begin} instruction pattern
|
|
|
|
@item @samp{doloop_begin}
|
|
|
|
Companion instruction to @code{doloop_end} required for machines that
|
2001-12-09 21:21:57 +01:00
|
|
|
need to perform some initialization, such as loading special registers
|
|
|
|
used by a low-overhead looping instruction. If initialization insns do
|
2000-12-21 23:08:17 +01:00
|
|
|
not always need to be emitted, use a @code{define_expand}
|
|
|
|
(@pxref{Expander Definitions}) and make it fail.
|
|
|
|
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{canonicalize_funcptr_for_compare} instruction pattern
|
|
|
|
@item @samp{canonicalize_funcptr_for_compare}
|
|
|
|
Canonicalize the function pointer in operand 1 and store the result
|
|
|
|
into operand 0.
|
|
|
|
|
|
|
|
Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
|
|
|
|
may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
|
|
|
|
and also has mode @code{Pmode}.
|
|
|
|
|
|
|
|
Canonicalization of a function pointer usually involves computing
|
|
|
|
the address of the function which would be called if the function
|
|
|
|
pointer were used in an indirect call.
|
|
|
|
|
|
|
|
Only define this pattern if function pointers on the target machine
|
|
|
|
can have different values but still call the same function when
|
|
|
|
used in an indirect call.
|
|
|
|
|
|
|
|
@cindex @code{save_stack_block} instruction pattern
|
|
|
|
@cindex @code{save_stack_function} instruction pattern
|
|
|
|
@cindex @code{save_stack_nonlocal} instruction pattern
|
|
|
|
@cindex @code{restore_stack_block} instruction pattern
|
|
|
|
@cindex @code{restore_stack_function} instruction pattern
|
|
|
|
@cindex @code{restore_stack_nonlocal} instruction pattern
|
|
|
|
@item @samp{save_stack_block}
|
|
|
|
@itemx @samp{save_stack_function}
|
|
|
|
@itemx @samp{save_stack_nonlocal}
|
|
|
|
@itemx @samp{restore_stack_block}
|
|
|
|
@itemx @samp{restore_stack_function}
|
|
|
|
@itemx @samp{restore_stack_nonlocal}
|
|
|
|
Most machines save and restore the stack pointer by copying it to or
|
|
|
|
from an object of mode @code{Pmode}. Do not define these patterns on
|
|
|
|
such machines.
|
|
|
|
|
|
|
|
Some machines require special handling for stack pointer saves and
|
|
|
|
restores. On those machines, define the patterns corresponding to the
|
|
|
|
non-standard cases by using a @code{define_expand} (@pxref{Expander
|
|
|
|
Definitions}) that produces the required insns. The three types of
|
|
|
|
saves and restores are:
|
|
|
|
|
|
|
|
@enumerate
|
|
|
|
@item
|
|
|
|
@samp{save_stack_block} saves the stack pointer at the start of a block
|
|
|
|
that allocates a variable-sized object, and @samp{restore_stack_block}
|
|
|
|
restores the stack pointer when the block is exited.
|
|
|
|
|
|
|
|
@item
|
|
|
|
@samp{save_stack_function} and @samp{restore_stack_function} do a
|
|
|
|
similar job for the outermost block of a function and are used when the
|
|
|
|
function allocates variable-sized objects or calls @code{alloca}. Only
|
|
|
|
the epilogue uses the restored stack pointer, allowing a simpler save or
|
|
|
|
restore sequence on some machines.
|
|
|
|
|
|
|
|
@item
|
|
|
|
@samp{save_stack_nonlocal} is used in functions that contain labels
|
|
|
|
branched to by nested functions. It saves the stack pointer in such a
|
|
|
|
way that the inner function can use @samp{restore_stack_nonlocal} to
|
|
|
|
restore the stack pointer. The compiler generates code to restore the
|
|
|
|
frame and argument pointer registers, but some machines require saving
|
|
|
|
and restoring additional data such as register window information or
|
|
|
|
stack backchains. Place insns in these patterns to save and restore any
|
|
|
|
such required data.
|
|
|
|
@end enumerate
|
|
|
|
|
|
|
|
When saving the stack pointer, operand 0 is the save area and operand 1
|
1998-06-30 16:45:56 +02:00
|
|
|
is the stack pointer. The mode used to allocate the save area defaults
|
|
|
|
to @code{Pmode} but you can override that choice by defining the
|
1998-07-01 12:22:13 +02:00
|
|
|
@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
|
1998-06-30 16:45:56 +02:00
|
|
|
specify an integral mode, or @code{VOIDmode} if no save area is needed
|
|
|
|
for a particular type of save (either because no save is needed or
|
|
|
|
because a machine-specific save area can be used). Operand 0 is the
|
|
|
|
stack pointer and operand 1 is the save area for restore operations. If
|
|
|
|
@samp{save_stack_block} is defined, operand 0 must not be
|
|
|
|
@code{VOIDmode} since these saves can be arbitrarily nested.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
A save area is a @code{mem} that is at a constant offset from
|
|
|
|
@code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
|
|
|
|
nonlocal gotos and a @code{reg} in the other two cases.
|
|
|
|
|
|
|
|
@cindex @code{allocate_stack} instruction pattern
|
|
|
|
@item @samp{allocate_stack}
|
1997-11-20 14:53:42 +01:00
|
|
|
Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
|
1997-03-25 20:26:08 +01:00
|
|
|
the stack pointer to create space for dynamically allocated data.
|
|
|
|
|
1997-11-20 14:53:42 +01:00
|
|
|
Store the resultant pointer to this space into operand 0. If you
|
|
|
|
are allocating space from the main stack, do this by emitting a
|
|
|
|
move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
|
|
|
|
If you are allocating the space elsewhere, generate code to copy the
|
|
|
|
location of the space to operand 0. In the latter case, you must
|
1997-12-07 01:31:01 +01:00
|
|
|
ensure this space gets freed when the corresponding space on the main
|
1997-11-20 14:53:42 +01:00
|
|
|
stack is free.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
Do not define this pattern if all that must be done is the subtraction.
|
|
|
|
Some machines require other operations such as stack probes or
|
|
|
|
maintaining the back chain. Define this pattern to emit those
|
|
|
|
operations in addition to updating the stack pointer.
|
|
|
|
|
1997-08-11 17:56:58 +02:00
|
|
|
@cindex @code{check_stack} instruction pattern
|
|
|
|
@item @samp{check_stack}
|
|
|
|
If stack checking cannot be done on your system by probing the stack with
|
|
|
|
a load or store instruction (@pxref{Stack Checking}), define this pattern
|
|
|
|
to perform the needed check and signaling an error if the stack
|
|
|
|
has overflowed. The single operand is the location in the stack furthest
|
|
|
|
from the current stack pointer that you need to validate. Normally,
|
|
|
|
on machines where this pattern is needed, you would obtain the stack
|
|
|
|
limit from a global or thread-specific variable or register.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{nonlocal_goto} instruction pattern
|
|
|
|
@item @samp{nonlocal_goto}
|
|
|
|
Emit code to generate a non-local goto, e.g., a jump from one function
|
|
|
|
to a label in an outer function. This pattern has four arguments,
|
|
|
|
each representing a value to be used in the jump. The first
|
1998-04-17 09:52:26 +02:00
|
|
|
argument is to be loaded into the frame pointer, the second is
|
1997-03-25 20:26:08 +01:00
|
|
|
the address to branch to (code to dispatch to the actual label),
|
|
|
|
the third is the address of a location where the stack is saved,
|
|
|
|
and the last is the address of the label, to be placed in the
|
|
|
|
location for the incoming static chain.
|
|
|
|
|
c-tree.texi, [...]: Be more consistent about the use of "GCC" and related terms.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/md.texi, doc/rtl.texi, doc/tm.texi: Be more consistent about
the use of "GCC" and related terms.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43547
2001-06-25 02:21:28 +02:00
|
|
|
On most machines you need not define this pattern, since GCC will
|
1997-03-25 20:26:08 +01:00
|
|
|
already generate the correct code, which is to load the frame pointer
|
|
|
|
and static chain, restore the stack (using the
|
|
|
|
@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
|
|
|
|
to the dispatcher. You need only define this pattern if this code will
|
|
|
|
not work on your machine.
|
|
|
|
|
|
|
|
@cindex @code{nonlocal_goto_receiver} instruction pattern
|
|
|
|
@item @samp{nonlocal_goto_receiver}
|
|
|
|
This pattern, if defined, contains code needed at the target of a
|
c-tree.texi, [...]: Replace . at end of sentences preceded by a capital letter with @..
* doc/c-tree.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppinternals.texi, doc/extend.texi, doc/gcc.texi,
doc/gcov.texi, doc/install-old.texi, doc/install.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Replace
. at end of sentences preceded by a capital letter with @..
From-SVN: r43611
2001-06-27 17:04:16 +02:00
|
|
|
nonlocal goto after the code already generated by GCC@. You will not
|
1997-03-25 20:26:08 +01:00
|
|
|
normally need to define this pattern. A typical reason why you might
|
|
|
|
need this pattern is if some value, such as a pointer to a global table,
|
1998-02-16 18:19:13 +01:00
|
|
|
must be restored when the frame pointer is restored. Note that a nonlocal
|
2000-02-14 11:37:13 +01:00
|
|
|
goto only occurs within a unit-of-translation, so a global table pointer
|
1998-02-16 18:19:13 +01:00
|
|
|
that is shared by all functions of a given module need not be restored.
|
|
|
|
There are no arguments.
|
1997-08-11 17:56:58 +02:00
|
|
|
|
|
|
|
@cindex @code{exception_receiver} instruction pattern
|
|
|
|
@item @samp{exception_receiver}
|
|
|
|
This pattern, if defined, contains code needed at the site of an
|
|
|
|
exception handler that isn't needed at the site of a nonlocal goto. You
|
|
|
|
will not normally need to define this pattern. A typical reason why you
|
|
|
|
might need this pattern is if some value, such as a pointer to a global
|
|
|
|
table, must be restored after control flow is branched to the handler of
|
|
|
|
an exception. There are no arguments.
|
1998-01-14 21:57:58 +01:00
|
|
|
|
1998-02-16 18:19:13 +01:00
|
|
|
@cindex @code{builtin_setjmp_setup} instruction pattern
|
|
|
|
@item @samp{builtin_setjmp_setup}
|
|
|
|
This pattern, if defined, contains additional code needed to initialize
|
|
|
|
the @code{jmp_buf}. You will not normally need to define this pattern.
|
|
|
|
A typical reason why you might need this pattern is if some value, such
|
|
|
|
as a pointer to a global table, must be restored. Though it is
|
|
|
|
preferred that the pointer value be recalculated if possible (given the
|
|
|
|
address of a label for instance). The single argument is a pointer to
|
|
|
|
the @code{jmp_buf}. Note that the buffer is five words long and that
|
|
|
|
the first three are normally used by the generic mechanism.
|
|
|
|
|
1998-01-14 21:57:58 +01:00
|
|
|
@cindex @code{builtin_setjmp_receiver} instruction pattern
|
|
|
|
@item @samp{builtin_setjmp_receiver}
|
|
|
|
This pattern, if defined, contains code needed at the site of an
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
built-in setjmp that isn't needed at the site of a nonlocal goto. You
|
1998-01-14 21:57:58 +01:00
|
|
|
will not normally need to define this pattern. A typical reason why you
|
|
|
|
might need this pattern is if some value, such as a pointer to a global
|
1998-02-16 18:19:13 +01:00
|
|
|
table, must be restored. It takes one argument, which is the label
|
|
|
|
to which builtin_longjmp transfered control; this pattern may be emitted
|
|
|
|
at a small offset from that label.
|
|
|
|
|
|
|
|
@cindex @code{builtin_longjmp} instruction pattern
|
|
|
|
@item @samp{builtin_longjmp}
|
|
|
|
This pattern, if defined, performs the entire action of the longjmp.
|
|
|
|
You will not normally need to define this pattern unless you also define
|
|
|
|
@code{builtin_setjmp_setup}. The single argument is a pointer to the
|
|
|
|
@code{jmp_buf}.
|
1998-10-14 04:03:03 +02:00
|
|
|
|
2001-03-28 13:04:51 +02:00
|
|
|
@cindex @code{eh_return} instruction pattern
|
|
|
|
@item @samp{eh_return}
|
1998-10-14 04:03:03 +02:00
|
|
|
This pattern, if defined, affects the way @code{__builtin_eh_return},
|
2001-03-28 13:04:51 +02:00
|
|
|
and thence the call frame exception handling library routines, are
|
|
|
|
built. It is intended to handle non-trivial actions needed along
|
|
|
|
the abnormal return path.
|
|
|
|
|
2003-05-11 00:59:04 +02:00
|
|
|
The address of the exception handler to which the function should return
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cpp.texi, doc/extend.texi,
doc/frontends.texi, doc/gcov.texi, doc/gty.texi, doc/install.texi,
doc/invoke.texi, doc/libgcc.texi, doc/md.texi, doc/rtl.texi,
doc/sourcebuild.texi, doc/standards.texi, doc/tm.texi,
doc/trouble.texi: Remove trailing whitespace.
From-SVN: r76098
2004-01-18 12:57:17 +01:00
|
|
|
is passed as operand to this pattern. It will normally need to copied by
|
2003-05-11 00:59:04 +02:00
|
|
|
the pattern to some special register or memory location.
|
|
|
|
If the pattern needs to determine the location of the target call
|
|
|
|
frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
|
|
|
|
if defined; it will have already been assigned.
|
|
|
|
|
|
|
|
If this pattern is not defined, the default action will be to simply
|
|
|
|
copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
|
|
|
|
that macro or this pattern needs to be defined if call frame exception
|
|
|
|
handling is to be used.
|
1999-02-27 01:16:01 +01:00
|
|
|
|
|
|
|
@cindex @code{prologue} instruction pattern
|
2001-07-09 08:10:09 +02:00
|
|
|
@anchor{prologue instruction pattern}
|
1999-02-27 01:16:01 +01:00
|
|
|
@item @samp{prologue}
|
|
|
|
This pattern, if defined, emits RTL for entry to a function. The function
|
2000-07-06 03:07:01 +02:00
|
|
|
entry is responsible for setting up the stack frame, initializing the frame
|
1999-02-27 01:16:01 +01:00
|
|
|
pointer register, saving callee saved registers, etc.
|
|
|
|
|
|
|
|
Using a prologue pattern is generally preferred over defining
|
2001-07-09 08:10:09 +02:00
|
|
|
@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
|
1999-02-27 01:16:01 +01:00
|
|
|
|
|
|
|
The @code{prologue} pattern is particularly useful for targets which perform
|
|
|
|
instruction scheduling.
|
|
|
|
|
|
|
|
@cindex @code{epilogue} instruction pattern
|
2001-07-09 08:10:09 +02:00
|
|
|
@anchor{epilogue instruction pattern}
|
1999-02-27 01:16:01 +01:00
|
|
|
@item @samp{epilogue}
|
2001-08-10 04:14:26 +02:00
|
|
|
This pattern emits RTL for exit from a function. The function
|
2000-07-06 03:07:01 +02:00
|
|
|
exit is responsible for deallocating the stack frame, restoring callee saved
|
1999-02-27 01:16:01 +01:00
|
|
|
registers and emitting the return instruction.
|
|
|
|
|
|
|
|
Using an epilogue pattern is generally preferred over defining
|
2001-07-09 08:10:09 +02:00
|
|
|
@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
|
1999-02-27 01:16:01 +01:00
|
|
|
|
|
|
|
The @code{epilogue} pattern is particularly useful for targets which perform
|
|
|
|
instruction scheduling or which have delay slots for their return instruction.
|
|
|
|
|
|
|
|
@cindex @code{sibcall_epilogue} instruction pattern
|
|
|
|
@item @samp{sibcall_epilogue}
|
|
|
|
This pattern, if defined, emits RTL for exit from a function without the final
|
|
|
|
branch back to the calling function. This pattern will be emitted before any
|
|
|
|
sibling call (aka tail call) sites.
|
|
|
|
|
|
|
|
The @code{sibcall_epilogue} pattern must not clobber any arguments used for
|
|
|
|
parameter passing or any stack slots for arguments passed to the current
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
function.
|
1999-12-04 04:00:04 +01:00
|
|
|
|
|
|
|
@cindex @code{trap} instruction pattern
|
|
|
|
@item @samp{trap}
|
|
|
|
This pattern, if defined, signals an error, typically by causing some
|
|
|
|
kind of signal to be raised. Among other places, it is used by the Java
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
front end to signal `invalid array index' exceptions.
|
1999-12-04 04:00:04 +01:00
|
|
|
|
|
|
|
@cindex @code{conditional_trap} instruction pattern
|
|
|
|
@item @samp{conditional_trap}
|
|
|
|
Conditional trap instruction. Operand 0 is a piece of RTL which
|
|
|
|
performs a comparison. Operand 1 is the trap code, an integer.
|
|
|
|
|
|
|
|
A typical @code{conditional_trap} pattern looks like
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "conditional_trap"
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
[(trap_if (match_operator 0 "trap_operator"
|
1999-12-04 04:00:04 +01:00
|
|
|
[(cc0) (const_int 0)])
|
|
|
|
(match_operand 1 "const_int_operand" "i"))]
|
|
|
|
""
|
|
|
|
"@dots{}")
|
|
|
|
@end smallexample
|
|
|
|
|
2001-12-07 02:42:35 +01:00
|
|
|
@cindex @code{prefetch} instruction pattern
|
|
|
|
@item @samp{prefetch}
|
|
|
|
|
|
|
|
This pattern, if defined, emits code for a non-faulting data prefetch
|
|
|
|
instruction. Operand 0 is the address of the memory to prefetch. Operand 1
|
|
|
|
is a constant 1 if the prefetch is preparing for a write to the memory
|
|
|
|
address, or a constant 0 otherwise. Operand 2 is the expected degree of
|
|
|
|
temporal locality of the data and is a value between 0 and 3, inclusive; 0
|
|
|
|
means that the data has no temporal locality, so it need not be left in the
|
|
|
|
cache after the access; 3 means that the data has a high degree of temporal
|
|
|
|
locality and should be left in all levels of cache possible; 1 and 2 mean,
|
|
|
|
respectively, a low or moderate degree of temporal locality.
|
|
|
|
|
|
|
|
Targets that do not support write prefetches or locality hints can ignore
|
|
|
|
the values of operands 1 and 2.
|
|
|
|
|
2007-01-28 20:26:43 +01:00
|
|
|
@cindex @code{blockage} instruction pattern
|
|
|
|
@item @samp{blockage}
|
|
|
|
|
|
|
|
This pattern defines a pseudo insn that prevents the instruction
|
|
|
|
scheduler from moving instructions across the boundary defined by the
|
|
|
|
blockage insn. Normally an UNSPEC_VOLATILE pattern.
|
|
|
|
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
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@cindex @code{memory_barrier} instruction pattern
|
|
|
|
@item @samp{memory_barrier}
|
|
|
|
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|
|
|
If the target memory model is not fully synchronous, then this pattern
|
|
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|
should be defined to an instruction that orders both loads and stores
|
|
|
|
before the instruction with respect to loads and stores after the instruction.
|
|
|
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This pattern has no operands.
|
|
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|
|
@cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
|
|
|
|
@item @samp{sync_compare_and_swap@var{mode}}
|
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This pattern, if defined, emits code for an atomic compare-and-swap
|
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operation. Operand 1 is the memory on which the atomic operation is
|
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|
performed. Operand 2 is the ``old'' value to be compared against the
|
|
|
|
current contents of the memory location. Operand 3 is the ``new'' value
|
|
|
|
to store in the memory if the compare succeeds. Operand 0 is the result
|
Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
|
|
|
of the operation; it should contain the contents of the memory
|
|
|
|
before the operation. If the compare succeeds, this should obviously be
|
|
|
|
a copy of operand 2.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
|
|
|
|
|
|
This pattern must show that both operand 0 and operand 1 are modified.
|
|
|
|
|
Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
|
|
|
This pattern must issue any memory barrier instructions such that all
|
|
|
|
memory operations before the atomic operation occur before the atomic
|
|
|
|
operation and all memory operations after the atomic operation occur
|
|
|
|
after the atomic operation.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
|
|
|
|
|
|
@cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
|
|
|
|
@item @samp{sync_compare_and_swap_cc@var{mode}}
|
|
|
|
|
|
|
|
This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
|
|
|
|
it should act as if compare part of the compare-and-swap were issued via
|
|
|
|
@code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
|
|
|
|
@code{NE} branches and @code{setcc} operations.
|
|
|
|
|
|
|
|
Some targets do expose the success or failure of the compare-and-swap
|
|
|
|
operation via the status flags. Ideally we wouldn't need a separate
|
|
|
|
named pattern in order to take advantage of this, but the combine pass
|
|
|
|
does not handle patterns with multiple sets, which is required by
|
|
|
|
definition for @code{sync_compare_and_swap@var{mode}}.
|
|
|
|
|
|
|
|
@cindex @code{sync_add@var{mode}} instruction pattern
|
|
|
|
@cindex @code{sync_sub@var{mode}} instruction pattern
|
|
|
|
@cindex @code{sync_ior@var{mode}} instruction pattern
|
|
|
|
@cindex @code{sync_and@var{mode}} instruction pattern
|
|
|
|
@cindex @code{sync_xor@var{mode}} instruction pattern
|
|
|
|
@cindex @code{sync_nand@var{mode}} instruction pattern
|
|
|
|
@item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
|
|
|
|
@itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
|
|
|
|
@itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
|
|
|
|
|
|
|
|
These patterns emit code for an atomic operation on memory.
|
|
|
|
Operand 0 is the memory on which the atomic operation is performed.
|
|
|
|
Operand 1 is the second operand to the binary operator.
|
|
|
|
|
2005-12-06 16:15:36 +01:00
|
|
|
The ``nand'' operation is @code{~op0 & op1}.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
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Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
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This pattern must issue any memory barrier instructions such that all
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memory operations before the atomic operation occur before the atomic
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operation and all memory operations after the atomic operation occur
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after the atomic operation.
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re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
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If these patterns are not defined, the operation will be constructed
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from a compare-and-swap operation, if defined.
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@cindex @code{sync_old_add@var{mode}} instruction pattern
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@cindex @code{sync_old_sub@var{mode}} instruction pattern
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@cindex @code{sync_old_ior@var{mode}} instruction pattern
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@cindex @code{sync_old_and@var{mode}} instruction pattern
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@cindex @code{sync_old_xor@var{mode}} instruction pattern
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@cindex @code{sync_old_nand@var{mode}} instruction pattern
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@item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
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@itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
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@itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
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These patterns are emit code for an atomic operation on memory,
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and return the value that the memory contained before the operation.
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Operand 0 is the result value, operand 1 is the memory on which the
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atomic operation is performed, and operand 2 is the second operand
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to the binary operator.
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Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
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This pattern must issue any memory barrier instructions such that all
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memory operations before the atomic operation occur before the atomic
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operation and all memory operations after the atomic operation occur
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after the atomic operation.
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re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
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|
If these patterns are not defined, the operation will be constructed
|
|
|
|
from a compare-and-swap operation, if defined.
|
|
|
|
|
|
|
|
@cindex @code{sync_new_add@var{mode}} instruction pattern
|
|
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|
@cindex @code{sync_new_sub@var{mode}} instruction pattern
|
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@cindex @code{sync_new_ior@var{mode}} instruction pattern
|
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|
@cindex @code{sync_new_and@var{mode}} instruction pattern
|
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|
@cindex @code{sync_new_xor@var{mode}} instruction pattern
|
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|
@cindex @code{sync_new_nand@var{mode}} instruction pattern
|
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|
@item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
|
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@itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
|
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@itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
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These patterns are like their @code{sync_old_@var{op}} counterparts,
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except that they return the value that exists in the memory location
|
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after the operation, rather than before the operation.
|
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@cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
|
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|
@item @samp{sync_lock_test_and_set@var{mode}}
|
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|
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This pattern takes two forms, based on the capabilities of the target.
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In either case, operand 0 is the result of the operand, operand 1 is
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the memory on which the atomic operation is performed, and operand 2
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is the value to set in the lock.
|
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|
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In the ideal case, this operation is an atomic exchange operation, in
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which the previous value in memory operand is copied into the result
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operand, and the value operand is stored in the memory operand.
|
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For less capable targets, any value operand that is not the constant 1
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should be rejected with @code{FAIL}. In this case the target may use
|
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an atomic test-and-set bit operation. The result operand should contain
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1 if the bit was previously set and 0 if the bit was previously clear.
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The true contents of the memory operand are implementation defined.
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This pattern must issue any memory barrier instructions such that the
|
Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
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pattern as a whole acts as an acquire barrier, that is all memory
|
|
|
|
operations after the pattern do not occur until the lock is acquired.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
|
|
|
|
|
|
If this pattern is not defined, the operation will be constructed from
|
|
|
|
a compare-and-swap operation, if defined.
|
|
|
|
|
|
|
|
@cindex @code{sync_lock_release@var{mode}} instruction pattern
|
|
|
|
@item @samp{sync_lock_release@var{mode}}
|
|
|
|
|
|
|
|
This pattern, if defined, releases a lock set by
|
|
|
|
@code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
|
rs6000.md (sync_add<mode>_internal, [...]): Use "bne- $-xxx" rather than local labels.
* config/rs6000/rs6000.md (sync_add<mode>_internal,
sync_addshort_internal, sync_sub<mode>_internal, sync_andsi_internal,
sync_anddi_internal, sync_boolsi_internal, sync_booldi_internal,
sync_boolc<mode>_internal, sync_boolc<mode>_internal2,
sync_boolcc<mode>_internal, sync_lock_test_and_set<mode>): Use
"bne- $-xxx" rather than local labels.
(sync_lock_release<mode>): Add second operand.
(lwsync): Use .long rather than a more meaningful opcode.
* doc/md.texi (Standard Names): Add description of second
parameter to sync_lock_test_and_set.
From-SVN: r98602
2005-04-23 06:27:48 +02:00
|
|
|
that contains the lock; operand 1 is the value to store in the lock.
|
|
|
|
|
|
|
|
If the target doesn't implement full semantics for
|
|
|
|
@code{sync_lock_test_and_set@var{mode}}, any value operand which is not
|
|
|
|
the constant 0 should be rejected with @code{FAIL}, and the true contents
|
|
|
|
of the memory operand are implementation defined.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
|
|
|
|
|
|
|
This pattern must issue any memory barrier instructions such that the
|
Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
gen_rtx_* not gen_rtx_fmt_*.
(rs6000_emit_vector_select): Likewise.
(rs6000_emit_sync): New.
* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
(larx, stcx, cmp): New mode substitutions.
(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
UNSPEC_ISYNC): New constants.
(rlwinm): Give name.
(memory_barrier, isync, lwsync): New insns.
(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
(sync_lock_release<mode>): New expander.
(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
(sync_add<mode>_internal, sync_addshort_internal,
sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
is the memory before, not after, the operation. Clarify
barrier requirements.
Index: testsuite/ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com>
* lib/target-supports.exp (check_effective_target_sync_int_long):
Add powerpc*.
From-SVN: r98527
2005-04-21 23:13:41 +02:00
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pattern as a whole acts as a release barrier, that is the lock is
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released only after all previous memory operations have completed.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
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If this pattern is not defined, then a @code{memory_barrier} pattern
|
rs6000.md (sync_add<mode>_internal, [...]): Use "bne- $-xxx" rather than local labels.
* config/rs6000/rs6000.md (sync_add<mode>_internal,
sync_addshort_internal, sync_sub<mode>_internal, sync_andsi_internal,
sync_anddi_internal, sync_boolsi_internal, sync_booldi_internal,
sync_boolc<mode>_internal, sync_boolc<mode>_internal2,
sync_boolcc<mode>_internal, sync_lock_test_and_set<mode>): Use
"bne- $-xxx" rather than local labels.
(sync_lock_release<mode>): Add second operand.
(lwsync): Use .long rather than a more meaningful opcode.
* doc/md.texi (Standard Names): Add description of second
parameter to sync_lock_test_and_set.
From-SVN: r98602
2005-04-23 06:27:48 +02:00
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will be emitted, followed by a store of the value to the memory operand.
|
re PR middle-end/14311 (builtins for atomic operations needed)
PR middle-end/14311
* builtin-types.def (BT_BOOL, BT_VOLATILE_PTR, BT_I1, BT_I2,
BT_I4, BT_I8, BT_FN_VOID_VPTR, BT_FN_I1_VPTR_I1, BT_FN_I2_VPTR_I2,
BT_FN_I4_VPTR_I4, BT_FN_I8_VPTR_I8, BT_FN_BOOL_VPTR_I1_I1,
BT_FN_BOOL_VPTR_I2_I2, BT_FN_BOOL_VPTR_I4_I4, BT_FN_BOOL_VPTR_I8_I8,
BT_FN_I1_VPTR_I1_I1, BT_FN_I2_VPTR_I2_I2, BT_FN_I4_VPTR_I4_I4,
BT_FN_I8_VPTR_I8_I8): New.
* builtins.def (DEF_SYNC_BUILTIN): New.
(BUILT_IN_FETCH_AND_ADD_N, BUILT_IN_FETCH_AND_ADD_1,
BUILT_IN_FETCH_AND_ADD_2, BUILT_IN_FETCH_AND_ADD_4,
BUILT_IN_FETCH_AND_ADD_8, BUILT_IN_FETCH_AND_SUB_N,
BUILT_IN_FETCH_AND_SUB_1, BUILT_IN_FETCH_AND_SUB_2,
BUILT_IN_FETCH_AND_SUB_4, BUILT_IN_FETCH_AND_SUB_8,
BUILT_IN_FETCH_AND_OR_N, BUILT_IN_FETCH_AND_OR_1,
BUILT_IN_FETCH_AND_OR_2, BUILT_IN_FETCH_AND_OR_4,
BUILT_IN_FETCH_AND_OR_8, BUILT_IN_FETCH_AND_AND_N,
BUILT_IN_FETCH_AND_AND_1, BUILT_IN_FETCH_AND_AND_2,
BUILT_IN_FETCH_AND_AND_4, BUILT_IN_FETCH_AND_AND_8,
BUILT_IN_FETCH_AND_XOR_N, BUILT_IN_FETCH_AND_XOR_1,
BUILT_IN_FETCH_AND_XOR_2, BUILT_IN_FETCH_AND_XOR_4,
BUILT_IN_FETCH_AND_XOR_8, BUILT_IN_FETCH_AND_NAND_N,
BUILT_IN_FETCH_AND_NAND_1, BUILT_IN_FETCH_AND_NAND_2,
BUILT_IN_FETCH_AND_NAND_4, BUILT_IN_FETCH_AND_NAND_8,
BUILT_IN_ADD_AND_FETCH_N, BUILT_IN_ADD_AND_FETCH_1,
BUILT_IN_ADD_AND_FETCH_2, BUILT_IN_ADD_AND_FETCH_4,
BUILT_IN_ADD_AND_FETCH_8, BUILT_IN_SUB_AND_FETCH_N,
BUILT_IN_SUB_AND_FETCH_1, BUILT_IN_SUB_AND_FETCH_2,
BUILT_IN_SUB_AND_FETCH_4, BUILT_IN_SUB_AND_FETCH_8,
BUILT_IN_OR_AND_FETCH_N, BUILT_IN_OR_AND_FETCH_1,
BUILT_IN_OR_AND_FETCH_2, BUILT_IN_OR_AND_FETCH_4,
BUILT_IN_OR_AND_FETCH_8, BUILT_IN_AND_AND_FETCH_N,
BUILT_IN_AND_AND_FETCH_1, BUILT_IN_AND_AND_FETCH_2,
BUILT_IN_AND_AND_FETCH_4, BUILT_IN_AND_AND_FETCH_8,
BUILT_IN_XOR_AND_FETCH_N, BUILT_IN_XOR_AND_FETCH_1,
BUILT_IN_XOR_AND_FETCH_2, BUILT_IN_XOR_AND_FETCH_4,
BUILT_IN_XOR_AND_FETCH_8, BUILT_IN_NAND_AND_FETCH_N,
BUILT_IN_NAND_AND_FETCH_1, BUILT_IN_NAND_AND_FETCH_2,
BUILT_IN_NAND_AND_FETCH_4, BUILT_IN_NAND_AND_FETCH_8,
BUILT_IN_BOOL_COMPARE_AND_SWAP_N, BUILT_IN_BOOL_COMPARE_AND_SWAP_1,
BUILT_IN_BOOL_COMPARE_AND_SWAP_2, BUILT_IN_BOOL_COMPARE_AND_SWAP_4,
BUILT_IN_BOOL_COMPARE_AND_SWAP_8, BUILT_IN_VAL_COMPARE_AND_SWAP_N,
BUILT_IN_VAL_COMPARE_AND_SWAP_1, BUILT_IN_VAL_COMPARE_AND_SWAP_2,
BUILT_IN_VAL_COMPARE_AND_SWAP_4, BUILT_IN_VAL_COMPARE_AND_SWAP_8,
BUILT_IN_LOCK_TEST_AND_SET_N, BUILT_IN_LOCK_TEST_AND_SET_1,
BUILT_IN_LOCK_TEST_AND_SET_2, BUILT_IN_LOCK_TEST_AND_SET_4,
BUILT_IN_LOCK_TEST_AND_SET_8, BUILT_IN_LOCK_RELEASE_N,
BUILT_IN_LOCK_RELEASE_1, BUILT_IN_LOCK_RELEASE_2,
BUILT_IN_LOCK_RELEASE_4, BUILT_IN_LOCK_RELEASE_8,
BUILT_IN_SYNCHRONIZE: New.
* builtins.c (called_as_built_in): Rewrite from CALLED_AS_BUILT_IN
as a function. Accept __sync_ as a prefix as well.
(expand_builtin_sync_operation, expand_builtin_compare_and_swap,
expand_builtin_lock_test_and_set, expand_builtin_synchronize,
expand_builtin_lock_release): New.
(expand_builtin): Call them.
* c-common.c (DEF_BUILTIN): Don't require __builtin_ prefix if
neither BOTH_P nor FALLBACK_P are defined.
(builtin_type_for_size): New.
(sync_resolve_size, sync_resolve_params, sync_resolve_return): New.
(resolve_overloaded_builtin): New.
* c-common.h (resolve_overloaded_builtin): Declare.
(builtin_type_for_size): Declare.
* c-typeck.c (build_function_call): Invoke resolve_overloaded_builtin.
* expr.c (sync_add_optab, sync_sub_optab, sync_ior_optab,
sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab,
sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab,
sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab,
sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab,
sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap,
sync_compare_and_swap_cc, sync_lock_test_and_set,
sync_lock_release): New.
* optabs.h: Declare them.
* expr.h (expand_val_compare_and_swap, expand_bool_compare_and_swap,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): Declare.
* genopinit.c (optabs): Add sync optabs.
* optabs.c (init_optabs): Initialize sync optabs.
(expand_val_compare_and_swap_1, expand_val_compare_and_swap,
expand_bool_compare_and_swap, expand_compare_and_swap_loop,
expand_sync_operation, expand_sync_fetch_operation,
expand_sync_lock_test_and_set): New.
* doc/extend.texi (Atomic Builtins): New section
* doc/md.texi (Standard Names): Add sync patterns.
From-SVN: r98154
2005-04-15 01:37:47 +02:00
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c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* cfgexpand.c: Include params.h.
(has_protected_decls, has_short_buffer): New.
(expand_stack_vars): Take a predicate to determine what to expand.
(defer_stack_allocation): True when flag_stack_protect on.
(SPCT_HAS_LARGE_CHAR_ARRAY, SPCT_HAS_SMALL_CHAR_ARRAY): New.
(SPCT_HAS_ARRAY, SPCT_HAS_AGGREGATE): New.
(stack_protect_classify_type, stack_protect_decl_phase): New.
(stack_protect_decl_phase_1, stack_protect_decl_phase_2): New.
(add_stack_protection_conflicts, create_stack_guard): New.
(expand_used_vars): Add stack protection logic.
(tree_expand_cfg): Likewise.
* common.opt (Wstack-protector): New.
(fstack-protector, fstack-protector-all): New.
* function.c: Include predict.h.
(assign_parm_adjust_stack_rtl): Zap stack_parm when stack protect
wants to copy the parameter into the stack frame.
(stack_protect_prologue, stack_protect_epilogue): New.
(expand_function_end): Call stack_protect_epilogue. Do
sjlj_emit_function_exit_after after naked_return_label.
* function.h (struct function): Add stack_protect_guard.
* params.def (PARAM_SSP_BUFFER_SIZE): New.
* toplev.c (process_options): Disable flag_stack_protect and/or
warn_stack_protect based on FRAME_GROWS_DOWNWARD.
* tree.h (stack_protect_prologue): Declare.
* target-def.h (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
(TARGET_INITIALIZER): Add them.
* target.h (struct gcc_target): Add stack_protect_guard and
stack_protect_fail.
* targhooks.c: Include ggc.h, gty header.
(stack_chk_guard_decl, default_stack_protect_guard): New.
(stack_chk_fail_decl, default_external_stack_protect_fail): New.
(default_hidden_stack_protect_fail): New.
* targhooks.h (default_stack_protect_guard): Declare.
(default_external_stack_protect_fail): Declare.
(default_hidden_stack_protect_fail): Declare.
* config/i386/i386.c (TARGET_STACK_PROTECT_FAIL): New.
* config/i386/i386.md (UNSPEC_SP_SET, UNSPEC_SP_TEST): New.
(trap): Use ud2.
(conditional_trap, conditional_trap_1): Remove.
(stack_protect_set, stack_protect_set_si, stack_protect_set_di): New.
(stack_protect_test, stack_protect_test_si, stack_protect_test_di): New.
* doc/md.texi (stack_protect_set, stack_protect_test): New.
* doc/tm.texi (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
* libgcc-std.ver (GCC_4.1.0): New.
* libgcc.h (__stack_chk_guard): Declare.
(__stack_chk_fail, __stack_chk_fail_local): Declare.
* libgcc2.c (L_stack_chk, L_stack_chk_local): New.
* mklibgcc.in (lib2funcs): Add them.
From-SVN: r101348
2005-06-27 09:41:16 +02:00
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@cindex @code{stack_protect_set} instruction pattern
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@item @samp{stack_protect_set}
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This pattern, if defined, moves a @code{Pmode} value from the memory
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in operand 1 to the memory in operand 0 without leaving the value in
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a register afterward. This is to avoid leaking the value some place
|
2005-10-06 02:05:33 +02:00
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that an attacker might use to rewrite the stack guard slot after
|
c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* cfgexpand.c: Include params.h.
(has_protected_decls, has_short_buffer): New.
(expand_stack_vars): Take a predicate to determine what to expand.
(defer_stack_allocation): True when flag_stack_protect on.
(SPCT_HAS_LARGE_CHAR_ARRAY, SPCT_HAS_SMALL_CHAR_ARRAY): New.
(SPCT_HAS_ARRAY, SPCT_HAS_AGGREGATE): New.
(stack_protect_classify_type, stack_protect_decl_phase): New.
(stack_protect_decl_phase_1, stack_protect_decl_phase_2): New.
(add_stack_protection_conflicts, create_stack_guard): New.
(expand_used_vars): Add stack protection logic.
(tree_expand_cfg): Likewise.
* common.opt (Wstack-protector): New.
(fstack-protector, fstack-protector-all): New.
* function.c: Include predict.h.
(assign_parm_adjust_stack_rtl): Zap stack_parm when stack protect
wants to copy the parameter into the stack frame.
(stack_protect_prologue, stack_protect_epilogue): New.
(expand_function_end): Call stack_protect_epilogue. Do
sjlj_emit_function_exit_after after naked_return_label.
* function.h (struct function): Add stack_protect_guard.
* params.def (PARAM_SSP_BUFFER_SIZE): New.
* toplev.c (process_options): Disable flag_stack_protect and/or
warn_stack_protect based on FRAME_GROWS_DOWNWARD.
* tree.h (stack_protect_prologue): Declare.
* target-def.h (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
(TARGET_INITIALIZER): Add them.
* target.h (struct gcc_target): Add stack_protect_guard and
stack_protect_fail.
* targhooks.c: Include ggc.h, gty header.
(stack_chk_guard_decl, default_stack_protect_guard): New.
(stack_chk_fail_decl, default_external_stack_protect_fail): New.
(default_hidden_stack_protect_fail): New.
* targhooks.h (default_stack_protect_guard): Declare.
(default_external_stack_protect_fail): Declare.
(default_hidden_stack_protect_fail): Declare.
* config/i386/i386.c (TARGET_STACK_PROTECT_FAIL): New.
* config/i386/i386.md (UNSPEC_SP_SET, UNSPEC_SP_TEST): New.
(trap): Use ud2.
(conditional_trap, conditional_trap_1): Remove.
(stack_protect_set, stack_protect_set_si, stack_protect_set_di): New.
(stack_protect_test, stack_protect_test_si, stack_protect_test_di): New.
* doc/md.texi (stack_protect_set, stack_protect_test): New.
* doc/tm.texi (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
* libgcc-std.ver (GCC_4.1.0): New.
* libgcc.h (__stack_chk_guard): Declare.
(__stack_chk_fail, __stack_chk_fail_local): Declare.
* libgcc2.c (L_stack_chk, L_stack_chk_local): New.
* mklibgcc.in (lib2funcs): Add them.
From-SVN: r101348
2005-06-27 09:41:16 +02:00
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having clobbered it.
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If this pattern is not defined, then a plain move pattern is generated.
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@cindex @code{stack_protect_test} instruction pattern
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@item @samp{stack_protect_test}
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This pattern, if defined, compares a @code{Pmode} value from the
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memory in operand 1 with the memory in operand 0 without leaving the
|
2005-06-30 16:30:21 +02:00
|
|
|
value in a register afterward and branches to operand 2 if the values
|
|
|
|
weren't equal.
|
c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* cfgexpand.c: Include params.h.
(has_protected_decls, has_short_buffer): New.
(expand_stack_vars): Take a predicate to determine what to expand.
(defer_stack_allocation): True when flag_stack_protect on.
(SPCT_HAS_LARGE_CHAR_ARRAY, SPCT_HAS_SMALL_CHAR_ARRAY): New.
(SPCT_HAS_ARRAY, SPCT_HAS_AGGREGATE): New.
(stack_protect_classify_type, stack_protect_decl_phase): New.
(stack_protect_decl_phase_1, stack_protect_decl_phase_2): New.
(add_stack_protection_conflicts, create_stack_guard): New.
(expand_used_vars): Add stack protection logic.
(tree_expand_cfg): Likewise.
* common.opt (Wstack-protector): New.
(fstack-protector, fstack-protector-all): New.
* function.c: Include predict.h.
(assign_parm_adjust_stack_rtl): Zap stack_parm when stack protect
wants to copy the parameter into the stack frame.
(stack_protect_prologue, stack_protect_epilogue): New.
(expand_function_end): Call stack_protect_epilogue. Do
sjlj_emit_function_exit_after after naked_return_label.
* function.h (struct function): Add stack_protect_guard.
* params.def (PARAM_SSP_BUFFER_SIZE): New.
* toplev.c (process_options): Disable flag_stack_protect and/or
warn_stack_protect based on FRAME_GROWS_DOWNWARD.
* tree.h (stack_protect_prologue): Declare.
* target-def.h (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
(TARGET_INITIALIZER): Add them.
* target.h (struct gcc_target): Add stack_protect_guard and
stack_protect_fail.
* targhooks.c: Include ggc.h, gty header.
(stack_chk_guard_decl, default_stack_protect_guard): New.
(stack_chk_fail_decl, default_external_stack_protect_fail): New.
(default_hidden_stack_protect_fail): New.
* targhooks.h (default_stack_protect_guard): Declare.
(default_external_stack_protect_fail): Declare.
(default_hidden_stack_protect_fail): Declare.
* config/i386/i386.c (TARGET_STACK_PROTECT_FAIL): New.
* config/i386/i386.md (UNSPEC_SP_SET, UNSPEC_SP_TEST): New.
(trap): Use ud2.
(conditional_trap, conditional_trap_1): Remove.
(stack_protect_set, stack_protect_set_si, stack_protect_set_di): New.
(stack_protect_test, stack_protect_test_si, stack_protect_test_di): New.
* doc/md.texi (stack_protect_set, stack_protect_test): New.
* doc/tm.texi (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
* libgcc-std.ver (GCC_4.1.0): New.
* libgcc.h (__stack_chk_guard): Declare.
(__stack_chk_fail, __stack_chk_fail_local): Declare.
* libgcc2.c (L_stack_chk, L_stack_chk_local): New.
* mklibgcc.in (lib2funcs): Add them.
From-SVN: r101348
2005-06-27 09:41:16 +02:00
|
|
|
|
2005-06-30 16:30:21 +02:00
|
|
|
If this pattern is not defined, then a plain compare pattern and
|
|
|
|
conditional branch pattern is used.
|
c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* c-cppbuiltin.c (c_cpp_builtins): Add __SSP_ALL__ and __SSP__.
* cfgexpand.c: Include params.h.
(has_protected_decls, has_short_buffer): New.
(expand_stack_vars): Take a predicate to determine what to expand.
(defer_stack_allocation): True when flag_stack_protect on.
(SPCT_HAS_LARGE_CHAR_ARRAY, SPCT_HAS_SMALL_CHAR_ARRAY): New.
(SPCT_HAS_ARRAY, SPCT_HAS_AGGREGATE): New.
(stack_protect_classify_type, stack_protect_decl_phase): New.
(stack_protect_decl_phase_1, stack_protect_decl_phase_2): New.
(add_stack_protection_conflicts, create_stack_guard): New.
(expand_used_vars): Add stack protection logic.
(tree_expand_cfg): Likewise.
* common.opt (Wstack-protector): New.
(fstack-protector, fstack-protector-all): New.
* function.c: Include predict.h.
(assign_parm_adjust_stack_rtl): Zap stack_parm when stack protect
wants to copy the parameter into the stack frame.
(stack_protect_prologue, stack_protect_epilogue): New.
(expand_function_end): Call stack_protect_epilogue. Do
sjlj_emit_function_exit_after after naked_return_label.
* function.h (struct function): Add stack_protect_guard.
* params.def (PARAM_SSP_BUFFER_SIZE): New.
* toplev.c (process_options): Disable flag_stack_protect and/or
warn_stack_protect based on FRAME_GROWS_DOWNWARD.
* tree.h (stack_protect_prologue): Declare.
* target-def.h (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
(TARGET_INITIALIZER): Add them.
* target.h (struct gcc_target): Add stack_protect_guard and
stack_protect_fail.
* targhooks.c: Include ggc.h, gty header.
(stack_chk_guard_decl, default_stack_protect_guard): New.
(stack_chk_fail_decl, default_external_stack_protect_fail): New.
(default_hidden_stack_protect_fail): New.
* targhooks.h (default_stack_protect_guard): Declare.
(default_external_stack_protect_fail): Declare.
(default_hidden_stack_protect_fail): Declare.
* config/i386/i386.c (TARGET_STACK_PROTECT_FAIL): New.
* config/i386/i386.md (UNSPEC_SP_SET, UNSPEC_SP_TEST): New.
(trap): Use ud2.
(conditional_trap, conditional_trap_1): Remove.
(stack_protect_set, stack_protect_set_si, stack_protect_set_di): New.
(stack_protect_test, stack_protect_test_si, stack_protect_test_di): New.
* doc/md.texi (stack_protect_set, stack_protect_test): New.
* doc/tm.texi (TARGET_STACK_PROTECT_GUARD): New.
(TARGET_STACK_PROTECT_FAIL): New.
* libgcc-std.ver (GCC_4.1.0): New.
* libgcc.h (__stack_chk_guard): Declare.
(__stack_chk_fail, __stack_chk_fail_local): Declare.
* libgcc2.c (L_stack_chk, L_stack_chk_local): New.
* mklibgcc.in (lib2funcs): Add them.
From-SVN: r101348
2005-06-27 09:41:16 +02:00
|
|
|
|
2007-07-11 06:13:10 +02:00
|
|
|
@cindex @code{clear_cache} instruction pattern
|
|
|
|
@item @samp{clear_cache}
|
|
|
|
|
|
|
|
This pattern, if defined, flushes the instruction cache for a region of
|
|
|
|
memory. The region is bounded to by the Pmode pointers in operand 0
|
|
|
|
inclusive and operand 1 exclusive.
|
|
|
|
|
|
|
|
If this pattern is not defined, a call to the library function
|
|
|
|
@code{__clear_cache} is used.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@c Each of the following nodes are wrapped in separate
|
|
|
|
@c "@ifset INTERNALS" to work around memory limits for the default
|
|
|
|
@c configuration in older tetex distributions. Known to not work:
|
|
|
|
@c tetex-1.0.7, known to work: tetex-2.0.2.
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Pattern Ordering
|
|
|
|
@section When the Order of Patterns Matters
|
|
|
|
@cindex Pattern Ordering
|
|
|
|
@cindex Ordering of Patterns
|
|
|
|
|
|
|
|
Sometimes an insn can match more than one instruction pattern. Then the
|
|
|
|
pattern that appears first in the machine description is the one used.
|
|
|
|
Therefore, more specific patterns (patterns that will match fewer things)
|
|
|
|
and faster instructions (those that will produce better code when they
|
|
|
|
do match) should usually go first in the description.
|
|
|
|
|
|
|
|
In some cases the effect of ordering the patterns can be used to hide
|
|
|
|
a pattern when it is not valid. For example, the 68000 has an
|
|
|
|
instruction for converting a fullword to floating point and another
|
|
|
|
for converting a byte to floating point. An instruction converting
|
|
|
|
an integer to floating point could match either one. We put the
|
|
|
|
pattern to convert the fullword first to make sure that one will
|
|
|
|
be used rather than the other. (Otherwise a large integer might
|
|
|
|
be generated as a single-byte immediate quantity, which would not work.)
|
|
|
|
Instead of using this pattern ordering it would be possible to make the
|
|
|
|
pattern for convert-a-byte smart enough to deal properly with any
|
|
|
|
constant value.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Dependent Patterns
|
|
|
|
@section Interdependence of Patterns
|
|
|
|
@cindex Dependent Patterns
|
|
|
|
@cindex Interdependence of Patterns
|
|
|
|
|
|
|
|
Every machine description must have a named pattern for each of the
|
|
|
|
conditional branch names @samp{b@var{cond}}. The recognition template
|
|
|
|
must always have the form
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(set (pc)
|
|
|
|
(if_then_else (@var{cond} (cc0) (const_int 0))
|
|
|
|
(label_ref (match_operand 0 "" ""))
|
|
|
|
(pc)))
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
In addition, every machine description must have an anonymous pattern
|
|
|
|
for each of the possible reverse-conditional branches. Their templates
|
|
|
|
look like
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(set (pc)
|
|
|
|
(if_then_else (@var{cond} (cc0) (const_int 0))
|
|
|
|
(pc)
|
|
|
|
(label_ref (match_operand 0 "" ""))))
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
They are necessary because jump optimization can turn direct-conditional
|
|
|
|
branches into reverse-conditional branches.
|
|
|
|
|
|
|
|
It is often convenient to use the @code{match_operator} construct to
|
|
|
|
reduce the number of patterns that must be specified for branches. For
|
|
|
|
example,
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(define_insn ""
|
|
|
|
[(set (pc)
|
|
|
|
(if_then_else (match_operator 0 "comparison_operator"
|
|
|
|
[(cc0) (const_int 0)])
|
|
|
|
(pc)
|
|
|
|
(label_ref (match_operand 1 "" ""))))]
|
|
|
|
"@var{condition}"
|
|
|
|
"@dots{}")
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
In some cases machines support instructions identical except for the
|
|
|
|
machine mode of one or more operands. For example, there may be
|
|
|
|
``sign-extend halfword'' and ``sign-extend byte'' instructions whose
|
|
|
|
patterns are
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(set (match_operand:SI 0 @dots{})
|
|
|
|
(extend:SI (match_operand:HI 1 @dots{})))
|
|
|
|
|
|
|
|
(set (match_operand:SI 0 @dots{})
|
|
|
|
(extend:SI (match_operand:QI 1 @dots{})))
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
Constant integers do not specify a machine mode, so an instruction to
|
|
|
|
extend a constant value could match either pattern. The pattern it
|
|
|
|
actually will match is the one that appears first in the file. For correct
|
|
|
|
results, this must be the one for the widest possible mode (@code{HImode},
|
|
|
|
here). If the pattern matches the @code{QImode} instruction, the results
|
|
|
|
will be incorrect if the constant value does not actually fit that mode.
|
|
|
|
|
|
|
|
Such instructions to extend constants are rarely generated because they are
|
|
|
|
optimized away, but they do occasionally happen in nonoptimized
|
|
|
|
compilations.
|
|
|
|
|
|
|
|
If a constraint in a pattern allows a constant, the reload pass may
|
|
|
|
replace a register with a constant permitted by the constraint in some
|
|
|
|
cases. Similarly for memory references. Because of this substitution,
|
|
|
|
you should not provide separate patterns for increment and decrement
|
|
|
|
instructions. Instead, they should be generated from the same pattern
|
|
|
|
that supports register-register add insns by examining the operands and
|
|
|
|
generating the appropriate machine instruction.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Jump Patterns
|
|
|
|
@section Defining Jump Instruction Patterns
|
|
|
|
@cindex jump instruction patterns
|
|
|
|
@cindex defining jump instruction patterns
|
|
|
|
|
c-tree.texi, [...]: Be more consistent about the use of "GCC" and related terms.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/md.texi, doc/rtl.texi, doc/tm.texi: Be more consistent about
the use of "GCC" and related terms.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43547
2001-06-25 02:21:28 +02:00
|
|
|
For most machines, GCC assumes that the machine has a condition code.
|
1997-03-25 20:26:08 +01:00
|
|
|
A comparison insn sets the condition code, recording the results of both
|
|
|
|
signed and unsigned comparison of the given operands. A separate branch
|
|
|
|
insn tests the condition code and branches or not according its value.
|
|
|
|
The branch insns come in distinct signed and unsigned flavors. Many
|
combine.c, [...]: consistently use "VAX", "VAXen", and "MicroVAX" in comments and documentation.
* combine.c, config.gcc, cse.c, defaults.h, real.c, reload.c,
simplify-rtx.c, config/alpha/alpha.h, config/avr/avr.h,
config/convex/convex.h, config/d30v/d30v.c,
config/d30v/d30v.h, config/dsp16xx/dsp16xx.h,
config/elxsi/elxsi.h, config/fr30/fr30.h, config/m88k/m88k.c,
config/mips/mips.h, config/mn10200/mn10200.h,
config/mn10300/mn10300.h, config/pdp11/pdp11.md,
config/v850/v850.h, config/vax/openbsd.h,
config/vax/openbsd1.h, config/vax/ultrix.h,
config/vax/vax-protos.h, config/vax/vax.c, config/vax/vax.h,
config/vax/vax.md, config/vax/vaxv.h, config/vax/xm-vms.h,
cp/decl2.c, doc/contrib.texi, doc/cpp.texi, doc/gcc.texi,
doc/install.texi, doc/invoke.texi, doc/md.texi, doc/rtl.texi,
doc/tm.texi: consistently use "VAX", "VAXen", and "MicroVAX"
in comments and documentation.
From-SVN: r44589
2001-08-03 03:19:20 +02:00
|
|
|
common machines, such as the VAX, the 68000 and the 32000, work this
|
1997-03-25 20:26:08 +01:00
|
|
|
way.
|
|
|
|
|
|
|
|
Some machines have distinct signed and unsigned compare instructions, and
|
|
|
|
only one set of conditional branch instructions. The easiest way to handle
|
|
|
|
these machines is to treat them just like the others until the final stage
|
|
|
|
where assembly code is written. At this time, when outputting code for the
|
|
|
|
compare instruction, peek ahead at the following branch using
|
|
|
|
@code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
|
|
|
|
being output, in the output-writing code in an instruction pattern.) If
|
|
|
|
the RTL says that is an unsigned branch, output an unsigned compare;
|
|
|
|
otherwise output a signed compare. When the branch itself is output, you
|
|
|
|
can treat signed and unsigned branches identically.
|
|
|
|
|
c-tree.texi, [...]: Be more consistent about the use of "GCC" and related terms.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/md.texi, doc/rtl.texi, doc/tm.texi: Be more consistent about
the use of "GCC" and related terms.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43547
2001-06-25 02:21:28 +02:00
|
|
|
The reason you can do this is that GCC always generates a pair of
|
1997-03-25 20:26:08 +01:00
|
|
|
consecutive RTL insns, possibly separated by @code{note} insns, one to
|
|
|
|
set the condition code and one to test it, and keeps the pair inviolate
|
|
|
|
until the end.
|
|
|
|
|
|
|
|
To go with this technique, you must define the machine-description macro
|
|
|
|
@code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
|
|
|
|
compare instruction is superfluous.
|
|
|
|
|
|
|
|
Some machines have compare-and-branch instructions and no condition code.
|
|
|
|
A similar technique works for them. When it is time to ``output'' a
|
|
|
|
compare instruction, record its operands in two static variables. When
|
|
|
|
outputting the branch-on-condition-code instruction that follows, actually
|
|
|
|
output a compare-and-branch instruction that uses the remembered operands.
|
|
|
|
|
|
|
|
It also works to define patterns for compare-and-branch instructions.
|
|
|
|
In optimizing compilation, the pair of compare and branch instructions
|
|
|
|
will be combined according to these patterns. But this does not happen
|
|
|
|
if optimization is not requested. So you must use one of the solutions
|
|
|
|
above in addition to any special patterns you define.
|
|
|
|
|
|
|
|
In many RISC machines, most instructions do not affect the condition
|
|
|
|
code and there may not even be a separate condition code register. On
|
|
|
|
these machines, the restriction that the definition and use of the
|
|
|
|
condition code be adjacent insns is not necessary and can prevent
|
|
|
|
important optimizations. For example, on the IBM RS/6000, there is a
|
|
|
|
delay for taken branches unless the condition code register is set three
|
|
|
|
instructions earlier than the conditional branch. The instruction
|
|
|
|
scheduler cannot perform this optimization if it is not permitted to
|
|
|
|
separate the definition and use of the condition code register.
|
|
|
|
|
|
|
|
On these machines, do not use @code{(cc0)}, but instead use a register
|
|
|
|
to represent the condition code. If there is a specific condition code
|
|
|
|
register in the machine, use a hard register. If the condition code or
|
|
|
|
comparison result can be placed in any general register, or if there are
|
|
|
|
multiple condition registers, use a pseudo register.
|
|
|
|
|
|
|
|
@findex prev_cc0_setter
|
|
|
|
@findex next_cc0_user
|
|
|
|
On some machines, the type of branch instruction generated may depend on
|
|
|
|
the way the condition code was produced; for example, on the 68k and
|
2002-09-16 00:48:06 +02:00
|
|
|
SPARC, setting the condition code directly from an add or subtract
|
1997-03-25 20:26:08 +01:00
|
|
|
instruction does not clear the overflow bit the way that a test
|
|
|
|
instruction does, so a different branch instruction must be used for
|
|
|
|
some conditional branches. For machines that use @code{(cc0)}, the set
|
|
|
|
and use of the condition code must be adjacent (separated only by
|
|
|
|
@code{note} insns) allowing flags in @code{cc_status} to be used.
|
|
|
|
(@xref{Condition Code}.) Also, the comparison and branch insns can be
|
|
|
|
located from each other by using the functions @code{prev_cc0_setter}
|
|
|
|
and @code{next_cc0_user}.
|
|
|
|
|
|
|
|
However, this is not true on machines that do not use @code{(cc0)}. On
|
|
|
|
those machines, no assumptions can be made about the adjacency of the
|
|
|
|
compare and branch insns and the above methods cannot be used. Instead,
|
|
|
|
we use the machine mode of the condition code register to record
|
|
|
|
different formats of the condition code register.
|
|
|
|
|
|
|
|
Registers used to store the condition code value should have a mode that
|
|
|
|
is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
|
|
|
|
additional modes are required (as for the add example mentioned above in
|
2005-06-08 02:28:41 +02:00
|
|
|
the SPARC), define them in @file{@var{machine}-modes.def}
|
2005-10-06 02:05:33 +02:00
|
|
|
(@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
|
2005-06-08 02:28:41 +02:00
|
|
|
a mode given an operand of a compare.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
If it is known during RTL generation that a different mode will be
|
|
|
|
required (for example, if the machine has separate compare instructions
|
|
|
|
for signed and unsigned quantities, like most IBM processors), they can
|
|
|
|
be specified at that time.
|
|
|
|
|
|
|
|
If the cases that require different modes would be made by instruction
|
|
|
|
combination, the macro @code{SELECT_CC_MODE} determines which machine
|
|
|
|
mode should be used for the comparison result. The patterns should be
|
2002-09-16 00:48:06 +02:00
|
|
|
written using that mode. To support the case of the add on the SPARC
|
1997-03-25 20:26:08 +01:00
|
|
|
discussed above, we have the pattern
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(set (reg:CC_NOOV 0)
|
|
|
|
(compare:CC_NOOV
|
|
|
|
(plus:SI (match_operand:SI 0 "register_operand" "%r")
|
|
|
|
(match_operand:SI 1 "arith_operand" "rI"))
|
|
|
|
(const_int 0)))]
|
|
|
|
""
|
|
|
|
"@dots{}")
|
|
|
|
@end smallexample
|
|
|
|
|
2002-09-16 00:48:06 +02:00
|
|
|
The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
|
1997-03-25 20:26:08 +01:00
|
|
|
for comparisons whose argument is a @code{plus}.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
2000-12-21 23:08:17 +01:00
|
|
|
@node Looping Patterns
|
|
|
|
@section Defining Looping Instruction Patterns
|
|
|
|
@cindex looping instruction patterns
|
|
|
|
@cindex defining looping instruction patterns
|
|
|
|
|
2002-09-15 20:24:08 +02:00
|
|
|
Some machines have special jump instructions that can be utilized to
|
2000-12-21 23:08:17 +01:00
|
|
|
make loops more efficient. A common example is the 68000 @samp{dbra}
|
|
|
|
instruction which performs a decrement of a register and a branch if the
|
|
|
|
result was greater than zero. Other machines, in particular digital
|
|
|
|
signal processors (DSPs), have special block repeat instructions to
|
|
|
|
provide low-overhead loop support. For example, the TI TMS320C3x/C4x
|
|
|
|
DSPs have a block repeat instruction that loads special registers to
|
|
|
|
mark the top and end of a loop and to count the number of loop
|
|
|
|
iterations. This avoids the need for fetching and executing a
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
@samp{dbra}-like instruction and avoids pipeline stalls associated with
|
2000-12-21 23:08:17 +01:00
|
|
|
the jump.
|
|
|
|
|
2001-08-18 23:02:44 +02:00
|
|
|
GCC has three special named patterns to support low overhead looping.
|
|
|
|
They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
|
|
|
|
and @samp{doloop_end}. The first pattern,
|
2000-12-21 23:08:17 +01:00
|
|
|
@samp{decrement_and_branch_until_zero}, is not emitted during RTL
|
|
|
|
generation but may be emitted during the instruction combination phase.
|
|
|
|
This requires the assistance of the loop optimizer, using information
|
|
|
|
collected during strength reduction, to reverse a loop to count down to
|
|
|
|
zero. Some targets also require the loop optimizer to add a
|
|
|
|
@code{REG_NONNEG} note to indicate that the iteration count is always
|
|
|
|
positive. This is needed if the target performs a signed loop
|
|
|
|
termination test. For example, the 68000 uses a pattern similar to the
|
|
|
|
following for its @code{dbra} instruction:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_insn "decrement_and_branch_until_zero"
|
|
|
|
[(set (pc)
|
|
|
|
(if_then_else
|
|
|
|
(ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
|
|
|
|
(const_int -1))
|
|
|
|
(const_int 0))
|
|
|
|
(label_ref (match_operand 1 "" ""))
|
|
|
|
(pc)))
|
|
|
|
(set (match_dup 0)
|
|
|
|
(plus:SI (match_dup 0)
|
|
|
|
(const_int -1)))]
|
|
|
|
"find_reg_note (insn, REG_NONNEG, 0)"
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@dots{}")
|
2000-12-21 23:08:17 +01:00
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Note that since the insn is both a jump insn and has an output, it must
|
|
|
|
deal with its own reloads, hence the `m' constraints. Also note that
|
|
|
|
since this insn is generated by the instruction combination phase
|
|
|
|
combining two sequential insns together into an implicit parallel insn,
|
|
|
|
the iteration counter needs to be biased by the same amount as the
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
decrement operation, in this case @minus{}1. Note that the following similar
|
2000-12-21 23:08:17 +01:00
|
|
|
pattern will not be matched by the combiner.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_insn "decrement_and_branch_until_zero"
|
|
|
|
[(set (pc)
|
|
|
|
(if_then_else
|
|
|
|
(ge (match_operand:SI 0 "general_operand" "+d*am")
|
|
|
|
(const_int 1))
|
|
|
|
(label_ref (match_operand 1 "" ""))
|
|
|
|
(pc)))
|
|
|
|
(set (match_dup 0)
|
|
|
|
(plus:SI (match_dup 0)
|
|
|
|
(const_int -1)))]
|
|
|
|
"find_reg_note (insn, REG_NONNEG, 0)"
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@dots{}")
|
2000-12-21 23:08:17 +01:00
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The other two special looping patterns, @samp{doloop_begin} and
|
2001-12-09 21:21:57 +01:00
|
|
|
@samp{doloop_end}, are emitted by the loop optimizer for certain
|
2000-12-21 23:08:17 +01:00
|
|
|
well-behaved loops with a finite number of loop iterations using
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
information collected during strength reduction.
|
2000-12-21 23:08:17 +01:00
|
|
|
|
|
|
|
The @samp{doloop_end} pattern describes the actual looping instruction
|
|
|
|
(or the implicit looping operation) and the @samp{doloop_begin} pattern
|
2001-12-09 21:21:57 +01:00
|
|
|
is an optional companion pattern that can be used for initialization
|
2000-12-21 23:08:17 +01:00
|
|
|
needed for some low-overhead looping instructions.
|
|
|
|
|
|
|
|
Note that some machines require the actual looping instruction to be
|
|
|
|
emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
|
|
|
|
the true RTL for a looping instruction at the top of the loop can cause
|
|
|
|
problems with flow analysis. So instead, a dummy @code{doloop} insn is
|
|
|
|
emitted at the end of the loop. The machine dependent reorg pass checks
|
|
|
|
for the presence of this @code{doloop} insn and then searches back to
|
|
|
|
the top of the loop, where it inserts the true looping insn (provided
|
|
|
|
there are no instructions in the loop which would cause problems). Any
|
|
|
|
additional labels can be emitted at this point. In addition, if the
|
|
|
|
desired special iteration counter register was not allocated, this
|
|
|
|
machine dependent reorg pass could emit a traditional compare and jump
|
|
|
|
instruction pair.
|
|
|
|
|
|
|
|
The essential difference between the
|
|
|
|
@samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
|
|
|
|
patterns is that the loop optimizer allocates an additional pseudo
|
|
|
|
register for the latter as an iteration counter. This pseudo register
|
|
|
|
cannot be used within the loop (i.e., general induction variables cannot
|
|
|
|
be derived from it), however, in many cases the loop induction variable
|
|
|
|
may become redundant and removed by the flow pass.
|
|
|
|
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Insn Canonicalizations
|
|
|
|
@section Canonicalization of Instructions
|
|
|
|
@cindex canonicalization of instructions
|
|
|
|
@cindex insn canonicalization
|
|
|
|
|
|
|
|
There are often cases where multiple RTL expressions could represent an
|
|
|
|
operation performed by a single machine instruction. This situation is
|
|
|
|
most commonly encountered with logical, branch, and multiply-accumulate
|
|
|
|
instructions. In such cases, the compiler attempts to convert these
|
|
|
|
multiple RTL expressions into a single canonical form to reduce the
|
|
|
|
number of insn patterns required.
|
|
|
|
|
|
|
|
In addition to algebraic simplifications, following canonicalizations
|
|
|
|
are performed:
|
|
|
|
|
|
|
|
@itemize @bullet
|
|
|
|
@item
|
|
|
|
For commutative and comparison operators, a constant is always made the
|
|
|
|
second operand. If a machine only supports a constant as the second
|
|
|
|
operand, only patterns that match a constant in the second operand need
|
|
|
|
be supplied.
|
|
|
|
|
2004-02-17 06:15:05 +01:00
|
|
|
@item
|
|
|
|
For associative operators, a sequence of operators will always chain
|
|
|
|
to the left; for instance, only the left operand of an integer @code{plus}
|
|
|
|
can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
|
|
|
|
@code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
|
|
|
|
@code{umax} are associative when applied to integers, and sometimes to
|
|
|
|
floating-point.
|
|
|
|
|
|
|
|
@item
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{neg}, canonicalization of
|
|
|
|
@cindex @code{not}, canonicalization of
|
|
|
|
@cindex @code{mult}, canonicalization of
|
|
|
|
@cindex @code{plus}, canonicalization of
|
|
|
|
@cindex @code{minus}, canonicalization of
|
|
|
|
For these operators, if only one operand is a @code{neg}, @code{not},
|
|
|
|
@code{mult}, @code{plus}, or @code{minus} expression, it will be the
|
|
|
|
first operand.
|
|
|
|
|
2002-12-05 02:05:13 +01:00
|
|
|
@item
|
|
|
|
In combinations of @code{neg}, @code{mult}, @code{plus}, and
|
|
|
|
@code{minus}, the @code{neg} operations (if any) will be moved inside
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cpp.texi, doc/extend.texi,
doc/frontends.texi, doc/gcov.texi, doc/gty.texi, doc/install.texi,
doc/invoke.texi, doc/libgcc.texi, doc/md.texi, doc/rtl.texi,
doc/sourcebuild.texi, doc/standards.texi, doc/tm.texi,
doc/trouble.texi: Remove trailing whitespace.
From-SVN: r76098
2004-01-18 12:57:17 +01:00
|
|
|
the operations as far as possible. For instance,
|
2002-12-05 02:05:13 +01:00
|
|
|
@code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
|
|
|
|
@code{(plus (mult (neg A) B) C)} is canonicalized as
|
|
|
|
@code{(minus A (mult B C))}.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@cindex @code{compare}, canonicalization of
|
|
|
|
@item
|
|
|
|
For the @code{compare} operator, a constant is always the second operand
|
|
|
|
on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
|
|
|
|
machines, there are rare cases where the compiler might want to construct
|
|
|
|
a @code{compare} with a constant as the first operand. However, these
|
|
|
|
cases are not common enough for it to be worthwhile to provide a pattern
|
|
|
|
matching a constant as the first operand unless the machine actually has
|
|
|
|
such an instruction.
|
|
|
|
|
|
|
|
An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
|
|
|
|
@code{minus} is made the first operand under the same conditions as
|
|
|
|
above.
|
|
|
|
|
2007-09-09 21:21:59 +02:00
|
|
|
@item
|
|
|
|
@code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
|
|
|
|
@code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
|
|
|
|
of @code{ltu}.
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
@item
|
|
|
|
@code{(minus @var{x} (const_int @var{n}))} is converted to
|
|
|
|
@code{(plus @var{x} (const_int @var{-n}))}.
|
|
|
|
|
|
|
|
@item
|
|
|
|
Within address computations (i.e., inside @code{mem}), a left shift is
|
|
|
|
converted into the appropriate multiplication by a power of two.
|
|
|
|
|
|
|
|
@cindex @code{ior}, canonicalization of
|
|
|
|
@cindex @code{and}, canonicalization of
|
|
|
|
@cindex De Morgan's law
|
1997-11-20 14:53:42 +01:00
|
|
|
@item
|
2004-10-13 22:53:43 +02:00
|
|
|
De Morgan's Law is used to move bitwise negation inside a bitwise
|
1997-03-25 20:26:08 +01:00
|
|
|
logical-and or logical-or operation. If this results in only one
|
|
|
|
operand being a @code{not} expression, it will be the first one.
|
|
|
|
|
|
|
|
A machine that has an instruction that performs a bitwise logical-and of one
|
|
|
|
operand with the bitwise negation of the other should specify the pattern
|
|
|
|
for that instruction as
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:@var{m} 0 @dots{})
|
|
|
|
(and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
|
|
|
|
(match_operand:@var{m} 2 @dots{})))]
|
|
|
|
"@dots{}"
|
|
|
|
"@dots{}")
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@noindent
|
|
|
|
Similarly, a pattern for a ``NAND'' instruction should be written
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:@var{m} 0 @dots{})
|
|
|
|
(ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
|
|
|
|
(not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
|
|
|
|
"@dots{}"
|
|
|
|
"@dots{}")
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
In both cases, it is not necessary to include patterns for the many
|
|
|
|
logically equivalent RTL expressions.
|
|
|
|
|
|
|
|
@cindex @code{xor}, canonicalization of
|
|
|
|
@item
|
|
|
|
The only possible RTL expressions involving both bitwise exclusive-or
|
|
|
|
and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
|
2001-06-25 01:04:49 +02:00
|
|
|
and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item
|
|
|
|
The sum of three items, one of which is a constant, will only appear in
|
|
|
|
the form
|
|
|
|
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
(plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
|
c-tree.texi, [...]: Use @smallexample instead of @example.
* doc/c-tree.texi, doc/compat.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/install.texi,
doc/interface.texi, doc/invoke.texi, doc/libgcc.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi, doc/trouble.texi: Use
@smallexample instead of @example.
From-SVN: r76075
2004-01-18 02:20:48 +01:00
|
|
|
@end smallexample
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item
|
|
|
|
On machines that do not use @code{cc0},
|
|
|
|
@code{(compare @var{x} (const_int 0))} will be converted to
|
2001-06-25 01:04:49 +02:00
|
|
|
@var{x}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{zero_extract}, canonicalization of
|
|
|
|
@cindex @code{sign_extract}, canonicalization of
|
|
|
|
@item
|
|
|
|
Equality comparisons of a group of bits (usually a single bit) with zero
|
|
|
|
will be written using @code{zero_extract} rather than the equivalent
|
|
|
|
@code{and} or @code{sign_extract} operations.
|
|
|
|
|
|
|
|
@end itemize
|
|
|
|
|
2005-11-26 13:04:45 +01:00
|
|
|
Further canonicalization rules are defined in the function
|
|
|
|
@code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Expander Definitions
|
|
|
|
@section Defining RTL Sequences for Code Generation
|
|
|
|
@cindex expander definitions
|
|
|
|
@cindex code generation RTL sequences
|
|
|
|
@cindex defining RTL sequences for code generation
|
|
|
|
|
|
|
|
On some target machines, some standard pattern names for RTL generation
|
|
|
|
cannot be handled with single insn, but a sequence of RTL insns can
|
|
|
|
represent them. For these target machines, you can write a
|
c-tree.texi, [...]: Replace . at end of sentences preceded by a capital letter with @..
* doc/c-tree.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppinternals.texi, doc/extend.texi, doc/gcc.texi,
doc/gcov.texi, doc/install-old.texi, doc/install.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Replace
. at end of sentences preceded by a capital letter with @..
From-SVN: r43611
2001-06-27 17:04:16 +02:00
|
|
|
@code{define_expand} to specify how to generate the sequence of RTL@.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@findex define_expand
|
|
|
|
A @code{define_expand} is an RTL expression that looks almost like a
|
|
|
|
@code{define_insn}; but, unlike the latter, a @code{define_expand} is used
|
|
|
|
only for RTL generation and it can produce more than one RTL insn.
|
|
|
|
|
|
|
|
A @code{define_expand} RTX has four operands:
|
|
|
|
|
|
|
|
@itemize @bullet
|
|
|
|
@item
|
|
|
|
The name. Each @code{define_expand} must have a name, since the only
|
|
|
|
use for it is to refer to it by name.
|
|
|
|
|
|
|
|
@item
|
1999-10-02 20:07:49 +02:00
|
|
|
The RTL template. This is a vector of RTL expressions representing
|
|
|
|
a sequence of separate instructions. Unlike @code{define_insn}, there
|
|
|
|
is no implicit surrounding @code{PARALLEL}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item
|
|
|
|
The condition, a string containing a C expression. This expression is
|
|
|
|
used to express how the availability of this pattern depends on
|
c-tree.texi, [...]: Be more consistent about the use of "GCC" and related terms.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/md.texi, doc/rtl.texi, doc/tm.texi: Be more consistent about
the use of "GCC" and related terms.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43547
2001-06-25 02:21:28 +02:00
|
|
|
subclasses of target machine, selected by command-line options when GCC
|
|
|
|
is run. This is just like the condition of a @code{define_insn} that
|
1997-03-25 20:26:08 +01:00
|
|
|
has a standard name. Therefore, the condition (if present) may not
|
|
|
|
depend on the data in the insn being matched, but only the
|
|
|
|
target-machine-type flags. The compiler needs to test these conditions
|
|
|
|
during initialization in order to learn exactly which named instructions
|
|
|
|
are available in a particular run.
|
|
|
|
|
|
|
|
@item
|
|
|
|
The preparation statements, a string containing zero or more C
|
|
|
|
statements which are to be executed before RTL code is generated from
|
|
|
|
the RTL template.
|
|
|
|
|
|
|
|
Usually these statements prepare temporary registers for use as
|
|
|
|
internal operands in the RTL template, but they can also generate RTL
|
|
|
|
insns directly by calling routines such as @code{emit_insn}, etc.
|
|
|
|
Any such insns precede the ones that come from the RTL template.
|
|
|
|
@end itemize
|
|
|
|
|
|
|
|
Every RTL insn emitted by a @code{define_expand} must match some
|
|
|
|
@code{define_insn} in the machine description. Otherwise, the compiler
|
|
|
|
will crash when trying to generate code for the insn or trying to optimize
|
|
|
|
it.
|
|
|
|
|
|
|
|
The RTL template, in addition to controlling generation of RTL insns,
|
|
|
|
also describes the operands that need to be specified when this pattern
|
|
|
|
is used. In particular, it gives a predicate for each operand.
|
|
|
|
|
|
|
|
A true operand, which needs to be specified in order to generate RTL from
|
|
|
|
the pattern, should be described with a @code{match_operand} in its first
|
|
|
|
occurrence in the RTL template. This enters information on the operand's
|
c-tree.texi, [...]: Be more consistent about the use of "GCC" and related terms.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install.texi, doc/invoke.texi,
doc/md.texi, doc/rtl.texi, doc/tm.texi: Be more consistent about
the use of "GCC" and related terms.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43547
2001-06-25 02:21:28 +02:00
|
|
|
predicate into the tables that record such things. GCC uses the
|
1997-03-25 20:26:08 +01:00
|
|
|
information to preload the operand into a register if that is required for
|
|
|
|
valid RTL code. If the operand is referred to more than once, subsequent
|
|
|
|
references should use @code{match_dup}.
|
|
|
|
|
|
|
|
The RTL template may also refer to internal ``operands'' which are
|
|
|
|
temporary registers or labels used only within the sequence made by the
|
|
|
|
@code{define_expand}. Internal operands are substituted into the RTL
|
|
|
|
template with @code{match_dup}, never with @code{match_operand}. The
|
|
|
|
values of the internal operands are not passed in as arguments by the
|
|
|
|
compiler when it requests use of this pattern. Instead, they are computed
|
|
|
|
within the pattern, in the preparation statements. These statements
|
|
|
|
compute the values and store them into the appropriate elements of
|
|
|
|
@code{operands} so that @code{match_dup} can find them.
|
|
|
|
|
|
|
|
There are two special macros defined for use in the preparation statements:
|
|
|
|
@code{DONE} and @code{FAIL}. Use them with a following semicolon,
|
|
|
|
as a statement.
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
|
|
|
|
@findex DONE
|
|
|
|
@item DONE
|
|
|
|
Use the @code{DONE} macro to end RTL generation for the pattern. The
|
|
|
|
only RTL insns resulting from the pattern on this occasion will be
|
|
|
|
those already emitted by explicit calls to @code{emit_insn} within the
|
|
|
|
preparation statements; the RTL template will not be generated.
|
|
|
|
|
|
|
|
@findex FAIL
|
|
|
|
@item FAIL
|
|
|
|
Make the pattern fail on this occasion. When a pattern fails, it means
|
|
|
|
that the pattern was not truly available. The calling routines in the
|
|
|
|
compiler will try other strategies for code generation using other patterns.
|
|
|
|
|
|
|
|
Failure is currently supported only for binary (addition, multiplication,
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
|
1997-03-25 20:26:08 +01:00
|
|
|
operations.
|
|
|
|
@end table
|
|
|
|
|
2000-12-04 18:23:34 +01:00
|
|
|
If the preparation falls through (invokes neither @code{DONE} nor
|
|
|
|
@code{FAIL}), then the @code{define_expand} acts like a
|
|
|
|
@code{define_insn} in that the RTL template is used to generate the
|
|
|
|
insn.
|
|
|
|
|
|
|
|
The RTL template is not used for matching, only for generating the
|
|
|
|
initial insn list. If the preparation statement always invokes
|
|
|
|
@code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
|
|
|
|
list of operands, such as this example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_expand "addsi3"
|
|
|
|
[(match_operand:SI 0 "register_operand" "")
|
|
|
|
(match_operand:SI 1 "register_operand" "")
|
|
|
|
(match_operand:SI 2 "register_operand" "")]
|
|
|
|
@end group
|
|
|
|
@group
|
|
|
|
""
|
|
|
|
"
|
2000-12-04 19:42:59 +01:00
|
|
|
@{
|
2000-12-04 18:23:34 +01:00
|
|
|
handle_add (operands[0], operands[1], operands[2]);
|
|
|
|
DONE;
|
2000-12-04 19:42:59 +01:00
|
|
|
@}")
|
2000-12-04 18:23:34 +01:00
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
1997-03-25 20:26:08 +01:00
|
|
|
Here is an example, the definition of left-shift for the SPUR chip:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
(define_expand "ashlsi3"
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
(ashift:SI
|
|
|
|
@end group
|
|
|
|
@group
|
|
|
|
(match_operand:SI 1 "register_operand" "")
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "")))]
|
|
|
|
""
|
|
|
|
"
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
@{
|
|
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
|
|
|
|| (unsigned) INTVAL (operands[2]) > 3)
|
|
|
|
FAIL;
|
|
|
|
@}")
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
This example uses @code{define_expand} so that it can generate an RTL insn
|
|
|
|
for shifting when the shift-count is in the supported range of 0 to 3 but
|
|
|
|
fail in other cases where machine insns aren't available. When it fails,
|
|
|
|
the compiler tries another strategy using different patterns (such as, a
|
|
|
|
library call).
|
|
|
|
|
|
|
|
If the compiler were able to handle nontrivial condition-strings in
|
|
|
|
patterns with names, then it would be possible to use a
|
|
|
|
@code{define_insn} in that case. Here is another case (zero-extension
|
|
|
|
on the 68000) which makes more use of the power of @code{define_expand}:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_expand "zero_extendhisi2"
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "")
|
|
|
|
(const_int 0))
|
|
|
|
(set (strict_low_part
|
|
|
|
(subreg:HI
|
|
|
|
(match_dup 0)
|
|
|
|
0))
|
|
|
|
(match_operand:HI 1 "general_operand" ""))]
|
|
|
|
""
|
|
|
|
"operands[1] = make_safe_from (operands[1], operands[0]);")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
@findex make_safe_from
|
|
|
|
Here two RTL insns are generated, one to clear the entire output operand
|
|
|
|
and the other to copy the input operand into its low half. This sequence
|
|
|
|
is incorrect if the input operand refers to [the old value of] the output
|
|
|
|
operand, so the preparation statement makes sure this isn't so. The
|
|
|
|
function @code{make_safe_from} copies the @code{operands[1]} into a
|
|
|
|
temporary register if it refers to @code{operands[0]}. It does this
|
|
|
|
by emitting another RTL insn.
|
|
|
|
|
|
|
|
Finally, a third example shows the use of an internal operand.
|
|
|
|
Zero-extension on the SPUR chip is done by @code{and}-ing the result
|
|
|
|
against a halfword mask. But this mask cannot be represented by a
|
|
|
|
@code{const_int} because the constant value is too large to be legitimate
|
|
|
|
on this machine. So it must be copied into a register with
|
|
|
|
@code{force_reg} and then the register used in the @code{and}.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_expand "zero_extendhisi2"
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
(and:SI (subreg:SI
|
|
|
|
(match_operand:HI 1 "register_operand" "")
|
|
|
|
0)
|
|
|
|
(match_dup 2)))]
|
|
|
|
""
|
|
|
|
"operands[2]
|
1750a.md, [...]: Use GEN_INT consistently.
* 1750a.md, arm.c, clipper.c, clipper.md: Use GEN_INT consistently.
* convex.h, dsp16xx.c, fx80.md, gmicro.c, gmicro.md: Likewise.
* i370.h, i370.md, i860.c, i860.h, i860.md, i960.c: Likewise.
* i960.h, i960.md, m32r.md, m68k.md, m68kv4.h, m88k.c: Likewise.
* m88k.md, ns32k.c, ns32k.md, pdp11.c, pdp11.h, pdp11.md: Likewise.
* pyr.c, pyr.h, pyr.md, romp.c, romp.h, romp.md: Likewise.
* rs6000.md, sparc.c, sparc.h, sparc.md, spur.c, spur.md: Likewise.
* tahoe.md, vax.h, vax.md, we32k.c, we32k.h, we32k.md: Likewise.
* md.texi: Likewise.
From-SVN: r18927
1998-04-01 07:20:26 +02:00
|
|
|
= force_reg (SImode, GEN_INT (65535)); ")
|
1997-03-25 20:26:08 +01:00
|
|
|
@end smallexample
|
|
|
|
|
2004-12-20 10:50:21 +01:00
|
|
|
@emph{Note:} If the @code{define_expand} is used to serve a
|
c-tree.texi, [...]: Fix spelling and typos.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/install.texi, doc/invoke.texi, doc/md.texi,
doc/objc.texi, doc/rtl.texi, doc/tm.texi: Fix spelling and typos.
Consistently use "built-in" and "bit-field". Minor logical markup
improvements.
* doc/gcc.1: Regenerate.
From-SVN: r43383
2001-06-15 00:51:18 +02:00
|
|
|
standard binary or unary arithmetic operation or a bit-field operation,
|
1997-03-25 20:26:08 +01:00
|
|
|
then the last insn it generates must not be a @code{code_label},
|
|
|
|
@code{barrier} or @code{note}. It must be an @code{insn},
|
|
|
|
@code{jump_insn} or @code{call_insn}. If you don't need a real insn
|
|
|
|
at the end, emit an insn to copy the result of the operation into
|
|
|
|
itself. Such an insn will generate no code, but it can avoid problems
|
2001-06-25 01:04:49 +02:00
|
|
|
in the compiler.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Insn Splitting
|
|
|
|
@section Defining How to Split Instructions
|
|
|
|
@cindex insn splitting
|
|
|
|
@cindex instruction splitting
|
|
|
|
@cindex splitting instructions
|
|
|
|
|
2002-04-30 00:34:36 +02:00
|
|
|
There are two cases where you should specify how to split a pattern
|
|
|
|
into multiple insns. On machines that have instructions requiring
|
|
|
|
delay slots (@pxref{Delay Slots}) or that have instructions whose
|
|
|
|
output is not available for multiple cycles (@pxref{Processor pipeline
|
|
|
|
description}), the compiler phases that optimize these cases need to
|
|
|
|
be able to move insns into one-instruction delay slots. However, some
|
|
|
|
insns may generate more than one machine instruction. These insns
|
|
|
|
cannot be placed into a delay slot.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
Often you can rewrite the single insn as a list of individual insns,
|
|
|
|
each corresponding to one machine instruction. The disadvantage of
|
|
|
|
doing so is that it will cause the compilation to be slower and require
|
|
|
|
more space. If the resulting insns are too complex, it may also
|
|
|
|
suppress some optimizations. The compiler splits the insn if there is a
|
|
|
|
reason to believe that it might improve instruction or delay slot
|
|
|
|
scheduling.
|
|
|
|
|
|
|
|
The insn combiner phase also splits putative insns. If three insns are
|
|
|
|
merged into one insn with a complex expression that cannot be matched by
|
|
|
|
some @code{define_insn} pattern, the combiner phase attempts to split
|
|
|
|
the complex pattern into two insns that are recognized. Usually it can
|
|
|
|
break the complex pattern into two patterns by splitting out some
|
|
|
|
subexpression. However, in some other cases, such as performing an
|
|
|
|
addition of a large constant in two insns on a RISC machine, the way to
|
|
|
|
split the addition into two insns is machine-dependent.
|
|
|
|
|
1999-10-02 20:07:49 +02:00
|
|
|
@findex define_split
|
1997-03-25 20:26:08 +01:00
|
|
|
The @code{define_split} definition tells the compiler how to split a
|
|
|
|
complex insn into several simpler insns. It looks like this:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_split
|
|
|
|
[@var{insn-pattern}]
|
|
|
|
"@var{condition}"
|
|
|
|
[@var{new-insn-pattern-1}
|
|
|
|
@var{new-insn-pattern-2}
|
|
|
|
@dots{}]
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@var{preparation-statements}")
|
1997-03-25 20:26:08 +01:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{insn-pattern} is a pattern that needs to be split and
|
|
|
|
@var{condition} is the final condition to be tested, as in a
|
|
|
|
@code{define_insn}. When an insn matching @var{insn-pattern} and
|
|
|
|
satisfying @var{condition} is found, it is replaced in the insn list
|
|
|
|
with the insns given by @var{new-insn-pattern-1},
|
|
|
|
@var{new-insn-pattern-2}, etc.
|
|
|
|
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
The @var{preparation-statements} are similar to those statements that
|
1997-03-25 20:26:08 +01:00
|
|
|
are specified for @code{define_expand} (@pxref{Expander Definitions})
|
|
|
|
and are executed before the new RTL is generated to prepare for the
|
|
|
|
generated code or emit some insns whose pattern is not fixed. Unlike
|
|
|
|
those in @code{define_expand}, however, these statements must not
|
|
|
|
generate any new pseudo-registers. Once reload has completed, they also
|
|
|
|
must not allocate any space in the stack frame.
|
|
|
|
|
|
|
|
Patterns are matched against @var{insn-pattern} in two different
|
|
|
|
circumstances. If an insn needs to be split for delay slot scheduling
|
|
|
|
or insn scheduling, the insn is already known to be valid, which means
|
|
|
|
that it must have been matched by some @code{define_insn} and, if
|
2001-10-10 01:11:55 +02:00
|
|
|
@code{reload_completed} is nonzero, is known to satisfy the constraints
|
1997-03-25 20:26:08 +01:00
|
|
|
of that @code{define_insn}. In that case, the new insn patterns must
|
|
|
|
also be insns that are matched by some @code{define_insn} and, if
|
2001-10-10 01:11:55 +02:00
|
|
|
@code{reload_completed} is nonzero, must also satisfy the constraints
|
1997-03-25 20:26:08 +01:00
|
|
|
of those definitions.
|
|
|
|
|
|
|
|
As an example of this usage of @code{define_split}, consider the following
|
|
|
|
example from @file{a29k.md}, which splits a @code{sign_extend} from
|
|
|
|
@code{HImode} to @code{SImode} into a pair of shift insns:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_split
|
|
|
|
[(set (match_operand:SI 0 "gen_reg_operand" "")
|
|
|
|
(sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
|
|
|
|
""
|
|
|
|
[(set (match_dup 0)
|
|
|
|
(ashift:SI (match_dup 1)
|
|
|
|
(const_int 16)))
|
|
|
|
(set (match_dup 0)
|
|
|
|
(ashiftrt:SI (match_dup 0)
|
|
|
|
(const_int 16)))]
|
|
|
|
"
|
|
|
|
@{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
When the combiner phase tries to split an insn pattern, it is always the
|
|
|
|
case that the pattern is @emph{not} matched by any @code{define_insn}.
|
|
|
|
The combiner pass first tries to split a single @code{set} expression
|
|
|
|
and then the same @code{set} expression inside a @code{parallel}, but
|
|
|
|
followed by a @code{clobber} of a pseudo-reg to use as a scratch
|
|
|
|
register. In these cases, the combiner expects exactly two new insn
|
|
|
|
patterns to be generated. It will verify that these patterns match some
|
|
|
|
@code{define_insn} definitions, so you need not do this test in the
|
|
|
|
@code{define_split} (of course, there is no point in writing a
|
|
|
|
@code{define_split} that will never produce insns that match).
|
|
|
|
|
|
|
|
Here is an example of this use of @code{define_split}, taken from
|
|
|
|
@file{rs6000.md}:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_split
|
|
|
|
[(set (match_operand:SI 0 "gen_reg_operand" "")
|
|
|
|
(plus:SI (match_operand:SI 1 "gen_reg_operand" "")
|
|
|
|
(match_operand:SI 2 "non_add_cint_operand" "")))]
|
|
|
|
""
|
|
|
|
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
|
|
|
|
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
|
|
|
|
"
|
|
|
|
@{
|
|
|
|
int low = INTVAL (operands[2]) & 0xffff;
|
|
|
|
int high = (unsigned) INTVAL (operands[2]) >> 16;
|
|
|
|
|
|
|
|
if (low & 0x8000)
|
|
|
|
high++, low |= 0xffff0000;
|
|
|
|
|
1750a.md, [...]: Use GEN_INT consistently.
* 1750a.md, arm.c, clipper.c, clipper.md: Use GEN_INT consistently.
* convex.h, dsp16xx.c, fx80.md, gmicro.c, gmicro.md: Likewise.
* i370.h, i370.md, i860.c, i860.h, i860.md, i960.c: Likewise.
* i960.h, i960.md, m32r.md, m68k.md, m68kv4.h, m88k.c: Likewise.
* m88k.md, ns32k.c, ns32k.md, pdp11.c, pdp11.h, pdp11.md: Likewise.
* pyr.c, pyr.h, pyr.md, romp.c, romp.h, romp.md: Likewise.
* rs6000.md, sparc.c, sparc.h, sparc.md, spur.c, spur.md: Likewise.
* tahoe.md, vax.h, vax.md, we32k.c, we32k.h, we32k.md: Likewise.
* md.texi: Likewise.
From-SVN: r18927
1998-04-01 07:20:26 +02:00
|
|
|
operands[3] = GEN_INT (high << 16);
|
|
|
|
operands[4] = GEN_INT (low);
|
1997-03-25 20:26:08 +01:00
|
|
|
@}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Here the predicate @code{non_add_cint_operand} matches any
|
|
|
|
@code{const_int} that is @emph{not} a valid operand of a single add
|
|
|
|
insn. The add with the smaller displacement is written so that it
|
|
|
|
can be substituted into the address of a subsequent operation.
|
|
|
|
|
|
|
|
An example that uses a scratch register, from the same file, generates
|
|
|
|
an equality comparison of a register and a large constant:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_split
|
|
|
|
[(set (match_operand:CC 0 "cc_reg_operand" "")
|
|
|
|
(compare:CC (match_operand:SI 1 "gen_reg_operand" "")
|
|
|
|
(match_operand:SI 2 "non_short_cint_operand" "")))
|
|
|
|
(clobber (match_operand:SI 3 "gen_reg_operand" ""))]
|
|
|
|
"find_single_use (operands[0], insn, 0)
|
|
|
|
&& (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
|
|
|
|
|| GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
|
|
|
|
[(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
|
|
|
|
(set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
|
|
|
|
"
|
|
|
|
@{
|
2005-03-05 20:56:31 +01:00
|
|
|
/* @r{Get the constant we are comparing against, C, and see what it
|
1997-03-25 20:26:08 +01:00
|
|
|
looks like sign-extended to 16 bits. Then see what constant
|
2005-03-05 20:56:31 +01:00
|
|
|
could be XOR'ed with C to get the sign-extended value.} */
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
int c = INTVAL (operands[2]);
|
|
|
|
int sextc = (c << 16) >> 16;
|
|
|
|
int xorv = c ^ sextc;
|
|
|
|
|
1750a.md, [...]: Use GEN_INT consistently.
* 1750a.md, arm.c, clipper.c, clipper.md: Use GEN_INT consistently.
* convex.h, dsp16xx.c, fx80.md, gmicro.c, gmicro.md: Likewise.
* i370.h, i370.md, i860.c, i860.h, i860.md, i960.c: Likewise.
* i960.h, i960.md, m32r.md, m68k.md, m68kv4.h, m88k.c: Likewise.
* m88k.md, ns32k.c, ns32k.md, pdp11.c, pdp11.h, pdp11.md: Likewise.
* pyr.c, pyr.h, pyr.md, romp.c, romp.h, romp.md: Likewise.
* rs6000.md, sparc.c, sparc.h, sparc.md, spur.c, spur.md: Likewise.
* tahoe.md, vax.h, vax.md, we32k.c, we32k.h, we32k.md: Likewise.
* md.texi: Likewise.
From-SVN: r18927
1998-04-01 07:20:26 +02:00
|
|
|
operands[4] = GEN_INT (xorv);
|
|
|
|
operands[5] = GEN_INT (sextc);
|
1997-03-25 20:26:08 +01:00
|
|
|
@}")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
To avoid confusion, don't write a single @code{define_split} that
|
|
|
|
accepts some insns that match some @code{define_insn} as well as some
|
|
|
|
insns that don't. Instead, write two separate @code{define_split}
|
|
|
|
definitions, one for the insns that are valid and one for the insns that
|
|
|
|
are not valid.
|
|
|
|
|
2001-07-22 23:42:35 +02:00
|
|
|
The splitter is allowed to split jump instructions into sequence of
|
|
|
|
jumps or create new jumps in while splitting non-jump instructions. As
|
|
|
|
the central flowgraph and branch prediction information needs to be updated,
|
2002-02-23 13:59:09 +01:00
|
|
|
several restriction apply.
|
2001-07-22 23:42:35 +02:00
|
|
|
|
|
|
|
Splitting of jump instruction into sequence that over by another jump
|
2001-12-09 21:21:57 +01:00
|
|
|
instruction is always valid, as compiler expect identical behavior of new
|
2001-07-22 23:42:35 +02:00
|
|
|
jump. When new sequence contains multiple jump instructions or new labels,
|
|
|
|
more assistance is needed. Splitter is required to create only unconditional
|
|
|
|
jumps, or simple conditional jump instructions. Additionally it must attach a
|
2003-06-23 18:01:42 +02:00
|
|
|
@code{REG_BR_PROB} note to each conditional jump. A global variable
|
2005-06-06 05:57:36 +02:00
|
|
|
@code{split_branch_probability} holds the probability of the original branch in case
|
2001-07-22 23:42:35 +02:00
|
|
|
it was an simple conditional jump, @minus{}1 otherwise. To simplify
|
2005-06-06 05:57:36 +02:00
|
|
|
recomputing of edge frequencies, the new sequence is required to have only
|
2001-07-22 23:42:35 +02:00
|
|
|
forward jumps to the newly created labels.
|
|
|
|
|
2001-12-29 00:03:33 +01:00
|
|
|
@findex define_insn_and_split
|
2000-05-03 19:45:26 +02:00
|
|
|
For the common case where the pattern of a define_split exactly matches the
|
|
|
|
pattern of a define_insn, use @code{define_insn_and_split}. It looks like
|
|
|
|
this:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn_and_split
|
|
|
|
[@var{insn-pattern}]
|
|
|
|
"@var{condition}"
|
|
|
|
"@var{output-template}"
|
|
|
|
"@var{split-condition}"
|
|
|
|
[@var{new-insn-pattern-1}
|
|
|
|
@var{new-insn-pattern-2}
|
|
|
|
@dots{}]
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@var{preparation-statements}"
|
2000-05-03 19:45:26 +02:00
|
|
|
[@var{insn-attributes}])
|
|
|
|
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{insn-pattern}, @var{condition}, @var{output-template}, and
|
|
|
|
@var{insn-attributes} are used as in @code{define_insn}. The
|
|
|
|
@var{new-insn-pattern} vector and the @var{preparation-statements} are used as
|
|
|
|
in a @code{define_split}. The @var{split-condition} is also used as in
|
|
|
|
@code{define_split}, with the additional behavior that if the condition starts
|
|
|
|
with @samp{&&}, the condition used for the split will be the constructed as a
|
2001-06-11 22:52:30 +02:00
|
|
|
logical ``and'' of the split condition with the insn condition. For example,
|
2000-05-03 19:45:26 +02:00
|
|
|
from i386.md:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn_and_split "zero_extendhisi2_and"
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
|
|
|
|
(clobber (reg:CC 17))]
|
|
|
|
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
|
|
|
|
"#"
|
|
|
|
"&& reload_completed"
|
2002-02-23 13:59:09 +01:00
|
|
|
[(parallel [(set (match_dup 0)
|
2001-08-18 23:02:44 +02:00
|
|
|
(and:SI (match_dup 0) (const_int 65535)))
|
2000-05-03 19:45:26 +02:00
|
|
|
(clobber (reg:CC 17))])]
|
|
|
|
""
|
|
|
|
[(set_attr "type" "alu1")])
|
|
|
|
|
|
|
|
@end smallexample
|
|
|
|
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
In this case, the actual split condition will be
|
2001-07-03 02:46:05 +02:00
|
|
|
@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
|
2000-05-03 19:45:26 +02:00
|
|
|
|
|
|
|
The @code{define_insn_and_split} construction provides exactly the same
|
|
|
|
functionality as two separate @code{define_insn} and @code{define_split}
|
|
|
|
patterns. It exists for compactness, and as a maintenance tool to prevent
|
|
|
|
having to ensure the two patterns' templates match.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
2001-11-14 21:17:08 +01:00
|
|
|
@node Including Patterns
|
|
|
|
@section Including Patterns in Machine Descriptions.
|
|
|
|
@cindex insn includes
|
|
|
|
|
|
|
|
@findex include
|
|
|
|
The @code{include} pattern tells the compiler tools where to
|
|
|
|
look for patterns that are in files other than in the file
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
@file{.md}. This is used only at build time and there is no preprocessing allowed.
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
It looks like:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
|
|
|
|
(include
|
|
|
|
@var{pathname})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
For example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
|
2002-02-23 13:59:09 +01:00
|
|
|
(include "filestuff")
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
@end smallexample
|
|
|
|
|
2002-08-22 01:24:14 +02:00
|
|
|
Where @var{pathname} is a string that specifies the location of the file,
|
c-tree.texi, [...]: Correct end-of-sentence markup and markup of "etc.", "e.g." and "i.e.".
* doc/c-tree.texi, doc/cfg.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppopts.texi, doc/extend.texi, doc/fragments.texi,
doc/frontends.texi, doc/gcov.texi, doc/hostconfig.texi,
doc/implement-c.texi, doc/install.texi, doc/invoke.texi,
doc/libgcc.texi, doc/md.texi, doc/passes.texi,
doc/portability.texi, doc/rtl.texi, doc/sourcebuild.texi,
doc/standards.texi, doc/tm.texi, doc/tree-ssa.texi,
doc/trouble.texi: Correct end-of-sentence markup and markup of
"etc.", "e.g." and "i.e.". Use @code in various places where
appropriate.
From-SVN: r90101
2004-11-05 02:36:57 +01:00
|
|
|
specifies the include file to be in @file{gcc/config/target/filestuff}. The
|
2001-11-14 21:17:08 +01:00
|
|
|
directory @file{gcc/config/target} is regarded as the default directory.
|
|
|
|
|
|
|
|
|
2002-02-23 13:59:09 +01:00
|
|
|
Machine descriptions may be split up into smaller more manageable subsections
|
|
|
|
and placed into subdirectories.
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
By specifying:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
|
2002-02-23 13:59:09 +01:00
|
|
|
(include "BOGUS/filestuff")
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
|
|
|
|
|
|
|
|
Specifying an absolute path for the include file such as;
|
|
|
|
@smallexample
|
|
|
|
|
2002-02-23 13:59:09 +01:00
|
|
|
(include "/u2/BOGUS/filestuff")
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
@end smallexample
|
2002-02-23 13:59:09 +01:00
|
|
|
is permitted but is not encouraged.
|
2001-11-14 21:17:08 +01:00
|
|
|
|
|
|
|
@subsection RTL Generation Tool Options for Directory Search
|
|
|
|
@cindex directory options .md
|
|
|
|
@cindex options, directory search
|
|
|
|
@cindex search options
|
|
|
|
|
|
|
|
The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
|
|
|
|
For example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
|
|
|
|
genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
|
|
|
|
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
|
|
|
|
Add the directory @var{dir} to the head of the list of directories to be
|
|
|
|
searched for header files. This can be used to override a system machine definition
|
|
|
|
file, substituting your own version, since these directories are
|
|
|
|
searched before the default machine description file directories. If you use more than
|
|
|
|
one @option{-I} option, the directories are scanned in left-to-right
|
|
|
|
order; the standard default directory come after.
|
|
|
|
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1999-10-02 20:07:49 +02:00
|
|
|
@node Peephole Definitions
|
|
|
|
@section Machine-Specific Peephole Optimizers
|
|
|
|
@cindex peephole optimizer definitions
|
|
|
|
@cindex defining peephole optimizers
|
|
|
|
|
|
|
|
In addition to instruction patterns the @file{md} file may contain
|
|
|
|
definitions of machine-specific peephole optimizations.
|
|
|
|
|
|
|
|
The combiner does not notice certain peephole optimizations when the data
|
|
|
|
flow in the program does not suggest that it should try them. For example,
|
|
|
|
sometimes two consecutive insns related in purpose can be combined even
|
|
|
|
though the second one does not appear to use a register computed in the
|
|
|
|
first one. A machine-specific peephole optimizer can detect such
|
|
|
|
opportunities.
|
|
|
|
|
|
|
|
There are two forms of peephole definitions that may be used. The
|
|
|
|
original @code{define_peephole} is run at assembly output time to
|
|
|
|
match insns and substitute assembly text. Use of @code{define_peephole}
|
|
|
|
is deprecated.
|
|
|
|
|
|
|
|
A newer @code{define_peephole2} matches insns and substitutes new
|
|
|
|
insns. The @code{peephole2} pass is run after register allocation
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
but before scheduling, which may result in much better code for
|
1999-10-02 20:07:49 +02:00
|
|
|
targets that do scheduling.
|
|
|
|
|
|
|
|
@menu
|
|
|
|
* define_peephole:: RTL to Text Peephole Optimizers
|
|
|
|
* define_peephole2:: RTL to RTL Peephole Optimizers
|
|
|
|
@end menu
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1999-10-02 20:07:49 +02:00
|
|
|
@node define_peephole
|
|
|
|
@subsection RTL to Text Peephole Optimizers
|
|
|
|
@findex define_peephole
|
|
|
|
|
|
|
|
@need 1000
|
|
|
|
A definition looks like this:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole
|
|
|
|
[@var{insn-pattern-1}
|
|
|
|
@var{insn-pattern-2}
|
|
|
|
@dots{}]
|
|
|
|
"@var{condition}"
|
|
|
|
"@var{template}"
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@var{optional-insn-attributes}")
|
1999-10-02 20:07:49 +02:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
The last string operand may be omitted if you are not using any
|
|
|
|
machine-specific information in this machine description. If present,
|
|
|
|
it must obey the same rules as in a @code{define_insn}.
|
|
|
|
|
|
|
|
In this skeleton, @var{insn-pattern-1} and so on are patterns to match
|
|
|
|
consecutive insns. The optimization applies to a sequence of insns when
|
|
|
|
@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
|
2001-06-25 01:04:49 +02:00
|
|
|
the next, and so on.
|
1999-10-02 20:07:49 +02:00
|
|
|
|
|
|
|
Each of the insns matched by a peephole must also match a
|
|
|
|
@code{define_insn}. Peepholes are checked only at the last stage just
|
|
|
|
before code generation, and only optionally. Therefore, any insn which
|
|
|
|
would match a peephole but no @code{define_insn} will cause a crash in code
|
|
|
|
generation in an unoptimized compilation, or at various optimization
|
|
|
|
stages.
|
|
|
|
|
|
|
|
The operands of the insns are matched with @code{match_operands},
|
|
|
|
@code{match_operator}, and @code{match_dup}, as usual. What is not
|
|
|
|
usual is that the operand numbers apply to all the insn patterns in the
|
|
|
|
definition. So, you can check for identical operands in two insns by
|
|
|
|
using @code{match_operand} in one insn and @code{match_dup} in the
|
|
|
|
other.
|
|
|
|
|
|
|
|
The operand constraints used in @code{match_operand} patterns do not have
|
|
|
|
any direct effect on the applicability of the peephole, but they will
|
|
|
|
be validated afterward, so make sure your constraints are general enough
|
|
|
|
to apply whenever the peephole matches. If the peephole matches
|
|
|
|
but the constraints are not satisfied, the compiler will crash.
|
|
|
|
|
|
|
|
It is safe to omit constraints in all the operands of the peephole; or
|
|
|
|
you can write constraints which serve as a double-check on the criteria
|
|
|
|
previously tested.
|
|
|
|
|
|
|
|
Once a sequence of insns matches the patterns, the @var{condition} is
|
|
|
|
checked. This is a C expression which makes the final decision whether to
|
|
|
|
perform the optimization (we do so if the expression is nonzero). If
|
|
|
|
@var{condition} is omitted (in other words, the string is empty) then the
|
|
|
|
optimization is applied to every sequence of insns that matches the
|
|
|
|
patterns.
|
|
|
|
|
|
|
|
The defined peephole optimizations are applied after register allocation
|
|
|
|
is complete. Therefore, the peephole definition can check which
|
|
|
|
operands have ended up in which kinds of registers, just by looking at
|
|
|
|
the operands.
|
|
|
|
|
|
|
|
@findex prev_active_insn
|
|
|
|
The way to refer to the operands in @var{condition} is to write
|
|
|
|
@code{operands[@var{i}]} for operand number @var{i} (as matched by
|
|
|
|
@code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
|
|
|
|
to refer to the last of the insns being matched; use
|
|
|
|
@code{prev_active_insn} to find the preceding insns.
|
|
|
|
|
|
|
|
@findex dead_or_set_p
|
|
|
|
When optimizing computations with intermediate results, you can use
|
|
|
|
@var{condition} to match only when the intermediate results are not used
|
|
|
|
elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
|
|
|
|
@var{op})}, where @var{insn} is the insn in which you expect the value
|
|
|
|
to be used for the last time (from the value of @code{insn}, together
|
|
|
|
with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
|
2001-06-25 01:04:49 +02:00
|
|
|
value (from @code{operands[@var{i}]}).
|
1999-10-02 20:07:49 +02:00
|
|
|
|
|
|
|
Applying the optimization means replacing the sequence of insns with one
|
|
|
|
new insn. The @var{template} controls ultimate output of assembler code
|
|
|
|
for this combined insn. It works exactly like the template of a
|
|
|
|
@code{define_insn}. Operand numbers in this template are the same ones
|
|
|
|
used in matching the original sequence of insns.
|
|
|
|
|
|
|
|
The result of a defined peephole optimizer does not need to match any of
|
|
|
|
the insn patterns in the machine description; it does not even have an
|
|
|
|
opportunity to match them. The peephole optimizer definition itself serves
|
|
|
|
as the insn pattern to control how the insn is output.
|
|
|
|
|
|
|
|
Defined peephole optimizers are run as assembler code is being output,
|
|
|
|
so the insns they produce are never combined or rearranged in any way.
|
|
|
|
|
|
|
|
Here is an example, taken from the 68000 machine description:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole
|
|
|
|
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
|
|
|
|
(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
(match_operand:DF 1 "register_operand" "ad"))]
|
|
|
|
"FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
|
|
|
|
@{
|
|
|
|
rtx xoperands[2];
|
2004-02-04 07:12:54 +01:00
|
|
|
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
|
1999-10-02 20:07:49 +02:00
|
|
|
#ifdef MOTOROLA
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
output_asm_insn ("move.l %1,(sp)", xoperands);
|
|
|
|
output_asm_insn ("move.l %1,-(sp)", operands);
|
|
|
|
return "fmove.d (sp)+,%0";
|
1999-10-02 20:07:49 +02:00
|
|
|
#else
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
output_asm_insn ("movel %1,sp@@", xoperands);
|
|
|
|
output_asm_insn ("movel %1,sp@@-", operands);
|
|
|
|
return "fmoved sp@@+,%0";
|
1999-10-02 20:07:49 +02:00
|
|
|
#endif
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
@})
|
1999-10-02 20:07:49 +02:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@need 1000
|
|
|
|
The effect of this optimization is to change
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
jbsr _foobar
|
|
|
|
addql #4,sp
|
|
|
|
movel d1,sp@@-
|
|
|
|
movel d0,sp@@-
|
|
|
|
fmoved sp@@+,fp0
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
into
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
@group
|
|
|
|
jbsr _foobar
|
|
|
|
movel d1,sp@@
|
|
|
|
movel d0,sp@@-
|
|
|
|
fmoved sp@@+,fp0
|
|
|
|
@end group
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@ignore
|
|
|
|
@findex CC_REVERSED
|
|
|
|
If a peephole matches a sequence including one or more jump insns, you must
|
|
|
|
take account of the flags such as @code{CC_REVERSED} which specify that the
|
|
|
|
condition codes are represented in an unusual manner. The compiler
|
|
|
|
automatically alters any ordinary conditional jumps which occur in such
|
|
|
|
situations, but the compiler cannot alter jumps which have been replaced by
|
|
|
|
peephole optimizations. So it is up to you to alter the assembler code
|
|
|
|
that the peephole produces. Supply C code to write the assembler output,
|
|
|
|
and in this C code check the condition code status flags and change the
|
|
|
|
assembler code as appropriate.
|
|
|
|
@end ignore
|
|
|
|
|
|
|
|
@var{insn-pattern-1} and so on look @emph{almost} like the second
|
|
|
|
operand of @code{define_insn}. There is one important difference: the
|
|
|
|
second operand of @code{define_insn} consists of one or more RTX's
|
|
|
|
enclosed in square brackets. Usually, there is only one: then the same
|
|
|
|
action can be written as an element of a @code{define_peephole}. But
|
|
|
|
when there are multiple actions in a @code{define_insn}, they are
|
|
|
|
implicitly enclosed in a @code{parallel}. Then you must explicitly
|
|
|
|
write the @code{parallel}, and the square brackets within it, in the
|
|
|
|
@code{define_peephole}. Thus, if an insn pattern looks like this,
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "divmodsi4"
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=d")
|
|
|
|
(div:SI (match_operand:SI 1 "general_operand" "0")
|
|
|
|
(match_operand:SI 2 "general_operand" "dmsK")))
|
|
|
|
(set (match_operand:SI 3 "general_operand" "=d")
|
|
|
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
"TARGET_68020"
|
|
|
|
"divsl%.l %2,%3:%0")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
then the way to mention this insn in a peephole is as follows:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole
|
|
|
|
[@dots{}
|
|
|
|
(parallel
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=d")
|
|
|
|
(div:SI (match_operand:SI 1 "general_operand" "0")
|
|
|
|
(match_operand:SI 2 "general_operand" "dmsK")))
|
|
|
|
(set (match_operand:SI 3 "general_operand" "=d")
|
|
|
|
(mod:SI (match_dup 1) (match_dup 2)))])
|
|
|
|
@dots{}]
|
|
|
|
@dots{})
|
|
|
|
@end smallexample
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1999-10-02 20:07:49 +02:00
|
|
|
@node define_peephole2
|
|
|
|
@subsection RTL to RTL Peephole Optimizers
|
|
|
|
@findex define_peephole2
|
|
|
|
|
|
|
|
The @code{define_peephole2} definition tells the compiler how to
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
substitute one sequence of instructions for another sequence,
|
1999-10-02 20:07:49 +02:00
|
|
|
what additional scratch registers may be needed and what their
|
|
|
|
lifetimes must be.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole2
|
|
|
|
[@var{insn-pattern-1}
|
|
|
|
@var{insn-pattern-2}
|
|
|
|
@dots{}]
|
|
|
|
"@var{condition}"
|
|
|
|
[@var{new-insn-pattern-1}
|
|
|
|
@var{new-insn-pattern-2}
|
|
|
|
@dots{}]
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"@var{preparation-statements}")
|
1999-10-02 20:07:49 +02:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The definition is almost identical to @code{define_split}
|
|
|
|
(@pxref{Insn Splitting}) except that the pattern to match is not a
|
|
|
|
single instruction, but a sequence of instructions.
|
|
|
|
|
|
|
|
It is possible to request additional scratch registers for use in the
|
|
|
|
output template. If appropriate registers are not free, the pattern
|
|
|
|
will simply not match.
|
|
|
|
|
|
|
|
@findex match_scratch
|
|
|
|
@findex match_dup
|
|
|
|
Scratch registers are requested with a @code{match_scratch} pattern at
|
|
|
|
the top level of the input pattern. The allocated register (initially) will
|
|
|
|
be dead at the point requested within the original sequence. If the scratch
|
|
|
|
is used at more than a single point, a @code{match_dup} pattern at the
|
|
|
|
top level of the input pattern marks the last position in the input sequence
|
|
|
|
at which the register must be available.
|
|
|
|
|
|
|
|
Here is an example from the IA-32 machine description:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole2
|
|
|
|
[(match_scratch:SI 2 "r")
|
|
|
|
(parallel [(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
(match_operator:SI 3 "arith_or_logical_operator"
|
|
|
|
[(match_dup 0)
|
|
|
|
(match_operand:SI 1 "memory_operand" "")]))
|
|
|
|
(clobber (reg:CC 17))])]
|
|
|
|
"! optimize_size && ! TARGET_READ_MODIFY"
|
|
|
|
[(set (match_dup 2) (match_dup 1))
|
|
|
|
(parallel [(set (match_dup 0)
|
|
|
|
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
|
|
|
|
(clobber (reg:CC 17))])]
|
|
|
|
"")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
This pattern tries to split a load from its use in the hopes that we'll be
|
|
|
|
able to schedule around the memory load latency. It allocates a single
|
|
|
|
@code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
|
|
|
|
to be live only at the point just before the arithmetic.
|
|
|
|
|
2000-07-06 03:07:01 +02:00
|
|
|
A real example requiring extended scratch lifetimes is harder to come by,
|
1999-10-02 20:07:49 +02:00
|
|
|
so here's a silly made-up example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_peephole2
|
|
|
|
[(match_scratch:SI 4 "r")
|
|
|
|
(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
|
|
|
(set (match_operand:SI 2 "" "") (match_dup 1))
|
|
|
|
(match_dup 4)
|
|
|
|
(set (match_operand:SI 3 "" "") (match_dup 1))]
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
|
|
"/* @r{determine 1 does not overlap 0 and 2} */"
|
1999-10-02 20:07:49 +02:00
|
|
|
[(set (match_dup 4) (match_dup 1))
|
|
|
|
(set (match_dup 0) (match_dup 4))
|
|
|
|
(set (match_dup 2) (match_dup 4))]
|
|
|
|
(set (match_dup 3) (match_dup 4))]
|
|
|
|
"")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
1999-10-02 20:45:42 +02:00
|
|
|
If we had not added the @code{(match_dup 4)} in the middle of the input
|
|
|
|
sequence, it might have been the case that the register we chose at the
|
|
|
|
beginning of the sequence is killed by the first or second @code{set}.
|
1999-10-02 20:07:49 +02:00
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Insn Attributes
|
|
|
|
@section Instruction Attributes
|
|
|
|
@cindex insn attributes
|
|
|
|
@cindex instruction attributes
|
|
|
|
|
|
|
|
In addition to describing the instruction supported by the target machine,
|
|
|
|
the @file{md} file also defines a group of @dfn{attributes} and a set of
|
|
|
|
values for each. Every generated insn is assigned a value for each attribute.
|
|
|
|
One possible attribute would be the effect that the insn has on the machine's
|
|
|
|
condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
|
|
|
|
to track the condition codes.
|
|
|
|
|
|
|
|
@menu
|
|
|
|
* Defining Attributes:: Specifying attributes and their values.
|
|
|
|
* Expressions:: Valid expressions for attribute values.
|
|
|
|
* Tagging Insns:: Assigning attribute values to insns.
|
|
|
|
* Attr Example:: An example of assigning attributes.
|
|
|
|
* Insn Lengths:: Computing the length of insns.
|
|
|
|
* Constant Attributes:: Defining attributes that are constant.
|
|
|
|
* Delay Slots:: Defining delay slots required for a machine.
|
2002-04-30 00:34:36 +02:00
|
|
|
* Processor pipeline description:: Specifying information for insn scheduling.
|
1997-03-25 20:26:08 +01:00
|
|
|
@end menu
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Defining Attributes
|
|
|
|
@subsection Defining Attributes and their Values
|
|
|
|
@cindex defining attributes and their values
|
|
|
|
@cindex attributes, defining
|
|
|
|
|
|
|
|
@findex define_attr
|
|
|
|
The @code{define_attr} expression is used to define each attribute required
|
|
|
|
by the target machine. It looks like:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_attr @var{name} @var{list-of-values} @var{default})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{name} is a string specifying the name of the attribute being defined.
|
|
|
|
|
|
|
|
@var{list-of-values} is either a string that specifies a comma-separated
|
|
|
|
list of values that can be assigned to the attribute, or a null string to
|
|
|
|
indicate that the attribute takes numeric values.
|
|
|
|
|
|
|
|
@var{default} is an attribute expression that gives the value of this
|
|
|
|
attribute for insns that match patterns whose definition does not include
|
|
|
|
an explicit value for this attribute. @xref{Attr Example}, for more
|
|
|
|
information on the handling of defaults. @xref{Constant Attributes},
|
|
|
|
for information on attributes that do not depend on any particular insn.
|
|
|
|
|
|
|
|
@findex insn-attr.h
|
|
|
|
For each defined attribute, a number of definitions are written to the
|
|
|
|
@file{insn-attr.h} file. For cases where an explicit set of values is
|
|
|
|
specified for an attribute, the following are defined:
|
|
|
|
|
|
|
|
@itemize @bullet
|
|
|
|
@item
|
|
|
|
A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
|
|
|
|
|
|
|
|
@item
|
2004-07-02 00:02:41 +02:00
|
|
|
An enumerated class is defined for @samp{attr_@var{name}} with
|
1997-03-25 20:26:08 +01:00
|
|
|
elements of the form @samp{@var{upper-name}_@var{upper-value}} where
|
2003-07-31 03:32:24 +02:00
|
|
|
the attribute name and value are first converted to uppercase.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@item
|
|
|
|
A function @samp{get_attr_@var{name}} is defined that is passed an insn and
|
|
|
|
returns the attribute value for that insn.
|
|
|
|
@end itemize
|
|
|
|
|
|
|
|
For example, if the following is present in the @file{md} file:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_attr "type" "branch,fp,load,store,arith" @dots{})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
the following lines will be written to the file @file{insn-attr.h}.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
#define HAVE_ATTR_type
|
|
|
|
enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
|
|
|
|
TYPE_STORE, TYPE_ARITH@};
|
|
|
|
extern enum attr_type get_attr_type ();
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
If the attribute takes numeric values, no @code{enum} type will be
|
|
|
|
defined and the function to obtain the attribute's value will return
|
|
|
|
@code{int}.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Expressions
|
|
|
|
@subsection Attribute Expressions
|
|
|
|
@cindex attribute expressions
|
|
|
|
|
|
|
|
RTL expressions used to define attributes use the codes described above
|
|
|
|
plus a few specific to attribute definitions, to be discussed below.
|
|
|
|
Attribute value expressions must have one of the following forms:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@cindex @code{const_int} and attributes
|
|
|
|
@item (const_int @var{i})
|
|
|
|
The integer @var{i} specifies the value of a numeric attribute. @var{i}
|
|
|
|
must be non-negative.
|
|
|
|
|
|
|
|
The value of a numeric attribute can be specified either with a
|
1999-02-21 19:39:33 +01:00
|
|
|
@code{const_int}, or as an integer represented as a string in
|
|
|
|
@code{const_string}, @code{eq_attr} (see below), @code{attr},
|
|
|
|
@code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
|
|
|
|
overrides on specific instructions (@pxref{Tagging Insns}).
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{const_string} and attributes
|
|
|
|
@item (const_string @var{value})
|
|
|
|
The string @var{value} specifies a constant attribute value.
|
|
|
|
If @var{value} is specified as @samp{"*"}, it means that the default value of
|
|
|
|
the attribute is to be used for the insn containing this expression.
|
|
|
|
@samp{"*"} obviously cannot be used in the @var{default} expression
|
2001-06-25 01:04:49 +02:00
|
|
|
of a @code{define_attr}.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
If the attribute whose value is being specified is numeric, @var{value}
|
|
|
|
must be a string containing a non-negative integer (normally
|
|
|
|
@code{const_int} would be used in this case). Otherwise, it must
|
|
|
|
contain one of the valid values for the attribute.
|
|
|
|
|
|
|
|
@cindex @code{if_then_else} and attributes
|
|
|
|
@item (if_then_else @var{test} @var{true-value} @var{false-value})
|
|
|
|
@var{test} specifies an attribute test, whose format is defined below.
|
|
|
|
The value of this expression is @var{true-value} if @var{test} is true,
|
|
|
|
otherwise it is @var{false-value}.
|
|
|
|
|
|
|
|
@cindex @code{cond} and attributes
|
|
|
|
@item (cond [@var{test1} @var{value1} @dots{}] @var{default})
|
|
|
|
The first operand of this expression is a vector containing an even
|
|
|
|
number of expressions and consisting of pairs of @var{test} and @var{value}
|
|
|
|
expressions. The value of the @code{cond} expression is that of the
|
|
|
|
@var{value} corresponding to the first true @var{test} expression. If
|
|
|
|
none of the @var{test} expressions are true, the value of the @code{cond}
|
|
|
|
expression is that of the @var{default} expression.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@var{test} expressions can have one of the following forms:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@cindex @code{const_int} and attribute tests
|
|
|
|
@item (const_int @var{i})
|
2001-10-10 01:11:55 +02:00
|
|
|
This test is true if @var{i} is nonzero and false otherwise.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@cindex @code{not} and attributes
|
|
|
|
@cindex @code{ior} and attributes
|
|
|
|
@cindex @code{and} and attributes
|
|
|
|
@item (not @var{test})
|
|
|
|
@itemx (ior @var{test1} @var{test2})
|
|
|
|
@itemx (and @var{test1} @var{test2})
|
|
|
|
These tests are true if the indicated logical function is true.
|
|
|
|
|
|
|
|
@cindex @code{match_operand} and attributes
|
|
|
|
@item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
|
|
|
|
This test is true if operand @var{n} of the insn whose attribute value
|
|
|
|
is being determined has mode @var{m} (this part of the test is ignored
|
|
|
|
if @var{m} is @code{VOIDmode}) and the function specified by the string
|
2001-10-10 01:11:55 +02:00
|
|
|
@var{pred} returns a nonzero value when passed operand @var{n} and mode
|
1997-03-25 20:26:08 +01:00
|
|
|
@var{m} (this part of the test is ignored if @var{pred} is the null
|
|
|
|
string).
|
|
|
|
|
|
|
|
The @var{constraints} operand is ignored and should be the null string.
|
|
|
|
|
|
|
|
@cindex @code{le} and attributes
|
|
|
|
@cindex @code{leu} and attributes
|
|
|
|
@cindex @code{lt} and attributes
|
|
|
|
@cindex @code{gt} and attributes
|
|
|
|
@cindex @code{gtu} and attributes
|
|
|
|
@cindex @code{ge} and attributes
|
|
|
|
@cindex @code{geu} and attributes
|
|
|
|
@cindex @code{ne} and attributes
|
|
|
|
@cindex @code{eq} and attributes
|
|
|
|
@cindex @code{plus} and attributes
|
|
|
|
@cindex @code{minus} and attributes
|
|
|
|
@cindex @code{mult} and attributes
|
|
|
|
@cindex @code{div} and attributes
|
|
|
|
@cindex @code{mod} and attributes
|
|
|
|
@cindex @code{abs} and attributes
|
|
|
|
@cindex @code{neg} and attributes
|
|
|
|
@cindex @code{ashift} and attributes
|
|
|
|
@cindex @code{lshiftrt} and attributes
|
|
|
|
@cindex @code{ashiftrt} and attributes
|
|
|
|
@item (le @var{arith1} @var{arith2})
|
|
|
|
@itemx (leu @var{arith1} @var{arith2})
|
|
|
|
@itemx (lt @var{arith1} @var{arith2})
|
|
|
|
@itemx (ltu @var{arith1} @var{arith2})
|
|
|
|
@itemx (gt @var{arith1} @var{arith2})
|
|
|
|
@itemx (gtu @var{arith1} @var{arith2})
|
|
|
|
@itemx (ge @var{arith1} @var{arith2})
|
|
|
|
@itemx (geu @var{arith1} @var{arith2})
|
|
|
|
@itemx (ne @var{arith1} @var{arith2})
|
|
|
|
@itemx (eq @var{arith1} @var{arith2})
|
|
|
|
These tests are true if the indicated comparison of the two arithmetic
|
|
|
|
expressions is true. Arithmetic expressions are formed with
|
|
|
|
@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
|
|
|
|
@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
|
2001-06-25 01:04:49 +02:00
|
|
|
@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@findex get_attr
|
|
|
|
@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
|
|
|
|
Lengths},for additional forms). @code{symbol_ref} is a string
|
|
|
|
denoting a C expression that yields an @code{int} when evaluated by the
|
|
|
|
@samp{get_attr_@dots{}} routine. It should normally be a global
|
2001-06-25 01:04:49 +02:00
|
|
|
variable.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@findex eq_attr
|
|
|
|
@item (eq_attr @var{name} @var{value})
|
|
|
|
@var{name} is a string specifying the name of an attribute.
|
|
|
|
|
|
|
|
@var{value} is a string that is either a valid value for attribute
|
|
|
|
@var{name}, a comma-separated list of values, or @samp{!} followed by a
|
|
|
|
value or list. If @var{value} does not begin with a @samp{!}, this
|
|
|
|
test is true if the value of the @var{name} attribute of the current
|
|
|
|
insn is in the list specified by @var{value}. If @var{value} begins
|
|
|
|
with a @samp{!}, this test is true if the attribute's value is
|
|
|
|
@emph{not} in the specified list.
|
|
|
|
|
|
|
|
For example,
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(eq_attr "type" "load,store")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
is equivalent to
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(ior (eq_attr "type" "load") (eq_attr "type" "store"))
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
If @var{name} specifies an attribute of @samp{alternative}, it refers to the
|
|
|
|
value of the compiler variable @code{which_alternative}
|
|
|
|
(@pxref{Output Statement}) and the values must be small integers. For
|
2001-06-25 01:04:49 +02:00
|
|
|
example,
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(eq_attr "alternative" "2,3")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
is equivalent to
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(ior (eq (symbol_ref "which_alternative") (const_int 2))
|
|
|
|
(eq (symbol_ref "which_alternative") (const_int 3)))
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Note that, for most attributes, an @code{eq_attr} test is simplified in cases
|
|
|
|
where the value of the attribute being tested is known for all insns matching
|
2001-06-25 01:04:49 +02:00
|
|
|
a particular pattern. This is by far the most common case.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
@findex attr_flag
|
|
|
|
@item (attr_flag @var{name})
|
|
|
|
The value of an @code{attr_flag} expression is true if the flag
|
|
|
|
specified by @var{name} is true for the @code{insn} currently being
|
|
|
|
scheduled.
|
|
|
|
|
|
|
|
@var{name} is a string specifying one of a fixed set of flags to test.
|
|
|
|
Test the flags @code{forward} and @code{backward} to determine the
|
|
|
|
direction of a conditional branch. Test the flags @code{very_likely},
|
|
|
|
@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
|
|
|
|
if a conditional branch is expected to be taken.
|
|
|
|
|
|
|
|
If the @code{very_likely} flag is true, then the @code{likely} flag is also
|
|
|
|
true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
|
|
|
|
|
|
|
|
This example describes a conditional branch delay slot which
|
|
|
|
can be nullified for forward branches that are taken (annul-true) or
|
|
|
|
for backward branches which are not taken (annul-false).
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_delay (eq_attr "type" "cbranch")
|
|
|
|
[(eq_attr "in_branch_delay" "true")
|
|
|
|
(and (eq_attr "in_branch_delay" "true")
|
|
|
|
(attr_flag "forward"))
|
|
|
|
(and (eq_attr "in_branch_delay" "true")
|
|
|
|
(attr_flag "backward"))])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The @code{forward} and @code{backward} flags are false if the current
|
|
|
|
@code{insn} being scheduled is not a conditional branch.
|
|
|
|
|
|
|
|
The @code{very_likely} and @code{likely} flags are true if the
|
|
|
|
@code{insn} being scheduled is not a conditional branch.
|
|
|
|
The @code{very_unlikely} and @code{unlikely} flags are false if the
|
|
|
|
@code{insn} being scheduled is not a conditional branch.
|
|
|
|
|
|
|
|
@code{attr_flag} is only used during delay slot scheduling and has no
|
|
|
|
meaning to other passes of the compiler.
|
1999-02-21 19:39:33 +01:00
|
|
|
|
|
|
|
@findex attr
|
|
|
|
@item (attr @var{name})
|
|
|
|
The value of another attribute is returned. This is most useful
|
|
|
|
for numeric attributes, as @code{eq_attr} and @code{attr_flag}
|
|
|
|
produce more efficient code for non-numeric attributes.
|
1997-03-25 20:26:08 +01:00
|
|
|
@end table
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Tagging Insns
|
|
|
|
@subsection Assigning Attribute Values to Insns
|
|
|
|
@cindex tagging insns
|
|
|
|
@cindex assigning attribute values to insns
|
|
|
|
|
|
|
|
The value assigned to an attribute of an insn is primarily determined by
|
|
|
|
which pattern is matched by that insn (or which @code{define_peephole}
|
|
|
|
generated it). Every @code{define_insn} and @code{define_peephole} can
|
|
|
|
have an optional last argument to specify the values of attributes for
|
|
|
|
matching insns. The value of any attribute not specified in a particular
|
|
|
|
insn is set to the default value for that attribute, as specified in its
|
|
|
|
@code{define_attr}. Extensive use of default values for attributes
|
|
|
|
permits the specification of the values for only one or two attributes
|
|
|
|
in the definition of most insn patterns, as seen in the example in the
|
2001-06-25 01:04:49 +02:00
|
|
|
next section.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
The optional last argument of @code{define_insn} and
|
|
|
|
@code{define_peephole} is a vector of expressions, each of which defines
|
|
|
|
the value for a single attribute. The most general way of assigning an
|
|
|
|
attribute's value is to use a @code{set} expression whose first operand is an
|
|
|
|
@code{attr} expression giving the name of the attribute being set. The
|
|
|
|
second operand of the @code{set} is an attribute expression
|
2001-06-25 01:04:49 +02:00
|
|
|
(@pxref{Expressions}) giving the value of the attribute.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
When the attribute value depends on the @samp{alternative} attribute
|
|
|
|
(i.e., which is the applicable alternative in the constraint of the
|
|
|
|
insn), the @code{set_attr_alternative} expression can be used. It
|
|
|
|
allows the specification of a vector of attribute expressions, one for
|
|
|
|
each alternative.
|
|
|
|
|
|
|
|
@findex set_attr
|
|
|
|
When the generality of arbitrary attribute expressions is not required,
|
|
|
|
the simpler @code{set_attr} expression can be used, which allows
|
|
|
|
specifying a string giving either a single attribute value or a list
|
|
|
|
of attribute values, one for each alternative.
|
|
|
|
|
|
|
|
The form of each of the above specifications is shown below. In each case,
|
|
|
|
@var{name} is a string specifying the attribute to be set.
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@item (set_attr @var{name} @var{value-string})
|
|
|
|
@var{value-string} is either a string giving the desired attribute value,
|
|
|
|
or a string containing a comma-separated list giving the values for
|
|
|
|
succeeding alternatives. The number of elements must match the number
|
|
|
|
of alternatives in the constraint of the insn pattern.
|
|
|
|
|
|
|
|
Note that it may be useful to specify @samp{*} for some alternative, in
|
|
|
|
which case the attribute will assume its default value for insns matching
|
|
|
|
that alternative.
|
|
|
|
|
|
|
|
@findex set_attr_alternative
|
|
|
|
@item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
|
|
|
|
Depending on the alternative of the insn, the value will be one of the
|
|
|
|
specified values. This is a shorthand for using a @code{cond} with
|
|
|
|
tests on the @samp{alternative} attribute.
|
|
|
|
|
|
|
|
@findex attr
|
|
|
|
@item (set (attr @var{name}) @var{value})
|
|
|
|
The first operand of this @code{set} must be the special RTL expression
|
|
|
|
@code{attr}, whose sole operand is a string giving the name of the
|
|
|
|
attribute being set. @var{value} is the value of the attribute.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
The following shows three different ways of representing the same
|
|
|
|
attribute value specification:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(set_attr "type" "load,store,arith")
|
|
|
|
|
|
|
|
(set_attr_alternative "type"
|
|
|
|
[(const_string "load") (const_string "store")
|
|
|
|
(const_string "arith")])
|
|
|
|
|
|
|
|
(set (attr "type")
|
|
|
|
(cond [(eq_attr "alternative" "1") (const_string "load")
|
|
|
|
(eq_attr "alternative" "2") (const_string "store")]
|
|
|
|
(const_string "arith")))
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@need 1000
|
|
|
|
@findex define_asm_attributes
|
|
|
|
The @code{define_asm_attributes} expression provides a mechanism to
|
|
|
|
specify the attributes assigned to insns produced from an @code{asm}
|
|
|
|
statement. It has the form:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_asm_attributes [@var{attr-sets}])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@noindent
|
|
|
|
where @var{attr-sets} is specified the same as for both the
|
|
|
|
@code{define_insn} and the @code{define_peephole} expressions.
|
|
|
|
|
|
|
|
These values will typically be the ``worst case'' attribute values. For
|
|
|
|
example, they might indicate that the condition code will be clobbered.
|
|
|
|
|
|
|
|
A specification for a @code{length} attribute is handled specially. The
|
|
|
|
way to compute the length of an @code{asm} insn is to multiply the
|
|
|
|
length specified in the expression @code{define_asm_attributes} by the
|
|
|
|
number of machine instructions specified in the @code{asm} statement,
|
|
|
|
determined by counting the number of semicolons and newlines in the
|
|
|
|
string. Therefore, the value of the @code{length} attribute specified
|
|
|
|
in a @code{define_asm_attributes} should be the maximum possible length
|
|
|
|
of a single machine instruction.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Attr Example
|
|
|
|
@subsection Example of Attribute Specifications
|
|
|
|
@cindex attribute specifications example
|
|
|
|
@cindex attribute specifications
|
|
|
|
|
|
|
|
The judicious use of defaulting is important in the efficient use of
|
|
|
|
insn attributes. Typically, insns are divided into @dfn{types} and an
|
|
|
|
attribute, customarily called @code{type}, is used to represent this
|
|
|
|
value. This attribute is normally used only to define the default value
|
|
|
|
for other attributes. An example will clarify this usage.
|
|
|
|
|
|
|
|
Assume we have a RISC machine with a condition code and in which only
|
|
|
|
full-word operations are performed in registers. Let us assume that we
|
|
|
|
can divide all insns into loads, stores, (integer) arithmetic
|
|
|
|
operations, floating point operations, and branches.
|
|
|
|
|
|
|
|
Here we will concern ourselves with determining the effect of an insn on
|
|
|
|
the condition code and will limit ourselves to the following possible
|
|
|
|
effects: The condition code can be set unpredictably (clobbered), not
|
|
|
|
be changed, be set to agree with the results of the operation, or only
|
|
|
|
changed if the item previously set into the condition code has been
|
|
|
|
modified.
|
|
|
|
|
|
|
|
Here is part of a sample @file{md} file for such a machine:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
|
|
|
|
|
|
|
|
(define_attr "cc" "clobber,unchanged,set,change0"
|
|
|
|
(cond [(eq_attr "type" "load")
|
|
|
|
(const_string "change0")
|
|
|
|
(eq_attr "type" "store,branch")
|
|
|
|
(const_string "unchanged")
|
|
|
|
(eq_attr "type" "arith")
|
|
|
|
(if_then_else (match_operand:SI 0 "" "")
|
|
|
|
(const_string "set")
|
|
|
|
(const_string "clobber"))]
|
|
|
|
(const_string "clobber")))
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SI 0 "general_operand" "=r,r,m")
|
|
|
|
(match_operand:SI 1 "general_operand" "r,m,r"))]
|
|
|
|
""
|
|
|
|
"@@
|
|
|
|
move %0,%1
|
|
|
|
load %0,%1
|
|
|
|
store %0,%1"
|
|
|
|
[(set_attr "type" "arith,load,store")])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Note that we assume in the above example that arithmetic operations
|
|
|
|
performed on quantities smaller than a machine word clobber the condition
|
|
|
|
code since they will set the condition code to a value corresponding to the
|
|
|
|
full-word result.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Insn Lengths
|
|
|
|
@subsection Computing the Length of an Insn
|
|
|
|
@cindex insn lengths, computing
|
|
|
|
@cindex computing the length of an insn
|
|
|
|
|
|
|
|
For many machines, multiple types of branch instructions are provided, each
|
|
|
|
for different length branch displacements. In most cases, the assembler
|
|
|
|
will choose the correct instruction to use. However, when the assembler
|
2005-02-10 09:38:23 +01:00
|
|
|
cannot do so, GCC can when a special attribute, the @code{length}
|
1997-03-25 20:26:08 +01:00
|
|
|
attribute, is defined. This attribute must be defined to have numeric
|
|
|
|
values by specifying a null string in its @code{define_attr}.
|
|
|
|
|
2005-02-10 09:38:23 +01:00
|
|
|
In the case of the @code{length} attribute, two additional forms of
|
1997-03-25 20:26:08 +01:00
|
|
|
arithmetic terms are allowed in test expressions:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@cindex @code{match_dup} and attributes
|
|
|
|
@item (match_dup @var{n})
|
|
|
|
This refers to the address of operand @var{n} of the current insn, which
|
|
|
|
must be a @code{label_ref}.
|
|
|
|
|
|
|
|
@cindex @code{pc} and attributes
|
|
|
|
@item (pc)
|
|
|
|
This refers to the address of the @emph{current} insn. It might have
|
|
|
|
been more consistent with other usage to make this the address of the
|
|
|
|
@emph{next} insn but this would be confusing because the length of the
|
|
|
|
current insn is to be computed.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@cindex @code{addr_vec}, length of
|
|
|
|
@cindex @code{addr_diff_vec}, length of
|
|
|
|
For normal insns, the length will be determined by value of the
|
2005-02-10 09:38:23 +01:00
|
|
|
@code{length} attribute. In the case of @code{addr_vec} and
|
1997-03-25 20:26:08 +01:00
|
|
|
@code{addr_diff_vec} insn patterns, the length is computed as
|
|
|
|
the number of vectors multiplied by the size of each vector.
|
|
|
|
|
|
|
|
Lengths are measured in addressable storage units (bytes).
|
|
|
|
|
|
|
|
The following macros can be used to refine the length computation:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
@findex ADJUST_INSN_LENGTH
|
|
|
|
@item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
|
|
|
|
If defined, modifies the length assigned to instruction @var{insn} as a
|
|
|
|
function of the context in which it is used. @var{length} is an lvalue
|
|
|
|
that contains the initially computed length of the insn and should be
|
1998-03-11 08:12:31 +01:00
|
|
|
updated with the correct length of the insn.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
This macro will normally not be required. A case in which it is
|
c-tree.texi, [...]: Replace . at end of sentences preceded by a capital letter with @..
* doc/c-tree.texi, doc/contrib.texi, doc/cpp.texi,
doc/cppinternals.texi, doc/extend.texi, doc/gcc.texi,
doc/gcov.texi, doc/install-old.texi, doc/install.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Replace
. at end of sentences preceded by a capital letter with @..
From-SVN: r43611
2001-06-27 17:04:16 +02:00
|
|
|
required is the ROMP@. On this machine, the size of an @code{addr_vec}
|
1997-03-25 20:26:08 +01:00
|
|
|
insn must be increased by two to compensate for the fact that alignment
|
|
|
|
may be required.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@findex get_attr_length
|
|
|
|
The routine that returns @code{get_attr_length} (the value of the
|
|
|
|
@code{length} attribute) can be used by the output routine to
|
|
|
|
determine the form of the branch instruction to be written, as the
|
|
|
|
example below illustrates.
|
|
|
|
|
|
|
|
As an example of the specification of variable-length branches, consider
|
|
|
|
the IBM 360. If we adopt the convention that a register will be set to
|
|
|
|
the starting address of a function, we can jump to labels within 4k of
|
|
|
|
the start using a four-byte instruction. Otherwise, we need a six-byte
|
|
|
|
sequence to load the address from memory and then branch to it.
|
|
|
|
|
|
|
|
On such a machine, a pattern for a branch instruction might be specified
|
|
|
|
as follows:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn "jump"
|
|
|
|
[(set (pc)
|
|
|
|
(label_ref (match_operand 0 "" "")))]
|
|
|
|
""
|
|
|
|
@{
|
|
|
|
return (get_attr_length (insn) == 4
|
i386.md: Global update to use new string syntax where it will improve readability.
* config/i386/i386.md: Global update to use new string syntax
where it will improve readability. Warning fixes:
(*truncdfsf2_2): Abort if which_alternative is not 0 or 1.
(*adddi_1_rex64, *adddi_2_rex64, *adddi_3_rex64,
*adddi_4_rex64, *adddi_5_rex64): Cast 1 to unsigned int.
* read-rtl.c: Syntactic sugar for C embedded in strings in
machine descriptions.
(read_string): Break inner loop into separate function. Takes
an int. Dispatch to read_quoted_string or read_braced_string
as appropriate. Automatically insert a leading star on braced
strings if STAR_IF_BRACED is true.
(read_quoted_string, read_braced_string): New functions.
* doc/rtl.texi, doc/md.texi: Document new syntax. Update
examples to match.
* rtl.c: Split RTL reader (read_rtx, read_skip_spaces,
traverse_md_constants, fatal_with_file_and_line,
fatal_expected_char, read_name, read_string, def_hash,
def_name_eq_p, read_constants, and related data) to its own
file. Weed out now-unnecessary #includes.
* read-rtl.c: New file.
* Makefile.in (HOST_RTL): Add read-rtl.o.
(read-rtl.o): New rule.
(rtl.o, $(HOST_PREFIX_1)rtl.o): Update dependencies.
* doc/gcc.texi (Passes): Talk briefly about the support
library used by genfoo.
* doc/rtl.texi (Reading RTL): read_rtx is not available in the
compiler itself.
From-SVN: r43646
2001-06-28 23:50:09 +02:00
|
|
|
? "b %l0" : "l r15,=a(%l0); br r15");
|
|
|
|
@}
|
2001-08-18 23:02:44 +02:00
|
|
|
[(set (attr "length")
|
|
|
|
(if_then_else (lt (match_dup 0) (const_int 4096))
|
|
|
|
(const_int 4)
|
|
|
|
(const_int 6)))])
|
1997-03-25 20:26:08 +01:00
|
|
|
@end smallexample
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Constant Attributes
|
|
|
|
@subsection Constant Attributes
|
|
|
|
@cindex constant attributes
|
|
|
|
|
|
|
|
A special form of @code{define_attr}, where the expression for the
|
|
|
|
default value is a @code{const} expression, indicates an attribute that
|
|
|
|
is constant for a given run of the compiler. Constant attributes may be
|
|
|
|
used to specify which variety of processor is used. For example,
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_attr "cpu" "m88100,m88110,m88000"
|
|
|
|
(const
|
|
|
|
(cond [(symbol_ref "TARGET_88100") (const_string "m88100")
|
|
|
|
(symbol_ref "TARGET_88110") (const_string "m88110")]
|
|
|
|
(const_string "m88000"))))
|
|
|
|
|
|
|
|
(define_attr "memory" "fast,slow"
|
|
|
|
(const
|
|
|
|
(if_then_else (symbol_ref "TARGET_FAST_MEM")
|
|
|
|
(const_string "fast")
|
|
|
|
(const_string "slow"))))
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The routine generated for constant attributes has no parameters as it
|
|
|
|
does not depend on any particular insn. RTL expressions used to define
|
|
|
|
the value of a constant attribute may use the @code{symbol_ref} form,
|
|
|
|
but may not use either the @code{match_operand} form or @code{eq_attr}
|
|
|
|
forms involving insn attributes.
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
1997-03-25 20:26:08 +01:00
|
|
|
@node Delay Slots
|
|
|
|
@subsection Delay Slot Scheduling
|
|
|
|
@cindex delay slots, defining
|
|
|
|
|
|
|
|
The insn attribute mechanism can be used to specify the requirements for
|
|
|
|
delay slots, if any, on a target machine. An instruction is said to
|
|
|
|
require a @dfn{delay slot} if some instructions that are physically
|
|
|
|
after the instruction are executed as if they were located before it.
|
|
|
|
Classic examples are branch and call instructions, which often execute
|
|
|
|
the following instruction before the branch or call is performed.
|
|
|
|
|
|
|
|
On some machines, conditional branch instructions can optionally
|
|
|
|
@dfn{annul} instructions in the delay slot. This means that the
|
|
|
|
instruction will not be executed for certain branch outcomes. Both
|
|
|
|
instructions that annul if the branch is true and instructions that
|
|
|
|
annul if the branch is false are supported.
|
|
|
|
|
|
|
|
Delay slot scheduling differs from instruction scheduling in that
|
|
|
|
determining whether an instruction needs a delay slot is dependent only
|
|
|
|
on the type of instruction being generated, not on data flow between the
|
|
|
|
instructions. See the next section for a discussion of data-dependent
|
|
|
|
instruction scheduling.
|
|
|
|
|
|
|
|
@findex define_delay
|
|
|
|
The requirement of an insn needing one or more delay slots is indicated
|
|
|
|
via the @code{define_delay} expression. It has the following form:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_delay @var{test}
|
|
|
|
[@var{delay-1} @var{annul-true-1} @var{annul-false-1}
|
|
|
|
@var{delay-2} @var{annul-true-2} @var{annul-false-2}
|
|
|
|
@dots{}])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{test} is an attribute test that indicates whether this
|
|
|
|
@code{define_delay} applies to a particular insn. If so, the number of
|
|
|
|
required delay slots is determined by the length of the vector specified
|
|
|
|
as the second argument. An insn placed in delay slot @var{n} must
|
|
|
|
satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
|
|
|
|
attribute test that specifies which insns may be annulled if the branch
|
|
|
|
is true. Similarly, @var{annul-false-n} specifies which insns in the
|
|
|
|
delay slot may be annulled if the branch is false. If annulling is not
|
2001-06-25 01:04:49 +02:00
|
|
|
supported for that delay slot, @code{(nil)} should be coded.
|
1997-03-25 20:26:08 +01:00
|
|
|
|
|
|
|
For example, in the common case where branch and call insns require
|
|
|
|
a single delay slot, which may contain any insn other than a branch or
|
|
|
|
call, the following would be placed in the @file{md} file:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_delay (eq_attr "type" "branch,call")
|
|
|
|
[(eq_attr "type" "!branch,call") (nil) (nil)])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Multiple @code{define_delay} expressions may be specified. In this
|
|
|
|
case, each such expression specifies different delay slot requirements
|
|
|
|
and there must be no insn for which tests in two @code{define_delay}
|
|
|
|
expressions are both true.
|
|
|
|
|
|
|
|
For example, if we have a machine that requires one delay slot for branches
|
|
|
|
but two for calls, no delay slot can contain a branch or call insn,
|
|
|
|
and any valid insn in the delay slot for the branch can be annulled if the
|
|
|
|
branch is true, we might represent this as follows:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_delay (eq_attr "type" "branch")
|
|
|
|
[(eq_attr "type" "!branch,call")
|
|
|
|
(eq_attr "type" "!branch,call")
|
|
|
|
(nil)])
|
|
|
|
|
|
|
|
(define_delay (eq_attr "type" "call")
|
|
|
|
[(eq_attr "type" "!branch,call") (nil) (nil)
|
|
|
|
(eq_attr "type" "!branch,call") (nil) (nil)])
|
|
|
|
@end smallexample
|
|
|
|
@c the above is *still* too long. --mew 4feb93
|
|
|
|
|
2004-03-10 01:09:37 +01:00
|
|
|
@end ifset
|
|
|
|
@ifset INTERNALS
|
2002-04-30 00:34:36 +02:00
|
|
|
@node Processor pipeline description
|
|
|
|
@subsection Specifying processor pipeline description
|
|
|
|
@cindex processor pipeline description
|
|
|
|
@cindex processor functional units
|
|
|
|
@cindex instruction latency time
|
|
|
|
@cindex interlock delays
|
|
|
|
@cindex data dependence delays
|
|
|
|
@cindex reservation delays
|
|
|
|
@cindex pipeline hazard recognizer
|
|
|
|
@cindex automaton based pipeline description
|
|
|
|
@cindex regular expressions
|
|
|
|
@cindex deterministic finite state automaton
|
|
|
|
@cindex automaton based scheduler
|
|
|
|
@cindex RISC
|
|
|
|
@cindex VLIW
|
|
|
|
|
2002-08-27 20:12:24 +02:00
|
|
|
To achieve better performance, most modern processors
|
2002-04-30 00:34:36 +02:00
|
|
|
(super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
|
|
|
|
processors) have many @dfn{functional units} on which several
|
|
|
|
instructions can be executed simultaneously. An instruction starts
|
|
|
|
execution if its issue conditions are satisfied. If not, the
|
2002-08-27 20:12:24 +02:00
|
|
|
instruction is stalled until its conditions are satisfied. Such
|
2002-04-30 00:34:36 +02:00
|
|
|
@dfn{interlock (pipeline) delay} causes interruption of the fetching
|
2004-09-11 10:34:26 +02:00
|
|
|
of successor instructions (or demands nop instructions, e.g.@: for some
|
2002-04-30 00:34:36 +02:00
|
|
|
MIPS processors).
|
|
|
|
|
|
|
|
There are two major kinds of interlock delays in modern processors.
|
|
|
|
The first one is a data dependence delay determining @dfn{instruction
|
|
|
|
latency time}. The instruction execution is not started until all
|
|
|
|
source data have been evaluated by prior instructions (there are more
|
|
|
|
complex cases when the instruction execution starts even when the data
|
2002-12-17 17:47:45 +01:00
|
|
|
are not available but will be ready in given time after the
|
2002-04-30 00:34:36 +02:00
|
|
|
instruction execution start). Taking the data dependence delays into
|
|
|
|
account is simple. The data dependence (true, output, and
|
|
|
|
anti-dependence) delay between two instructions is given by a
|
|
|
|
constant. In most cases this approach is adequate. The second kind
|
|
|
|
of interlock delays is a reservation delay. The reservation delay
|
|
|
|
means that two instructions under execution will be in need of shared
|
2004-09-11 10:34:26 +02:00
|
|
|
processors resources, i.e.@: buses, internal registers, and/or
|
2002-04-30 00:34:36 +02:00
|
|
|
functional units, which are reserved for some time. Taking this kind
|
|
|
|
of delay into account is complex especially for modern @acronym{RISC}
|
|
|
|
processors.
|
|
|
|
|
|
|
|
The task of exploiting more processor parallelism is solved by an
|
2002-08-27 20:12:24 +02:00
|
|
|
instruction scheduler. For a better solution to this problem, the
|
2002-04-30 00:34:36 +02:00
|
|
|
instruction scheduler has to have an adequate description of the
|
genattr.c (struct range, [...]): Remove them.
2004-07-19 Paolo Bonzini <bonzini@gnu.org>
* genattr.c (struct range, struct function_unit,
write_units, extend_range, init_range): Remove them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
Output "#define INSN_SCHEDULING" here.
* genattrtab.c (struct range, struct function_unit_op,
struct function_unit, struct dimension, enum operator,
operate_exp, expand_units, simplify_knowing,
encode_units_mask, simplify_by_exploding,
find_and_mark_used_attributes, unmark_used_attributes,
add_values_to_cover, increment_current_value,
test_for_current_value, simplify_with_current_value,
simplify_with_current_value_aux, gen_unit,
write_unit_name, write_function_unit_info,
write_complex_function, write_toplevel_expr,
find_single_value, extend_range): Remove.
(write_attr_get): Do not handle common_av->value
being an FFS.
(struct attr_desc): Remove func_units_p and blockage_p.
(write_attr_valueq): Do not handle them.
(find_attr): Do not clear them.
(make_internal_attr): Do not initialize them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
* sched-vis.c (init_target_units, insn_print_units,
init_block_visualization, print_block_visualization,
visualize_scheduled_insns, visualize_no_unit,
visualize_stall_cycles, visualize_alloc,
visualize_free, target_units, get_visual_tbl_length,
MAX_VISUAL_LINES, INSN_LEN, n_visual_lines,
visual_tbl_line_length, visual_tbl, n_vis_no_unit,
MAX_VISUAL_NO_UNIT, vis_no_unit): Remove.
* haifa-sched.c (blockage_range, clear_units,
schedule_unit, actual_hazard, potential_hazard,
insn_unit, unit_last_insn, unit_tick,
actual_hazard_this_instance, potential_hazard,
schedule_unit, max_insn_queue_index_value): Remove.
(MAX_INSN_QUEUE_INDEX): Removed, renamed throughout to
max_insn_queue_index.
* rtl.def (DEFINE_FUNCTION_UNIT): Remove.
* doc/md.texi (Processor pipeline description): Remove
references to old pipeline descriptions.
(Automaton pipeline description): Merge with the above.
(Old pipeline description, Comparison of the two descriptions):
Remove.
* bt-load.c (migrate_btr_def): Remove references to
use_pipeline_interface.
* haifa-sched.c (insn_cost, schedule_insn,
schedule_block, advance_one_cycle, sched_init,
queue_to_ready, sched_finish): Likewise.
* modulo-sched.c (sms_schedule, advance_one_cycle,
ps_has_conflicts): Likewise.
* sched-rgn.c (init_ready): Likewise.
(debug_dependencies): Likewise, and remove an "if (1)".
* target.h (use_dfa_pipeline_interface): Remove.
* config/alpha/alpha.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arc/arc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arm/arm.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/c4x/c4x.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/frv/frv.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/i386/i386.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/ia64/ia64.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/iq2000/iq2000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/m32r/m32r.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mcore/mcore.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mips/mips.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/pa/pa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/rs6000/rs6000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/s390/s390.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sh/sh.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sparc/sparc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/v850/v850.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/xtensa/xtensa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* doc/tm.texi (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
From-SVN: r84944
2004-07-20 09:27:18 +02:00
|
|
|
processor parallelism (or @dfn{pipeline description}). GCC
|
|
|
|
machine descriptions describe processor parallelism and functional
|
|
|
|
unit reservations for groups of instructions with the aid of
|
|
|
|
@dfn{regular expressions}.
|
2002-08-27 20:12:24 +02:00
|
|
|
|
|
|
|
The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
|
2002-04-30 00:34:36 +02:00
|
|
|
figure out the possibility of the instruction issue by the processor
|
2002-08-27 20:12:24 +02:00
|
|
|
on a given simulated processor cycle. The pipeline hazard recognizer is
|
|
|
|
automatically generated from the processor pipeline description. The
|
genattr.c (struct range, [...]): Remove them.
2004-07-19 Paolo Bonzini <bonzini@gnu.org>
* genattr.c (struct range, struct function_unit,
write_units, extend_range, init_range): Remove them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
Output "#define INSN_SCHEDULING" here.
* genattrtab.c (struct range, struct function_unit_op,
struct function_unit, struct dimension, enum operator,
operate_exp, expand_units, simplify_knowing,
encode_units_mask, simplify_by_exploding,
find_and_mark_used_attributes, unmark_used_attributes,
add_values_to_cover, increment_current_value,
test_for_current_value, simplify_with_current_value,
simplify_with_current_value_aux, gen_unit,
write_unit_name, write_function_unit_info,
write_complex_function, write_toplevel_expr,
find_single_value, extend_range): Remove.
(write_attr_get): Do not handle common_av->value
being an FFS.
(struct attr_desc): Remove func_units_p and blockage_p.
(write_attr_valueq): Do not handle them.
(find_attr): Do not clear them.
(make_internal_attr): Do not initialize them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
* sched-vis.c (init_target_units, insn_print_units,
init_block_visualization, print_block_visualization,
visualize_scheduled_insns, visualize_no_unit,
visualize_stall_cycles, visualize_alloc,
visualize_free, target_units, get_visual_tbl_length,
MAX_VISUAL_LINES, INSN_LEN, n_visual_lines,
visual_tbl_line_length, visual_tbl, n_vis_no_unit,
MAX_VISUAL_NO_UNIT, vis_no_unit): Remove.
* haifa-sched.c (blockage_range, clear_units,
schedule_unit, actual_hazard, potential_hazard,
insn_unit, unit_last_insn, unit_tick,
actual_hazard_this_instance, potential_hazard,
schedule_unit, max_insn_queue_index_value): Remove.
(MAX_INSN_QUEUE_INDEX): Removed, renamed throughout to
max_insn_queue_index.
* rtl.def (DEFINE_FUNCTION_UNIT): Remove.
* doc/md.texi (Processor pipeline description): Remove
references to old pipeline descriptions.
(Automaton pipeline description): Merge with the above.
(Old pipeline description, Comparison of the two descriptions):
Remove.
* bt-load.c (migrate_btr_def): Remove references to
use_pipeline_interface.
* haifa-sched.c (insn_cost, schedule_insn,
schedule_block, advance_one_cycle, sched_init,
queue_to_ready, sched_finish): Likewise.
* modulo-sched.c (sms_schedule, advance_one_cycle,
ps_has_conflicts): Likewise.
* sched-rgn.c (init_ready): Likewise.
(debug_dependencies): Likewise, and remove an "if (1)".
* target.h (use_dfa_pipeline_interface): Remove.
* config/alpha/alpha.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arc/arc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arm/arm.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/c4x/c4x.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/frv/frv.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/i386/i386.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/ia64/ia64.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/iq2000/iq2000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/m32r/m32r.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mcore/mcore.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mips/mips.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/pa/pa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/rs6000/rs6000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/s390/s390.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sh/sh.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sparc/sparc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/v850/v850.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/xtensa/xtensa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* doc/tm.texi (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
From-SVN: r84944
2004-07-20 09:27:18 +02:00
|
|
|
pipeline hazard recognizer generated from the machine description
|
|
|
|
is based on a deterministic finite state automaton (@acronym{DFA}):
|
|
|
|
the instruction issue is possible if there is a transition from one
|
|
|
|
automaton state to another one. This algorithm is very fast, and
|
|
|
|
furthermore, its speed is not dependent on processor
|
|
|
|
complexity@footnote{However, the size of the automaton depends on
|
|
|
|
processor complexity. To limit this effect, machine descriptions
|
|
|
|
can split orthogonal parts of the machine description among several
|
|
|
|
automata: but then, since each of these must be stepped independently,
|
|
|
|
this does cause a small decrease in the algorithm's performance.}.
|
2002-04-30 00:34:36 +02:00
|
|
|
|
|
|
|
@cindex automaton based pipeline description
|
genattr.c (struct range, [...]): Remove them.
2004-07-19 Paolo Bonzini <bonzini@gnu.org>
* genattr.c (struct range, struct function_unit,
write_units, extend_range, init_range): Remove them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
Output "#define INSN_SCHEDULING" here.
* genattrtab.c (struct range, struct function_unit_op,
struct function_unit, struct dimension, enum operator,
operate_exp, expand_units, simplify_knowing,
encode_units_mask, simplify_by_exploding,
find_and_mark_used_attributes, unmark_used_attributes,
add_values_to_cover, increment_current_value,
test_for_current_value, simplify_with_current_value,
simplify_with_current_value_aux, gen_unit,
write_unit_name, write_function_unit_info,
write_complex_function, write_toplevel_expr,
find_single_value, extend_range): Remove.
(write_attr_get): Do not handle common_av->value
being an FFS.
(struct attr_desc): Remove func_units_p and blockage_p.
(write_attr_valueq): Do not handle them.
(find_attr): Do not clear them.
(make_internal_attr): Do not initialize them.
(main): Remove code dealing with DEFINE_FUNCTION_UNIT.
* sched-vis.c (init_target_units, insn_print_units,
init_block_visualization, print_block_visualization,
visualize_scheduled_insns, visualize_no_unit,
visualize_stall_cycles, visualize_alloc,
visualize_free, target_units, get_visual_tbl_length,
MAX_VISUAL_LINES, INSN_LEN, n_visual_lines,
visual_tbl_line_length, visual_tbl, n_vis_no_unit,
MAX_VISUAL_NO_UNIT, vis_no_unit): Remove.
* haifa-sched.c (blockage_range, clear_units,
schedule_unit, actual_hazard, potential_hazard,
insn_unit, unit_last_insn, unit_tick,
actual_hazard_this_instance, potential_hazard,
schedule_unit, max_insn_queue_index_value): Remove.
(MAX_INSN_QUEUE_INDEX): Removed, renamed throughout to
max_insn_queue_index.
* rtl.def (DEFINE_FUNCTION_UNIT): Remove.
* doc/md.texi (Processor pipeline description): Remove
references to old pipeline descriptions.
(Automaton pipeline description): Merge with the above.
(Old pipeline description, Comparison of the two descriptions):
Remove.
* bt-load.c (migrate_btr_def): Remove references to
use_pipeline_interface.
* haifa-sched.c (insn_cost, schedule_insn,
schedule_block, advance_one_cycle, sched_init,
queue_to_ready, sched_finish): Likewise.
* modulo-sched.c (sms_schedule, advance_one_cycle,
ps_has_conflicts): Likewise.
* sched-rgn.c (init_ready): Likewise.
(debug_dependencies): Likewise, and remove an "if (1)".
* target.h (use_dfa_pipeline_interface): Remove.
* config/alpha/alpha.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arc/arc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/arm/arm.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/c4x/c4x.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/frv/frv.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/i386/i386.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/ia64/ia64.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/iq2000/iq2000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/m32r/m32r.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mcore/mcore.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/mips/mips.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/pa/pa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/rs6000/rs6000.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/s390/s390.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sh/sh.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/sparc/sparc.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/v850/v850.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* config/xtensa/xtensa.c (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
* doc/tm.texi (TARGET_USE_DFA_PIPELINE_INTERFACE): Remove.
From-SVN: r84944
2004-07-20 09:27:18 +02:00
|
|
|
The rest of this section describes the directives that constitute
|
|
|
|
an automaton-based processor pipeline description. The order of
|
|
|
|
these constructions within the machine description file is not
|
|
|
|
important.
|
2002-04-30 00:34:36 +02:00
|
|
|
|
|
|
|
@findex define_automaton
|
|
|
|
@cindex pipeline hazard recognizer
|
|
|
|
The following optional construction describes names of automata
|
|
|
|
generated and used for the pipeline hazards recognition. Sometimes
|
|
|
|
the generated finite state automaton used by the pipeline hazard
|
2002-08-27 20:12:24 +02:00
|
|
|
recognizer is large. If we use more than one automaton and bind functional
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cpp.texi, doc/extend.texi,
doc/frontends.texi, doc/gcov.texi, doc/gty.texi, doc/install.texi,
doc/invoke.texi, doc/libgcc.texi, doc/md.texi, doc/rtl.texi,
doc/sourcebuild.texi, doc/standards.texi, doc/tm.texi,
doc/trouble.texi: Remove trailing whitespace.
From-SVN: r76098
2004-01-18 12:57:17 +01:00
|
|
|
units to the automata, the total size of the automata is usually
|
2002-04-30 00:34:36 +02:00
|
|
|
less than the size of the single automaton. If there is no one such
|
|
|
|
construction, only one finite state automaton is generated.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_automaton @var{automata-names})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{automata-names} is a string giving names of the automata. The
|
|
|
|
names are separated by commas. All the automata should have unique names.
|
2003-05-14 14:40:57 +02:00
|
|
|
The automaton name is used in the constructions @code{define_cpu_unit} and
|
2002-04-30 00:34:36 +02:00
|
|
|
@code{define_query_cpu_unit}.
|
|
|
|
|
|
|
|
@findex define_cpu_unit
|
|
|
|
@cindex processor functional units
|
2003-05-14 14:40:57 +02:00
|
|
|
Each processor functional unit used in the description of instruction
|
2002-04-30 00:34:36 +02:00
|
|
|
reservations should be described by the following construction.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_cpu_unit @var{unit-names} [@var{automaton-name}])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{unit-names} is a string giving the names of the functional units
|
|
|
|
separated by commas. Don't use name @samp{nothing}, it is reserved
|
|
|
|
for other goals.
|
|
|
|
|
2002-08-27 20:12:24 +02:00
|
|
|
@var{automaton-name} is a string giving the name of the automaton with
|
2002-04-30 00:34:36 +02:00
|
|
|
which the unit is bound. The automaton should be described in
|
|
|
|
construction @code{define_automaton}. You should give
|
|
|
|
@dfn{automaton-name}, if there is a defined automaton.
|
|
|
|
|
2003-01-10 00:15:34 +01:00
|
|
|
The assignment of units to automata are constrained by the uses of the
|
|
|
|
units in insn reservations. The most important constraint is: if a
|
|
|
|
unit reservation is present on a particular cycle of an alternative
|
|
|
|
for an insn reservation, then some unit from the same automaton must
|
|
|
|
be present on the same cycle for the other alternatives of the insn
|
|
|
|
reservation. The rest of the constraints are mentioned in the
|
|
|
|
description of the subsequent constructions.
|
|
|
|
|
2002-04-30 00:34:36 +02:00
|
|
|
@findex define_query_cpu_unit
|
|
|
|
@cindex querying function unit reservations
|
|
|
|
The following construction describes CPU functional units analogously
|
2003-01-10 00:15:34 +01:00
|
|
|
to @code{define_cpu_unit}. The reservation of such units can be
|
|
|
|
queried for an automaton state. The instruction scheduler never
|
|
|
|
queries reservation of functional units for given automaton state. So
|
|
|
|
as a rule, you don't need this construction. This construction could
|
2004-09-11 10:34:26 +02:00
|
|
|
be used for future code generation goals (e.g.@: to generate
|
2003-01-10 00:15:34 +01:00
|
|
|
@acronym{VLIW} insn templates).
|
2002-04-30 00:34:36 +02:00
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{unit-names} is a string giving names of the functional units
|
|
|
|
separated by commas.
|
|
|
|
|
2002-08-27 20:12:24 +02:00
|
|
|
@var{automaton-name} is a string giving the name of the automaton with
|
2002-04-30 00:34:36 +02:00
|
|
|
which the unit is bound.
|
|
|
|
|
|
|
|
@findex define_insn_reservation
|
|
|
|
@cindex instruction latency time
|
|
|
|
@cindex regular expressions
|
|
|
|
@cindex data bypass
|
2002-08-27 20:12:24 +02:00
|
|
|
The following construction is the major one to describe pipeline
|
2002-04-30 00:34:36 +02:00
|
|
|
characteristics of an instruction.
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn_reservation @var{insn-name} @var{default_latency}
|
|
|
|
@var{condition} @var{regexp})
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@var{default_latency} is a number giving latency time of the
|
|
|
|
instruction. There is an important difference between the old
|
|
|
|
description and the automaton based pipeline description. The latency
|
|
|
|
time is used for all dependencies when we use the old description. In
|
2002-08-27 20:12:24 +02:00
|
|
|
the automaton based pipeline description, the given latency time is only
|
|
|
|
used for true dependencies. The cost of anti-dependencies is always
|
2002-04-30 00:34:36 +02:00
|
|
|
zero and the cost of output dependencies is the difference between
|
|
|
|
latency times of the producing and consuming insns (if the difference
|
2002-08-27 20:12:24 +02:00
|
|
|
is negative, the cost is considered to be zero). You can always
|
|
|
|
change the default costs for any description by using the target hook
|
2002-04-30 00:34:36 +02:00
|
|
|
@code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
|
|
|
|
|
2003-06-03 08:56:42 +02:00
|
|
|
@var{insn-name} is a string giving the internal name of the insn. The
|
2002-04-30 00:34:36 +02:00
|
|
|
internal names are used in constructions @code{define_bypass} and in
|
|
|
|
the automaton description file generated for debugging. The internal
|
2002-08-27 20:12:24 +02:00
|
|
|
name has nothing in common with the names in @code{define_insn}. It is a
|
2002-04-30 00:34:36 +02:00
|
|
|
good practice to use insn classes described in the processor manual.
|
|
|
|
|
|
|
|
@var{condition} defines what RTL insns are described by this
|
|
|
|
construction. You should remember that you will be in trouble if
|
|
|
|
@var{condition} for two or more different
|
|
|
|
@code{define_insn_reservation} constructions is TRUE for an insn. In
|
|
|
|
this case what reservation will be used for the insn is not defined.
|
|
|
|
Such cases are not checked during generation of the pipeline hazards
|
|
|
|
recognizer because in general recognizing that two conditions may have
|
|
|
|
the same value is quite difficult (especially if the conditions
|
|
|
|
contain @code{symbol_ref}). It is also not checked during the
|
|
|
|
pipeline hazard recognizer work because it would slow down the
|
|
|
|
recognizer considerably.
|
|
|
|
|
2002-08-27 20:12:24 +02:00
|
|
|
@var{regexp} is a string describing the reservation of the cpu's functional
|
2002-04-30 00:34:36 +02:00
|
|
|
units by the instruction. The reservations are described by a regular
|
|
|
|
expression according to the following syntax:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
regexp = regexp "," oneof
|
|
|
|
| oneof
|
|
|
|
|
|
|
|
oneof = oneof "|" allof
|
|
|
|
| allof
|
|
|
|
|
|
|
|
allof = allof "+" repeat
|
|
|
|
| repeat
|
c-tree.texi, [...]: Remove trailing whitespace.
* doc/c-tree.texi, doc/cpp.texi, doc/extend.texi,
doc/frontends.texi, doc/gcov.texi, doc/gty.texi, doc/install.texi,
doc/invoke.texi, doc/libgcc.texi, doc/md.texi, doc/rtl.texi,
doc/sourcebuild.texi, doc/standards.texi, doc/tm.texi,
doc/trouble.texi: Remove trailing whitespace.
From-SVN: r76098
2004-01-18 12:57:17 +01:00
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2002-04-30 00:34:36 +02:00
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repeat = element "*" number
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| element
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element = cpu_function_unit_name
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| reservation_name
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| result_name
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| "nothing"
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| "(" regexp ")"
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@end smallexample
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@itemize @bullet
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@item
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@samp{,} is used for describing the start of the next cycle in
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the reservation.
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@item
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@samp{|} is used for describing a reservation described by the first
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regular expression @strong{or} a reservation described by the second
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regular expression @strong{or} etc.
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@item
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@samp{+} is used for describing a reservation described by the first
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regular expression @strong{and} a reservation described by the
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second regular expression @strong{and} etc.
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@item
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@samp{*} is used for convenience and simply means a sequence in which
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the regular expression are repeated @var{number} times with cycle
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advancing (see @samp{,}).
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@item
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@samp{cpu_function_unit_name} denotes reservation of the named
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functional unit.
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@item
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@samp{reservation_name} --- see description of construction
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@samp{define_reservation}.
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@item
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@samp{nothing} denotes no unit reservations.
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@end itemize
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@findex define_reservation
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Sometimes unit reservations for different insns contain common parts.
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In such case, you can simplify the pipeline description by describing
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the common part by the following construction
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@smallexample
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(define_reservation @var{reservation-name} @var{regexp})
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@end smallexample
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@var{reservation-name} is a string giving name of @var{regexp}.
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Functional unit names and reservation names are in the same name
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space. So the reservation names should be different from the
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2003-06-03 08:56:42 +02:00
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functional unit names and can not be the reserved name @samp{nothing}.
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2002-04-30 00:34:36 +02:00
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@findex define_bypass
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@cindex instruction latency time
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@cindex data bypass
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The following construction is used to describe exceptions in the
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latency time for given instruction pair. This is so called bypasses.
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@smallexample
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(define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
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[@var{guard}])
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@end smallexample
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@var{number} defines when the result generated by the instructions
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given in string @var{out_insn_names} will be ready for the
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instructions given in string @var{in_insn_names}. The instructions in
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the string are separated by commas.
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2002-08-27 20:12:24 +02:00
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@var{guard} is an optional string giving the name of a C function which
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2002-04-30 00:34:36 +02:00
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defines an additional guard for the bypass. The function will get the
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two insns as parameters. If the function returns zero the bypass will
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be ignored for this case. The additional guard is necessary to
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2004-09-11 10:34:26 +02:00
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recognize complicated bypasses, e.g.@: when the consumer is only an address
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2002-04-30 00:34:36 +02:00
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of insn @samp{store} (not a stored value).
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@findex exclusion_set
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@findex presence_set
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@findex final_presence_set
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2002-04-30 00:34:36 +02:00
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@findex absence_set
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2003-01-10 00:15:34 +01:00
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@findex final_absence_set
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2002-04-30 00:34:36 +02:00
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@cindex VLIW
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@cindex RISC
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2003-06-03 08:56:42 +02:00
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The following five constructions are usually used to describe
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@acronym{VLIW} processors, or more precisely, to describe a placement
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of small instructions into @acronym{VLIW} instruction slots. They
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can be used for @acronym{RISC} processors, too.
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2002-04-30 00:34:36 +02:00
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@smallexample
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(exclusion_set @var{unit-names} @var{unit-names})
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(presence_set @var{unit-names} @var{patterns})
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(final_presence_set @var{unit-names} @var{patterns})
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(absence_set @var{unit-names} @var{patterns})
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(final_absence_set @var{unit-names} @var{patterns})
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2002-04-30 00:34:36 +02:00
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@end smallexample
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@var{unit-names} is a string giving names of functional units
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separated by commas.
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2003-01-10 00:15:34 +01:00
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@var{patterns} is a string giving patterns of functional units
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2005-04-15 12:24:13 +02:00
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separated by comma. Currently pattern is one unit or units
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2003-01-10 00:15:34 +01:00
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separated by white-spaces.
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2002-04-30 00:34:36 +02:00
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The first construction (@samp{exclusion_set}) means that each
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functional unit in the first string can not be reserved simultaneously
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with a unit whose name is in the second string and vice versa. For
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example, the construction is useful for describing processors
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2004-09-11 10:34:26 +02:00
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(e.g.@: some SPARC processors) with a fully pipelined floating point
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2002-04-30 00:34:36 +02:00
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functional unit which can execute simultaneously only single floating
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point insns or only double floating point insns.
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The second construction (@samp{presence_set}) means that each
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functional unit in the first string can not be reserved unless at
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2003-01-10 00:15:34 +01:00
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least one of pattern of units whose names are in the second string is
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reserved. This is an asymmetric relation. For example, it is useful
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for description that @acronym{VLIW} @samp{slot1} is reserved after
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@samp{slot0} reservation. We could describe it by the following
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construction
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@smallexample
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(presence_set "slot1" "slot0")
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@end smallexample
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Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
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reservation. In this case we could write
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@smallexample
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(presence_set "slot1" "slot0 b0")
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@end smallexample
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The third construction (@samp{final_presence_set}) is analogous to
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@samp{presence_set}. The difference between them is when checking is
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done. When an instruction is issued in given automaton state
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reflecting all current and planned unit reservations, the automaton
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state is changed. The first state is a source state, the second one
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is a result state. Checking for @samp{presence_set} is done on the
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source state reservation, checking for @samp{final_presence_set} is
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done on the result reservation. This construction is useful to
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describe a reservation which is actually two subsequent reservations.
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For example, if we use
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@smallexample
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(presence_set "slot1" "slot0")
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@end smallexample
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the following insn will be never issued (because @samp{slot1} requires
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@samp{slot0} which is absent in the source state).
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@smallexample
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(define_reservation "insn_and_nop" "slot0 + slot1")
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@end smallexample
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but it can be issued if we use analogous @samp{final_presence_set}.
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The forth construction (@samp{absence_set}) means that each functional
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unit in the first string can be reserved only if each pattern of units
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whose names are in the second string is not reserved. This is an
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asymmetric relation (actually @samp{exclusion_set} is analogous to
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2006-09-15 17:27:43 +02:00
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this one but it is symmetric). For example it might be useful in a
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@acronym{VLIW} description to say that @samp{slot0} cannot be reserved
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after either @samp{slot1} or @samp{slot2} have been reserved. This
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can be described as:
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2003-01-10 00:15:34 +01:00
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@smallexample
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2006-09-15 17:27:43 +02:00
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(absence_set "slot0" "slot1, slot2")
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2003-01-10 00:15:34 +01:00
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@end smallexample
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Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
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are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
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this case we could write
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@smallexample
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(absence_set "slot2" "slot0 b0, slot1 b1")
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@end smallexample
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2002-04-30 00:34:36 +02:00
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2002-08-27 20:12:24 +02:00
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All functional units mentioned in a set should belong to the same
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2002-04-30 00:34:36 +02:00
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automaton.
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2003-01-10 00:15:34 +01:00
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The last construction (@samp{final_absence_set}) is analogous to
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@samp{absence_set} but checking is done on the result (state)
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reservation. See comments for @samp{final_presence_set}.
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2002-04-30 00:34:36 +02:00
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@findex automata_option
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@cindex deterministic finite state automaton
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@cindex nondeterministic finite state automaton
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@cindex finite state automaton minimization
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You can control the generator of the pipeline hazard recognizer with
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the following construction.
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@smallexample
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(automata_option @var{options})
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@end smallexample
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@var{options} is a string giving options which affect the generated
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code. Currently there are the following options:
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@itemize @bullet
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@item
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@dfn{no-minimization} makes no minimization of the automaton. This is
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2003-01-10 00:15:34 +01:00
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only worth to do when we are debugging the description and need to
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look more accurately at reservations of states.
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2002-04-30 00:34:36 +02:00
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@item
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2007-01-08 23:24:13 +01:00
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@dfn{time} means printing time statistics about the generation of
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automata.
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@item
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@dfn{stats} means printing statistics about the generated automata
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such as the number of DFA states, NDFA states and arcs.
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2002-06-18 18:18:23 +02:00
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@item
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@dfn{v} means a generation of the file describing the result automata.
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The file has suffix @samp{.dfa} and can be used for the description
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verification and debugging.
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@item
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@dfn{w} means a generation of warning instead of error for
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non-critical errors.
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2002-04-30 00:34:36 +02:00
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@item
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@dfn{ndfa} makes nondeterministic finite state automata. This affects
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the treatment of operator @samp{|} in the regular expressions. The
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usual treatment of the operator is to try the first alternative and,
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if the reservation is not possible, the second alternative. The
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nondeterministic treatment means trying all alternatives, some of them
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2005-04-01 01:26:33 +02:00
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may be rejected by reservations in the subsequent insns.
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2004-01-13 20:52:24 +01:00
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@item
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@dfn{progress} means output of a progress bar showing how many states
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were generated so far for automaton being processed. This is useful
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during debugging a @acronym{DFA} description. If you see too many
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generated states, you could interrupt the generator of the pipeline
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hazard recognizer and try to figure out a reason for generation of the
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huge automaton.
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2002-04-30 00:34:36 +02:00
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@end itemize
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As an example, consider a superscalar @acronym{RISC} machine which can
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issue three insns (two integer insns and one floating point insn) on
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the cycle but can finish only two insns. To describe this, we define
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the following functional units.
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@smallexample
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(define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
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2002-08-27 20:12:24 +02:00
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(define_cpu_unit "port0, port1")
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2002-04-30 00:34:36 +02:00
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@end smallexample
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All simple integer insns can be executed in any integer pipeline and
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their result is ready in two cycles. The simple integer insns are
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issued into the first pipeline unless it is reserved, otherwise they
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are issued into the second pipeline. Integer division and
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multiplication insns can be executed only in the second integer
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pipeline and their results are ready correspondingly in 8 and 4
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2004-09-11 10:34:26 +02:00
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cycles. The integer division is not pipelined, i.e.@: the subsequent
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2002-04-30 00:34:36 +02:00
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integer division insn can not be issued until the current division
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insn finished. Floating point insns are fully pipelined and their
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2002-08-27 20:12:24 +02:00
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results are ready in 3 cycles. Where the result of a floating point
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insn is used by an integer insn, an additional delay of one cycle is
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incurred. To describe all of this we could specify
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2002-04-30 00:34:36 +02:00
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@smallexample
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(define_cpu_unit "div")
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2003-05-31 09:43:47 +02:00
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(define_insn_reservation "simple" 2 (eq_attr "type" "int")
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2002-08-27 20:12:24 +02:00
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"(i0_pipeline | i1_pipeline), (port0 | port1)")
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2002-04-30 00:34:36 +02:00
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2003-05-31 09:43:47 +02:00
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(define_insn_reservation "mult" 4 (eq_attr "type" "mult")
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2002-08-27 20:12:24 +02:00
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"i1_pipeline, nothing*2, (port0 | port1)")
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2002-04-30 00:34:36 +02:00
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2003-05-31 09:43:47 +02:00
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(define_insn_reservation "div" 8 (eq_attr "type" "div")
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2002-08-27 20:12:24 +02:00
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"i1_pipeline, div*7, div + (port0 | port1)")
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2002-04-30 00:34:36 +02:00
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2003-05-31 09:43:47 +02:00
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(define_insn_reservation "float" 3 (eq_attr "type" "float")
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2002-08-27 20:12:24 +02:00
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"f_pipeline, nothing, (port0 | port1))
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2002-04-30 00:34:36 +02:00
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2002-08-27 20:12:24 +02:00
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(define_bypass 4 "float" "simple,mult,div")
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2002-04-30 00:34:36 +02:00
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@end smallexample
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To simplify the description we could describe the following reservation
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@smallexample
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(define_reservation "finish" "port0|port1")
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@end smallexample
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and use it in all @code{define_insn_reservation} as in the following
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construction
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@smallexample
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2003-05-31 09:43:47 +02:00
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(define_insn_reservation "simple" 2 (eq_attr "type" "int")
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2002-04-30 00:34:36 +02:00
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"(i0_pipeline | i1_pipeline), finish")
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@end smallexample
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2004-03-10 01:09:37 +01:00
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@end ifset
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@ifset INTERNALS
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rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
|
|
|
@node Conditional Execution
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|
@section Conditional Execution
|
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|
@cindex conditional execution
|
|
|
|
@cindex predication
|
|
|
|
|
|
|
|
A number of architectures provide for some form of conditional
|
|
|
|
execution, or predication. The hallmark of this feature is the
|
|
|
|
ability to nullify most of the instructions in the instruction set.
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|
When the instruction set is large and not entirely symmetric, it
|
|
|
|
can be quite tedious to describe these forms directly in the
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|
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|
@file{.md} file. An alternative is the @code{define_cond_exec} template.
|
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@findex define_cond_exec
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@smallexample
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(define_cond_exec
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[@var{predicate-pattern}]
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"@var{condition}"
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
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|
"@var{output-template}")
|
rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
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@end smallexample
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@var{predicate-pattern} is the condition that must be true for the
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insn to be executed at runtime and should match a relational operator.
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One can use @code{match_operator} to match several relational operators
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at once. Any @code{match_operand} operands must have no more than one
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alternative.
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@var{condition} is a C expression that must be true for the generated
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pattern to match.
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@findex current_insn_predicate
|
c-tree.texi, [...]: Use more logical markup.
* doc/c-tree.texi, doc/contrib.texi, doc/extend.texi,
doc/gcc.texi, doc/gcov.texi, doc/install-old.texi,
doc/invoke.texi, doc/md.texi, doc/rtl.texi, doc/tm.texi: Use more
logical markup. Use TeX quotes and dashes. Use @dots{} and
@minus{}. Avoid spaces inside @var. Update last modification
date in gcc.texi.
* doc/gcc.1, doc/gcov.1: Regenerate.
From-SVN: r43369
2001-06-14 13:08:04 +02:00
|
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|
@var{output-template} is a string similar to the @code{define_insn}
|
rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
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|
output template (@pxref{Output Template}), except that the @samp{*}
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|
and @samp{@@} special cases do not apply. This is only useful if the
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assembly text for the predicate is a simple prefix to the main insn.
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In order to handle the general case, there is a global variable
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@code{current_insn_predicate} that will contain the entire predicate
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if the current insn is predicated, and will otherwise be @code{NULL}.
|
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|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
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When @code{define_cond_exec} is used, an implicit reference to
|
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the @code{predicable} instruction attribute is made.
|
2001-06-27 02:04:39 +02:00
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@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
|
rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
|
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|
exactly two elements in its @var{list-of-values}). Further, it must
|
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|
not be used with complex expressions. That is, the default and all
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
uses in the insns must be a simple constant, not dependent on the
|
rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
|
|
|
alternative or anything else.
|
|
|
|
|
c-tree.texi, [...]: Remove trailing whitespace.
* c-tree.texi, contrib.texi, cpp.texi, extend.texi, gcc.texi,
gcov.texi, install.texi, md.texi, objc.texi, rtl.texi, tm.texi:
Remove trailing whitespace.
From-SVN: r42678
2001-05-28 22:57:50 +02:00
|
|
|
For each @code{define_insn} for which the @code{predicable}
|
rtl.def (DEFINE_COND_EXEC): New.
* rtl.def (DEFINE_COND_EXEC): New.
* md.texi: Document it.
* gensupport.c (input_file): Remove.
(struct queue_elem): Add lineno.
(rtx_ready_queue): Remove.
(errors): New.
(predicable_default): New.
(predicable_true, predicable_false): New.
(define_attr_queue, define_attr_tail): New.
(define_insn_queue, define_insn_tail): New.
(define_cond_exec_queue, define_cond_exec_tail): New.
(other_queue, other_tail): New.
(queue_pattern): New.
(process_rtx): Add patterns to the appropriate queues.
(is_predicable, identify_predicable_attribute): New.
(n_alternatives, collect_insn_data): New.
(alter_predicate_for_insn, alter_test_for_insn): New.
(shift_output_template, alter_output_for_insn): New.
(process_one_cond_exec, process_define_cond_exec): New.
(init_md_reader): Read the entire file. Process define_cond_exec.
(read_md_rtx): Return elements from the queues.
From-SVN: r33751
2000-05-07 02:48:53 +02:00
|
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|
attribute is true, a new @code{define_insn} pattern will be
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generated that matches a predicated version of the instruction.
|
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|
For example,
|
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@smallexample
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(define_insn "addsi"
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[(set (match_operand:SI 0 "register_operand" "r")
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(plus:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))]
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"@var{test1}"
|
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"add %2,%1,%0")
|
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(define_cond_exec
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[(ne (match_operand:CC 0 "register_operand" "c")
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(const_int 0))]
|
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"@var{test2}"
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"(%0)")
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@end smallexample
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@noindent
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generates a new pattern
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@smallexample
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(define_insn ""
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[(cond_exec
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(ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
|
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(set (match_operand:SI 0 "register_operand" "r")
|
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(plus:SI (match_operand:SI 1 "register_operand" "r")
|
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(match_operand:SI 2 "register_operand" "r"))))]
|
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"(@var{test2}) && (@var{test1})"
|
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"(%3) add %2,%1,%0")
|
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@end smallexample
|
2000-11-22 02:22:02 +01:00
|
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|
2004-03-10 01:09:37 +01:00
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@end ifset
|
|
|
|
@ifset INTERNALS
|
2000-11-22 02:22:02 +01:00
|
|
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@node Constant Definitions
|
|
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|
@section Constant Definitions
|
|
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@cindex constant definitions
|
|
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|
@findex define_constants
|
|
|
|
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|
|
|
Using literal constants inside instruction patterns reduces legibility and
|
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|
|
can be a maintenance problem.
|
|
|
|
|
|
|
|
To overcome this problem, you may use the @code{define_constants}
|
|
|
|
expression. It contains a vector of name-value pairs. From that
|
|
|
|
point on, wherever any of the names appears in the MD file, it is as
|
|
|
|
if the corresponding value had been written instead. You may use
|
|
|
|
@code{define_constants} multiple times; each appearance adds more
|
|
|
|
constants to the table. It is an error to redefine a constant with
|
|
|
|
a different value.
|
|
|
|
|
|
|
|
To come back to the a29k load multiple example, instead of
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_insn ""
|
|
|
|
[(match_parallel 0 "load_multiple_operation"
|
|
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
|
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
|
|
|
(use (reg:SI 179))
|
|
|
|
(clobber (reg:SI 179))])]
|
|
|
|
""
|
|
|
|
"loadm 0,0,%1,%2")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
You could write:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
(define_constants [
|
|
|
|
(R_BP 177)
|
|
|
|
(R_FC 178)
|
|
|
|
(R_CR 179)
|
|
|
|
(R_Q 180)
|
|
|
|
])
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
[(match_parallel 0 "load_multiple_operation"
|
|
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
|
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
|
|
|
(use (reg:SI R_CR))
|
|
|
|
(clobber (reg:SI R_CR))])]
|
|
|
|
""
|
|
|
|
"loadm 0,0,%1,%2")
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The constants that are defined with a define_constant are also output
|
|
|
|
in the insn-codes.h header file as #defines.
|
Separate user and internals manuals.
* Makefile.in (info, $(docdir)/gcc.info, dvi, gcc.dvi): Update
dependencies.
($(docdir)/gccint.info, gccint.dvi): New targets.
(maintainer-clean, install-info, uninstall): Update.
* doc/.cvsignore: Add gccint.info*.
* doc/include/gcc-common.texi: New file.
* doc/gcc.texi: Use it. Adjust to be a user-only manual. Put
copyright notice in a macro. Don't include ISBN unless FSFPRINT
is defined.
* doc/gccint.texi: New file.
* doc/configfiles.texi, doc/extend.texi, doc/invoke.texi,
doc/md.texi, doc/passes.texi, doc/tm.texi, doc/trouble.texi:
Update for separate user and internals manuals.
f:
* g77.texi, invoke.texi: Update links to GCC manual.
java:
* gcj.texi: Update link to GCC manual.
From-SVN: r48119
2001-12-17 20:20:05 +01:00
|
|
|
@end ifset
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
@ifset INTERNALS
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
@node Iterators
|
|
|
|
@section Iterators
|
|
|
|
@cindex iterators in @file{.md} files
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
|
|
|
|
Ports often need to define similar patterns for more than one machine
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
mode or for more than one rtx code. GCC provides some simple iterator
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
facilities to make this process easier.
|
|
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|
@menu
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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|
* Mode Iterators:: Generating variations of patterns for different modes.
|
|
|
|
* Code Iterators:: Doing the same for codes.
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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|
@end menu
|
|
|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
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@node Mode Iterators
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@subsection Mode Iterators
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|
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@cindex mode iterators in @file{.md} files
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
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|
|
|
|
|
Ports often need to define similar patterns for two or more different modes.
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For example:
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@itemize @bullet
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@item
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If a processor has hardware support for both single and double
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floating-point arithmetic, the @code{SFmode} patterns tend to be
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very similar to the @code{DFmode} ones.
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@item
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If a port uses @code{SImode} pointers in one configuration and
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@code{DImode} pointers in another, it will usually have very similar
|
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@code{SImode} and @code{DImode} patterns for manipulating pointers.
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@end itemize
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|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
Mode iterators allow several patterns to be instantiated from one
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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|
@file{.md} file template. They can be used with any type of
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rtx-based construct, such as a @code{define_insn},
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@code{define_split}, or @code{define_peephole2}.
|
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|
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@menu
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
* Defining Mode Iterators:: Defining a new mode iterator.
|
|
|
|
* Substitutions:: Combining mode iterators with substitutions
|
|
|
|
* Examples:: Examples
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
@end menu
|
|
|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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@node Defining Mode Iterators
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@subsubsection Defining Mode Iterators
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@findex define_mode_iterator
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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The syntax for defining a mode iterator is:
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@end smallexample
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This allows subsequent @file{.md} file constructs to use the mode suffix
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@code{:@var{name}}. Every construct that does so will be expanded
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@var{n} times, once with every use of @code{:@var{name}} replaced by
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@code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
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and so on. In the expansion for a particular @var{modei}, every
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C condition will also require that @var{condi} be true.
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For example:
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@end smallexample
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defines a new mode suffix @code{:P}. Every construct that uses
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@code{:P} will be expanded twice, once with every @code{:P} replaced
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by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
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The @code{:SI} version will only apply if @code{Pmode == SImode} and
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the @code{:DI} version will only apply if @code{Pmode == DImode}.
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As with other @file{.md} conditions, an empty string is treated
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as ``always true''. @code{(@var{mode} "")} can also be abbreviated
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to @code{@var{mode}}. For example:
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@end smallexample
|
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means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
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but that the @code{:SI} expansion has no such constraint.
|
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|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
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|
Iterators are applied in the order they are defined. This can be
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|
significant if two iterators are used in a construct that requires
|
2005-05-11 00:40:37 +02:00
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|
substitutions. @xref{Substitutions}.
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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2005-05-11 00:40:37 +02:00
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@node Substitutions
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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@subsubsection Substitution in Mode Iterators
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@findex define_mode_attr
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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If an @file{.md} file construct uses mode iterators, each version of the
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2005-05-11 00:40:37 +02:00
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construct will often need slightly different strings or modes. For
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example:
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@itemize @bullet
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@item
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When a @code{define_expand} defines several @code{add@var{m}3} patterns
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(@pxref{Standard Names}), each expander will need to use the
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appropriate mode name for @var{m}.
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@item
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When a @code{define_insn} defines several instruction patterns,
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each instruction will often use a different assembler mnemonic.
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2005-05-11 00:40:37 +02:00
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@item
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When a @code{define_insn} requires operands with different modes,
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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using an iterator for one of the operand modes usually requires a specific
|
2005-05-11 00:40:37 +02:00
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mode for the other operand(s).
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@end itemize
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GCC supports such variations through a system of ``mode attributes''.
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There are two standard attributes: @code{mode}, which is the name of
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the mode in lower case, and @code{MODE}, which is the same thing in
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upper case. You can define other attributes using:
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@smallexample
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(define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
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@end smallexample
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where @var{name} is the name of the attribute and @var{valuei}
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is the value associated with @var{modei}.
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
|
2005-05-11 00:40:37 +02:00
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each string and mode in the pattern for sequences of the form
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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@code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
|
2005-05-11 00:40:37 +02:00
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mode attribute. If the attribute is defined for @var{mode}, the whole
|
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@code{<...>} sequence will be replaced by the appropriate attribute
|
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value.
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
|
|
|
|
|
|
|
For example, suppose an @file{.md} file has:
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|
|
|
|
|
|
|
@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
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|
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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(define_mode_attr load [(SI "lw") (DI "ld")])
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@end smallexample
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If one of the patterns that uses @code{:P} contains the string
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@code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
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will use @code{"lw\t%0,%1"} and the @code{DI} version will use
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@code{"ld\t%0,%1"}.
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2005-05-11 00:40:37 +02:00
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Here is an example of using an attribute for a mode:
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator LONG [SI DI])
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2005-05-11 00:40:37 +02:00
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(define_mode_attr SHORT [(SI "HI") (DI "SI")])
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(define_insn ...
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(sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
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@end smallexample
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|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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The @code{@var{iterator}:} prefix may be omitted, in which case the
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substitution will be attempted for every iterator expansion.
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@node Examples
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
@subsubsection Mode Iterator Examples
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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Here is an example from the MIPS port. It defines the following
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modes and attributes (among others):
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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(define_mode_attr d [(SI "") (DI "d")])
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@end smallexample
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and uses the following template to define both @code{subsi3}
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and @code{subdi3}:
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@smallexample
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(define_insn "sub<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(minus:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))]
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""
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"<d>subu\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "<MODE>")])
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@end smallexample
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This is exactly equivalent to:
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@smallexample
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(minus:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))]
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""
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"subu\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(minus:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "register_operand" "d")))]
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""
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"dsubu\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "DI")])
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@end smallexample
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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@node Code Iterators
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@subsection Code Iterators
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@cindex code iterators in @file{.md} files
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@findex define_code_iterator
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@findex define_code_attr
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
|
read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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The construct:
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@smallexample
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_code_iterator @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@end smallexample
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defines a pseudo rtx code @var{name} that can be instantiated as
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@var{codei} if condition @var{condi} is true. Each @var{codei}
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must have the same rtx format. @xref{RTL Classes}.
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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As with mode iterators, each pattern that uses @var{name} will be
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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expanded @var{n} times, once with all uses of @var{name} replaced by
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@var{code1}, once with all uses replaced by @var{code2}, and so on.
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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@xref{Defining Mode Iterators}.
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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It is possible to define attributes for codes as well as for modes.
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There are two standard code attributes: @code{code}, the name of the
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code in lower case, and @code{CODE}, the name of the code in upper case.
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Other attributes are defined using:
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@smallexample
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(define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
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@end smallexample
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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Here's an example of code iterators in action, taken from the MIPS port:
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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@smallexample
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
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eq ne gt ge lt le gtu geu ltu leu])
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read-rtl.c (map_value, [...]): New structures.
* read-rtl.c (map_value, mapping, macro_group): New structures.
(BELLWETHER_CODE): New macro.
(modes, codes, bellwether_codes): New variables.
(find_mode, uses_mode_macro_p, apply_mode_macro, find_code)
(uses_code_macro_p, apply_code_macro, apply_macro_to_string)
(apply_macro_to_rtx, uses_macro_p, add_condition_to_string)
(add_condition_to_rtx, apply_macro_traverse, add_mapping)
(add_map_value, initialize_macros): New functions.
(def_hash, def_hash_eq_p): Generalize to anything that points to,
or starts with, a char * field.
(find_macro, read_mapping, check_code_macro): New functions.
(read_rtx_1): New, split out from read_rtx. Handle the new
define_{mode,code}_{macro,attr} constructs. Use find_macro
to parse the name of a code or mode. Use BELLWETHER_CODE to
extract the format and to choose a suitable code for rtx_alloc.
Modify recursive invocations to use read_rtx_1.
(read_rtx): Call initialize_macros. Apply code and mode macros
to the rtx returned by read_rtx_1. Cache everything after the
first macro expansion for subsequent read_rtx calls.
* doc/md.texi: Document new .md constructs.
* config/mips/mips.md (GPR): New mode macro.
(d, si8_di5): New mode attributes.
(any_cond): New code macro.
(add[sd]i3): Redefine using :GPR.
(*add[sd]i3): Likewise, renaming from add[sd]i3_internal.
(*add[sd]i3_sp[12], *add<mode>3_mips16): Redefine using :GPR, naming
previously unnamed MIPS16 patterns.
(*addsi3_extended): Renamed from addsi3_internal_2. Fix overly long
lines. Don't match (plus (const_int 0) ...).
(*addsi3_extended_mips16): Name previously unnamed MIPS16 pattern.
Use a define_split to generate the addition.
(sub[sd]i3): Redefine using :GPR. Turn subsi3 into a define_insn.
(subsi3_internal): Delete.
(*subsi3_extended): Renamed from subsi3_internal_2.
(bunordered, bordered, bunlt, bunge, buneq, bltgt, bunle, bungt)
(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Redefine
using an any_cond template.
From-SVN: r86404
2004-08-23 07:55:50 +02:00
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(define_expand "b<code>"
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[(set (pc)
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(if_then_else (any_cond:CC (cc0)
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(const_int 0))
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(label_ref (match_operand 0 ""))
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(pc)))]
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""
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@{
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gen_conditional_branch (operands, <CODE>);
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DONE;
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@})
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@end smallexample
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This is equivalent to:
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@smallexample
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(define_expand "bunordered"
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[(set (pc)
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(if_then_else (unordered:CC (cc0)
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(const_int 0))
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(label_ref (match_operand 0 ""))
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(pc)))]
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""
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@{
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gen_conditional_branch (operands, UNORDERED);
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DONE;
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@})
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(define_expand "bordered"
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[(set (pc)
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(if_then_else (ordered:CC (cc0)
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(const_int 0))
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(label_ref (match_operand 0 ""))
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(pc)))]
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""
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@{
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gen_conditional_branch (operands, ORDERED);
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DONE;
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@})
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...
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@end smallexample
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@end ifset
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