2005-11-15 22:33:04 +01:00
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2005-11-16 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct
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frsqrtes.
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2005-11-14 03:25:39 +01:00
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2005-11-14 David Ung <davidu@mips.com>
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* mips16-opc.c: Add MIPS16e save/restore opcodes.
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* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
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codes for save/restore.
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2005-11-10 15:32:28 +01:00
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2005-11-10 Andreas Schwab <schwab@suse.de>
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* m68k-dis.c (print_insn_m68k): Only match FPU insns with
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coprocessor ID 1.
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2005-11-08 17:16:47 +01:00
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2005-11-08 H.J. Lu <hongjiu.lu@intel.com>
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* m32c-desc.c: Regenerated.
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bfd:
Add ms2.
* archures.c (bfd_mach_ms2): Define.
* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
(ms1_elf_merge_private_bfd_data): Remove unused variables. Add
correct merging logic, with workaround.
(ms1_elf_print_private_bfd_data): Add ms2 case.
* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
cpu:
Add ms2
* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
model.
(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
f-cb2incr, f-rc3): New fields.
(LOOP): New instruction.
(JAL-HAZARD): New hazard.
(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
New operands.
(mul, muli, dbnz, iflush): Enable for ms2
(jal, reti): Has JAL-HAZARD.
(ldctxt, ldfb, stfb): Only ms1.
(fbcb): Only ms1,ms1-003.
(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
fbcbincrs, mfbcbincrs): Enable for ms2.
(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
* ms1.opc (parse_loopsize): New.
(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
(print_pcrel): New.
gas:
Add ms2.
* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
(ms1_architectures): Add ms2.
(md_parse_option): Add ms2.
(md_show_usage): Add ms2.
(md_assemble): Add JAL_HAZARD detection logic.
(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
* doc/c-ms1.texi: New.
* doc/all.texi: Add MS1.
* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
* doc/Makefile.in: Rebuilt.
* doc/Makefile: Rebuilt.
gas/testsuite:
Add ms2.
* gas/ms1/allinsn.d: Adjust pcrel disassembly.
* gas/ms1/errors.exp: Fix target triplet.
* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
* gas/ms1/ms1-16-003.s: Tweak label.
* gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test.
* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
* gas/ms1/relocs.d: Adjust expected machine name and pcrel
disassembly.
* gas/ms1/relocs.exp: Adjust target triplet.
include:
Add ms2.
* elf/ms1.h (EF_MS1_CPU_MS2): New.
opcodes:
Add ms2.
* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
ms1-opc.c, ms1-opc.h: Regenerated.
2005-11-08 12:15:13 +01:00
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2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
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Add ms2.
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* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
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ms1-opc.c, ms1-opc.h: Regenerated.
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2005-11-07 23:21:48 +01:00
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2005-11-07 Steve Ellcey <sje@cup.hp.com>
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* configure: Regenerate after modifying bfd/warning.m4.
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2005-11-07 01:19:12 +01:00
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2005-11-07 Alan Modra <amodra@bigpond.net.au>
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* i386-dis.c (ckprefix): Handle rex on fwait. Don't print
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ignored rex prefixes here.
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(print_insn): Instead, handle them similarly to fwait followed
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by non-fp insns.
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2005-11-02 17:58:31 +01:00
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2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
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* iq2000-desc.c: Regenerated.
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* iq2000-desc.h: Likewise.
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* iq2000-dis.c: Likewise.
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* iq2000-opc.c: Likewise.
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2005-11-02 17:53:11 +01:00
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2005-11-02 Paul Brook <paul@codesourcery.com>
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* arm-dis.c (print_insn_thumb32): Word align blx target address.
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2005-10-31 07:10:33 +01:00
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2005-10-31 Alan Modra <amodra@bigpond.net.au>
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* arm-dis.c (print_insn): Warning fix.
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2005-10-30 18:40:28 +01:00
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2005-10-30 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.am: Run "make dep-am".
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* Makefile.in: Regenerated.
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* dep-in.sed: Replace " ./" with " ".
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2005-10-28 21:49:22 +02:00
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2005-10-28 Dave Brolley <brolley@redhat.com>
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* All CGEN-generated sources: Regenerate.
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Contribute the following changes:
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2005-09-19 Dave Brolley <brolley@redhat.com>
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* disassemble.c (disassemble_init_for_target): Add 'break' to case for
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bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
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bfd_arch_m32c case.
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2005-02-16 Dave Brolley <brolley@redhat.com>
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* cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
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cgen_isa_mask_* to cgen_bitset_*.
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* cgen-opc.c: Likewise.
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2003-11-28 Richard Sandiford <rsandifo@redhat.com>
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* cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
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* *-dis.c: Regenerate.
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2003-06-05 DJ Delorie <dj@redhat.com>
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* cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
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it, as it may point to a reused buffer. Set prev_isas when we
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change cpus.
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2002-12-13 Dave Brolley <brolley@redhat.com>
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* cgen-opc.c (cgen_isa_mask_create): New support function for
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CGEN_ISA_MASK.
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(cgen_isa_mask_init): Ditto.
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(cgen_isa_mask_clear): Ditto.
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(cgen_isa_mask_add): Ditto.
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(cgen_isa_mask_set): Ditto.
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(cgen_isa_supported): Ditto.
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(cgen_isa_mask_compare): Ditto.
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(cgen_isa_mask_intersection): Ditto.
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(cgen_isa_mask_copy): Ditto.
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(cgen_isa_mask_combine): Ditto.
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* cgen-dis.in (libiberty.h): #include it.
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(isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
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(print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
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* Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
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* Makefile.in: Regenerated.
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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
imm operand is needed.
(adjnz, sbjnz): Pass the right operands.
(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
unary-insn): Add -g variants for opcodes that need to support :G.
(not.BW:G, push.BW:G): Call it.
(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
stzx16-imm8-imm8-abs16): Fix operand typos.
* m32c.opc (m32c_asm_hash): Support bnCND.
(parse_signed4n, print_signed4n): New.
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
2005-10-28 01:54:17 +02:00
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2005-10-27 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
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* m32c-desc.c: Regenerate.
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* m32c-desc.h: Regenerate.
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* m32c-dis.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32c-opc.c: Regenerate.
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* m32c-opc.h: Regenerate.
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2005-10-26 16:59:12 +02:00
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2005-10-26 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
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* m32c-desc.c: Regenerate.
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* m32c-desc.h: Regenerate.
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* m32c-dis.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32c-opc.c: Regenerate.
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* m32c-opc.h: Regenerate.
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2005-10-26 16:09:29 +02:00
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|
2005-10-26 Paul Brook <paul@codesourcery.com>
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* arm-dis.c (arm_opcodes): Correct "sel" entry.
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2005-10-26 09:49:05 +02:00
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2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
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* m32r-asm.c: Regenerate.
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2005-10-25 20:52:02 +02:00
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|
2005-10-25 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
|
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* m32c-desc.c: Regenerate.
|
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* m32c-desc.h: Regenerate.
|
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* m32c-dis.c: Regenerate.
|
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* m32c-ibld.c: Regenerate.
|
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* m32c-opc.c: Regenerate.
|
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* m32c-opc.h: Regenerate.
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|
2005-10-25 19:40:19 +02:00
|
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|
2005-10-25 Arnold Metselaar <arnold.metselaar@planet.nl>
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* configure.in: Add target architecture bfd_arch_z80.
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* configure: Regenerated.
|
2005-11-07 01:19:12 +01:00
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* disassemble.c (disassembler)<ARCH_z80>: Add case
|
2005-10-25 19:40:19 +02:00
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bfd_arch_z80.
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* z80-dis.c: New file.
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2005-10-25 04:20:17 +02:00
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|
2005-10-25 Alan Modra <amodra@bigpond.net.au>
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* po/POTFILES.in: Regenerate.
|
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* po/opcodes.pot: Regenerate.
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|
2005-10-24 09:42:50 +02:00
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|
2005-10-24 Jan Beulich <jbeulich@novell.com>
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* ia64-asmtab.c: Regenerate.
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|
[cpu]
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
indexld, indexls): .w variants have `1' bit.
(rot32.b): QI, not SI.
(rot32.w): HI, not SI.
(xchg16): HI for .w variant.
[opcodes]
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
2005-10-22 02:03:13 +02:00
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|
2005-10-21 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
|
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* m32c-desc.c: Regenerate.
|
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|
* m32c-desc.h: Regenerate.
|
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|
* m32c-dis.c: Regenerate.
|
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|
|
* m32c-ibld.c: Regenerate.
|
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|
|
* m32c-opc.c: Regenerate.
|
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|
|
* m32c-opc.h: Regenerate.
|
|
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|
|
2005-10-21 18:28:18 +02:00
|
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|
|
2005-10-21 Nick Clifton <nickc@redhat.com>
|
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|
|
* bfin-dis.c: Tidy up code, removing redundant constructs.
|
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|
2005-10-19 17:05:10 +02:00
|
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|
|
2005-10-19 Martin Schwidefsky <schwidefsky@de.ibm.com>
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* s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add
|
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instructions.
|
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|
2005-10-19 16:44:17 +02:00
|
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|
2005-10-18 Nick Clifton <nickc@redhat.com>
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* m32r-asm.c: Regenerate after updating m32r.opc.
|
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|
2005-10-18 18:39:41 +02:00
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|
2005-10-18 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (print_insn_bfin): Do proper endian transform when
|
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|
reading instruction from memory.
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|
2005-10-18 09:53:17 +02:00
|
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|
2005-10-18 Nick Clifton <nickc@redhat.com>
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|
* m32r-asm.c: Regenerate after updating m32r.opc.
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|
2005-10-14 10:33:27 +02:00
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|
2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
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* m32r-asm.c: Regenerate after updating m32r.opc.
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|
2005-10-08 16:52:07 +02:00
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|
2005-10-08 James Lemke <jim@wasabisystems.com>
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* arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
|
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|
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operations.
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|
2005-10-06 21:21:14 +02:00
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|
2005-10-06 Daniel Jacobowitz <dan@codesourcery.com>
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|
|
* ppc-dis.c (struct dis_private): Remove.
|
|
|
|
|
|
(powerpc_dialect): Avoid aliasing warnings.
|
|
|
|
|
|
(print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
|
|
|
|
|
|
|
2005-10-03 12:52:38 +02:00
|
|
|
|
2005-09-30 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/ga.po: New Irish translation.
|
|
|
|
|
|
* configure.in (ALL_LINGUAS): Add "ga".
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2005-09-30 20:05:59 +02:00
|
|
|
|
2005-09-30 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Run "make dep-am".
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* aclocal.m4: Likewise.
|
|
|
|
|
|
* configure: Likewise.
|
|
|
|
|
|
|
2005-09-30 17:28:52 +02:00
|
|
|
|
2005-09-30 Catherine Moore <clm@cm00re.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Bfin support.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* aclocal.m4: Regenerated.
|
|
|
|
|
|
* bfin-dis.c: New file.
|
|
|
|
|
|
* configure.in: Bfin support.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* disassemble.c (ARCH_bfin): Define.
|
|
|
|
|
|
(disassembler): Add case for bfd_arch_bfin.
|
|
|
|
|
|
|
2005-09-28 17:34:53 +02:00
|
|
|
|
2005-09-28 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
|
|
|
|
|
|
(indirEv): Use it.
|
|
|
|
|
|
(stackEv): New.
|
|
|
|
|
|
(Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
|
|
|
|
|
|
(dis386): Document and use new 'V' meta character. Use it for
|
|
|
|
|
|
single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
|
|
|
|
|
|
opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
|
|
|
|
|
|
(putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
|
|
|
|
|
|
data prefix as used whenever DFLAG was examined. Handle 'V'.
|
|
|
|
|
|
(intel_operand_size): Use stack_v_mode.
|
|
|
|
|
|
(OP_E): Use stack_v_mode, but handle only the special case of
|
|
|
|
|
|
64-bit mode without operand size override here; fall through to
|
|
|
|
|
|
v_mode case otherwise.
|
|
|
|
|
|
(OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
|
|
|
|
|
|
and no operand size override is present.
|
|
|
|
|
|
(OP_J): Use get32s for obtaining the displacement also when rex64
|
|
|
|
|
|
is present.
|
|
|
|
|
|
|
2005-09-08 14:49:27 +02:00
|
|
|
|
2005-09-08 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
|
|
|
|
|
|
|
2005-09-06 20:46:57 +02:00
|
|
|
|
2005-09-06 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (MT32): New define.
|
|
|
|
|
|
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
|
|
|
|
|
|
bottom to avoid opcode collision with "mftr" and "mttr".
|
|
|
|
|
|
Add MT instructions.
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
|
|
|
|
|
|
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
|
|
|
|
|
|
formats.
|
|
|
|
|
|
|
2005-09-02 16:54:27 +02:00
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add null terminator.
|
|
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): New.
|
|
|
|
|
|
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
|
|
|
|
|
|
(print_insn_coprocessor): New function.
|
|
|
|
|
|
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
|
|
|
|
|
|
format characters.
|
|
|
|
|
|
(print_insn_thumb32): Use print_insn_coprocessor.
|
|
|
|
|
|
|
2005-08-30 13:21:59 +02:00
|
|
|
|
2005-08-30 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
|
|
|
|
|
|
|
2005-08-26 17:33:43 +02:00
|
|
|
|
2005-08-26 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (intel_operand_size): New, broken out from OP_E for
|
|
|
|
|
|
re-use.
|
|
|
|
|
|
(OP_E): Call intel_operand_size, move call site out of mode
|
|
|
|
|
|
dependent code.
|
|
|
|
|
|
(OP_OFF): Call intel_operand_size if suffix_always. Remove
|
|
|
|
|
|
ATTRIBUTE_UNUSED from parameters.
|
|
|
|
|
|
(OP_OFF64): Likewise.
|
|
|
|
|
|
(OP_ESreg): Call intel_operand_size.
|
|
|
|
|
|
(OP_DSreg): Likewise.
|
|
|
|
|
|
(OP_DIR): Use colon rather than semicolon as separator of far
|
|
|
|
|
|
jump/call operands.
|
|
|
|
|
|
|
* mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
(mips_builtin_opcodes): Add DSP instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
mips64, mips64r2.
(print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
operand formats.
2005-08-25 20:12:44 +02:00
|
|
|
|
2005-08-25 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
|
|
|
|
|
|
(mips_builtin_opcodes): Add DSP instructions.
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
|
|
|
|
|
|
mips64, mips64r2.
|
|
|
|
|
|
(print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
|
|
|
|
|
|
operand formats.
|
|
|
|
|
|
|
2005-08-23 13:06:10 +02:00
|
|
|
|
2005-08-23 David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
|
2005-11-07 01:19:12 +01:00
|
|
|
|
instructions to the table.
|
2005-08-23 13:06:10 +02:00
|
|
|
|
|
2005-08-18 05:51:51 +02:00
|
|
|
|
2005-08-18 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
2005-08-18 05:59:24 +02:00
|
|
|
|
* a29k-dis.c: Delete.
|
2005-08-18 05:51:51 +02:00
|
|
|
|
* Makefile.am: Remove a29k support.
|
|
|
|
|
|
* configure.in: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2005-08-15 17:37:15 +02:00
|
|
|
|
2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_dialect): Handle e300.
|
|
|
|
|
|
(print_ppc_disassembler_options): Likewise.
|
|
|
|
|
|
* ppc-opc.c (PPCE300): Define.
|
|
|
|
|
|
(powerpc_opcodes): Mark icbt as available for the e300.
|
|
|
|
|
|
|
2005-08-14 03:15:34 +02:00
|
|
|
|
2005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
|
|
|
|
|
|
Use "rp" instead of "%r2" in "b,l" insns.
|
|
|
|
|
|
|
* s390-dis.c (print_insn_s390): Print unsigned operands with %u.
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
(main): Likewise.
* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
and 4 bit optional masks.
(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
(s390_opformats): Likewise.
* s390-opc.txt: Add new instructions for cpu type z9-109.
2005-08-12 20:03:03 +02:00
|
|
|
|
2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-dis.c (print_insn_s390): Print unsigned operands with %u.
|
|
|
|
|
|
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
|
|
|
|
|
|
(main): Likewise.
|
|
|
|
|
|
* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
|
|
|
|
|
|
and 4 bit optional masks.
|
|
|
|
|
|
(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
|
|
|
|
|
|
INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
|
|
|
|
|
|
(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
|
|
|
|
|
|
MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
|
|
|
|
|
|
(s390_opformats): Likewise.
|
|
|
|
|
|
* s390-opc.txt: Add new instructions for cpu type z9-109.
|
|
|
|
|
|
|
2005-08-05 19:52:06 +02:00
|
|
|
|
2005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
|
|
|
|
|
|
|
2005-07-29 19:39:39 +02:00
|
|
|
|
2005-07-29 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
|
|
|
|
|
|
|
2005-07-29 19:28:33 +02:00
|
|
|
|
2005-07-29 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
|
|
|
|
|
|
(print_insn_thumb32): Fix decoding of thumb2 'I' operands.
|
|
|
|
|
|
|
2005-07-26 05:21:53 +02:00
|
|
|
|
2005-07-25 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-asm.c Regenerate.
|
|
|
|
|
|
* m32c-dis.c Regenerate.
|
|
|
|
|
|
|
2005-07-20 21:36:54 +02:00
|
|
|
|
2005-07-20 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassemble_init_for_target): M32C ISAs are
|
|
|
|
|
|
enums, so convert them to bit masks, which attributes are.
|
|
|
|
|
|
|
2005-07-19 12:01:32 +02:00
|
|
|
|
2005-07-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Restore alpha ordering to list of arches.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* disassemble.c: Restore alpha ordering to list of arches.
|
|
|
|
|
|
|
|
|
|
|
|
2005-07-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-asm.c: Regenerate.
|
|
|
|
|
|
* m32c-desc.c: Regenerate.
|
|
|
|
|
|
* m32c-desc.h: Regenerate.
|
|
|
|
|
|
* m32c-dis.c: Regenerate.
|
|
|
|
|
|
* m32c-ibld.h: Regenerate.
|
|
|
|
|
|
* m32c-opc.c: Regenerate.
|
|
|
|
|
|
* m32c-opc.h: Regenerate.
|
|
|
|
|
|
|
2005-07-19 06:11:19 +02:00
|
|
|
|
2005-07-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PNI_Fixup): Update comment.
|
|
|
|
|
|
(VMX_Fixup): Properly handle the suffix check.
|
|
|
|
|
|
|
2005-07-17 04:26:26 +02:00
|
|
|
|
2005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
|
|
|
|
|
|
mfctl disassembly.
|
|
|
|
|
|
|
2005-07-16 04:03:55 +02:00
|
|
|
|
2005-07-16 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Run "make dep-am".
|
|
|
|
|
|
(stamp-m32c): Fix cpu dependencies.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* ip2k-dis.c: Regenerate.
|
|
|
|
|
|
|
2005-07-15 15:49:53 +02:00
|
|
|
|
2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
|
|
|
|
|
|
(VMX_Fixup): New. Fix up Intel VMX Instructions.
|
|
|
|
|
|
(Em): New.
|
|
|
|
|
|
(Gm): New.
|
|
|
|
|
|
(VM): New.
|
|
|
|
|
|
(dis386_twobyte): Updated entries 0x78 and 0x79.
|
|
|
|
|
|
(twobyte_has_modrm): Likewise.
|
|
|
|
|
|
(grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
|
|
|
|
|
|
(OP_G): Handle m_mode.
|
|
|
|
|
|
|
ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
2005-07-15 00:52:28 +02:00
|
|
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2005-07-14 Jim Blandy <jimb@redhat.com>
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Add support for the Renesas M32C and M16C.
|
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|
|
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
|
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|
* m32c-desc.h, m32c-opc.h: New.
|
|
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* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
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|
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
|
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m32c-opc.c.
|
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(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
|
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m32c-ibld.lo, m32c-opc.lo.
|
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(CLEANFILES): List stamp-m32c.
|
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(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
|
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(CGEN_CPUS): Add m32c.
|
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(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
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(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
|
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(m32c_opc_h): New variable.
|
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(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
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(m32c-opc.lo): New rules.
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* Makefile.in: Regenerated.
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* configure.in: Add case for bfd_m32c_arch.
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* configure: Regenerated.
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* disassemble.c (ARCH_m32c): New.
|
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[ARCH_m32c]: #include "m32c-desc.h".
|
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(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
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(disassemble_init_for_target) [ARCH_m32c]: Same.
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* cgen-ops.h, cgen-types.h: New files.
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* Makefile.am (HFILES): List them.
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* Makefile.in: Regenerated.
|
2005-11-07 01:19:12 +01:00
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Kaveh Ghazi's printf format attribute checking patch.
bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
2005-07-07 21:27:52 +02:00
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2005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
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d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
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ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
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m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
|
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ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
|
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v850-dis.c: Fix format bugs.
|
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* ia64-gen.c (fail, warn): Add format attribute.
|
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* or32-opc.c (debug): Likewise.
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2005-07-07 13:37:10 +02:00
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2005-07-07 Khem Raj <kraj@mvista.com>
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* arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
|
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disassembly pattern.
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2005-07-06 10:19:39 +02:00
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2005-07-06 Alan Modra <amodra@bigpond.net.au>
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* Makefile.am (stamp-m32r): Fix path to cpu files.
|
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(stamp-m32r, stamp-iq2000): Likewise.
|
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* Makefile.in: Regenerate.
|
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|
|
* m32r-asm.c: Regenerate.
|
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* po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
|
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ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
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2005-07-05 17:07:46 +02:00
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2005-07-05 Nick Clifton <nickc@redhat.com>
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* iq2000-asm.c: Regenerate.
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* ms1-asm.c: Regenerate.
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2005-07-05 09:16:54 +02:00
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|
2005-07-05 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (SVME_Fixup): New.
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(grps): Use it for the lidt entry.
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(PNI_Fixup): Call OP_M rather than OP_E.
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(INVLPG_Fixup): Likewise.
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2005-07-04 19:51:36 +02:00
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2005-07-04 H.J. Lu <hongjiu.lu@intel.com>
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* tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
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2005-07-01 13:16:33 +02:00
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2005-07-01 Nick Clifton <nickc@redhat.com>
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* a29k-dis.c: Update to ISO C90 style function declarations and
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fix formatting.
|
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* alpha-opc.c: Likewise.
|
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* arc-dis.c: Likewise.
|
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* arc-opc.c: Likewise.
|
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* avr-dis.c: Likewise.
|
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* cgen-asm.in: Likewise.
|
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* cgen-dis.in: Likewise.
|
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* cgen-ibld.in: Likewise.
|
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* cgen-opc.c: Likewise.
|
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* cris-dis.c: Likewise.
|
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* d10v-dis.c: Likewise.
|
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* d30v-dis.c: Likewise.
|
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* d30v-opc.c: Likewise.
|
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* dis-buf.c: Likewise.
|
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|
* dlx-dis.c: Likewise.
|
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|
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|
* h8300-dis.c: Likewise.
|
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* h8500-dis.c: Likewise.
|
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* hppa-dis.c: Likewise.
|
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* i370-dis.c: Likewise.
|
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* i370-opc.c: Likewise.
|
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* m10200-dis.c: Likewise.
|
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|
* m10300-dis.c: Likewise.
|
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|
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|
* m68k-dis.c: Likewise.
|
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|
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|
* m88k-dis.c: Likewise.
|
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|
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|
* mips-dis.c: Likewise.
|
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|
* mmix-dis.c: Likewise.
|
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|
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|
* msp430-dis.c: Likewise.
|
|
|
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|
* ns32k-dis.c: Likewise.
|
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|
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|
|
* or32-dis.c: Likewise.
|
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|
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|
* or32-opc.c: Likewise.
|
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|
* pdp11-dis.c: Likewise.
|
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|
* pj-dis.c: Likewise.
|
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|
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|
* s390-dis.c: Likewise.
|
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|
* sh-dis.c: Likewise.
|
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|
* sh64-dis.c: Likewise.
|
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|
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|
* sparc-dis.c: Likewise.
|
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|
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|
|
* sparc-opc.c: Likewise.
|
|
|
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|
|
* sysdep.h: Likewise.
|
|
|
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|
* tic30-dis.c: Likewise.
|
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|
* tic4x-dis.c: Likewise.
|
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|
* tic80-dis.c: Likewise.
|
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* v850-dis.c: Likewise.
|
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* v850-opc.c: Likewise.
|
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|
* vax-dis.c: Likewise.
|
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* w65-dis.c: Likewise.
|
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|
* z8kgen.c: Likewise.
|
2005-11-07 01:19:12 +01:00
|
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|
2005-07-01 13:16:33 +02:00
|
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|
* fr30-*: Regenerate.
|
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* frv-*: Regenerate.
|
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* ip2k-*: Regenerate.
|
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* iq2000-*: Regenerate.
|
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|
* m32r-*: Regenerate.
|
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|
* ms1-*: Regenerate.
|
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* openrisc-*: Regenerate.
|
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|
* xstormy16-*: Regenerate.
|
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|
2005-06-23 13:18:26 +02:00
|
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|
2005-06-23 Ben Elliston <bje@gnu.org>
|
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|
* m68k-dis.c: Use ISC C90.
|
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|
|
|
* m68k-opc.c: Formatting fixes.
|
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|
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|
|
2005-06-16 19:01:12 +02:00
|
|
|
|
2005-06-16 David Ung <davidu@mips.com>
|
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|
|
|
|
|
2005-11-07 01:19:12 +01:00
|
|
|
|
* mips16-opc.c (mips16_opcodes): Add the following MIPS16e
|
|
|
|
|
|
instructions to the table; seb/seh/sew/zeb/zeh/zew.
|
2005-06-16 19:01:12 +02:00
|
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|
2005-06-15 18:23:54 +02:00
|
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|
|
2005-06-15 Dave Brolley <brolley@redhat.com>
|
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|
|
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|
|
|
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|
|
Contribute Morpho ms1 on behalf of Red Hat
|
2005-11-07 01:19:12 +01:00
|
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|
|
* ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
|
2005-06-15 18:23:54 +02:00
|
|
|
|
ms1-opc.h: New files, Morpho ms1 target.
|
|
|
|
|
|
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|
|
|
|
|
2004-05-14 Stan Cox <scox@redhat.com>
|
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|
|
|
|
|
|
|
|
* disassemble.c (ARCH_ms1): Define.
|
|
|
|
|
|
(disassembler): Handle bfd_arch_ms1
|
|
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|
|
|
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|
|
2004-05-13 Michael Snyder <msnyder@redhat.com>
|
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|
|
|
|
|
|
|
|
|
|
* Makefile.am, Makefile.in: Add ms1 target.
|
|
|
|
|
|
* configure.in: Ditto.
|
|
|
|
|
|
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
2005-06-08 Zack Weinberg <zack@codesourcery.com>
|
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|
|
|
|
|
|
|
|
|
|
* arm-opc.h: Delete; fold contents into ...
|
|
|
|
|
|
* arm-dis.c: ... here. Move includes of internal COFF headers
|
|
|
|
|
|
next to includes of internal ELF headers.
|
|
|
|
|
|
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
|
|
|
|
|
|
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
|
|
|
|
|
|
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
|
|
|
|
|
|
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
|
|
|
|
|
|
(iwmmxt_wwnames, iwmmxt_wwssnames):
|
|
|
|
|
|
Make const.
|
|
|
|
|
|
(regnames): Remove iWMMXt coprocessor register sets.
|
|
|
|
|
|
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
|
|
|
|
|
|
(get_arm_regnames): Adjust fourth argument to match above changes.
|
|
|
|
|
|
(set_iwmmxt_regnames): Delete.
|
|
|
|
|
|
(print_insn_arm): Constify 'c'. Use ISO syntax for function
|
|
|
|
|
|
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
|
|
|
|
|
|
and iwmmxt_cregnames, not set_iwmmxt_regnames.
|
|
|
|
|
|
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
|
|
|
|
|
|
ISO syntax for function pointer calls.
|
|
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
2005-06-07 Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Split up the comments describing the format codes, so
|
|
|
|
|
|
that the ARM and 16-bit Thumb opcode tables each have comments
|
|
|
|
|
|
preceding them that describe all the codes, and only the codes,
|
|
|
|
|
|
valid in those tables. (32-bit Thumb table is already like this.)
|
|
|
|
|
|
Reorder the lists in all three comments to match the order in
|
|
|
|
|
|
which the codes are implemented.
|
|
|
|
|
|
Remove all forward declarations of static functions. Convert all
|
|
|
|
|
|
function definitions to ISO C format.
|
|
|
|
|
|
(print_insn_arm, print_insn_thumb16, print_insn_thumb32):
|
|
|
|
|
|
Return nothing.
|
|
|
|
|
|
(print_insn_thumb16): Remove unused case 'I'.
|
|
|
|
|
|
(print_insn): Update for changed calling convention of subroutines.
|
|
|
|
|
|
|
2005-05-25 08:50:23 +02:00
|
|
|
|
2005-05-25 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
|
|
|
|
|
|
hex (but retain it being displayed as signed). Remove redundant
|
|
|
|
|
|
checks. Add handling of displacements for 16-bit addressing in Intel
|
|
|
|
|
|
mode.
|
|
|
|
|
|
|
2005-05-25 08:47:58 +02:00
|
|
|
|
2005-05-25 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_name): Remove pointless mode_64bit check.
|
|
|
|
|
|
(OP_E): Remove redundant REX_EXTZ handling. Remove pointless
|
|
|
|
|
|
masking of 'rm' in 16-bit memory address handling.
|
|
|
|
|
|
|
2005-05-19 09:00:40 +02:00
|
|
|
|
2005-05-19 Anton Blanchard <anton@samba.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
|
|
|
|
|
|
(print_ppc_disassembler_options): Document it.
|
|
|
|
|
|
* ppc-opc.c (SVC_LEV): Define.
|
|
|
|
|
|
(LEV): Allow optional operand.
|
|
|
|
|
|
(POWER5): Define.
|
|
|
|
|
|
(powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
|
|
|
|
|
|
"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
|
|
|
|
|
|
|
2005-05-19 05:18:04 +02:00
|
|
|
|
2005-05-19 Kelley Cook <kcook@gcc.gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
2005-05-17 Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
|
|
|
|
|
|
instructions. Adjust disassembly of some opcodes to match
|
|
|
|
|
|
unified syntax.
|
|
|
|
|
|
(thumb32_opcodes): New table.
|
|
|
|
|
|
(print_insn_thumb): Rename print_insn_thumb16; don't handle
|
|
|
|
|
|
two-halfword branches here.
|
|
|
|
|
|
(print_insn_thumb32): New function.
|
|
|
|
|
|
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
|
|
|
|
|
|
and print_insn_thumb32. Be consistent about order of
|
|
|
|
|
|
halfwords when printing 32-bit instructions.
|
|
|
|
|
|
|
2005-05-07 15:30:02 +02:00
|
|
|
|
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 843
|
|
|
|
|
|
* i386-dis.c (branch_v_mode): New.
|
|
|
|
|
|
(indirEv): Use branch_v_mode instead of v_mode.
|
|
|
|
|
|
(OP_E): Handle branch_v_mode.
|
|
|
|
|
|
|
2005-05-07 15:26:28 +02:00
|
|
|
|
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* d10v-dis.c (dis_2_short): Support 64bit host.
|
|
|
|
|
|
|
2005-05-07 09:52:54 +02:00
|
|
|
|
2005-05-07 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/nl.po: Updated translation.
|
|
|
|
|
|
|
2005-05-07 09:34:31 +02:00
|
|
|
|
2005-05-07 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Update the address and phone number of the FSF organization in
|
|
|
|
|
|
the GPL notices in the following files:
|
|
|
|
|
|
a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
|
|
|
|
|
|
arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
|
|
|
|
|
|
avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
|
|
|
|
|
|
cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
|
|
|
|
|
|
crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
|
|
|
|
|
|
d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
|
|
|
|
|
|
fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
|
|
|
|
|
|
fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
|
|
|
|
|
|
frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
|
|
|
|
|
|
h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
|
|
|
|
|
|
i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
|
|
|
|
|
|
ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
|
|
|
|
|
|
ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
|
|
|
|
|
|
ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
|
|
|
|
|
|
ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
|
|
|
|
|
|
iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
|
|
|
|
|
|
iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
|
|
|
|
|
|
m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
|
|
|
|
|
|
m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
|
|
|
|
|
|
m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
|
|
|
|
|
|
maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
|
|
|
|
|
|
mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
|
|
|
|
|
|
openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
|
|
|
|
|
|
openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
|
|
|
|
|
|
or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
|
|
|
|
|
|
pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
|
|
|
|
|
|
s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
|
|
|
|
|
|
sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
|
|
|
|
|
|
tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
|
|
|
|
|
|
v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
|
|
|
|
|
|
xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
|
|
|
|
|
|
xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
|
|
|
|
|
|
xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
|
|
|
|
|
|
|
2005-05-05 23:45:58 +02:00
|
|
|
|
2005-05-05 James E Wilson <wilson@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-opc.c: Include sysdep.h before libiberty.h.
|
|
|
|
|
|
|
2005-05-05 11:17:37 +02:00
|
|
|
|
2005-05-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (ALL_LINGUAS): Add vi.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/vi.po: New.
|
|
|
|
|
|
|
2005-04-26 12:24:45 +02:00
|
|
|
|
2005-04-26 Jerome Guitton <guitton@gnat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Fix the check for basename declaration.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2005-04-19 06:50:37 +02:00
|
|
|
|
2005-04-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (RTO): Define.
|
|
|
|
|
|
(powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
|
|
|
|
|
|
entries to suit PPC440.
|
|
|
|
|
|
|
2005-04-18 22:59:20 +02:00
|
|
|
|
2005-04-18 Mark Kettenis <kettenis@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
|
|
|
|
|
|
Add xcrypt-ctr.
|
|
|
|
|
|
|
2005-04-14 11:48:24 +02:00
|
|
|
|
2005-04-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fi.po: New translation: Finnish.
|
|
|
|
|
|
* configure.in (ALL_LINGUAS): Add fi.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2005-04-14 07:26:44 +02:00
|
|
|
|
2005-04-14 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (NO_WERROR): Define.
|
|
|
|
|
|
* configure.in: Invoke AM_BINUTILS_WARNINGS.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* aclocal.m4: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2005-04-04 12:09:52 +02:00
|
|
|
|
2005-04-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-asm.c: Regenerate.
|
|
|
|
|
|
* frv-asm.c: Regenerate.
|
|
|
|
|
|
* iq2000-asm.c: Regenerate.
|
|
|
|
|
|
* m32r-asm.c: Regenerate.
|
|
|
|
|
|
* openrisc-asm.c: Regenerate.
|
|
|
|
|
|
|
2005-04-01 18:06:40 +02:00
|
|
|
|
2005-04-01 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
|
|
|
|
|
|
visible operands in Intel mode. The first operand of monitor is
|
|
|
|
|
|
%rax in 64-bit mode.
|
|
|
|
|
|
|
2005-04-01 18:03:40 +02:00
|
|
|
|
2005-04-01 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
|
|
|
|
|
|
easier future additions.
|
|
|
|
|
|
|
2005-03-31 18:52:54 +02:00
|
|
|
|
2005-03-31 Jerome Guitton <guitton@gnat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Check for basename.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* config.in: Ditto.
|
|
|
|
|
|
|
2005-03-29 21:30:47 +02:00
|
|
|
|
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (SEG_Fixup): New.
|
|
|
|
|
|
(Sv): New.
|
|
|
|
|
|
(dis386): Use "Sv" for 0x8c and 0x8e.
|
|
|
|
|
|
|
2005-03-29 18:13:48 +02:00
|
|
|
|
2005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
Nick Clifton <nickc@redhat.com>
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-03-29 18:13:48 +02:00
|
|
|
|
* vax-dis.c: (entry_addr): New varible: An array of user supplied
|
|
|
|
|
|
function entry mask addresses.
|
|
|
|
|
|
(entry_addr_occupied_slots): New variable: The number of occupied
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
elements in entry_addr.
|
2005-03-29 18:13:48 +02:00
|
|
|
|
(entry_addr_total_slots): New variable: The total number of
|
|
|
|
|
|
elements in entry_addr.
|
|
|
|
|
|
(parse_disassembler_options): New function. Fills in the entry_addr
|
|
|
|
|
|
array.
|
|
|
|
|
|
(free_entry_array): New function. Release the memory used by the
|
|
|
|
|
|
entry addr array. Suppressed because there is no way to call it.
|
|
|
|
|
|
(is_function_entry): Check if a given address is a function's
|
|
|
|
|
|
start address by looking at supplied entry mask addresses and
|
|
|
|
|
|
symbol information, if available.
|
|
|
|
|
|
(print_insn_vax): Use parse_disassembler_options and is_function_entry.
|
|
|
|
|
|
|
2005-03-23 20:21:16 +01:00
|
|
|
|
2005-03-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris-dis.c (print_with_operands): Use ~31L for long instead
|
|
|
|
|
|
of ~31.
|
|
|
|
|
|
|
2005-03-20 18:12:16 +01:00
|
|
|
|
2005-03-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mmix-opc.c (O): Revert the last change.
|
|
|
|
|
|
(Z): Likewise.
|
|
|
|
|
|
|
2005-03-19 19:29:14 +01:00
|
|
|
|
2005-03-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
|
|
|
|
|
|
(Z): Likewise.
|
|
|
|
|
|
|
2005-03-19 05:23:24 +01:00
|
|
|
|
2005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mmix-opc.c (O, Z): Force expression as unsigned long.
|
|
|
|
|
|
|
2005-03-18 17:12:38 +01:00
|
|
|
|
2005-03-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ip2k-asm.c: Regenerate.
|
|
|
|
|
|
* op/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2005-03-16 17:17:14 +01:00
|
|
|
|
2005-03-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
2005-03-16 18:18:17 +01:00
|
|
|
|
* configure.in (werror): New switch: Add -Werror to the
|
2005-03-16 17:17:14 +01:00
|
|
|
|
compiler command line. Enabled by default. Disable via
|
2005-03-16 18:18:17 +01:00
|
|
|
|
--disable-werror.
|
2005-03-16 17:17:14 +01:00
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2005-03-16 03:38:39 +01:00
|
|
|
|
2005-03-16 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
|
|
|
|
|
|
BOOKE.
|
|
|
|
|
|
|
2005-03-15 00:39:09 +01:00
|
|
|
|
2005-03-15 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
2005-03-15 06:25:37 +01:00
|
|
|
|
* po/es.po: Commit new Spanish translation.
|
|
|
|
|
|
|
2005-03-15 00:39:09 +01:00
|
|
|
|
* po/fr.po: Commit new French translation.
|
|
|
|
|
|
|
2005-03-14 10:35:26 +01:00
|
|
|
|
2005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* vax-dis.c: Fix spelling error
|
|
|
|
|
|
(print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
|
|
|
|
|
|
of just "Entry mask: < r1 ... >"
|
|
|
|
|
|
|
2005-03-12 19:14:05 +01:00
|
|
|
|
2005-03-12 Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Document %E and %V.
|
|
|
|
|
|
Add entries for v6T2 ARM instructions:
|
|
|
|
|
|
bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
|
|
|
|
|
|
(print_insn_arm): Add support for %E and %V.
|
2005-03-12 19:25:47 +01:00
|
|
|
|
(thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
|
2005-03-12 19:14:05 +01:00
|
|
|
|
|
2005-03-10 13:52:30 +01:00
|
|
|
|
2005-03-10 Jeff Baker <jbaker@qnx.com>
|
|
|
|
|
|
Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
|
|
|
|
|
|
(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
|
|
|
|
|
|
(SPRG_MASK): Delete.
|
|
|
|
|
|
(XSPRG_MASK): Mask off extra bits now part of sprg field.
|
2005-03-12 19:14:05 +01:00
|
|
|
|
(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
|
2005-03-10 13:52:30 +01:00
|
|
|
|
mfsprg4..7 after msprg and consolidate.
|
|
|
|
|
|
|
2005-03-09 14:08:26 +01:00
|
|
|
|
2005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* vax-dis.c (entry_mask_bit): New array.
|
|
|
|
|
|
(print_insn_vax): Decode function entry mask.
|
|
|
|
|
|
|
2005-03-07 21:05:44 +01:00
|
|
|
|
2005-03-07 Aldy Hernandez <aldyh@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
|
|
|
|
|
|
|
2005-03-05 13:14:34 +01:00
|
|
|
|
2005-03-05 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2005-03-03 16:42:05 +01:00
|
|
|
|
2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
|
|
|
|
|
|
|
2005-03-09 14:08:26 +01:00
|
|
|
|
* arc-dis.c (a4_decoding_class): New enum.
|
2005-03-05 13:14:34 +01:00
|
|
|
|
(dsmOneArcInst): Use the enum values for the decoding class.
|
|
|
|
|
|
Remove redundant case in the switch for decodingClass value 11.
|
2005-03-03 16:42:05 +01:00
|
|
|
|
|
2005-03-02 09:01:32 +01:00
|
|
|
|
2005-03-02 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
|
|
|
|
|
|
accesses.
|
|
|
|
|
|
(OP_C): Consider lock prefix in non-64-bit modes.
|
|
|
|
|
|
|
2005-02-24 14:38:01 +01:00
|
|
|
|
2005-02-24 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* cris-dis.c (format_hex): Remove ineffective warning fix.
|
|
|
|
|
|
* crx-dis.c (make_instruction): Warning fix.
|
|
|
|
|
|
* frv-asm.c: Regenerate.
|
|
|
|
|
|
|
2005-02-23 12:53:31 +01:00
|
|
|
|
2005-02-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2005-02-23 17:04:40 +01:00
|
|
|
|
* cgen-dis.in: Use bfd_byte for buffers that are passed to
|
|
|
|
|
|
read_memory.
|
2005-03-05 13:14:34 +01:00
|
|
|
|
|
2005-02-23 17:04:40 +01:00
|
|
|
|
* ia64-opc.c (locate_opcode_ent): Initialise opval array.
|
2005-03-05 13:14:34 +01:00
|
|
|
|
|
2005-02-23 12:53:31 +01:00
|
|
|
|
* crx-dis.c (make_instruction): Move argument structure into inner
|
|
|
|
|
|
scope and ensure that all of its fields are initialised before
|
|
|
|
|
|
they are used.
|
|
|
|
|
|
|
2005-02-23 17:04:40 +01:00
|
|
|
|
* fr30-asm.c: Regenerate.
|
|
|
|
|
|
* fr30-dis.c: Regenerate.
|
|
|
|
|
|
* frv-asm.c: Regenerate.
|
|
|
|
|
|
* frv-dis.c: Regenerate.
|
|
|
|
|
|
* ip2k-asm.c: Regenerate.
|
|
|
|
|
|
* ip2k-dis.c: Regenerate.
|
|
|
|
|
|
* iq2000-asm.c: Regenerate.
|
|
|
|
|
|
* iq2000-dis.c: Regenerate.
|
|
|
|
|
|
* m32r-asm.c: Regenerate.
|
|
|
|
|
|
* m32r-dis.c: Regenerate.
|
|
|
|
|
|
* openrisc-asm.c: Regenerate.
|
|
|
|
|
|
* openrisc-dis.c: Regenerate.
|
|
|
|
|
|
* xstormy16-asm.c: Regenerate.
|
|
|
|
|
|
* xstormy16-dis.c: Regenerate.
|
|
|
|
|
|
|
2005-02-22 14:01:53 +01:00
|
|
|
|
2005-02-22 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-ext.c: Warning fixes.
|
|
|
|
|
|
* arc-ext.h: Likewise.
|
|
|
|
|
|
* cgen-opc.c: Likewise.
|
|
|
|
|
|
* ia64-gen.c: Likewise.
|
|
|
|
|
|
* maxq-dis.c: Likewise.
|
|
|
|
|
|
* ns32k-dis.c: Likewise.
|
|
|
|
|
|
* w65-dis.c: Likewise.
|
|
|
|
|
|
* ia64-asmtab.c: Regenerate.
|
|
|
|
|
|
|
2005-02-22 01:33:20 +01:00
|
|
|
|
2005-02-22 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-desc.c: Regenerate.
|
|
|
|
|
|
* fr30-desc.h: Regenerate.
|
|
|
|
|
|
* fr30-opc.c: Regenerate.
|
|
|
|
|
|
* fr30-opc.h: Regenerate.
|
|
|
|
|
|
* frv-desc.c: Regenerate.
|
|
|
|
|
|
* frv-desc.h: Regenerate.
|
|
|
|
|
|
* frv-opc.c: Regenerate.
|
|
|
|
|
|
* frv-opc.h: Regenerate.
|
|
|
|
|
|
* ip2k-desc.c: Regenerate.
|
|
|
|
|
|
* ip2k-desc.h: Regenerate.
|
|
|
|
|
|
* ip2k-opc.c: Regenerate.
|
|
|
|
|
|
* ip2k-opc.h: Regenerate.
|
|
|
|
|
|
* iq2000-desc.c: Regenerate.
|
|
|
|
|
|
* iq2000-desc.h: Regenerate.
|
|
|
|
|
|
* iq2000-opc.c: Regenerate.
|
|
|
|
|
|
* iq2000-opc.h: Regenerate.
|
|
|
|
|
|
* m32r-desc.c: Regenerate.
|
|
|
|
|
|
* m32r-desc.h: Regenerate.
|
|
|
|
|
|
* m32r-opc.c: Regenerate.
|
|
|
|
|
|
* m32r-opc.h: Regenerate.
|
|
|
|
|
|
* m32r-opinst.c: Regenerate.
|
|
|
|
|
|
* openrisc-desc.c: Regenerate.
|
|
|
|
|
|
* openrisc-desc.h: Regenerate.
|
|
|
|
|
|
* openrisc-opc.c: Regenerate.
|
|
|
|
|
|
* openrisc-opc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-desc.c: Regenerate.
|
|
|
|
|
|
* xstormy16-desc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-opc.c: Regenerate.
|
|
|
|
|
|
* xstormy16-opc.h: Regenerate.
|
|
|
|
|
|
|
2005-02-21 12:48:33 +01:00
|
|
|
|
2005-02-21 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Run "make dep-am"
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2005-02-15 13:52:03 +01:00
|
|
|
|
2005-02-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
|
|
|
|
|
|
compile time warnings.
|
|
|
|
|
|
(print_keyword): Likewise.
|
|
|
|
|
|
(default_print_insn): Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-desc.c: Regenerated.
|
|
|
|
|
|
* fr30-desc.h: Regenerated.
|
|
|
|
|
|
* fr30-dis.c: Regenerated.
|
|
|
|
|
|
* fr30-opc.c: Regenerated.
|
|
|
|
|
|
* fr30-opc.h: Regenerated.
|
|
|
|
|
|
* frv-desc.c: Regenerated.
|
|
|
|
|
|
* frv-dis.c: Regenerated.
|
|
|
|
|
|
* frv-opc.c: Regenerated.
|
|
|
|
|
|
* ip2k-asm.c: Regenerated.
|
|
|
|
|
|
* ip2k-desc.c: Regenerated.
|
|
|
|
|
|
* ip2k-desc.h: Regenerated.
|
|
|
|
|
|
* ip2k-dis.c: Regenerated.
|
|
|
|
|
|
* ip2k-opc.c: Regenerated.
|
|
|
|
|
|
* ip2k-opc.h: Regenerated.
|
|
|
|
|
|
* iq2000-desc.c: Regenerated.
|
|
|
|
|
|
* iq2000-dis.c: Regenerated.
|
|
|
|
|
|
* iq2000-opc.c: Regenerated.
|
|
|
|
|
|
* m32r-asm.c: Regenerated.
|
|
|
|
|
|
* m32r-desc.c: Regenerated.
|
|
|
|
|
|
* m32r-desc.h: Regenerated.
|
|
|
|
|
|
* m32r-dis.c: Regenerated.
|
|
|
|
|
|
* m32r-opc.c: Regenerated.
|
|
|
|
|
|
* m32r-opc.h: Regenerated.
|
|
|
|
|
|
* m32r-opinst.c: Regenerated.
|
|
|
|
|
|
* openrisc-desc.c: Regenerated.
|
|
|
|
|
|
* openrisc-desc.h: Regenerated.
|
|
|
|
|
|
* openrisc-dis.c: Regenerated.
|
|
|
|
|
|
* openrisc-opc.c: Regenerated.
|
|
|
|
|
|
* openrisc-opc.h: Regenerated.
|
|
|
|
|
|
* xstormy16-desc.c: Regenerated.
|
|
|
|
|
|
* xstormy16-desc.h: Regenerated.
|
|
|
|
|
|
* xstormy16-dis.c: Regenerated.
|
|
|
|
|
|
* xstormy16-opc.c: Regenerated.
|
|
|
|
|
|
* xstormy16-opc.h: Regenerated.
|
|
|
|
|
|
|
2005-02-14 16:47:19 +01:00
|
|
|
|
2005-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-buf.c (perror_memory): Use sprintf_vma to print out
|
|
|
|
|
|
address.
|
|
|
|
|
|
|
2005-02-11 17:04:06 +01:00
|
|
|
|
2005-02-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2005-02-11 17:09:30 +01:00
|
|
|
|
* iq2000-asm.c: Regenerate.
|
|
|
|
|
|
|
2005-02-11 17:04:06 +01:00
|
|
|
|
* frv-dis.c: Regenerate.
|
|
|
|
|
|
|
2005-02-08 05:52:24 +01:00
|
|
|
|
2005-02-07 Jim Blandy <jimb@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (CGEN): Load guile.scm before calling the main
|
|
|
|
|
|
application script.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
|
|
|
|
|
|
Simply pass the cgen-opc.scm path to ${cgen} as its first
|
|
|
|
|
|
argument; ${cgen} itself now contains the '-s', or whatever is
|
|
|
|
|
|
appropriate for the Scheme being used.
|
|
|
|
|
|
|
2005-01-31 21:32:45 +01:00
|
|
|
|
2005-01-31 Andrew Cagney <cagney@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate to track ../gettext.m4.
|
|
|
|
|
|
|
2005-01-31 09:48:32 +01:00
|
|
|
|
2005-01-31 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-gen.c (NELEMS): Define.
|
|
|
|
|
|
(shrink): Generate alias with missing second predicate register when
|
|
|
|
|
|
opcode has two outputs and these are both predicates.
|
|
|
|
|
|
* ia64-opc-i.c (FULL17): Define.
|
|
|
|
|
|
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
|
|
|
|
|
|
here to generate output template.
|
|
|
|
|
|
(TBITCM, TNATCM): Undefine after use.
|
|
|
|
|
|
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
|
|
|
|
|
|
first input. Add ld16 aliases without ar.csd as second output. Add
|
|
|
|
|
|
st16 aliases without ar.csd as second input. Add cmpxchg aliases
|
|
|
|
|
|
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
|
|
|
|
|
|
ar.ccv as third/fourth inputs. Consolidate through...
|
|
|
|
|
|
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
|
|
|
|
|
|
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
|
|
|
|
|
|
* ia64-asmtab.c: Regenerate.
|
|
|
|
|
|
|
2005-01-27 15:48:23 +01:00
|
|
|
|
2005-01-27 Andrew Cagney <cagney@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate to track ../gettext.m4 change.
|
|
|
|
|
|
|
2005-01-25 21:22:41 +01:00
|
|
|
|
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv-asm.c: Rebuilt.
|
|
|
|
|
|
* frv-desc.c: Rebuilt.
|
|
|
|
|
|
* frv-desc.h: Rebuilt.
|
|
|
|
|
|
* frv-dis.c: Rebuilt.
|
|
|
|
|
|
* frv-ibld.c: Rebuilt.
|
|
|
|
|
|
* frv-opc.c: Rebuilt.
|
|
|
|
|
|
* frv-opc.h: Rebuilt.
|
|
|
|
|
|
|
2005-01-24 21:01:09 +01:00
|
|
|
|
2005-01-24 Andrew Cagney <cagney@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate, ../gettext.m4 was updated.
|
|
|
|
|
|
|
2005-01-21 20:43:05 +01:00
|
|
|
|
2005-01-21 Fred Fish <fnf@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
|
|
|
|
|
|
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
|
|
|
|
|
|
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
|
|
|
|
|
|
* mips-dis.c: Ditto.
|
|
|
|
|
|
|
2005-01-20 07:54:48 +01:00
|
|
|
|
2005-01-20 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
|
|
|
|
|
|
|
2005-01-20 00:31:15 +01:00
|
|
|
|
2005-01-19 Fred Fish <fnf@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (no_aliases): New disassembly option flag.
|
|
|
|
|
|
(set_default_mips_dis_options): Init no_aliases to zero.
|
|
|
|
|
|
(parse_mips_dis_option): Handle no-aliases option.
|
|
|
|
|
|
(print_insn_mips): Ignore table entries that are aliases
|
|
|
|
|
|
if no_aliases is set.
|
|
|
|
|
|
(print_insn_mips16): Ditto.
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Add initializer column for
|
|
|
|
|
|
new pinfo2 member and add INSN_ALIAS initializers as needed. Also
|
|
|
|
|
|
move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
|
|
|
|
|
|
* mips16-opc.c (mips16_opcodes): Ditto.
|
|
|
|
|
|
|
2005-01-17 15:08:17 +01:00
|
|
|
|
2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
|
|
|
|
|
|
(inheritance diagram): Add missing edge.
|
|
|
|
|
|
(arch_sh1_up): Rename arch_sh_up to match external name to make life
|
|
|
|
|
|
easier for the testsuite.
|
|
|
|
|
|
(arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
|
|
|
|
|
|
(arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
|
2005-02-22 01:33:20 +01:00
|
|
|
|
(arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
|
2005-01-17 15:08:17 +01:00
|
|
|
|
arch_sh2a_or_sh4_up child.
|
|
|
|
|
|
(sh_table): Do renaming as above.
|
|
|
|
|
|
Correct comment for ldc.l for gas testsuite to read.
|
|
|
|
|
|
Remove rogue mul.l from sh1 (duplicate of the one for sh2).
|
|
|
|
|
|
Correct comments for movy.w and movy.l for gas testsuite to read.
|
|
|
|
|
|
Correct comments for fmov.d and fmov.s for gas testsuite to read.
|
|
|
|
|
|
|
2005-01-12 20:40:20 +01:00
|
|
|
|
2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
|
|
|
|
|
|
|
2005-01-12 20:12:52 +01:00
|
|
|
|
2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
|
|
|
|
|
|
|
2005-01-10 10:54:50 +01:00
|
|
|
|
2005-01-10 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassemble_init_for_target) <case
|
|
|
|
|
|
bfd_arch_ia64>: Set skip_zeroes to 16.
|
|
|
|
|
|
<case bfd_arch_tic4x>: Set skip_zeroes to 32.
|
|
|
|
|
|
|
2004-12-23 14:52:11 +01:00
|
|
|
|
2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
|
|
|
|
|
|
|
2004-12-14 23:27:05 +01:00
|
|
|
|
2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* avr-dis.c: Prettyprint. Added printing of symbol names in all
|
|
|
|
|
|
memory references. Convert avr_operand() to C90 formatting.
|
|
|
|
|
|
|
2004-12-05 13:29:04 +01:00
|
|
|
|
2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
|
|
|
|
|
|
|
2004-11-29 17:34:35 +01:00
|
|
|
|
2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
|
|
|
|
|
|
(no_op_insn): Initialize array with instructions that have no
|
|
|
|
|
|
operands.
|
|
|
|
|
|
* crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
|
|
|
|
|
|
|
2004-11-29 11:12:57 +01:00
|
|
|
|
2004-11-29 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Correct top-level comment.
|
|
|
|
|
|
|
2004-11-27 12:09:21 +01:00
|
|
|
|
2004-11-27 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
|
|
|
|
|
|
architecuture defining the insn.
|
|
|
|
|
|
(arm_opcodes, thumb_opcodes): Delete. Move to ...
|
2004-11-27 12:18:29 +01:00
|
|
|
|
* arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
|
|
|
|
|
|
field.
|
2004-11-27 12:09:21 +01:00
|
|
|
|
Also include opcode/arm.h.
|
|
|
|
|
|
* Makefile.am (arm-dis.lo): Update dependency list.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2004-11-22 18:44:03 +01:00
|
|
|
|
2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
|
|
|
|
|
|
reflect the change to the short immediate syntax.
|
|
|
|
|
|
|
2004-11-19 13:34:13 +01:00
|
|
|
|
2004-11-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
2004-11-19 13:38:56 +01:00
|
|
|
|
* or32-opc.c (debug): Warning fix.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2004-11-19 13:34:13 +01:00
|
|
|
|
* maxq-dis.c: Formatting.
|
|
|
|
|
|
(print_insn): Warning fix.
|
|
|
|
|
|
|
bfd/
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
2004-11-17 18:50:28 +01:00
|
|
|
|
2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (WORD_ADDRESS): Define.
|
|
|
|
|
|
(print_insn): Use it. Correct big-endian end-of-section handling.
|
|
|
|
|
|
|
2004-11-09 15:53:56 +01:00
|
|
|
|
2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
|
|
|
|
|
|
Vineet Sharma <vineets@noida.hcltech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* maxq-dis.c: New file.
|
|
|
|
|
|
* disassemble.c (ARCH_maxq): Define.
|
2005-02-22 01:33:20 +01:00
|
|
|
|
(disassembler): Add 'print_insn_maxq_little' for handling maxq
|
2004-11-09 15:53:56 +01:00
|
|
|
|
instructions..
|
|
|
|
|
|
* configure.in: Add case for bfd_maxq_arch.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* Makefile.am: Add support for maxq-dis.c
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* aclocal.m4: Regenerate.
|
|
|
|
|
|
|
2004-11-05 12:01:00 +01:00
|
|
|
|
2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
|
|
|
|
|
|
mode.
|
|
|
|
|
|
* crx-dis.c: Likewise.
|
|
|
|
|
|
|
Generally, handle CRISv32.
* cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
(struct cris_disasm_data): New type.
(format_reg, format_hex, cris_constraint, print_flags)
(get_opcode_entry): Add struct cris_disasm_data * parameter. All
callers changed.
(format_sup_reg, print_insn_crisv32_with_register_prefix)
(print_insn_crisv32_without_register_prefix)
(print_insn_crisv10_v32_with_register_prefix)
(print_insn_crisv10_v32_without_register_prefix)
(cris_parse_disassembler_options): New functions.
(bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
parameter. All callers changed.
(get_opcode_entry): Call malloc, not xmalloc. Return NULL on
failure.
(cris_constraint) <case 'Y', 'U'>: New cases.
(bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
for constraint 'n'.
(print_with_operands) <case 'Y'>: New case.
(print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
<case 'N', 'Y', 'Q'>: New cases.
(print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
(print_insn_cris_with_register_prefix)
(print_insn_cris_without_register_prefix): Call
cris_parse_disassembler_options.
* cris-opc.c (cris_spec_regs): Mention that this table isn't used
for CRISv32 and the size of immediate operands. New v32-only
entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
Change brp to be v3..v10.
(cris_support_regs): New vector.
(cris_opcodes): Update head comment. New format characters '[',
']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
Add new opcodes for v32 and adjust existing opcodes to accommodate
differences to earlier variants.
(cris_cond15s): New vector.
2004-11-04 15:54:38 +01:00
|
|
|
|
2004-11-04 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
Generally, handle CRISv32.
|
|
|
|
|
|
* cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
|
|
|
|
|
|
(struct cris_disasm_data): New type.
|
|
|
|
|
|
(format_reg, format_hex, cris_constraint, print_flags)
|
|
|
|
|
|
(get_opcode_entry): Add struct cris_disasm_data * parameter. All
|
|
|
|
|
|
callers changed.
|
|
|
|
|
|
(format_sup_reg, print_insn_crisv32_with_register_prefix)
|
|
|
|
|
|
(print_insn_crisv32_without_register_prefix)
|
|
|
|
|
|
(print_insn_crisv10_v32_with_register_prefix)
|
|
|
|
|
|
(print_insn_crisv10_v32_without_register_prefix)
|
|
|
|
|
|
(cris_parse_disassembler_options): New functions.
|
|
|
|
|
|
(bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
|
|
|
|
|
|
parameter. All callers changed.
|
|
|
|
|
|
(get_opcode_entry): Call malloc, not xmalloc. Return NULL on
|
|
|
|
|
|
failure.
|
|
|
|
|
|
(cris_constraint) <case 'Y', 'U'>: New cases.
|
|
|
|
|
|
(bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
|
|
|
|
|
|
for constraint 'n'.
|
|
|
|
|
|
(print_with_operands) <case 'Y'>: New case.
|
|
|
|
|
|
(print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
|
|
|
|
|
|
<case 'N', 'Y', 'Q'>: New cases.
|
|
|
|
|
|
(print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
|
|
|
|
|
|
(print_insn_cris_with_register_prefix)
|
|
|
|
|
|
(print_insn_cris_without_register_prefix): Call
|
|
|
|
|
|
cris_parse_disassembler_options.
|
|
|
|
|
|
* cris-opc.c (cris_spec_regs): Mention that this table isn't used
|
|
|
|
|
|
for CRISv32 and the size of immediate operands. New v32-only
|
|
|
|
|
|
entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
|
|
|
|
|
|
spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
|
|
|
|
|
|
ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
|
|
|
|
|
|
Change brp to be v3..v10.
|
|
|
|
|
|
(cris_support_regs): New vector.
|
|
|
|
|
|
(cris_opcodes): Update head comment. New format characters '[',
|
|
|
|
|
|
']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
|
|
|
|
|
|
Add new opcodes for v32 and adjust existing opcodes to accommodate
|
|
|
|
|
|
differences to earlier variants.
|
|
|
|
|
|
(cris_cond15s): New vector.
|
|
|
|
|
|
|
gas/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
2004-11-04 10:16:09 +01:00
|
|
|
|
2004-11-04 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
|
|
|
|
|
|
(indirEb): Remove.
|
|
|
|
|
|
(Mp): Use f_mode rather than none at all.
|
|
|
|
|
|
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
|
|
|
|
|
|
replaces what previously was x_mode; x_mode now means 128-bit SSE
|
|
|
|
|
|
operands.
|
|
|
|
|
|
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
|
|
|
|
|
|
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
|
|
|
|
|
|
pinsrw's second operand is Edqw.
|
|
|
|
|
|
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
|
|
|
|
|
|
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
|
|
|
|
|
|
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
|
|
|
|
|
|
mode when an operand size override is present or always suffixing.
|
|
|
|
|
|
More instructions will need to be added to this group.
|
|
|
|
|
|
(putop): Handle new macro chars 'C' (short/long suffix selector),
|
|
|
|
|
|
'I' (Intel mode override for following macro char), and 'J' (for
|
|
|
|
|
|
adding the 'l' prefix to far branches in AT&T mode). When an
|
|
|
|
|
|
alternative was specified in the template, honor macro character when
|
|
|
|
|
|
specified for Intel mode.
|
|
|
|
|
|
(OP_E): Handle new *_mode values. Correct pointer specifications for
|
|
|
|
|
|
memory operands. Consolidate output of index register.
|
|
|
|
|
|
(OP_G): Handle new *_mode values.
|
|
|
|
|
|
(OP_I): Handle const_1_mode.
|
|
|
|
|
|
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
|
|
|
|
|
|
respective opcode prefix bits have been consumed.
|
|
|
|
|
|
(OP_EM, OP_EX): Provide some default handling for generating pointer
|
|
|
|
|
|
specifications.
|
|
|
|
|
|
|
2004-10-28 12:31:14 +02:00
|
|
|
|
2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c (REV_COP_INST): New macro, reverse operand order of
|
|
|
|
|
|
COP_INST macro.
|
|
|
|
|
|
|
2004-10-27 12:27:00 +02:00
|
|
|
|
2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
|
|
|
|
|
|
(getregliststring): Support HI/LO and user registers.
|
2005-02-22 01:33:20 +01:00
|
|
|
|
* crx-opc.c (crx_instruction): Update data structure according to the
|
2004-10-27 12:27:00 +02:00
|
|
|
|
rearrangement done in CRX opcode header file.
|
|
|
|
|
|
(crx_regtab): Likewise.
|
|
|
|
|
|
(crx_optab): Likewise.
|
2005-02-22 01:33:20 +01:00
|
|
|
|
(crx_instruction): Reorder load/stor instructions, remove unsupported
|
2004-10-27 12:27:00 +02:00
|
|
|
|
formats.
|
|
|
|
|
|
support new Co-Processor instruction 'cpi'.
|
|
|
|
|
|
|
2004-10-27 11:30:09 +02:00
|
|
|
|
2004-10-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/iq2000-asm.c: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-desc.c: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-desc.h: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-dis.c: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-ibld.c: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-opc.c: Regenerate.
|
|
|
|
|
|
* opcodes/iq2000-opc.h: Regenerate.
|
|
|
|
|
|
|
2004-10-25 11:47:25 +02:00
|
|
|
|
2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
|
|
|
|
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us4, us5 (respectively).
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Remove unsupported 'popa' instruction.
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Reverse operands order in store co-processor instructions.
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2004-10-15 07:49:33 +02:00
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2004-10-15 Alan Modra <amodra@bigpond.net.au>
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* Makefile.am: Run "make dep-am"
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* Makefile.in: Regenerate.
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2004-10-12 20:33:17 +02:00
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2004-10-12 Bob Wilson <bob.wilson@acm.org>
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* xtensa-dis.c: Use ISO C90 formatting.
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2004-10-09 03:21:03 +02:00
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2004-10-09 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c: Revert 2004-09-09 change.
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bfd ChangeLog
* elf32-xtensa.c (elf32xtensa_size_opt): New global variable.
(xtensa_default_isa): Global variable moved here from xtensa-isa.c.
(elf32xtensa_no_literal_movement): New global variable.
(elf_howto_table): Add entries for new relocations.
(elf_xtensa_reloc_type_lookup): Handle new relocations.
(property_table_compare): When addresses are equal, compare sizes and
various property flags.
(property_table_matches): New.
(xtensa_read_table_entries): Extend to read new property tables. Add
output_addr parameter to indicate that output addresses should be used.
Use bfd_get_section_limit.
(elf_xtensa_find_property_entry): New.
(elf_xtensa_in_literal_pool): Use elf_xtensa_find_property_entry.
(elf_xtensa_check_relocs): Handle new relocations.
(elf_xtensa_do_reloc): Use bfd_get_section_limit. Handle new
relocations. Use new xtensa-isa.h functions.
(build_encoding_error_message): Remove encode_result parameter. Add
new target_address parameter used to detect alignment errors.
(elf_xtensa_relocate_section): Use bfd_get_section_limit. Clean up
error handling. Use new is_operand_relocation function.
(elf_xtensa_combine_prop_entries, elf_xtensa_merge_private_bfd_data):
Use underbar macro for error messages. Formatting.
(get_const16_opcode): New.
(get_l32r_opcode): Add a separate flag for initialization.
(get_relocation_opnd): Operand number is no longer explicit in the
relocation. Change to decode the opcode and analyze its operands.
(get_relocation_slot): New.
(get_relocation_opcode): Add bfd parameter. Use bfd_get_section_limit.
Use new xtensa-isa.h functions to handle multislot instructions.
(is_l32r_relocation): Add bfd parameter. Use is_operand_relocation.
(get_asm_simplify_size, is_alt_relocation, is_operand_relocation,
insn_decode_len, insn_decode_opcode, check_branch_target_aligned,
check_loop_aligned, check_branch_target_aligned_address, narrowable,
widenable, narrow_instruction, widen_instruction, op_single_fmt_table,
get_single_format, init_op_single_format_table): New.
(elf_xtensa_do_asm_simplify): Add error_message parameter and use it
instead of calling _bfd_error_handler. Use new xtensa-isa.h functions.
(contract_asm_expansion): Add error_message parameter and pass it to
elf_xtensa_do_asm_simplify. Replace use of R_XTENSA_OP0 relocation
with R_XTENSA_SLOT0_OP.
(get_expanded_call_opcode): Extend to handle either L32R or CONST16
instructions. Use new xtensa-isa.h functions.
(r_reloc struct): Add new virtual_offset field.
(r_reloc_init): Add contents and content_length parameters. Set
virtual_offset field to zero. Add contents to target_offset field for
partial_inplace relocations.
(r_reloc_is_defined): Check for null.
(print_r_reloc): New debug function.
(source_reloc struct): Replace xtensa_operand field with pair of the
opcode and the operand position. Add is_abs_literal field.
(init_source_reloc): Specify operand by opcode/position pair. Set
is_abs_literal field.
(source_reloc_compare): When target_offsets are equal, compare other
fields to make sorting predictable.
(literal_value struct): Add is_abs_literal field.
(value_map_hash_table struct): Add has_last_loc and last_loc fields.
(init_literal_value): New.
(is_same_value): Replace with ...
(literal_value_equal): ... this function. Add comparisons of
virtual_offset and is_abs_literal fields.
(value_map_hash_table_init): Use bfd_zmalloc. Check for allocation
failure. Initialize has_last_loc field.
(value_map_hash_table_delete): New.
(hash_literal_value): Rename to ...
(literal_value_hash): ... this. Include is_abs_literal flag and
virtual_offset field in the hash value.
(get_cached_value): Rename to ...
(value_map_get_cached_value): ... this. Update calls to
literal_value_hash and literal_value_equal.
(add_value_map): Check for allocation failure. Update calls to
value_map_get_cached_value and literal_value_hash.
(text_action, text_action_list, text_action_t): New types.
(find_fill_action, compute_removed_action_diff, adjust_fill_action,
text_action_add, text_action_add_literal, offset_with_removed_text,
offset_with_removed_text_before_fill, find_insn_action,
print_action_list, print_removed_literals): New.
(offset_with_removed_literals): Delete.
(xtensa_relax_info struct): Add is_relaxable_asm_section, action_list,
fix_array, fix_array_count, allocated_relocs, relocs_count, and
allocated_relocs_count fields.
(init_xtensa_relax_info): Initialize new fields.
(reloc_bfd_fix struct): Add new translated field.
(reloc_bfd_fix_init): Add translated parameter and use it to set the
translated field.
(fix_compare, cache_fix_array): New.
(get_bfd_fix): Remove fix_list parameter and get all relax_info for the
section via get_xtensa_relax_info. Use cache_fix_array to set up
sorted fix_array and use bsearch instead of linear search.
(section_cache_t): New struct.
(init_section_cache, section_cache_section, clear_section_cache): New.
(ebb_t, ebb_target_enum, proposed_action, ebb_constraint): New types.
(init_ebb_constraint, free_ebb_constraint, init_ebb, extend_ebb_bounds,
extend_ebb_bounds_forward, extend_ebb_bounds_backward,
insn_block_decodable_len, ebb_propose_action, ebb_add_proposed_action):
New.
(retrieve_contents): Use bfd_get_section_limit.
(elf_xtensa_relax_section): Add relocations_analyzed flag. Update call
to compute_removed_literals. Free value_map_hash_table when no longer
needed.
(analyze_relocations): Check is_relaxable_asm_section flag. Call
compute_text_actions for all sections.
(find_relaxable_sections): Mark sections as relaxable if they contain
ASM_EXPAND relocations that can be optimized. Adjust r_reloc_init
call. Increment relax_info src_count field only for appropriate
relocation types. Remove is_literal_section check.
(collect_source_relocs): Use bfd_get_section_limit. Adjust calls to
r_reloc_init and find_associated_l32r_irel. Check
is_relaxable_asm_section flag. Handle L32R instructions with absolute
literals. Pass is_abs_literal flag to init_source_reloc.
(is_resolvable_asm_expansion): Use bfd_get_section_limit. Check for
CONST16 instructions. Adjust calls to r_reloc_init and
pcrel_reloc_fits. Handle weak symbols conservatively.
(find_associated_l32r_irel): Add bfd parameter and pass it to
is_l32r_relocation.
(compute_text_actions, compute_ebb_proposed_actions,
compute_ebb_actions, check_section_ebb_pcrels_fit,
check_section_ebb_reduces, text_action_add_proposed,
compute_fill_extra_space): New.
(remove_literals): Replace with ...
(compute_removed_literals): ... this function. Call
init_section_cache. Use bfd_get_section_limit. Sort internal_relocs.
Call xtensa_read_table_entries to get the property table. Skip
relocations other than R_XTENSA_32 and R_XTENSA_PLT. Use new
is_removable_literal, remove_dead_literal, and
identify_literal_placement functions.
(get_irel_at_offset): Rewrite to use bsearch on sorted relocations
instead of linear search.
(is_removable_literal, remove_dead_literal,
identify_literal_placement): New.
(relocations_reach): Update check for literal not referenced by any
PC-relative relocations. Adjust call to pcrel_reloc_fits.
(coalesce_shared_literal, move_shared_literal): New.
(relax_section): Use bfd_get_section_limit. Call
translate_section_fixes. Update calls to r_reloc_init and
offset_with_removed_text. Check new is_relaxable_asm_section flag.
Add call to pin_internal_relocs. Add special handling for
R_XTENSA_ASM_SIMPLIFY and R_XTENSA_DIFF* relocs. Use virtual_offset
info to calculate new addend_displacement variable. Replace code for
deleting literals with more general code to perform the actions
determined by the action_list for the section.
(translate_section_fixes, translate_reloc_bfd_fix): New.
(translate_reloc): Check new is_relaxable_asm_section flag. Call
find_removed_literal only if is_operand_relocation. Update call to
offset_with_removed_text. Use new target_offset and removed_bytes
variables.
(move_literal): New.
(relax_property_section): Use bfd_get_section_limit. Set new
is_full_prop_section flag and handle new property tables. Update calls
to r_reloc_init and offset_with_removed_text. Check
is_relaxable_asm_section flag. Handle expansion of zero-sized
unreachable entries, with use of offset_with_removed_text_before_fill.
For relocatable links, combine entries only for literal tables.
(relax_section_symbols): Check is_relaxable_asm_section flag. Update
calls to offset_with_removed_text. Translate st_size field for
function symbols.
(do_fix_for_relocatable_link): Change to return bfd_boolean to indicate
failure. Add contents parameter. Update call to get_bfd_fix. Update
call to r_reloc_init. Call _bfd_error_handler and return FALSE for
R_XTENSA_ASM_EXPAND relocs.
(do_fix_for_final_link): Add input_bfd and contents parameters. Update
call to get_bfd_fix. Include offset from contents for partial_inplace
relocations.
(is_reloc_sym_weak): New.
(pcrel_reloc_fits): Use new xtensa-isa.h functions.
(prop_sec_len): New.
(xtensa_is_property_section): Handle new property sections.
(is_literal_section): Delete.
(internal_reloc_compare): When r_offset matches, compare r_info and
r_addend to make sorting predictable.
(internal_reloc_matches): New.
(xtensa_get_property_section_name): Handle new property sections.
(xtensa_get_property_predef_flags): New.
(xtensa_callback_required_dependence): Use bfd_get_section_limit.
Update calls to xtensa_isa_init, is_l32r_relocation, and r_reloc_init.
* xtensa-isa.c (xtensa_default_isa): Moved to elf32-xtensa.c.
(xtisa_errno, xtisa_error_msg): New variables.
(xtensa_isa_errno, xtensa_isa_error_msg): New.
(xtensa_insnbuf_alloc): Add error handling.
(xtensa_insnbuf_to_chars): Add num_chars parameter. Update to
use xtensa_format_decode. Add error handling.
(xtensa_insnbuf_from_chars): Add num_chars parameter. Decode the
instruction length to find the number of bytes to copy.
(xtensa_isa_init): Add error handling. Replace calls to
xtensa_load_isa and xtensa_extend_isa with code to initialize lookup
tables in the xtensa_modules structure.
(xtensa_check_isa_config, xtensa_add_isa, xtensa_load_isa,
xtensa_extend_isa): Delete.
(xtensa_isa_free): Change to only free lookup tables.
(opname_lookup_compare): Replace with ...
(xtensa_isa_name_compare): ... this function. Use strcasecmp.
(xtensa_insn_maxlength): Rename to ...
(xtensa_isa_maxlength): ... this.
(xtensa_insn_length): Delete.
(xtensa_insn_length_from_first_byte): Replace with ...
(xtensa_isa_length_from_chars): ... this function.
(xtensa_num_opcodes): Rename to ...
(xtensa_isa_num_opcodes): ... this.
(xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_regfiles, xtensa_isa_num_stages,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot): New functions.
(xtensa_opcode_lookup): Add error handling.
(xtensa_decode_insn): Replace with ...
(xtensa_opcode_decode): ... this function, with new format and
slot parameters. Add error handling.
(xtensa_encode_insn): Replace with ...
(xtensa_opcode_encode): ... this function, which does the encoding via
one of the entries in the "encode_fns" array. Add error handling.
(xtensa_opcode_name): Add error handling.
(xtensa_opcode_is_branch, xtensa_opcode_is_jump, xtensa_opcode_is_loop,
xtensa_opcode_is_call): New.
(xtensa_num_operands): Replace with ...
(xtensa_opcode_num_operands): ... this function. Add error handling.
(xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible): New.
(xtensa_get_operand, xtensa_operand_kind): Delete.
(xtensa_operand_inout): Add error handling and special-case for
"sout" operands.
(xtensa_operand_get_field, xtensa_operand_set_field): Rewritten to
operate on one slot of an instruction. Added error handling.
(xtensa_operand_encode): Handle default operands with no encoding
functions. Check for success by comparing against decoded value.
Add error handling.
(xtensa_operand_decode): Handle default operands. Return decoded value
through argument pointer. Add error handling.
(xtensa_operand_is_register, xtensa_operand_regfile,
xtensa_operand_num_regs, xtensa_operand_is_known_reg): New.
(xtensa_operand_isPCRelative): Rename to ...
(xtensa_operand_is_PCrelative): ... this. Add error handling.
(xtensa_operand_do_reloc, xtensa_operand_undo_reloc): Return value
through argument pointer. Add error handling.
(xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New.
* xtensa-modules.c: Rewrite to use new data structures.
* reloc.c (BFD_RELOC_XTENSA_DIFF8, BFD_RELOC_XTENSA_DIFF16,
BFD_RELOC_XTENSA_DIFF32, BFD_RELOC_XTENSA_SLOT0_OP,
BFD_RELOC_XTENSA_SLOT1_OP, BFD_RELOC_XTENSA_SLOT2_OP,
BFD_RELOC_XTENSA_SLOT3_OP, BFD_RELOC_XTENSA_SLOT4_OP,
BFD_RELOC_XTENSA_SLOT5_OP, BFD_RELOC_XTENSA_SLOT6_OP,
BFD_RELOC_XTENSA_SLOT7_OP, BFD_RELOC_XTENSA_SLOT8_OP,
BFD_RELOC_XTENSA_SLOT9_OP, BFD_RELOC_XTENSA_SLOT10_OP,
BFD_RELOC_XTENSA_SLOT11_OP, BFD_RELOC_XTENSA_SLOT12_OP,
BFD_RELOC_XTENSA_SLOT13_OP, BFD_RELOC_XTENSA_SLOT14_OP,
BFD_RELOC_XTENSA_SLOT0_ALT, BFD_RELOC_XTENSA_SLOT1_ALT,
BFD_RELOC_XTENSA_SLOT2_ALT, BFD_RELOC_XTENSA_SLOT3_ALT,
BFD_RELOC_XTENSA_SLOT4_ALT, BFD_RELOC_XTENSA_SLOT5_ALT,
BFD_RELOC_XTENSA_SLOT6_ALT, BFD_RELOC_XTENSA_SLOT7_ALT,
BFD_RELOC_XTENSA_SLOT8_ALT, BFD_RELOC_XTENSA_SLOT9_ALT,
BFD_RELOC_XTENSA_SLOT10_ALT, BFD_RELOC_XTENSA_SLOT11_ALT,
BFD_RELOC_XTENSA_SLOT12_ALT, BFD_RELOC_XTENSA_SLOT13_ALT,
BFD_RELOC_XTENSA_SLOT14_ALT): Add new relocations.
* Makefile.am (xtensa-isa.lo, xtensa-modules.lo): Update dependencies.
* Makefile.in: Regenerate.
* bfd-in2.h: Likewise.
* libbfd.h: Likewise.
gas ChangeLog
* config/tc-xtensa.c (absolute_literals_supported): New global flag.
(UNREACHABLE_MAX_WIDTH): Define.
(XTENSA_FETCH_WIDTH): Delete.
(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
prefer_const16, prefer_l32r): New global variables.
(LIT4_SECTION_NAME): Define.
(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
(frag_flags struct): New.
(xtensa_block_info struct): Move from tc-xtensa.h. Add flags field.
(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
(bitfield, bit_is_set, set_bit, clear_bit): Define.
(MAX_FORMATS): Define.
(op_placement_info struct, op_placement_table): New.
(O_pltrel, O_hi16, O_lo16): Define.
(directiveE enum): Rename directive_generics to directive_transform.
Delete directive_relax. Add directive_schedule,
directive_absolute_literals, and directive_last_directive.
(directive_info): Rename "generics" to "transform". Delete "relax".
Add "schedule" and "absolute-literals".
(directive_state): Adjust entries to match changes in directive_info.
(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
(align_only_targets, software_a0_b_retw_interlock,
software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
software_avoid_short_loop, software_avoid_close_loop_end,
software_avoid_all_short_loops, specific_opcode): Delete.
(warn_unaligned_branch_targets): New.
(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
(option_[no_]link_relax, option_[no_]transform,
option_[no_]absolute_literals, option_warn_unaligned_targets,
option_prefer_l32r, option_prefer_const16, option_target_hardware):
New enum values.
(option_[no_]align_only_targets, option_literal_section_name,
option_text_section_name, option_data_section_name,
option_bss_section_name, option_eb, option_el): Delete.
(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
and target-hardware. Delete entries for [no-]target-align-only,
literal-section-name, text-section-name, data-section-name, and
bss-section-name.
(md_parse_option): Handle new options and remove old ones. Accept but
ignore [no-]density options. Warn for [no-]generics and [no-]relax
and treat them as [no-]transform.
(md_show_usage): Add new options and remove old ones.
(xtensa_setup_hw_workarounds): New.
(md_pseudo_table): Change "word" entry to use xtensa_elf_cons. Add
"long", "short", "loc" and "frequency" entries.
(use_generics): Rename to ...
(use_transform): ... this function. Add past_xtensa_end check.
(use_longcalls): Add past_xtensa_end check.
(code_density_available, can_relax): Delete.
(do_align_targets): New.
(get_directive): Accept dashes in directive names. Warn about
[no-]generics and [no-]relax directives and treat them as
[no-]transform.
(xtensa_begin_directive): Call md_flush_pending_output only for some
directives. Check for directives inside instruction bundles. Warn
about deprecated ".begin literal" usage. Warn and ignore [no-]density
directives. Handle new directives. Check generating_literals flag
for literal_prefix.
(xtensa_end_directive): Check for directives inside instruction
bundles. Warn and ignore [no-]density directives. Handle new
directives. Call xtensa_set_frag_assembly_state.
(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
xtensa_dwarf2_emit_insn): New.
(xtensa_literal_position): Call md_flush_pending_output. Do not check
use_literal_section flag.
(xtensa_literal_pseudo): Call md_flush_pending_output. Handle absolute
literals. Use xtensa_elf_cons to parse the expression.
(xtensa_literal_prefix): Do not check use_literal_section. Support
".lit4" sections for absolute literals. Change prefix convention to
replace ".text" (or ".t" in a linkonce section). No need to call
subseg_set.
(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
(expression_end): Handle closing braces and colons.
(PLT_SUFFIX, plt_suffix): Delete.
(expression_maybe_register): Use new xtensa-isa.h functions. Use
xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
and O_hi16 expressions as well.
(tokenize_arguments): Handle closing braces and colons.
(parse_arguments): Use new xtensa-isa.h functions. Handle "invisible"
operands and paired register syntax.
(get_invisible_operands): New.
(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax. Use
new xtensa-isa.h functions.
(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
(xg_translate_idioms): Check if inside bundle. Use use_transform.
Handle new Xtensa LX RSR/WSR/XSR syntax. Remove code to widen density
instructions. Use xtensa_translate_zero_immed.
(operand_is_immed, operand_is_pcrel_label): Delete.
(get_relaxable_immed): Use new xtensa-isa.h functions.
(get_opcode_from_buf): Add slot parameter. Use new xtensa-isa.h
functions.
(xtensa_print_insn_table, print_vliw_insn): New.
(is_direct_call_opcode): Use new xtensa-isa.h functions.
(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
is_branch_or_jump_opcode): Delete.
(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
(opnum_to_reloc, reloc_to_opnum): Delete.
(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
xtensa-isa.h functions. Operate on one slot of an instruction.
(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
xg_get_insn_size): Delete.
(xg_get_build_instr_size): Use xg_get_single_size.
(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_get_max_narrow_insn_size): Delete.
(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
xg_is_relaxable_insn): Update calls to xg_build_widen_table. Use
xg_get_single_size.
(xg_build_to_insn): Record the loc field. Handle OP_OPERAND_HI16U and
OP_OPERAND_LOW16U. Check xg_valid_literal_expression.
(xg_expand_to_stack, xg_expand_narrow): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_immeds_fit): Use new xtensa-isa.h functions. Update call to
xg_check_operand.
(xg_symbolic_immeds_fit): Likewise. Also handle O_lo16 and O_hi16, and
treat weak symbols conservatively.
(xg_check_operand): Use new xtensa-isa.h functions.
(is_dnrange): Delete.
(xg_assembly_relax): Inline previous calls to tinsn_copy.
(xg_finish_frag): Specify separate relax states for the frag and slot0.
(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
xtensa-isa.h functions.
(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
xg_instruction_matches_options): New.
(xg_instruction_matches_rule): Handle O_register expressions. Call
xg_instruction_matches_options.
(transition_rule_cmp): New.
(xg_instruction_match): Update call to xg_build_simplify_table.
(xg_build_token_insn): Record loc fields.
(xg_simplify_insn): Check is_specific_opcode field and
density_supported flag.
(xg_expand_assembly_insn): Skip checking code_density_available. Use
new xtensa-isa.h functions. Call use_transform instead of can_relax.
(xg_assemble_literal): Add error handling for O_big. Call
record_alignment. Handle O_pltrel.
(xg_valid_literal_expression): New.
(xg_assemble_literal_space): Add slot parameter. Remove call to
set_expr_symbol_offset. Add call to record_alignment. Update call to
xg_finish_frag.
(xg_emit_insn): Delete.
(xg_emit_insn_to_buf): Add format parameter. Update calls to
xg_add_opcode_fix and xtensa_insnbuf_to_chars.
(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
and slot parameters. Handle new "alternate" relocations for absolute
literals and CONST16 instructions. Check for bad uses of O_lo16 and
O_hi16. Use new xtensa-isa.h functions.
(xg_assemble_tokens): Delete.
(is_register_writer): Use new xtensa-isa.h functions.
(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
old-style RSR from LCOUNT.
(next_frag_opcode): Delete.
(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
update_next_frag_state): New.
(update_next_frag_nop_state): Delete.
(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
(xtensa_mark_literal_pool_location): Check use_literal_section flag and
the state of the absolute-literals directive. Add calls to
record_alignment and xtensa_set_frag_assembly_state. Call
xtensa_switch_to_non_abs_literal_fragment instead of
xtensa_switch_to_literal_fragment.
(build_nop): New.
(assemble_nop): Use build_nop. Update call to xtensa_insnbuf_to_chars.
(get_expanded_loop_offset): Change check for undefined opcode to an
assertion.
(xtensa_set_frag_assembly_state, relaxable_section,
xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
(md_begin): Update call to xtensa_isa_init. Initialize linkrelax to 1.
Set lit4_seg_name. Call xg_init_vinsn. Initialize new global opcodes.
Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
(xtensa_init_fix_data): New.
(xtensa_frob_label): Reset label symbol to the current frag. Check
do_align_targets and generating_literals flag. Propagate frequency
info to new alignment frag. Call xtensa_set_frag_assembly_state.
(xtensa_unrecognized_line): New.
(xtensa_flush_pending_output): Check if inside a bundle. Add a call
to xtensa_set_frag_assembly_state.
(error_reset_cur_vinsn): New.
(md_assemble): Remove check for literal frag. Remove call to
istack_init. Call use_transform instead of use_generics. Parse
explicit instruction format specifiers. Move code for
a0_b_retw_interlock workaround to xg_assemble_vliw_tokens. Call
error_reset_cur_vinsn on errors. Add call to get_invisible_operands.
Add dwarf2_where call. Remote automatic alignment for ENTRY
instructions. Move call to xtensa_clear_insn_labels to the end.
Rearrange to handle bundles.
(xtensa_cons_fix_new): Delete.
(xtensa_handle_align): New.
(xtensa_frag_init): Call xtensa_set_frag_assembly_state. Remove
assignment to is_no_density field.
(md_pcrel_from): Use new xtensa-isa.h functions. Use decode_reloc
instead of reloc_to_opnum. Handle "alternate" relocations.
(xtensa_force_relocation, xtensa_check_inside_bundle,
xtensa_elf_section_change_hook): New.
(xtensa_symbol_new_hook): Delete.
(xtensa_fix_adjustable): Check for difference of symbols with an
offset. Check for external and weak symbols.
(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
(md_estimate_size_before_relax): Return expansion for the first slot.
(tc_gen_reloc): Handle difference of symbols by producing
XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
into the output. Handle new XTENSA_SLOT*_OP relocs by storing the
tentative values into the output when linkrelax is set.
(XTENSA_PROP_SEC_NAME): Define.
(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
Create literal tables only if using literal sections. Create new
property tables instead of old instruction tables. Check for unaligned
branch targets and loops.
(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
new_resource_table, clear_resource_table, resize_resource_table,
resources_available, reserve_resources, release_resources,
opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
resources_conflict, xg_find_narrowest_format, relaxation_requirements,
bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
(xtensa_end): Call xtensa_flush_pending_output. Set past_xtensa_end
flag. Update checks for workaround options. Call
xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
(xtensa_cleanup_align_frags): Add special case for branch targets.
Check for and mark unreachable frags.
(xtensa_fix_target_frags): Remove use of align_only_targets flag.
Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
end of a zero-overhead loop body.
(frag_can_negate_branch): Handle instructions with multiple slots.
Use new xtensa-isa.h functions
(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
xtensa_mark_zcl_first_insns): New.
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
transformations are disabled.
(next_instrs_are_b_retw): Use new xtensa-isa.h functions. Handle
multislot instructions.
(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
Likewise. Also error if transformations are disabled.
(unrelaxed_frag_max_size): New.
(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
xtensa-isa.h functions.
(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
xtensa_opcode_is_loop instead of is_loop_opcode.
(get_text_align_power): Replace as_fatal with assertion.
(get_text_align_fill_size): Iterate instead of using modulus when
use_nops is false.
(get_noop_aligned_address): Assert that this is for a machine-dependent
RELAX_ALIGN_NEXT_OPCODE frag. Use next_frag_opcode_is_loop,
xg_get_single_size, and frag_format_size.
(get_widen_aligned_address): Rename to ...
(get_aligned_diff): ... this function. Add max_diff parameter.
Remove handling of rs_align/rs_align_code frags. Use
next_frag_format_size, get_text_align_power, get_text_align_fill_size,
next_frag_opcode_is_loop, and xg_get_single_size. Compute max_diff
and pass it back to caller.
(xtensa_relax_frag): Use relax_frag_loop_align. Add code for new
RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types. Check relax_seen.
(relax_frag_text_align): Rename to ...
(relax_frag_loop_align): ... this function. Assume loops can only be
in the first slot of an instruction.
(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
instruction. Remove call to frag_wane.
(relax_frag_narrow): Rename to ...
(relax_frag_for_align): ... this function. Extend to handle
RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
RELAX_NARROW for the first slot.
(find_address_of_next_align_frag, bytes_to_stretch): New.
(future_alignment_required): Use find_address_of_next_align_frag and
bytes_to_stretch. Look ahead to subsequent frags to make smarter
alignment decisions.
(relax_frag_immed): Add format, slot, and estimate_only parameters.
Check if transformations are enabled for b_j_loop_end workaround.
Use new xtensa-isa.h functions and handle multislot instructions.
Update call to xg_assembly_relax.
(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
frag types.
(convert_frag_narrow): Add segP, format and slot parameters. Call
convert_frag_immed for branch instructions. Adjust calls to
tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf. Use
xg_get_single_size and xg_get_single_format.
(convert_frag_fill_nop): New.
(convert_frag_immed): Add format and slot parameters. Handle multislot
instructions and use new xtensa-isa.h functions. Update calls to
tinsn_immed_from_frag and xg_assembly_relax. Check if transformations
enabled for b_j_loop_end workaround. Use build_nop instead of
assemble_nop. Check is_specific_opcode flag. Check for unreachable
frags. Use xg_get_single_size. Handle O_pltrel.
(fix_new_exp_in_seg): Remove check for old plt flag.
(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
xtensa_insnbuf_to_chars. Call tinsn_immed_from_frag. Change check
for loop opcode to an assertion. Mark all frags up to the end of the
loop as not transformable.
(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
(get_subseg_info): New.
(xtensa_move_literals): Call xtensa_set_frag_assembly_state. Add null
check for dest_seg.
(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
(xtensa_switch_to_non_abs_literal_fragment): New.
(cache_literal_section): Add is_code parameter and pass it through to
retrieve_literal_seg.
(retrieve_literal_seg): Add is_code parameter and use it to set the
flags on the literal section. Handle case where head parameter is 0.
(get_frag_is_no_transform, set_frag_is_specific_opcode,
set_frag_is_no_transform): New.
(xtensa_create_property_segments): Add end_property_function parameter
and pass it through to add_xt_block_frags. Call bfd_get_section_flags
and skip SEC_DEBUGGING and !SEC_ALLOC sections.
(xtensa_create_xproperty_segments, section_has_xproperty): New.
(add_xt_block_frags): Add end_property_function parameter and call it
if it is non-zero. Call xtensa_frag_flags_init.
(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
get_frag_property_flags, frag_flags_to_number,
xtensa_frag_flags_combinable, xt_block_aligned_size,
xtensa_xt_block_combine, add_xt_prop_frags,
init_op_placement_info_table, opcode_fits_format_slot,
xg_get_single_size, xg_get_single_format): New.
(istack_push): Inline call to tinsn_copy.
(tinsn_copy): Delete.
(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
CONST16 opcodes. Handle O_big, O_illegal, and O_absent.
(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
functions. Handle invisible operands.
(tinsn_to_slotbuf): New.
(tinsn_check_arguments): Use new xtensa-isa.h functions.
(tinsn_from_chars): Add slot parameter. Rewrite using xg_init_vinsn,
vinsn_from_chars, and xg_free_vinsn.
(tinsn_from_insnbuf): New.
(tinsn_immed_from_frag): Add slot parameter and handle multislot
instructions. Handle symbol differences.
(get_num_stack_text_bytes): Use xg_get_single_size.
(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
get_expr_register, set_expr_symbol_offset_diff): New.
* config/tc-xtensa.h (MAX_SLOTS): Define.
(xtensa_relax_statesE): Move from tc-xtensa.c. Add
RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
RELAX_NONE types.
(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
(xtensa_frag_type struct): Add is_assembly_state_set,
use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
is_align, is_text_align, alignment, and is_first_loop_insn fields.
Replace is_generics and is_relax fields by is_no_transform field.
Delete is_text and is_longcalls fields. Change text_expansion and
literal_expansion to arrays of MAX_SLOTS entries. Add arrays of
per-slot information: literal_frags, slot_subtypes, slot_symbols,
slot_sub_symbols, and slot_offsets. Add fr_prev field.
(xtensa_fix_data struct): New.
(xtensa_symfield_type struct): Delete plt field.
(xtensa_block_info struct): Move definition to tc-xtensa.h. Add
forward declaration here.
(xt_section_type enum): Delete xt_insn_sec. Add xt_prop_sec.
(XTENSA_SECTION_RENAME): Undefine.
(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
(unit_num_copies_func, opcode_num_units_func,
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
(resource_table struct): New.
* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
literal_space, symbol, sub_symbol, offset, and literal_frag fields.
(tinsn_copy): Delete prototype.
(vliw_insn struct): New.
* config/xtensa-relax.c (insn_pattern_struct): Add options field.
(widen_spec_list): Add option conditions for density and boolean
instructions. Add expansions using CONST16 and conditions for using
CONST16 vs. L32R. Use new Xtensa LX RSR/WSR syntax. Add entries for
predicted branches.
(simplify_spec_list): Add option conditions for density instructions.
Add entry for NOP instruction.
(append_transition): Add cmp function pointer parameter and use it to
insert the new entry in order.
(operand_function_LOW16U, operand_function_HI16U): New.
(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(enter_opname, split_string): Use xstrdup instead of strdup.
(init_insn_pattern): Initialize new options field.
(clear_req_or_option_list, clear_req_option_list,
clone_req_or_option_list, clone_req_option_list, parse_option_cond):
New.
(parse_insn_pattern): Parse option conditions.
(transition_applies): New.
(build_transition): Use new xtensa-isa.h functions. Fix incorrectly
swapped last arguments in calls to append_constant_value_condition.
Call clone_req_option_list. Add warning about invalid opcode.
Handle LOW16U and HI16U function names.
(build_transition_table): Add cmp parameter and use it in calls to
append_transition. Use new xtensa-isa.h functions. Check
transition_applies before adding entries.
(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
pass it through to build_transition_table.
* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
ReqOption, transition_cmp_fn): New types.
(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(transition_rule struct): Add options field.
* doc/as.texinfo (Overview): Update Xtensa options.
* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
--[no-]relax, and --[no-]generics options. Update descriptions of
--text-section-literals and --[no-]longcalls. Add
--[no-]absolute-literals and --[no-]transform.
(Xtensa Syntax): Add description of syntax for FLIX instructions.
Remove use of "generic" and "specific" terminology for opcodes.
(Xtensa Registers): Generalize the syntax description to include
user-defined register files.
(Xtensa Automatic Alignment): Update.
(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
(Xtensa Call Relaxation): Linker can now remove most of the overhead.
(Xtensa Directives): Remove confusing rules about precedence.
(Density Directive, Relax Directive): Delete.
(Schedule Directive): New.
(Generics Directive): Rename to ...
(Transform Directive): ... this node.
(Literal Directive): Update for absolute literals. Missing
literal_position directive is now an error.
(Literal Position Directive): Update for absolute literals.
(Freeregs Directive): Delete.
(Absolute Literals Directive): New.
(Frame Directive): Minor editing.
* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
Update dependencies.
* Makefile.in: Regenerate.
gas/testsuite ChangeLog
* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
Change entry_align test to expect an error.
* gas/xtensa/entry_misalign2.s: Use no-transform instead of
no-generics directives.
include ChangeLog
* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
(config_sturct struct): Delete.
(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
(xtensa_insn_decode_fn): Rename to ...
(xtensa_opcode_decode_fn): ... this.
(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
xtensa_undo_reloc_fn): Update.
(xtensa_encoding_template_fn): Delete.
(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
xtensa_length_decode_fn): New.
(xtensa_format_internal, xtensa_slot_internal): New types.
(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
get_field, and set_field fields. Add name, field_id, regfile,
num_regs, and flags fields.
(xtensa_arg_internal): New type.
(xtensa_iclass_internal): Change operands field to array of
xtensa_arg_internal. Add num_stateOperands, stateOperands,
num_interfaceOperands, and interfaceOperands fields.
(xtensa_opcode_internal): Delete length, template, and iclass fields.
Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
(opname_lookup_entry): Delete.
(xtensa_regfile_internal, xtensa_interface_internal,
xtensa_funcUnit_internal, xtensa_state_internal,
xtensa_sysreg_internal, xtensa_lookup_entry): New.
(xtensa_isa_internal): Replace opcode_table field with opcodes field.
Change type of opname_lookup_table. Delete num_modules,
module_opcode_base, module_decode_fn, config, and has_density fields.
Add num_formats, formats, format_decode_fn, length_decode_fn,
num_slots, slots, num_fields, num_operands, operands, num_iclasses,
iclasses, num_regfiles, regfiles, num_states, states,
state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
max_sysreg_num, sysreg_table, num_interfaces, interfaces,
interface_lookup_table, num_funcUnits, funcUnits and
funcUnit_lookup_table fields.
(xtensa_isa_module, xtensa_isa_modules): Delete.
(xtensa_isa_name_compare): New prototype.
(xtisa_errno, xtisa_error_msg): New.
* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
(xtensa_isa): Change type.
(xtensa_operand): Delete.
(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
xtensa_funcUnit_use): New types.
(libisa_module_specifier): Delete.
(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
xtensa_insnbuf_from_chars): Update prototypes.
(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
xtensa_encode_insn, xtensa_insn_length,
xtensa_insn_length_from_first_byte, xtensa_num_operands,
xtensa_operand_kind, xtensa_encode_result,
xtensa_operand_isPCRelative): Delete.
(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
xtensa_operand_set_field, xtensa_operand_encode,
xtensa_operand_decode, xtensa_operand_do_reloc,
xtensa_operand_undo_reloc): Update prototypes.
(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
xtensa_opcode_is_loop, xtensa_opcode_is_call,
xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible, xtensa_operand_is_register,
xtensa_operand_regfile, xtensa_operand_num_regs,
xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
* elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
(XTENSA_PROP_SEC_NAME): Define.
(property_table_entry): Add flags field.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
ld ChangeLog
* ld.texinfo (Xtensa): Describe new linker relaxation to optimize
assembler-generated longcall sequences. Describe new --size-opt
option.
* emulparams/elf32xtensa.sh (OTHER_SECTIONS): Add .xt.prop section.
* emultempl/xtensaelf.em (remove_section,
replace_insn_sec_with_prop_sec, replace_instruction_table_sections,
elf_xtensa_after_open): New.
(OPTION_OPT_SIZEOPT, OPTION_LITERAL_MOVEMENT,
OPTION_NO_LITERAL_MOVEMENT): Define.
(elf32xtensa_size_opt, elf32xtensa_no_literal_movement): New globals.
(PARSE_AND_LIST_LONGOPTS): Add size-opt and [no-]literal-movement.
(PARSE_AND_LIST_OPTIONS): Add --size-opt.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_OPT_SIZEOPT,
OPTION_LITERAL_MOVEMENT, and OPTION_NO_LITERAL_MOVEMENT.
(LDEMUL_AFTER_OPEN): Set to elf_xtensa_after_open.
* scripttempl/elfxtensa.sc: Update with changes from elf.sc.
* Makefile.am (eelf32xtensa.c): Update dependencies.
* Makefile.in: Regenerate.
ld/testsuite ChangeLog
* ld-xtensa/lcall1.s: Use .literal directive.
* ld-xtensa/lcall2.s: Align function entry.
* ld-xtensa/coalesce2.s: Likewise.
opcodes ChangeLog
* xtensa-dis.c (state_names): Delete.
(fetch_data): Use xtensa_isa_maxlength.
(print_xtensa_operand): Replace operand parameter with opcode/operand
pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
(print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
instruction bundles. Use xmalloc instead of malloc.
2004-10-08 02:22:15 +02:00
|
|
|
|
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* xtensa-dis.c (state_names): Delete.
|
|
|
|
|
|
(fetch_data): Use xtensa_isa_maxlength.
|
|
|
|
|
|
(print_xtensa_operand): Replace operand parameter with opcode/operand
|
|
|
|
|
|
pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
|
|
|
|
|
|
(print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
|
|
|
|
|
|
instruction bundles. Use xmalloc instead of malloc.
|
|
|
|
|
|
|
2004-10-07 17:34:08 +02:00
|
|
|
|
2004-10-07 David Gibson <david@gibson.dropbear.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c: Replace literal "0"s with NULLs in pointer
|
|
|
|
|
|
initializers.
|
|
|
|
|
|
|
2004-10-07 16:18:17 +02:00
|
|
|
|
2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c (crx_instruction): Support Co-processor insns.
|
|
|
|
|
|
* crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
|
|
|
|
|
|
(getregliststring): Change function to use the above enum.
|
|
|
|
|
|
(print_arg): Handle CO-Processor insns.
|
|
|
|
|
|
(crx_cinvs): Add 'b' option to invalidate the branch-target
|
|
|
|
|
|
cache.
|
|
|
|
|
|
|
* opcodes/ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
2004-10-07 01:58:13 +02:00
|
|
|
|
2004-10-06 Aldy Hernandez <aldyh@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
|
|
|
|
|
|
efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
|
|
|
|
|
|
efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
|
|
|
|
|
|
efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
|
|
|
|
|
|
efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
|
|
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|
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|
|
2004-10-01 13:19:38 +02:00
|
|
|
|
2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
|
|
|
|
|
|
|
|
|
|
|
|
* pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
|
|
|
|
|
|
rather than add it.
|
|
|
|
|
|
|
2004-09-30 18:21:50 +02:00
|
|
|
|
2004-09-30 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
|
|
|
|
|
|
* arm-opc.h: Document %e. Add ARMv6ZK instructions.
|
|
|
|
|
|
|
2004-09-17 19:04:34 +02:00
|
|
|
|
2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
|
|
|
|
|
|
(CONFIG_STATUS_DEPENDENCIES): New.
|
|
|
|
|
|
(Makefile): Removed.
|
|
|
|
|
|
(config.status): Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
|
2004-09-17 08:13:39 +02:00
|
|
|
|
2004-09-17 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Run "make dep-am".
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* aclocal.m4: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2004-09-11 22:22:51 +02:00
|
|
|
|
2004-09-11 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Rebuild.
|
|
|
|
|
|
|
2004-09-09 14:42:37 +02:00
|
|
|
|
2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (L): Make this field not optional.
|
|
|
|
|
|
|
2004-09-03 16:31:41 +02:00
|
|
|
|
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
|
|
|
|
|
|
Fix parameter to 'm[t|f]csr' insns.
|
|
|
|
|
|
|
2004-08-30 20:59:50 +02:00
|
|
|
|
2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Autoupdate to autoconf 2.59.
|
|
|
|
|
|
* aclocal.m4: Rebuild with aclocal 1.4p6.
|
|
|
|
|
|
* configure: Rebuild with autoconf 2.59.
|
|
|
|
|
|
* Makefile.in: Rebuild with automake 1.4p6 (picking up
|
|
|
|
|
|
bfd changes for autoconf 2.59 on the way).
|
|
|
|
|
|
* config.in: Rebuild with autoheader 2.59.
|
|
|
|
|
|
|
2004-08-27 11:32:02 +02:00
|
|
|
|
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-desc.[ch], frv-opc.[ch]: Regenerated.
|
|
|
|
|
|
|
2004-07-30 14:36:38 +02:00
|
|
|
|
2004-07-30 Michal Ludvig <mludvig@suse.cz>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
|
|
|
|
|
|
(GRPPADLCK2): New define.
|
|
|
|
|
|
(twobyte_has_modrm): True for 0xA6.
|
|
|
|
|
|
(grps): GRPPADLCK2 for opcode 0xA6.
|
|
|
|
|
|
|
include/elf/ChangeLog:
Introduce SH2a support.
2004-02-18 Corinna Vinschen <vinschen@redhat.com>
* sh.h (EF_SH2A_NOFPU): New.
2003-12-01 Michael Snyder <msnyder@redhat.com>
* sh.h (EF_SH2A): New.
bfd/ChangeLog:
Introduce SH2a support.
2004-02-18 Corinna Vinschen <vinschen@redhat.com>
* archures.c (bfd_mach_sh2a_nofpu): New.
* bfd-in2.h: Rebuilt.
* cpu-sh.c (SH2A_NOFPU_NEXT): New.
(arch_info_struct): Add sh2a_nofpu.
* elf32-sh.c (sh_elf_set_mach_from_flags): Handle sh2a_nofpu.
2003-12-29 DJ Delorie <dj@redhat.com>
* reloc.c: Add relocs for sh2a.
* bfd-in2.h: Regenerate.
* libbfd.hh: Regenerate.
2003-12-01 Michael Snyder <msnyder@redhat.com>
* archures.c (bfd_mach_sh2a): New.
* bfd-in2.h: Rebuilt.
* cpu-sh.c (SH_NEXT, SH2_NEXT, etc.): Change defines to enums.
(SH2A_NEXT): New.
(arch_info_struct): Add sh2a.
* elf32-sh.c (sh_elf_set_mach_from_flags): Handle sh2a.
binutils/ChangeLog:
* readelf.c (get_machine_flags <EM_SH>): Handle EF_SH2A and
EF_SH2A_NOFPU.
gas/ChangeLog:
Introduce SH2a support.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/tc-sh.c (get_specific): Change arch_sh2a_up to
arch_sh2a_nofpu_up.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/tc-sh.c (md_parse_option): Add sh2a-nofpu ISA handling.
2004-02-20 Corinna Vinschen <vinschen@redhat.com>
* config/tc-sh.c (sh_elf_final_processing): Move sh2a recognition
to end of conditional expression.
2004-02-20 Corinna Vinschen <vinschen@redhat.com>
* config/tc-sh.c: Add sh2a-nofpu support.
2003-12-29 DJ Delorie <dj@redhat.com>
* tc-sh.c: Add sh2a support.
(parse_reg): Add tbr.
(parse_at): Support @@(disp,tbr).
(get_specific): Support sh2a opcodes.
(insert4): New, for 4 byte relocs.
(build_Mytes): Support sh2a opcodes.
(md_apply_fix3_Mytes): Support sh2a opcodes.
2003-12-02 Michael Snyder <msnyder@redhat.com>
* config/tc-sh.c (md_parse_option): Handle sh2a.
(sh_elf_final_processing): Ditto.
gas/testsuite/ChangeLog:
2003-12-30 DJ Delorie <dj@redhat.com>
* gas/sh/sh2a.s: New.
* gas/sh/sh2a.d: New.
* gas/sh/basic.exp: Add it.
opcodes/ChangeLog:
Introduce SH2a support.
* sh-opc.h (arch_sh2a_base): Renumber.
(arch_sh2a_nofpu_base): Remove.
(arch_sh_base_mask): Adjust.
(arch_opann_mask): New.
(arch_sh2a, arch_sh2a_nofpu): Adjust.
(arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
(sh_table): Adjust whitespace.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
instruction list throughout.
(arch_sh2a_up): Redefine to include fpu instruction set. Use instead
of arch_sh2a in instruction list throughout.
(arch_sh2e_up): Accomodate above changes.
(arch_sh2_up): Ditto.
2004-02-20 Corinna Vinschen <vinschen@redhat.com>
* sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
2004-02-18 Corinna Vinschen <vinschen@redhat.com>
* sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
* sh-opc.h (arch_sh2a_nofpu): New.
(arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
(sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
instruction.
2004-01-20 DJ Delorie <dj@redhat.com>
* sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
2003-12-29 DJ Delorie <dj@redhat.com>
* sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
sh_opcode_info, sh_table): Add sh2a support.
(arch_op32): New, to tag 32-bit opcodes.
* sh-dis.c (print_insn_sh): Support sh2a opcodes.
2003-12-02 Michael Snyder <msnyder@redhat.com>
* sh-opc.h (arch_sh2a): Add.
* sh-dis.c (arch_sh2a): Handle.
* sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
2004-07-29 07:19:27 +02:00
|
|
|
|
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Introduce SH2a support.
|
|
|
|
|
|
* sh-opc.h (arch_sh2a_base): Renumber.
|
|
|
|
|
|
(arch_sh2a_nofpu_base): Remove.
|
|
|
|
|
|
(arch_sh_base_mask): Adjust.
|
|
|
|
|
|
(arch_opann_mask): New.
|
|
|
|
|
|
(arch_sh2a, arch_sh2a_nofpu): Adjust.
|
|
|
|
|
|
(arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
|
|
|
|
|
|
(sh_table): Adjust whitespace.
|
|
|
|
|
|
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
|
|
|
|
|
|
* sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
|
|
|
|
|
|
instruction list throughout.
|
|
|
|
|
|
(arch_sh2a_up): Redefine to include fpu instruction set. Use instead
|
|
|
|
|
|
of arch_sh2a in instruction list throughout.
|
|
|
|
|
|
(arch_sh2e_up): Accomodate above changes.
|
|
|
|
|
|
(arch_sh2_up): Ditto.
|
|
|
|
|
|
2004-02-20 Corinna Vinschen <vinschen@redhat.com>
|
|
|
|
|
|
* sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
|
|
|
|
|
|
2004-02-18 Corinna Vinschen <vinschen@redhat.com>
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
|
|
|
|
|
|
* sh-opc.h (arch_sh2a_nofpu): New.
|
|
|
|
|
|
(arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
|
|
|
|
|
|
(sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
2004-01-20 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
|
|
|
|
|
|
2003-12-29 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
* sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
|
|
|
|
|
|
sh_opcode_info, sh_table): Add sh2a support.
|
|
|
|
|
|
(arch_op32): New, to tag 32-bit opcodes.
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Support sh2a opcodes.
|
|
|
|
|
|
2003-12-02 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
* sh-opc.h (arch_sh2a): Add.
|
|
|
|
|
|
* sh-dis.c (arch_sh2a): Handle.
|
|
|
|
|
|
* sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
|
|
|
|
|
|
|
2004-07-27 13:37:12 +02:00
|
|
|
|
2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
|
|
|
|
|
|
|
2004-07-22 18:52:43 +02:00
|
|
|
|
2004-07-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR/280
|
|
|
|
|
|
* h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
|
|
|
|
|
|
insns - this is done by objdump itself.
|
|
|
|
|
|
* h8500-dis.c (print_insn_h8500): Likewise.
|
|
|
|
|
|
|
2004-07-21 18:09:43 +02:00
|
|
|
|
2004-07-21 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
|
|
|
|
|
|
regardless of address size prefix in effect.
|
|
|
|
|
|
(ptr_reg): Size or address registers does not depend on rex64, but
|
|
|
|
|
|
on the presence of an address size override.
|
|
|
|
|
|
(OP_MMX): Use rex.x only for xmm registers.
|
|
|
|
|
|
(OP_EM): Use rex.z only for xmm registers.
|
|
|
|
|
|
|
2004-07-20 19:59:00 +02:00
|
|
|
|
2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
|
|
|
|
|
|
move/branch operations to the bottom so that VR5400 multimedia
|
|
|
|
|
|
instructions take precedence in disassembly.
|
|
|
|
|
|
|
2004-07-20 19:49:31 +02:00
|
|
|
|
2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
|
|
|
|
|
|
ISA-specific "break" encoding.
|
|
|
|
|
|
|
2004-07-13 18:28:05 +02:00
|
|
|
|
2004-07-13 Elvis Chiang <elvisfb@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-opc.h: Fix typo in comment.
|
|
|
|
|
|
|
2004-07-11 16:29:50 +02:00
|
|
|
|
2004-07-11 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c (m68k_valid_ea): Fix typos in last change.
|
|
|
|
|
|
|
2004-07-09 20:42:14 +02:00
|
|
|
|
2004-07-09 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c (m68k_valid_ea): Check validity of all codes.
|
|
|
|
|
|
|
2004-07-07 19:28:53 +02:00
|
|
|
|
2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
|
|
|
|
|
|
(ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
|
|
|
|
|
|
(crx-dis.lo): New target.
|
|
|
|
|
|
(crx-opc.lo): Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in: Handle bfd_crx_arch.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* crx-dis.c: New file.
|
|
|
|
|
|
* crx-opc.c: New file.
|
|
|
|
|
|
* disassemble.c (ARCH_crx): Define.
|
|
|
|
|
|
(disassembler): Handle ARCH_crx.
|
|
|
|
|
|
|
2004-06-30 20:12:38 +02:00
|
|
|
|
2004-06-29 James E Wilson <wilson@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
|
|
|
|
|
|
* ia64-asmtab.c: Regnerate.
|
|
|
|
|
|
|
2004-06-28 16:08:08 +02:00
|
|
|
|
2004-06-28 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
|
|
|
|
|
|
(extract_fxm): Don't test dialect.
|
|
|
|
|
|
(XFXFXM_MASK): Include the power4 bit.
|
|
|
|
|
|
(XFXM): Add p4 param.
|
|
|
|
|
|
(powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
|
|
|
|
|
|
|
2004-06-27 08:31:22 +02:00
|
|
|
|
2004-06-27 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
* disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
|
|
|
|
|
|
|
2004-06-26 10:32:12 +02:00
|
|
|
|
2004-06-26 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (BH, XLBH_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
|
|
|
|
|
|
|
2004-06-23 17:06:58 +02:00
|
|
|
|
2004-06-24 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (x_mode): Comment.
|
|
|
|
|
|
(two_source_ops): File scope.
|
|
|
|
|
|
(float_mem): Correct fisttpll and fistpll.
|
|
|
|
|
|
(float_mem_mode): New table.
|
|
|
|
|
|
(dofloat): Use it.
|
|
|
|
|
|
(OP_E): Correct intel mode PTR output.
|
|
|
|
|
|
(ptr_reg): Use open_char and close_char.
|
|
|
|
|
|
(PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
|
|
|
|
|
|
operands. Set two_source_ops.
|
|
|
|
|
|
|
2004-06-15 03:14:22 +02:00
|
|
|
|
2004-06-15 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
|
|
|
|
|
|
instead of _raw_size.
|
|
|
|
|
|
|
2004-06-08 22:40:59 +02:00
|
|
|
|
2004-06-08 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-gen.c (in_iclass): Handle more postinc st
|
|
|
|
|
|
and ld variants.
|
|
|
|
|
|
* ia64-asmtab.c: Rebuilt.
|
|
|
|
|
|
|
2004-06-01 15:56:11 +02:00
|
|
|
|
2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.txt: Correct architecture mask for some opcodes.
|
|
|
|
|
|
lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
|
|
|
|
|
|
in the esa mode as well.
|
|
|
|
|
|
|
2004-05-28 14:32:10 +02:00
|
|
|
|
2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-dis.c (target_arch): Make unsigned.
|
|
|
|
|
|
(print_insn_sh): Replace (most of) switch with a call to
|
|
|
|
|
|
sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
|
|
|
|
|
|
* sh-opc.h: Redefine architecture flags values.
|
|
|
|
|
|
Add sh3-nommu architecture.
|
|
|
|
|
|
Reorganise <arch>_up macros so they make more visual sense.
|
|
|
|
|
|
(SH_MERGE_ARCH_SET): Define new macro.
|
|
|
|
|
|
(SH_VALID_BASE_ARCH_SET): Likewise.
|
|
|
|
|
|
(SH_VALID_MMU_ARCH_SET): Likewise.
|
|
|
|
|
|
(SH_VALID_CO_ARCH_SET): Likewise.
|
|
|
|
|
|
(SH_VALID_ARCH_SET): Likewise.
|
|
|
|
|
|
(SH_MERGE_ARCH_SET_VALID): Likewise.
|
|
|
|
|
|
(SH_ARCH_SET_HAS_FPU): Likewise.
|
|
|
|
|
|
(SH_ARCH_SET_HAS_DSP): Likewise.
|
|
|
|
|
|
(SH_ARCH_UNKNOWN_ARCH): Likewise.
|
|
|
|
|
|
(sh_get_arch_from_bfd_mach): Add prototype.
|
|
|
|
|
|
(sh_get_arch_up_from_bfd_mach): Likewise.
|
|
|
|
|
|
(sh_get_bfd_mach_from_arch_set): Likewise.
|
|
|
|
|
|
(sh_merge_bfd_arc): Likewise.
|
|
|
|
|
|
|
2004-05-24 16:33:22 +02:00
|
|
|
|
2004-05-24 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c(print_insn_m68k): Strip body of diassembly out
|
2005-02-22 01:33:20 +01:00
|
|
|
|
into new match_insn_m68k function. Loop over canidate
|
|
|
|
|
|
matches and select first that completely matches.
|
2004-05-24 16:33:22 +02:00
|
|
|
|
* m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
|
|
|
|
|
|
* m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
|
2005-02-22 01:33:20 +01:00
|
|
|
|
to verify addressing for MAC/EMAC.
|
2004-05-24 16:33:22 +02:00
|
|
|
|
* m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
|
|
|
|
|
|
reigster halves since 'fpu' and 'spl' look misleading.
|
|
|
|
|
|
* m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
|
|
|
|
|
|
* m68k-opc.c: Rearragne mac/emac cases to use longest for
|
|
|
|
|
|
first, tighten up match masks.
|
|
|
|
|
|
* m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
|
|
|
|
|
|
'size' from special case code in print_insn_m68k to
|
|
|
|
|
|
determine decode size of insns.
|
|
|
|
|
|
|
2004-05-19 07:11:48 +02:00
|
|
|
|
2004-05-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
|
|
|
|
|
|
well as when -mpower4.
|
|
|
|
|
|
|
2004-05-13 14:54:36 +02:00
|
|
|
|
2004-05-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po: Updated French translation.
|
|
|
|
|
|
|
2004-05-05 16:33:14 +02:00
|
|
|
|
2004-05-05 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c(print_insn_m68k): Add new chips, use core
|
|
|
|
|
|
variants in arch_mask. Only set m68881/68851 for 68k chips.
|
|
|
|
|
|
* m68k-op.c: Switch from ColdFire chips to core variants.
|
|
|
|
|
|
|
2004-05-05 15:43:36 +02:00
|
|
|
|
2004-05-05 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
2004-05-19 07:11:48 +02:00
|
|
|
|
PR 147.
|
2004-05-05 15:43:36 +02:00
|
|
|
|
* ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
|
|
|
|
|
|
|
2004-04-30 08:46:53 +02:00
|
|
|
|
2004-04-29 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
2004-04-30 09:14:40 +02:00
|
|
|
|
* ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
|
|
|
|
|
|
(powerpc_opcodes): Add "dbczl" instruction for PPC970.
|
2004-04-30 08:46:53 +02:00
|
|
|
|
|
2004-04-23 04:47:39 +02:00
|
|
|
|
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Print the value in constant pool
|
|
|
|
|
|
as a symbol if it looks like a symbol.
|
|
|
|
|
|
|
2004-04-22 12:33:16 +02:00
|
|
|
|
2004-04-22 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
|
|
|
|
|
|
appropriate ColdFire architectures.
|
|
|
|
|
|
(print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
|
|
|
|
|
|
mask addressing.
|
|
|
|
|
|
Add EMAC instructions, fix MAC instructions. Remove
|
|
|
|
|
|
macmw/macml/msacmw/msacml instructions since mask addressing now
|
|
|
|
|
|
supported.
|
|
|
|
|
|
|
2004-04-20 12:23:51 +02:00
|
|
|
|
2004-04-20 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
|
|
|
|
|
|
(fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
|
|
|
|
|
|
suffix. Use fmov*x macros, create all 3 fpsize variants in one
|
|
|
|
|
|
macro. Adjust all users.
|
|
|
|
|
|
|
2004-04-15 10:55:27 +02:00
|
|
|
|
2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
|
2005-02-22 01:33:20 +01:00
|
|
|
|
|
2004-04-15 10:55:27 +02:00
|
|
|
|
* h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
|
|
|
|
|
|
separately.
|
|
|
|
|
|
|
2004-03-30 11:29:19 +02:00
|
|
|
|
2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r-asm.c: Regenerate.
|
|
|
|
|
|
|
2004-03-29 20:09:09 +02:00
|
|
|
|
2004-03-29 Stan Shebs <shebs@apple.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
|
|
|
|
|
|
used.
|
|
|
|
|
|
|
2004-03-19 08:02:24 +01:00
|
|
|
|
2004-03-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* aclocal.m4: Regenerate.
|
|
|
|
|
|
* config.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 01:58:43 +01:00
|
|
|
|
2004-03-16 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
|
|
|
|
|
|
PPC_OPERANDS_GPR_0.
|
|
|
|
|
|
* ppc-opc.c (RA0): Define.
|
|
|
|
|
|
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
|
|
|
|
|
|
(RAOPT): Rename from RAO. Update all uses.
|
2004-03-16 12:46:15 +01:00
|
|
|
|
(powerpc_opcodes): Use RA0 as appropriate.
|
opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 01:58:43 +01:00
|
|
|
|
|
2004-03-15 20:07:39 +01:00
|
|
|
|
2004-03-15 Aldy Hernandez <aldyh@redhat.com>
|
opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 01:58:43 +01:00
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
|
2004-03-15 20:07:39 +01:00
|
|
|
|
|
2004-03-15 14:36:28 +01:00
|
|
|
|
2004-03-15 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-dis.c (print_insn_sparc): Update getword prototype.
|
|
|
|
|
|
|
2004-03-12 14:38:16 +01:00
|
|
|
|
2004-03-12 Michal Ludvig <mludvig@suse.cz>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (GRPPLOCK): Delete.
|
2004-03-15 14:36:28 +01:00
|
|
|
|
(grps): Delete GRPPLOCK entry.
|
2004-03-12 14:38:16 +01:00
|
|
|
|
|
* i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
(M, Mp): Use OP_M.
(None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
(GRPPADLCK): Define.
(dis386): Use NOP_Fixup on "nop".
(dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
(twobyte_has_modrm): Set for 0xa7.
(padlock_table): Delete. Move to..
(grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
and clflush.
(print_insn): Revert PADLOCK_SPECIAL code.
(OP_E): Delete sfence, lfence, mfence checks.
* gas/i386/katmai.d: Revert last change.
2004-03-12 14:06:50 +01:00
|
|
|
|
2004-03-12 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
|
|
|
|
|
|
(M, Mp): Use OP_M.
|
|
|
|
|
|
(None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
|
|
|
|
|
|
(GRPPADLCK): Define.
|
|
|
|
|
|
(dis386): Use NOP_Fixup on "nop".
|
|
|
|
|
|
(dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
|
|
|
|
|
|
(twobyte_has_modrm): Set for 0xa7.
|
|
|
|
|
|
(padlock_table): Delete. Move to..
|
|
|
|
|
|
(grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
|
|
|
|
|
|
and clflush.
|
|
|
|
|
|
(print_insn): Revert PADLOCK_SPECIAL code.
|
|
|
|
|
|
(OP_E): Delete sfence, lfence, mfence checks.
|
|
|
|
|
|
|
2004-03-12 11:47:49 +01:00
|
|
|
|
2004-03-12 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
|
|
|
|
|
|
(INVLPG_Fixup): New function.
|
|
|
|
|
|
(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
|
|
|
|
|
|
|
2004-03-12 11:14:29 +01:00
|
|
|
|
2004-03-12 Michal Ludvig <mludvig@suse.cz>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
|
|
|
|
|
|
(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
|
|
|
|
|
|
(padlock_table): New struct with PadLock instructions.
|
|
|
|
|
|
(print_insn): Handle PADLOCK_SPECIAL.
|
|
|
|
|
|
|
2004-03-12 08:01:37 +01:00
|
|
|
|
2004-03-12 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (grps): Use clflush by default for 0x0fae/7.
|
|
|
|
|
|
(OP_E): Twiddle clflush to sfence here.
|
|
|
|
|
|
|
2004-03-08 11:06:13 +01:00
|
|
|
|
2004-03-08 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
|
2004-03-03 19:01:49 +01:00
|
|
|
|
2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
|
|
|
|
|
|
nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
|
|
|
|
|
|
* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
|
|
|
|
|
|
accordingly.
|
|
|
|
|
|
|
2004-03-01 11:11:46 +01:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-asm.c: Regenerate.
|
|
|
|
|
|
* frv-desc.c: Regenerate.
|
|
|
|
|
|
* frv-desc.h: Regenerate.
|
|
|
|
|
|
* frv-dis.c: Regenerate.
|
|
|
|
|
|
* frv-ibld.c: Regenerate.
|
|
|
|
|
|
* frv-opc.c: Regenerate.
|
|
|
|
|
|
* frv-opc.h: Regenerate.
|
|
|
|
|
|
|
2004-03-01 10:42:33 +01:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-desc.c, frv-opc.c: Regenerate.
|
|
|
|
|
|
|
cpu/
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
2004-03-01 10:26:33 +01:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
|
|
|
|
|
|
|
2004-02-27 15:17:36 +01:00
|
|
|
|
2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
|
|
|
|
|
|
Also correct mistake in the comment.
|
|
|
|
|
|
|
2004-02-26 17:14:42 +01:00
|
|
|
|
2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
|
|
|
|
|
|
ensure that double registers have even numbers.
|
|
|
|
|
|
Add REG_N_B01 for nn01 (binary 01) nibble to ensure
|
|
|
|
|
|
that reserved instruction 0xfffd does not decode the same
|
|
|
|
|
|
as 0xfdfd (ftrv).
|
|
|
|
|
|
* sh-opc.h: Add REG_N_D nibble type and use it whereever
|
|
|
|
|
|
REG_N refers to a double register.
|
|
|
|
|
|
Add REG_N_B01 nibble type and use it instead of REG_NM
|
|
|
|
|
|
in ftrv.
|
|
|
|
|
|
Adjust the bit patterns in a few comments.
|
|
|
|
|
|
|
2004-02-26 04:24:44 +01:00
|
|
|
|
2004-02-25 Aldy Hernandez <aldyh@redhat.com>
|
2004-03-15 14:36:28 +01:00
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
|
2004-02-26 04:24:44 +01:00
|
|
|
|
|
2004-02-20 06:10:13 +01:00
|
|
|
|
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
|
|
|
|
|
|
|
2004-02-20 05:56:34 +01:00
|
|
|
|
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add m*ivor35.
|
|
|
|
|
|
|
2004-02-20 05:45:37 +01:00
|
|
|
|
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
2004-03-15 14:36:28 +01:00
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
|
|
|
|
|
|
mtivor32, mtivor33, mtivor34.
|
2004-02-20 05:45:37 +01:00
|
|
|
|
|
2004-02-20 01:17:23 +01:00
|
|
|
|
2004-02-19 Aldy Hernandez <aldyh@redhat.com>
|
2004-03-15 14:36:28 +01:00
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add mfmcar.
|
2004-02-20 01:17:23 +01:00
|
|
|
|
|
2004-02-18 17:28:18 +01:00
|
|
|
|
2004-02-10 Petko Manolov <petkan@nucleusys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-opc.h Maverick accumulator register opcode fixes.
|
|
|
|
|
|
|
2004-02-13 04:21:49 +01:00
|
|
|
|
2004-02-13 Ben Elliston <bje@wasabisystems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r-dis.c: Regenerate.
|
|
|
|
|
|
|
2004-01-28 01:05:47 +01:00
|
|
|
|
2004-01-27 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-opc.h (sh_table): "fsrra", not "fssra".
|
|
|
|
|
|
|
2004-01-23 13:08:24 +01:00
|
|
|
|
2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
|
|
|
|
|
|
contraints.
|
|
|
|
|
|
|
2004-01-19 00:46:32 +01:00
|
|
|
|
2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
|
|
|
|
|
|
|
2004-01-19 00:12:47 +01:00
|
|
|
|
2004-01-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E): Print scale factor on intel mode sib when not
|
|
|
|
|
|
1. Don't print scale factor on AT&T mode when index missing.
|
|
|
|
|
|
|
2004-01-16 04:16:00 +01:00
|
|
|
|
2004-01-16 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
|
|
|
|
|
|
when loaded into XR registers.
|
|
|
|
|
|
|
2004-01-14 11:05:00 +01:00
|
|
|
|
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-desc.h: Regenerate.
|
|
|
|
|
|
* frv-desc.c: Regenerate.
|
|
|
|
|
|
* frv-opc.c: Regenerate.
|
|
|
|
|
|
|
2004-01-13 20:56:46 +01:00
|
|
|
|
2004-01-13 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
|
|
|
|
|
|
|
2004-01-09 12:53:16 +01:00
|
|
|
|
2004-01-09 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-opc.h (arm_opcodes): Move generic mcrr after known
|
|
|
|
|
|
specific opcodes.
|
|
|
|
|
|
|
2004-01-07 19:39:40 +01:00
|
|
|
|
2004-01-07 Daniel Jacobowitz <drow@mvista.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (libopcodes_la_DEPENDENCIES)
|
|
|
|
|
|
(libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
|
|
|
|
|
|
comment about the problem.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2004-01-06 20:18:43 +01:00
|
|
|
|
2004-01-06 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2003-12-19 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
|
|
|
|
|
|
cut&paste errors in shifting/truncating numerical operands.
|
|
|
|
|
|
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
|
|
|
|
|
|
(parse_uslo16): Likewise.
|
|
|
|
|
|
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
|
|
|
|
|
|
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
|
|
|
|
|
|
(parse_s12): Likewise.
|
|
|
|
|
|
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
|
|
|
|
|
|
(parse_uslo16): Likewise.
|
|
|
|
|
|
(parse_uhi16): Parse gothi and gotfuncdeschi.
|
|
|
|
|
|
(parse_d12): Parse got12 and gotfuncdesc12.
|
|
|
|
|
|
(parse_s12): Likewise.
|
|
|
|
|
|
|
2004-01-02 18:26:11 +01:00
|
|
|
|
2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430-dis.c (msp430_doubleoperand): Check for an 'add'
|
|
|
|
|
|
instruction which looks similar to an 'rla' instruction.
|
2003-12-15 23:01:43 +01:00
|
|
|
|
|
2004-01-02 12:16:21 +01:00
|
|
|
|
For older changes see ChangeLog-0203
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
2001-01-11 20:01:42 +01:00
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
1999-05-03 09:29:11 +02:00
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
