* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
* igen.c (main): Change -I to add include paths for :include:
files.
Implement -G as per sim/igen, with just gen-icache=N support.
Call load_insn_table() with the built include path.
* ld-insn.c (parse_include_entry): New. Load an :include: file.
(load_insn_table): New `includes' argument. Look for :include:
entries and call parse_include_entry() for them.
(main): Adjust load_insn_table() call.
* ld-insn.h (model_include_fields): New enum.
(load_insn_table): Update prototype.
* table.c (struct _open_table, struct _table): Rework
structures to handle included files.
(table_push): Move the guts of table_open() here.
* table.c (struct _open table, struct table): Make table object an
indirect ptr to the current table file.
(current_line, new_table_entry, next_line): Make file arg type
open_table.
(table_open): Use table_push.
(table_entry_read): Point variable file at current table, at eof, pop
last open table.
* misc.h (NZALLOC): New macro. From sim/igen.
* table.h, table.c (table_push): New function.
(tmp-gencode, gencode.o, gencode): Delete targets.
(simops.h): New file.
($(BUILT_SRC_FROM_IGEN)): Do not depend on simops.h.
* gencode.c: Delete file.
* hw_htab.c (htab_map_binary): Don't try to map the text section
when it is empty.
* emul_chirp.c (map_over_chirp_note): Default load-base to -1 not
CHIRP_LOAD_BASE.
(emul_chirp_create): Map in the interrupt table.
* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
* interp.c (sim_resume): New function from sim-resume.c, install
the stepping event after having processed the pending ticks.
(has_stepped): Likewise.
(sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
pending interrupts.
* interrupts.c (interrupts_process): Keep track of the last number
of masked insn cycles.
(interrupts_initialize): Clear last number of masked insn cycles.
(interrupts_info): Report them.
(interrupts_update_pending): Compute clear and set masks of
interrupts and clear the interrupt bits before setting them
(due to SCI interrupt sharing).
* interrupts.h (struct interrupts): New members last_mask_cycles
and xirq_last_mask_cycles.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-03-16 Frank Ch. Eigler <fche@redhat.com>
Add support for mmap-based memory regions.
* sim-memopt.c (mmap_next_fd): New global.
(sim_memory_init): Reinitialize it.
(OPTION_MEMORY_MAPFILE, memory_option_handler): Support new
"--memory-mapfile FILE" option. Check for some errors.
(do_memopt_add): Conditionally do mmap instead of malloc for
backing store of simulated memory. Check for more errors.
(do_simopt_delete, sim_memory_uninstall): Corresponding cleanup.
* sim-memopt.h (munmap_length): New member of _sim_memopt.
* configure.in: Look for mmap/fstat related functions and headers.
* config.in, configure: Regenerated.
2001-02-09 Ben Elliston <bje@redhat.com>
* (profile_print_pc): Write header out in target byte order.
2001-02-09 Ben Elliston <bje@redhat.com>
* sim-profile.c (profile_pc_init): Correct bug in loop logic when
adjusting the pc shift value.
later inspection by the trap handler.
(count_argc): New function.
(prog_argv): Declare static.
(sim_write): Declare.
(trap): Implement argc, argnlen and argn system calls. Do not
abort on unknown system calls--simply return -1.
* syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define.
[common/ChangeLog]
2001-01-12 Chris Demetriou <cgd@sibyte.com>
* aclocal.m4 (SIM_AC_OPTION_SCACHE): Properly
handle the case where a numeric value is supplied.
[eg. m32r/ChangeLog]
2001-01-12 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated with sim_scache fix.
* sim-fpu.h (sim_fpu_printn_fpu): Declare.
* sim-fpu.c (print_bits): Add digits parameter. Print only as many
trailing digits as specified (-1 to print all digits).
(sim_fpu_print_fpu): New wrapper around sim_fpu_printn_fpu.
(sim_fpu_printn_fpu): Rename from sim_fpu_print_fpu; update calls
to print_bits ().
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
In sim/ppc:
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
* lib/sim-defs.exp (run_sm_test): Correct comment. "output" and
"xerror" options do not use a list of machines. Clear options from
previous test case. Use "$cpu_option" to identify the machine to the
assembler, if specified.
* cgen.sh: Handle an isa argument between cpu and mach. Default to
`all'. Pass `-i' options to cgen applications.
* Make-common.in (cgen-arch, cgen-cpu, cgen-decode, cgen-cpu-decode,
cgen-desc): Pass $(isa) to cgen.sh.
2000-10-19 Frank Ch. Eigler <fche@redhat.com>
On advice from Chris G. Demetriou <cgd@sibyte.com>:
* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
* dv-m68hc11tim.c (cycle_to_string): New function to translate
the cpu cycle into some formatted time string.
(m68hc11tim_print_timer): Use it.
* dv-m68hc11sio.c (m68hc11sio_info): Use cycle_to_string.
* dv-m68hc11spi.c (m68hc11spi_info): Likewise.
* interrupts.c (interrupts_info): Likewise.
* m68hc11_sim.c (cpu_info): Likewise.
* sim-profile.h (PROFILE_DATA): Add cpu_freq.
(PROFILE_CPU_FREQ): New macro.
* sim-profile.c (OPTION_PROFILE_CPU_FREQUENCY): New enumerator.
(profile-options): Add profile-cpu-frequency.
(parse_frequency): New function.
(profile_option_handler): Handle OPTION_PROFILE_CPU_FREQUENCY.
(profile_print_speed): Print cpu frequency and simulated execution time.
Re-indent other items to match.
(movm): Initialize PC and mask.
(mov, movbu, movhu): Set srcreg2 from RI0.
(bsch): Initialize c.
(sat16_cmp): Actually do the comparison.
(mov_llt): Do not overwrite dstreg with uninitialized variable.
* sim-events.c (sim_events_remain_time): New function returning
the time that remains before the event is raised.
* hw-events.c (hw_event_remain_time): Likewise.
* sim-events.h (sim_events_remain_time): Declare.
* hw-events.h (hw_event_remain_time): Declare.
* sim-hw.c: Use <errno.h> instead of <sys/errno.h>
(OPTION_HW_LIST): New option --hw-list to list the devices.
(hw_option_handler): List the device tree with 'sim_hw_print'.
* sim-bits.h (_MSB_16, _LSB_16): Define for 16-bit targets.
(MASK, LSBIT, MSBIT): Likewise and use _MSB_16 and _LSB_16.
(EXTENDED): Define for 16-bit word size.
* sim-bits.c (LSEXTRACTED, MSEXTRACTED, LSINSERTED,
MSINSERTED, LSSEXT, MSSEXT): Implement for 16-bit word size.
* sim-types.h: Added support for 16-bit targets.
(ARM_Strong_Prop, STRONGARM): Define.
* arminit.c (ARMul_NewState): Reset is_StrongARM.
(ARMul_SelectProcessor): Set is_StrongARM.
* wrapper.c (sim_create_inferior): Use bfd machine type to
determine processor type to emulate.
* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
when emulating StrongARM.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC. Moved the existing logic...
(WriteR15Branch): ... here. New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-06-20 Frank Ch. Eigler <fche@redhat.com>
* compile.c: Don't include "wait.h".
(sim_resume): Use local SIM_WIFEXITED and SIM_WIFSIGNALED macros
instead of WIF* from host.
* Makefile.in (interp.o): Depends on ppi.c .
(ppi.c): New rule.
* gencode.c (printonmatch, think, genopc): Deleted.
(MAX_NR_STUFF): Now 42.
(tab): Add SH-DSP CPU instructions.
Amalgamate ldc / stc / lds / sts instructions with similar
bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>.
Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
(movsxy_tab): New array.
For movs, change MMMM field to GGGG, and mmmm field to MMMM.
Added entries for movx, movy and parallel processing insns.
(ppi_tab): New array.
(qfunc): Stabilize sort.
(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
(dumptable): Now takes three arguments. Changed all callers.
Emit just one contigous jump table.
(filltable): Now takes an argument. Changed all callers.
Make index static.
(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
(gensim_caselist): New function, broken out of gensim.
Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
Handle ref '9'.
(gensim): Handle 'N' in code field and '8' in refs field.
Call gensim_caselist - twice.
(ppi_index): New static variable.
(main): Unsupport default action.
Add dsp support for -x / -s option. Add -p option.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
(saved_state_type): Rearrange to allow amalgamated ldc / stc /
lds / sts to work efficiently.
(target_dsp): New static variable.
(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
(set_fpscr1): Likewise. Use target_dsp to check for dsp.
(MOD_MSi, SIG_BUS_FETCH): Deleted.
(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
(SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead
of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
(set_sr): Reflect saved_state_type change. Fix SR_RB handling.
Use SET_MOD.
(MA, L, TL, TB): Now controlled by ACE_FAST.
(SEXT32): Just cast to int.
(SIGN32): Fixed to only shift by 31.
(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
(ppi_insn): Declare.
(ppi.c): Include.
(init_dsp): Set target_dsp. When it changes, switch end of
sh_jump_table with sh_dsp_table.
(sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead.
Don't Declare PR if it's #defined.
Fix single-stepping (Was broken in Mar 6 16:59:10 patch).
(sim_store_register, sim_read_register): Translate accesses to
reflect saved_state_type change.
* interp.c (set_sr): Set sr.
(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
(DSP_R): Fix definition.
(sim_resume): Remove outdated SET_SR use.
* interp.c (saved_state): New members for struct member asregs:
rs, re, insn_end, xram_start, yram_start.
(struct loop_bounds): New struct.
(SKIP_INSN): New macro.
(get_loop_bounds): New function.
(endianw): Renamed to global_endianw.
(maskw): negated bits.
(PC): Now insn_ptr.
(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
(SIG_BUS_FETCH): Likewise
(raise_exception, riat_fast): New functions.
(raise_buserror, sim_stop): Use raise_exception.
(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
Reverse sense of mask argument.
(FP_OP, set_dr): Use RAISE_EXCEPTION.
(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
Declare. Remove redundant masking.
(wwat_fast, rwat_fast): Add argument endianw. Changed callers.
(MA): Updated for change pc -> PC.
(Delay_Slot): Use RIAT.
(empty): Deleted.
(trap): Remove argument little_endian. Add argument endianw.
Changed all callers. Use raise_exception.
(macw): Add argument endainw. Changed all callers.
(init_dsp): New function, extended after broken out of init_pointers.
(sim_resume): Replace pc with insn_ptr. Replace little_endian with
endianw. Replace nia with nip. Reverse sense of maskb / maskw /
maskl. Implement logic for zero-overhead loops. Don't try to
interpret garbage when getting a SIGBUS at insn fetch.
(sim_open): Call init_dsp.
* gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H /
RAISE_EXCEPTION where appropriate.
Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.
* interp.c (sim_store_register, sim_fetch_register):
Do proper endianness switch.
* interp.c (saved_state_type): New members for struct member asregs:
xymem_select, xmem, ymem, xmem_offset, ymem_offset.
(special_address): Delete.
(BUSERROR): Now a two-argument predicate.
(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
(process_wlat_addr, process_wwat_addr): New functions.
(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
(process_rbat_addr): Likewise.
(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
(do_rdat, trap): Delete SLOW code.
(SEXT32, SIGN32): New macros.
(swap, swap16): Now integer in - integer out. Changed all callers.
(strswaplen, strnswap): Delete SLOW versions.
(init_pointers): Initialize dsp memory selection (preliminary).
(sim_store_register, sim_fetch_register): Use swap instead of
big / little endian read / write functions.
* interp.c (maskl): Deleted.
(endianw, endianb): New variables.
(special_address): Now inline.
(bp_holder): Put raising of buserror there, rename to:
(raise_buserror).
(BUSERROR): Now yields a value. Changed all users.
(wbat_big): Delete.
(wlat_fast, wwat_fast, wbat_fast): New functions.
(rlat_fast, rwat_fast, rbat_fast): Likewise.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
(do_rdat, do_wdat): Likewise. Take maskl argument instead of
little_endian one. Changed caller macros.
(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
(strswaplen, strnswap): New functions.
(trap): Use them to fix up endian mismatches;
disable SYS_execve and SYS_execv; fix double address translation for
SYS_pipe and SYS_stat.
(sym_write, sym_read): Add endianness translation.
(sym_store_register, sym_fetch_register): Add maskl local variable.
(sim_open): Set endianw and endianb.
genericXor, genericBtst): Use `unsigned32'.
* op_utils.c: Likewise.
* mn10300.igen, am33.igen: Use `unsigned32', `signed32',
`unsigned64' or `signed64' where type width is relevant.
sim:
* Makefile.in (interp.o): Depends on ppi.c .
(ppi.c): New rule.
* gencode.c (printonmatch, think, genopc): Deleted.
(MAX_NR_STUFF): Now 42.
(tab): Add SH-DSP CPU instructions.
Amalgamate ldc / stc / lds / sts instructions with similar
bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>.
Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
(movsxy_tab): New array.
For movs, change MMMM field to GGGG, and mmmm field to MMMM.
Added entries for movx, movy and parallel processing insns.
(ppi_tab): New array.
(qfunc): Stabilize sort.
(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
(dumptable): Now takes three arguments. Changed all callers.
Emit just one contigous jump table.
(filltable): Now takes an argument. Changed all callers.
Make index static.
(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
(gensim_caselist): New function, broken out of gensim.
Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
Handle ref '9'.
(gensim): Handle 'N' in code field and '8' in refs field.
Call gensim_caselist - twice.
(ppi_index): New static variable.
(main): Unsupport default action.
Add dsp support for -x / -s option. Add -p option.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
(saved_state_type): Rearrange to allow amalgamated ldc / stc /
lds / sts to work efficiently.
(target_dsp): New static variable.
(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
(set_fpscr1): Likewise. Use target_dsp to check for dsp.
(MOD_MSi, SIG_BUS_FETCH): Deleted.
(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
(SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead
of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
(set_sr): Reflect saved_state_type change. Fix SR_RB handling.
Use SET_MOD.
(MA, L, TL, TB): Now controlled by ACE_FAST.
(SEXT32): Just cast to int.
(SIGN32): Fixed to only shift by 31.
(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
(ppi_insn): Declare.
(ppi.c): Include.
(init_dsp): Set target_dsp. When it changes, switch end of
sh_jump_table with sh_dsp_table.
(sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead.
Don't Declare PR if it's #defined.
Fix single-stepping (Was broken in Mar 6 16:59:10 patch).
(sim_store_register, sim_read_register): Translate accesses to
reflect saved_state_type change.
* interp.c (set_sr): Set sr.
(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
(DSP_R): Fix definition.
(sim_resume): Remove outdated SET_SR use.
* interp.c (saved_state): New members for struct member asregs:
rs, re, insn_end, xram_start, yram_start.
(struct loop_bounds): New struct.
(SKIP_INSN): New macro.
(get_loop_bounds): New function.
(endianw): Renamed to global_endianw.
(maskw): negated bits.
(PC): Now insn_ptr.
(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
(SIG_BUS_FETCH): Likewise
(raise_exception, riat_fast): New functions.
(raise_buserror, sim_stop): Use raise_exception.
(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
Reverse sense of mask argument.
(FP_OP, set_dr): Use RAISE_EXCEPTION.
(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
Declare. Remove redundant masking.
(wwat_fast, rwat_fast): Add argument endianw. Changed callers.
(MA): Updated for change pc -> PC.
(Delay_Slot): Use RIAT.
(empty): Deleted.
(trap): Remove argument little_endian. Add argument endianw.
Changed all callers. Use raise_exception.
(macw): Add argument endainw. Changed all callers.
(init_dsp): New function, extended after broken out of init_pointers.
(sim_resume): Replace pc with insn_ptr. Replace little_endian with
endianw. Replace nia with nip. Reverse sense of maskb / maskw /
maskl. Implement logic for zero-overhead loops. Don't try to
interpret garbage when getting a SIGBUS at insn fetch.
(sim_open): Call init_dsp.
* gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H /
RAISE_EXCEPTION where appropriate.
Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.
* interp.c (sim_store_register, sim_fetch_register):
Do proper endianness switch.
* interp.c (saved_state_type): New members for struct member asregs:
xymem_select, xmem, ymem, xmem_offset, ymem_offset.
(special_address): Delete.
(BUSERROR): Now a two-argument predicate.
(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
(process_wlat_addr, process_wwat_addr): New functions.
(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
(process_rbat_addr): Likewise.
(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
(do_rdat, trap): Delete SLOW code.
(SEXT32, SIGN32): New macros.
(swap, swap16): Now integer in - integer out. Changed all callers.
(strswaplen, strnswap): Delete SLOW versions.
(init_pointers): Initialize dsp memory selection (preliminary).
(sim_store_register, sim_fetch_register): Use swap instead of
big / little endian read / write functions.
* interp.c (maskl): Deleted.
(endianw, endianb): New variables.
(special_address): Now inline.
(bp_holder): Put raising of buserror there, rename to:
(raise_buserror).
(BUSERROR): Now yields a value. Changed all users.
(wbat_big): Delete.
(wlat_fast, wwat_fast, wbat_fast): New functions.
(rlat_fast, rwat_fast, rbat_fast): Likewise.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
(do_rdat, do_wdat): Likewise. Take maskl argument instead of
little_endian one. Changed caller macros.
(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
(strswaplen, strnswap): New functions.
(trap): Use them to fix up endian mismatches;
disable SYS_execve and SYS_execv; fix double address translation for
SYS_pipe and SYS_stat.
(sym_write, sym_read): Add endianness translation.
(sym_store_register, sym_fetch_register): Add maskl local variable.
(sim_open): Set endianw and endianb.
gdb:
* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
bfd_mach_sh3_dsp.
(sh_show_regs): Floating point registers are called fr0-fr15.
For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
Handle sh-dsp and sh3-dsp.
config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
don't have floating point registers.
(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.
2000-04-14 Gary Thomas <gthomas@redhat.com>
* v850.igen: Define 'br *' as illegal since this is the only
way to provide a breakpoint on some v850 family processors.
2000-03-11 Philip Blundell <philb@gnu.org>
* armemu.c (LoadSMult, LoadMult): Correct handling of aborts.
Patch from Allan Skillman <Allan.Skillman@arm.com>.
* cgen-fpu.h: Rename extsfdf to fextsfdf. Rename truncdfsf to
ftruncdfsf.
* cgen-accfp.c (fextsfdf): New function.
(ftruncdfsf): New function.
(cgen_init_accurate_fpu): Initialize fextsfdf and ftruncdfsf.
2000-03-08 Dave Brolley <brolley@redhat.com>
* cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_SF_WRITE.
(CGEN_WRITE_QUEUE_ELEMENT): Add fn_sf_write.
(sim_queue_fn_si_write): Last argument is has type USI.
(sim_queue_fn_sf_write): New function.
* cgen-par.c (sim_queue_fn_si_write): Declare 'value' as USI.
(sim_queue_fn_sf_write): New function.
(cgen_write_queue_element_execute): Handle CGEN_FN_SF_WRITE.
* merge from internal repo -> sourceware
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
instead of sim_trace() to run the program; include support for ``-o''
option (operating environment); when a signal occurs, only continue
execution when operating environment mode.
Update d10v.
* sparc-desc.h: New file.
* sparc-opc.h: New file.
* decode64.c: New file.
* decode64.h: New file.
* sem64.c: New file.
* cpu64.c: New file.
* cpu64.h: New file.
* model64.h: New file.
* mloop64.in: New file.
* regs64.h: New file.
* trap64.c: New file.
* cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
CPU, start periodic background I/O polls.
(tx3904sio_poll): New function: periodic I/O poller.
(PROFILE_USEFUL_MASK): New macro.
* sim-profile.c (profile_options): Make like trace_options, allow
optional on|off arg where applicable.
(set_profile_option_mask): New function.
(sim_profile_set_option): New function.
(profile_option_handler): Simplify.
Have -p only enable selected things, not everything.
Add missing break to OPTION_PROFILE_PC_RANGE.
* cgen-scache.c (scache_options): Allow optional on|off arg to
--profile-scache.
(scache_option_handler): Use sim_profile_set_option.
for internal PR 18869 and 18870.
1999-01-26 Frank Ch. Eigler <fche@cygnus.com>
* sim-memopt.c (memory_options): Add MEMORY_FILL option.
(memory_option_handler): Implement MEMORY_FILL option. Make
MEMORY_CLEAR an alias for MEMORY_FILL=0.
(parse_ulong_value): New function.
(do_memopt_add): Allocate all buffers. Optionally fill them.
(CGEN_MAIN_SCM): Add rtx-funcs.scm.
(cgen-arch): Pass $(mach) to cgen.sh.
* cgen-engine.h (SEM_BRANCH_FINI): New arg pcvar, all uses updated.
(SEM_BRANCH_INIT_EXTRACT): New macro.
(SEM_BRANCH_INIT): Add taken_p.
(TARGET_SEM_BRANCH_FINI): Provide default definition.
(SEM_BRANCH_FINI): Use it.
(SEM_INSN): Update.
* cgen-run.c (sim_resume): Handle tracing of last insn.
* cgen-scache.h (WITH_SCACHE): Define as 0 if not defined.
* cgen-trace.c (current_abuf): New static global.
(trace_insn_init): Initialize it.
(trace_insn_fini): Use it.
(trace_insn): Set it.
* cgen.sh (arch case): Pass -m ${mach} to cgen.
* genmloop.sh (@cpu@_emit_before): Only define if WITH_SCACHE_PBB.
(@cpu@_emit_after): Ditto.
(simple @cpu@_engine_run_full): New local `pc'. Initialize semantic
labels if WITH_SEM_SWITCH_FULL.
* sim-model.c: Include bfd.h.
(sim_model_init): New function.
(sim_model_install): Record init fn.
* sim-model.h (MACH): New member bfd_name.
* sim-module.c (modules): Initialize model before scache.
[ChangeLog]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
start-sanitize-sky
* interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook.
Call sim_engine_halt on BreakPoint.
end-sanitize-sky
[ChangeLog.sky]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* sky-gdb.c (sky_sim_engine_halt): Do not set CIA here.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
(load_word): Call SIM_CORE_SIGNAL hook on error.
(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
starting. For exception dispatching, pass PC instead of NULL_CIA.
(decode_coproc): Use COP0_BADVADDR to store faulting address.
* sim-main.h (COP0_BADVADDR): Define.
(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
(_sim_cpu): Add exc_* fields to store register value snapshots.
* mips.igen (*): Replace memory-related SignalException* calls
with references to SIM_CORE_SIGNAL hook.
* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
fix.
* sim-main.c (*): Minor warning cleanups.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o.
* interp.c (sim_open): Add stub mn103002 cache control memory regions.
Set OPERATING_ENVIRONMENT on "stdeval1" board.
(mn10300_core_signal): New function to intercept memory errors.
(program_interrupt): New function to dispatch to exception vector
(mn10300_exception_*): New functions to snapshot pre/post exception
state.
* sim-main.h (SIM_CORE_SIGNAL): Define hook - call mn10300_core_signal.
(SIM_ENGINE_HALT_HOOK): Do nothing.
(SIM_CPU_EXCEPTION*): Define hooks to call mn10300_cpu_exception*().
(_sim_cpu): Add exc_* fields to store register value snapshots.
* dv-mn103ser.c (*): Support dv-sockser backend for UART I/O.
Various endianness and warning fixes.
* mn10300.igen (illegal): Call program_interrupt on error.
(break): Call program_interrupt on breakpoint
Several changes from <janczyn@cygnus.com> and <cagney@cygnus.com>
merged in:
* dv-mn103int.c (mn103int_ioctl): New function for NMI
generation. (mn103int_finish): Install it as ioctl handler.
* dv-mn103tim.c: Support timer 6 specially. Endianness fixes.
1998-12-24 Frank Ch. Eigler <fche@cygnus.com>
* dv-sockser.c (DEFAULT_TIMEOUT): Increase to 1 ms.
* nrun.c (main): Remain in simulation loop for traps and
exceptions when in operating environment mode.
(ui_loop_hook): New stub hook for standalone use.
* sim-events.c (sim_events_process): Call ui_loop_hook
periodically on CYGWIN host.
* sim-reason.c (sim_stop_reason): Return host signal numbers
to gdb on sim_stopped and sim_signalled cases.
* sim-engine.c (sim_engine_halt): Call SIM_CPU_EXCEPTION_SUSPEND
hook just before longjmp.
* sim-resume.c (sim_resume): Call SIM_CPU_EXCEPTION_RESUME
hook just before sim_engine_run.
* sim-n-core.h (sim_core_trace_M): Allay const warning.
* sim-trace.h (trace_generic): Ditto.
* sim-trace.c (trace_generic): Ditto.
* sim/fr30/ldres.cgs: New testcase.
* sim/fr30/stres.cgs: New testcase.
* sim/fr30/copop.cgs: New testcase.
* sim/fr30/copld.cgs: New testcase.
* sim/fr30/copst.cgs: New testcase.
* sim/fr30/copsv.cgs: New testcase.
* sim/fr30/nop.cgs: New testcase.
* sim/fr30/andccr.cgs: New testcase.
* sim/fr30/orccr.cgs: New testcase.
* sim/fr30/addsp.cgs: New testcase.
* sim/fr30/stilm.cgs: New testcase.
* sim/fr30/extsb.cgs: New testcase.
* sim/fr30/extub.cgs: New testcase.
* sim/fr30/extsh.cgs: New testcase.
* sim/fr30/extuh.cgs: New testcase.
* sim/fr30/enter.cgs: New testcase.
* sim/fr30/leave.cgs: New testcase.
* sim/fr30/xchb.cgs: New testcase.
* sim/fr30/dmovb.cgs: New testcase.
* sim/fr30/dmov.cgs: New testcase.
* sim/fr30/dmovh.cgs: New testcase.
* sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
* sim/fr30/ret.cgs: Add tests fir ret:d.
* sim/fr30/inte.cgs: New testcase.
* sim/fr30/reti.cgs: New testcase.
* sim/fr30/bra.cgs: New testcase.
* sim/fr30/bno.cgs: New testcase.
* sim/fr30/beq.cgs: New testcase.
* sim/fr30/bne.cgs: New testcase.
* sim/fr30/bc.cgs: New testcase.
* sim/fr30/bnc.cgs: New testcase.
* sim/fr30/bn.cgs: New testcase.
* sim/fr30/bp.cgs: New testcase.
* sim/fr30/bv.cgs: New testcase.
* sim/fr30/bnv.cgs: New testcase.
* sim/fr30/blt.cgs: New testcase.
* sim/fr30/bge.cgs: New testcase.
* sim/fr30/ble.cgs: New testcase.
* sim/fr30/bgt.cgs: New testcase.
* sim/fr30/bls.cgs: New testcase.
* sim/fr30/bhi.cgs: New testcase.
