Written by matthew green <mrg@redhat.com>, with fixes from Aldy
Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
Nick Clifton <nickc@redhat.com>.
* ppc-instructions: Include altivec.igen and e500.igen.
(model_busy, model_data): Add vr_busy and vscr_busy.
(model_trace_release): Trace vr_busy and vscr_busy.
(model_new_cycle): Update vr_busy and vscr_busy.
(model_make_busy): Update vr_busy and vscr_busy.
* registers.c (register_description): Add Altivec and e500
registers.
* psim.c (psim_read_register, psim_read_register): Handle Altivec
and e500 registers.
* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
* configure.in (sim_filter): When *altivec* add "av". When *spe*
or *simd* add e500.
(sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add
WITH_E500.
* configure: Re-generate.
* e500.igen, altivec.igen: New files.
* e500_expression.h, altivec_expression.h: New files.
* idecode_expression.h: Update copyright. Include
"e500_expression.h" and "altivec_expression.h".
* e500_registers.h, altivec_registers.h: New files.
* registers.h: Update copyright. Include "e500_registers.h" and
"altivec_registers.h".
(registers): Add Altivec and e500 specific registers.
* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
"idecode_altivec.h".
(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
(tmp-igen): Add dependencies on altivec.igen and e500.igen .
From matthew green <mrg@redhat.com>:
* sim-fpu.h: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New prototypes.
* sim-fpu.c: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New inline functions.
* cgen-trace.h (sim_disasm_read_memory): Update args to be compatible
with disassemble_info:read_memory_func.
* cgen-trace.c (sim_disasm_read_memory): Ditto.
* compile.c: Replace "Hitachi" with "Renesas".
(decode): Distinguish AV_H8S from AV_H8H.
(sim_resume): H8SX can use any register for TAS.
(decode): Add support for VECIND.
(sim_resume): Implement rte/l and rts/l.
(GETSR): New macro (actually old macro reincarnated).
(decode): Add handling for IMM2.
(sim_resume): Drop extra block around jmp, jsr, rts.
Add handling for trapa and rte.
For divxu.b, change 0xffff mask to 0xff.
(set_h8300h): Add bfd_mach_h8300sxn machine.
* compile.c (sim_info): Fix typo in output.
* h8300/compile.c (set_h8300h): Replace 'flag' arguments
with a bfd_machine argument, and decode it inline.
Check for bfd_mach_h8300hn and bfd_mach_h8300sn.
2003-03-20 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* compile.c (cmdline_location): Added function to
return the location of 8-bit (256 locations) where the
Command Line arguments would be stored.
(decode): Added a TRAP to 0xcc for Commandline
processing using pseudo opcode O_SYS_CMDLINE.
(sim_resume): Added handling of O_SYS_CMDLINE Trap.
(sim_create_inferior): Setting a pointer to
Commandline Args array.
* inst.h: Added a new variable ptr_command_line for
storing pointer to Commandline array.
2003-03-14 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* compile.c (decode): Added code for some more magic traps.
* compile.c (sim_resume): Added support for File I/O system
calls through callback to host_system.
System calls provided support for :
open, read, write, lseek, close, stat, fstat
Only basic support for stat and fstat.
* gen-engine.c (print_engine_issue_prefix_hook): Don't add the
global prefix to ENGINE_ISSUE_PREFIX_HOOK.
(print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
This patch fixes the gcc.dg/nest.c failures for sh-elf.
Fri Oct 11 16:22:28 2002 J"orn Rennecke <joern.rennecke@superh.com>
* interp.c (trap): Return int. Take extra parameter for address
of the trap instruction. Changed all callers.
Add case 33 for profiling.
* gencode.c (trapa): Handle trap 33 using the trap function.
Add read of vector for generic traps.
bank window to some virtual address to read from extended memory.
(m68hc11cpu_io_write_buffer): Likewise for writing.
(attach_m68hc11_regs): When use_bank property is defined, attached
to the 68HC12 16K memory bank window.
* interp.c (sim_hw_configure): Create memory region for banked
memory.
* sim-main.h (M6812_CALL_INDIRECT): Add to enum.
(m6811_regs): Add page register.
(cpu_set_page, cpu_get_page): New macros.
(phys_to_virt): New function.
(cpu_get_indexed_operand_addr, cpu_return): Declare.
* gencode.c: Identify indirect addressing mode for call and fix daa.
(gen_function_entry): New param to tell if src8/dst8 locals are
necessary.
(gen_interpreter): Use it to avoid generation of unused variables.
* interp.c (sim_fetch_register): Allow to read page register; page
register, A, B and CCR are only 1 byte wide.
(sim_store_register): Likewise for writing.
* mips.igen (do_load_double, do_store_double): New functions.
(LDC1, SDC1): Rename to...
(LDC1b, SDC1b): respectively.
(LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp,
renumbering the sh-dsp registers to use distinct numbers.
sim/sh:
* Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h.
* interp.c: Include "gdb/sim-sh.h".
(sim_store_register, sim_fetch_register): Use constants defined there.
gdb:
* sh-tdep.c (sh_dsp_register_sim_regno): New function.
(sh_gdbarch_init): Use it for sh-dsp.
* mdmx.c (SD_): Delete.
(Unpredictable): Re-define, for now, to directly invoke
unpredictable_action().
(mdmx_acc_op): Fix error in .ob immediate handling.
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
* mips.igen (MOVN, MOVZ): Trace result.
(TNEI): Print "tnei" as the opcode name in traces.
(CEIL.W): Add disassembly string for traces.
(RSQRT.fmt): Make location of disassembly string consistent
with other instructions.
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c: Fix more comment spelling and formatting.
(value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
(denorm_mode): New function.
(fpu_unary, fpu_binary): Round results after operation, collect
status from rounding operations, and update the FCSR.
(convert): Collect status from integer conversions and rounding
operations, and update the FCSR. Adjust NaN values that result
from conversions. Convert to use sim_io_eprintf rather than
fprintf, and remove some debugging code.
* cp1.h (fenr_FS): New define.
(z8k_inv_list): Delete global.
(DIRTY_HACK): Delete macro.
(makelist): Delete global.
(main): Delete code making a list. Delete dirty hack code. Use
lookup_inst instead of z8k_inv_list.
* list.c: Delete file.
* Makefile.in (writecode): Do not link in list.o.
(list.o): Delete target.
* sim-main.h (FGRIDX): Remove, replace all uses with...
(FGR_BASE): New macro.
(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
(NR_FGR, FGR): Likewise.
* interp.c: Replace all uses of FGRIDX with FGR_BASE.
* mips.igen: Likewise.
* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
file, remove PARAMS from prototypes.
(value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
simulator state arguments.
(ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
pass simulator state arguments.
* cp1.c (SD): Redefine as CPU_STATE(cpu).
(store_fpr, convert): Remove 'sd' argument.
(value_fpr): Likewise. Convert to use 'SD' instead.
Ed Satterthwaite <ehs@broadcom.com>
* configure.in (mipsisa64sb1*-*-*): New target for supporting
Broadcom SiByte SB-1 processor configurations.
* configure: Regenerate.
* sb1.igen: New file.
* mips.igen: Include sb1.igen.
(sb1): New model.
* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
* mdmx.igen: Add "sb1" model to all appropriate functions and
instructions.
* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
(ob_func, ob_acc): Reference the above.
(qh_acc): Adjust to keep the same size as ob_acc.
* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
* interp.c (sim_create_inferior): Add comment.
From Alan Matsuoka <alanm@redhat.com>:
From 2001-04-27 Jason Eckhardt <jle@cygnus.com>:
* simops.c (OP_4400): Output "mvf0f" instead of "mf0f".
(OP_4401): Output "mvf0t" instead of "mf0t".
(OP_460B): Do not output a flag register.
(OP_4609): Do not output a flag register.
* sim-d10v.h: New file. Moved from include/sim-d10v.h.
* Makefile.in (INCLUDE): Add "gdb/sim-d10v.h".
* interp.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h".
* d10v-tdep.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h".
* Makefile.in (sim_d10v_h): Update definition.
include:
* dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype.
gdb:
* sh-tdep.c (gdb_print_insn_sh64): Delete.
(gdb_print_insn_sh): Just set info->endian and use print_insn_sh.
(sh_gdbarch_init): Always use gdb_print_insn_sh.
opcodes:
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
* sh-dis.c (LITTLE_BIT): Delete.
(print_insn_sh, print_insn_shl): Deleted.
(print_insn_shx): Renamed to
(print_insn_sh). No longer static. Handle SHmedia instructions.
Use info->endian to determine endianness.
* sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete.
(print_insn_sh64x): No longer static. Renamed to
(print_insn_sh64). Removed pfun_compact and endian arguments.
If we got an uneven address to indicate SHmedia, adjust it.
Return -2 for SHcompact instructions.
sim/sh64:
* sim-if.c (sh64_disassemble_insn): Use print_insn_sh instead of
print_insn_shl.
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* callback.c: Use 'deprecated' rather than 'depreciated.'
[ igen/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* igen.c: Use 'deprecated' rather than 'depreciated.'
[ mips/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* interp.c: Use 'deprecated' rather than 'depreciated.'
* sim-main.h: Likewise.
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
* ppc-instructions (lswx): Do the register control with the
register count. Initialize the right register in the loop.
(mtfsfi) : Correct prefix for the instruction.
* cp1.c (fpu_format_name): New function to replace...
(DOFMT): This. Delete, and update all callers.
(fpu_rounding_mode_name): New function to replace...
(RMMODE): This. Delete, and update all callers.
* interp.c: Move FPU support routines from here to...
* cp1.c: Here. New file.
* Makefile.in (SIM_OBJS): Add cp1.o to object list.
(cp1.o): New target.
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
immediate or code as a hex value with the "%#lx" format.
(ANDI): Likewise, and fix printed instruction name.
cpu struct.
(sim_hw_configure): Connect the capture input/output events.
* sim-main.h (_sim_cpu): New member hw_cpu.
(m68hc11cpu_set_oscillator): Declare.
(m68hc11cpu_clear_oscillator): Declare.
(m68hc11cpu_set_port): Declare.
* dv-m68hc11.c (m68hc11_options): New for oscillator commands.
(m68hc11cpu_ports): New input ports and output ports to reflect
the HC11 IOs.
(m68hc11_delete): Cleanup any running oscillator.
(attach_m68hc11_regs): Create the input oscillators.
(make_oscillator): New function.
(find_oscillator): New function.
(oscillator_handler): New function.
(reset_oscillators): New function.
(m68hc11cpu_port_event): Handle the new input ports.
(m68hc11cpu_set_oscillator): New function.
(m68hc11cpu_clear_oscillator): New function.
(get_frequency): New function.
(m68hc11_option_handler): New function.
(m68hc11cpu_set_port): New function.
(m68hc11cpu_io_write): Post the port output events.
* dv-m68hc11spi.c (set_bit_port): Use m68hc11cpu_set_port to set
the output port value.
* dv-m68hc11tim.c (m68hc11tim_port_event): Handle CAPTURE event
by latching the TCNT value in the register.
vector address according to cpu mode.
(interrupts_initialize): Move reset portion to the above.
(interrupt_names): New table to give a name to interrupts.
(idefs): Handle pulse accumulator interrupts.
(interrupts_info): Print the interrupt history.
(interrupt_option_handler): New function.
(interrupt_options): New table of options.
(interrupts_update_pending): Keep track of when interrupts are
raised and implement breakpoint-on-raise-interrupt.
(interrupts_process): Keep track of when interrupts are taken
and implement breakpoint-on-interrupt.
* interrupts.h (struct interrupt_history): Define.
(struct interrupt): Keep track of the interrupt history.
(interrupts_reset): Declare.
(interrupts_initialize): Update prototype.
* m68hc11_sim.c (cpu_reset): Reset interrupts.
(cpu_initialize): Cleanup.
* sim-main.h (status_UX, status_SX, status_KX, status_TS)
(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
(status_CU3): New definitions.
* sim-main.h (ExceptionCause): Add new values for MIPS32
and MIPS64: MDMX, MCheck, CacheErr. Update comments
for DebugBreakPoint and NMIReset to note their status in
MIPS32 and MIPS64.
(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
(SignalExceptionCacheErr): New exception macros.
* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
* sim-main.h (COP_Usable): Define, but for now coprocessor 1
is always enabled.
(SignalExceptionCoProcessorUnusable): Take as argument the
unusable coprocessor number.
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
* igen.c (main): Change -I to add include paths for :include:
files.
Implement -G as per sim/igen, with just gen-icache=N support.
Call load_insn_table() with the built include path.
* ld-insn.c (parse_include_entry): New. Load an :include: file.
(load_insn_table): New `includes' argument. Look for :include:
entries and call parse_include_entry() for them.
(main): Adjust load_insn_table() call.
* ld-insn.h (model_include_fields): New enum.
(load_insn_table): Update prototype.
* table.c (struct _open_table, struct _table): Rework
structures to handle included files.
(table_push): Move the guts of table_open() here.
* table.c (struct _open table, struct table): Make table object an
indirect ptr to the current table file.
(current_line, new_table_entry, next_line): Make file arg type
open_table.
(table_open): Use table_push.
(table_entry_read): Point variable file at current table, at eof, pop
last open table.
* misc.h (NZALLOC): New macro. From sim/igen.
* table.h, table.c (table_push): New function.
(tmp-gencode, gencode.o, gencode): Delete targets.
(simops.h): New file.
($(BUILT_SRC_FROM_IGEN)): Do not depend on simops.h.
* gencode.c: Delete file.
* hw_htab.c (htab_map_binary): Don't try to map the text section
when it is empty.
* emul_chirp.c (map_over_chirp_note): Default load-base to -1 not
CHIRP_LOAD_BASE.
(emul_chirp_create): Map in the interrupt table.
* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
* interp.c (sim_resume): New function from sim-resume.c, install
the stepping event after having processed the pending ticks.
(has_stepped): Likewise.
(sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
pending interrupts.
* interrupts.c (interrupts_process): Keep track of the last number
of masked insn cycles.
(interrupts_initialize): Clear last number of masked insn cycles.
(interrupts_info): Report them.
(interrupts_update_pending): Compute clear and set masks of
interrupts and clear the interrupt bits before setting them
(due to SCI interrupt sharing).
* interrupts.h (struct interrupts): New members last_mask_cycles
and xirq_last_mask_cycles.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-03-16 Frank Ch. Eigler <fche@redhat.com>
Add support for mmap-based memory regions.
* sim-memopt.c (mmap_next_fd): New global.
(sim_memory_init): Reinitialize it.
(OPTION_MEMORY_MAPFILE, memory_option_handler): Support new
"--memory-mapfile FILE" option. Check for some errors.
(do_memopt_add): Conditionally do mmap instead of malloc for
backing store of simulated memory. Check for more errors.
(do_simopt_delete, sim_memory_uninstall): Corresponding cleanup.
* sim-memopt.h (munmap_length): New member of _sim_memopt.
* configure.in: Look for mmap/fstat related functions and headers.
* config.in, configure: Regenerated.
2001-02-09 Ben Elliston <bje@redhat.com>
* (profile_print_pc): Write header out in target byte order.
2001-02-09 Ben Elliston <bje@redhat.com>
* sim-profile.c (profile_pc_init): Correct bug in loop logic when
adjusting the pc shift value.
later inspection by the trap handler.
(count_argc): New function.
(prog_argv): Declare static.
(sim_write): Declare.
(trap): Implement argc, argnlen and argn system calls. Do not
abort on unknown system calls--simply return -1.
* syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define.
[common/ChangeLog]
2001-01-12 Chris Demetriou <cgd@sibyte.com>
* aclocal.m4 (SIM_AC_OPTION_SCACHE): Properly
handle the case where a numeric value is supplied.
[eg. m32r/ChangeLog]
2001-01-12 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated with sim_scache fix.
* sim-fpu.h (sim_fpu_printn_fpu): Declare.
* sim-fpu.c (print_bits): Add digits parameter. Print only as many
trailing digits as specified (-1 to print all digits).
(sim_fpu_print_fpu): New wrapper around sim_fpu_printn_fpu.
(sim_fpu_printn_fpu): Rename from sim_fpu_print_fpu; update calls
to print_bits ().
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
In sim/ppc:
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
Michael Snyder
Andrew Cagney
Frank Ch. Eigler
Chris Demetriou
Ian Lance Taylor
Nick Clifton
D.Venkatasubramanian
Stephane Carrez
David Carlton
Joern Rennecke
Kazu Hirata
Ben Elliston
Doug Evans
Alan Modra
Jim Wilson
Dave Brolley
Geoffrey Keating
Andrey Volkov
Elena Zannoni
Tom Rix
Aldy Hernandez
Richard Henderson
DJ Delorie
Alexandre Oliva
David O'Brien
Anthony Green
Keith Seitz
Hans-Peter Nilsson
Matthew Green
Fred Fish
Ben Harris
John R. Moore
Daniel Jacobowitz
Jim Blandy
J.T. Conklin
Michael Meissner
Jonathan Larmour
Michael Chastain