2020-03-06 11:44:12 +01:00
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2020-03-06 Nick Clifton <nickc@redhat.com>
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PR 25572
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* as.c (main): Allow matching input and outputs when they are
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not regular files.
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2020-03-06 08:56:47 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_mem_size): Generalize broadcast special
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casing.
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(check_VecOperands): Zap xmmword/ymmword/zmmword when more than
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one of byte/word/dword/qword is set alongside a SIMD register in
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a template's operand.
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x86: drop/replace IgnoreSize
Even after commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06 08:55:52 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_template): Extend code in logic
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rejecting certain suffixes in certain modes to also cover mask
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register use and VecSIB. Drop special casing of broadcast. Skip
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immediates in the check.
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2020-03-06 08:55:03 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_template): Fold duplicate code in
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logic rejecting certain suffixes in certain modes. Drop
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pointless "else".
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2020-03-06 08:53:18 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Exlucde !vexw insns
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alongside !norex64 ones.
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* testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
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with both 32- and 64-bit GPR operands.
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* testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
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32- and 64-bit GPR operands.
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* testsuite/gas/i386/x86-64-avx512bw-intel.d,
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testsuite/gas/i386/x86-64-avx512bw.d,
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testsuite/gas/i386/x86-64-avx512f-intel.d,
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testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
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2020-03-06 08:52:12 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Drop use of rex64.
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(process_suffix): For REX.W for 64-bit CRC32.
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2020-03-06 08:50:56 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (i386_addressing_mode): For 32-bit
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addressing for MPX insns without base/index.
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* testsuite/gas/i386/mpx-16bit.s,
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* testsuite/gas/i386/mpx-16bit.d: New.
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* testsuite/gas/i386/i386.exp: Run new test.
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2020-03-06 08:49:45 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
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testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
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testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
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testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
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* testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
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as well as a BSWAP one.
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* testsuite/gas/i386/rdpid.s: Add 16-bit case.
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* testsuite/gas/i386/sse2-16bit.s: Cover more insns.
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* testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
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testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
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testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
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testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
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testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
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testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
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testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
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testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
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testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
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testsuite/gas/i386/vmx.d: Adjust expectations.
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2020-03-06 08:48:48 +01:00
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
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from having their operands swapped.
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* testsuite/gas/i386/waitpkg.s,
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testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
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3-operand cases as well as testing of 16-bit code generation.
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* testsuite/gas/i386/waitpkg.d,
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testsuite/gas/i386/waitpkg-intel.d,
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testsuite/gas/i386/x86-64-waitpkg.d,
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testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
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2020-03-04 06:08:04 +01:00
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2020-03-04 Nelson Chu <nelson.chu@sifive.com>
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2020-03-04 06:08:05 +01:00
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* config/tc-riscv.c (percent_op_utype): Support the modifier
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%got_pcrel_hi.
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* doc/c-riscv.texi: Add documentation.
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* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
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modifier %got_pcrel_hi.
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* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
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* testsuite/gas/riscv/relax-reloc.d: Likewise.
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* testsuite/gas/riscv/relax-reloc.s: Likewise.
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2020-03-04 06:08:04 +01:00
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* doc/c-riscv.texi (relocation modifiers): Add documentation.
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(RISC-V-Formats): Update the section name from "Instruction Formats"
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to "RISC-V Instruction Formats".
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2020-03-04 18:28:46 +01:00
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2020-03-04 Alexandre Oliva <oliva@adacore.com>
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* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
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detected in a section which does not have at least 4 byte
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alignment.
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* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
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* testsuite/gas/arm/ldr-t.s: Likewise.
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* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
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* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
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disassembly, ignoring any NOPs that may have been inserted because
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of section alignment.
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* testsuite/gas/arm/ldr-t.d: Likewise.
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2020-03-04 08:58:13 +01:00
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2020-03-04 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (cpu_arch): Add .sev_es entry.
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* doc/c-i386.texi: Mention sev_es.
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* testsuite/gas/i386/arch-13.s: Add SEV-ES case.
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* testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
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expectations.
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* testsuite/gas/i386/arch-13-znver1.d,
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testsuite/gas/i386/arch-13-znver2.d: Extend -march=.
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2020-03-03 20:24:16 +01:00
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2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (match_template): Replace ignoresize and
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defaultsize with mnemonicsize.
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(process_suffix): Likewise.
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2020-03-03 17:31:42 +01:00
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2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25627
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* config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
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instruction LD IY,(HL).
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* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
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* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
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* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
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* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
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x86: Allow integer conversion without suffix in AT&T syntax
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
2020-03-03 16:39:18 +01:00
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2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25622
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* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
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x86-64-default-suffix-avx.
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* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
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vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
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* testsuite/gas/i386/noreg64.d: Updated.
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* testsuite/gas/i386/noreg64.l: Likewise.
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* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
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* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
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* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
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2020-03-03 14:09:19 +01:00
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2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25604
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* config/tc-z80.c (contains_register): Prevent an illegal memory
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access when checking an expression for a register name.
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2020-03-02 23:14:26 +01:00
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2020-03-03 Alan Modra <amodra@gmail.com>
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* config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips
|
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support.
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2020-03-02 00:47:18 +01:00
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2020-03-02 Alan Modra <amodra@gmail.com>
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* config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section.
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* config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata
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and .sbss sections.
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* config/tc-score.c: Delete !BFD_ASSEMBLER code throughout.
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(s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section.
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(s3_s_score_lcomm): Likewise.
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* config/tc-score7.c: Similarly.
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* read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
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2020-02-28 08:58:13 +01:00
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2020-02-28 YunQiang Su <syq@debian.org>
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PR gas/25539
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* config/tc-mips.c (fix_loongson3_llsc): Compare label value
|
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to handle multi-labels.
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(has_label_name): New.
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2020-02-26 15:23:11 +01:00
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|
2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-arm.c (enum pred_instruction_type): Remove
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NEUTRAL_IT_NO_VPT_INSN predication type.
|
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(cxn_handle_predication): Modify to require condition suffixes.
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(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
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* testsuite/gas/arm/cde-scalar.s: Update test.
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* testsuite/gas/arm/cde-warnings.l: Update test.
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* testsuite/gas/arm/cde-warnings.s: Update test.
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2020-02-26 03:27:19 +01:00
|
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|
2020-02-26 Alan Modra <amodra@gmail.com>
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* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
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N_() on empty string.
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2020-02-26 03:08:11 +01:00
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|
|
2020-02-26 Alan Modra <amodra@gmail.com>
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* read.c (read_a_source_file): Call strncpy with length one
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less than size of original_case_string.
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2020-02-25 06:04:46 +01:00
|
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|
|
2020-02-26 Alan Modra <amodra@gmail.com>
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* config/obj-elf.c: Indent labels correctly.
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* config/obj-macho.c: Likewise.
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* config/tc-aarch64.c: Likewise.
|
|
|
|
|
|
* config/tc-alpha.c: Likewise.
|
|
|
|
|
|
* config/tc-arm.c: Likewise.
|
|
|
|
|
|
* config/tc-cr16.c: Likewise.
|
|
|
|
|
|
* config/tc-crx.c: Likewise.
|
|
|
|
|
|
* config/tc-frv.c: Likewise.
|
|
|
|
|
|
* config/tc-i386-intel.c: Likewise.
|
|
|
|
|
|
* config/tc-i386.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-nds32.c: Likewise.
|
|
|
|
|
|
* config/tc-riscv.c: Likewise.
|
|
|
|
|
|
* config/tc-s12z.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c: Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
* read.c: Likewise.
|
|
|
|
|
|
* symbols.c: Likewise.
|
|
|
|
|
|
* write.c: Likewise.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 11:18:49 +01:00
|
|
|
|
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
2020-02-12 11:18:51 +01:00
|
|
|
|
* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
|
|
|
|
|
|
we are assembling instruction with CSR. Call riscv_csr_read_only_check
|
|
|
|
|
|
after parsing all arguments.
|
|
|
|
|
|
(enum csr_insn_type): New enum is used to classify the CSR instruction.
|
|
|
|
|
|
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
|
|
|
|
|
|
are used to check if we write a read-only CSR by the CSR instruction.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
|
|
|
|
|
|
all CSR for the read-only CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
|
|
|
|
|
|
all CSR instructions for the read-only CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
|
|
|
|
|
|
|
2020-02-12 11:18:50 +01:00
|
|
|
|
* config/tc-riscv.c (struct riscv_set_options): New field csr_check.
|
|
|
|
|
|
(riscv_opts): Initialize it.
|
|
|
|
|
|
(reg_lookup_internal): Check the `riscv_opts.csr_check`
|
|
|
|
|
|
before doing the CSR checking.
|
|
|
|
|
|
(enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK.
|
|
|
|
|
|
(md_longopts): Add mcsr-check and mno-csr-check.
|
|
|
|
|
|
(md_parse_option): Handle new enum option values.
|
|
|
|
|
|
(s_riscv_option): Handle new long options.
|
|
|
|
|
|
* doc/c-riscv.texi: Add description for the new .option and assembler
|
|
|
|
|
|
options.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
|
|
|
|
|
|
the CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 11:18:49 +01:00
|
|
|
|
* config/tc-riscv.c (csr_extra_hash): New.
|
|
|
|
|
|
(enum riscv_csr_class): New enum. Used to decide
|
|
|
|
|
|
whether or not this CSR is legal in the current ISA string.
|
|
|
|
|
|
(struct riscv_csr_extra): New structure to hold all extra information
|
|
|
|
|
|
of CSR.
|
|
|
|
|
|
(riscv_init_csr_hashes): New. According to the DECLARE_CSR and
|
|
|
|
|
|
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
|
|
|
|
|
|
Call hash_reg_name to insert CSR address into reg_names_hash.
|
|
|
|
|
|
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
|
|
|
|
|
|
Decide whether the CSR is valid according to the csr_extra_hash.
|
|
|
|
|
|
(reg_lookup_internal): Call reg_csr_lookup_internal for CSRs.
|
|
|
|
|
|
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
|
|
|
|
|
|
not a boolean. This is same as riscv_init_csr_hash, so keep the
|
|
|
|
|
|
consistent usage.
|
|
|
|
|
|
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
|
|
|
|
|
|
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
|
|
|
|
|
|
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
|
|
|
|
|
|
f-ext CSR are not allowed.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
|
|
|
|
|
|
source file is `priv-reg.s`, and the ISA is rv64if, so the
|
|
|
|
|
|
rv32-only CSR are not allowed.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
|
|
|
|
|
|
|
2020-02-20 14:05:21 +01:00
|
|
|
|
2020-02-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32.
|
|
|
|
|
|
(tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
|
|
|
|
|
|
|
PR25569, PDP11 ld -s clobbers last data byte
This patch fixes an ancient wart in aout support, in that text and
data section sizes are rounded up for alignment rather that just the
corresponding header sizes. Changing section sizes could conceivably
result in buffer overflows if section contents were held in memory.
Also, keeping the original section sizes allows this PR to be fixed
nicely.
bfd/
PR 25569
* aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use
"text", "data" and "bss" section pointer vars. Don't update
section size, just exec header sizes.
(adjust_sizes_and_vmas): Don't update text section size. Set
initial exec header a_text. Print exec headers sizes.
* pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic),
(adjust_sizes_and_vmas): Similarly. Formatting.
(final_link): Correct final file extension.
gas/
PR 25569
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
on section size adjustment, instead perform another write if
exec header size is larger than section size.
2020-02-20 12:23:44 +01:00
|
|
|
|
2020-02-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25569
|
|
|
|
|
|
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
|
|
|
|
|
|
on section size adjustment, instead perform another write if
|
|
|
|
|
|
exec header size is larger than section size.
|
|
|
|
|
|
|
2020-02-06 04:14:21 +01:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-riscv.texi: Add the doc entries for -march-attr/
|
|
|
|
|
|
-mno-arch-attr command line options.
|
|
|
|
|
|
|
2020-02-19 23:51:07 +01:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/c-add-addi.d: New testcase.
|
|
|
|
|
|
* testsuite/gas/riscv/c-add-addi.s: Likewise.
|
|
|
|
|
|
|
2020-02-19 18:46:10 +01:00
|
|
|
|
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25576
|
|
|
|
|
|
* config/tc-z80.c (md_parse_option): Do not use an underscore
|
|
|
|
|
|
prefix for local labels in SDCC compatability mode.
|
|
|
|
|
|
(z80_start_line_hook): Remove SDCC dollar label support.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.s: Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25517
|
|
|
|
|
|
* config/tc-z80.c: Add -march option.
|
|
|
|
|
|
* doc/as.texi: Update Z80 documentation.
|
|
|
|
|
|
* doc/c-z80.texi: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.d: Update command line.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/gbz80_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_extra.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_ii8.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z180.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z180_z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_ii8.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_in_f_c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_out_c_0.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_sli.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_reloc.d: Likewise.
|
|
|
|
|
|
|
2020-02-19 13:54:45 +01:00
|
|
|
|
2020-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
|
|
|
|
|
|
with GNU_PROPERTY_X86_FEATURE_2_MMX.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run property-3 and
|
|
|
|
|
|
x86-64-property-3.
|
|
|
|
|
|
* testsuite/gas/i386/property-3.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/property-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
|
|
|
|
|
|
|
2020-02-17 16:12:10 +01:00
|
|
|
|
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .popcnt.
|
|
|
|
|
|
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
|
|
|
|
|
|
Add a tab before @samp{.sse4a}.
|
|
|
|
|
|
|
2020-02-17 08:59:07 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Don't try to guess a suffix
|
|
|
|
|
|
for AddrPrefixOpReg templates. Combine the two pieces of
|
|
|
|
|
|
addrprefixopreg handling. Reject 16-bit address reg in 64-bit
|
|
|
|
|
|
mode.
|
|
|
|
|
|
|
2020-02-17 08:57:54 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/14439
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Also suppress operand
|
|
|
|
|
|
swapping for MONITOR{,X} and MWAIT{,X}.
|
|
|
|
|
|
* testsuite/gas/i386/sse3.s, testsuite/gas/i386/x86-64-sse3.s:
|
|
|
|
|
|
Add Intel syntax monitor/mwait tests.
|
|
|
|
|
|
* testsuite/gas/i386/sse3.d, testsuite/gas/i386/x86-64-sse3.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
*testsuite/gas/i386/sse3-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse3-intel.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-02-17 08:56:18 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/6518
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Re-work Intel-syntax
|
|
|
|
|
|
[XYZ]MMWord memory operand ambiguity recognition logic (largely
|
|
|
|
|
|
re-indentation).
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps
|
|
|
|
|
|
cases.
|
|
|
|
|
|
* testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/inval-avx.l,
|
|
|
|
|
|
testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-ambig.s,
|
|
|
|
|
|
testsuite/gas/i386/avx512vl-ambig.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-16 17:36:51 +01:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
|
|
|
|
|
|
nosse4.
|
|
|
|
|
|
* doc/c-i386.texi: Document sse4a and nosse4a.
|
|
|
|
|
|
|
2020-02-14 15:09:28 +01:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi: Remove the old movsx and movzx documentation
|
|
|
|
|
|
for AT&T syntax.
|
|
|
|
|
|
|
2020-02-14 14:27:28 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Move movsx/movzx special
|
|
|
|
|
|
casing ...
|
|
|
|
|
|
(process_suffix): ... here. Consider just the first operand
|
|
|
|
|
|
initially.
|
|
|
|
|
|
(check_long_reg): Drop opcode 0x63 special case again.
|
|
|
|
|
|
* testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s,
|
|
|
|
|
|
testsuite/gas/i386/ilp32/x86-64.s, testsuite/gas/i386/x86_64.s:
|
|
|
|
|
|
Move ambiguous operand size tests ...
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: ... here.
|
|
|
|
|
|
* testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d
|
|
|
|
|
|
testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d,
|
|
|
|
|
|
testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
|
|
|
|
|
|
testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l,
|
|
|
|
|
|
testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-movsxd.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-movsxd-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86_64.d, testsuite/gas/i386/x86_64-intel.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l,
|
|
|
|
|
|
testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l,
|
|
|
|
|
|
testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-02-14 14:04:23 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Also skip segment
|
|
|
|
|
|
override prefix emission if it matches an already present one.
|
|
|
|
|
|
* testsuite/gas/i386/prefix32.s: Add double segment override
|
|
|
|
|
|
cases.
|
|
|
|
|
|
* testsuite/gas/i386/prefix32.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-14 14:03:19 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Drop ineffectual segment
|
|
|
|
|
|
overrides when optimizing.
|
|
|
|
|
|
* testsuite/gas/i386/lea-optimize.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
|
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
2020-02-14 14:02:05 +01:00
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Also check insn prefix
|
|
|
|
|
|
for ineffectual segment override warning. Don't cover possible
|
|
|
|
|
|
VEX/EVEX encoded insns there.
|
|
|
|
|
|
* testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d,
|
|
|
|
|
|
testsuite/gas/i386/lea.e: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-14 13:57:01 +01:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
|
|
|
|
|
|
syntax.
|
|
|
|
|
|
|
2020-02-13 22:44:17 +01:00
|
|
|
|
2020-02-13 Fangrui Song <maskray@google.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25551
|
|
|
|
|
|
* config/tc-i386.c (tc_i386_fix_adjustable): Don't check
|
|
|
|
|
|
BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4.
|
|
|
|
|
|
* testsuite/gas/i386/relax-5.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/relax-5.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-relax-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-relax-4.s: Likewise.
|
|
|
|
|
|
|
2020-02-13 10:19:28 +01:00
|
|
|
|
2020-02-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in
|
|
|
|
|
|
"nosse4" entry.
|
|
|
|
|
|
|
2020-02-12 16:20:56 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (avx512): New (at file scope), moved from
|
|
|
|
|
|
(check_VecOperands): ... here.
|
|
|
|
|
|
(process_suffix): Add [XYZ]MMword operand size handling.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS
|
|
|
|
|
|
tests.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/noavx512-2.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-12 16:19:03 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24546
|
|
|
|
|
|
* config/tc-i386.c (match_template): Apply AMD64 check to 64-bit
|
|
|
|
|
|
code only.
|
|
|
|
|
|
* config/tc-i386-intel.c (i386_intel_operand): Also handle
|
|
|
|
|
|
CALL/JMP in O_tbyte_ptr case.
|
|
|
|
|
|
* doc/c-i386.texi: Mention far call and full pointer load ISA
|
|
|
|
|
|
differences.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-3.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-3.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-5.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-5.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-12 10:59:32 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (REGISTER_WARNINGS): Delete.
|
|
|
|
|
|
(check_byte_reg): Skip only source operand of CRC32. Drop Non-
|
|
|
|
|
|
64-bit-only warning.
|
|
|
|
|
|
(check_word_reg): Consistently error on mismatching register
|
|
|
|
|
|
size and suffix.
|
|
|
|
|
|
* testsuite/gas/i386/general.s: Replace dword GPR with word one
|
|
|
|
|
|
for movw. Replace suffix / GPR for orb.
|
|
|
|
|
|
* testsuite/gas/i386/inval.s: Add tests for movw with dword and
|
|
|
|
|
|
byte GPRs as well as ones for inb/outb with a word accumulator.
|
|
|
|
|
|
* testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l,
|
|
|
|
|
|
testsuite/gas/i386/inval.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-12 10:58:42 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (operand_type_register_match): Also fall
|
|
|
|
|
|
through initial two if()-s when the template allows for a GPR
|
|
|
|
|
|
operand. Adjust comment.
|
|
|
|
|
|
|
2020-02-11 11:20:55 +01:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
(struct _i386_insn): New field "short_form".
|
|
|
|
|
|
(optimize_encoding): Drop setting of shortform field.
|
|
|
|
|
|
(process_suffix): Set i.short_form. Replace shortform use.
|
|
|
|
|
|
(process_operands): Replace shortform use.
|
|
|
|
|
|
|
2020-02-11 11:17:33 +01:00
|
|
|
|
2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (vcx_handle_register_arguments): Remove `for`
|
|
|
|
|
|
loop initial declaration.
|
|
|
|
|
|
|
2020-02-10 17:39:02 +01:00
|
|
|
|
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
|
|
|
|
|
|
instructions that can have 5 arguments.
|
|
|
|
|
|
(enum operand_parse_code): Add new operands.
|
|
|
|
|
|
(parse_operands): Account for new operands.
|
|
|
|
|
|
(S5): New macro.
|
|
|
|
|
|
(enum neon_shape_el): Introduce P suffixes for coprocessor.
|
|
|
|
|
|
(neon_select_shape): Account for P suffix.
|
|
|
|
|
|
(LOW1): Move macro to global position.
|
|
|
|
|
|
(HI4): Move macro to global position.
|
|
|
|
|
|
(vcx_assign_vec_d): New.
|
|
|
|
|
|
(vcx_assign_vec_m): New.
|
|
|
|
|
|
(vcx_assign_vec_n): New.
|
|
|
|
|
|
(enum vcx_reg_type): New.
|
|
|
|
|
|
(vcx_get_reg_type): New.
|
|
|
|
|
|
(vcx_size_pos): New.
|
|
|
|
|
|
(vcx_vec_pos): New.
|
|
|
|
|
|
(vcx_handle_shape): New.
|
|
|
|
|
|
(vcx_ensure_register_in_range): New.
|
|
|
|
|
|
(vcx_handle_register_arguments): New.
|
|
|
|
|
|
(vcx_handle_insn_block): New.
|
|
|
|
|
|
(vcx_handle_common_checks): New.
|
|
|
|
|
|
(do_vcx1): New.
|
|
|
|
|
|
(do_vcx2): New.
|
|
|
|
|
|
(do_vcx3): New.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-fp.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-fp.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-mve.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-mve.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve-or-neon.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve-or-neon.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.l:
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.s:
|
|
|
|
|
|
* testsuite/gas/arm/cde.d:
|
|
|
|
|
|
* testsuite/gas/arm/cde.s:
|
|
|
|
|
|
|
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 17:38:00 +01:00
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2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-arm.c (arm_ext_cde*): New feature sets for each
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CDE coprocessor that can be enabled.
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(enum pred_instruction_type): New pred type.
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(BAD_NO_VPT): New error message.
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(BAD_CDE): New error message.
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(BAD_CDE_COPROC): New error message.
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(enum operand_parse_code): Add new immediate operands.
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(parse_operands): Account for new immediate operands.
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(check_cde_operand): New.
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(cde_coproc_enabled): New.
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(cde_coproc_pos): New.
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(cde_handle_coproc): New.
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(cxn_handle_predication): New.
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(do_custom_instruction_1): New.
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(do_custom_instruction_2): New.
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(do_custom_instruction_3): New.
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(do_cx1): New.
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(do_cx1a): New.
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(do_cx1d): New.
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(do_cx1da): New.
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(do_cx2): New.
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(do_cx2a): New.
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(do_cx2d): New.
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(do_cx2da): New.
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(do_cx3): New.
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(do_cx3a): New.
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(do_cx3d): New.
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(do_cx3da): New.
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(handle_pred_state): Define new IT block behaviour.
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(insns): Add newn CX*{,d}{,a} instructions.
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(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
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Define new cdecp extension strings.
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* doc/c-arm.texi: Document new cdecp extension arguments.
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* testsuite/gas/arm/cde-scalar.d: New test.
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* testsuite/gas/arm/cde-scalar.s: New test.
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* testsuite/gas/arm/cde-warnings.d: New test.
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* testsuite/gas/arm/cde-warnings.l: New test.
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* testsuite/gas/arm/cde-warnings.s: New test.
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* testsuite/gas/arm/cde.d: New test.
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* testsuite/gas/arm/cde.s: New test.
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2020-02-10 17:37:22 +01:00
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2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25516
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* config/tc-i386.c (intel64): Renamed to ...
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(isa64): This.
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(match_template): Accept Intel64 only instruction by default.
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(i386_displacement): Updated.
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(md_parse_option): Updated.
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* c-i386.texi: Update -mamd64/-mintel64 documentation.
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* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
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-mamd64 to x86-64-sysenter-amd.
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* testsuite/gas/i386/x86-64-sysenter.d: New file.
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2020-02-06 15:12:45 +01:00
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2020-02-10 Alan Modra <amodra@gmail.com>
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* config/obj-elf.c (obj_elf_change_section): Error for section
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type, attr or entsize changes in assembly.
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* testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test.
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* testsuite/gas/elf/section5.l: Update.
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2020-02-10 01:57:16 +01:00
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2020-02-10 Alan Modra <amodra@gmail.com>
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* output-file.c (output_file_close): Do a normal close when
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flag_always_generate_output.
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* write.c (write_object_file): Don't stop output when
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flag_always_generate_output.
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2020-02-07 15:53:46 +01:00
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2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25469
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* config/tc-z80.c: Add -gbz80 command line option to generate code
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for the GameBoy Z80. Add support for generating DWARF.
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* config/tc-z80.h: Add support for DWARF debug information
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generation.
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* doc/c-z80.texi: Document new command line option.
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* testsuite/gas/z80/gbz80_all.d: New file.
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* testsuite/gas/z80/gbz80_all.s: New file.
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* testsuite/gas/z80/z80.exp: Run the new tests.
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* testsuite/gas/z80/z80n_all.d: New file.
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* testsuite/gas/z80/z80n_all.s: New file.
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* testsuite/gas/z80/z80n_reloc.d: New file.
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ELF: Support the section flag 'o' in .section directive
As shown in
https://sourceware.org/bugzilla/show_bug.cgi?id=25490
--gc-sections will silently remove __patchable_function_entries section
and generate corrupt result. This patch adds the section flag 'o' to
.section directive:
.section __patchable_function_entries,"awo",@progbits,foo
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat
.section __patchable_function_entries,"awo",@progbits,bar,unique,4
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1
which specifies the symbol name which the section references. Assmebler
will set its elf_linked_to_section to a local section where the symbol
is defined.
Linker is updated to call mark_hook if gc_mark of any of its linked-to
sections is set after all sections, except for backend specific ones,
have been garbage collected.
bfd/
PR gas/25381
* bfd-in2.h: Regenerated.
* elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook
on section if gc_mark of any of its linked-to sections is set
and don't set gc_mark again.
* section.c (asection): Add linked_to_symbol_name to map_head
union.
gas/
PR gas/25381
* config/obj-elf.c (get_section): Also check
linked_to_symbol_name.
(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
(obj_elf_parse_section_letters): Handle the 'o' flag.
(build_group_lists): Renamed to ...
(build_additional_section_info): This. Set elf_linked_to_section
from map_head.linked_to_symbol_name.
(elf_adjust_symtab): Updated.
* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
* doc/as.texi: Document the 'o' flag.
* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
* testsuite/gas/elf/section18.d: New file.
* testsuite/gas/elf/section18.s: Likewise.
* testsuite/gas/elf/section19.d: Likewise.
* testsuite/gas/elf/section19.s: Likewise.
* testsuite/gas/elf/section20.d: Likewise.
* testsuite/gas/elf/section20.s: Likewise.
* testsuite/gas/elf/section21.d: Likewise.
* testsuite/gas/elf/section21.l: Likewise.
* testsuite/gas/elf/section21.s: Likewise.
ld/
PR ld/24526
PR ld/25021
PR ld/25490
* testsuite/ld-elf/elf.exp: Run PR ld/25490 tests.
* testsuite/ld-elf/pr24526.d: New file.
* testsuite/ld-elf/pr24526.s: Likewise.
* testsuite/ld-elf/pr25021.d: Likewise.
* testsuite/ld-elf/pr25021.s: Likewise.
* testsuite/ld-elf/pr25490-2-16.rd: Likewise.
* testsuite/ld-elf/pr25490-2-32.rd: Likewise.
* testsuite/ld-elf/pr25490-2-64.rd: Likewise.
* testsuite/ld-elf/pr25490-2.s: Likewise.
* testsuite/ld-elf/pr25490-3-16.rd: Likewise.
* testsuite/ld-elf/pr25490-3-32.rd: Likewise.
* testsuite/ld-elf/pr25490-3-64.rd: Likewise.
* testsuite/ld-elf/pr25490-3.s: Likewise.
* testsuite/ld-elf/pr25490-4-16.rd: Likewise.
* testsuite/ld-elf/pr25490-4-32.rd: Likewise.
* testsuite/ld-elf/pr25490-4-64.rd: Likewise.
* testsuite/ld-elf/pr25490-4.s: Likewise.
* testsuite/ld-elf/pr25490-5-16.rd: Likewise.
* testsuite/ld-elf/pr25490-5-32.rd: Likewise.
* testsuite/ld-elf/pr25490-5-64.rd: Likewise.
* testsuite/ld-elf/pr25490-5.s: Likewise.
* testsuite/ld-elf/pr25490-6-16.rd: Likewise.
* testsuite/ld-elf/pr25490-6-32.rd: Likewise.
* testsuite/ld-elf/pr25490-6-64.rd: Likewise.
* testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-07 03:04:58 +01:00
|
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|
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25381
|
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* config/obj-elf.c (get_section): Also check
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linked_to_symbol_name.
|
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(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
|
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(obj_elf_parse_section_letters): Handle the 'o' flag.
|
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(build_group_lists): Renamed to ...
|
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(build_additional_section_info): This. Set elf_linked_to_section
|
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from map_head.linked_to_symbol_name.
|
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(elf_adjust_symtab): Updated.
|
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* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
|
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* doc/as.texi: Document the 'o' flag.
|
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* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
|
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* testsuite/gas/elf/section18.d: New file.
|
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* testsuite/gas/elf/section18.s: Likewise.
|
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* testsuite/gas/elf/section19.d: Likewise.
|
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* testsuite/gas/elf/section19.s: Likewise.
|
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* testsuite/gas/elf/section20.d: Likewise.
|
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* testsuite/gas/elf/section20.s: Likewise.
|
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* testsuite/gas/elf/section21.d: Likewise.
|
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* testsuite/gas/elf/section21.l: Likewise.
|
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* testsuite/gas/elf/section21.s: Likewise.
|
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2020-02-06 16:50:16 +01:00
|
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|
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention x86 assembler options to align branches for
|
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|
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binutils 2.34.
|
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2020-02-06 13:44:39 +01:00
|
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2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
|
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* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique
|
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only for ELF targets.
|
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* testsuite/gas/i386/unique.d: Don't xfail.
|
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* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
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2020-02-06 01:22:29 +01:00
|
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|
2020-02-06 Alan Modra <amodra@gmail.com>
|
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* testsuite/gas/i386/unique.d: xfail for non-elf targets.
|
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* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
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2020-02-05 06:49:17 +01:00
|
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|
2020-02-06 Alan Modra <amodra@gmail.com>
|
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* testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in
|
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xfail, and rename test.
|
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* testsuite/gas/elf/section12b.d: Likewise.
|
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* testsuite/gas/elf/section16a.d: Likewise.
|
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* testsuite/gas/elf/section16b.d: Likewise.
|
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ELF: Add support for unique section ID to assembler
Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-03 02:07:51 +01:00
|
|
|
|
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25380
|
|
|
|
|
|
* config/obj-elf.c (section_match): Removed.
|
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|
|
|
|
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
|
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|
|
section_id.
|
|
|
|
|
|
(obj_elf_change_section): Replace info and group_name arguments
|
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|
|
|
|
with match_p. Also update the section ID and flags from match_p.
|
|
|
|
|
|
(obj_elf_section): Handle "unique,N". Update call to
|
|
|
|
|
|
obj_elf_change_section.
|
|
|
|
|
|
* config/obj-elf.h (elf_section_match): New.
|
|
|
|
|
|
(obj_elf_change_section): Updated.
|
|
|
|
|
|
* config/tc-arm.c (start_unwind_section): Update call to
|
|
|
|
|
|
obj_elf_change_section.
|
|
|
|
|
|
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (microblaze_s_data): Likewise.
|
|
|
|
|
|
(microblaze_s_sdata): Likewise.
|
|
|
|
|
|
(microblaze_s_rdata): Likewise.
|
|
|
|
|
|
(microblaze_s_bss): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (s_change_section): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_profiler): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (parse_rx_section): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
|
|
|
|
|
|
* doc/as.texi: Document "unique,N" in .section directive.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
|
|
|
|
|
|
* testsuite/gas/elf/section15.d: New file.
|
|
|
|
|
|
* testsuite/gas/elf/section15.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/unique.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/unique.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
|
|
|
|
|
|
|
2020-02-02 17:20:18 +01:00
|
|
|
|
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
|
|
|
|
|
|
|
2020-02-02 02:59:19 +01:00
|
|
|
|
2020-02-01 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-moxie.c (md_begin): Don't force big-endian mode.
|
|
|
|
|
|
|
2020-01-31 19:32:48 +01:00
|
|
|
|
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_cons): Handle %gotoff as well as
|
|
|
|
|
|
%tls_ldo.
|
|
|
|
|
|
|
2020-01-31 18:13:18 +01:00
|
|
|
|
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25472
|
|
|
|
|
|
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
|
|
|
|
|
|
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
|
|
|
|
|
|
+mve.
|
|
|
|
|
|
* testsuite/gas/arm/mve_dsp.d: New test.
|
|
|
|
|
|
|
2020-01-31 17:43:57 +01:00
|
|
|
|
2020-01-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE
|
|
|
|
|
|
rather than BFD_RELOC_NONE.
|
|
|
|
|
|
|
2020-01-31 17:16:19 +01:00
|
|
|
|
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
|
|
|
|
|
|
to support VLDMIA instruction for MVE.
|
|
|
|
|
|
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
* testsuite/gas/arm/mve-ldst.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-ldst.s: Likewise.
|
|
|
|
|
|
|
2020-01-31 15:45:51 +01:00
|
|
|
|
2020-01-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po: Updated French translation.
|
|
|
|
|
|
* po/ru.po: Updated Russian translation.
|
|
|
|
|
|
|
2020-01-31 09:03:56 +01:00
|
|
|
|
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
|
|
|
|
|
|
.s for the movprfx.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.d,
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.l,
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
|
|
|
|
|
|
|
2020-01-30 17:03:22 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_disp): Tighten base_opcode check.
|
|
|
|
|
|
* testsuite/gas/i386/got.s: Add LSL, MOVLPS, and BNDCN cases.
|
|
|
|
|
|
* testsuite/gas/i386/got-no-relax.d, testsuite/gas/i386/got.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
|
2020-01-30 13:59:04 +01:00
|
|
|
|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
|
|
|
|
|
|
* testsuite/gas/bpf/alu-be.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
|
|
|
|
|
|
* testsuite/gas/bpf/alu32-be.d: Likewise.
|
|
|
|
|
|
|
2020-01-30 11:36:33 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-2.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-4.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch.s: Add RETW cases.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-branch.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-2.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-4.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-30 11:35:20 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): .
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add IRET and LRET cases.
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET.
|
|
|
|
|
|
Add LRETQ case.
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without
|
|
|
|
|
|
suffix.
|
|
|
|
|
|
testsuite/gas/i386/x86_64.s: Add RETF cases.
|
|
|
|
|
|
* testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86_64-intel.d
|
|
|
|
|
|
testsuite/gas/i386/x86_64.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-suffix.e,
|
|
|
|
|
|
testsuite/gas/i386/x86_64.e: New.
|
|
|
|
|
|
|
2020-01-30 11:33:53 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Redo and move FLDENV et al
|
|
|
|
|
|
special case.
|
|
|
|
|
|
|
2020-01-27 13:38:10 +01:00
|
|
|
|
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/25445
|
|
|
|
|
|
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
|
|
|
|
|
|
movsxd.
|
|
|
|
|
|
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
|
|
|
|
|
|
differences. Document movslq and movsxd.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
|
|
|
|
|
|
|
2020-01-27 01:21:52 +01:00
|
|
|
|
2020-01-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Replace case statements with switch
|
|
|
|
|
|
statements.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/macros.exp: Likewise.
|
|
|
|
|
|
* testsuite/lib/gas-defs.exp: Likewise.
|
|
|
|
|
|
|
2020-01-27 11:40:02 +01:00
|
|
|
|
2020-01-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25403
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_4-a.s: Likewise.
|
|
|
|
|
|
|
2020-01-23 01:45:04 +01:00
|
|
|
|
2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
|
|
|
|
|
|
s exts must be known, so rename *ok* to *fail*.
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-sx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
|
|
|
|
|
|
above change.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.
|
|
|
|
|
|
|
2020-01-22 18:24:14 +01:00
|
|
|
|
2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (check_long_reg): Always disallow double word
|
|
|
|
|
|
suffix in mnemonic with word general register.
|
|
|
|
|
|
* testsuite/gas/i386/general.s: Replace word general register
|
|
|
|
|
|
with double word general register for movl.
|
|
|
|
|
|
* testsuite/gas/i386/inval.s: Add tests for movl with word general
|
|
|
|
|
|
register.
|
|
|
|
|
|
* testsuite/gas/i386/general.l: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/inval.l: Likewise.
|
|
|
|
|
|
|
PowerPC64 __tls_get_addr_desc
This implements register saving and restoring in the __tls_get_addr
call stub, so that when glibc supports the optimized tls call stub gcc
can generate code that assumes only r0, r12 and of course r3 are
changed on a __tls_get_addr call. When gcc expects __tls_get_addr
calls to preserve registers the call will be to __tls_get_addr_desc,
which will be translated by the linker to a call to __tls_get_addr_opt.
bfd/
* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
tga_desc_fd.
(is_tls_get_addr): Match tga_desc and tga_desc_df too.
(STDU_R1_0R1, ADDI_R1_R1): Define.
(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd. Indirect
tga_desc_fd to opt_fd, and tga_desc to opt. Set
no_tls_get_addr_regsave.
(branch_reloc_hash_match): Add hash3 and hash4.
(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
(ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_relocate_section): Likewise.
(plt_stub_size, build_plt_stub): Likewise. Size regsave
__tls_get_addr stub.
(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
eh_frame.
(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too. Size
eh_frame for regsave __tls_get_addr.
gas/
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
__tls_get_addr_desc and __tls_get_addr_opt.
ld/
* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
--tls-get-addr-regsave and --no-tls-get-addr-regsave.
(params): Init new field.
* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
Document.
* testsuite/ld-powerpc/tlsdesc.s,
* testsuite/ld-powerpc/tlsdesc.d,
* testsuite/ld-powerpc/tlsdesc.wf,
* testsuite/ld-powerpc/tlsdesc2.d,
* testsuite/ld-powerpc/tlsdesc2.wf,
* testsuite/ld-powerpc/tlsexenors.d,
* testsuite/ld-powerpc/tlsexenors.r,
* testsuite/ld-powerpc/tlsexers.d,
* testsuite/ld-powerpc/tlsexers.r,
* testsuite/ld-powerpc/tlsexetocnors.d,
* testsuite/ld-powerpc/tlsexetocrs.d,
* testsuite/ld-powerpc/tlsexetocrs.r,
* testsuite/ld-powerpc/tlsopt6.d,
* testsuite/ld-powerpc/tlsopt6.wf: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
2020-01-20 03:08:00 +01:00
|
|
|
|
2020-01-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
|
|
|
|
|
|
__tls_get_addr_desc and __tls_get_addr_opt.
|
|
|
|
|
|
|
2020-01-21 14:41:05 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.s: Add alignment directive.
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.l: Adjust expectations.
|
|
|
|
|
|
|
2020-01-21 08:30:05 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Merge CRC32 handling into
|
|
|
|
|
|
generic code path. Deal with No_lSuf being set in a template.
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
|
|
|
|
|
|
instead of error(s) when operand size is ambiguous.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add CRC32 tests.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
|
x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Drop SYSRET special case
|
|
|
|
|
|
and an intel_syntax check. Re-write lack-of-suffix processing
|
|
|
|
|
|
logic.
|
|
|
|
|
|
* doc/c-i386.texi: Document operand size defaults for suffix-
|
|
|
|
|
|
less AT&T syntax insns.
|
|
|
|
|
|
* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
|
|
|
|
|
|
testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx-scalar.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-bundle.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-lock-1.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse2avx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
|
|
|
|
|
|
* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-nops.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse-noavx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
|
|
|
|
|
|
insns.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add further tests.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-nops.d,
|
|
|
|
|
|
testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
|
|
|
|
|
|
testsuite/gas/i386/sse-noavx.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-nops.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse-noavx.d
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-01-21 08:25:31 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx512_bf16_vl.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Add broadcast forms
|
|
|
|
|
|
of VCVTNEPS2BF16{X,Y}. Add operand-size less Intel syntax
|
|
|
|
|
|
broadcast forms of VCVTNEPS2BF16.
|
|
|
|
|
|
* testsuite/gas/i386/avx512_bf16_vl.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-20 16:10:23 +01:00
|
|
|
|
2020-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
x86-64: Fix TLSDESC relaxation for x32
For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix
even if it isn't required. Otherwise linker can’t safely perform
GDesc -> IE/LE optimization. X32 TLSDESC sequences can be:
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
...
67 ff 10 call *x@TLSCALL(%eax)
or the same sequence as LP64:
48 8d 05 00 00 00 00 lea foo@TLSDESC(%rip), %reg
...
ff 10 call *foo@TLSCALL(%rax)
We need to support both sequences for x32. For both GDesc -> IE/LE
transitions,
67 ff 10 call *x@TLSCALL(%eax)
should relaxed to
0f 1f 00 nopl (%rax)
For GDesc -> LE transition,
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
should relaxed to
40 c7 c0 fc ff ff ff rex movl $x@tpoff, %reg
For GDesc -> IE transition,
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
should relaxed to
40 8b 05 00 00 00 00 rex movl x@gottpoff(%rip), %eax
bfd/
PR ld/25416
* elf64-x86-64.c (elf_x86_64_check_tls_transition): Support
"rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in
X32 mode.
(elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE
transition, relax "rex leal x@tlsdesc(%rip), %reg" to
"rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax
"rex leal x@tlsdesc(%rip), %reg" to
"rex movl x@gottpoff(%rip), %eax". For both transitions, relax
"call *(%eax)" to "nopl (%rax)".
gas/
PR ld/25416
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
x32 object.
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
R_X86_64_GOTPC32_TLSDESC relocation.
ld/
PR ld/25416
* testsuite/ld-x86-64/pr25416-1.s: New file
* testsuite/ld-x86-64/pr25416-1a.d: Likewise.
* testsuite/ld-x86-64/pr25416-1b.d: Likewise.
* testsuite/ld-x86-64/pr25416-1.s: Likewise.
* testsuite/ld-x86-64/pr25416-2.s: Likewise.
* testsuite/ld-x86-64/pr25416-2a.d: Likewise.
* testsuite/ld-x86-64/pr25416-2b.d: Likewise.
* testsuite/ld-x86-64/pr25416-3.d: Likewise.
* testsuite/ld-x86-64/pr25416-3.s: Likewise.
* testsuite/ld-x86-64/pr25416-4.d: Likewise.
* testsuite/ld-x86-64/pr25416-4.s: Likewise.
* testsuite/ld-x86-64/pr25416-5a.c: Likewise.
* testsuite/ld-x86-64/pr25416-5b.s: Likewise.
* testsuite/ld-x86-64/pr25416-5c.s: Likewise.
* testsuite/ld-x86-64/pr25416-5d.s: Likewise.
* testsuite/ld-x86-64/pr25416-5e.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
2020-01-20 15:58:51 +01:00
|
|
|
|
2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/25416
|
|
|
|
|
|
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
|
|
|
|
|
|
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
|
|
|
|
|
|
x32 object.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
|
|
|
|
|
|
R_X86_64_GOTPC32_TLSDESC relocation.
|
|
|
|
|
|
|
2020-01-18 15:12:07 +01:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/gas.pot: Regenerate.
|
|
|
|
|
|
|
2020-01-18 14:50:25 +01:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Binutils 2.34 branch created.
|
|
|
|
|
|
|
2020-01-17 16:07:55 +01:00
|
|
|
|
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
|
|
|
|
|
|
with vex_encoding_vex.
|
|
|
|
|
|
(parse_insn): Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
|
|
|
|
|
|
and {vex3} documentation.
|
|
|
|
|
|
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
|
|
|
|
|
|
{vex}.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
|
|
|
|
|
|
|
2020-01-16 14:50:52 +01:00
|
|
|
|
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25376
|
|
|
|
|
|
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
|
|
|
|
|
|
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
|
|
|
|
|
|
|
2020-01-16 10:07:36 +01:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_template): Drop found_cpu_match local
|
|
|
|
|
|
variable.
|
|
|
|
|
|
|
2020-01-16 10:05:35 +01:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/avx512dq-inval.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-01-15 14:17:27 +01:00
|
|
|
|
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
|
|
|
|
|
|
relocations when the target is 430X, except when extracting part of an
|
|
|
|
|
|
expression.
|
|
|
|
|
|
(msp430_srcoperand): Adjust comment.
|
|
|
|
|
|
Initialize the expp member of the msp430_operand_s struct as
|
|
|
|
|
|
appropriate.
|
|
|
|
|
|
(msp430_dstoperand): Likewise.
|
|
|
|
|
|
* testsuite/gas/msp430/msp430.exp: Run new test.
|
|
|
|
|
|
* testsuite/gas/msp430/reloc-lo-430x.d: New test.
|
|
|
|
|
|
* testsuite/gas/msp430/reloc-lo-430x.s: New test.
|
|
|
|
|
|
|
2020-01-15 06:45:43 +01:00
|
|
|
|
2020-01-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Add sparc-*-freebsd case.
|
|
|
|
|
|
|
2020-01-14 17:59:37 +01:00
|
|
|
|
2020-01-14 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1a.d: Updated for Darwin.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1d.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1e.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1f.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1g.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1h.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1i.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a,
|
|
|
|
|
|
x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin.
|
|
|
|
|
|
|
2020-01-14 14:13:57 +01:00
|
|
|
|
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25377
|
|
|
|
|
|
* config/tc-z80.c: Add support for half precision, single
|
|
|
|
|
|
precision and double precision floating point values.
|
|
|
|
|
|
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
|
|
|
|
|
|
* doc/as.texi: Add new z80 command line options.
|
|
|
|
|
|
* doc/c-z80.texi: Document new z80 command line options.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.s: New test.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/z80/z80.exp: Run the new test.
|
|
|
|
|
|
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
|
|
|
|
|
|
* testsuite/gas/z80/fp_zeda32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/strings.d: Update expected output.
|
|
|
|
|
|
|
2020-01-13 16:31:39 +01:00
|
|
|
|
2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
|
|
|
|
|
|
dependency.
|
|
|
|
|
|
|
2020-01-13 10:16:47 +01:00
|
|
|
|
2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
|
|
|
|
|
|
the CPU.
|
|
|
|
|
|
* config/tc-arc.h: Add header if/defs.
|
|
|
|
|
|
* testsuite/gas/arc/pseudos.d: Improve matching pattern.
|
|
|
|
|
|
|
2020-01-13 04:57:19 +01:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/wasm32/allinsn.d: Update expected output.
|
|
|
|
|
|
|
2020-01-12 10:46:22 +01:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
|
|
|
|
|
|
insertion.
|
|
|
|
|
|
|
2020-01-10 07:59:59 +01:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
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* testsuite/gas/elf/pr14891.s: Don't start directives in first column.
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* testsuite/gas/elf/pr21661.d: Don't run on hpux.
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2020-01-09 12:47:44 +01:00
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2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25224
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* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
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opcode byte values.
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(emit_ld_r_r): Likewise.
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(emit_ld_rr_m): Likewise.
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(emit_ld_rr_nn): Likewise.
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|
2020-01-09 11:40:04 +01:00
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|
2020-01-09 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding): Add
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is_any_vex_encoding() invocations. Drop respective
|
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i.tm.extension_opcode == None checks.
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2020-01-09 11:39:33 +01:00
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Check RegRex is clear during
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REX transformations. Correct comment indentation.
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2020-01-09 11:38:59 +01:00
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding): Generalize register
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transformation for TEST optimization.
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2020-01-09 11:38:01 +01:00
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/x86-64-sysenter-amd.s,
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testsuite/gas/i386/x86-64-sysenter-amd.d,
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testsuite/gas/i386/x86-64-sysenter-amd.l,
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testsuite/gas/i386/x86-64-sysenter-intel.d,
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testsuite/gas/i386/x86-64-sysenter-mixed.d: New.
|
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* testsuite/gas/i386/i386.exp: Run new tests.
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|
2020-01-08 18:00:54 +01:00
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|
2020-01-08 Nick Clifton <nickc@redhat.com>
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|
PR 25284
|
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|
|
* doc/as.texi (Align): Document the fact that all arguments can be
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|
|
omitted.
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|
(Balign): Likewise.
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|
(P2align): Likewise.
|
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|
|
2020-01-08 17:30:20 +01:00
|
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|
|
2020-01-08 Nick Clifton <nickc@redhat.com>
|
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|
|
PR 14891
|
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|
|
* config/obj-elf.c (obj_elf_section): Fail if the section name is
|
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|
|
|
|
already defined as a different symbol type.
|
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|
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|
|
* testsuite/gas/elf/pr14891.s: New test source file.
|
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|
|
* testsuite/gas/elf/pr14891.d: New test driver.
|
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|
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|
|
* testsuite/gas/elf/pr14891.s: New test expected error output.
|
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|
|
* testsuite/gas/elf/elf.exp: Run the new test.
|
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|
|
2020-01-08 02:12:36 +01:00
|
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|
|
2020-01-08 Alan Modra <amodra@gmail.com>
|
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|
|
|
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|
|
* config/tc-z8k.c (md_begin): Make idx unsigned.
|
|
|
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|
|
(get_specific): Likewise for this_index.
|
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|
|
2020-01-07 14:29:16 +01:00
|
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|
|
2020-01-07 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
|
* onfig/tc-arc.c (parse_reloc_symbol): New function.
|
|
|
|
|
|
(tokenize_arguments): Clean up, use parse_reloc_symbol function.
|
|
|
|
|
|
(md_operand): Set X_md to absent.
|
|
|
|
|
|
(arc_parse_name): Check for X_md.
|
|
|
|
|
|
|
2020-01-03 17:23:19 +01:00
|
|
|
|
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
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|
|
|
|
|
|
|
|
|
|
PR 25311
|
|
|
|
|
|
* as.h (TC_STRING_ESCAPES): Provide a default definition.
|
|
|
|
|
|
* app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of
|
|
|
|
|
|
NO_STRING_ESCAPES.
|
|
|
|
|
|
* read.c (next_char_of_string): Likewise.
|
|
|
|
|
|
* config/tc-ppc.h (TC_STRING_ESCAPES): Define.
|
|
|
|
|
|
* config/tc-z80.h (TC_STRING_ESCAPES): Define.
|
|
|
|
|
|
|
2020-01-03 13:59:54 +01:00
|
|
|
|
2020-01-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
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|
|
2020-01-03 10:16:44 +01:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
|
|
|
|
|
|
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-03 10:14:16 +01:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
|
|
|
|
|
|
by-element usdot. Add 64-bit form tests for by-element sudot.
|
|
|
|
|
|
* testsuite/gas/aarch64/i8mm.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-03 10:13:31 +01:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
|
|
|
|
|
|
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-03 10:12:49 +01:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/f64mm.d,
|
|
|
|
|
|
testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-02 15:10:40 +01:00
|
|
|
|
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add
|
|
|
|
|
|
support for assembler code generated by SDCC. Add new relocation
|
|
|
|
|
|
types. Add z80-elf target support.
|
|
|
|
|
|
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
|
|
|
|
|
|
labels. Local labels starts from ".L".
|
|
|
|
|
|
* NEWS: Mention the new support.
|
|
|
|
|
|
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
|
|
|
|
|
|
* testsuite/gas/all/fwdexp.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/all/cond.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/all/cond.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/all/fwdexp.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/all/fwdexp.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section2.e-mips: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app4.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/app4b.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
|
|
|
|
|
|
* testsuite/gas/z80/z80.exp: Add new tests
|
|
|
|
|
|
* testsuite/gas/z80/dollar.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/dollar.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_suf.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_isuf.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_suf.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/r800_extra.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/r800_extra.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/r800_ii8.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/r800_z80_doc.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z180.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z180.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z180_z80_doc.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_doc.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_doc.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_ii8.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_ii8.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_in_f_c.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_in_f_c.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_out_c_0.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_out_c_0.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_reloc.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_reloc.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_sli.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80_sli.s: New file.
|
|
|
|
|
|
|
2019-10-21 17:59:11 +02:00
|
|
|
|
2020-01-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
|
|
|
|
|
|
REGLIST_RN.
|
|
|
|
|
|
|
2020-01-01 09:22:19 +01:00
|
|
|
|
2020-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2020-01-01 08:37:11 +01:00
|
|
|
|
For older changes see ChangeLog-2019
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
2020-01-01 08:37:11 +01:00
|
|
|
|
Copyright (C) 2020 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|