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Append ".p2align 4" to some x86 directive tests Append ".p2align 4" to some x86 directive tests for explicit paddings for section alignment to avoid implicit section alignment in assembler listings. * testsuite/gas/i386/avx512vl-2.l: Append "#pass". * testsuite/gas/i386/noavx-1.l: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. * testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4". * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-26 16:55:38 +02:00
2016-05-26 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
* testsuite/gas/i386/noavx-1.l: Likewise.
* testsuite/gas/i386/nommx-1.l: Likewise.
* testsuite/gas/i386/nosse-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
* testsuite/gas/i386/noavx-1.s: Likewise.
* testsuite/gas/i386/nommx-1.s: Likewise.
* testsuite/gas/i386/nosse-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
metag: make an array's type unsigned char[] It contains values between 128 and 256 which fit in an unsigned char, but not a signed char, so we should explicitly use unsigned char to not rely on how these values are converted to signed char. gas/ChangeLog: 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-metag.c (metag_handle_align): Make the type of noop unsigned char.
2016-05-23 13:42:14 +02:00
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-metag.c (metag_handle_align): Make the type of noop
unsigned char.
rx: make the type of a variable bfd_reloc_code_real_type gas/ChangeLog: 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-rx.c (md_convert_frag): Make the type of reloc_type bfd_reloc_code_real_type.
2016-05-22 04:24:24 +02:00
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
bfd_reloc_code_real_type.
Require another match for AVX512VL The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit AVX512 instruction. We must match another AVX512 bit. PR gas/20140 * config/tc-i386.c (cpu_flags_match): Require another match for AVX512VL. * testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2, x86-64-avx512vl-1 and x86-64-avx512vl-2. * testsuite/gas/i386/avx512vl-1.l: New file. * testsuite/gas/i386/avx512vl-1.s: Likewise. * testsuite/gas/i386/avx512vl-2.l: Likewise. * testsuite/gas/i386/avx512vl-2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-25 23:59:05 +02:00
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20140
* config/tc-i386.c (cpu_flags_match): Require another match
for AVX512VL.
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
x86-64-avx512vl-1 and x86-64-avx512vl-2.
* testsuite/gas/i386/avx512vl-1.l: New file.
* testsuite/gas/i386/avx512vl-1.s: Likewise.
* testsuite/gas/i386/avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
Enable VREX for AVX512 directives Enable VREX for AVX512 instructions with upper 16 vector registers. gas/ PR gas/20141 * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. * testsuite/gas/i386/x86-64-pr20141.d: New file. * testsuite/gas/i386/x86-64-pr20141.s: Likewise. opcodes/ PR gas/20141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. * i386-init.h: Regenerated.
2016-05-25 19:49:25 +02:00
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20141
* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
* testsuite/gas/i386/x86-64-pr20141.d: New file.
* testsuite/gas/i386/x86-64-pr20141.s: Likewise.
Reimplement .no87/.nommx/.nosse/.noavx directives Move all .noXXX directives to cpu_noarch. gas/ * config/tc-i386.c (arch_entry): Remove negated. (noarch_entry): New struct. (cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx. (cpu_noarch): New. (set_cpu_arch): Check cpu_noarch after cpu_arch. (md_parse_option): Allow -march=+nosse. Check cpu_noarch after cpu_arch. (output_message): New function. (show_arch): Use it. Handle cpu_noarch. * testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3, nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2. * testsuite/gas/i386/noavx-1.l: New file. * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/noavx-2.s: Likewise. * testsuite/gas/i386/noavx-2.l: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nommx-2.s: Likewise. * testsuite/gas/i386/nommx-2.l: Likewise. * testsuite/gas/i386/nommx-3.s: Likewise. * testsuite/gas/i386/nommx-3.l: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/nosse-2.s: Likewise. * testsuite/gas/i386/nosse-2.l: Likewise. * testsuite/gas/i386/nosse-3.s: Likewise. * testsuite/gas/i386/nosse-3.l: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. * i386-init.h: Regenerated.
2016-05-25 19:25:50 +02:00
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (arch_entry): Remove negated.
(noarch_entry): New struct.
(cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx.
(cpu_noarch): New.
(set_cpu_arch): Check cpu_noarch after cpu_arch.
(md_parse_option): Allow -march=+nosse. Check cpu_noarch after
cpu_arch.
(output_message): New function.
(show_arch): Use it. Handle cpu_noarch.
* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
* testsuite/gas/i386/noavx-1.l: New file.
* testsuite/gas/i386/noavx-1.s: Likewise.
* testsuite/gas/i386/noavx-2.s: Likewise.
* testsuite/gas/i386/noavx-2.l: Likewise.
* testsuite/gas/i386/nommx-1.s: Likewise.
* testsuite/gas/i386/nommx-1.l: Likewise.
* testsuite/gas/i386/nommx-2.s: Likewise.
* testsuite/gas/i386/nommx-2.l: Likewise.
* testsuite/gas/i386/nommx-3.s: Likewise.
* testsuite/gas/i386/nommx-3.l: Likewise.
* testsuite/gas/i386/nosse-1.s: Likewise.
* testsuite/gas/i386/nosse-1.l: Likewise.
* testsuite/gas/i386/nosse-2.s: Likewise.
* testsuite/gas/i386/nosse-2.l: Likewise.
* testsuite/gas/i386/nosse-3.s: Likewise.
* testsuite/gas/i386/nosse-3.l: Likewise.
Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu. PR target/2006764 * config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64 instruction if supported by the currently selected fpu variant. * testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR. * testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-25 14:09:51 +02:00
2016-05-25 Chua Zheng Leong <chuazl@comp.nus.edu.sg>
Fix typo in changelog entry
2016-05-25 14:12:14 +02:00
PR target/20067
Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu. PR target/2006764 * config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64 instruction if supported by the currently selected fpu variant. * testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR. * testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-25 14:09:51 +02:00
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
instruction if supported by the currently selected fpu variant.
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA Do not convert jump relocs against local MIPS16 or microMIPS symbols to refer to a section symbol instead even on RELA targets, as it makes it impossible for the linker to make a JAL to JALX conversion based on ISA symbol annotation, breaking regular and compressed MIPS interlinking. gas/ * config/tc-mips.c (mips_fix_adjustable): Also return 0 for jump relocations against MIPS16 or microMIPS symbols on RELA targets. * testsuite/gas/mips/jalx-local.d: New test. * testsuite/gas/mips/jalx-local-n32.d: New test. * testsuite/gas/mips/jalx-local-n64.d: New test. * testsuite/gas/mips/jalx-local.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-local.d: New test. * testsuite/ld-mips-elf/jalx-local-n32.d: New test. * testsuite/ld-mips-elf/jalx-local-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-24 14:54:31 +02:00
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu. PR target/2006764 * config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64 instruction if supported by the currently selected fpu variant. * testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR. * testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-25 14:09:51 +02:00
MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA Do not convert jump relocs against local MIPS16 or microMIPS symbols to refer to a section symbol instead even on RELA targets, as it makes it impossible for the linker to make a JAL to JALX conversion based on ISA symbol annotation, breaking regular and compressed MIPS interlinking. gas/ * config/tc-mips.c (mips_fix_adjustable): Also return 0 for jump relocations against MIPS16 or microMIPS symbols on RELA targets. * testsuite/gas/mips/jalx-local.d: New test. * testsuite/gas/mips/jalx-local-n32.d: New test. * testsuite/gas/mips/jalx-local-n64.d: New test. * testsuite/gas/mips/jalx-local.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-local.d: New test. * testsuite/ld-mips-elf/jalx-local-n32.d: New test. * testsuite/ld-mips-elf/jalx-local-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-24 14:54:31 +02:00
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
jump relocations against MIPS16 or microMIPS symbols on RELA
targets.
* testsuite/gas/mips/jalx-local.d: New test.
* testsuite/gas/mips/jalx-local-n32.d: New test.
* testsuite/gas/mips/jalx-local-n64.d: New test.
* testsuite/gas/mips/jalx-local.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Cut TLS reloc dead code path in `md_apply_fix' With code refactoring made in commit b886a2ab0d52 and the addition of `calculate_reloc' and a separate test for TLS relocs against constants made there the preexisting fall-through from the TLS reloc switch case has effectively become a dead execution path. This is because the call to `calculate_reloc' present there is only made if `fixP->fx_done' is true, which can only be the case if `fixP->fx_addsy' is NULL, which in turn has already triggered the TLS reloc test and made execution break out of the switch statement. Remove the fall-through then and reshape code accordingly. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust code accordingly.
2016-05-24 15:05:19 +02:00
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_apply_fix)
<BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust
code accordingly.
xtensa: make map_suffix_reloc_to_operator return operatorT It always returns an element of the enum operatorT, so it should be clearer to make that the return type. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (struct suffix_reloc_map): Change type of field operator to operatorT. (map_suffix_reloc_to_operator): Change return type to operatorT.
2016-05-23 06:39:47 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct suffix_reloc_map): Change type of field
operator to operatorT.
(map_suffix_reloc_to_operator): Change return type to operatorT.
d30v: make var type operatorT gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-d30v.c (find_format): Change type of X_op to operatorT.
2016-05-22 09:39:00 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-d30v.c (find_format): Change type of X_op to operatorT.
mmix: constify handler_charp gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-mmix.c (mmix_parse_predefined_name): Change type of handler_charp to const char *.
2016-05-22 06:32:22 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mmix.c (mmix_parse_predefined_name): Change type of
handler_charp to const char *.
ft32: fixup TARGET_FORMAT Nothing ever assigns to ft32_target_format, so its always null, which means the bfd target arch is the default one. It looks like ft32 only has one target format, so we can just define TARGET_FORMAT to be that literal string. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove. (ft32_target_format): Likewise. (TARGET_FORMAT): Adjust.
2016-05-21 10:21:32 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove.
(ft32_target_format): Likewise.
(TARGET_FORMAT): Adjust.
ia64: use XOBNEW and XOBNEWVEC gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ia64.c (dot_rot): simplify allocations from obstacks. (ia64_frob_label): Likewise.
2016-05-20 12:33:35 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (dot_rot): simplify allocations from obstacks.
(ia64_frob_label): Likewise.
change some variable's type to op_err They only hold values from the op_err enum, so it should be clearer to give them the enum type. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-cr16.c (check_range): Make type of retval op_err. * config/tc-crx.c: Likewise.
2016-05-13 10:05:59 +02:00
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-cr16.c (check_range): Make type of retval op_err.
* config/tc-crx.c: Likewise.
[ARC] Add XY registers, update neg instruction. gas/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_begin): Add XY registers. (cpu_types): Code density is default off for ARC EM. opcodes/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (neg): New instruction variant.
2016-05-19 12:33:17 +02:00
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_begin): Add XY registers.
(cpu_types): Code density is default off for ARC EM.
[ARC] Rename "class" named attributes. gas/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * config/tc-arc.c (attributes_t): Renamed attribute class to attr_class. (find_opcode_match, assemble_insn, tokenize_extinsn): Changed. opcode/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * arc-dis.c (find_format, find_format, get_auxreg) (print_insn_arc): Changed. * arc-ext.h (INSERT_XOP): Likewise. include/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * opcode/arc.h (struct arc_opcode): Renamed attribute class to insn_class. (struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23 17:25:46 +02:00
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (attributes_t): Renamed attribute class to
attr_class.
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
oops - omitted from previous delta
2016-05-23 14:56:46 +02:00
2016-05-23 Kuba Sejdak <jakub.sejdak@phoesys.com>
* configuse.tgt: Add entry for arm-phoenix.
tic54x: use concat more gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_sect): simplify string creation.
2016-05-19 04:48:34 +02:00
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_sect): simplify string creation.
spu: make some constants unsigned The field in spu_opcode is unsigned, and for some values of opcode we can end up shifting into the high bit. So avoid possibly creating a negative number and then assigning it to a unsigned field by shifting an unsigned constant. gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
2016-05-19 04:39:18 +02:00
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
tic54x: rename typedef of struct symbol_ generic gas code has a struct symbol, and tic54x typedefs a struct to symbol. This seems at least rather confusing, and it seems like target specific headers shouldn't put such generic names in the global namespace preventing other generic code from using them. opcodes/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * tic54x-dis.c (sprint_mmr): Adjust. * tic54x-opc.c: Likewise. gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_mmregs): Adjust. (md_begin): Likewise. (encode_condition): Likewise. (encode_cc3): Likewise. (encode_cc2): Likewise. (encode_operand): Likewise. (tic54x_undefined_symbol): Likewise. include/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of plain symbol.
2016-05-19 05:48:48 +02:00
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_mmregs): Adjust.
(md_begin): Likewise.
(encode_condition): Likewise.
(encode_cc3): Likewise.
(encode_cc2): Likewise.
(encode_operand): Likewise.
(tic54x_undefined_symbol): Likewise.
MIPS: Add support for P6600 gas/ * config/tc-mips.c (mips_cpu_info_table): Update comment. Add p6600 entry. * doc/c-mips.texi: Document p6600 -march option.
2016-05-20 16:20:42 +02:00
2016-05-20 Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (mips_cpu_info_table): Update comment. Add
p6600 entry.
* doc/c-mips.texi: Document p6600 -march option.
Preserve addend for R_386_GOT32 and R_X86_64_GOT32 We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in "movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax". PR gas/19600 * config/tc-i386.c (md_apply_fix): Preserve addend for BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32. * testsuite/gas/i386/addend.d: New file. * testsuite/gas/i386/addend.s: Likewise. * testsuite/gas/i386/x86-64-addend.d: Likewise. * testsuite/gas/i386/x86-64-addend.s: Likewise. * testsuite/gas/i386/i386.exp: Run addend and x86-64-addend. * testsuite/gas/i386/reloc32.d: Updated.
2016-05-20 15:01:28 +02:00
2016-05-20 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19600
* config/tc-i386.c (md_apply_fix): Preserve addend for
BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
* testsuite/gas/i386/addend.d: New file.
* testsuite/gas/i386/addend.s: Likewise.
* testsuite/gas/i386/x86-64-addend.d: Likewise.
* testsuite/gas/i386/x86-64-addend.s: Likewise.
* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
* testsuite/gas/i386/reloc32.d: Updated.
MIPS: Fix the encoding of immediates with microMIPS JALX The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation with microMIPS J/JAL/JALS instructions, however unlike the latters its encoded immediate argument is unusually shifted left by 2 rather than 1 in calculating the value used for the operation requested. We already handle this exception in `mips_elf_calculate_relocation' in LD, in a scenario where JALX is produced as a result of relaxing JAL for the purpose of making a cross-mode jump. We also get it right in the disassembler in `decode_micromips_operand'. What we don't correctly do however is processing microMIPS JALX produced by GAS from an assembly source, where a non-zero constant argument or a symbol reference with a non-zero in-place addend has been used. In this case the same calculation is made as for microMIPS J/JAL/JALS, causing the wrong encoding to be produced by GAS on making an object file, and then again by LD in the final link. The latter in particular causes the calculation, where the addend fits in the relocatable field, to produce different final addresses for the same source code depending on whether REL or RELA relocations are used. Correct these issues by special-casing microMIPS JALX in the places that have been previously missed. bfd/ * elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for microMIPS JALX. gas/ * config/tc-mips.c (append_insn): Correct the encoding of a constant argument for microMIPS JALX. (tc_gen_reloc): Correct the encoding of an in-place addend for microMIPS JALX. * testsuite/gas/mips/jalx-addend.d: New test. * testsuite/gas/mips/jalx-addend-n32.d: New test. * testsuite/gas/mips/jalx-addend-n64.d: New test. * testsuite/gas/mips/jalx-imm.d: New test. * testsuite/gas/mips/jalx-imm-n32.d: New test. * testsuite/gas/mips/jalx-imm-n64.d: New test. * testsuite/gas/mips/jalx-addend.s: New test source. * testsuite/gas/mips/jalx-imm.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-addend.d: New test. * testsuite/ld-mips-elf/jalx-addend-n32.d: New test. * testsuite/ld-mips-elf/jalx-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-20 14:32:19 +02:00
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Correct the encoding of a
constant argument for microMIPS JALX.
(tc_gen_reloc): Correct the encoding of an in-place addend for
microMIPS JALX.
* testsuite/gas/mips/jalx-addend.d: New test.
* testsuite/gas/mips/jalx-addend-n32.d: New test.
* testsuite/gas/mips/jalx-addend-n64.d: New test.
* testsuite/gas/mips/jalx-imm.d: New test.
* testsuite/gas/mips/jalx-imm-n32.d: New test.
* testsuite/gas/mips/jalx-imm-n64.d: New test.
* testsuite/gas/mips/jalx-addend.s: New test source.
* testsuite/gas/mips/jalx-imm.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Correct tab-after-space formatting mistakes * config/tc-mips.c: Correct tab-after-space formatting mistakes throughout.
2016-05-20 13:41:50 +02:00
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c: Correct tab-after-space formatting mistakes
throughout.
gas/arc: Make member of arc_flags const By making the flgp field of struct arc_flags constant we can remove a place where we cast away the const-ness of a variable. Also, given that the value assigned to this field almost always comes from compile-time constant data, having the field non-constant is probably a bad thing. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Remove casting away of const. * config/tc-arc.h (struct arc_flags): Make flgp field const.
2016-05-06 14:59:03 +02:00
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Remove casting away of
const.
* config/tc-arc.h (struct arc_flags): Make flgp field const.
gas/arc: Use BFD_VMA_FMT for printf format specifier Some debug code has the wrong printf format specifier for some types that are (ultimately) bfd_vma. Fixed by using BFD_VMA_FMT string. This only becomes an issue when building the tc-arc.c file with -DDEBUG=1 to build in the debug code. gas/ChangeLog: * config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where appropriate. (md_convert_frag): Likewise.
2016-05-04 15:11:11 +02:00
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
appropriate.
(md_convert_frag): Likewise.
gas/arc: Fix array overrun when checking opcode array The opcode array iterator mechanism can, in some situations, result in reading memory outside of the opcode array. When using the iterator-next mechanism to find the next possible arc_opcode, if we find an opcode where the name field is NULL, or the name does not match, then the cached opcode pointer is not set to NULL. The result is that another call to iterator-next will again increment the opcode pointer (which might now point outside the opcode array) and attempt to access the name field of this undefined opcode. Fixed in this commit by clearing the cached opcode pointer. I've added a test case, which currently shows the bug, however, this will only expose this bug while the opcode used (dsp_fp_cmp) is the last opcode in the table. gas/ChangeLog: * config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set cached opcode to NULL when we reach a non-matching opcode. * testsuite/gas/arc/asm-errors-2.d: New file. * testsuite/gas/arc/asm-errors-2.err: New file. * testsuite/gas/arc/asm-errors-2.s: New file.
2016-05-04 14:57:10 +02:00
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
cached opcode to NULL when we reach a non-matching opcode.
* testsuite/gas/arc/asm-errors-2.d: New file.
* testsuite/gas/arc/asm-errors-2.err: New file.
* testsuite/gas/arc/asm-errors-2.s: New file.
gas/arc: Add guard against operand array overflow. Currently supplying an input file with too many operands to an instruction will cause the assembler to overflow and array and trigger undefined behaviour. This change checks that we don't access outside the limits of the operand array. gas/ChangeLog: * config/tc-arc.c (tokenize_arguments): Add checks for array overflow. * testsuite/gas/arc/asm-errors.s: Addition test line added. * testsuite/gas/arc/asm-errors.err: Update expected results.
2016-05-03 14:43:44 +02:00
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
rx: make field type enum gas/ChangeLog: 2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-rx.c (struct cpu_type): Change the type of a field from int to enum rx_cpu_types.
2016-05-14 10:33:53 +02:00
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (struct cpu_type): Change the type of a field from
int to enum rx_cpu_types.
change the type of some fields to bfd_reloc_code_real_type gas/ChangeLog: 2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-dlx.c (struct machine_it): change the type of a field from int to bfd_reloc_code_real_type. * config/tc-tic4x.c: Likewise.
2016-05-14 08:34:23 +02:00
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-dlx.c (struct machine_it): change the type of a field from
int to bfd_reloc_code_real_type.
* config/tc-tic4x.c: Likewise.
commit ChangeLog for previous commit
2016-05-18 12:17:33 +02:00
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-v850.c (v850_target_arch): change type to enum
bfd_architecture.
* config/tc-v850.h (v850_target_arch): Likewise.
PPC_OPERAND_SIGNOPT range. Commit b84bf58a accidentally extended the range of allowed negative numbers. * config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT allowed negative range. * testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256. * testsuite/gas/ppc/power9.d: Update.
2016-05-18 03:57:56 +02:00
2016-05-18 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
allowed negative range.
* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
* testsuite/gas/ppc/power9.d: Update.
Make ARMv8-M GAS tests pass on non ELF targets 2016-05-17 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * testsuite/gas/arm/archv8m-cmse-msr-base.d: Force Thumb when disassembling and stop skipping targets. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. * testsuite/gas/arm/archv8m-base.d: Also allow nops after the last instruction for targets that have stronger alignment requirement. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main.d: Likewise. * testsuite/gas/arm/archv8m.s: Add label. * testsuite/gas/arm/archv8m-cmse.s: Likewise. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.
2016-05-17 17:35:12 +02:00
2016-05-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Force Thumb when
disassembling and stop skipping targets.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
* testsuite/gas/arm/archv8m-base.d: Also allow nops after the last
instruction for targets that have stronger alignment requirement.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main.d: Likewise.
* testsuite/gas/arm/archv8m.s: Add label.
* testsuite/gas/arm/archv8m-cmse.s: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise.
m32r: make mach_table static and const It is only read in tc-m32r.c, so it might as well be static and const, and that should help the compiler slightly. gas/ChangeLog: 2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-m32r.c (mach_table): Make static and const.
2016-05-14 22:31:45 +02:00
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32r.c (mach_table): Make static and const.
tc-vax.c: make prototype of flonum_gen2vax match its definition gas/ChangeLog: 2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-vax.c (flonum_gen2vax): Adjust prototype to match definition.
2016-05-14 08:34:02 +02:00
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-vax.c (flonum_gen2vax): Adjust prototype to match
definition.
stop defining linkrelax in multiple places Defining linkrelax to have different values in as.c and tc-msp430.c / tc-mn10300.c is at least rather tricky, and seems fragile, when we can just set it in md_begin instead. gas/ChangeLog: 2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-mn10300.c (md_begin): set linkrelax here instead of defining it. * config/tc-msp430.c (md_begin): Likewise.
2016-05-14 06:34:05 +02:00
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mn10300.c (md_begin): set linkrelax here instead of
defining it.
* config/tc-msp430.c (md_begin): Likewise.
m68hc11: make some vars type bfd_reloc_code_real_type These variables only hold values from the bfd_reloc_code_real_type enum, and are passed to functions that expect the argument to be of type bfd_reloc_code_real_type, so it seems to make sense that there type is bfd_reloc_code_real_type rather than int. gas/ChangeLog: 2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-m68hc11.c (fixup8): Change variables type from int to bfd_reloc_code_real_type where appropriate. (fixup16): Likewise. (fixup8_xg): Likewise.
2016-05-14 21:27:26 +02:00
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m68hc11.c (fixup8): Change variables type from int to
bfd_reloc_code_real_type where appropriate.
(fixup16): Likewise.
(fixup8_xg): Likewise.
SH64/GAS: Fix a -Wwrite-strings build failure Fix a commit 6757cf57697d ("enable -Wwrite-strings for gas") regression. gas/ * config/tc-sh64.c (shmedia_check_limits): Constify `msg'.
2016-05-16 00:14:52 +02:00
2016-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-sh64.c (shmedia_check_limits): Constify `msg'.
Accept valid one byte signed and unsigned values for the IMM8 operand. opcodes/ * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. gas/ * testsuite/gas/ppc/power9.d <xxspltib>: Add additional operand tests. * testsuite/gas/ppc/power9.s: Likewise.
2016-05-13 22:15:00 +02:00
2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <xxspltib>: Add additional operand tests.
* testsuite/gas/ppc/power9.s: Likewise.
Fix build breakage * config/obj-coff.c (weak_uniquify): Delete unused var.
2016-05-13 08:27:10 +02:00
2016-05-13 Alan Modra <amodra@gmail.com>
* config/obj-coff.c (weak_uniquify): Delete unused var.
use XNEW and related macros more Its a bit shorter and simpler than raw xmalloc. gas/ChangeLog: 2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * app.c (app_push): Use XNEW and related macros. * as.c (parse_args): Likewise. * cgen.c (make_right_shifted_expr): Likewise. (gas_cgen_tc_gen_reloc): Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff.c (stack_init): Likewise. (stack_push): Likewise. (coff_obj_symbol_new_hook): Likewise. (coff_obj_symbol_clone_hook): Likewise. (add_lineno): Likewise. (coff_frob_symbol): Likewise. * config/obj-elf.c (obj_elf_section_name): Likewise. (build_group_lists): Likewise. * config/obj-evax.c (evax_symbol_new_hook): Likewise. * config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise. * config/tc-aarch64.c (insert_reg_alias): Likewise. (find_or_make_literal_pool): Likewise. (add_to_lit_pool): Likewise. (fill_instruction_hash_table): Likewise. * config/tc-alpha.c (load_expression): Likewise. (emit_jsrjmp): Likewise. (s_alpha_ent): Likewise. (s_alpha_end): Likewise. (s_alpha_linkage): Likewise. (md_begin): Likewise. (tc_gen_reloc): Likewise. * config/tc-arc.c (arc_insert_opcode): Likewise. (arc_extcorereg): Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c (preprocess_reglist): Likewise. * config/tc-d10v.c: Likewise. * config/tc-frv.c (frv_insert_vliw_insn): Likewise. (frv_tomcat_shuffle): Likewise. * config/tc-h8300.c: Likewise. * config/tc-i370.c (i370_macro): Likewise. * config/tc-i386.c (lex_got): Likewise. (md_parse_option): Likewise. * config/tc-ia64.c (alloc_record): Likewise. (set_imask): Likewise. (save_prologue_count): Likewise. (dot_proc): Likewise. (dot_endp): Likewise. (ia64_frob_label): Likewise. (add_qp_imply): Likewise. (add_qp_mutex): Likewise. (mark_resource): Likewise. (dot_alias): Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. (s_save): Likewise. (mri_control_label): Likewise. (push_mri_control): Likewise. (build_mri_control_operand): Likewise. (s_mri_else): Likewise. (s_mri_break): Likewise. (s_mri_next): Likewise. (s_mri_for): Likewise. (s_mri_endw): Likewise. * config/tc-metag.c (create_mnemonic_htab): Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c (s_loc): Likewise. * config/tc-nds32.c (nds32_relax_hint): Likewise. * config/tc-nios2.c (nios2_insn_reloc_new): Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c (shmedia_frob_section_type): Likewise. * config/tc-sparc.c: Likewise. * config/tc-spu.c: Likewise. * config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise. (tic6x_start_unwind_section): Likewise. * config/tc-tilegx.c: Likewise. * config/tc-tilepro.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise. (new_resource_table): Likewise. (resize_resource_table): Likewise. (xtensa_create_trampoline_frag): Likewise. (xtensa_maybe_create_literal_pool_frag): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c (append_transition): Likewise. (append_condition): Likewise. (append_value_condition): Likewise. (append_constant_value_condition): Likewise. (append_literal_op): Likewise. (append_label_op): Likewise. (append_constant_op): Likewise. (append_field_op): Likewise. (append_user_fn_field_op): Likewise. (enter_opname_n): Likewise. (enter_opname): Likewise. (split_string): Likewise. (parse_insn_templ): Likewise. (clone_req_or_option_list): Likewise. (clone_req_option_list): Likewise. (parse_option_cond): Likewise. (parse_insn_pattern): Likewise. (parse_insn_repl): Likewise. (build_transition): Likewise. (build_transition_table): Likewise. * dw2gencfi.c (alloc_fde_entry): Likewise. (alloc_cfi_insn_data): Likewise. (cfi_add_CFA_remember_state): Likewise. (dot_cfi_escape): Likewise. (dot_cfi_fde_data): Likewise. (select_cie_for_fde): Likewise. * dwarf2dbg.c (dwarf2_directive_loc): Likewise. * ecoff.c (ecoff_add_bytes): Likewise. (ecoff_build_debug): Likewise. * input-scrub.c (input_scrub_push): Likewise. (input_scrub_begin): Likewise. (input_scrub_next_buffer): Likewise. * itbl-ops.c (append_insns_as_macros): Likewise. (alloc_entry): Likewise. (alloc_field): Likewise. * listing.c (listing_newline): Likewise. (listing_listing): Likewise. * macro.c (get_any_string): Likewise. (delete_macro): Likewise. * stabs.c (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * subsegs.c (subseg_change): Likewise. (subseg_get): Likewise. * symbols.c (define_dollar_label): Likewise. (symbol_relc_make_sym): Likewise. * write.c (write_relocs): Likewise.
2016-04-06 22:26:46 +02:00
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* app.c (app_push): Use XNEW and related macros.
* as.c (parse_args): Likewise.
* cgen.c (make_right_shifted_expr): Likewise.
(gas_cgen_tc_gen_reloc): Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff.c (stack_init): Likewise.
(stack_push): Likewise.
(coff_obj_symbol_new_hook): Likewise.
(coff_obj_symbol_clone_hook): Likewise.
(add_lineno): Likewise.
(coff_frob_symbol): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(build_group_lists): Likewise.
* config/obj-evax.c (evax_symbol_new_hook): Likewise.
* config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise.
* config/tc-aarch64.c (insert_reg_alias): Likewise.
(find_or_make_literal_pool): Likewise.
(add_to_lit_pool): Likewise.
(fill_instruction_hash_table): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(emit_jsrjmp): Likewise.
(s_alpha_ent): Likewise.
(s_alpha_end): Likewise.
(s_alpha_linkage): Likewise.
(md_begin): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (arc_insert_opcode): Likewise.
(arc_extcorereg): Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c (preprocess_reglist): Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-frv.c (frv_insert_vliw_insn): Likewise.
(frv_tomcat_shuffle): Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-i370.c (i370_macro): Likewise.
* config/tc-i386.c (lex_got): Likewise.
(md_parse_option): Likewise.
* config/tc-ia64.c (alloc_record): Likewise.
(set_imask): Likewise.
(save_prologue_count): Likewise.
(dot_proc): Likewise.
(dot_endp): Likewise.
(ia64_frob_label): Likewise.
(add_qp_imply): Likewise.
(add_qp_mutex): Likewise.
(mark_resource): Likewise.
(dot_alias): Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c (m68k_frob_label): Likewise.
(s_save): Likewise.
(mri_control_label): Likewise.
(push_mri_control): Likewise.
(build_mri_control_operand): Likewise.
(s_mri_else): Likewise.
(s_mri_break): Likewise.
(s_mri_next): Likewise.
(s_mri_for): Likewise.
(s_mri_endw): Likewise.
* config/tc-metag.c (create_mnemonic_htab): Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mmix.c (s_loc): Likewise.
* config/tc-nds32.c (nds32_relax_hint): Likewise.
* config/tc-nios2.c (nios2_insn_reloc_new): Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c (shmedia_frob_section_type): Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-spu.c: Likewise.
* config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise.
(tic6x_start_unwind_section): Likewise.
* config/tc-tilegx.c: Likewise.
* config/tc-tilepro.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise.
(new_resource_table): Likewise.
(resize_resource_table): Likewise.
(xtensa_create_trampoline_frag): Likewise.
(xtensa_maybe_create_literal_pool_frag): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c (append_transition): Likewise.
(append_condition): Likewise.
(append_value_condition): Likewise.
(append_constant_value_condition): Likewise.
(append_literal_op): Likewise.
(append_label_op): Likewise.
(append_constant_op): Likewise.
(append_field_op): Likewise.
(append_user_fn_field_op): Likewise.
(enter_opname_n): Likewise.
(enter_opname): Likewise.
(split_string): Likewise.
(parse_insn_templ): Likewise.
(clone_req_or_option_list): Likewise.
(clone_req_option_list): Likewise.
(parse_option_cond): Likewise.
(parse_insn_pattern): Likewise.
(parse_insn_repl): Likewise.
(build_transition): Likewise.
(build_transition_table): Likewise.
* dw2gencfi.c (alloc_fde_entry): Likewise.
(alloc_cfi_insn_data): Likewise.
(cfi_add_CFA_remember_state): Likewise.
(dot_cfi_escape): Likewise.
(dot_cfi_fde_data): Likewise.
(select_cie_for_fde): Likewise.
* dwarf2dbg.c (dwarf2_directive_loc): Likewise.
* ecoff.c (ecoff_add_bytes): Likewise.
(ecoff_build_debug): Likewise.
* input-scrub.c (input_scrub_push): Likewise.
(input_scrub_begin): Likewise.
(input_scrub_next_buffer): Likewise.
* itbl-ops.c (append_insns_as_macros): Likewise.
(alloc_entry): Likewise.
(alloc_field): Likewise.
* listing.c (listing_newline): Likewise.
(listing_listing): Likewise.
* macro.c (get_any_string): Likewise.
(delete_macro): Likewise.
* stabs.c (generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
* subsegs.c (subseg_change): Likewise.
(subseg_get): Likewise.
* symbols.c (define_dollar_label): Likewise.
(symbol_relc_make_sym): Likewise.
* write.c (write_relocs): Likewise.
use xstrdup, xmemdup0 and concat more gas/ChangeLog: 2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/obj-coff.c (obj_coff_def): Simplify string copying. (weak_name2altname): Likewise. (weak_uniquify): Likewise. (obj_coff_section): Likewise. (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_section_name): Likewise. (obj_elf_init_stab_section): Likewise. * config/obj-evax.c (evax_shorten_name): Likewise. * config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise. * config/tc-aarch64.c (create_register_alias): Likewise. * config/tc-alpha.c (load_expression): Likewise. (s_alpha_file): Likewise. (s_alpha_section_name): Likewise. (tc_gen_reloc): Likewise. * config/tc-arc.c (md_assemble): Likewise. * config/tc-arm.c (create_neon_reg_alias): Likewise. (start_unwind_section): Likewise. * config/tc-hppa.c (pa_build_unwind_subspace): Likewise. (hppa_elf_mark_end_of_function): Likewise. * config/tc-nios2.c (nios2_modify_arg): Likewise. (nios2_negate_arg): Likewise. * config/tc-rx.c (rx_section): Likewise. * config/tc-sh64.c (sh64_consume_datalabel): Likewise. * config/tc-tic30.c (tic30_find_parallel_insn): Likewise. * config/tc-tic54x.c (tic54x_include): Likewise. (tic54x_macro_info): Likewise. (subsym_get_arg): Likewise. (subsym_substitute): Likewise. (tic54x_start_line_hook): Likewise. * config/tc-xtensa.c (xtensa_literal_prefix): Likewise. (xg_reverse_shift_count): Likewise. * config/xtensa-relax.c (enter_opname_n): Likewise. (split_string): Likewise. * dwarf2dbg.c (get_filenum): Likewise. (process_entries): Likewise. * expr.c (operand): Likewise. * itbl-ops.c (alloc_entry): Likewise. * listing.c (listing_message): Likewise. (listing_title): Likewise. * macro.c (check_macro): Likewise. * stabs.c (s_xstab): Likewise. * symbols.c (symbol_relc_make_expr): Likewise. * write.c (compress_debug): Likewise.
2016-03-28 11:49:15 +02:00
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-coff.c (obj_coff_def): Simplify string copying.
(weak_name2altname): Likewise.
(weak_uniquify): Likewise.
(obj_coff_section): Likewise.
(obj_coff_init_stab_section): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(obj_elf_init_stab_section): Likewise.
* config/obj-evax.c (evax_shorten_name): Likewise.
* config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise.
* config/tc-aarch64.c (create_register_alias): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(s_alpha_file): Likewise.
(s_alpha_section_name): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (md_assemble): Likewise.
* config/tc-arm.c (create_neon_reg_alias): Likewise.
(start_unwind_section): Likewise.
* config/tc-hppa.c (pa_build_unwind_subspace): Likewise.
(hppa_elf_mark_end_of_function): Likewise.
* config/tc-nios2.c (nios2_modify_arg): Likewise.
(nios2_negate_arg): Likewise.
* config/tc-rx.c (rx_section): Likewise.
* config/tc-sh64.c (sh64_consume_datalabel): Likewise.
* config/tc-tic30.c (tic30_find_parallel_insn): Likewise.
* config/tc-tic54x.c (tic54x_include): Likewise.
(tic54x_macro_info): Likewise.
(subsym_get_arg): Likewise.
(subsym_substitute): Likewise.
(tic54x_start_line_hook): Likewise.
* config/tc-xtensa.c (xtensa_literal_prefix): Likewise.
(xg_reverse_shift_count): Likewise.
* config/xtensa-relax.c (enter_opname_n): Likewise.
(split_string): Likewise.
* dwarf2dbg.c (get_filenum): Likewise.
(process_entries): Likewise.
* expr.c (operand): Likewise.
* itbl-ops.c (alloc_entry): Likewise.
* listing.c (listing_message): Likewise.
(listing_title): Likewise.
* macro.c (check_macro): Likewise.
* stabs.c (s_xstab): Likewise.
* symbols.c (symbol_relc_make_expr): Likewise.
* write.c (compress_debug): Likewise.
Use correct regexp syntax in ARM PR20068 test
2016-05-12 18:19:44 +02:00
2016-05-12 Nick Clifton <nickc@redhat.com>
PR target/20068
* testsuite/gas/arm/pr20068.d: Use correct regexp syntax.
Update pr20068 test to allow for big endian ARM configuration
2016-05-11 19:04:03 +02:00
2016-05-11 Nick Clifton <nickc@redhat.com>
PR target/20068
* testsuite/gas/arm/pr20068.d: Adjust expected output to allow for
big endian ARM configurations.
Add MIPS32 DSPr3 support. bfd/ * elfxx-mips.c (print_mips_ases): Add DSPR3. binutils/ * readelf.c (print_mips_ases): Add DSPR3. gas/ * config/tc-mips.c (options): Add OPTION_DSPR3 and OPTION_NO_DSPR3. (md_longopts): Likewise. (md_show_usage): Add help for -mdspr3 and -mno-dspr3. (mips_ases): Define availability for DSPr3. (mips_ase_groups): Add ASE_DSPR3 to the DSP group. (mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3. * doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2 formatting. * doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and .set nodspr3. Fix -mdspr2 formatting. * testsuite/gas/mips/mips32-dspr3.d: New file. * testsuite/gas/mips/mips32-dspr3.s: Likewise. * testsuite/gas/mips/mips.exp: Run mips32-dspr3 test. include/ * elf/mips.h (AFL_ASE_DSPR3): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3. * opcode/mips.h (ASE_DSPR3): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and mips64r6. * mips-opc.c (D34): New macro. (mips_builtin_opcodes): Define bposge32c for DSPr3.
2014-11-26 12:15:01 +01:00
2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (options): Add OPTION_DSPR3 and
OPTION_NO_DSPR3.
(md_longopts): Likewise.
(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
(mips_ases): Define availability for DSPr3.
(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
* doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
formatting.
* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
.set nodspr3. Fix -mdspr2 formatting.
* testsuite/gas/mips/mips32-dspr3.d: New file.
* testsuite/gas/mips/mips32-dspr3.s: Likewise.
* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
Ensure that padding in the constant pool uses constant values. PR target/20068 * config/tc-arm.c (add_to_lit_pool): Ensure that the padding added to the pool uses O_constant. * testsuite/gas/arm/pr20068.s: New test. * testsuite/gas/arm/pr20068.d: Test driver.
2016-05-11 13:51:04 +02:00
2016-05-11 Nick Clifton <nickc@redhat.com>
PR target/20068
* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
to the pool uses O_constant.
* testsuite/gas/arm/pr20068.s: New test.
* testsuite/gas/arm/pr20068.d: Test driver.
Skip new ARM security extension tests on non-ELF based targets. * testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-05-11 10:04:17 +02:00
2016-05-11 Nick Clifton <nickc@redhat.com>
oops - fix up changelog entry
2016-05-11 10:06:58 +02:00
* testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
Skip new ARM security extension tests on non-ELF based targets. * testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-05-11 10:04:17 +02:00
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
* testsuite/gas/i386/i386.exp: Run RDPID tests.
* testsuite/gas/i386/prefix.d: Adjust.
* testsuite/gas/i386/rdpid.s: New test.
* testsuite/gas/i386/rdpid.d: Ditto.
* testsuite/gas/i386/rdpid-intel.d: Ditto.
* testsuite/gas/i386/x86-64-rdpid.s: Ditto.
* testsuite/gas/i386/x86-64-rdpid.d: Ditto.
* testsuite/gas/i386/x86-64-rdpid-intel.d: Ditto.
Enable Intel RDPID instruction. This patch enables Intel RDPID instruction described in Intel64 and IA-32 Architectures Software Developer's Manual, April 2016. gas/ * config/tc-i386.c (cpu_arch): Add RDPID. * doc/c-i386.texi: Document RDPID. gas/testsuite/ * gas/i386/i386.exp: Run RDPID tests. * gas/i386/prefix.d: Adjust. * gas/i386/rdpid.s: New test. * gas/i386/rdpid.d: Ditto. * gas/i386/rdpid-intel.d: Ditto. * gas/i386/x86-64-rdpid.s: Ditto. * gas/i386/x86-64-rdpid.d: Ditto. * gas/i386/x86-64-rdpid-intel.d: Ditto. opcodes/ * i386-dis.c (prefix_table): Add RDPID instruction. * i386-gen.c (cpu_flag_init): Add RDPID flag. (cpu_flags): Add RDPID bitfield. * i386-opc.h (enum): Add RDPID element. (i386_cpu_flags): Add RDPID field. * i386-opc.tbl: Add RDPID instruction. * i386-init.h: Regenerate. * i386-tbl.h: Regenerate.
2016-05-10 20:35:52 +02:00
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
* config/tc-i386.c (cpu_arch): Add RDPID.
* doc/c-i386.texi: Document RDPID.
Use getters/setters to access ARM branch type 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (elf32_arm_size_stubs): Use new macros ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get and set branch type of a symbol. (bfd_elf32_arm_process_before_allocation): Likewise. (elf32_arm_relocate_section): Likewise and fix identation along the way. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_symbol): Likewise. (elf32_arm_swap_symbol_in): Likewise. (elf32_arm_swap_symbol_out): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to set branch type of a symbol. gdb/ * arm-tdep.c (arm_elf_make_msymbol_special): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. include/ * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE enumerator. (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro. (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise. (ARM_SYM_BRANCH_TYPE): Replace by ... (ARM_GET_SYM_BRANCH_TYPE): This and ... (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether BFD_ASSERT is defined or not. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. opcodes/ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. (print_insn): Likewise.
2016-05-10 17:14:23 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
set branch type of a symbol.
Add support for ARMv8-M Mainline with DSP extension 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (elf32_arm_merge_eabi_attributes): Add merging logic for Tag_DSP_extension. binutils/ * readelf.c (display_arm_attribute): Add output for Tag_DSP_extension. (arm_attr_public_tags): Define DSP_extension attribute. gas/ * NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions. * config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP instructions. (arm_extensions): Add dsp extension for ARMv8-M Mainline. (aeabi_set_public_attributes): Memorize the feature bits of the architecture selected for Tag_CPU_arch. Use it to set Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension. (arm_convert_symbolic_attribute): Define Tag_DSP_extension. * testsuite/gas/arm/arch7em-bad.d: Rename to ... * testsuite/gas/arm/arch7em-bad-1.d: This. * testsuite/gas/arm/arch7em-bad-2.d: New file. * testsuite/gas/arm/arch7em-bad-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise. include/ * elf/arm.h (Tag_DSP_extension): Define. ld/ * testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New test. * testsuite/ld-arm/attr-merge-10b-dsp.s: New file. * testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10 16:15:15 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions.
* config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP
instructions.
(arm_extensions): Add dsp extension for ARMv8-M Mainline.
(aeabi_set_public_attributes): Memorize the feature bits of the
architecture selected for Tag_CPU_arch. Use it to set
Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension.
(arm_convert_symbolic_attribute): Define Tag_DSP_extension.
* testsuite/gas/arm/arch7em-bad.d: Rename to ...
* testsuite/gas/arm/arch7em-bad-1.d: This.
* testsuite/gas/arm/arch7em-bad-2.d: New file.
* testsuite/gas/arm/arch7em-bad-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise.
* testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise.
Allow extension availability to depend on several architecture bits 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_option_extension_value_table): Make allowed_archs an array with 2 entries. (ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs. (ARM_EXT_OPT2): New macro filling the two entries of allowed_archs. (arm_extensions): Use separate entries in allowed_archs when several archs are allowed to use an extension and change ARCH_ANY in ARM_ARCH_NONE in allowed_archs. (arm_parse_extension): Check that, for each allowed_archs entry, all bits are set in the current architecture, ignoring ARM_ANY entries. (s_arm_arch_extension): Likewise. include/ * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10 16:06:41 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (struct arm_option_extension_value_table): Make
allowed_archs an array with 2 entries.
(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
(arm_extensions): Use separate entries in allowed_archs when several
archs are allowed to use an extension and change ARCH_ANY in
ARM_ARCH_NONE in allowed_archs.
(arm_parse_extension): Check that, for each allowed_archs entry, all
bits are set in the current architecture, ignoring ARM_ANY entries.
(s_arm_arch_extension): Likewise.
Add support for ARMv8-M security extensions instructions 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
2016-05-10 16:01:53 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
shared with a non M profile architecture.
(do_rn): New function.
(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
than arm_ext_v8m.
(v7m_psrs): Add ARMv8-M security extensions new special registers.
(insns): Add ARMv8-M Security Extensions instructions.
(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
arm_ext_v8m_m to decide the profile and the Thumb ISA.
* testsuite/gas/arm/archv8m-cmse.s: New file.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/any-cmse.d: Likewise.
* testsuite/gas/arm/any-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
opcodes,gas: sparc: fix mnemonic of faligndatai opcodes/ChangeLog: 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. gas/ChangeLog: 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai. * testsuite/gas/sparc/sparc5vis4.d: Likewise.
2016-05-09 13:09:53 +02:00
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
[ARM][gas] Fix warnings about uninitialised uses and unused const variables * config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED. (fpu_arch_vfp_v3): Likewise. (fpu_arch_neon_v1): Likewise. (arm_arch_full): Likewise. (parse_neon_el_struct_list): Initialize fields of firsttype.
2016-05-06 14:36:07 +02:00
2016-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED.
(fpu_arch_vfp_v3): Likewise.
(fpu_arch_neon_v1): Likewise.
(arm_arch_full): Likewise.
(parse_neon_el_struct_list): Initialize fields of firsttype.
[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructions gas/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP. (arc_extinsn): Handle new introduced syntax. * testsuite/gas/arc/textinsn1op.d: New file. * testsuite/gas/arc/textinsn1op.s: Likewise. * doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP. opcodes/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. (arcExtMap_genOpcode): Likewise. * arc-opc.c (arg_32bit_rc): Define new variable. (arg_32bit_u6): Likewise. (arg_32bit_limm): Likewise. include/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_SYNTAX_1OP): Declare (ARC_SYNTAX_NOP): Likewsie. (ARC_OP1_MUST_BE_IMM): Update defined value. (ARC_OP1_IMM_IMPLIED): Likewise. (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-05-03 13:44:13 +02:00
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
(arc_extinsn): Handle new introduced syntax.
* testsuite/gas/arc/textinsn1op.d: New file.
* testsuite/gas/arc/textinsn1op.s: Likewise.
* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.
Assume that the GAS testsuite for the AVR is being run without -mlink-relax specified. * testsuite/gas/lns/lns.exp: Add avr to list of targets using DW_LNS_fixed_advance_pc.
2016-05-03 11:56:30 +02:00
2016-05-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* testsuite/gas/lns/lns.exp: Add avr to list of targets using
DW_LNS_fixed_advance_pc.
Provide xmemdup0 and some tidies in as.h * as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define. (xmemdup0): New inline function.
2016-04-27 08:12:50 +02:00
2016-04-27 Alan Modra <amodra@gmail.com>
* as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define.
(xmemdup0): New inline function.
MIPS/GAS: Fix an ISA override not lifting ABI restrictions Correct a regression introduced with commit 919731affbef ("Add MIPS .module directive") causing code like: .set mips3 dli $2, 0x9000000080000000 to fail assembly with the following error message produced: Error: number (0x9000000080000000) larger than 32 bits if built with `mips3' selected as the global ISA (e.g. `-march=mips3'). This is because a `.set' directive doing an ISA override does not lift the ABI restriction on register sizes if the ISA remains unchanged. Previously the directive always set register sizes from the ISA chosen, which is what some code expects. Restore the old semantics then. gas/ * config/tc-mips.c (code_option_type): New enum. (parse_code_option): Return status indicating option type. (s_mipsset): Update `parse_code_option' call site accordingly. Always set register sizes from the ISA with ISA overrides. (s_module): Update `parse_code_option' call site. * testsuite/gas/mips/isa-override-1.d: New test. * testsuite/gas/mips/micromips@isa-override-1.d: New test. * testsuite/gas/mips/mips1@isa-override-1.d: New test. * testsuite/gas/mips/mips2@isa-override-1.d: New test. * testsuite/gas/mips/mips32@isa-override-1.d: New test. * testsuite/gas/mips/mips32r2@isa-override-1.d: New test. * testsuite/gas/mips/mips32r3@isa-override-1.d: New test. * testsuite/gas/mips/mips32r5@isa-override-1.d: New test. * testsuite/gas/mips/mips32r6@isa-override-1.d: New test. * testsuite/gas/mips/mips64r2@isa-override-1.d: New test. * testsuite/gas/mips/mips64r3@isa-override-1.d: New test. * testsuite/gas/mips/mips64r5@isa-override-1.d: New test. * testsuite/gas/mips/mips64r6@isa-override-1.d: New test. * testsuite/gas/mips/r3000@isa-override-1.d: New test. * testsuite/gas/mips/r3900@isa-override-1.d: New test. * testsuite/gas/mips/r5900@isa-override-1.d: New test. * testsuite/gas/mips/octeon@isa-override-1.d: New test. * testsuite/gas/mips/octeon3@isa-override-1.d: New test. * testsuite/gas/mips/isa-override-2.l: New list test. * testsuite/gas/mips/mips1@isa-override-2.l: New list test. * testsuite/gas/mips/mips2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r3@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r5@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r6@isa-override-2.l: New list test. * testsuite/gas/mips/r3000@isa-override-2.l: New list test. * testsuite/gas/mips/r3900@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-1.l: New stderr output. * testsuite/gas/mips/isa-override-1.s: New test source. * testsuite/gas/mips/r5900@isa-override-1.s: New test source. * testsuite/gas/mips/isa-override-2.s: New test source. * testsuite/gas/mips/mips1@isa-override-2.s: New test source. * testsuite/gas/mips/mips2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: New test source. * testsuite/gas/mips/r3000@isa-override-2.s: New test source. * testsuite/gas/mips/r3900@isa-override-2.s: New test source. * testsuite/gas/mips/octeon3@isa-override-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-22 02:04:52 +02:00
2016-04-22 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (code_option_type): New enum.
(parse_code_option): Return status indicating option type.
(s_mipsset): Update `parse_code_option' call site accordingly.
Always set register sizes from the ISA with ISA overrides.
(s_module): Update `parse_code_option' call site.
* testsuite/gas/mips/isa-override-1.d: New test.
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
* testsuite/gas/mips/isa-override-2.l: New list test.
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/isa-override-1.s: New test source.
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
* testsuite/gas/mips/isa-override-2.s: New test source.
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
update many old style function definitions This includes regenerating a bunch of files in opcodes/ with trunk cgen. gprof/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * basic_blocks.c: Update old style function definitions. * cg_arcs.c: Likewise. * cg_print.c: Likewise. * gen-c-prog.awk: Likewise. * gmon_io.c: Likewise. * hertz.c: Likewise. * hist.c: Likewise. * sym_ids.c: Likewise. bfd/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cache.c: Update old style function definitions. * elf32-m68k.c: Likewise. * elf64-mmix.c: Likewise. * stab-syms.c: Likewise. opcodes/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * alpha-dis.c: Regenerate. * crx-dis.c: Likewise. * disassemble.c: Likewise. * epiphany-opc.c: Likewise. * fr30-opc.c: Likewise. * frv-opc.c: Likewise. * ip2k-opc.c: Likewise. * iq2000-opc.c: Likewise. * lm32-opc.c: Likewise. * lm32-opinst.c: Likewise. * m32c-opc.c: Likewise. * m32r-opc.c: Likewise. * m32r-opinst.c: Likewise. * mep-opc.c: Likewise. * mt-opc.c: Likewise. * or1k-opc.c: Likewise. * or1k-opinst.c: Likewise. * tic80-opc.c: Likewise. * xc16x-opc.c: Likewise. * xstormy16-opc.c: Likewise. ld/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * emultempl/scoreelf.em: Likewise. binutils/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * resres.c: Likewise. gas/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cgen.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-rl78.c: Likewise.
2016-04-14 00:30:46 +02:00
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cgen.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-rl78.c: Likewise.
gas/doc/arc: Add nps400 references into the documentation Add nps400 to the list of acceptable values for the -mcpu command line switch, and to the .cpu directive. I've added an extra cross reference from -mcpu to .cpu to improve navigation of the documentation. gas/ChangeLog: * doc/c-arc.texi (ARC Options): Add nps400 to list of valus for -mcpu. Add cross reference to .cpu directive from -mcpu option. (ARC Directives): Add NPS400 to .cpu directive list.
2016-04-19 20:02:27 +02:00
2016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
-mcpu. Add cross reference to .cpu directive from -mcpu option.
(ARC Directives): Add NPS400 to .cpu directive list.
[AArch64] Support RAS extension for ARMv8 onwards. The RAS extension was introduced as part of the ARMv8.2 architecture where it is a required feature. It is also available as an optional feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is currently enabled by default for -march=armv8.2-a but is not available for -march=armv8 or -march=armv8.1-a. This patch adds the feature extension '+ras' to enable the RAS extension for ARMv8 and ARMv8.1, it is disabled by default. gas/ 2016-04-20 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "ras". * doc/c-aarch64.texi (AArch64 Extensions): Add "ras". * testsuite/gas/aarch64/armv8-ras-1.d: New. * testsuite/gas/aarch64/armv8-ras-1.s: New. * testsuite/gas/aarch64/illegal-ras-1.d: New. * testsuite/gas/aarch64/illegal-ras-1.s: New. Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-20 10:31:49 +02:00
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
opcodes/arc: Add yet more nps instructions Add some more arc/nps400 instructions and the associated operands. There's also a test added into the assembler. gas/ChangeLog: * testsuite/gas/arc/nps400-6.d: New file. * testsuite/gas/arc/nps400-6.s: New file. include/ChangeLog: * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8. opcodes/ChangeLog: * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp instructions. * arc-opc.c (insert_nps_bitop_size): Delete. (extract_nps_bitop_size): Delete. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. (extract_nps_qcmp_m3): Define. (extract_nps_qcmp_m2): Define. (extract_nps_qcmp_m1): Define. (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and NPS_QCMP_M3.
2016-04-01 20:51:50 +02:00
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-6.d: New file.
* testsuite/gas/arc/nps400-6.s: New file.
opcodes/arc: Add more nps instructions Add dctcp, dcip, dcet, and dcacl instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-4.d: New file. * testsuite/gas/arc/nps400-4.s: New file. * testsuite/gas/arc/nps400-5.d: New file. * testsuite/gas/arc/nps400-5.s: New file. include/ChangeLog: * opcode/arc.h (insn_class_t): Add NET and ACL class. opcodes/ChangeLog: * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-03-31 20:51:14 +02:00
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-4.d: New file.
* testsuite/gas/arc/nps400-4.s: New file.
* testsuite/gas/arc/nps400-5.d: New file.
* testsuite/gas/arc/nps400-5.s: New file.
.cfi_remember_state/.cfi_restore_state documentation * doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve documentation.
2016-04-19 01:46:09 +02:00
2016-04-19 Martin Galvan <martin.galvan@tallertechnologies.com>
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve
documentation.
Revert "gas/arc: Make .cpu directive case-insensitive" This reverts commit 9a452709fe126ea6da23a53426362e4435d2dc06. This change was committed as obvious, but it has been rightly been pointed out to me that this change is not obvious, and as such I am reverting it. gas/ChangeLog: Revert prevous change. * config/tc-arc.c (arc_option): Make .cpu directive case-sensitive again.
2016-04-18 00:17:44 +02:00
2016-04-17 Andrew Burgess <andrew.burgess@embecosm.com>
Revert prevous change.
* config/tc-arc.c (arc_option): Make .cpu directive
case-sensitive again.
gas/arc: Make .cpu directive case-insensitive gas/ChangeLog: * config/tc-arc.c (arc_option): Make .cpu directive case-insensitive.
2016-04-16 17:21:32 +02:00
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_option): Make .cpu directive
case-insensitive.
gas/arc: Support NPS400 in .cpu directive gas/ChangeLog: * config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
2016-04-16 17:19:40 +02:00
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
remove pointless assignment Presumably this was supposed to be regname[sizeof (regname) - 1] but was typoed to regname[sizeof (rename) - 1]. However that should be unnecessary because sprintf should null terminate. As is this assignment is invalid ISO C because rename refers to the function rename (), and sizeof on functions is undefined. In GNU C C the size of functions is 1 so the expression is the same as regname[0]. The following call to sprintf () clearly will over right that, so the statement either has no effect or is invalid. Given that it seems safe to just remove it. While we are there correct the size of regname, and switch from snprintf to sprintf since we know the exact length of the result. gas/ChangeLog: 2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-mips.c (md_begin): Remove useless assignment.
2016-04-13 11:03:22 +02:00
2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mips.c (md_begin): Remove useless assignment.
Regenerate Makefile.in/aclocal.m4 automake 1.11.6 bfd/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. binutils/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gas/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gold/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * testsuite/Makefile.in: Likewise. gprof/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. ld/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. opcodes/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise.
2016-04-16 01:20:02 +02:00
2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.in: Regenerated with automake 1.11.6.
* aclocal.m4: Likewise.
* doc/Makefile.in: Likewise.
Fix non-ELF powerpc build breakage * config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
2016-04-15 16:07:30 +02:00
2016-04-15 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
make a few variables static They are only used in one file, so we might as well restrict there scope to that file, and theoretically this might slightly improve compilers ability to optimize usage of these variables. gas/ChangeLog: 2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nios2.c (nios2_as_options): Make file static. * config/tc-ppc.c (toc_reloc_ypes): Likewise. * config/tc-sparc.c (native_op_table): Likewise.
2016-04-13 10:15:10 +02:00
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nios2.c (nios2_as_options): Make file static.
* config/tc-ppc.c (toc_reloc_ypes): Likewise.
* config/tc-sparc.c (native_op_table): Likewise.
remove some unused globals gas/ChangeLog: 2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-m32c.c (M32C_Macros): Remove. * config/tc-msp430.c (option_numbers): Likewise.
2016-04-12 16:02:58 +02:00
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32c.c (M32C_Macros): Remove.
* config/tc-msp430.c (option_numbers): Likewise.
arc/nps400 : New cmem instructions and associated relocation Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-30 01:02:19 +02:00
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
gas/arc: Unify tests run on big/little endian arc assembler We were running a slightly different set of assembler tests on big and little endian arc targets. This commit unifies the set of tests run. gas/ChangeLog: * testsuite/gas/arc/add_s-err.s: Update target pattern. * testsuite/gas/arc/warn.s: Likewise. * testsuite/gas/elf/elf.exp: Run test for arc.
2016-04-07 23:56:44 +02:00
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/add_s-err.s: Update target pattern.
* testsuite/gas/arc/warn.s: Likewise.
* testsuite/gas/elf/elf.exp: Run test for arc.
Fix copying Solaris binaries with objcopy. PR target/19938 bfd * elf-bbfd.h (struct elf_backend_data): New field: elf_strtab_flags. New field: elf_backend_set_special_section_info_and_link * elfxx-target.h (elf_backend_strtab_flags): Define if not already defined. (elf_backend_set_special_section_info_and_link): Define if not already defined. (elfNN_bed): Use elf_backend_set_special_section_info_and_link and elf_backend_strtab_flags macros to initialise fields in structure. * elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS being set even if SHF_MERGE is not set. (elf_fake_sections): Likewise. (section_match): New function. Matches two ELF sections based upon fixed characteristics. (find_link): New function. Locates a section in a BFD that matches a section in a different BFD. (_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link fields of reserved sections. (bfd_elf_compute_section_file_positions): Set the flags for the .shstrtab section based upon the elf_strtab_flags field in the elf_backend_data structure. (swap_out_syms): Likewise for the .strtab section. * elflink.c (bfd_elf_final_link): Set the flags for the .strtab section based upon the elf_strtab_flags field in the elf_backend_data structure. * elf32-i386.c (elf32_i386_set_special_info_link): New function. (elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris targets. (elf_backend_set_special_section_info_and_link): Define for Solaris targets. * elf32-sparc.c: Likewise. * elf64-x86-64.c: Likewise. binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/readelf.s: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-14 13:04:09 +02:00
2016-04-14 Nick Clifton <nickc@redhat.com>
PR target/19938
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
sections possibly having the SHF_STRINGS flag bit set.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
[ARC] Fix setting private elf flags when parsing .cpu. gas/ 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (mach_type_specified_p): Change type to bfd_boolean. (arc_option): Set private flags when parsing cpu pseudo-op. (md_parse_option): Set mach_type_specified_p to TRUE.
2016-04-12 14:51:57 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (mach_type_specified_p): Change type to
bfd_boolean.
(arc_option): Set private flags when parsing cpu pseudo-op.
(md_parse_option): Set mach_type_specified_p to TRUE.
oops - omitted from previous delta.
2016-04-13 16:10:48 +02:00
2016-04-13 Nick Clifton <nickc@redhat.com>
PR target/19937
* testsuite/gas/v850/pr19937.s: New test.
* testsuite/gas/v850/pr19937.d: New test control file.
* testsuite/gas/v850/basic.exp: Run the new test.
MIPS/GAS: Correct branch relaxation for weak symbols Weak symbols can be preempted at link time so always choose the longer sequence in branch relaxation, according to the relaxation level chosen, so that any symbol finally used as the branch target is reachable. 2016-04-13 Maciej W. Rozycki <macro@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the target is a weak symbol. (relaxed_micromips_32bit_branch_length): Likewise. (relaxed_micromips_16bit_branch_length): Likewise. * testsuite/gas/mips/branch-weak-1.d: New test. * testsuite/gas/mips/branch-weak-2.d: New test. * testsuite/gas/mips/branch-weak-3.d: New test. * testsuite/gas/mips/branch-weak-4.d: New test. * testsuite/gas/mips/branch-weak-5.d: New test. * testsuite/gas/mips/branch-weak.l: New stderr output. * testsuite/gas/mips/branch-weak.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 12:59:36 +02:00
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the target is a weak symbol.
(relaxed_micromips_32bit_branch_length): Likewise.
(relaxed_micromips_16bit_branch_length): Likewise.
* testsuite/gas/mips/branch-weak-1.d: New test.
* testsuite/gas/mips/branch-weak-2.d: New test.
* testsuite/gas/mips/branch-weak-3.d: New test.
* testsuite/gas/mips/branch-weak-4.d: New test.
* testsuite/gas/mips/branch-weak-5.d: New test.
* testsuite/gas/mips/branch-weak.l: New stderr output.
* testsuite/gas/mips/branch-weak.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Relax branches to symbols resolved at link time Where branch relaxation is enabled emit the long sequence for branches whose distance cannot be determined, i.e. to symbols that are undefined or in a different segment. These symbols are only resolved at link time and therefore the longer sequence ensures the branch target is in range, which cannot be guaranteed with a direct branch. This is the opposite to the current implementation, originally proposed here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The proposal was then extensively discussed before the final version was posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html> and eventually committed: commit 4a6a3df43dbb37853a7b88b10ae97d9ec5daf987 Author: Alexandre Oliva <aoliva@redhat.com> Date: Sat Oct 12 05:23:33 2002 +0000 The case considered here was not commented in the review however and the original version remains. With branch relaxation enabled it makes more sense to do it consistently, so that all code impure with respect to branch distances can be linked. Direct branches are still produced for the cases concerned where branch relaxation is disabled, which is the default. gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the distance cannot be determined. (relaxed_micromips_32bit_branch_length): Likewise. * testsuite/gas/mips/branch-extern-1.d: New test. * testsuite/gas/mips/branch-extern-2.d: New test. * testsuite/gas/mips/branch-extern-3.d: New test. * testsuite/gas/mips/branch-extern-4.d: New test. * testsuite/gas/mips/branch-extern.l: New stderr output. * testsuite/gas/mips/branch-extern.s: New test source. * testsuite/gas/mips/branch-section-1.d: New test. * testsuite/gas/mips/branch-section-2.d: New test. * testsuite/gas/mips/branch-section-3.d: New test. * testsuite/gas/mips/branch-section-4.d: New test. * testsuite/gas/mips/branch-section.l: New stderr output. * testsuite/gas/mips/branch-section.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 01:20:35 +02:00
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the distance cannot be determined.
(relaxed_micromips_32bit_branch_length): Likewise.
* testsuite/gas/mips/branch-extern-1.d: New test.
* testsuite/gas/mips/branch-extern-2.d: New test.
* testsuite/gas/mips/branch-extern-3.d: New test.
* testsuite/gas/mips/branch-extern-4.d: New test.
* testsuite/gas/mips/branch-extern.l: New stderr output.
* testsuite/gas/mips/branch-extern.s: New test source.
* testsuite/gas/mips/branch-section-1.d: New test.
* testsuite/gas/mips/branch-section-2.d: New test.
* testsuite/gas/mips/branch-section-3.d: New test.
* testsuite/gas/mips/branch-section-4.d: New test.
* testsuite/gas/mips/branch-section.l: New stderr output.
* testsuite/gas/mips/branch-section.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add support for .extCondCode, .extCoreRegister and .extAuxRegister. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-06 16:08:04 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (arc_flags): Delete code, add flgp.
Update ARC instruction data-base. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/noargs_a7.d: New file. * testsuite/gas/arc/noargs_a7.s: Likewise. * testsuite/gas/arc/noargs_hs.d: Likewise. * testsuite/gas/arc/noargs_hs.s: Likewise. opcode/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h: Add rtsc, sleep with no arguments. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-06 16:47:56 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/noargs_a7.d: New file.
* testsuite/gas/arc/noargs_a7.s: Likewise.
* testsuite/gas/arc/noargs_hs.d: Likewise.
* testsuite/gas/arc/noargs_hs.s: Likewise.
Add support for .extInstruction pseudo-op. gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
Remove unneeded AUX register symbols. gas/ 2016-03-31 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (preprocess_operands): Mark AUX symbol. (arc_adjust_symtab): New function. * config/tc-arc.h (ARC_FLAG_AUX): Define. (obj_adjust_symtab): Likewise. * testsuite/gas/arc/taux.d: New file. * testsuite/gas/arc/taux.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-03-31 12:40:13 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
(arc_adjust_symtab): New function.
* config/tc-arc.h (ARC_FLAG_AUX): Define.
(obj_adjust_symtab): Likewise.
* testsuite/gas/arc/taux.d: New file.
* testsuite/gas/arc/taux.s: Likewise.
MIPS/GAS: Sanitize `.option picX' pseudo-op gas/ * config/tc-mips.c (s_option): Sanitize `.option picX' pseudo-op. * testsuite/gas/mips/option-pic-1.d: New test. * testsuite/gas/mips/option-pic-2.l: New list test. * testsuite/gas/mips/option-pic-1.s: New test source. * testsuite/gas/mips/option-pic-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 22:35:50 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (s_option): Sanitize `.option picX'
pseudo-op.
* testsuite/gas/mips/option-pic-1.d: New test.
* testsuite/gas/mips/option-pic-2.l: New list test.
* testsuite/gas/mips/option-pic-1.s: New test source.
* testsuite/gas/mips/option-pic-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Disallow `.option picX' with VxWorks PIC gas/ * config/tc-mips.c (s_option): Reject `.option picX' if VxWorks PIC. * testsuite/gas/mips/option-pic-vxworks-1.l: New list test. * testsuite/gas/mips/option-pic-vxworks-2.l: New list test. * testsuite/gas/mips/option-pic-vxworks-1.s: New test source. * testsuite/gas/mips/option-pic-vxworks-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 22:23:40 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
PIC.
* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Correct call formatting in `can_swap_branch_p' gas/ * config/tc-mips.c (can_swap_branch_p): Correct call formatting.
2016-04-09 14:27:30 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (can_swap_branch_p): Correct call formatting.
GAS: Fix a typo in `as_bad' description gas/ * messages.c (as_bad): Fix a typo in description.
2016-04-09 14:22:54 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* messages.c (as_bad): Fix a typo in description.
MIPS/GAS: Unify messages in `mips_check_options' gas/ * config/tc-mips.c (mips_check_options): Unify messages.
2016-04-09 14:19:00 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_check_options): Unify messages.
MIPS/GAS: Use `opts->isa' consistently in `mips_check_options' gas/ * config/tc-mips.c (mips_check_options): Use `opts->isa' consistently.
2016-04-09 13:55:09 +02:00
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_check_options): Use `opts->isa'
consistently.
Fix regexps in PR19910 test to cope with COFF and AOUT sparc targets. PR target/19910 * testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with COFF and AOUT sparc targets.
2016-04-08 11:36:49 +02:00
2016-04-08 Nick Clifton <nickc@redhat.com>
PR target/19910
* testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with
COFF and AOUT sparc targets.
arc/nps400: Add new instructions Add some new control instructions to the opcodes library, and a new test for these new instructions to the assembler. The new instructions use an instruction flag longer than any seen before (on arc), and so the max flag length is extended to accommodate this. gas/ChangeLog: * config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7. * testsuite/gas/arc/nps400-2.d: New file. * testsuite/gas/arc/nps400-2.s: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. * arc-opc.c (arc_flag_operands): Add new flags. (arc_flag_classes): Add new classes.
2016-03-29 00:05:09 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7.
* testsuite/gas/arc/nps400-2.d: New file.
* testsuite/gas/arc/nps400-2.s: New file.
gas/arc: Handle multiple arc_opcode chains for same mnemonic This commit completes support for having multiple instructions with the same mnemonic in non-contiguous blocks within the arc_opcodes table. The commit adds an iterator mechanism for the arc_opcode_hash_entry structure, which is then used in find_opcode_match to consider all arc_opcode entries with the same mnemonic, even when these instructions are stored in non-contiguous blocks. I extend the comment on the arc_opcodes table to discuss how entries within the table are organised, and to mention how instructions can be split into multiple groups if needed, but that the table is still searched in table order. There should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New structure. (arc_opcode_hash_entry_iterator_init): New function. (arc_opcode_hash_entry_iterator_next): New function. (find_opcode_match): Iterate over all arc_opcode entries referenced by the arc_opcode_hash_entry passed in as a parameter. opcodes/ChangeLog: * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
2016-03-28 18:08:29 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
structure.
(arc_opcode_hash_entry_iterator_init): New function.
(arc_opcode_hash_entry_iterator_next): New function.
(find_opcode_match): Iterate over all arc_opcode entries
referenced by the arc_opcode_hash_entry passed in as a parameter.
gas/arc: Additional work to support multiple arc_opcode chains Building on earlier commits, this commit moves along support for having multiple arc_opcode entries in the arc_opcodes table that have the same mnemonic (name) field, but are not stored in a contiguous block in the table. In this commit we support looking up the arc_opcode_hash_entry from the hash table, and passing this along to the find_opcode_match function, which then finds the specific arc_opcode that we're assembling. We still don't actually support the multiple chains of arc_opcode entries in this commit, but the limitation is now isolated to the find_opcode_match function. There is no user visible change after this commit. gas/ChangeLog: * config/tc-arc.c (arc_find_opcode): Now returns arc_opcode_hash_entry pointer. (find_opcode_match): Update argument type, extract arc_opcode from incoming arc_opcode_hash_entry. (find_special_case_pseudo): Update return type. (find_special_case_flag): Update return type. (find_special_case): Update return type. (assemble_tokens): Lookup arc_opcode_hash_entry based on instruction mnemonic, then use find_opcode_match to identify specific arc_opcode.
2016-03-28 17:04:58 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_find_opcode): Now returns
arc_opcode_hash_entry pointer.
(find_opcode_match): Update argument type, extract arc_opcode from
incoming arc_opcode_hash_entry.
(find_special_case_pseudo): Update return type.
(find_special_case_flag): Update return type.
(find_special_case): Update return type.
(assemble_tokens): Lookup arc_opcode_hash_entry based on
instruction mnemonic, then use find_opcode_match to identify
specific arc_opcode.
gas/arc: Modify structure used to hold opcodes The arc assembler builds a hash table to hold references to arc_opcode entries in the arc_opcodes table. This hash assumes that each mnemonic will always appear in a contiguous blocks within the arc_opcodes table; all ADD instruction will be together, all AND instructions will likewise be together and so on. The problem with this is that as different variations of arc are added, then it is often more convenient to split instructions apart, so all the base ADD instructions are together, but, variants of ADD specific to one variation of arc are grouped with other instructions specific to that arc variant. The current data structures don't support splitting the instructions in this way. This commit is a first step towards addressing this limitation. In this commit the hash table that currently holds arc_opcode pointers directly, instead holds a pointer to a new, intermediate, data structure. This new data structure holds the pointer to the arc_opcode. In this way, we can, in the future support having the intermediate structure hold multiple pointers to different arc_opcode groups. There should be no visible functional change after this commit. gas/ChangeLog: * config/tc-arc.c (struct arc_opcode_hash_entry): New structure. (arc_find_opcode): New function. (find_special_case_pseudo): Use arc_find_opcode. (find_special_case_flag): Likewise. (assemble_tokens): Likewise. (md_begin): Build hash using struct arc_opcode_hash_entry.
2016-03-28 15:27:43 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
(arc_find_opcode): New function.
(find_special_case_pseudo): Use arc_find_opcode.
(find_special_case_flag): Likewise.
(assemble_tokens): Likewise.
(md_begin): Build hash using struct arc_opcode_hash_entry.
[ARC] Prepare strings for automatic translation. gas/ 2016-04-07 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_option): Prepare string for automatic translation. (declare_register): Likewise.
2016-04-07 14:01:17 +02:00
2016-04-07 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (arc_option): Prepare string for automatic
translation.
(declare_register): Likewise.
[ARC] Prepare strings for automatic translation. gas/ 2016-04-07 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_option): Prepare string for automatic translation. (declare_register): Likewise.
2016-04-07 14:01:17 +02:00
Update AArch64 documentation regarding architecture extensions. * doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE. Correct entry for RDMA. Alpha sort entries.
2016-04-07 14:29:50 +02:00
2016-04-06 James Greenhalgh <james.greenhalgh@arm.com>
* doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE.
Correct entry for RDMA. Alpha sort entries.
gas/arc: Allow greater range of characters into flag names An upcoming commit will add a new arc instruction flag that uses characters that have never appeared in an arc instruction flag before. Currently the assembler is very conservative about which characters can or cannot appear in an instruction flag. This commit relaxes these constraints a little. After this commit all alpha-numeric characters are now allowed into instruction flags. This complete set is not required for the upcoming change, however, having this slightly larger set does not impact the assemblers ability to correctly parse input, but does make it easier to add new flag to the instruction table. gas/ChangeLog: * config/tc-arc.c (tokenize_flags): Allow greater range of characters into flag names.
2016-03-28 23:51:12 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (tokenize_flags): Allow greater range of
characters into flag names.
gas/arc: Remove preprocess_operands function The preprocess_operands function changes the incoming list of assembler tokens based on the assumption that the first arc_operand found will be the same instruction class as all of the arc_operands for the same mnemonic. Though this assumption is probably fine, removing this assumption, and pushing the token change down into assemble_tokens makes the code no more complex, and might even be easier to follow. There should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Handle O_symbol case, add new de_fault label. (preprocess_operands): Delete. (assemble_tokens): Remove call to preprocess_operands.
2016-03-28 16:49:25 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
new de_fault label.
(preprocess_operands): Delete.
(assemble_tokens): Remove call to preprocess_operands.
Allow integer contants to have a U suffix. Improve error reporting for missing closing parentheses. PR gas/19910 * config/tc-sparc.c (sparc_ip): Report an error if the expression inside a %-macro could not be fully parsed. * expr.c (integer_constant): Accept and ignore U suffixes to integers. (operand): When a missing closing parenthesis is encountered, report the character that was found instead. * testsuite/gas/mips/tls-ill.l: Update expected error message. * testsuite/gas/sparc/pr19910-1.d: New test driver. * testsuite/gas/sparc/pr19910-1.s: New test. * testsuite/gas/sparc/pr19910-2.l: Expected error output. * testsuite/gas/sparc/pr19910-2.s: New test. * testsuite/gas/sparc/sparc.exp: Run the new tests.
2016-04-07 13:34:06 +02:00
2016-04-07 Nick Clifton <nickc@redhat.com>
PR gas/19910
* config/tc-sparc.c (sparc_ip): Report an error if the expression
inside a %-macro could not be fully parsed.
* expr.c (integer_constant): Accept and ignore U suffixes to
integers.
(operand): When a missing closing parenthesis is encountered,
report the character that was found instead.
* testsuite/gas/mips/tls-ill.l: Update expected error message.
* testsuite/gas/sparc/pr19910-1.d: New test driver.
* testsuite/gas/sparc/pr19910-1.s: New test.
* testsuite/gas/sparc/pr19910-2.l: Expected error output.
* testsuite/gas/sparc/pr19910-2.s: New test.
* testsuite/gas/sparc/sparc.exp: Run the new tests.
Fix MSP430 assembler's detection of NOP and EINT. * config/tc-msp430.c (msp430_operands): Check for a NOP preceding an EINT instruction. Warn/fix as necessary. * testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP. * testsuite/gas/msp430/bad.l: Update expected messages.
2016-04-06 16:57:19 +02:00
2016-04-06 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding
an EINT instruction. Warn/fix as necessary.
* testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP.
* testsuite/gas/msp430/bad.l: Update expected messages.
arc/nps400: Add additional instructions Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions for the nps400 arc machine type. gas/ChangeLog: * testsuite/gas/arc/nps400-1.d: Update expected results. * testsuite/gas/arc/nps400-1.s: Additional test cases. opcodes/ChangeLog: * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions. * arc-opc.c (arc_flag_operands): Add F_NPS_R. (arc_flag_classes): Add C_NPS_R. (insert_nps_bitop_size_2b): New function. (extract_nps_bitop_size_2b): Likewise. (insert_nps_bitop_uimm8): Likewise. (extract_nps_bitop_uimm8): Likewise. (arc_operands): Add new operand entries.
2016-03-21 19:49:34 +01:00
2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-1.d: Update expected results.
* testsuite/gas/arc/nps400-1.s: Additional test cases.
[ARC] Fix support for double assist instructions. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Add a new subclass field. Add double assist accumulator register values. * arc-tbl.h: Use DPA subclass to mark the double assist instructions. Use DPX/SPX subclas to mark the FPX instructions. * arc-opc.c (RSP): Define instead of SP. (arc_aux_regs): Add the subclass field. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (DPA, DPX, SPX): New subclass enums. (ARC_FPUDA): Define. (arc_aux_reg): Add new field. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (is_code_density_p): Compare directly the subclass field. (is_spfp_p, is_dpfp_p, is_spfp_p): Define. (check_cpu_feature): New function. (find_opcode_match): Use check_cpu_feature function. (preprocess_operands): Likewise. (md_parse_option): Use mfpuda, mdpfp, mspfp options. * testsuite/gas/arc/tdpfp.d: New file. * testsuite/gas/arc/tfpuda.d: Likewise. * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 17:37:29 +02:00
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (is_code_density_p): Compare directly the
subclass field.
(is_spfp_p, is_dpfp_p, is_spfp_p): Define.
(check_cpu_feature): New function.
(find_opcode_match): Use check_cpu_feature function.
(preprocess_operands): Likewise.
(md_parse_option): Use mfpuda, mdpfp, mspfp options.
* testsuite/gas/arc/tdpfp.d: New file.
* testsuite/gas/arc/tfpuda.d: Likewise.
* testsuite/gas/arc/tfpx.s: Likewise.
[ARC] Fix support for double assist instructions. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Add a new subclass field. Add double assist accumulator register values. * arc-tbl.h: Use DPA subclass to mark the double assist instructions. Use DPX/SPX subclas to mark the FPX instructions. * arc-opc.c (RSP): Define instead of SP. (arc_aux_regs): Add the subclass field. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (DPA, DPX, SPX): New subclass enums. (ARC_FPUDA): Define. (arc_aux_reg): Add new field. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (is_code_density_p): Compare directly the subclass field. (is_spfp_p, is_dpfp_p, is_spfp_p): Define. (check_cpu_feature): New function. (find_opcode_match): Use check_cpu_feature function. (preprocess_operands): Likewise. (md_parse_option): Use mfpuda, mdpfp, mspfp options. * testsuite/gas/arc/tdpfp.d: New file. * testsuite/gas/arc/tfpuda.d: Likewise. * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 17:37:29 +02:00
[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar) gas/ * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16. * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests. * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results. * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results. * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source. * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase. * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb. * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results. opcodes/ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-04-05 16:54:00 +02:00
2016-04-05 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New tests.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results.
* testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results.
* testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source.
* testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase.
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise
for Thumb.
[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar) gas/ * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16. * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests. * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results. * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results. * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source. * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase. * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb. * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results. opcodes/ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-04-05 16:54:00 +02:00
* testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results.
[ARC] Don't allow pc-rel relocations for J* instructions. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for JUMP instructions type. * testsuite/gas/arc/relocs-errors.d: New file. * testsuite/gas/arc/relocs-errors.err: Likewise. * testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-05 16:22:19 +02:00
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for
[ARC] Don't allow pc-rel relocations for J* instructions. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for JUMP instructions type. * testsuite/gas/arc/relocs-errors.d: New file. * testsuite/gas/arc/relocs-errors.err: Likewise. * testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-05 16:22:19 +02:00
JUMP instructions type.
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/relocs-errors.d: New file.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* testsuite/gas/arc/relocs-errors.s: Likewise.
[ARC] Don't allow pc-rel relocations for J* instructions. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for JUMP instructions type. * testsuite/gas/arc/relocs-errors.d: New file. * testsuite/gas/arc/relocs-errors.err: Likewise. * testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-05 16:22:19 +02:00
Add missing ChangeLog entry for PR gas/19909 fix
2016-04-15 14:59:16 +02:00
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19909
* config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding
only if i.disp_encoding != disp_encoding_32bit.
* gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32.
* gas/testsuite/gas/i386/x86-64-disp32.s: Likewise.
* gas/testsuite/gas/i386/disp32.d: Updated.
* gas/testsuite/gas/i386/x86-64-disp32.d: Likewise.
Add a testcase for PR gas/19498 PR gas/19498 * testsuite/gas/i386/i386.exp: Run pr19498. * testsuite/gas/i386/pr19498.d: New file. * testsuite/gas/i386/pr19498.s: Likewise.
2016-04-05 05:45:30 +02:00
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19498
* testsuite/gas/i386/i386.exp: Run pr19498.
* testsuite/gas/i386/pr19498.d: New file.
* testsuite/gas/i386/pr19498.s: Likewise.
gas/arc: Use #define from include/opcode/arc.h In tc-arc.h we redefine constants that are also defined in the include/opcode/arc.h header file. The problem is that changing one without changing the other resulting in strange crashes. We could comment both locations to stress the importance of remembering to update the other location too, or we could just include the opcode/arc.h header file into the assembler. Given that other targets include their opcode/ARCH.h header file, and only having a single definition, where possible, is usually the safest solution, that's what I switch too with this commit. gas/ChangeLog: * config/tc-arc.h: Include 'opcode/arc.h'. (MAX_INSN_ARGS): Delete. (MAX_INSN_FLGS): Delete.
2016-04-01 19:35:29 +02:00
2016-04-04 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h: Include 'opcode/arc.h'.
(MAX_INSN_ARGS): Delete.
(MAX_INSN_FLGS): Delete.
PR19498, Invalid "symbol definition loop" PR 19498 * symbols.c (resolve_symbol_value): Clear sy_resolving on exit from function on all paths that set sy_resolving.
2016-04-04 08:49:27 +02:00
2016-04-04 Alan Modra <amodra@gmail.com>
PR 19498
* symbols.c (resolve_symbol_value): Clear sy_resolving on exit
from function on all paths that set sy_resolving.
use XNEW and related macros more gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * app.c (app_push): use XNEW macro. * as.c: Likewise. * config/obj-elf.c (obj_elf_change_section): Likewise. (elf_copy_symbol_attributes): Likewise. (obj_elf_size): Likewise. (build_group_lists): Likewise. * config/tc-aarch64.c (add_operand_error_record): Likewise. (md_assemble): Likewise. (tc_gen_reloc): Likewise. (get_upper_str): Likewise. (aarch64_parse_features): Likewise. * config/tc-arm.c (insert_reg_alias): Likewise. (insert_neon_reg_alias): Likewise. (find_or_make_literal_pool): Likewise. (s_arm_elf_cons): Likewise. (add_unwind_opcode): Likewise. (arm_parse_extension): Likewise. * config/tc-avr.c (create_record_for_frag): Likewise. * config/tc-crx.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c (s_proc): Likewise. * config/tc-ft32.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c (pa_proc): Likewise. (create_new_space): Likewise. (create_new_subspace): Likewise. * config/tc-i860.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-iq2000.c (iq2000_add_macro): Likewise. (iq2000_record_hi16): Likewise. * config/tc-m32c.c (m32c_indirect_operand): Likewise. * config/tc-m32r.c (debug_sym): Likewise. (m32r_record_hi16): Likewise. * config/tc-m68k.c (m68k_ip): Likewise. (md_begin): Likewise. * config/tc-mcore.c: Likewise. * config/tc-microblaze.c (check_got): Likewise. * config/tc-mips.c (append_insn): Likewise. (s_mipsset): Likewise. (mips_record_label): Likewise. (s_mips_end): Likewise. * config/tc-mmix.c (mmix_frob_file): Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-moxie.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise. * config/tc-ns32k.c: Likewise. * config/tc-or1k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-pj.c (fake_opcode): Likewise. * config/tc-ppc.c (ppc_apuinfo_section_add): Likewise. (ppc_macro): Likewise. (ppc_dwsect): Likewise. (ppc_machine): Likewise. * config/tc-rl78.c (rl78_frag_init): Likewise. * config/tc-rx.c (rx_frag_init): Likewise. * config/tc-s390.c (s390_lit_suffix): Likewise. (s390_machine): Likewise. (s390_machinemode): Likewise. * config/tc-score.c (s3_insert_reg): Likewise. (s3_gen_reloc): Likewise. * config/tc-score7.c (s7_insert_reg): Likewise. (s7_gen_reloc): Likewise. * config/tc-tic30.c (tic30_operand): Likewise. * config/tc-tic4x.c (tic4x_inst_make): Likewise. * config/tc-tic54x.c (stag_add_field): Likewise. (tic54x_struct): Likewise. (tic54x_space): Likewise. (tic54x_field): Likewise. (tic54x_mlib): Likewise. (subsym_substitute): Likewise. * config/tc-tic6x.c (tic6x_frob_label): Likewise. * config/tc-vax.c: Likewise. * config/tc-xc16x.c: Likewise. * config/tc-xtensa.c (xtensa_add_insn_label): Likewise. (directive_push): Likewise. (xtensa_begin_directive): Likewise. (tokenize_arguments): Likewise. (xtensa_add_literal_sym): Likewise. (new_resource_table): Likewise. (resize_resource_table): Likewise. (emit_single_op): Likewise. (xtensa_create_trampoline_frag): Likewise. (xtensa_maybe_create_literal_pool_frag): Likewise. (xtensa_add_config_info): Likewise. (xtensa_realloc_fixup_cache): Likewise. (add_subseg_info): Likewise. (cache_literal_section): Likewise. (add_xt_block_frags): Likewise. (add_xt_prop_frags): Likewise. (init_op_placement_info_table): Likewise. (build_section_rename): Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * depend.c (register_dependency): Likewise. * dwarf2dbg.c (get_line_subseg): Likewise. (dwarf2_gen_line_info_1): Likewise. (get_filenum): Likewise. * ecoff.c (allocate_scope): Likewise. (allocate_vlinks): Likewise. (allocate_shash): Likewise. (allocate_thash): Likewise. (allocate_tag): Likewise. (allocate_forward): Likewise. (allocate_thead): Likewise. (allocate_lineno_list): Likewise. * expr.c (make_expr_symbol): Likewise. * hash.c (hash_new_sized): Likewise. * input-file.c (input_file_push): Likewise. * listing.c (file_info): Likewise. (listing_newline): Likewise. * macro.c (new_formal): Likewise. (define_macro): Likewise. * remap.c (add_debug_prefix_map): Likewise. * symbols.c (symbol_find_noref): Likewise. (define_dollar_label): Likewise. (fb_label_instance_inc): Likewise. (symbol_relc_make_value): Likewise.
2016-04-01 15:26:30 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* app.c (app_push): use XNEW macro.
* as.c: Likewise.
* config/obj-elf.c (obj_elf_change_section): Likewise.
(elf_copy_symbol_attributes): Likewise.
(obj_elf_size): Likewise.
(build_group_lists): Likewise.
* config/tc-aarch64.c (add_operand_error_record): Likewise.
(md_assemble): Likewise.
(tc_gen_reloc): Likewise.
(get_upper_str): Likewise.
(aarch64_parse_features): Likewise.
* config/tc-arm.c (insert_reg_alias): Likewise.
(insert_neon_reg_alias): Likewise.
(find_or_make_literal_pool): Likewise.
(s_arm_elf_cons): Likewise.
(add_unwind_opcode): Likewise.
(arm_parse_extension): Likewise.
* config/tc-avr.c (create_record_for_frag): Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c (s_proc): Likewise.
* config/tc-ft32.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c (pa_proc): Likewise.
(create_new_space): Likewise.
(create_new_subspace): Likewise.
* config/tc-i860.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-iq2000.c (iq2000_add_macro): Likewise.
(iq2000_record_hi16): Likewise.
* config/tc-m32c.c (m32c_indirect_operand): Likewise.
* config/tc-m32r.c (debug_sym): Likewise.
(m32r_record_hi16): Likewise.
* config/tc-m68k.c (m68k_ip): Likewise.
(md_begin): Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-microblaze.c (check_got): Likewise.
* config/tc-mips.c (append_insn): Likewise.
(s_mipsset): Likewise.
(mips_record_label): Likewise.
(s_mips_end): Likewise.
* config/tc-mmix.c (mmix_frob_file): Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-moxie.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-or1k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-pj.c (fake_opcode): Likewise.
* config/tc-ppc.c (ppc_apuinfo_section_add): Likewise.
(ppc_macro): Likewise.
(ppc_dwsect): Likewise.
(ppc_machine): Likewise.
* config/tc-rl78.c (rl78_frag_init): Likewise.
* config/tc-rx.c (rx_frag_init): Likewise.
* config/tc-s390.c (s390_lit_suffix): Likewise.
(s390_machine): Likewise.
(s390_machinemode): Likewise.
* config/tc-score.c (s3_insert_reg): Likewise.
(s3_gen_reloc): Likewise.
* config/tc-score7.c (s7_insert_reg): Likewise.
(s7_gen_reloc): Likewise.
* config/tc-tic30.c (tic30_operand): Likewise.
* config/tc-tic4x.c (tic4x_inst_make): Likewise.
* config/tc-tic54x.c (stag_add_field): Likewise.
(tic54x_struct): Likewise.
(tic54x_space): Likewise.
(tic54x_field): Likewise.
(tic54x_mlib): Likewise.
(subsym_substitute): Likewise.
* config/tc-tic6x.c (tic6x_frob_label): Likewise.
* config/tc-vax.c: Likewise.
* config/tc-xc16x.c: Likewise.
* config/tc-xtensa.c (xtensa_add_insn_label): Likewise.
(directive_push): Likewise.
(xtensa_begin_directive): Likewise.
(tokenize_arguments): Likewise.
(xtensa_add_literal_sym): Likewise.
(new_resource_table): Likewise.
(resize_resource_table): Likewise.
(emit_single_op): Likewise.
(xtensa_create_trampoline_frag): Likewise.
(xtensa_maybe_create_literal_pool_frag): Likewise.
(xtensa_add_config_info): Likewise.
(xtensa_realloc_fixup_cache): Likewise.
(add_subseg_info): Likewise.
(cache_literal_section): Likewise.
(add_xt_block_frags): Likewise.
(add_xt_prop_frags): Likewise.
(init_op_placement_info_table): Likewise.
(build_section_rename): Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* depend.c (register_dependency): Likewise.
* dwarf2dbg.c (get_line_subseg): Likewise.
(dwarf2_gen_line_info_1): Likewise.
(get_filenum): Likewise.
* ecoff.c (allocate_scope): Likewise.
(allocate_vlinks): Likewise.
(allocate_shash): Likewise.
(allocate_thash): Likewise.
(allocate_tag): Likewise.
(allocate_forward): Likewise.
(allocate_thead): Likewise.
(allocate_lineno_list): Likewise.
* expr.c (make_expr_symbol): Likewise.
* hash.c (hash_new_sized): Likewise.
* input-file.c (input_file_push): Likewise.
* listing.c (file_info): Likewise.
(listing_newline): Likewise.
* macro.c (new_formal): Likewise.
(define_macro): Likewise.
* remap.c (add_debug_prefix_map): Likewise.
* symbols.c (symbol_find_noref): Likewise.
(define_dollar_label): Likewise.
(fb_label_instance_inc): Likewise.
(symbol_relc_make_value): Likewise.
use xstrdup and friends more gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/obj-elf.c (obj_elf_vendor_attribute): Use xstrdup. * config/tc-ppc.c (ppc_frob_file_before_adjust): Likewise. (ppc_znop): Likewise. (ppc_pe_section): Likewise. (ppc_frob_symbol): Likewise. * config/tc-tic30.c (tic30_operand): Likewise. * config/tc-tic4x.c (tic4x_sect): Likewise. (tic4x_usect): Likewise.
2016-04-02 15:27:18 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-elf.c (obj_elf_vendor_attribute): Use xstrdup.
* config/tc-ppc.c (ppc_frob_file_before_adjust): Likewise.
(ppc_znop): Likewise.
(ppc_pe_section): Likewise.
(ppc_frob_symbol): Likewise.
* config/tc-tic30.c (tic30_operand): Likewise.
* config/tc-tic4x.c (tic4x_sect): Likewise.
(tic4x_usect): Likewise.
cleanup FLT_CHARS and EXP_CHARS Providing declarations in tc.h points out that alpha wasn't properly marking FLT_CHARS as const. We can also get rid of the confusing redefinition of X_CHARS to mmix_x_chars. Finally we can get rid of some now redundant declarations of these constants. gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-alpha.c: Const qualify FLT_CHARS. * config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS. * config/tc-cris.h: Likewise. * expr.c: Likewise. * config/tc-mmix.c (md_atof): Adjust comment. * config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros. * tc.h: Declare FLT_CHARS and EXP_CHARS.
2016-04-02 22:38:40 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-alpha.c: Const qualify FLT_CHARS.
* config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS.
* config/tc-cris.h: Likewise.
* expr.c: Likewise.
* config/tc-mmix.c (md_atof): Adjust comment.
* config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros.
* tc.h: Declare FLT_CHARS and EXP_CHARS.
update ChangeLog for previous commit
2016-04-04 01:49:05 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-score.c (s3_gen_reloc): Add const qualifiers.
* config/tc-score7.c (s7_gen_reloc): Likewise.
arm: change the type of a variable to bfd_reloc_code_real_type It is only ever assigned values in the enum, and it is passed to functions that expect the argument's type to be the enum. gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-arm.c (do_t_branch): Change the type of reloc to bfd_reloc_code_real_type.
2016-04-01 01:49:05 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (do_t_branch): Change the type of reloc to
bfd_reloc_code_real_type.
bfin: simplify current_inputline Its not used for anything outside of md_assemble () so it doesn't need to be extern. While we are there we can replace free () and xmalloc () with XRESIZEVEC which should be faster. gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/bfin-parse.y (current_inputline): Remove definition. * config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
2016-04-02 14:22:05 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/bfin-parse.y (current_inputline): Remove definition.
* config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
avr: simplify some option parsing with strcasecmp () Instead of canonicalizing the argument we can just use a case insensitive compare. gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-avr.c (md_parse_option): Use strcasecmp () to compare strings.
2016-04-02 13:57:10 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (md_parse_option): Use strcasecmp () to compare
strings.
PR19896, Segmentation fault on bad input PR 19896 * read.c (assign_symbol): Consume rest of line after an error rather than continuing to process the line.
2016-04-02 08:47:26 +02:00
2016-04-02 Alan Modra <amodra@gmail.com>
PR 19896
* read.c (assign_symbol): Consume rest of line after an error
rather than continuing to process the line.
gas/arc: Change 'LENGHT' to 'LENGTH' Small spelling mistake in a #define, fixed in this commit. gas/ChangeLog: * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to... (MAX_FLAG_NAME_LENGTH): ...this. (struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH. * config/tc-arc.c (tokenize_flags): Likewise.
2016-03-28 23:48:34 +02:00
2016-04-01 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to...
(MAX_FLAG_NAME_LENGTH): ...this.
(struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH.
* config/tc-arc.c (tokenize_flags): Likewise.
Constify more * cgen.c (weak_operand_overflow_check): Return const char*. * messages.c (as_internal_value_out_of_range): Formatting. (as_warn_value_out_of_range): Consify prefix param. (as_bad_value_out_of_range): Likewise. * read.c (s_errwarn): Constify msg.. (s_float_space, float_cons): ..and err. * as.h (as_warn_value_out_of_range, as_bad_value_out_of_range, ieee_md_atof, vax_md_atof): Update prototypes. * tc.h (md_atof): Update prototype. * config/atof-ieee.c (ieee_md_atof): Return const char*. * config/atof-vax.c (vax_md_atof): Likewise. * config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg. * config/tc-aarch64.c (md_atof): Return const char*. * config/tc-alpha.c (s_alpha_section_name): Likewise. (s_alpha_comm): Constify sec_name. (section_name): Constify. (s_alpha_section): Consify name.. (alpha_elf_section_letter): ..and ptr_msg param.. (md_atof): ..and return. * config/tc-alpha.h (alpha_elf_section_letter): Update prototype. * config/tc-arc.c (md_atof): Return const char*. * config/tc-arm.c (md_atof): Likewise. * config/tc-avr.c (md_atof): Likewise. * config/tc-bfin.c (md_atof): Likewise. * config/tc-cr16.c (md_atof): Likewise. * config/tc-cris.c (md_atof): Likewise. * config/tc-crx.c (md_atof): Likewise. * config/tc-d10v.c (md_atof): Likewise. * config/tc-d30v.c (md_atof): Likewise. * config/tc-dlx.c (md_atof): Likewise. * config/tc-epiphany.c (md_atof): Likewise. * config/tc-fr30.c (md_atof): Likewise. * config/tc-frv.c (md_atof): Likewise. * config/tc-ft32.c (md_atof): Likewise. * config/tc-h8300.c (md_atof): Likewise. * config/tc-hppa.c (struct default_subspace_dict): Constify name. (struct default_space_dict): Likewise. (create_new_space): Constify name param. (create_new_subspace): Likewise. (is_defined_space, is_defined_subspace): Likewise. (pa_parse_space_stmt): Constify space_name param. (md_atof): Return const char*. (pa_spaces_begin): Constify name. * config/tc-i370.c (md_atof): Return const char*. * config/tc-i386.c (md_atof): Likewise. (x86_64_section_letter): Constify ptr_msg param. * config/tc-i386.h (x86_64_section_letter): Update prototype. * config/tc-i860.c (struct i860_it): Constify error. (md_atof): Return const char*. * config/tc-i960.c (md_atof): Likewise. * config/tc-ia64.c (md_atof): Likewise. (ia64_elf_section_letter): Constify ptr_msg param. * config/tc-ia64.h (ia64_elf_section_letter): Update prototype. * config/tc-ip2k.c (md_atof): Return const char*. * config/tc-iq2000.c (md_atof): Likewise. * config/tc-lm32.c (md_atof): Likewise. * config/tc-m32c.c (md_atof): Likewise. * config/tc-m32r.c (md_atof): Likewise. * config/tc-m68hc11.c (md_atof): Likewise. * config/tc-m68k.c (md_atof): Likewise. * config/tc-mcore.c (md_atof): Likewise. * config/tc-mep.c (md_atof): Likewise. (mep_elf_section_letter): Constify ptr_msg param. * config/tc-mep.h (mep_elf_section_letter): Update prototype. * config/tc-metag.c (md_atof): Return const char*. * config/tc-microblaze.c (md_atof): Likewise. * config/tc-microblaze.h (md_atof): Delete prototype. * config/tc-mips.c (mips_parse_argument_token): Constify err. (md_atof): Return const char*. * config/tc-mmix.c (md_atof): Likewise. * config/tc-mn10200.c (md_atof): Likewise. * config/tc-mn10300.c (md_atof): Likewise. * config/tc-moxie.c (md_atof): Likewise. * config/tc-msp430.c (md_atof): Likewise. * config/tc-mt.c (md_atof): Likewise. * config/tc-nds32.c (md_atof): Likewise. * config/tc-nios2.c (md_atof): Likewise. (nios2_elf_section_letter): Constify ptr_msg param. * config/tc-nios2.h (nios2_elf_section_letter): Update prototype. * config/tc-ns32k.c (md_atof): Return const char*. * config/tc-or1k.c (md_atof): Likewise. * config/tc-pdp11.c (struct pdp11_code): Constify error. (md_atof): Return const char*. * config/tc-pj.c (md_atof): Likewise. * config/tc-ppc.c (md_atof): Likewise. * config/tc-rl78.c (md_atof): Likewise. * config/tc-rx.c (md_atof): Likewise. * config/tc-s390.c (md_atof): Likewise. * config/tc-score.c (s3_atof, md_atof): Likewise. * config/tc-sh.c (md_atof): Likewise. * config/tc-sparc.c (struct sparc_it): Constify error. (md_atof): Return const char*. * config/tc-spu.c (md_atof): Likewise. * config/tc-tic30.c (md_atof): Likewise. * config/tc-tic4x.c (md_atof): Likewise. * config/tc-tic54x.c (md_atof): Likewise. * config/tc-tic6x.c (md_atof): Likewise. * config/tc-tilegx.c (md_atof): Likewise. * config/tc-tilepro.c (md_atof): Likewise. * config/tc-v850.c (parse_register_list, md_atof): Likewise. * config/tc-vax.c (md_atof): Likewise. * config/tc-visium.c (md_atof): Likewise. * config/tc-xc16x.c (md_atof): Likewise. * config/tc-xgate.c (md_atof): Likewise. * config/tc-xstormy16.c (md_atof): Likewise. * config/tc-xtensa.c (md_atof): Likewise. * config/tc-z80.c (md_atof): Likewise. * config/tc-z8k.c (md_atof): Likewise.
2016-04-01 14:07:50 +02:00
2016-04-01 Alan Modra <amodra@gmail.com>
* cgen.c (weak_operand_overflow_check): Return const char*.
* messages.c (as_internal_value_out_of_range): Formatting.
(as_warn_value_out_of_range): Consify prefix param.
(as_bad_value_out_of_range): Likewise.
* read.c (s_errwarn): Constify msg..
(s_float_space, float_cons): ..and err.
* as.h (as_warn_value_out_of_range, as_bad_value_out_of_range,
ieee_md_atof, vax_md_atof): Update prototypes.
* tc.h (md_atof): Update prototype.
* config/atof-ieee.c (ieee_md_atof): Return const char*.
* config/atof-vax.c (vax_md_atof): Likewise.
* config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg.
* config/tc-aarch64.c (md_atof): Return const char*.
* config/tc-alpha.c (s_alpha_section_name): Likewise.
(s_alpha_comm): Constify sec_name.
(section_name): Constify.
(s_alpha_section): Consify name..
(alpha_elf_section_letter): ..and ptr_msg param..
(md_atof): ..and return.
* config/tc-alpha.h (alpha_elf_section_letter): Update prototype.
* config/tc-arc.c (md_atof): Return const char*.
* config/tc-arm.c (md_atof): Likewise.
* config/tc-avr.c (md_atof): Likewise.
* config/tc-bfin.c (md_atof): Likewise.
* config/tc-cr16.c (md_atof): Likewise.
* config/tc-cris.c (md_atof): Likewise.
* config/tc-crx.c (md_atof): Likewise.
* config/tc-d10v.c (md_atof): Likewise.
* config/tc-d30v.c (md_atof): Likewise.
* config/tc-dlx.c (md_atof): Likewise.
* config/tc-epiphany.c (md_atof): Likewise.
* config/tc-fr30.c (md_atof): Likewise.
* config/tc-frv.c (md_atof): Likewise.
* config/tc-ft32.c (md_atof): Likewise.
* config/tc-h8300.c (md_atof): Likewise.
* config/tc-hppa.c (struct default_subspace_dict): Constify name.
(struct default_space_dict): Likewise.
(create_new_space): Constify name param.
(create_new_subspace): Likewise.
(is_defined_space, is_defined_subspace): Likewise.
(pa_parse_space_stmt): Constify space_name param.
(md_atof): Return const char*.
(pa_spaces_begin): Constify name.
* config/tc-i370.c (md_atof): Return const char*.
* config/tc-i386.c (md_atof): Likewise.
(x86_64_section_letter): Constify ptr_msg param.
* config/tc-i386.h (x86_64_section_letter): Update prototype.
* config/tc-i860.c (struct i860_it): Constify error.
(md_atof): Return const char*.
* config/tc-i960.c (md_atof): Likewise.
* config/tc-ia64.c (md_atof): Likewise.
(ia64_elf_section_letter): Constify ptr_msg param.
* config/tc-ia64.h (ia64_elf_section_letter): Update prototype.
* config/tc-ip2k.c (md_atof): Return const char*.
* config/tc-iq2000.c (md_atof): Likewise.
* config/tc-lm32.c (md_atof): Likewise.
* config/tc-m32c.c (md_atof): Likewise.
* config/tc-m32r.c (md_atof): Likewise.
* config/tc-m68hc11.c (md_atof): Likewise.
* config/tc-m68k.c (md_atof): Likewise.
* config/tc-mcore.c (md_atof): Likewise.
* config/tc-mep.c (md_atof): Likewise.
(mep_elf_section_letter): Constify ptr_msg param.
* config/tc-mep.h (mep_elf_section_letter): Update prototype.
* config/tc-metag.c (md_atof): Return const char*.
* config/tc-microblaze.c (md_atof): Likewise.
* config/tc-microblaze.h (md_atof): Delete prototype.
* config/tc-mips.c (mips_parse_argument_token): Constify err.
(md_atof): Return const char*.
* config/tc-mmix.c (md_atof): Likewise.
* config/tc-mn10200.c (md_atof): Likewise.
* config/tc-mn10300.c (md_atof): Likewise.
* config/tc-moxie.c (md_atof): Likewise.
* config/tc-msp430.c (md_atof): Likewise.
* config/tc-mt.c (md_atof): Likewise.
* config/tc-nds32.c (md_atof): Likewise.
* config/tc-nios2.c (md_atof): Likewise.
(nios2_elf_section_letter): Constify ptr_msg param.
* config/tc-nios2.h (nios2_elf_section_letter): Update prototype.
* config/tc-ns32k.c (md_atof): Return const char*.
* config/tc-or1k.c (md_atof): Likewise.
* config/tc-pdp11.c (struct pdp11_code): Constify error.
(md_atof): Return const char*.
* config/tc-pj.c (md_atof): Likewise.
* config/tc-ppc.c (md_atof): Likewise.
* config/tc-rl78.c (md_atof): Likewise.
* config/tc-rx.c (md_atof): Likewise.
* config/tc-s390.c (md_atof): Likewise.
* config/tc-score.c (s3_atof, md_atof): Likewise.
* config/tc-sh.c (md_atof): Likewise.
* config/tc-sparc.c (struct sparc_it): Constify error.
(md_atof): Return const char*.
* config/tc-spu.c (md_atof): Likewise.
* config/tc-tic30.c (md_atof): Likewise.
* config/tc-tic4x.c (md_atof): Likewise.
* config/tc-tic54x.c (md_atof): Likewise.
* config/tc-tic6x.c (md_atof): Likewise.
* config/tc-tilegx.c (md_atof): Likewise.
* config/tc-tilepro.c (md_atof): Likewise.
* config/tc-v850.c (parse_register_list, md_atof): Likewise.
* config/tc-vax.c (md_atof): Likewise.
* config/tc-visium.c (md_atof): Likewise.
* config/tc-xc16x.c (md_atof): Likewise.
* config/tc-xgate.c (md_atof): Likewise.
* config/tc-xstormy16.c (md_atof): Likewise.
* config/tc-xtensa.c (md_atof): Likewise.
* config/tc-z80.c (md_atof): Likewise.
* config/tc-z8k.c (md_atof): Likewise.
make xtensa_section_rename () take const char * Xtensa uses it in several macros passing it a literal string, so its convenient for the argument type to be const char *. However some of the code in symbols.c seems to assume tc_canonicalize_symbol_name () will return a non const pointer, and some other target's implementations even modify the argument, so it seems best to return a char * which means casting away const on the argument when we return it instead of another string. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (struct rename_section_struct): Make old_name const. (xtensa_section_rename): Make argument type const char *. * config/tc-xtensa.h (xtensa_section_rename): Adjust.
2016-03-20 06:37:55 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct rename_section_struct): Make old_name
const.
(xtensa_section_rename): Make argument type const char *.
* config/tc-xtensa.h (xtensa_section_rename): Adjust.
tc-i960.c: add some casts when assigning literals to args[i] parse_ldconst () takes a char ** as a in / out argument, and sometimes points args[0] to a constant string. Then in some cases after parse_ldconst () returns md_assemble () twiddles the contents of arg[0]. So it seems like it would take some work to avoid these casts, and its not really clear that work is worth it. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-i960.c (parse_ldconst): Cast to char * when assigning to args[0].
2016-03-24 12:52:39 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_ldconst): Cast to char * when assigning to
args[0].
cast the arg to md_assemble () to char * For these targets its not clear how md_assemble can usefully be split up so that part can take const char *. There is also a fair number of targets that need md_assemble () to take a char *, so we can't easily make the argument const. So since there isn't many callers it seems easiest to just add a couple of casts. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to char *. (m32c_indirect_operand): Likewise. * config/tc-nds32.c (do_pseudo_b): Likewise. (do_pseudo_bal): Likewise. (do_pseudo_ls_bhw): Likewise.
2016-03-20 06:13:05 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to
char *.
(m32c_indirect_operand): Likewise.
* config/tc-nds32.c (do_pseudo_b): Likewise.
(do_pseudo_bal): Likewise.
(do_pseudo_ls_bhw): Likewise.
cast to char * when assigning to optarg gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * as.c (parse_args): Cast literal to char * when assigning to optarg.
2016-02-22 23:27:30 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (parse_args): Cast literal to char * when assigning to optarg.
work around get_symbol_name () in sparc and ia64 get_symbol_name () returns a char * in a out arg, which means we need to cast to assign a literal to the variable passed to get_symbol_name (). It seems like better APIs than get_symbol_name () could be provided, but that seems like a fair amount of work so just casting seems to be the betterthing to do for now. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ia64.c (md_assemble): Add temporary variable to pass to get_symbol_name (). * config/tc-sparc.c (s_register): Cast a literal to char * in assignment.
2016-02-28 23:21:12 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (md_assemble): Add temporary variable to pass to
get_symbol_name ().
* config/tc-sparc.c (s_register): Cast a literal to char * in
assignment.
cast literal to char * when assigning to input_line_ptr various places either directly or indirectly set input_line_pointer to point at a literal. Currently lots of places modify the string input_line_pointer points at, so making it const isn't easy. Since most if not all of these places assign to input_line_pointer to parse an expression it would probably be best to add ways to generate and deal with expressions that doesn't involve parsing strings, but for now adding some casts seems easiest. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-i960.c (parse_expr): Cast to char * when assigning to input_line_pointer. * config/tc-m32r.c (expand_debug_syms): Likewise. * config/tc-msp430.c (msp430_dstoperand): Likewise. * config/tc-z80.c (md_begin): Likewise. * stabs.c (stabs_generate_asm_func): Likewise.
2016-02-22 22:17:14 +01:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_expr): Cast to char * when assigning to
input_line_pointer.
* config/tc-m32r.c (expand_debug_syms): Likewise.
* config/tc-msp430.c (msp430_dstoperand): Likewise.
* config/tc-z80.c (md_begin): Likewise.
* stabs.c (stabs_generate_asm_func): Likewise.
get rid of K&R style args gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cgen.c: Modernize the way functions declare arguments. * config/tc-bfin.c: Likewise. * config/tc-pdp11.c: Likewise. * literal.c: Likewise. * read.c: Likewise. * stabs.c: Likewise.
2016-03-27 10:30:31 +02:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cgen.c: Modernize the way functions declare arguments.
* config/tc-bfin.c: Likewise.
* config/tc-pdp11.c: Likewise.
* literal.c: Likewise.
* read.c: Likewise.
* stabs.c: Likewise.
make some variables unsigned these places define char arrays containing values greater than 0x80 which doesn't fit in an 8 bit signed char, but does fit in an unsigned one. gas/ChangeLog: 2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-aarch64.c (aarch64_handle_align): Make the type of some variables unsigned char[]. * config/tc-alpha.c (alpha_handle_align): Likewise. * config/tc-arm.c (arm_handle_align): Likewise. * config/tc-z80.c: Likewise.
2016-03-27 13:07:27 +02:00
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c (aarch64_handle_align): Make the type of some
variables unsigned char[].
* config/tc-alpha.c (alpha_handle_align): Likewise.
* config/tc-arm.c (arm_handle_align): Likewise.
* config/tc-z80.c: Likewise.
Fix compile time warning about comparison between signed and unsigned values. PR target/19880 * config/tc-arm.c (do_t_push_pop): Cast bitmask to unsigned before shifting.
2016-03-30 17:18:04 +02:00
2016-03-30 Nick Clifton <nickc@redhat.com>
PR target/19880
* config/tc-arm.c (do_t_push_pop): Cast bitmask to unsigned before
shifting.
[ARC] Allow equ redefintion tests for ARC. gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/all/gas.exp: Don't xfail on ARC. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/all/redef3.d: Allow execution for ARC.
2016-03-30 16:21:25 +02:00
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* testsuite/gas/all/gas.exp: Don't xfail on ARC.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/all/redef3.d: Allow execution for ARC.
[ARC] Allow equ redefintion tests for ARC. gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/all/gas.exp: Don't xfail on ARC. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/all/redef3.d: Allow execution for ARC.
2016-03-30 16:21:25 +02:00
[ARC] Fix warn.exp test error. gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/warn.exp: Fix matching pattern.
2016-03-30 16:09:56 +02:00
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/warn.exp: Fix matching pattern.
[ARC] Fix warn.exp test error. gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/warn.exp: Fix matching pattern.
2016-03-30 16:09:56 +02:00
[ARC] Add support for Quarkse opcodes. gas/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/ext2op.d: New file. * testsuite/gas/arc/ext2op.s: Likewise. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/ext3op.s: Likewise. opcodes/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (invld07): Remove. * arc-ext-tbl.h: New file. * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. * arc-opc.c (arc_opcodes): Add ext-tbl include. include/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass. (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP) (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL) (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU) (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS) (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL) (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC) (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC) (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU) (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS) (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL) (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C) (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL) (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
[ARC] Add support for Quarkse opcodes. gas/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/ext2op.d: New file. * testsuite/gas/arc/ext2op.s: Likewise. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/ext3op.s: Likewise. opcodes/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (invld07): Remove. * arc-ext-tbl.h: New file. * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. * arc-opc.c (arc_opcodes): Add ext-tbl include. include/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass. (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP) (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL) (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU) (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS) (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL) (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC) (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC) (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU) (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS) (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL) (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C) (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL) (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
make md_parse_option () take a const char * This is mostly just adding const in many places, however there are a couple interesting things. We need to add casts in tc-s390.c and tc-cris.c because they have functions that assign to input_line_pointer an argument that sometimes comes from md_parse_option. Presumably this is safe because those targets never pass literals to md_parse_option (), but this code should probably be improved in the future. Also xtensa passes the argument to strtoll which is a rather odd function, it takes a const char * as argument and returns a pointer into that string as a char * through an out argument, but we can work around that by adding more variables. gas/ChangeLog: 2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-aarch64.c (struct aarch64_long_option_table): Ad const qualifier. * config/tc-alpha.c (md_parse_option): Likewise. * config/tc-arc.c (md_parse_option): Likewise. * config/tc-arm.c (struct arm_long_option_table): Likewise. (md_parse_option): Likewise. * config/tc-avr.c (md_parse_option): Likewise. * config/tc-bfin.c (md_parse_option): Likewise. * config/tc-cr16.c (md_parse_option): Likewise. * config/tc-cris.c (s_cris_arch): Likewise. (md_parse_option): Likewise. * config/tc-crx.c (md_parse_option): Likewise. * config/tc-d10v.c (md_parse_option): Likewise. * config/tc-d30v.c (md_parse_option): Likewise. * config/tc-dlx.c (md_parse_option): Likewise. * config/tc-epiphany.c (md_parse_option): Likewise. * config/tc-fr30.c (md_parse_option): Likewise. * config/tc-frv.c (md_parse_option): Likewise. * config/tc-ft32.c (md_parse_option): Likewise. * config/tc-h8300.c (md_parse_option): Likewise. * config/tc-hppa.c (md_parse_option): Likewise. * config/tc-i370.c (md_parse_option): Likewise. * config/tc-i386.c (md_parse_option): Likewise. * config/tc-i860.c (md_parse_option): Likewise. * config/tc-i960.c (md_parse_option): Likewise. * config/tc-ia64.c (md_parse_option): Likewise. * config/tc-ip2k.c (md_parse_option): Likewise. * config/tc-iq2000.c (md_parse_option): Likewise. * config/tc-lm32.c (md_parse_option): Likewise. * config/tc-m32c.c (md_parse_option): Likewise. * config/tc-m32r.c (md_parse_option): Likewise. * config/tc-m68hc11.c (md_parse_option): Likewise. * config/tc-m68k.c (md_parse_option): Likewise. * config/tc-mcore.c (md_parse_option): Likewise. * config/tc-mep.c (md_parse_option): Likewise. * config/tc-metag.c (struct metag_long_option): Likewise. (md_parse_option): Likewise. * config/tc-microblaze.c (md_parse_option): Likewise. * config/tc-microblaze.h (md_parse_option): Remove prototype. * config/tc-mips.c (md_parse_option): Adjust. * config/tc-mmix.c (md_parse_option): Likewise. * config/tc-mn10200.c (md_parse_option): Likewise. * config/tc-mn10300.c (md_parse_option): Likewise. * config/tc-moxie.c (md_parse_option): Likewise. * config/tc-msp430.c (md_parse_option): Likewise. * config/tc-mt.c (md_parse_option): Likewise. * config/tc-nds32.c (md_parse_option): Likewise. * config/tc-nds32.h (nds32_parse_option): Likewise. * config/tc-nios2.c (md_parse_option): Likewise. * config/tc-ns32k.c (md_parse_option): Likewise. * config/tc-or1k.c (md_parse_option): Likewise. * config/tc-pdp11.c (md_parse_option): Likewise. * config/tc-pj.c (md_parse_option): Likewise. * config/tc-ppc.c (md_parse_option): Likewise. * config/tc-rl78.c (md_parse_option): Likewise. * config/tc-rx.c (md_parse_option): Likewise. * config/tc-s390.c (s390_parse_cpu): Likewise. * config/tc-score.c (md_parse_option): Likewise. * config/tc-sh.c (md_parse_option): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. * config/tc-spu.c (md_parse_option): Likewise. * config/tc-tic30.c (md_parse_option): Likewise. * config/tc-tic4x.c (md_parse_option): Likewise. * config/tc-tic54x.c (md_parse_option): Likewise. * config/tc-tic6x.c (md_parse_option): Likewise. * config/tc-tilegx.c (md_parse_option): Likewise. * config/tc-tilepro.c (md_parse_option): Likewise. * config/tc-v850.c (md_parse_option): Likewise. * config/tc-vax.c (md_parse_option): Likewise. * config/tc-visium.c (struct visium_long_option_table): Likewise. * config/tc-xc16x.c (md_parse_option): Likewise. * config/tc-xgate.c (md_parse_option): Likewise. * config/tc-xstormy16.c (md_parse_option): Likewise. * config/tc-xtensa.c (md_parse_option): Likewise. * config/tc-z80.c (md_parse_option): Likewise. * config/tc-z8k.c (md_parse_option): Likewise. * tc.h (md_parse_option): Likewise.
2016-02-27 15:35:32 +01:00
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c (struct aarch64_long_option_table): Ad const
qualifier.
* config/tc-alpha.c (md_parse_option): Likewise.
* config/tc-arc.c (md_parse_option): Likewise.
* config/tc-arm.c (struct arm_long_option_table): Likewise.
(md_parse_option): Likewise.
* config/tc-avr.c (md_parse_option): Likewise.
* config/tc-bfin.c (md_parse_option): Likewise.
* config/tc-cr16.c (md_parse_option): Likewise.
* config/tc-cris.c (s_cris_arch): Likewise.
(md_parse_option): Likewise.
* config/tc-crx.c (md_parse_option): Likewise.
* config/tc-d10v.c (md_parse_option): Likewise.
* config/tc-d30v.c (md_parse_option): Likewise.
* config/tc-dlx.c (md_parse_option): Likewise.
* config/tc-epiphany.c (md_parse_option): Likewise.
* config/tc-fr30.c (md_parse_option): Likewise.
* config/tc-frv.c (md_parse_option): Likewise.
* config/tc-ft32.c (md_parse_option): Likewise.
* config/tc-h8300.c (md_parse_option): Likewise.
* config/tc-hppa.c (md_parse_option): Likewise.
* config/tc-i370.c (md_parse_option): Likewise.
* config/tc-i386.c (md_parse_option): Likewise.
* config/tc-i860.c (md_parse_option): Likewise.
* config/tc-i960.c (md_parse_option): Likewise.
* config/tc-ia64.c (md_parse_option): Likewise.
* config/tc-ip2k.c (md_parse_option): Likewise.
* config/tc-iq2000.c (md_parse_option): Likewise.
* config/tc-lm32.c (md_parse_option): Likewise.
* config/tc-m32c.c (md_parse_option): Likewise.
* config/tc-m32r.c (md_parse_option): Likewise.
* config/tc-m68hc11.c (md_parse_option): Likewise.
* config/tc-m68k.c (md_parse_option): Likewise.
* config/tc-mcore.c (md_parse_option): Likewise.
* config/tc-mep.c (md_parse_option): Likewise.
* config/tc-metag.c (struct metag_long_option): Likewise.
(md_parse_option): Likewise.
* config/tc-microblaze.c (md_parse_option): Likewise.
* config/tc-microblaze.h (md_parse_option): Remove prototype.
* config/tc-mips.c (md_parse_option): Adjust.
* config/tc-mmix.c (md_parse_option): Likewise.
* config/tc-mn10200.c (md_parse_option): Likewise.
* config/tc-mn10300.c (md_parse_option): Likewise.
* config/tc-moxie.c (md_parse_option): Likewise.
* config/tc-msp430.c (md_parse_option): Likewise.
* config/tc-mt.c (md_parse_option): Likewise.
* config/tc-nds32.c (md_parse_option): Likewise.
* config/tc-nds32.h (nds32_parse_option): Likewise.
* config/tc-nios2.c (md_parse_option): Likewise.
* config/tc-ns32k.c (md_parse_option): Likewise.
* config/tc-or1k.c (md_parse_option): Likewise.
* config/tc-pdp11.c (md_parse_option): Likewise.
* config/tc-pj.c (md_parse_option): Likewise.
* config/tc-ppc.c (md_parse_option): Likewise.
* config/tc-rl78.c (md_parse_option): Likewise.
* config/tc-rx.c (md_parse_option): Likewise.
* config/tc-s390.c (s390_parse_cpu): Likewise.
* config/tc-score.c (md_parse_option): Likewise.
* config/tc-sh.c (md_parse_option): Likewise.
* config/tc-sparc.c (md_parse_option): Likewise.
* config/tc-spu.c (md_parse_option): Likewise.
* config/tc-tic30.c (md_parse_option): Likewise.
* config/tc-tic4x.c (md_parse_option): Likewise.
* config/tc-tic54x.c (md_parse_option): Likewise.
* config/tc-tic6x.c (md_parse_option): Likewise.
* config/tc-tilegx.c (md_parse_option): Likewise.
* config/tc-tilepro.c (md_parse_option): Likewise.
* config/tc-v850.c (md_parse_option): Likewise.
* config/tc-vax.c (md_parse_option): Likewise.
* config/tc-visium.c (struct visium_long_option_table): Likewise.
* config/tc-xc16x.c (md_parse_option): Likewise.
* config/tc-xgate.c (md_parse_option): Likewise.
* config/tc-xstormy16.c (md_parse_option): Likewise.
* config/tc-xtensa.c (md_parse_option): Likewise.
* config/tc-z80.c (md_parse_option): Likewise.
* config/tc-z8k.c (md_parse_option): Likewise.
* tc.h (md_parse_option): Likewise.
apply ChangeLog for previous commit
2016-03-29 13:40:22 +02:00
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-bfin.c (gencode): Use XOBNEW obstack_alloc () wrapper.
* config/tc-hppa.c (fix_new_hppa): Likewise.
(pa_vtable_entry): Likewise.
(pa_vtable_inherit): Likewise.
* config/tc-m68k.c (md_begin): Likewise.
add more const qualifiers gas/ChangeLog: 2016-03-28 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/obj-elf.c (obj_elf_section_name): Return const char *. * config/obj-elf.h (obj_elf_section_name): Adjust. * config/tc-aarch64.c (aarch64_parse_features): Likewise. (aarch64_parse_cpu): Likewise. (aarch64_parse_arch): Likewise. * config/tc-arm.c (arm_parse_extension): Likewise. (arm_parse_cpu): Likewise. (arm_parse_arch): Likewise. * config/tc-nds32.c: Likewise. * config/xtensa-relax.c (parse_special_fn): Likewise. * stabs.c (generate_asm_file): Likewise.
2016-03-24 03:39:13 +01:00
2016-03-28 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-elf.c (obj_elf_section_name): Return const char *.
* config/obj-elf.h (obj_elf_section_name): Adjust.
* config/tc-aarch64.c (aarch64_parse_features): Likewise.
(aarch64_parse_cpu): Likewise.
(aarch64_parse_arch): Likewise.
* config/tc-arm.c (arm_parse_extension): Likewise.
(arm_parse_cpu): Likewise.
(arm_parse_arch): Likewise.
* config/tc-nds32.c: Likewise.
* config/xtensa-relax.c (parse_special_fn): Likewise.
* stabs.c (generate_asm_file): Likewise.
split up cr16s md_assemble () gas/ChangeLog: 2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-cr16.c (cr16_assemble): New function. (md_assemble): Call cr16_assemble.
2016-03-20 06:21:48 +01:00
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-cr16.c (cr16_assemble): New function.
(md_assemble): Call cr16_assemble.
rename flag_size_check to flag_allow_nonconst_size and make it a bool This name describes what the variable means slightly better, and the enum with two values that is only used for this one variable is kind of silly. gas/ChangeLog: 2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * as.c (parse_args): Adjust. * as.h (flag_size_check): Rename to flag_allow_nonconst_size. * config/obj-elf.c (elf_frob_symbol): Adjust.
2016-03-25 20:43:13 +01:00
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (parse_args): Adjust.
* as.h (flag_size_check): Rename to flag_allow_nonconst_size.
* config/obj-elf.c (elf_frob_symbol): Adjust.
gas: sparc: allow ASR registers in the 0..31 range in V9 and later In the SPARC V9 (and later) versions of the SPARC specification, the section C.1.1 "Register Names" specifies that: "asr_reg. An asr_reg is an Ancillary State Register name. It may have one of the following values: %asr16-%asr31" The rationale of having this restriction was that the registers from 16 to 31 are reserved to implementations, and are therefore "non-V9". It also assumes that the existing ASR registers in the range 0..31 will have their own names such as %y, that can be used to access such registers. However, this is problematic. When a new ASR register is introduced, such as %mcdper a.k.a. %asr14, it is useful to be able to use %asr14 in order to not depend on the latest version of the assembler. The Solaris assembler is lax and allows to assembly instructions referring to %asr0 to %asr31. This patch makes the GNU assembler to mimic that behavior. gas/ChangeLog: 2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR registers to be in the 16..31 range.
2016-03-24 18:28:41 +01:00
2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR
registers to be in the 16..31 range.
make microblaze build with -Wwrite-strings frag_var () assigns its last argument to frag::fr_opcode, and it turns out some targets modify the string that points to. However it appears niether the generic code or the microblaze code modifies what fr_opcode points to, so this code should be safe. So we unfortunately need to cast to char * when passing an argument to frag_var () but otherwise microblaze can itself point to these strings with const char *. gas/ChangeLog: 2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-microblaze.c (md_assemble): Cast opc to char * when calling frag_var ().
2016-03-20 02:48:07 +01:00
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-microblaze.c (md_assemble): Cast opc to char * when calling
frag_var ().
localize string returned from visium's md_atof () I'm not sure the string it returns is particularly useful, or better than the string returned by other atof implementations on failure, but given the others return a localized string it seems like this one should too. gas/ChangeLog: 2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-visium.c (md_atof): Localize the string returned on failure.
2016-03-19 12:38:46 +01:00
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-visium.c (md_atof): Localize the string returned on
failure.
make more variables const gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-h8300.c (h8300_elf_section): Add const qualifiers. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-m68hc11.c (md_begin): Likewise. (print_opcode_list): Likewise. * config/tc-msp430.c (msp430_section): Likewise. * config/tc-score.c (struct s3_insn_to_dependency): Likewise. (s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (struct s7_insn_to_dependency): Likewise. (s7_build_dependency_insn_hsh): Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (subsym_get_arg): Likewise. * config/tc-xtensa.c (struct suffix_reloc_map): Likewise. (get_directive): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c: Likewise. * symbols.c (symbol_create): Likewise. (local_symbol_make): Likewise. (symbol_relc_make_expr): Likewise. include/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/i960.h: Add const qualifiers. * opcode/tic4x.h (struct tic4x_inst): Likewise.
2016-03-20 06:34:02 +01:00
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-h8300.c (h8300_elf_section): Add const qualifiers.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-m68hc11.c (md_begin): Likewise.
(print_opcode_list): Likewise.
* config/tc-msp430.c (msp430_section): Likewise.
* config/tc-score.c (struct s3_insn_to_dependency): Likewise.
(s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (struct s7_insn_to_dependency): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(subsym_get_arg): Likewise.
* config/tc-xtensa.c (struct suffix_reloc_map): Likewise.
(get_directive): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c: Likewise.
* symbols.c (symbol_create): Likewise.
(local_symbol_make): Likewise.
(symbol_relc_make_expr): Likewise.
tc-pdp11.c: remove useless code if the condition is true then we know that str already points to a'\0' in the string passed to the function. Since we know the latter part of the function doesn't modify that string, and str already points to a null byte there's no point in changing str to point to a literal empty string. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-pdp11.c (md_assemble): Remove useless if and assignment to str.
2016-03-20 06:07:55 +01:00
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-pdp11.c (md_assemble): Remove useless if and assignment to
str.
tc-sparc.c: get rid of wierd usage of strchr () This lets us avoid assigning a literal to a char *, and perhaps more importantly makes it clearer what is going on here. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr () call with a switch.
2016-03-20 06:36:16 +01:00
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr ()
call with a switch.
use do_align () directly in tc-ia64.c gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ia64.c (ia64_do_align): Remove. (ia64_cons_align): Call do_align () directly. (dot_proc): Likewise. (stmt_float_cons): Likewise.
2016-02-29 00:00:00 +01:00
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (ia64_do_align): Remove.
(ia64_cons_align): Call do_align () directly.
(dot_proc): Likewise.
(stmt_float_cons): Likewise.
replace some raw xmalloc / xrealloc with the XNEW* macros This increases consistancy of how we allocate memory, and always casting the result to the proper type. It also helps make sure we get any use of sizeof on the result type correct. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * listing.c (listing_message): Use XNEW style allocation macros. * read.c (read_a_source_file): Likewise. (read_symbol_name): Likewise. (s_mri_common): Likewise. (assign_symbol): Likewise. (s_reloc): Likewise. (emit_expr_with_reloc): Likewise. (s_incbin): Likewise. (s_include): Likewise. * sb.c (sb_build): Likewise. (sb_check): Likewise.
2016-02-14 04:00:07 +01:00
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* listing.c (listing_message): Use XNEW style allocation macros.
* read.c (read_a_source_file): Likewise.
(read_symbol_name): Likewise.
(s_mri_common): Likewise.
(assign_symbol): Likewise.
(s_reloc): Likewise.
(emit_expr_with_reloc): Likewise.
(s_incbin): Likewise.
(s_include): Likewise.
* sb.c (sb_build): Likewise.
(sb_check): Likewise.
Fix tic54x regression One of the tic54x testcases looks for a section alignment of 1. After 9136aa49 the alignment became 0. While it happens that an alignment of 0 is treated as an alignment of 1, there is no reason to not apply the explicit alignment. * write.c (record_alignment): Revert 2016-02-18 change.
2016-03-22 13:18:37 +01:00
2016-03-22 Alan Modra <amodra@gmail.com>
* write.c (record_alignment): Revert 2016-02-18 change.
Remove more alloca calls * config/tc-alpha.c (load_expression): Replace alloca with xmalloc. (emit_jsrjmp, tc_gen_reloc): Likewise. * config/tc-i370.c (i370_macro): Likewise.
2016-03-22 13:08:53 +01:00
2016-03-22 Alan Modra <amodra@gmail.com>
* config/tc-alpha.c (load_expression): Replace alloca with xmalloc.
(emit_jsrjmp, tc_gen_reloc): Likewise.
* config/tc-i370.c (i370_macro): Likewise.
Add -Wstack-usage to the gcc warning flags list, but only if using a sufficiently recent version of gcc. bfd * warning.m4 (GCC_WARN_CFLAGS): Only add -Wstack-usage if using a sufficiently recent version of GCC. * configure: Regenerate. others * configure: Regenerate.
2016-03-22 10:41:16 +01:00
2016-03-22 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
arc/nps400: Add first nps400 instructions Adds the first few nps400 instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-0.d: New file. * testsuite/gas/arc/nps400-0.s: New file. * testsuite/gas/arc/nps400-1.d: New file. * testsuite/gas/arc/nps400-1.s: New file. include/ChangeLog: * opcodes/arc.h (insn_class_t): Add BITOP type. opcodes/ChangeLog: * arc-nps400-tbl.h: New file. * arc-opc.c: Add top level comment. (insert_nps_3bit_dst): New function. (extract_nps_3bit_dst): New function. (insert_nps_3bit_src2): New function. (extract_nps_3bit_src2): New function. (insert_nps_bitop_size): New function. (extract_nps_bitop_size): New function. (arc_flag_operands): Add nps400 entries. (arc_flag_classes): Add nps400 entries. (arc_operands): Add nps400 entries. (arc_opcodes): Add nps400 include.
2016-03-15 23:01:34 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
arc/opcodes: Use flag operand class to handle multiple flag matches When parsing the operand instruction flags we don't currently detect the case where multiple flags are provided from the same class set, these will be accepted and the bit values merged together, resulting in the wrong instruction being assembled. For example: adc.n.eq r0,r0,r2 Will assemble without error, yet, upon disassembly, the instruction will actually be: adc.c r0,r0,r2 In a later commit the concept of required flags will be introduced. Required flags are just like normal instruction flags, except that they must be present for the instruction to match. Adding this will allow for simpler instructions in the instruction table, and allow for more sharing of operand extraction and insertion functions. To solve both of the above issues (multiple flags being invalid, and required flags), this commit reworks the flag class mechanism. Currently the flag class is never used. Each instruction can reference multiple flag classes, each flag class has a class type and a set of flags. However, at present, the class type is never used. The current values identify the type of instruction that the flag will be used in, but this is not required information. Instead, this commit discards the old flag classes, and introduces 3 new classes. The first F_CLASS_NONE, is just a NULL marker value, and is only used in the NULL marker flag class. The other two flag classes are F_FLAG_OPTIONAL, and F_FLAG_REQUIRED. The class F_FLAG_OPTIONAL has the property that at most one of the flags in the flag set for that class must be present in the instruction. The "at most" one means that no flags being present is fine. The class F_FLAG_REQUIRED is not currently used, but will be soon. With this class, exactly one of the flags from this class must be present in the instruction. If the flag class contains a single flag, then of course that flag must be present. However, if the flag class contained two or more, then one, and only one of them must be present. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. Handle flag class. * testsuite/gas/arc/asm-errors.d: New file. * testsuite/gas/arc/asm-errors.err: New file. * testsuite/gas/arc/asm-errors.s: New file. include/ChangeLog: * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. opcodes/ChangeLog: * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values.
2016-03-14 23:17:47 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
arc: Add nps400 machine type, and assembler flag. This commit introduces the nps400 machine type as a variant of arc. There's a new flag in the assembler to select this machine type. All other changes are just adding handling of the new machine type into the relevant places. The nps400 is an arc700 variant with some vendor specific instructions added into the instruction set. This commit does not add any of the new instructions, this is just laying the groundwork for future commits. However, in preparation for these new instructions a new opcode define for nps400 has been added to include/opcode/arc.h, this new opcode define is used in the assembler and disassembler along with the existing define for arc700 such that when assembling and disassembling for nps400 the user will have access to all arc700 instructions and all the nps400 vendor extension instructions. bfd/ChangeLog: * archures.c (bfd_mach_arc_nps400): Define. * bfd-in2.h: Regenerate. * cpu-arc.c (arch_info_struct): New entry for nps400, renumber some existing entries to make space. * elf32-arc.c (arc_elf_object_p): Add nps400 case. (arc_elf_final_write_processing): Likewise. binutils/ChangeLog: * readelf.c (decode_ARC_machine_flags): Handle nps400. gas/ChangeLog: * config/tc-arc.c (cpu_types): Add nps400 entry. (check_zol): Handle nps400. include/ChangeLog: * elf/arc.h (E_ARC_MACH_NPS400): Define. * opcode/arc.h (ARC_OPCODE_NPS400): Define. opcodes/ChangeLog: * arc-dis.c (print_insn_arc): Handle nps400.
2016-03-15 22:51:50 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
arc: Remove EF_ARC_CPU_GENERIC constant. The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h file, and is used in a few places in binutils, however, this constant should never make it into the elf header flags; we always set a valid cpu type in the assembler, which should then be copied over during linking. There are some non-gnu arc compilers that don't write an architecture type into the e_flags field, instead leaving the field as 0, which is the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine type to distinguish between the old and newer arc architectures, setting the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700 architectures, while using EM_ARC_COMPACT2 for newer arcem and archs architectures. Previously when displaying the machine flags for an older EM_ARC_COMPACT machine, if the e_flags had not been filled in, then we relied on the default case statement to display the message "Generic ARCompact", while in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC to print "ARC Generic", leaving the default case to print a message about unrecognised cpu flag. After this commit EF_ARC_CPU_GENERIC has been removed, for both machine types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case statement to handle the situation where the e_flags has not been filled in. The message displayed is now "Unknown ARCompact" (for older arc architectures) and "Unknown ARC" (for the newer architectures). The switch from "Generic" to "Unknown" in the message string is for clarity, calling the file "Generic" can give the impression that the file is compiled for a common sub-set of the architectures, and would therefore run on any type of machine (or at least any type of new or old machine depending on if the machine type is ARC or ARCv2). However, this was not what "Generic" meant, it really meant "Unknown", so that's what we now say. As part of the merging of the readelf flag reading code, I have unified the strings used in displaying the ELF ABI. This means that for older arc machines (arc600, arc601, and arc700) the string used for the original ABI, and ABIv2 have changed, the current ABIv3 remains the same. For the newer architectures (arcem and archs) the abi strings remain unchanged in all cases. bfd/ChangeLog: * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of EF_ARC_CPU_GENERIC. (arc_elf_final_write_processing): Don't bother setting cpu field in e_flags, this will have been set elsewhere. binutils/ChangeLog: * readelf.c (get_machine_flags): Move arc processing into... (decode_ARC_machine_flags): ... new function. Remove use of EF_ARC_CPU_GENERIC, change default case from "generic arc" to "unknown arc". Merged ABI printing between two machine types. gas/ChangeLog: * config/tc-arc.c (arc_select_cpu): Remove use of EF_ARC_CPU_GENERIC. include/ChangeLog: * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-15 22:38:30 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
arc/gas: default mach is arc700, initialised in md_begin This commit restructures the selection of the default cpu/mach so that the choice is made from md_begin (if the user has not provided a command line choice). This will reduce the amount of change needed in a later patch. At the request of Synopsys, the default architecture changes to ARC700 from this commit, previously the default was a non-existent super-architecture that contained all instructions from all arc variants. There's some clean up associated with removing the default merged architecture, and a small test fix now that the default is ARC700. binutils/ChangeLog: * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700 to the architecture list. gas/ChangeLog: * config/tc-arc.c (arc_target): Delay initialisation until arc_select_cpu. (arc_target_name): Likewise. (arc_features): Likewise. (arc_mach_type): Likewise. (cpu_types): Remove "all" entry. (arc_select_cpu): New function, most of the content is from... (md_parse_option): ... here. Call new arc_select_cpu. (md_begin): Call arc_select_cpu if needed, default is now arc700. include/ChangeLog: * opcode/arc.h (ARC_OPCODE_BASE): Delete. opcodes/ChangeLog: * arc-opc.c (BASE): Delete.
2016-03-01 12:41:12 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
gas/arc: Fix test for big-endian arc The inline-data test checks the specific bytes laid down by the assembler, and so relies on the endianness of the target. I could change the expected results to be endian agnostic, however, I worried that a bug in the assembler that gets the endianness wrong would then slip through. Instead I add a new test for big-endian arc, and restrict the existing test to little-endian arc. gas/ChangeLog: * testsuite/gas/arc/inline-data-1.d: Add target restriction. * testsuite/gas/arc/inline-data-2.d: New file.
2016-03-15 23:38:41 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
Remove use of alloca. bfd * warning.m4 (GCC_WARN_CFLAGS): Add -Wstack-usage=262144 * configure: Regenerate. * elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Replace use of alloca with call to xmalloc. * elf32-nds32.c: Likewise. * elf64-hppa.c: Likewise. * elfxx-mips.c: Likewise. * pef.c: Likewise. * pei-x86_64.c: Likewise. * som.c: Likewise. * xsym.c: Likewise. binutils * dlltool.c: Replace use of alloca with call to xmalloc. * dllwrap.c: Likewise. * nlmconv.c: Likewise. * objdump.c: Likewise. * resrc.c: Likewise. * winduni.c: Likewise. * configure: Regenerate. gas * atof-generic.c: Replace use of alloca with call to xmalloc. * cgen.c: Likewise. * dwarf2dbg.c: Likewise. * macro.c: Likewise. * remap.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic30.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/te-vms.c: Likewise. * configure: Regenerate. ld * emultempl/msp430.em: Replace use of alloca with call to xmalloc. * plugin.c: Likewise. * pe-dll.c: Likewise.
2016-03-21 17:31:46 +01:00
2016-03-21 Nick Clifton <nickc@redhat.com>
* atof-generic.c: Replace use of alloca with call to xmalloc.
* cgen.c: Likewise.
* dwarf2dbg.c: Likewise.
* macro.c: Likewise.
* remap.c: Likewise.
* stabs.c: Likewise.
* symbols.c: Likewise.
* config/obj-elf.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic30.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/te-vms.c: Likewise.
* configure: Regenerate.
tc-i386.c: store encoded instructions in unsigned char[] char can be a signed type, and some of the values in these arrays are greater than 0x80 which means they are outside of the range a signed char can store. Fortunately it seems most compilers handle this in the obvious way by storing the same bits as a negative number, but this is wierd and easily fixed. gas/ChangeLog: 2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * tc-i386.c (f32_1): Change type to unsigned char[]. (f32_2): Likewise. (f32_3): Likewise. (f32_4): Likewise. (f32_5): Likewise. (f32_6): Likewise. (f32_7): Likewise. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_3): Likewise. (f16_4): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (f32_patt): Likewise. (f16_patt): Likewise. (alt_3): Likewise. (alt_4): Likewise. (alt_5): Likewise. (alt_6): Likewise. (alt_7): Likewise. (alt_8): Likewise. (alt_9): Likewise. (alt_10): Likewise. (alt_patt): Likewise.
2016-02-14 20:41:38 +01:00
2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* tc-i386.c (f32_1): Change type to unsigned char[].
(f32_2): Likewise.
(f32_3): Likewise.
(f32_4): Likewise.
(f32_5): Likewise.
(f32_6): Likewise.
(f32_7): Likewise.
(f32_8): Likewise.
(f32_9): Likewise.
(f32_10): Likewise.
(f32_11): Likewise.
(f32_12): Likewise.
(f32_13): Likewise.
(f32_14): Likewise.
(f16_3): Likewise.
(f16_4): Likewise.
(f16_5): Likewise.
(f16_6): Likewise.
(f16_7): Likewise.
(f16_8): Likewise.
(jump_31): Likewise.
(f32_patt): Likewise.
(f16_patt): Likewise.
(alt_3): Likewise.
(alt_4): Likewise.
(alt_5): Likewise.
(alt_6): Likewise.
(alt_7): Likewise.
(alt_8): Likewise.
(alt_9): Likewise.
(alt_10): Likewise.
(alt_patt): Likewise.
Fix generation of as.1 manual page so that it can be converted to DocBook format. gas * doc/as.texinfo: Place the target specific command line options into their own man page section. etc * texi2pod.pl: Add TARGET to the list of recognised man page sections.
2016-03-18 14:07:33 +01:00
2016-03-18 Nick Clifton <nickc@redhat.com>
Update description of AArch64 assembler directives. gas * doc/c-aarch64.texi (AArch64 Directives): Add descriptions of .cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall, .tlsdescldr and .xword directives.
2016-03-18 18:30:12 +01:00
* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
.tlsdescldr and .xword directives.
Fix the disassembly of the AArch64's OOR instruction as a MOV instruction. PR target/19721 opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand of MOV insn that aliases an ORR insn. gas * testsuite/gas/aarch64/pr19721.s: New test source file. * testsuite/gas/aarch64/pr19721.d: New test driver file.
2016-03-18 18:02:20 +01:00
PR target/19721
* testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
Fix generation of as.1 manual page so that it can be converted to DocBook format. gas * doc/as.texinfo: Place the target specific command line options into their own man page section. etc * texi2pod.pl: Add TARGET to the list of recognised man page sections.
2016-03-18 14:07:33 +01:00
* doc/as.texinfo: Place the target specific command line options
into their own man page section.
[ARM] Support ARMv8.2 FP16 simd instructions gas/ * config/tc-arm.c (N_S_32): New. (N_F_16_32): Likewise. (N_SUF_32): Support N_F16. (N_IF_32): Likewise. (neon_dyadic_misc): Likewise. (do_neon_cmp): Likewise. (do_neon_cmp_inv): Likewise. (do_neon_mul): Likewise. (do_neon_fcmp_absolute): Likewise. (do_neon_step): Likewise. (do_neon_abs_neg): Likewise. (CVT_FLAVOR_VAR): Likewise. (do_neon_cvt_1): Likewise. (do_neon_recip_est): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (neon_check_type): Check architecture support for FP16 extension. (insns): Update comments. * testsuite/gas/arm/armv8-2-fp16-simd.s: New test source. * testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection error file. opcode/ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-03-16 17:11:59 +01:00
2016-03-16 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (N_S_32): New.
(N_F_16_32): Likewise.
(N_SUF_32): Support N_F16.
(N_IF_32): Likewise.
(neon_dyadic_misc): Likewise.
(do_neon_cmp): Likewise.
(do_neon_cmp_inv): Likewise.
(do_neon_mul): Likewise.
(do_neon_fcmp_absolute): Likewise.
(do_neon_step): Likewise.
(do_neon_abs_neg): Likewise.
(CVT_FLAVOR_VAR): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_recip_est): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(neon_check_type): Check architecture support for FP16 extension.
(insns): Update comments.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
error file.
Fix checking bignum values that are being inserted into byte sized containers. * read.c (emit_expr_with_reloc): Add code check a bignum with nbytes == 1. * config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes other than 32-bits. * testsuite/gas/elf/bignum.s: New test source file. * testsuite/gas/elf/bignum.d: New test driver file. * testsuite/gas/elf/elf.exp: Run the new test.
2016-03-16 12:33:55 +01:00
2016-03-16 Nick Clifton <nickc@redhat.com>
* read.c (emit_expr_with_reloc): Add code check a bignum with
nbytes == 1.
* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
other than 32-bits.
* testsuite/gas/elf/bignum.s: New test source file.
* testsuite/gas/elf/bignum.d: New test driver file.
* testsuite/gas/elf/elf.exp: Run the new test.
Update x86 register name documentation. * doc/c-i386.texi (Register Naming): Update to details of the latest architecture version.
2016-03-15 12:00:28 +01:00
2016-03-15 Ulrich Drepper <drepper@gmail.com>
* doc/c-i386.texi (Register Naming): Update to details of the
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
latest architecture version.
Update x86 register name documentation. * doc/c-i386.texi (Register Naming): Update to details of the latest architecture version.
2016-03-15 12:00:28 +01:00
PR gas/19744: Thumb-1 pcrop relocations don't work on Thumb-2 targets gas/ * config/tc-arm.c (do_arit): Protect against bad relocations usage. (do_mov): Likewise. (do_t_add_sub): Allow pcrop relocations for Thumb-2 targets. (do_t_mov_cmp): Likewise. (do_t_add_sub): Protect against bad relocations usage. (do_t_mov_cmp): Likewise. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local-armv7-m.s: New. * gas/arm/adds-thumb1-reloc-local-armv7-m.d: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.s: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.d: New. ld/ * testsuite/ld-arm/arm-elf.exp: New tests. * testsuite/ld-arm/thumb1-adds-armv7-m.s: New. * testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
2016-03-10 17:05:29 +01:00
2016-03-10 Mickael Guene <mickael.guene@st.com>
PR gas/19744
* config/tc-arm.c (do_arit): Protect against bad relocations usage.
(do_mov): Likewise.
(do_t_add_sub): Allow pcrop relocations for Thumb-2 targets.
(do_t_mov_cmp): Likewise.
(do_t_add_sub): Protect against bad relocations usage.
(do_t_mov_cmp): Likewise.
testsuite/ChangeLog is no longer supposed to exist move entries to main ChangeLog
2016-03-17 00:27:50 +01:00
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.s: New.
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.d: New.
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.s: New.
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.d: New.
PR gas/19744: Thumb-1 pcrop relocations don't work on Thumb-2 targets gas/ * config/tc-arm.c (do_arit): Protect against bad relocations usage. (do_mov): Likewise. (do_t_add_sub): Allow pcrop relocations for Thumb-2 targets. (do_t_mov_cmp): Likewise. (do_t_add_sub): Protect against bad relocations usage. (do_t_mov_cmp): Likewise. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local-armv7-m.s: New. * gas/arm/adds-thumb1-reloc-local-armv7-m.d: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.s: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.d: New. ld/ * testsuite/ld-arm/arm-elf.exp: New tests. * testsuite/ld-arm/thumb1-adds-armv7-m.s: New. * testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
2016-03-10 17:05:29 +01:00
fixup -Wshadow warnings on gcc-4.7 gcc 4.7 complains about variables that shadow function names, which now happens in tc-arm.c because there is a global function do_align (), and local variables do_align. The simplest fix for this seems to be to rename those variables to do_alignment. gas/ChangeLog: 2016-03-09 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-arm.c (neon_alignment_bit): Rename do_align to do_alignment. (do_neon_ld_st_lane): Likewise. (do_neon_ld_dup): Likewise.
2016-03-09 02:02:07 +01:00
2016-03-09 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (neon_alignment_bit): Rename do_align to
do_alignment.
(do_neon_ld_st_lane): Likewise.
(do_neon_ld_dup): Likewise.
[ARC] Allow non-instruction relocations within .text sections bfd/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32. (arc_bfd_put_32): Becomes an alias for bfd_put_32. (arc_elf_howto_init): Added assert to validate relocations. (get_middle_endian_relocation): Delete. (middle_endian_convert): New function. (ME): Redefine, now does nothing. (IS_ME): New define. (arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO' definition to call middle_endian_convert. Add a new local variable and make use of this throughout. Added call to arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations. gas/ 2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com> * testsuite/gas/arc/inline-data-1.d: New file. * testsuite/gas/arc/inline-data-1.s: New file. include/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf/arc-reloc.def: Add a call to ME within the formula for each relocation that requires middle-endian correction.
2016-03-08 14:19:52 +01:00
2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: New file.
* testsuite/gas/arc/inline-data-1.s: New file.
[ARM] Add support for Cortex-R8 2016-03-07 Andre Vieira <andre.simoesdiasvieira@arm.com> gas/ * config/tc-arm.c (arm_cpus): Add cortex-r8. * doc/c-arm.texi: Add cortex-r8.
2016-03-07 18:31:57 +01:00
2016-03-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (arm_cpus): Add cortex-r8.
* doc/c-arm.texi: Add cortex-r8.
Add const qualifiers at various places. opcodes * mcore-opc.h: Add const qualifiers. * microblaze-opc.h (struct op_code_struct): Likewise. * sh-opc.h: Likewise. * tic4x-dis.c (tic4x_print_indirect): Likewise. (tic4x_print_op): Likewise. include * opcode/dlx.h (struct dlx_opcode): Add const qualifiers. * opcode/h8300.h (struct h8_opcode): Likewise. * opcode/hppa.h (struct pa_opcode): Likewise. * opcode/msp430.h: Likewise. * opcode/spu.h (struct spu_opcode): Likewise. * opcode/tic30.h (struct _register): Likewise. * opcode/tic4x.h (struct tic4x_register): Likewise. (struct tic4x_cond): Likewise. (struct tic4x_indirect): Likewise. (struct tic4x_inst): Likewise. * opcode/visium.h (struct reg_entry): Likewise. gas * config/tc-arc.c: Add const qualifiers. * config/tc-h8300.c (md_begin): Likewise. * config/tc-ia64.c (print_prmask): Likewise. * config/tc-msp430.c (msp430_operands): Likewise. * config/tc-nds32.c (struct suffix_name): Likewise. (struct nds32_parse_option_table): Likewise. (struct nds32_set_option_table): Likewise. (do_pseudo_pushpopm): Likewise. (do_pseudo_pushpop_stack): Likewise. (nds32_relax_relocs): Likewise. (nds32_flag): Likewise. (struct nds32_hint_map): Likewise. (nds32_find_reloc_table): Likewise. (nds32_match_hint_insn): Likewise. * config/tc-s390.c: Likewise. * config/tc-sh.c (get_specific): Likewise. * config/tc-tic30.c: Likewise. * config/tc-tic4x.c (tic4x_inst_add): Likewise. (tic4x_indirect_parse): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-z80.c (struct reg_entry): Likewise. * config/tc-epiphany.c (md_assemble): Adjust. (epiphany_assemble): New function. (epiphany_elf_section_rtn): Call do_align directly. (epiphany_elf_section_text): Likewise. * config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise. (ip2k_elf_section_text): Likewise. * read.c (do_align): Make it not static. * read.h (do_align): New prototype.
2016-03-07 16:16:28 +01:00
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arc.c: Add const qualifiers.
* config/tc-h8300.c (md_begin): Likewise.
* config/tc-ia64.c (print_prmask): Likewise.
* config/tc-msp430.c (msp430_operands): Likewise.
* config/tc-nds32.c (struct suffix_name): Likewise.
(struct nds32_parse_option_table): Likewise.
(struct nds32_set_option_table): Likewise.
(do_pseudo_pushpopm): Likewise.
(do_pseudo_pushpop_stack): Likewise.
(nds32_relax_relocs): Likewise.
(nds32_flag): Likewise.
(struct nds32_hint_map): Likewise.
(nds32_find_reloc_table): Likewise.
(nds32_match_hint_insn): Likewise.
* config/tc-s390.c: Likewise.
* config/tc-sh.c (get_specific): Likewise.
* config/tc-tic30.c: Likewise.
* config/tc-tic4x.c (tic4x_inst_add): Likewise.
(tic4x_indirect_parse): Likewise.
* config/tc-vax.c (vax_cons): Likewise.
* config/tc-z80.c (struct reg_entry): Likewise.
* config/tc-epiphany.c (md_assemble): Adjust.
(epiphany_assemble): New function.
(epiphany_elf_section_rtn): Call do_align directly.
(epiphany_elf_section_text): Likewise.
* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
(ip2k_elf_section_text): Likewise.
* read.c (do_align): Make it not static.
* read.h (do_align): New prototype.
[ARM] Build attributes for ARMv8.1-A AdvSIMD binutils/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * readelf.c (arm_attry_tag_FP_arch): Add "NEON for ARMv8.1". gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (aeabi_set_public_attributes): Emit attribute for ARMv8.1 AdvSIMD use. * testsuite/gas/arm/attr-march-armv8-a+rdma.d: New. * testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New. Change-Id: I3c356e0681b97df2f9c0dabd7c0fd1b441cc2755
2016-03-04 15:16:48 +01:00
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Emit attribute
for ARMv8.1 AdvSIMD use.
* testsuite/gas/arm/attr-march-armv8-a+rdma.d: New.
* testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New.
[ARM] Add feature check for ARMv8.1 AdvSIMD instructions. gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA feature. (record_feature_use): New. (mark_feature_used): Use record_feature_use. (do_neon_qrdmlah): New. (insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and variants. (arm_extensions): Put into alphabetical order. Re-indent "simd" and "rdma" entries. Fix the incorrect merge value for "+rdma". * testsuite/gas/arm/armv8-a+rdma-warning.d: New. * testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options. Make source file explicit. * testsuite/gas/arm/armv8-a+rdma.l: New. * testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension directives. Fix white-space. * testsuite/gas/arm/armv8_1-a+simd.d: New. include/opcode 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. (ARM_CPU_HAS_FEATURE): Add comment. Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-04 12:28:28 +01:00
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
feature.
(record_feature_use): New.
(mark_feature_used): Use record_feature_use.
(do_neon_qrdmlah): New.
(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
variants.
(arm_extensions): Put into alphabetical order. Re-indent "simd"
and "rdma" entries. Fix the incorrect merge value for "+rdma".
* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
Make source file explicit.
* testsuite/gas/arm/armv8-a+rdma.l: New.
* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
directives. Fix white-space.
* testsuite/gas/arm/armv8_1-a+simd.d: New.
Adjust testsuite/gas/i386/x86_64-intel.d for COFF * testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
2016-03-02 14:15:32 +01:00
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
[ARC] Local symbols relocation cleanup bfd/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * elf32-arc.c (elf_arc_relocate_section): Added rules to fix the relocation addend when sections get merged. gas/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> * config/tc-arc.c (arc_extra_reloc): Change size to 0. (tc_arc_fix_adjustable): Changed default return value to 1. * testsuite/gas/arc/j.d: Updated expected symbol * testsuite/gas/arc/jl.d: Likewise * testsuite/gas/arc/relax-avoid1.d: Likewise * testsuite/gas/arc/st.d: Likewise ld/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * testsuite/ld-elf/merge.d: Removed xfail for ARC. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise.
2016-02-29 16:51:11 +01:00
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (arc_extra_reloc): Change size to 0.
(tc_arc_fix_adjustable): Changed default return value to 1.
* testsuite/gas/arc/j.d: Updated expected symbol
* testsuite/gas/arc/jl.d: Likewise
* testsuite/gas/arc/relax-avoid1.d: Likewise
* testsuite/gas/arc/st.d: Likewise
[ARC] Local symbols relocation cleanup bfd/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * elf32-arc.c (elf_arc_relocate_section): Added rules to fix the relocation addend when sections get merged. gas/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> * config/tc-arc.c (arc_extra_reloc): Change size to 0. (tc_arc_fix_adjustable): Changed default return value to 1. * testsuite/gas/arc/j.d: Updated expected symbol * testsuite/gas/arc/jl.d: Likewise * testsuite/gas/arc/relax-avoid1.d: Likewise * testsuite/gas/arc/st.d: Likewise ld/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * testsuite/ld-elf/merge.d: Removed xfail for ARC. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise.
2016-02-29 16:51:11 +01:00
[ARC] General fixes. bfd/ 2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com> * elf32-arc.c (arc_elf_final_write_processing): Add condition to the flag change. (elf_arc_relocate_section): Fixes and conditions to support PIE. Assert for code sections dynamic relocs. gas/ 2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> * config/tc-arc.c: Enable code density instructions for ARC EM. ld/ 2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com> * scripttempl/arclinux.sc: Force .tdata and .tbss to always be generated.
2016-02-29 16:07:48 +01:00
2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
* config/tc-arc.c: Enable code density instructions for ARC EM.
Add ChangeLog entries for PR ld/19645
2016-02-26 15:44:03 +01:00
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
for ELF assemblers.
* as.c (flag_use_elf_stt_common): New.
(show_usage): Add --elf-stt-common=.
(option_values): Add OPTION_ELF_STT_COMMON.
(std_longopts): Add --elf-stt-common=.
(parse_args): Handle --elf-stt-common=.
* as.h (flag_use_elf_stt_common): New.
* config.in: Regenerated.
* configure: Likewise.
* configure.ac: Add --enable-elf-stt-common and define
DEFAULT_GENERATE_ELF_STT_COMMON.
* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
* doc/as.texinfo: Document --elf-stt-common=.
* testsuite/gas/elf/common3.s: New file.
* testsuite/gas/elf/common3a.d: Likewise.
* testsuite/gas/elf/common3b.d: Likewise.
* testsuite/gas/elf/common4.s: Likewise.
* testsuite/gas/elf/common4a.d: Likewise.
* testsuite/gas/elf/common4b.d: Likewise.
* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
and common4b.
* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compress-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compressed-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
of dw2-compress-3 and dw2-compressed-3.
Convert more variables to a constant form. * as.c (select_emulation_mode): Add const qualifiers. * as.h: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c (struct aarch64_option_table): Likewise. (struct aarch64_cpu_option_table): Likewise. (struct aarch64_arch_option_table): Likewise. (struct aarch64_option_cpu_value_table): Likewise. (struct aarch64_long_option_table): Likewise. (struct aarch64_option_abi_value_table): Likewise. * config/tc-arm.c (struct reloc_entry): Likewise. (tc_gen_reloc): Likewise. (struct arm_option_table): Likewise. (struct arm_legacy_option_table): Likewise. (struct arm_cpu_option_table): Likewise. (struct arm_arch_option_table): Likewise. (struct arm_option_extension_value_table): Likewise. (struct arm_option_fpu_value_table): Likewise. (struct arm_option_value_table): Likewise. (struct arm_long_option_table): Likewise. * config/tc-avr.c (struct avr_opcodes_s): Likewise. (struct mcu_type_s): Likewise. (struct exp_mod_s): Likewise. (avr_operand): Likewise. (avr_operands): Likewise. * config/tc-d10v.c (md_begin): Likewise. * config/tc-dlx.c: Likewise. * config/tc-fr30.c (fr30_is_colon_insn): Likewise. * config/tc-ft32.c (parse_condition): Likewise. * config/tc-h8300.c (do_a_fix_imm): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (hppa_regname_to_dw2regnum): Likewise. * config/tc-i370.c (i370_elf_suffix): Likewise. * config/tc-i960.c (struct tabentry): Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-m68k.h: Likewise. * config/tc-mcore.c (parse_psrmod): Likewise. * config/tc-metag.c (struct metag_core_option): Likewise. (struct metag_long_option): Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c (macro): Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c (struct rcodes_s): Likewise. (struct hcodes_s): Likewise. (md_parse_option): Likewise. * config/tc-ns32k.c (struct ns32k_option): Likewise. (optlist): Likewise. * config/tc-ppc.c (ppc_elf_suffix): Likewise. (tc_ppc_regname_to_dw2regnum): Likewise. * config/tc-ppc.h: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c (struct cpu_type): Likewise. * config/tc-sh.c (sh_regname_to_dw2regnum): Likewise. * config/tc-sparc.c (struct priv_reg_entry): Likewise. (sparc_ip): Likewise. * config/tc-spu.c (insn_fmt_string): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. * config/tc-v850.c: Likewise. * config/tc-visium.c (struct visium_arch_option_table): Likewise. (struct visium_long_option_table): Likewise. * config/tc-xgate.c: Likewise. * config/tc-z8k.c: Likewise. * read.c (add_include_dir): Likewise. * read.h: Likewise.
2016-02-25 17:55:21 +01:00
2016-02-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (select_emulation_mode): Add const qualifiers.
* as.h: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c (struct aarch64_option_table): Likewise.
(struct aarch64_cpu_option_table): Likewise.
(struct aarch64_arch_option_table): Likewise.
(struct aarch64_option_cpu_value_table): Likewise.
(struct aarch64_long_option_table): Likewise.
(struct aarch64_option_abi_value_table): Likewise.
* config/tc-arm.c (struct reloc_entry): Likewise.
(tc_gen_reloc): Likewise.
(struct arm_option_table): Likewise.
(struct arm_legacy_option_table): Likewise.
(struct arm_cpu_option_table): Likewise.
(struct arm_arch_option_table): Likewise.
(struct arm_option_extension_value_table): Likewise.
(struct arm_option_fpu_value_table): Likewise.
(struct arm_option_value_table): Likewise.
(struct arm_long_option_table): Likewise.
* config/tc-avr.c (struct avr_opcodes_s): Likewise.
(struct mcu_type_s): Likewise.
(struct exp_mod_s): Likewise.
(avr_operand): Likewise.
(avr_operands): Likewise.
* config/tc-d10v.c (md_begin): Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-fr30.c (fr30_is_colon_insn): Likewise.
* config/tc-ft32.c (parse_condition): Likewise.
* config/tc-h8300.c (do_a_fix_imm): Likewise.
* config/tc-hppa.c (pa_ip): Likewise.
(hppa_regname_to_dw2regnum): Likewise.
* config/tc-i370.c (i370_elf_suffix): Likewise.
* config/tc-i960.c (struct tabentry): Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-m68k.h: Likewise.
* config/tc-mcore.c (parse_psrmod): Likewise.
* config/tc-metag.c (struct metag_core_option): Likewise.
(struct metag_long_option): Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c (macro): Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c (struct rcodes_s): Likewise.
(struct hcodes_s): Likewise.
(md_parse_option): Likewise.
* config/tc-ns32k.c (struct ns32k_option): Likewise.
(optlist): Likewise.
* config/tc-ppc.c (ppc_elf_suffix): Likewise.
(tc_ppc_regname_to_dw2regnum): Likewise.
* config/tc-ppc.h: Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c (struct cpu_type): Likewise.
* config/tc-sh.c (sh_regname_to_dw2regnum): Likewise.
* config/tc-sparc.c (struct priv_reg_entry): Likewise.
(sparc_ip): Likewise.
* config/tc-spu.c (insn_fmt_string): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
* config/tc-v850.c: Likewise.
* config/tc-visium.c (struct visium_arch_option_table): Likewise.
(struct visium_long_option_table): Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-z8k.c: Likewise.
* read.c (add_include_dir): Likewise.
* read.h: Likewise.
gas: Update tests for big-endian arc targets Some gas tests are excluded for arc targets using the pattern arc-*-*, however this only covers little endian arc targets. This commit extends the patter to cover big endian arc targets, the pattern is now arc*-*-*. gas/ChangeLog: * testsuite/gas/all/gas.exp: Change target pattern to cover arceb-*. * testsuite/gas/all/redef3.d: Likewise. * testsuite/gas/elf/elf.exp: Likewise.
2016-02-23 01:05:27 +01:00
2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/all/gas.exp: Change target pattern to cover
arceb-*.
* testsuite/gas/all/redef3.d: Likewise.
* testsuite/gas/elf/elf.exp: Likewise.
[GAS][ARM][3/3]Add armv8.2 fp16 scalar instruction support. Based on SE_H instruction shape. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (BAD_FP16): New error message macro. (do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2 fp16 scalar instructions. (neon_check_type): Allow different size from key. (do_vfp_nsyn_add_sub): Add support SE_H shape support. (try_vfp_nsyn): Likewise. (do_vfp_nsyn_mla_mls): Likewise. (do_vfp_nsyn_fma_fms): Likewise. (do_vfp_nsyn_ldm_stm): Likewise (do_vfp_nsyn_sqrt): Likewise (do_vfp_nsyn_div): Likewise (do_vfp_nsyn_nmul): Likewise. (do_vfp_nsyn_cmp): Likewise. (do_neon_shll): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_neon_cvttb_2): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_ldr_str): Likewise. (do_vfp_nsyn_fpv8): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (insns): New entry for vins, vmovx. (md_apply_fix): Left shift 1 bit for fp16 vldr/vstr. * testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.s: New. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
2016-02-24 18:59:35 +01:00
2016-02-24 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (BAD_FP16): New error message macro.
(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
fp16 scalar instructions.
(neon_check_type): Allow different size from key.
(do_vfp_nsyn_add_sub): Add support SE_H shape support.
(try_vfp_nsyn): Likewise.
(do_vfp_nsyn_mla_mls): Likewise.
(do_vfp_nsyn_fma_fms): Likewise.
(do_vfp_nsyn_ldm_stm): Likewise
(do_vfp_nsyn_sqrt): Likewise
(do_vfp_nsyn_div): Likewise
(do_vfp_nsyn_nmul): Likewise.
(do_vfp_nsyn_cmp): Likewise.
(do_neon_shll): Likewise.
(do_vfp_nsyn_cvt_fpv8): Likewise.
(do_neon_cvttb_2): Likewise.
(do_neon_mov): Likewise.
(do_neon_rshift_round_imm): Likewise.
(do_neon_ldr_str): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(insns): New entry for vins, vmovx.
(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
[GAS][ARM][2/3]Add SE_H shape to represent fp16 type. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape. (neon_shape_class): New SC_HALF. (neon_shape_el): New SE_H. (neon_shape_el_size): New size for SE_H. (N_F_ALL): New macro to aggregate N_F16, N_F32, N_64. (neon_select_shape): Add SE_H support code. (el_type_of_type_chk): Use N_F_ALL. (do_vfp_nsyn_cvt): Add SE_H shape support. (do_neon_cvtz): Likewise. (do_neon_cvt_1): Likewise. (do_neon_cvttb_1): Likewise.
2016-02-24 15:18:16 +01:00
2016-02-24 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape.
(neon_shape_class): New SC_HALF.
(neon_shape_el): New SE_H.
(neon_shape_el_size): New size for SE_H.
(N_F_ALL): New macro to aggregate N_F16, N_F32, N_64.
(neon_select_shape): Add SE_H support code.
(el_type_of_type_chk): Use N_F_ALL.
(do_vfp_nsyn_cvt): Add SE_H shape support.
(do_neon_cvtz): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_cvttb_1): Likewise.
[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support. opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. (print_insn_coprocessor): Support fp16 instruction. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.d: Adjust output. * testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24 15:08:39 +01:00
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.d: Adjust output.
* testsuite/gas/arm/copro.s: Adjust co-processor num.
[OPCODES][ARM]Fix mask for a few coprocessor opcodes. opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm, vrint(mpna). gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/mask_1.d: New. * testsuite/gas/arm/mask_1.s: New.
2016-02-24 14:55:30 +01:00
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/mask_1.d: New.
* testsuite/gas/arm/mask_1.s: New.
[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2 opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (print_insn_coprocessor): Check co-processor number for cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11. * testsuite/gas/arm/copro.d: Update.
2016-02-24 14:48:59 +01:00
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
* testsuite/gas/arm/copro.d: Update.
[ARM][gas] Add support for Cortex-A32 2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add entry for cortex-a32. * doc/c-arm.texi (ARM Options): Document cortex-a32.
2016-02-24 11:55:09 +01:00
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add entry for cortex-a32.
* doc/c-arm.texi (ARM Options): Document cortex-a32.
[ARM][doc] Document cortex-a17 mcpu option 2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * doc/c-arm.texi (ARM Options): Document cortex-a17.
2016-02-24 11:53:55 +01:00
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* doc/c-arm.texi (ARM Options): Document cortex-a17.
[ARM][doc] Document cortex-a17 mcpu option 2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * doc/c-arm.texi (ARM Options): Document cortex-a17.
2016-02-24 11:53:55 +01:00
Skip tests for common directive on hpux hpux has a non-standard common directive. * testsuite/gas/elf/elf.exp: Skip tests for common directive on hpux.
2016-02-23 19:40:03 +01:00
2016-02-23 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/elf/elf.exp: Skip tests for common directive on
hpux.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
2016-02-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* output-file.c (output_file_create): Make file name argument const.
(output_file_close): Likewise.
* output-file.h (output_file_create): Adjust.
(output_file_close): Likewise.
* depend.c (quote_string_for_make): Make src argument const char *.
(register_dependency): Likewise.
(wrap_output): Likewise.
* as.h (register_dependency): Adjust.
* config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to
as_where ();
* symbols.c (S_SET_EXTERNAL): Likewise.
* input-scrub.c (as_where): Return the file name.
* as.h (as_where): Adjust prototype.
* app.c (do_scrub_chars): Adjust.
* cond.c (s_elseif): Likewise.
(s_else): Likewise.
(initialize_cframe): Likewise.
* config/obj-coff.c (obj_coff_init_stab_section): Likewise.
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
* config/obj-som.c (obj_som_init_stab_section): Likewise.
* config/tc-aarch64.c (output_info): Likewise.
* config/tc-ia64.c (md_assemble): Likewise.
(dot_alias): Likewise.
* config/tc-m68k.c (m68k_frob_label): Likewise.
* config/tc-mmix.c (s_bspec): Likewise.
(mmix_handle_mmixal): Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(tic54x_adjust_symtab): Likewise.
* config/tc-xtensa.c (directive_push): Likewise.
(xtensa_sanity_check): Likewise.
(xtensa_relax_frag): Likewise.
(md_convert_frag): Likewise.
(tinsn_to_slotbuf): Likewise.
* dwarf2dbg.c (dwarf2_where): Likewise.
* ecoff.c (add_file): Likewise.
(ecoff_generate_asm_lineno): Likewise.
* expr.c (make_expr_symbol): Likewise.
* frags.c (frag_new): Likewise.
(frag_var_init): Likewise.
* listing.c (listing_newline): Likewise.
* messages.c (identify): Likewise.
(as_show_where): Likewise.
(as_warn_internal): Likewise.
(as_bad_internal): Likewise.
* read.c (s_irp): Likewise.
(s_macro): Likewise.
(s_reloc): Likewise.
* stabs.c (stabs_generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_func): Likewise.
* write.c (fix_new_internal): Likewise.
* as.h (PRINTF_WHERE_LIKE): Make file name argument const.
(as_warn_value_out_of_range): Adjust prototype.
(as_bad_value_out_of_range): Adjust prototype.
* messages.c (identify): Make file name argument const char *.
(as_warn_internal): Likewise.
(as_warn_where): Likewise.
(as_bad_internal): Likewise.
(as_bad_where): Likewise.
(as_internal_value_out_of_range): Likewise.
(as_warn_value_out_of_range): Likewise.
(as_bad_value_out_of_range): Likewise.
* as.h (found_comment_file): Change type to const char *.
* cond.c (file_line::file): Likewise.
* config/obj-coff.c (obj_coff_init_stab_section): Make variable const.
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
* config/obj-som.c (obj_som_init_stab_section): Likewise.
* config/tc-aarch64.c (output_info): Likewise.
* config/tc-alpha.c (insert_operand): Likewise.
* config/tc-arc.c (insert_operand): Likewise.
* config/tc-d30v.c (check_size): Likewise.
* config/tc-ia64.c (struct alias): Likewise.
* config/tc-m68k.c (struct label_line): Likewise.
* config/tc-mcore.c (md_apply_fix): Likewise.
* config/tc-microblaze.c (md_estimate_size_before_relax): Likewise.
* config/tc-mips.c (mips16_immed): Likewise.
* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
* config/tc-ppc.c (ppc_insert_operand): Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-s390.c (s390_insert_operand): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(tic54x_adjust_symtab): Likewise.
* config/tc-tilegx.c (insert_operand): Likewise.
(apply_special_operator): Likewise.
* config/tc-tilepro.c (insert_operand): Likewise.
* config/tc-xtensa.c (directive_push): Likewise.
* ecoff.c (add_file): Likewise.
(ecoff_generate_asm_lineno): Likewise.
* listing.c (listing_newline): Likewise.
* read.c (s_irp): Likewise.
* write.c (install_reloc): Likewise.
* write.h (struct fix): Likewise.
* input-file.c (file_name): Change type to const char *.
(saved_file::file_name): Likewise.
(input_file_open): Change type of argument to const char *.
* input-file.h (input_file_open): Adjust.
* input-scrub.c (logical_input_file): change type to const char *.
(physical_input_file): Likewise.
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
(struct input_save): Adjust.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
(input_scrub_push): Adjust.
(input_scrub_begin): Adjust.
(as_where): Adjust.
* input-scrub.c (input_scrub_new_file): Make file name argument const.
(input_scrub_include_file): Likewise.
(new_logical_line_flags): Likewise.
(new_logical_line): Likewise.
* as.h: Adjust.
* frags.h (struct frag): Change type of fr_file to const char *.
* expr.c (expr_symbol_where): Change type of file argument to
const char **.
* expr.h (expr_symbol_where): Likewise.
* config/tc-i370.c (md_apply_fix): adjust.
* config/tc-mmix.c (mmix_md_end): Likewise.
* config/tc-ppc.c (md_apply_fix): Likewise.
* config/tc-s390.c (md_apply_fix): Likewise.
* symbols.c (report_op_error): Likewise.
(resolve_symbol_value): Likewise.
* config/tc-ia64.c (slot::src_file): Change type to const char *.
(rsrc::file): Likewise.
* config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to
const char *.
(xtensa_relax_frag): Likewise.
(md_convert_frag): Likewise.
(tinsn_to_slotbuf): Likewise.
* expr.c (expr_symbol_line): Likewise.
* macro.c (define_macro): Likewise.
* macro.h (macro_struct): Likewise.
* messages.c (as_show_where): Likewise.
* read.c (s_macro): Likewise.
* stabs.c (stabs_generate_asm_file): Likewise.
(generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
* write.h (struct reloc_list): Likewise.
* input-scrub.c (as_where): Change return type to const char *.
* as.h (as_wheree): Adjust.
Set BFD compression bits in write_object_file There is no need to set BFD compression bits for each section. We should just set it once in write_object_file. * write.c (compress_debug): Move BFD compression bits setting to ... (write_object_file): Here.
2016-02-21 15:43:20 +01:00
2016-02-21 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Move BFD compression bits setting
to ...
(write_object_file): Here.
[i386] Check RegVRex in register_number Increment register number by 16 if RegVRex is set. * config/tc-i386.c (register_number): Check RegVRex. * testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd with %zmm19 and %zmm3. * testsuite/gas/i386/x86-64-avx512f-intel.d: Updated. * testsuite/gas/i386/x86-64-avx512f.d: Likewise.
2016-02-20 18:23:20 +01:00
2016-02-20 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (register_number): Check RegVRex.
* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
with %zmm19 and %zmm3.
* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
[ARM] Add FP16 feature extension for ARMv8.2 architecture include/ * opcode/arm.h (ARM_EXT2_FP16_INSN): New. gas/ * config/tc-arm.c (arm_ext_fp16): New. (arm_extensions): New entry for "fp16".
2016-02-19 15:27:23 +01:00
2016-02-19 Matthew Wahab <matthew.wahab@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (arm_ext_fp16): New.
(arm_extensions): New entry for "fp16".
Prevent seg-fault in gas reading a binary input file. PR 19630 * read.c (read_a_source_file): Check for assemble_one returning with input_line_pointer set to NULL.
2016-02-19 14:19:57 +01:00
2016-02-19 Nick Clifton <nickc@redhat.com>
PR 19630
* read.c (read_a_source_file): Check for assemble_one returning
with input_line_pointer set to NULL.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
2016-02-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
Add const to various variables in the gas sources. * symbols.c (decode_local_label_name): Make type a const char *. * listing.c (print_source): Make type of p const char *. (print_line): Make type of string const char *. (buffer_line): Return const char *. (title): Make type const char *. (subtitle): Likewise. (listing_listing): Make type of p const char *. * messages.c (as_internal_value_out_of_range): Make type of prefix const char *. * stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname and string const char *. * read.c (_bfd_rel): Make type of name const char *. * app.c (out_string): Change type to const char *. (struct app_save::out_string): Likewise.
2016-02-19 13:03:08 +01:00
Change the return type of the rebuffer_line function to void. * listing.c (rebuffer_line): Change return type to void.
2016-02-19 13:13:08 +01:00
* listing.c (rebuffer_line): Change return type to void.
Add const to various variables in the gas sources. * symbols.c (decode_local_label_name): Make type a const char *. * listing.c (print_source): Make type of p const char *. (print_line): Make type of string const char *. (buffer_line): Return const char *. (title): Make type const char *. (subtitle): Likewise. (listing_listing): Make type of p const char *. * messages.c (as_internal_value_out_of_range): Make type of prefix const char *. * stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname and string const char *. * read.c (_bfd_rel): Make type of name const char *. * app.c (out_string): Change type to const char *. (struct app_save::out_string): Likewise.
2016-02-19 13:03:08 +01:00
* symbols.c (decode_local_label_name): Make type a const char *.
* listing.c (print_source): Make type of p const char *.
(print_line): Make type of string const char *.
(buffer_line): Return const char *.
(title): Make type const char *.
(subtitle): Likewise.
(listing_listing): Make type of p const char *.
* messages.c (as_internal_value_out_of_range): Make type of prefix
const char *.
* stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname
and string const char *.
* read.c (_bfd_rel): Make type of name const char *.
* app.c (out_string): Change type to const char *.
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
(struct app_save::out_string): Likewise.
Add const to various variables in the gas sources. * symbols.c (decode_local_label_name): Make type a const char *. * listing.c (print_source): Make type of p const char *. (print_line): Make type of string const char *. (buffer_line): Return const char *. (title): Make type const char *. (subtitle): Likewise. (listing_listing): Make type of p const char *. * messages.c (as_internal_value_out_of_range): Make type of prefix const char *. * stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname and string const char *. * read.c (_bfd_rel): Make type of name const char *. * app.c (out_string): Change type to const char *. (struct app_save::out_string): Likewise.
2016-02-19 13:03:08 +01:00
Avoid setting or recording negative alignments when the target stores multiple octets in a single byte. gas * read.c (finish_bundle): Avoid recording a negative alignment. (do_align): Use unsigned values for n, len and max. Only create a frag if the alignment requirement is greater than the minimum byte alignment. Avoid recording a negative alignment. (s_align): Use unsigned values where appropriate. (bss_alloc): Use an unsigned value for the alignment. (sizeof_sleb128): Add a comment noting that we encode one octet per byte, regardless of the value of OCTETS_PER_BYTE_POWER. (emit_leb129_expr): Abort if the emitted encoding was longer than expected. * read.h (output_leb128): Update prototype. (sizeof_leb128): Update prototype. (bss_alloc): Update prototype. * write.c (record_alignment): Use an unsigned value for the alignment. Do not record alignments less than the minimum alignment for a byte. * write.h (record_alignment): Update prototype.
2016-02-18 10:47:31 +01:00
2016-02-18 Dan Gisselquist <dgisselq@verizon.net>
Nick Clifton <nickc@redhat.com>
* read.c (finish_bundle): Avoid recording a negative alignment.
(do_align): Use unsigned values for n, len and max. Only create
a frag if the alignment requirement is greater than the minimum
byte alignment. Avoid recording a negative alignment.
(s_align): Use unsigned values where appropriate.
(bss_alloc): Use an unsigned value for the alignment.
(sizeof_sleb128): Add a comment noting that we encode one octet
per byte, regardless of the value of OCTETS_PER_BYTE_POWER.
(emit_leb129_expr): Abort if the emitted encoding was longer than
expected.
* read.h (output_leb128): Update prototype.
(sizeof_leb128): Update prototype.
(bss_alloc): Update prototype.
* write.c (record_alignment): Use an unsigned value for the
alignment. Do not record alignments less than the minimum
alignment for a byte.
* write.h (record_alignment): Update prototype.
xtensa: fix .init/.fini literals moving Despite the documentation and the comment in xtensa_move_literals, in the presence of --text-section-literals and --auto-litpools literals are moved from the separate literal sections into .init and .fini, because the check in the xtensa_move_literals is incorrect. This moving was broken with introduction of auto litpools: some literals now may be lost. This happens because literal frags emitted from .init and .fini are not closed when new .literal_position marks new literal pool. Then frag_align(2, 0, 0) changes type of the last literal frag to rs_align. rs_align frags are skipped in the xtensa_move_literals. As a result fixups against such literals are not moved out of .init.literal/ .fini.literal sections producing the following assembler error: test.S: Warning: fixes not all moved from .init.literal test.S: Internal error! Fix check for .init.literal/.fini.literal in the xtensa_move_literals and don't let it move literals from there in the presence of --text-section-literals or --auto-litpools. 2016-02-17 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (xtensa_move_literals): Fix check for .init.literal/.fini.literal section name. * testsuite/gas/xtensa/all.exp: Add init-fini-literals to the list of xtensa tests. * testsuite/gas/xtensa/init-fini-literals.d: New file: init-fini-literals test result patterns. * testsuite/gas/xtensa/init-fini-literals.s: New file: init-fini-literals test.
2016-02-16 00:23:28 +01:00
2016-02-17 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_move_literals): Fix check for
.init.literal/.fini.literal section name.
* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
list of xtensa tests.
* testsuite/gas/xtensa/init-fini-literals.d: New file:
init-fini-literals test result patterns.
* testsuite/gas/xtensa/init-fini-literals.s: New file:
init-fini-literals test.
Update list of known MSP430 MCUs. * config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's devices.csv file as of March 2016.
2016-02-17 10:55:32 +01:00
2016-02-17 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
devices.csv file as of March 2016.
[ARC] Enable .cfi_* pseudo-ops. gas/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tc_arc_frame_initial_instructions): New function. (tc_arc_regname_to_dw2regnum): Likewise. * config/tc-arc.h (TARGET_USE_CFIPOP): Define (tc_cfi_frame_initial_instructions): Likewise. (tc_regname_to_dw2regnum): Likewise. gas/testsuite 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * gas/cfi/cfi-arc-1.d: New file. * gas/cfi/cfi-arc-1.s: Likewise. * gas/cfi/cfi.exp: Allow running tests for arc. binutils/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
2016-02-16 15:56:04 +01:00
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tc_arc_frame_initial_instructions): New
function.
(tc_arc_regname_to_dw2regnum): Likewise.
* config/tc-arc.h (TARGET_USE_CFIPOP): Define
(tc_cfi_frame_initial_instructions): Likewise.
(tc_regname_to_dw2regnum): Likewise.
testsuite/ChangeLog is no longer supposed to exist move entries to main ChangeLog
2016-03-17 00:27:50 +01:00
* testsuite/gas/cfi/cfi-arc-1.d: New file.
* testsuite/gas/cfi/cfi-arc-1.s: Likewise.
* testsuite/gas/cfi/cfi.exp: Allow running tests for arc.
[ARC] Enable .cfi_* pseudo-ops. gas/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tc_arc_frame_initial_instructions): New function. (tc_arc_regname_to_dw2regnum): Likewise. * config/tc-arc.h (TARGET_USE_CFIPOP): Define (tc_cfi_frame_initial_instructions): Likewise. (tc_regname_to_dw2regnum): Likewise. gas/testsuite 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * gas/cfi/cfi-arc-1.d: New file. * gas/cfi/cfi-arc-1.s: Likewise. * gas/cfi/cfi.exp: Allow running tests for arc. binutils/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
2016-02-16 15:56:04 +01:00
Remove documentation of deleted function S_IS_EXTERN.
2016-02-16 11:37:32 +01:00
2016-02-16 Trevor Saunders <tbsaunde@tbsaunde.org>
* doc/internals.texi (S_IS_EXTERN): Remove.
Fix formatting problems caused by previous update to as.texinfo. * doc/as.texinfo (Section): Fix up texinfo snafus in previous update.
2016-02-16 11:35:54 +01:00
2016-02-16 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Section): Fix up texinfo snafus in previous
update.
[PR19620][GAS][AArch64]Remove mov[z,k,n] relocation symbol name restriction. In AArch64 gas, register name or string starts with valid register name is not allowed as symbol name for mov[z,k,n] instruction. This patch removes the restriction. gas/ PR gas/19620 * config/tc-aarch64.c (parse_half): Remove restrictions on symbol name. * testsuite/gas/aarch64/movw_label.d: New. * testsuite/gas/aarch64/movw_label.s: New.
2016-02-16 11:00:29 +01:00
2016-02-16 Renlin Li <renlin.li@arm.com>
PR gas/19620
* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
* testsuite/gas/aarch64/movw_label.d: New.
* testsuite/gas/aarch64/movw_label.s: New.
Fix typos in gas/ChangeLog
2016-02-16 01:11:23 +01:00
2016-02-15 Vinay Kumar G. <Vinay.G@kpit.com>
Correct opcode generated for RX indirect MOVs without an offset. PR gas/19665 * config/rx-parse.y (MOV): Opcode generation for index register addressing mode. * testsuite/gas/rx/rx.exp: Updated for new testcase. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/mov.d: Update expected output.
2016-02-15 17:34:34 +01:00
Fix changelog entry for previous delta.
2016-02-15 17:54:49 +01:00
PR gas/19556
Correct opcode generated for RX indirect MOVs without an offset. PR gas/19665 * config/rx-parse.y (MOV): Opcode generation for index register addressing mode. * testsuite/gas/rx/rx.exp: Updated for new testcase. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/mov.d: Update expected output.
2016-02-15 17:34:34 +01:00
* config/rx-parse.y (MOV): Opcode generation for index
register addressing mode.
* testsuite/gas/rx/rx.exp: Updated for new testcase.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/mov.d: Update expected output.
Fix typos in gas/ChangeLog
2016-02-16 01:11:23 +01:00
2016-02-15 Nick Clifton <nickc@redhat.com>
Enhance GAS's .section directive so that it can take numeric values for the flags and type fields. (ELF only) gas * doc/as.texinfo (.section): Document that numeric values can now be used for the flags and type fields of the ELF target's .section directive. Add notes about the restrictions on setting flags and types. * config/obj-elf.c (obj_elf_change_section): Allow known sections to be given processor specific section types. Allow processor and application specific flags of a section to be set after definition. (obj_elf_parse_section_letters): Handle parsing numeric values. (obj_elf_section_type): Handle parsing numeric values. (obj_elf_section): Allow numeric type values. * config/obj-elf.h (obj_elf_change_section): Update prototype. * testsuite/gas/elf/section10.d: New test. * testsuite/gas/elf/section10.s: Source file for new test. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. * NEWS: Mention the new feature. bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values for length and type fields. Use a signed value for the suffix_length field. binutils* readelf.c (get_section_type_name): Add hex prefix to offsets printed for LOPROC and LOOS values. Ensure that a result is always returned for the V850 target, even when an unrecognised processor specific value is encountered. (process_section_headers): Display key values in the order in which they appear to the user. Add the "C (compressed)" value to the list. ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/ld-i386/pr12921.d: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sh/tlsbin-2.d: Likewise. * testsuite/ld-sh/tlspic-2.d: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/ilp32-4.d: Likewise. * testsuite/ld-x86-64/pr12718.d: Likewise. * testsuite/ld-x86-64/pr12921.d: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/split-by-file.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-xtensa/tlsbin.rd: Likewise. * testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-02-15 12:11:46 +01:00
* doc/as.texinfo (.section): Document that numeric values can now
be used for the flags and type fields of the ELF target's .section
directive. Add notes about the restrictions on setting flags and
types.
* config/obj-elf.c (obj_elf_change_section): Allow known sections
to be given processor specific section types. Allow processor and
application specific flags of a section to be set after
definition.
(obj_elf_parse_section_letters): Handle parsing numeric values.
(obj_elf_section_type): Handle parsing numeric values.
(obj_elf_section): Allow numeric type values.
* config/obj-elf.h (obj_elf_change_section): Update prototype.
* testsuite/gas/elf/section10.d: New test.
* testsuite/gas/elf/section10.s: Source file for new test.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
the description of the flags produced by readelf.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
* NEWS: Mention the new feature.
Allow the .cfi_sections directive to be reissued provided that CFI generation has not yet started. PR gas/19614 * dw2gencfi.c (cfi_sections_set): Delay setting this variable until it is actually used. (cfi_set_sections): Set cfi_sections_set to true. (dot_cfi_startproc): Likewise. (dot_cfi_endproc): Likewise. (dot_cfi_fde_data): Likewise. (cfi_finish): Likewise. (dot_cfi_sections): Do not set cfi_sections_set. * doc/as.texinfo (.cfi_sections): Note that targets can provide their own cfi section name. Also note that the directive can be reissued provided that CFI generation has not started. * testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and .cfi_endproc directives so that the redefinition of .cfi_sections will trigger the generation of the error message. * testsuite/gas/mips/compact-eh-err2.l: Update expected line number of error message.
2016-02-11 16:30:55 +01:00
2016-02-11 Nick Clifton <nickc@redhat.com>
PR gas/19614
* dw2gencfi.c (cfi_sections_set): Delay setting this variable
until it is actually used.
(cfi_set_sections): Set cfi_sections_set to true.
(dot_cfi_startproc): Likewise.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
(dot_cfi_sections): Do not set cfi_sections_set.
* doc/as.texinfo (.cfi_sections): Note that targets can provide
their own cfi section name. Also note that the directive can be
reissued provided that CFI generation has not started.
* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
.cfi_endproc directives so that the redefinition of .cfi_sections
will trigger the generation of the error message.
* testsuite/gas/mips/compact-eh-err2.l: Update expected line
number of error message.
Add support for ARC instruction relaxation in the assembler. gas/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS) (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE): Define. (arc_flags, arc_relax_type): New structure. * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY) (RELAX_TABLE_ENTRY_MAX): New define. (relaxation_state, md_relax_table, arc_relaxable_insns) (arc_num_relaxable_ins): New variable. (rlx_operand_type, arc_rlx_types): New enums. (arc_relaxable_ins): New structure. (OPTION_RELAX): New option. (arc_insn): New relax member. (arc_flags): Remove. (relax_insn_p): New function. (apply_fixups): Likewise. (relaxable_operand): Likewise. (may_relax_expr): Likewise. (relaxable_flag): Likewise. (arc_pcrel_adjust): Likewise. (md_estimate_size_before_relax): Implement. (md_convert_frag): Likewise. (md_parse_option): Handle new mrelax option. (md_show_usage): Likewise. (assemble_insn): Set relax member. (emit_insn0): New function. (emit_insn1): Likewise. (emit_insn): Handle relaxation case. * NEWS: Mention the new relaxation option. * doc/c-arc.texi (ARC Options): Document new mrelax option. gas/testsuite 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> * gas/arc/relax-avoid1.d: New file. * gas/arc/relax-avoid1.s: Likewise. * gas/arc/relax-avoid2.d: Likewise. * gas/arc/relax-avoid2.s: Likewise. * gas/arc/relax-avoid3.d: Likewise. * gas/arc/relax-avoid3.s: Likewise. * gas/arc/relax-b.d: Likewise. * gas/arc/relax-b.s: Likewise. include/opcode/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes): Declare. opcodes/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New variable.
2016-02-10 13:09:01 +01:00
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
* doc/as.texinfo (Target ARC Options): Likewise.
* testsuite/gas/arc/relax-avoid1.d: New file.
* testsuite/gas/arc/relax-avoid1.s: Likewise.
* testsuite/gas/arc/relax-avoid2.d: Likewise.
* testsuite/gas/arc/relax-avoid2.s: Likewise.
* testsuite/gas/arc/relax-avoid3.d: Likewise.
* testsuite/gas/arc/relax-avoid3.s: Likewise.
* testsuite/gas/arc/relax-b.d: Likewise.
* testsuite/gas/arc/relax-b.s: Likewise.
FIx formatting that triggers a new compile time warning message. * config/tc-ia64.c (dot_prologue): Fix formatting.
2016-02-08 15:51:10 +01:00
2016-02-08 Nick Clifton <nickc@redhat.com>
* config/tc-ia64.c (dot_prologue): Fix formatting.
Remove support for creating ARM NOREAD sections. gas * config/obj-elf.c (obj_elf_change_section): Remove support for ARM NOREAD sections. * config/tc-arm.c (arm_elf_section_letter): Delete. * config/tc-arm.h (md_elf_section_letter): Delete. * doc/c-arm.texi (ARM Section Attribute): Delete section. * testsuite/gas/arm/section-execute-only.d: Delete. * testsuite/gas/arm/section-execute-only.s: Delete. ld * testsuite/ld-arm/arm-elf.exp: Remove ARM NOREAD section tests. * testsuite/ld-arm/thumb1-input-section-flag-match.d: Delete. * testsuite/ld-arm/thumb1-input-section-flag-match.s: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.s: Delete.
2016-02-04 12:57:57 +01:00
2016-02-04 Nick Clifton <nickc@redhat.com>
* config/obj-elf.c (obj_elf_change_section): Remove support for
ARM NOREAD sections.
* config/tc-arm.c (arm_elf_section_letter): Delete.
* config/tc-arm.h (md_elf_section_letter): Delete.
* doc/c-arm.texi (ARM Section Attribute): Delete section.
* testsuite/gas/arm/section-execute-only.d: Delete.
* testsuite/gas/arm/section-execute-only.s: Delete.
Fix the encoding of the MSP430's RRUX instruction. PR target/19561 opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for decoding an RRC instruction with the ZC bit set in the extension word. include * opcode/msp430.h (IGNORE_CARRY_BIT): New define. (RRUX): Synthesise using case 2 rather than 7. gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2 to handle encoding of RRUX instruction. * testsuite/gas/msp430/msp430x.s: Add more tests of the extended shift instructions. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-04 10:55:10 +01:00
2016-02-04 Nick Clifton <nickc@redhat.com>
PR target/19561
* config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
xtensa: fix signedness of gas relocations Change 1058c7532d0b "Use signed data type for R_XTENSA_DIFF* relocation offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations substituted for BFD_RELOC_*. This made it impossible to encode arbitrary 8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc directive. Revert this part and add test. gas/ 2016-02-03 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF* substitutions for BFD_RELOC_* as unsigned. * gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests. * gas/testsuite/gas/xtensa/loc.d: New file: loc test result patterns. * gas/testsuite/gas/xtensa/loc.s: New file: loc test.
2016-02-02 15:11:38 +01:00
2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
substitutions for BFD_RELOC_* as unsigned.
Fix the encoding of the MSP430's RRUX instruction. PR target/19561 opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for decoding an RRC instruction with the ZC bit set in the extension word. include * opcode/msp430.h (IGNORE_CARRY_BIT): New define. (RRUX): Synthesise using case 2 rather than 7. gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2 to handle encoding of RRUX instruction. * testsuite/gas/msp430/msp430x.s: Add more tests of the extended shift instructions. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-04 10:55:10 +01:00
* testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests.
* testsuite/gas/xtensa/loc.d: New file: loc test result patterns.
* testsuite/gas/xtensa/loc.s: New file: loc test.
xtensa: fix signedness of gas relocations Change 1058c7532d0b "Use signed data type for R_XTENSA_DIFF* relocation offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations substituted for BFD_RELOC_*. This made it impossible to encode arbitrary 8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc directive. Revert this part and add test. gas/ 2016-02-03 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF* substitutions for BFD_RELOC_* as unsigned. * gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests. * gas/testsuite/gas/xtensa/loc.d: New file: loc test result patterns. * gas/testsuite/gas/xtensa/loc.s: New file: loc test.
2016-02-02 15:11:38 +01:00
msp430: Set DWARF2_ADDR_SIZE to 4. This change makes gas's notion of the msp430 dwarf2 address size match that of gcc and gdb. This is needed so that the format of addresses generated for DW_LNE_set_address in .debug_line will match the address size for the compilation unit. In gcc/config/msp430/msp430.h, it's set to 4: #define DWARF2_ADDR_SIZE 4 Likewise in gdb/msp430-tdep.c: set_gdbarch_dwarf2_addr_size (gdbarch, 4); (As far as I can tell, however, GDB doesn't use this value when decoding .debug_line. Instead, GDB uses the Pointer Size from the compilation unit.) readelf is able to seamlessly handle mismatches between these various sizes by using the size of the DW_LNE_set_address instruction to determine the address size. Another way to fix this problem is to make GDB behave in a similar manner. In my opinion, GDB should detect and inform the user about these mismatches; it's not clear to me if it's correct for GDB to go ahead and read the address anyway when a size mismatch is detected. Without this change, addresses in .debug_line are encoded in two bytes for some multilibs. When GDB reads the address for DW_LNE_set_address, it uses the pointer size provided by the CU. When these values don't match, GDB reads the wrong number of bytes. In the cases that I've looked at, GDB is reading 4 bytes from a 2 byte container, which results in a garbage address. GDB discards lines which have a bogus address; the end result is that GDB records no line number information for CUs which have a mismatch between the address size (from the CU) and the format of the address used by DW_LNE_set_address. gas/ChangeLog: * config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-27 20:44:38 +01:00
2016-02-03 Kevin Buettner <kevinb@redhat.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
msp430: Set DWARF2_ADDR_SIZE to 4. This change makes gas's notion of the msp430 dwarf2 address size match that of gcc and gdb. This is needed so that the format of addresses generated for DW_LNE_set_address in .debug_line will match the address size for the compilation unit. In gcc/config/msp430/msp430.h, it's set to 4: #define DWARF2_ADDR_SIZE 4 Likewise in gdb/msp430-tdep.c: set_gdbarch_dwarf2_addr_size (gdbarch, 4); (As far as I can tell, however, GDB doesn't use this value when decoding .debug_line. Instead, GDB uses the Pointer Size from the compilation unit.) readelf is able to seamlessly handle mismatches between these various sizes by using the size of the DW_LNE_set_address instruction to determine the address size. Another way to fix this problem is to make GDB behave in a similar manner. In my opinion, GDB should detect and inform the user about these mismatches; it's not clear to me if it's correct for GDB to go ahead and read the address anyway when a size mismatch is detected. Without this change, addresses in .debug_line are encoded in two bytes for some multilibs. When GDB reads the address for DW_LNE_set_address, it uses the pointer size provided by the CU. When these values don't match, GDB reads the wrong number of bytes. In the cases that I've looked at, GDB is reading 4 bytes from a 2 byte container, which results in a garbage address. GDB discards lines which have a bogus address; the end result is that GDB records no line number information for CUs which have a mismatch between the address size (from the CU) and the format of the address used by DW_LNE_set_address. gas/ChangeLog: * config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-27 20:44:38 +01:00
Add -mrelax-relocations= to x86 assembler The x86 relax relocations introduced in binutils 2.26 aren't supported by linker on Solaris older than Solaris 12. To use x86 assembler with older Solaris linker, this patch adds 1. A command line option -mrelax-relocations= to x86 assembler to control whether to generate relax relocations. 2. A configure option --enable-x86-relax-relocations to decide whether x86 assembler should generate relax relocations by default. It is defaulted to yes, except for x86 Solaris targets older than Solaris 12. gas/ PR gas/19520 * NEWS: Mention new command line option -mrelax-relocations and new configure option --enable-x86-relax-relocations for x86 target. * config.in: Regenerated. * configure.ac: Add --enable-x86-relax-relocations. (ac_default_x86_relax_relocations): New. Default to 1 except for x86 Solaris targets older than Solaris 12. (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define. * configure: Likewise. * config/tc-i386.c (generate_relax_relocations): New. (OPTION_MRELAX_RELOCATIONS): Likewise. (output_disp): Don't generate relax relocations if generate_relax_relocations is 0. (md_longopts): Add -mrelax-relocations. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS. * doc/c-i386.texi: Document -mrelax-relocations=. * testsuite/gas/i386/got-no-relax.d: New file. * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise. * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as. * testsuite/gas/i386/localpic.d: Likewise. * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise. * testsuite/gas/i386/reloc32.d: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. * testsuite/gas/i386/i386.exp: Run got-no-relax and x86-64-gotpcrel-no-relax. ld/ PR gas/19520 * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as. * testsuite/ld-i386/call1.d: Likewise. * testsuite/ld-i386/call2.d: Likewise. * testsuite/ld-i386/call3a.d: Likewise. * testsuite/ld-i386/call3b.d: Likewise. * testsuite/ld-i386/call3c.d: Likewise. * testsuite/ld-i386/call3d.d: Likewise. * testsuite/ld-i386/call3e.d: Likewise. * testsuite/ld-i386/call3f.d: Likewise. * testsuite/ld-i386/call3g.d: Likewise. * testsuite/ld-i386/call3h.d: Likewise. * testsuite/ld-i386/jmp1.d: Likewise. * testsuite/ld-i386/jmp2.d: Likewise. * testsuite/ld-i386/lea1c.d: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/load2.d: Likewise. * testsuite/ld-i386/load3.d: Likewise. * testsuite/ld-i386/load4a.d: Likewise. * testsuite/ld-i386/load5a.d: Likewise. * testsuite/ld-i386/mov2b.d: Likewise. * testsuite/ld-i386/mov3.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-x86-64/call1a.d: Likewise. * testsuite/ld-x86-64/call1b.d: Likewise. * testsuite/ld-x86-64/call1c.d: Likewise. * testsuite/ld-x86-64/call1d.d: Likewise. * testsuite/ld-x86-64/call1e.d: Likewise. * testsuite/ld-x86-64/call1f.d: Likewise. * testsuite/ld-x86-64/call1h.d: Likewise. * testsuite/ld-x86-64/call1i.d: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it. * testsuite/ld-i386/got1.dd: Updated. * testsuite/ld-i386/got1d.S (1): Removed. * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-02-03 17:25:15 +01:00
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19520
* NEWS: Mention new command line option -mrelax-relocations and
new configure option --enable-x86-relax-relocations for x86
target.
* config.in: Regenerated.
* configure.ac: Add --enable-x86-relax-relocations.
(ac_default_x86_relax_relocations): New. Default to 1 except
for x86 Solaris targets older than Solaris 12.
(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
* configure: Likewise.
* config/tc-i386.c (generate_relax_relocations): New.
(OPTION_MRELAX_RELOCATIONS): Likewise.
(output_disp): Don't generate relax relocations if
generate_relax_relocations is 0.
(md_longopts): Add -mrelax-relocations.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
* doc/c-i386.texi: Document -mrelax-relocations=.
* testsuite/gas/i386/got-no-relax.d: New file.
* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
* testsuite/gas/i386/localpic.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
* testsuite/gas/i386/reloc32.d: Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/i386.exp: Run got-no-relax and
x86-64-gotpcrel-no-relax.
Mention -mfence-as-lock-add=yes for x86 assembler * NEWS: Mention new command line option -mfence-as-lock-add=yes for x86 target.
2016-02-03 15:42:39 +01:00
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention new command line option -mfence-as-lock-add=yes
for x86 target.
Remove duplicated marker for 2.26 in gas/NEWS * NEWS: Remove duplicated marker for 2.26.
2016-02-03 15:37:21 +01:00
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Remove duplicated marker for 2.26.
[GAS][ARM]Skip none elf target for testsuite/gas/arm/thumb2_it_search.s gas/ * testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
2016-02-02 16:52:42 +01:00
2016-02-02 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
gas/ip2k: Add all instructions assembler test Basic all instructions assembler test, auto-generated by CGEN, then fixed by hand for some cases where CGEN had generated invalid instruction operands. gas/ChangeLog: * testsuite/gas/ip2k/allinsn.d: New file. * testsuite/gas/ip2k/allinsn.s: New file. * testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
2016-02-01 17:31:35 +01:00
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/ip2k/allinsn.d: New file.
* testsuite/gas/ip2k/allinsn.s: New file.
* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
epiphany/gas: Update expected test results for 0 offset loads In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 some of the load instructions with a zero offset (where the offset is not mentioned) were marked as NO-DIS, meaning that the disassembler must display the offset, even though it is zero. This change seems a little strange to me as it was only applied to some loads, not all, and the same change was not applied to the stores. However, I'm reluctant to revert a specific change to the assembler, when the output is obviously correct. With this commit then I simply bring the expected assembler test results into line with what is actually produced. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to some load instructions. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/regression.d: Likewise.
2016-02-01 21:21:19 +01:00
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
epiphany/gas: Remove .l suffix from expected test results In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 all instruction aliases that have a '.l' suffix were marked as NO-DIS, so the disassembler will not display them, in preference to the instruction without the suffix. However, the gas testsuite was not updated at the time, this commit fixes that oversight. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l' suffixes from instruction mnemonics in expected output. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/regression.d: Likewise. * testsuite/gas/epiphany/sample.d: Likewise.
2016-02-01 21:01:52 +01:00
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
suffixes from instruction mnemonics in expected output.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
gas/epiphany: Update expected register names in tests In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 the register aliases sb, sl, and ip were made less preferred than r9, r10, and r12, however, the expected test results were not updated. This commit fixes this oversight and updates the test results. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Update expected register names. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/sample.d: Likewise.
2016-02-01 20:20:25 +01:00
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Update expected register
names.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
epiphany/disassembler: Improve alignment of output. Always set the bytes_per_line field (of struct disassemble_info) to the same constant value, this is inline with the advice contained within include/dis-asm.h. Setting this field to a constant value will cause the disassembler output to be better aligned. cpu/ChangeLog: * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to a constant to better align disassembler output. opcodes/ChangeLog: * epiphany-dis.c: Regenerated from latest cpu files. gas/ChangeLog: * testsuite/gas/epiphany/sample.d: Update expected output.
2016-02-01 19:21:37 +01:00
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/sample.d: Update expected output.
Fix ARC TLS support. * config/tc-arc.c (md_apply_fix): Allow addendum. (arc_reloc_op): Allow complex expressions for tpoff. (md_apply_fix): Handle resolved TLS local symbol. * gas/arc/tls-relocs1.d: New file. * gas/arc/tls-relocs1.s: Likewise.
2016-02-01 18:03:56 +01:00
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Fix gas/ChangeLog
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (md_apply_fix): Allow addendum.
(arc_reloc_op): Allow complex expressions for tpoff.
(md_apply_fix): Handle resolved TLS local symbol.
Fix ARC TLS support. * config/tc-arc.c (md_apply_fix): Allow addendum. (arc_reloc_op): Allow complex expressions for tpoff. (md_apply_fix): Handle resolved TLS local symbol. * gas/arc/tls-relocs1.d: New file. * gas/arc/tls-relocs1.s: Likewise.
2016-02-01 18:03:56 +01:00
* testsuite/gas/arc/tls-relocs1.d: New file.
* testsuite/gas/arc/tls-relocs1.s: Likewise.
Fix a problem building the ARM assembler using LLVM. PR target/19311 * config/tc-arm.c (encode_arm_immediate): Recode to improve efficiency and avoid an LLVM loop optimization bug.
2016-02-01 15:32:25 +01:00
2016-02-01 Loria <Loria@phantasia.org>
PR target/19311
* config/tc-arm.c (encode_arm_immediate): Recode to improve
efficiency and avoid an LLVM loop optimization bug.
Fix error building Microblaze assembler on a 32-bit host. * config/tc-microblaze.c (parse_imm): Fix compile time warning message extending a negative 32-bit value into a larger signed value on a 32-bit host.
2016-02-01 12:36:59 +01:00
2016-02-01 Nick Clifton <nickc@redhat.com>
* config/tc-microblaze.c (parse_imm): Fix compile time warning
message extending a negative 32-bit value into a larger signed
value on a 32-bit host.
Replace == with = in gas/configure.ac PR gas/19532 * configure.ac (compressed_debug_sections): Replace == with =. * configure: Regenerated.
2016-01-29 16:47:45 +01:00
2016-01-29 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19532
* configure.ac (compressed_debug_sections): Replace == with =.
* configure: Regenerated.
Add option -mfence-as-lock-add=[no|yes]. With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded as lock addl $0x0, (%{r,e}sp). gas/: * config/tc-i386.c (avoid_fence): New. (output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence is true. (OPTION_FENCE_AS_LOCK_ADD): New. (md_longopts): Add -mfence-as-lock-add. (md_parse_option): Handle -mfence-as-lock-add. (md_show_usage): Add -mfence-as-lock-add=[no|yes]. * doc/c-i386.texi (-mfence-as-lock-add): Document. gas/testsuite/: * gas/i386/i386.exp: Run new tests. * gas/i386/fence-as-lock-add.s: New. * gas/i386/fence-as-lock-add-yes.d: Likewise. * gas/i386/fence-as-lock-add-no.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-29 13:46:50 +01:00
2016-01-29 Andrew Senkevich <andrew.senkevich@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (avoid_fence): New.
(output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
is true.
(OPTION_FENCE_AS_LOCK_ADD): New.
(md_longopts): Add -mfence-as-lock-add.
(md_parse_option): Handle -mfence-as-lock-add.
(md_show_usage): Add -mfence-as-lock-add=[no|yes].
* doc/c-i386.texi (-mfence-as-lock-add): Document.
Add testsuite/ to the last gas ChangeLog entry
2016-01-29 14:01:07 +01:00
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/fence-as-lock-add.s: New.
* testsuite/gas/i386/fence-as-lock-add-yes.d: Likewise.
* testsuite/gas/i386/fence-as-lock-add-no.d: Likewise.
* testsuite/gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
* testsuite/gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
Add option -mfence-as-lock-add=[no|yes]. With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded as lock addl $0x0, (%{r,e}sp). gas/: * config/tc-i386.c (avoid_fence): New. (output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence is true. (OPTION_FENCE_AS_LOCK_ADD): New. (md_longopts): Add -mfence-as-lock-add. (md_parse_option): Handle -mfence-as-lock-add. (md_show_usage): Add -mfence-as-lock-add=[no|yes]. * doc/c-i386.texi (-mfence-as-lock-add): Document. gas/testsuite/: * gas/i386/i386.exp: Run new tests. * gas/i386/fence-as-lock-add.s: New. * gas/i386/fence-as-lock-add-yes.d: Likewise. * gas/i386/fence-as-lock-add-no.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-29 13:46:50 +01:00
Remove trailing `]' in --enable-compressed-debug-sections * configure.ac (compressed_debug_sections): Remove trailing `]'. * configure: Regenerated.
2016-01-27 19:24:51 +01:00
2016-01-27 H.J. Lu <hongjiu.lu@intel.com>
* configure.ac (compressed_debug_sections): Remove trailing `]'.
* configure: Regenerated.
Rename OPTION_OMIT_LOCK_PREFIX to OPTION_MOMIT_LOCK_PREFIX Use OPTION_MXXX for -mxxx option in x86 assembler. * config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ... (OPTION_MOMIT_LOCK_PREFIX): This. (md_longopts): Updated. (md_parse_option): Likewise.
2016-01-26 02:01:11 +01:00
2016-01-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ...
(OPTION_MOMIT_LOCK_PREFIX): This.
(md_longopts): Updated.
(md_parse_option): Likewise.
Avoid the use of gp-relative addressing when abicalls are in effect.
2016-01-25 21:39:40 +01:00
2016-01-25 Catherine Moore <clm@codesourcery.com>
* config/mips/tc-mips.c (md_begin): Avoid gp-relative addressing
if abicalls are in effect.
* testsuite/gas/mips/sdata-gp.s: New test.
* testsuite/gas/mips/sdata-gp.d: New expected output
* testsuite/gas/mips/mips.exp: Run new test.
[PATCH[ARM]Check mapping symbol while backward searching for IT block. opcodes/ * arm-dis.c (mapping_symbol_for_insn): New function. (find_ifthen_state): Call mapping_symbol_for_insn(). gas/ * testsuite/gas/arm/thumb2_it_search.d: New. * testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-25 16:06:54 +01:00
2016-01-25 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/thumb2_it_search.d: New.
* testsuite/gas/arm/thumb2_it_search.s: New.
Fix gas testsuite failures for ARM netbesdelf configuration. PR gas/19454 * testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope with arm-netbsdelf target. * testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
2016-01-21 15:39:34 +01:00
2016-01-21 Nick Clifton <nickc@redhat.com>
PR gas/19454
* testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope
with arm-netbsdelf target.
* testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
Skip ARM v8 tests for COFF based targets.
2016-01-20 16:00:57 +01:00
2016-01-20 Nick Clifton <nickc@redhat.com>
Fix unexpected failures in GAS testsuite for ARM VxWorks target. PR 19456 * testsuite/gas/arm/weakdef-1.d: Skip for VxWorks. * testsuite/gas/arm/blx-bl-convert.d * testsuite/gas/arm/plt-1.d: Likewise. * testsuite/gas/arm/reloc-bad.d: Likewise. * testsuite/gas/arm/thumb-w-good.d: Likewise. * testsuite/gas/arm/thumb2_pool.d: Likewise. * testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks * testsuite/gas/arm/tls_vxworks.d: Update expected output.
2016-01-20 18:02:42 +01:00
PR 19456
* testsuite/gas/arm/weakdef-1.d: Skip for VxWorks.
* testsuite/gas/arm/blx-bl-convert.d
* testsuite/gas/arm/plt-1.d: Likewise.
* testsuite/gas/arm/reloc-bad.d: Likewise.
* testsuite/gas/arm/thumb-w-good.d: Likewise.
* testsuite/gas/arm/thumb2_pool.d: Likewise.
* testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks
* testsuite/gas/arm/tls_vxworks.d: Update expected output.
Upda the documentation on assembler error message generation. PR 19499 * doc/as.texinfo (Errors): Correct documentation describing the interaction of .file and .line with warning and error messages.
2016-01-20 17:21:34 +01:00
PR 19499
* doc/as.texinfo (Errors): Correct documentation describing the
interaction of .file and .line with warning and error messages.
Skip ARM v8 tests for COFF based targets.
2016-01-20 16:00:57 +01:00
PR 19458
* testsuite/gas/arm/armv8_2-a.d: Skip for COFF based targets.
* testsuite/gas/arm/archv8m-main.d: Likewise.
* testsuite/gas/arm/archv8m-base.d: Likewise.
[AArch64] Reject invalid immediate operands to MSR UAO In the instruction to write to the ARMv8.2 PSTATE field UAO, MSR UAO, #<imm>, the immediate should be either 0 or 1 but GAS accepts any unsigned 4-bit integer. This patch implements the constraint on the immediate, generating an error if the immediate operand is invalid, and adds tests for the illegal forms. opcodes/ 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Check validity of MSR UAO immediate operand. gas/ 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> * testsuite/gas/aarch64/armv8_2-a-illegal.d: New. * testsuite/gas/aarch64/armv8_2-a-illegal.l: New. * testsuite/gas/aarch64/armv8_2-a-illegal.s: New. Change-Id: Ibdec4967c00b1ef3be9dbc43d23b2c70d1a0b28c
2016-01-20 15:25:46 +01:00
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.
Add support for an ARM specific 'y' section attribute flag to mark the section as NOREAD. bfd/ChangeLog: * elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread section using '.text.noread' pattern. gas/ChangeLog: * config/obj-elf.c (obj_elf_change_section) : Allow arm section with SHF_ARM_NOREAD section flag. * config/tc-arm.h (md_elf_section_letter) : Implement this hook to handle letter 'y'. (arm_elf_section_letter) : Declare it. * config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set SHF_ARM_NOREAD section flag. * doc/c-arm.texi (ARM section attribute 'y'): Document it. gas/testsuite/ChangeLog: * gas/arm/section-execute-only.s: New test case. * gas/arm/section-execute-only.d: Expected output. ld/testsuite/ChangeLog: * ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y' attribute usage. * ld-arm/thumb1-noread-present-one-section.s: Likewise. * ld-arm/thumb1-noread-present-two-section.s: Likewise. * ld-arm/thumb1-input-section-flag-match.s: Likewise. binutils/ChangeLog: * readelf.c (get_elf_section_flags): Display y letter for section with SHF_ARM_NOREAD section flag in readelf section output. (process_section_headers): Add y letter in readelf section output key mapping for ARM architecture.
2016-01-20 13:53:50 +01:00
2016-01-20 Mickael Guene <mickael.guene@st.com>
Terry Guo <terry.guo@arm.com>
* config/obj-elf.c (obj_elf_change_section) : Allow arm section with
SHF_ARM_NOREAD section flag.
* config/tc-arm.h (md_elf_section_letter) : Implement this hook to
handle letter 'y'.
(arm_elf_section_letter) : Declare it.
* config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
SHF_ARM_NOREAD section flag.
* doc/c-arm.texi (ARM section attribute): Document the 'y' attribute.
* testsuite/gas/arm/section-execute-only.s: New test case.
* testsuite/gas/arm/section-execute-only.d: Expected output.
MIPS: Remove remnants of 48-bit microMIPS instruction support The POOL48A major opcode was defined in early revisions of the 64-bit microMIPS ISA, has never been implemented, and was removed before the 64-bit microMIPS ISA specification[1] has been finalized. This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS 48-bit LI instruction"). References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of Major Opcode Field", p. 578 gas/ * config/tc-mips.c (micromips_insn_length): Remove the mention of 48-bit microMIPS instructions. gdb/ * mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS instruction support. (micromips_next_pc): Likewise. (micromips_scan_prologue): Likewise. (micromips_deal_with_atomic_sequence): Likewise. (micromips_stack_frame_destroyed_p): Likewise. (mips_breakpoint_from_pc): Likewise. opcodes/ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS instruction support.
2016-01-18 22:29:37 +01:00
2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
Provide AC_PROG_LEX that copes with LEX=missing from top-level config/ PR binutils/19481 * override.m4 (AC_PROG_LEX): Define. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. ld/ * configure: Regenerate.
2016-01-18 06:36:49 +01:00
2016-01-18 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
Regen configure Picks up 2016-01-12 libtool.m4 change. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2016-01-17 02:50:55 +01:00
2016-01-17 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
m68hc11/12 and xgate config.sub weirdness Oddly, config.sub converts a duple ending in -elf for these target to -unknown-none, which means they aren't seen as elf targets by binutils. So, counter that. This exposes a number of testsuite issues (ones you would have seen if configuring with a full triple, say m68hc11-unknown-elf). binutils/ * testsuite/lib/binutils-common.exp (is_elf_format): Return true for m68hc11/12 and xgate triples. gas/ * testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test. ld/ * testsuite/lib/ld-lib.exp (check_shared_lib_support): Exclude xgate. * testsuite/ld-elf/endsym.d: xfail m68hc11/12 and xgate. * testsuite/ld-elf/pr14156a.d: Likewise. * testsuite/ld-elf/pr14926.d: Don't run for m68hc11/12 and xgate. * testsuite/ld-elf/sec64k.exp: Likewise.
2016-01-17 02:43:43 +01:00
2016-01-17 Alan Modra <amodra@gmail.com>
* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
Fix display of RL78 MOVW instructions that use the stack pointer. * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw instructions that can support stack pointer operations. * rl78-decode.c: Regenerate. * rl78-dis.c: Fix display of stack pointer in MOVW based instructions. * testsuite/gas/rl78/sp-relative-movw.s: New test. * testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly. * testsuite/gas/rl78/rl78.exp: Run the new test.
2016-01-14 17:23:35 +01:00
2016-01-14 Nick Clifton <nickc@redhat.com>
* testsuite/gas/rl78/sp-relative-movw.s: New test.
* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
* testsuite/gas/rl78/rl78.exp: Run the new test.
[AArch64] Fix missing architecture checks for ARMv8.2 system registers. Some of the RAS system registers added to binutils as part of the ARMv8.2 support are missing the feature checks to warn when they aren't supported by the target. This patch adds the missing feature checks with a test to check that the correct warnings are given for all the ARMv8.2 system registers. gas/ 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> * testsuite/gas/aarch64/illegal-sysreg-2.l: New. * testsuite/gas/aarch64/illegal-sysreg-2.d: New. opcodes/ 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, erxtatus_el1 and erxaddr_el1. Change-Id: I66b590ea49c1eb6b0e5c93e0dc2bc9c4e79a52fe
2016-01-14 11:55:11 +01:00
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-2.l: New.
* testsuite/gas/aarch64/illegal-sysreg-2.d: New.
Nios II/GAS: Fix build error in `output_movia' Fix: cc1: warnings being treated as errors .../gas/config/tc-nios2.c: In function 'output_movia': .../gas/config/tc-nios2.c:3474: warning: 'code' may be used uninitialized in this function make[4]: *** [tc-nios2.o] Error 1 seen with GCC 4.1.2 and 4.4.7. gas/ * config/tc-nios2.c (output_movia): Preset `code' to 0.
2016-01-13 21:58:29 +01:00
2016-01-13 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-nios2.c (output_movia): Preset `code' to 0.
Remove spurious condition in test for closing parenthesis. * config/tc-h8300.c (get_operand): Remove spurious condition in test for closing parenthesis.
2016-01-13 18:47:34 +01:00
2016-01-13 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/tc-h8300.c (get_operand): Remove spurious condition in
test for closing parenthesis.
[ARM] Support ARMv8.2 RAS extension. The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-12 17:35:30 +01:00
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): New.
(insns): Add "esb".
* testsuite/gas/arm/armv8_2-a.d: New.
* testsuite/gas/arm/armv8_2-a.s: New.
PowerPC gas test vsx3 Tweak for padding, now present for COFF. * testsuite/gas/ppc/vsx3.d: Accept nop padding.
2016-01-12 08:50:26 +01:00
2016-01-12 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/vsx3.d: Accept nop padding.
Delete opcodes that have been removed from ISA 3.0. opcodes/ * ppc-opc.c <xscmpnedp>: Delete. <xvcmpnedp>: Likewise. <xvcmpnedp.>: Likewise. <xvcmpnesp>: Likewise. <xvcmpnesp.>: Likewise. gas/ * testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp.>: Delete tests. * testsuite/gas/ppc/power9.s: Likewise. * testsuite/gas/ppc/vsx3.d: Likewise. * testsuite/gas/ppc/vsx3.s: Likewise.
2016-01-11 18:54:58 +01:00
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
xvcmpnesp, xvcmpnesp.>: Delete tests.
* testsuite/gas/ppc/power9.s: Likewise.
* testsuite/gas/ppc/vsx3.d: Likewise.
* testsuite/gas/ppc/vsx3.s: Likewise.
m68k: fix constraints of move.[bw] for ISA_B/C For ISA_B/C only the combination #,d(An) is allowed in addition to the ISA_A combinations for move.b and move.w (and pc-relative is never allowed as destination). opcodes/ PR gas/13050 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in addition to ISA_A. gas/ PR gas/13050 * testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2. * testsuite/gas/m68k/p13050-1.s: New file. * testsuite/gas/m68k/p13050-2.d: New file. * testsuite/gas/m68k/p13050-2.s: New file.
2016-01-08 11:38:00 +01:00
2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
PR gas/13050
* testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2.
* testsuite/gas/m68k/p13050-1.s: New file.
* testsuite/gas/m68k/p13050-2.d: New file.
* testsuite/gas/m68k/p13050-2.s: New file.
bfd/arc: Add R_ prefix to all relocation names The convention within for relocation names is that they start with the string "R_", however, this is not so for ARC for the display names of relocations, however, internally, the names for the relocations types do have the 'R_' prefix. I suspect that the missing 'R_' on the output strings was an oversight, as I can't see any comment to the contrary. To bring ARC into line with other targets, this commit adds the 'R_' prefix to the output strings used for relocation names, and updates all of the assembler tests where this was exposed. bfd/ChangeLog: * elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to place 'R_' before the reloc name returned. (elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before the relocation string. gas/ChangeLog: * testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names. * testsuite/gas/arc/add.d: Likewise. * testsuite/gas/arc/and.d: Likewise. * testsuite/gas/arc/asl.d: Likewise. * testsuite/gas/arc/asr.d: Likewise. * testsuite/gas/arc/bic.d: Likewise. * testsuite/gas/arc/extb.d: Likewise. * testsuite/gas/arc/extw.d: Likewise. * testsuite/gas/arc/j.d: Likewise. * testsuite/gas/arc/jl.d: Likewise. * testsuite/gas/arc/ld2.d: Likewise. * testsuite/gas/arc/lsr.d: Likewise. * testsuite/gas/arc/mov.d: Likewise. * testsuite/gas/arc/or.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/rlc.d: Likewise. * testsuite/gas/arc/ror.d: Likewise. * testsuite/gas/arc/rrc.d: Likewise. * testsuite/gas/arc/sbc.d: Likewise. * testsuite/gas/arc/sda-relocs.d: Likewise. * testsuite/gas/arc/sda-relocs2.d: Likewise. * testsuite/gas/arc/sexb.d: Likewise. * testsuite/gas/arc/sexw.d: Likewise. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/sub.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/xor.d: Likewise.
2016-01-05 15:46:39 +01:00
2016-01-06 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
* testsuite/gas/arc/add.d: Likewise.
* testsuite/gas/arc/and.d: Likewise.
* testsuite/gas/arc/asl.d: Likewise.
* testsuite/gas/arc/asr.d: Likewise.
* testsuite/gas/arc/bic.d: Likewise.
* testsuite/gas/arc/extb.d: Likewise.
* testsuite/gas/arc/extw.d: Likewise.
* testsuite/gas/arc/j.d: Likewise.
* testsuite/gas/arc/jl.d: Likewise.
* testsuite/gas/arc/ld2.d: Likewise.
* testsuite/gas/arc/lsr.d: Likewise.
* testsuite/gas/arc/mov.d: Likewise.
* testsuite/gas/arc/or.d: Likewise.
* testsuite/gas/arc/pcl-relocs.d: Likewise.
* testsuite/gas/arc/pcrel-relocs.d: Likewise.
* testsuite/gas/arc/pic-relocs.d: Likewise.
* testsuite/gas/arc/plt-relocs.d: Likewise.
* testsuite/gas/arc/rlc.d: Likewise.
* testsuite/gas/arc/ror.d: Likewise.
* testsuite/gas/arc/rrc.d: Likewise.
* testsuite/gas/arc/sbc.d: Likewise.
* testsuite/gas/arc/sda-relocs.d: Likewise.
* testsuite/gas/arc/sda-relocs2.d: Likewise.
* testsuite/gas/arc/sexb.d: Likewise.
* testsuite/gas/arc/sexw.d: Likewise.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/sub.d: Likewise.
* testsuite/gas/arc/tls-relocs.d: Likewise.
* testsuite/gas/arc/xor.d: Likewise.
Copyright update for binutils
2016-01-01 12:25:12 +01:00
2016-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
For older changes see ChangeLog-2015 and testsuite/ChangeLog-2015
Copyright (C) 2016 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
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