Upon re-consideration in commit 569d50f1c6 ("x86: further refine SSE
check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns
doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a
being an AMD-only extension, it shouldn't be part of the ISA extensions
set for which the diagnostic may get issued. Undo that part.
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
(elf32xtensa_abi): New global variable.
(xtensa_abi_choice): New function.
(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
XSHAL_ABI to select PLT code.
gas/
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
include/
* elf/xtensa.h (xtensa_abi_choice): New declaration.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test
ABI tag consistency.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
OPTION_ABI_CALL0 and declare elf32xtensa_abi.
(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
--abi-call0.
* ld.texi: Add description for options --abi-windowed and
--abi-call0.
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is
0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable,
but may also cause risk of compatibility. Binutils already support the
-mpriv-spec options and ELF priv attributes, which can used to choose what
privileged spec you want, and then give a correponding CSR name and address
to use. But Gdb and other tools don't have the simialr mechanism for now.
However, there are two things can be confirmed,
1. If we don't have a way to control the priv specs, then the changes, like
MISA, will cause risk and hard to maintain.
2. We get the guarantee that the CSR address won't be reused in the future
specs, even if it is dropped.
I'm not sure if Gdb needs to care about the priv spec versions, it is still
discussing. But drop the priv spec v1.9, and make sure that we won't reuse
the CSR address is a useful solution for now. Also, we might drop the v1.9.1
in a year or two. After that, specs above v1.10 should be compatible anyway.
gas/
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
include/
* opcode/riscv-opc.h: Update the defined versions of CSR from
PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the
MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
* opcode/riscv.h (enum riscv_priv_spec_class): Remove
PRIV_SPEC_CLASS_1P9.
opcodes/
* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
All of data size, rep, lock, and rex prefixes are invalid with VEX- and
alike encoded insns. Make sure they get printed explicitly in all cases,
to signal the anomaly. With this, do away with "rex_ignored" - if there
is a rex prefix, we want to print it anyway for VEX etc (and there's
nothing "ignored" about it in the first place - such an instruction will
raise #UD).
Various AVX insns utilizing the X macro fail to reject F3/F2 embedded
prefix encodings. As the PREFIX_OPCODE attribute wasn't used by any
non-legacy-encoded insns so far, re-use it to achieve the intended
effect.
An unwanted side effect of 5990e377e5 ("x86-64: Intel64 adjustments
for insns dealing with far pointers") was that with -mintel64 LCALL and
LJMP would now default to 64-bit operand size. Since 64-bit far branches
aren't portable, the default operand size should still be 32-bit.
However, since the 64-bit variant is permitted, an ambiguous operand
warning should be issued.
As to the actual code change, please note that the conditional
surrounding the switch() that gets adjusted covers several cases which
are of no interest to or benign in 64-bit mode, hence the new
conditional added can be quite a bit less involved.
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not
be randomly ignored. Fix this for insns without operands as well as for
insns referencing the high 16 [XYZ]MM registers. To achieve the former,
re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and
moving its only operand check to check_VecOperands().
This involves fixing a testcase relying on {vex2} to get ignored.
With the introduction of what right now is the very first conditional
in the function's loop (commit dc821c5f9a ["x86: replace Reg8, Reg16,
Reg32, and Reg64"]), the last if() in the same loop has become
pointless - retain just its body.
First of all, these registers have never been available on any 64-bit
CPU, and hence should not be recognized in 64-bit mode. But even before
that they had already disappeared - also don't recognize them when 586
or 686 architectures were explicitly set.
While putting together the previous patch I noticed that this test,
forever since its introduction, was dead. Update it so it will pass,
and enable it.
In 0e0eea7820 ("x86: x87-related adjustments") I screwed up CFI
directives with FPU support disabled, by moving the conditional there
across a check of "allow_pseudo_reg". Add the missing check.
Register aliases (created e.g. via .set) check their target register at
the time of creation of the alias. While this makes sense, it's not
enough: The underlying register must also be "visible" at the time of
use. Wrong use of such aliases would lead to internal errors in e.g.
add_prefix() or build_modrm_byte().
Split the checking part of parse_real_register() into a new helper
function and use it also from the latter part of parse_register() (at
the same time replacing a minor open coded part of it).
Since parse_register() returning NULL already has a meaning, a fake new
"bad register" indicator gets added, which all callers need to check
for.
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
The GAS struct frag ends with a field `fr_literal' whose purpose is to
mark the begining of the frag's data:
struct frag {
...
/* Data begins here. */
char fr_literal[1];
};
The code in gas/config/tc-bpf.c recently committed:
where = fixP->fx_frag->fr_literal + fixP->fx_where;
where[1] = target_big_endian ? 0x01 : 0x10;
triggers the stringop-overflow warning in GCC 10+, since the compiler
assumes the size of the modified buffer is 1 byte. This patch
slightly modifies the code to make tc-bpf.c buildable with GCC 10+.
2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
stringop-overflow.
gas/
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
Fix ip2k-elf and xstormy16-elf build due to
commit e9bffec9af
Author: Jose E. Marchesi <jose.marchesi@oracle.com>
Date: Thu Jun 4 16:15:53 2020 +0200
opcodes: discriminate endianness and insn-endianness in CGEN ports
* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
cgen_get_insn_value.
* config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
endianness to cgen_get_insn_value and cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
* bpf.opc (bpf_print_insn): Do not set endian_code here.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
bpf_cgen_cpu_open.
(md_assemble): Remove no longer needed hack.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* disassemble.c (disassemble_init_for_target): Set endian_code for
bpf targets.
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-dis.c: Likewise.
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
This fixes some minor bugs in the docs for the .insn directive pointed out
by Frédéric Pétrot, and I added a few more cleanups since I was changing
the docs.
gas/
PR 26051
* doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B
formats using simm12(rs1). Correct SB and B to use rs1 and rs2.
Move B before SB. Move J before UJ.
This patch fixes internal errors in (at least) arm and aarch64 GAS
when assembling code that attempts a negative .org. The bug appears
to be a regression introduced in binutils-2.29 by commit 9875b36538.
* write.c (relax_segment): Fix handling of negative offset when
relaxing an rs_org frag.
* testsuite/gas/aarch64/org-neg.d: New test.
* testsuite/gas/aarch64/org-neg.l: Error output for test.
* testsuite/gas/aarch64/org-neg.s: Input for test.
* testsuite/gas/arm/org-neg.d: New test.
* testsuite/gas/arm/org-neg.l: Error output for test.
* testsuite/gas/arm/org-neg.s: Input for test.
These failures were caused by the PDP11's mix of little-endian octets
in shorts but shorts in big endian order for long or quad so regexps
did not match. Also tests used addresses as values in .long which
required BRD_RELOC_32 that was not implemented.
* gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad
* gas/testsuite/gas/all/gas.exp: Select alternate test scripts for
pdp11, skip octa test completely.
* gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
* gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
* gas/testsuite/gas/all/cond-pdp11.l: Match different octet order.
* bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of
addreses in .long (used in testsuites) and .stab values.
PR gas/26001
* gas/config/tc-pdp11.c (parse_reg): Distinguish register names from
symbols that begin with a register name.
* gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
* gas/testsuite/gas/pdp11/pr26001.s: Likewise.
* gas/testsuite/gas/pdp11/pr26001.d: Likewise.
The next pointer of struct riscv_csr_extra was not always initilized
to NULL or a valid pointer, causing the assembler to attempt to read
through an uninitialized pointer on startup.
gas/ChangeLog:
* config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
pointer when creating struct riscv_csr_extra.
Accept vector alignment hints on z13 although they are ignored there.
The advantage is that any binary compiled for architecture level z13 may
run on z14 or later and benefit from vector alignment hints.
gas/ChangeLog:
2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
load/store instruction variants with alignment hints.
* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
instruction variants with alignment hints.
opcodes/ChangeLog:
2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* s390-opc.txt: Relocate vector load/store instructions with
additional alignment parameter and change architecture level
constraint from z14 to z13.
opcode/crx.h has
typedef enum
{
...
MAX_REG
}
reg;
typedef enum
{
c0 = MAX_REG,
}
copreg;
tc-crx.c has
static int
getreg_image (reg r)
{
...
/* Check whether the register is in registers table. */
if (r < MAX_REG)
rreg = &crx_regtab[r];
/* Check whether the register is in coprocessor registers table. */
else if (r < (int) MAX_COPREG)
rreg = &crx_copregtab[r-MAX_REG];
}
Change getreg_image's argument type to int and replace fragP->fr_literal
with &fragP->fr_literal[0] to silence GCC 10 warning.
PR gas/26044
* config/tc-crx.c (getreg_image): Change argument type to int.
(md_convert_frag): Replace fragP->fr_literal with
&fragP->fr_literal[0].
The frag code makes a distinction between inserting frags before the frag
chains are chained together and afterward. After chaining, we need to set
now_seg before creating the frag. tc-xtensa.c has a function called
fix_new_exp_in_seg that handles this right, but switches segments twice each
time it is called. In this case, we can inline it and pull the save and
restore out of the loop to get better code.
gas/
PR 26025
* config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
asection to segT. New locals seg and subseg. Call subseg_set before
fix_new_exp. Call subseg_set after loop to restore original values.
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
* write.c (write_contents): Use bfd_get_filename rather than
accessing bfd->filename directly. Use bfd_section_name rather
than accessing section->name directly.
sy_resolving ought to not be set for a struct local_symbol, but it is
apparent from local_symbol_make that the field is not initialised.
* symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK
before looking at add_symbol->sy_flags.sy_resolving.
This patch fixes a bug in GAS where the assembler enters a tight loop
when attempting to resolve recursively-defined symbols, e.g. when
trying to assemble "a=a".
This is a regression introduced between binutils 2.32 and 2.33,
by commit 1903f1385b
* symbols.c (struct local_symbol): Update comment.
(resolve_symbol_value): For resolved symbols equated to other
symbols, verify that the referenced symbol is not a local_symbol
before accessing sy_value. Don't leave symbol loops during
finalize_syms resolution.
* testsuite/gas/all/assign-bad-recursive.d: New test.
* testsuite/gas/all/assign-bad-recursive.l: Error output for test.
* testsuite/gas/all/assign-bad-recursive.s: Assembly for test.
* testsuite/gas/all/gas.exp: Run it.
opcodes/
* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
gas/
* testsuite/gas/ppc/byte_rev.d,
* testsuite/gas/ppc/byte_rev.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
opcodes/
* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
gas/
* testsuite/gas/ppc/power10.s: New test.
* testsuite/gas/ppc/power10.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
binutils* dwarf.c (do_checks): New global variable.
(display_formatted_table): Warn about an unexpected number of
columns in the table, if checks are enabled. Do not complain
about the lack of data following the number of entries in the
table if the table is empty.
(display_debug_lines_decoded): Only warn about an unexpected
number of columns in a table if checks are enabled.
* dwarf.h (do_checks): Add a prototype.
* elfcomm.c (error): Remove weak attribute.
(warn): Likewise.
* readelf.c (do_checks): Delete.
(warn): Delete.
(process_section_headers): Only warn about empty sections if
checks are enabled.
gas * dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
construction of a DWARF-5 directory name table.
* testsuite/gas/elf/pr25917.d: Update expected output.
PR 25917
* dwarf.c (display_debug_lines_decoded): Warn if encountering a
supicious number of entries for DWARF-5 format directory and file
name tables. Do not display file name table header if the table
is empty. Do not allocate space for empty tables.
This fixes PR 25863 by fixing the condition in the parsing of vmul in
do_mve_vmull. It also simplifies the code in there fixing latent issues that
would lead to NEON code being accepted when it shouldn't.
gas/ChangeLog:
2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25863
* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
PR 25917
* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
table's existence before looking at its entries.
* testsuite/gas/elf/pr25917.s: New test source file.
* testsuite/gas/elf/pr25917.d: New test driver.
* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
Starting with RH.0 release Xtensa ISA adds immediate parameter to
simcall opcode. For assembly source compatibility treat "simcall"
instruction without parameter as "simcall 0" when parameter is required.
2020-04-29 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0
if it's not defined.
(microarch_earliest): New static variable.
(xg_translate_idioms): Translate "simcall" to "simcall 0" when
simcall opcode has mandatory parameter.
(xg_init_global_config): Initialize microarch_earliest.
PR 22699
opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
IMM0_8U case.
gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
IMM0_8S and add support for IMM0_8U.
* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
unsigned 8-bit immediate.
* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago. The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.
However the 32-bit version of bfd never got support for this. The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.
This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.
This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.
bfd/ChangeLog:
* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
to x86_64_pe_big_vec as it not a big-endian format.
(vec i386_pe_big_vec): New.
* configure.ac: Likewise.
* targets.c: Likewise.
* configure: Regenerate.
* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
COFF_WITH_PE_BIGOBJ): New.
* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
New.
(x86_64_pe_be_vec): Moved.
gas/ChangeLog:
* NEWS: Add news entry for big-obj.
* config/tc-i386.c (i386_target_format): Support new format.
* doc/c-i386.texi: Add i386 support.
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
ld/ChangeLog:
* pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
PR 25878
* dwarf2dbg.c (struct file_entry): Add auto_assigned field.
(assign_file_to_slot): New function. Fills in an entry in the
files table.
(allocate_filenum): Use new function.
(allocate_filename_to_slot): Use new function. If the specified
slot entry is already in use, but was chosen automatically then
reassign the automatic entry.
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
symbol for ".symver .. remove".
* doc/as.texi (.symver): Update.
* testsuite/gas/symver/symver11.s: Make foo weak.
* testsuite/gas/symver/symver11.d: Expect an error.
* testsuite/gas/symver/symver7.d: Allow other random symbols.
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand. This restriction has only been lifted for
the MC68020+ and CPU32.
opcodes:
PR 25848
* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
cmpi only on m68020up and cpu32.
gas:
PR 25848
* testsuite/gas/m68k/operands.s: Add tests for cmpi.
* testsuite/gas/m68k/operands.d: Update.
* testsuite/gas/m68k/op68000.d: Update for new error messages.
The check in bfd_get_full_section_contents is trying to check that we don't
allocate more space for a section than the size of the section is on disk.
Previously we excluded linker created sections since they didn't have a size on
disk. However we also need to exclude sections with no content as well such as
the BSS section. Space for these would not have been allocated by the assembler
and so the check would incorrectly fail.
bfd/ChangeLog:
PR binutils/24753
* compress.c (bfd_get_full_section_contents): Exclude sections with no
content.
gas/ChangeLog:
PR binutils/24753
* testsuite/gas/arm/pr24753.d: New test.
* testsuite/gas/arm/pr24753.s: New test.
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:
.symver foo, foo@VERS_1, local # Change foo to a local symbol.
.symver foo, foo@VERS_2, hidden # Change foo to a hidden symbol.
.symver foo, foo@@VERS_3, remove # Remove foo from symbol table.
.symver foo, bar@V1 # Assign foo to bar@V1 and baz@V2.
.symver foo, baz@V2
PR gas/23840
PR gas/25295
* NEWS: Mention .symver extension.
* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
function.
(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
add a version name. Add local, hidden and remove visibility
support.
(elf_frob_symbol): Handle the list of version names. Update the
original symbol to local, hidden or remove it from the symbol
table.
(elf_frob_file_before_adjust): Handle the list of version names.
* config/obj-elf.h (elf_visibility): New.
(elf_versioned_name_list): Likewise.
(elf_obj_sy): Change local to bitfield. Add rename, bad_version
and visibility. Change versioned_name pointer to struct
elf_versioned_name_list.
* doc/as.texi: Update .symver directive.
* testsuite/gas/symver/symver.exp: Run all *.d tests. Add more
error checking tests.
* testsuite/gas/symver/symver6.d: New file.
* testsuite/gas/symver/symver7.d: Likewise.
* testsuite/gas/symver/symver7.s: Likewise.
* testsuite/gas/symver/symver8.d: Likewise.
* testsuite/gas/symver/symver8.s: Likewise.
* testsuite/gas/symver/symver9.s: Likewise.
* testsuite/gas/symver/symver9a.d: Likewise.
* testsuite/gas/symver/symver9b.d: Likewise.
* testsuite/gas/symver/symver10.s: Likewise.
* testsuite/gas/symver/symver10a.d: Likewise.
* testsuite/gas/symver/symver10b.d: Likewise.
* testsuite/gas/symver/symver11.d: Likewise.
* testsuite/gas/symver/symver11.s: Likewise.
* testsuite/gas/symver/symver12.d: Likewise.
* testsuite/gas/symver/symver12.s: Likewise.
* testsuite/gas/symver/symver13.d: Likewise.
* testsuite/gas/symver/symver13.s: Likewise.
* testsuite/gas/symver/symver14.d: Likewise.
* testsuite/gas/symver/symver14.l: Likewise.
* testsuite/gas/symver/symver15.d: Likewise.
* testsuite/gas/symver/symver15.l: Likewise.
* testsuite/gas/symver/symver6.l: Removed.
* testsuite/gas/symver/symver6.s: Updated.
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_barrier_psb): Update error messages
to include TSB.
* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
* testsuite/gas/aarch64/system.d: Update.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_none): New.
* aarch64-asm.h (ins_none): New declaration.
* aarch64-dis.c (aarch64_ext_none): New.
* aarch64-dis.h (ext_none): New declaration.
* aarch64-opc.c (aarch64_print_operand): Update case for
AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
(AARCH64_OPERANDS): Update inserter/extracter for
AARCH64_OPND_BARRIER_PSB to use new dummy functions.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Cui,Lili
Jan Beulich
Alan Modra
Max Filippov
H.J. Lu
Nelson Chu
Seth Girvan
Alex Coplan
Nick Clifton
Jose E. Marchesi
Stephen Casner
Jim Wilson
Simon Cook
Stefan Schulze Frielinghaus
Peter Bergner
Alexander Fedotov
Alan Modra
liuhongt
Gunther Nikl
Andre Simoes Dias Vieira
Yoshinori Sato
Tamar Christina
Andreas Schwab
Sudakshina Das