While actually starting to use that new directive, I noticed a few
oversights of the original commit.
gas/
2015-02-06 Jan Beulich <jbeulich@suse.com>
* dw2gencfi.c (select_cie_for_fde): Also bail on CFI_label.
(cfi_change_reg_numbers): Also do nothing for CFI_label.
(cfi_pseudo_table): Also handle .cfi_label when not supporting
CFI directives.
gcc-5 correctly complains "loop exit may only be reached after
undefined behavior". I was going to correct this by checking the
index before dereferencing the array rather than the other way around,
but then I noticed it is possible for extract_cmd to write the
terminating zero one past the end of "cmd". Fixing that means no
index check is needed in md_assemble.
* config/tc-msp430.c (md_assemble): Correct size passed to
extract_cmd. Remove index check.
Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end
of section.
gas/
* read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}.
* write.c (get_frag_for_reloc): Allow match just past end of frag.
gas/testsuite/
* gas/all/none.s,
* gas/all/none.d: New test.
* gas/all/gas.exp: Run it.
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
registers for scalar operations)
- vector string instructions
gas/ChangeLog:
* config/tc-s390.c (struct pd_reg): Remove.
(pre_defined_registers): Remove.
(REG_NAME_CNT): Remove.
(reg_name_search): Calculate the register number instead of doing
a lookup.
(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
reg_name_search signature.
(s390_parse_cpu): Support the new arch string z13.
(s390_insert_operand): Support for vector registers with the extra
field for the fifth bit of each vector register operand.
(md_gather_operand): Adjust to the new handling of optional
parameters.
* doc/as.texinfo: Document the z13 cpu string.
gas/testsuite/ChangeLog:
* gas/s390/esa-g5.d: Add a variant without the optional operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z10.d: For variants with a zero optional argument
it is not dumped by objdump anymore.
* gas/s390/zarch-zEC12.d: Likewise.
* gas/s390/zarch-z13.d: New file.
* gas/s390/zarch-z13.s: New file.
* gas/s390/s390.exp: Run the test for the z13 files.
include/opcode/ChangeLog:
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
ld/testsuite/ChangeLog:
* ld-s390/tlsbin.dd: The nopr register operand is optional and not
printed if 0 anymore.
opcodes/ChangeLog:
* s390-dis.c (s390_extract_operand): Support vector register
operands.
(s390_print_insn_with_opcode): Support new operands types and add
new handling of optional operands.
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
and include opcode/s390.h instead.
(struct op_struct): New field `flags'.
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
(dumpTable): Dump flags.
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
string.
* s390-opc.c: Add new operands types, instruction formats, and
instruction masks.
(s390_opformats): Add new formats for .insn.
* s390-opc.txt: Add new instructions.
When runtime patching code (like e.g. done by the Linux kernel) there
may be cases where the set of stack frame alterations differs between
unpatched and patched code. Consequently the corresponding unwind data
needs patching too. Locating the right places within an FDE, however,
is rather cumbersome without a way to insert labels in the resulting
section. Hence this patch introduces a new directive, .cfi_label. Note
that with the way CFI data gets emitted currently (at the end of the
assembly process) this can't support local FB- and dollar-labels.
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New.
(cfi_pseudo_table): Add "cfi_label".
(output_cfi_insn): Handle CFI_label.
(select_cie_for_fde): Als terminate CIE when encountering
CFI_label.
* dw2gencfi.h (cfi_add_label): Declare.
(struct cfi_insn_data): New member "sym_name".
(CFI_label): New.
* read.c (read_symbol_name): Drop "static".
* read.h (read_symbol_name): Declare.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New.
gas/cfi/cfi.exp: Run new tests.
These two, other than VQSHLU, didn't have their immediates properly range
checked so far.
(Re-sending unchanged from the original v2 due to never having got an
answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.)
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range.
(do_neon_qshl_imm): Likewise.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for invalid VSHL,
VQSHL, and VQSHLU immediates.
* gas/arm/neon-addressing-bad.l: Update accordingly.
The C standard doesn't guarantee a function pointer can be cast to
void* and vice versa.
binutils/
* prdbg.c (print_debugging_info): Don't use void* for function
pointer param.
* budbg.h (print_debugging_info): Update prototype.
gas/
* read.c (s_altmacro, s_reloc): Make definition static.
When fixups are converted to a difference type within md_apply_fix, we
previously left the contents of VALP (the value that was initially
computed within write.c:fixup_segment) unchanged. This is harmless,
except that this value is used within write.c:fixup_segment once we
return from md_apply_fix to perform an overflow check.
In some cases, the value computed in write.c:fixup_segment is so wrong
that an overflow error can be triggered. These errors are incorrect.
This patch avoids the overflow errors by adjusting the value in
write.c:fixup_segment using the VALP pointer in md_apply_fix.
A test for this issue is included.
gas/ChangeLog:
* config/tc-avr.c (md_apply_fix): Update the contents of VALP for
diff fixups.
gas/testsuite/ChangeLog:
* gas/avr/large-debug-line-table.d: New file.
* gas/avr/large-debug-line-table.s: New file.
the X-Gene scheduling description up in the respective GCC backend.
* config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and
X-Gene 2.
* doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
Using e.g.
.arch_extension simd
.arch_extension nocrypto
so far results in SIMD support getting disabled, which I can't see being
the purpose of the "no"-prefixed variants of architecture extension
specifications.
Of course it is questionable whether the current, counter intuitive
behavior needs to be retained, and the new behavior perhaps be made work
through e.g. a newly recognized "no-" prefix.
gas/
2015-01-07 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (struct arm_option_extension_value_table):
Split field "value" into fields "merge_value" and "clear_value".
(arm_extensions): Adjust initializer accordingly.
Adds documentation describing the -mlink-relax and -mno-link-relax
command line options.
gas/ChangeLog:
* doc/c-avr.texi: Document -mlink-relax and -mno-link-relax.
Have the assembler prepare for linker relaxation by default. This
means that users will be able to make use of linker relaxation without
having to adjust the assembler flags, this can make life easier when
compiling libraries.
Having this on by default in the assembler should make no difference to
the assembler code produced, however, some of the debug information will
be slightly less compressed.
A few tests needed to be updated as a result of this change as they
relied on linker relaxation support being off by default.
I've tightened up the definition of which sections can be relaxed on AVR
as part of this commit, the assembler used to think that all
non-debugging sections could be relaxed, when in reality only code
sections can be relaxed for AVR. The previous definition was not
dangerous, just over cautious. The new tighter definition allows an
extra test (gas/testsuite/gas/all/forward.d) to continue to pass.
gas/ChangeLog:
* config/tc-avr.c (struct avr_opt_s): Change link_relax to
no_link_relax, extend comment.
(enum options): Add new OPTION_NO_LINK_RELAX.
(md_longopts): Add entry for -mno-link-relax.
(md_parse_option): Handle OPTION_NO_LINK_RELAX, and update
OPTION_LINK_RELAX.
(md_begin): Initialise linkrelax from no_link_relax.
(md_show_usage): Include -mno-link-relax option.
(relaxable_section): Only allocatable code sections can be
relaxed.
* config/tc-avr.h (TC_LINKRELAX_FIXUP): Define.
gas/testsuite/ChangeLog:
* gas/all/gas.exp: Test will not pass on AVR due to linker
relaxation support.
* gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option.
* gas/avr/link-relax-elf-flag-clear.d: Likewise.
ld/testsuite/ChangeLog:
* ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax
option.
* ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
The AVR target uses a bit in the elf header flags to indicate if the
object was assembled ready for linker relaxation. Previously this flag
was always set, even when the object was not assembled ready for linker
relaxation.
This patch moves setting of the flag into the assembler, and sets it
only when the assembler is preparing the file for linker relaxation.
bfd/ChangeLog:
* elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set
EF_AVR_LINKRELAX_PREPARED unconditionally.
gas/ChangeLog:
* config/tc-avr.c: Add include for elf/avr.h.
(avr_elf_final_processing): New function.
* config/tc-avr.h (elf_tc_final_processing): Define.
(avr_elf_final_processing): Declare
gas/testsuite/ChangeLog:
* gas/avr/link-relax-elf-flag-clear.d: New file.
* gas/avr/link-relax-elf-flag-set.d: New file.
* gas/avr/link-relax-elf-flag.s: New file.
gas/
* config/tc-mips.c (md_apply_fix): Apply alignment check
to the symbol and offset rather than *valP for
BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
for BFD_RELOC_MIPS_19_PCREL_S2.
gas/testsuite/
* gas/mips/r6-64.s: Remove .align directives from LDPC
instructions and add further tests for LDPC.
* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
output and update for new tests.
* gas/mips/r6-64-n64.d: Likewise.
* gas/mips/ldpc-unalign.l: New file.
* gas/mips/ldpc-unalign.s: Likewise.
* gas/mips/mips.exp: Run ldpc-unalign test.
This makes gas .cfi output to .debug_frame match register numbering
emitted by gcc. md_reg_eh_frame_to_debug_frame follows the ABI,
targets not using it, notably Linux, don't.
* config/tc-ppc.h (md_reg_eh_frame_to_debug_frame): Match current
gcc behaviour.
* config/te-aix.h: New file.
* configure.tgt: Use em=aix for powerpc-aix.
For conditional branches that need more than one trampoline to reach its
target assembler couldn't always find suitable trampoline because
post-loop condition check was placed inside the loop, resulting in
premature loop termination. Move check outside the loop.
This fixes the following build errors seen when assembling huge files
produced by gcc:
Error: jump target out of range; no usable trampoline found
Error: operand 1 of 'j' has out of range value '307307'
2014-11-25 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (search_trampolines): Move post-loop
condition check outside the search loop.
gas/testsuite/
* gas/xtensa/trampoline.d: Add expected output for branches.
* gas/xtensa/trampoline.s: Add test case for branches.
gas/
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (md_assemble): Do not consider relaxation.
(md_convert_frag): Test and set target arch attribute accordingly.
(aeabi_set_attribute_string): Turn it into a global function.
* config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
(aeabi_set_public_attributes): Declare it.
gas/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/attr-arch-assumption.d: New file.
* gas/arm/attr-arch-assumption.s: Likewise.
ld/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/tls-longplt-lib.s: Require ARMv6T2.
* ld-arm/tls-longplt.s: Likewise.
* ld-arm/tls-longplt-lib.d: Updated.
* ld-arm/tls-longplt.d: Likewise.
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
Structions with R_X86_64_GOTTPOFF relocation must be encoded with REX
prefix even if it isn't required by destination register. Otherwise
linker can't safely perform IE -> LE optimization.
bfd/
PR ld/17482
* elf64-x86-64.c (elf_x86_64_relocate_section): Update comments
for IE->LE transition.
gas/
PR ld/17482
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for structions with R_X86_64_GOTTPOFF relocation for x32 if needed.
gas/testsuite/
PR ld/17482
* gas/i386/ilp32/x32-tls.d: New file.
* gas/i386/ilp32/x32-tls.s: Likewise.
ld/testsuite/
PR ld/17482
* ld-x86-64/tlsie4.dd: Updated.
bfd/
* elfxx-mips.c (update_mips_abiflags_isa): Add E_MIPS_ARCH_32R6
and E_MIPS_ARCH_64R6 support.
ld/testsuite/
* ld-mips-elf/abiflags-strip10-ph.d: New file.
* ld-mips-elf/mips-eld.exp: Run the new test.
gas/
* config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6
and INSN_ISA64R6 support.
gas/testsuite/
* gas/mips/elf_arch_mips32r6.d: New file.
* gas/mips/elf_arch_mips64r6.d: New file.
* gas/mips/mips.exp: Run the new tests.
obstack_next_free is supposed to return a void* rather than the char*
it does currently, so expressions involving pointer arithmetic need
a cast. Avoid the issue.
* config/tc-d10v.c (find_opcode): Call frag_now_fix_octets rather
than equivalent obstack_next_free expression.
* config/tc-d30v.c (find_format): Likewise.
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
2014-10-21 Andrew Pinski <apinski@cavium.com>
* config/tc-aarch64.c (aarch64_cpus):
Add thunderx.
* doc/c-aarch64.texi: Document that thunderx
is a valid processor name.
fixed part of a fragment for output generation only, which required
MAX_MEM_FOR_RS_ALIGN_CODE to be large enough to hold the maximum pad.
* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
* config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle
large alignments with a constant fragment size of
MAX_MEM_FOR_RS_ALIGN_CODE.
This makes sure `HAVE_CODE_COMPRESSION' evaluates correctly when the
`.insn' directive is used at the beginning of a source file before any
instructions have been produced and that ELF file header's MIPS16 and
microMIPS ASE flags are set correctly in the case where no instructions
have been produced other than with the said directive.
gas/
* config/tc-mips.c (s_insn): Set file options.
gas/testsuite/
* gas/mips/insn-opts.d: New test.
* gas/mips/insn-opts.s: New test source.
* gas/mips/mips.exp: Run the new test.
The construct being added to the cond.s test case otherwise triggered
both the "missing closing ..." and the "stray ..." (twice) warnings in
_find_end_of_line(). As that code fragments suggests, this is needed to
support (include) files that can be used for both assembler .include
and compiler #include directives.
Asserting "idx" to be non-negative when subsequent code handles this
case is bogus. In fact the assertion triggers e.g. when mistakenly
using the arm32 comment character @ following an instruction.
While doing this I also noticed that despite there being local
variables "detail" and "idx", not all places where they could be used
did actually make use of them, so this is being adjusted at once.
Finally, for the code to be slightly more robust, also change
comparisons against -1 to such checking for a (non-)negative value.
The write.c change is to make gas report an error if reg_section
symbols should leak in future. The tc-i386.c change is the real fix.
Note that the error isn't the most helpful, "redefined symbol cannot
be used on reloc", but I'm not inclined to improve what is really an
internal gas error. reg_section symbols shouldn't leak..
gas/
PR 17493
* write.c (adjust_reloc_syms): Don't allow symbols in reg_section
to be reduced to reg_section section symbol.
* gas/config/tc-i386.c (i386_finalize_immediate): Reject all
reg_section immediates.
gas/testsuite/
* gas/i386/inval-equ-2.l: Adjust.
If src contains n or more bytes, strncat() writes n+1 bytes to dest
(n from src plus the terminating null byte). Therefore, the size of
dest must be at least strlen(dest)+n+1.
* config/tc-tic4x.c (md_assemble): Correct strncat size.
Hash lookup is silly when we can attach the line table info directly
to sections instead. Worse, hash lookup fails when we have multiple
sections with the same name.
gas/
* dwarf2dbg.c (all_segs_hash): Delete.
(get_line_subseg): Delete last_seg, last_subseg, last_line_subseg.
Retrieve line_seg for section via seg_info.
* subsegs.h (segment_info_typet): Add dwarf2_line_seg.
gas/testsuite/
* gas/elf/group2.d, * gas/elf/group2.s: New test.
* gas/elf/elf.exp: Run it.
Refactor each relaxation pattern to raise the maintainability.
In origin, all patterns is analysed in nds32_elf_relax_section,
so it is hard to debug and maintain. Therefore, we classify all
patterns into different functions in this patch.
Moreover, we adjust all optimizations into nds32_elf_relax_section
to take these optimizations in turn. This can promise all relaxation
being done after calling gld${EMULATION_NAME}_after_allocation.
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elfn32-mips.c: Likewise.
* elfxx-mips.c (MIPSR6_P): New define.
(mipsr6_exec_plt_entry): New array.
(hi16_reloc_p): Add support for R_MIPS_PCHI16.
(lo16_reloc_p): Add support for R_MIPS_PCLO16.
(aligned_pcrel_reloc_p): New function.
(mips_elf_relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(mips_elf_calculate_relocation): Add support for relocs:
R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
R_MIPS_PCHI16 and R_MIPS_PCLO16.
(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(_bfd_mips_elf_relocate_section): Add a check for unaligned
pc relative relocs.
(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
plt entry.
(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
(mips_32bit_flags_p): Add support for mips32r6.
* libbfd.h (bfd_reloc_code_real_names): Add entries for
BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
binutils/
* readelf.c (get_machine_flags): Add support for mips32r6 and
mips64r6.
elfcpp/
* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
gas/
* config/tc-mips.c (mips_nan2008): New static global.
(mips_flag_nan2008): Removed.
(LL_SC_FMT): New define.
(COP12_FMT): Updated.
(ISA_IS_R6): New define.
(ISA_HAS_64BIT_REGS): Add mips64r6.
(ISA_HAS_DROR): Likewise.
(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_LEGACY_NAN): New define.
(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
(mips_ase): Add field rem_rev.
(mips_ases): Updated to add which ISA an ASE was removed in.
(mips_isa_rev): Add support for mips32r6 and mips64r6.
(mips_check_isa_supports_ase): Add support to check if an ASE
has been removed in the specified MIPS ISA revision.
(validate_mips_insn): Skip '-' character.
(macro_build): Likewise.
(mips_check_options): Prevent R6 working with fp32, mips16,
micromips, or branch relaxation.
(file_mips_check_options): Set R6 floating point registers to
64 bit. Also deal with the nan2008 option.
(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(match_check_prev_operand): New static function.
(match_same_rs_rt_operand): New static function.
(match_non_zero_reg_operand): New static function.
(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(insns_between): Added case to deal with forbidden slots.
(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
and BFD_RELOC_MIPS_26_PCREL_S2.
(match_insn): Add support for operands -A, -B, +' and +". Also
skip '-' character.
(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
(md_parse_option): Add support for mips32r6 and mips64r6. Also
update the nan option handling.
(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2.
(mips_force_relocation): Prevent forced relaxation for MIPS r6.
(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(s_mipsset): Add support for mips32r6 and mips64r6.
(s_nan): Update to support the new nan2008 framework.
(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(mips_elf_final_processing): Updated to use the mips_nan2008.
(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
macros for R6.
(mips_fix_adjustable): Make PC relative R6 relocations relative
to the symbol and not the section.
* configure.ac: Add support for mips32r6 and mips64r6.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
non-supported instructions from being tested.
* gas/mips/24k-triple-stores-2.s: Likewise.
* gas/mips/24k-triple-stores-3.s: Likewise.
* gas/mips/24k-triple-stores-6.s: Likewise.
* gas/mips/beq.s: Likewise.
* gas/mips/eva.s: Likewise.
* gas/mips/ld-zero-3.s: Likewise.
* gas/mips/mips32-cp2.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/add.s: Don't test the add instructions if r6, and
add padding.
* gas/mips/add.d: Check for a triple dot not a nop at the end of the
disassembly output.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
* gas/mips/mipsr6@add.d: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
* gas/mips/mipsr6@beq.d: New file.
* gas/mips/mipsr6@bge.d: New file.
* gas/mips/mipsr6@bgeu.d: New file.
* gas/mips/mipsr6@blt.d: New file.
* gas/mips/mipsr6@bltu.d: New file.
* gas/mips/mipsr6@branch-misc-1.d: New file.
* gas/mips/mipsr6@branch-misc-2-64.d: New file.
* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
* gas/mips/mipsr6@branch-misc-4-64.d: New file.
* gas/mips/mipsr6@cache.d: New file.
* gas/mips/mipsr6@eva.d: New file.
* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
* gas/mips/mipsr6@jal-svr4pic.d: New file.
* gas/mips/mipsr6@ld-zero-2.d: New file.
* gas/mips/mipsr6@ld-zero-3.d: New file.
* gas/mips/mipsr6@loc-swap-dis.d: New file.
* gas/mips/mipsr6@mips32-cp2.d: New file.
* gas/mips/mipsr6@mips32-imm.d: New file.
* gas/mips/mipsr6@mips32.d: New file.
* gas/mips/mipsr6@mips32r2.d: New file.
* gas/mips/mipsr6@mips4-fp.d: New file.
* gas/mips/mipsr6@mips4-fp.l: New file.
* gas/mips/mipsr6@mips4-fp.s: New file.
* gas/mips/mipsr6@mips4.d: New file.
* gas/mips/mipsr6@mips5-fp.d: New file.
* gas/mips/mipsr6@mips5-fp.l: New file.
* gas/mips/mipsr6@mips5-fp.s: New file.
* gas/mips/mipsr6@mips64.d: New file.
* gas/mips/mipsr6@msa-branch.d: New file.
* gas/mips/mipsr6@msa.d: New file.
* gas/mips/mipsr6@pref.d: New file.
* gas/mips/mipsr6@relax-swap3.d: New file.
* gas/mips/r6-64-n32.d: New file.
* gas/mips/r6-64-n64.d: New file.
* gas/mips/r6-64-removed.l: New file.
* gas/mips/r6-64-removed.s: New file.
* gas/mips/r6-64.s: New file.
* gas/mips/r6-attr-none-double.d: New file.
* gas/mips/r6-n32.d: New file.
* gas/mips/r6-n64.d: New file.
* gas/mips/r6-removed.l: New file.
* gas/mips/r6-removed.s: New file.
* gas/mips/r6.d: New file.
* gas/mips/r6.s: New file.
* gas/mips/mipsr6@mips32-dsp.d: New file.
* gas/mips/mipsr6@mips32-dspr2.d: New file.
* gas/mips/mipsr6@mips32r2-ill.l: New file.
* gas/mips/mipsr6@mips32r2-ill.s: New file.
* gas/mips/cache.s: Add r6 instruction varients.
* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
architectures. Also prevent non r6 supported tests from running.
Finally, add in support for running the new r6 tests.
(run_dump_test_arch): Add support for mipsr6 tests.
(run_list_test_arch): Add support for using files of the
form arch@testname.l .
include/elf/
* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(E_MIPS_ARCH_32R6): New define.
(E_MIPS_ARCH_64R6): New define.
include/opcode/
* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+I, +O, +R, +:, +\, +", +;
(mips_check_prev_operand): New struct.
(INSN2_FORBIDDEN_SLOT): New define.
(INSN_ISA32R6): New define.
(INSN_ISA64R6): New define.
(INSN_UPTO32R6): New define.
(INSN_UPTO64R6): New define.
(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
(ISA_MIPS32R6): New define.
(ISA_MIPS64R6): New define.
(CPU_MIPS32R6): New define.
(CPU_MIPS64R6): New define.
(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
ld/
* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
opcodes/
* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
mips64r6.
(parse_mips_dis_option): Allow MSA and virtualization support for
mips64r6.
(mips_print_arg_state): Add fields dest_regno and seen_dest.
(mips_seen_register): New function.
(print_insn_arg): Refactored code to use mips_seen_register
function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
the register rather than aborting.
(print_insn_args): Add length argument. Add code to correctly
calculate the instruction address for pc relative instructions.
(validate_insn_args): New static function.
(print_insn_mips): Prevent jalx disassembling for r6. Use
validate_insn_args.
(print_insn_micromips): Use validate_insn_args.
all the arguments are valid.
* mips-formats.h (PREV_CHECK): New define.
* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
(RD_pc): New define.
(FS): New define.
(I37): New define.
(I69): New define.
(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
MIPS R6 instructions from MIPS R2 instructions.
This patch fixes two related problems:
- By default gas is supposed to bump the current architecture
(starting with v6) as it finds "higher" instructions as the
assembling progresses. There are four possible cases depending on
the usage of the -A and -bump options:
(a) No -A and -bump are specified. In this case max_architecture
must be the highest architecture not conflicting with the
default architecture. The default opcode architecture is
indirectly set in configure.tgt and is "v9" in sparc64 systems
(from "v9-64"). Thus the maximum architecture in sparc64
systems must be "v9b". No warnings are echoed when the assembly
of an instruction bumps the current architecture.
(b) Only -bump is specified. This is like (a) but warnings are
always issued when the assembly of an instruction bumps the
current architecture.
(c) Only -A is specified. In this case bumping to a new
architecture is an error.
(d) Both -A and -bump are specified. In this case max_architecture
must be the highest architecture not conflicting with the
default architecture, but warnings are only to be issued when
bumping to an architecture higher than the architecture selected
in the -A option.
`max_architecture' is a global variable defined in tc-sparc.c which
is initialized to the opcode architecture corresponding to the
default architecture ("sparclite" for sparc-* targets and "v9" for
sparc64-* targets). Then in `md_begin' it is set to the highest
non-conflicting architecture, but only when both -A and -bump are
specified.
Thus (a) does not work:
$ echo "fzero %f0" | as
{standard input}: Assembler messages:
{standard input}:1: Error: Architecture mismatch on "fzero".
{standard input}:1: (Requires v9a|v9b; requested architecture is v9.)
Neither (b):
$ echo "fzero %f0" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Error: Architecture mismatch on "fzero".
{standard input}:1: (Requires v9a|v9b; requested architecture is v9.)
Only (d) does:
$ echo "fzero %f0" | as -Av9 -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9a" on "fzero"
This patch fixes that function to "upgrade" `max_architecture' also
in the (a) and (b) cases.
Note that this problem becomes apparent only in sparc64-* targets
because in sparc-* targets the default architecture is the "higher"
among the 32bit architectures ("sparclite").
- Gas maintains a set of hardware capabilities associated with each
gas architecture, in `sparc_arch_table'. On the other hand
libopcodes maintains a set of hardware capabilities needed by each
individual sparc instruction.
When an instruction is assembled in `sparc_ip' gas checks for the
presence of the hardware capabilities required by the instruction,
emitting an error if some capability is missing.
However, this mechanism does not work properly if the current
architecture is bumped due to an instruction requiring new hw
capabilities not present on either the default architecture or an
architecture specified with -A:
$ echo "fzero %f0" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9a" on "fzero"
{standard input}:1: Error: Hardware capability "vis" not enabled for "fzero".
This patch fixes this by adding the set of required hw caps of an
instruction if it triggers an architecture bump.
The patch has been tested in sparc64-unknown-linux-gnu.
gas/ChangeLog:
2014-09-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Update the set of allowed hwcaps
when bumping the current architecture.
(md_begin): Adjust the highetst architecture level also when a
specific architecture is not requested.
gas/
* config/tc-arm.c (aeabi_set_public_attributes): Update intended_arch based
on the info we got during parsing.
(arm_handle_align): Make sure the p2align expanding logic under thumb
unchanged.
gas/testsuite/
* gas/arm/blx-bl-convert.d: New testcase.
* gas/arm/blx-bl-convert.l: Warning expectation.
* gas/arm/blx-bl-convert.s: Source file.
This change removes code duplication for the SAA macro in line with other
such macros and also adds a !microMIPS internal consistency guard as
there's no microMIPS encoding of the underlying SAA/SAAD instructions.
* config/tc-mips.c (macro) <M_SAA_AB>: Remove duplicate code and
jump to...
<M_SAAD_AB>: ... here. Assert that !microMIPS.
Only set the VLE flag if the instruction has been pulled via the VLE
instruction set. This way the flag is guaranteed to be set for VLE-only
instructions or for VLE-only processors, however it'll remain clear for
dual-mode instructions on dual-mode and, more importantly, standard-mode
processors.
gas/
* config/tc-ppc.c (md_assemble): Only set the PPC_APUINFO_VLE
flag if both the processor and opcode flags match.
ld/testsuite/
* ld-powerpc/apuinfo-vle.rd: New test.
* ld-powerpc/apuinfo-vle.s: New test source.
* ld-powerpc/apuinfo.rd: Adjust according to GAS PPC_APUINFO_VLE
handling change.
* ld-powerpc/powerpc.exp: Run the new test.
cc1: warnings being treated as errors
.../gas/config/tc-arm.c: In function 'add_to_lit_pool':
.../gas/config/tc-arm.c:3193: error: 'imm1' may be used uninitialized in this function
* config/tc-arm.c (add_to_lit_pool): Preinitialize `imm1'.
Before FreeBSD-8 there was/is no arm support from the OS side.
FreeBSD-9.x added ARM support but only for the OABI.
From FreeBSD-10 upwards there is EABI support.
* Makefile.am: Add FreeBSD ARM support.
* Mafefile.in: Regenerate.
* configure.tgt: Add FreeBSD ARM support.
* config/te-armfbsdeabi.h: New file.
* config/te-armfbsdvfp.h: Likewise.
Directories that don't use libtool need to add -ldl (on most *nix
hosts) to provide dlopen for libbfd.
config/
* plugins.m4 (AC_PLUGINS): If plugins are enabled, add -ldl to
LIBS via AC_SEARCH_LIBS.
gdb/
* acinclude.m4 (GDB_AC_CHECK_BFD): Don't add -ldl.
* config.in: Regenerate.
sim/ppc/
* configure.ac: Invoke AC_PLUGINS.
* config.in: Regenerate.
and regen lots of configure files.
than 4. This affects DWARF debug info generation in particular.
* config/tc-rl78.c (md_apply_fix): Correct handling of small sized
RELOC_RL78_DIFF fixups.
This also makes --enable-plugins default to on for hosts that can
support plugins, so we have consistent lto toolchain support. The
ACX_LARGEFILE moves aren't strictly necessary, but are harmless and
will be necessary if plugin support is extended to more hosts via
libtool's dlopen support. I started down that path then decided it
was more work than I was interested in doing. (ACX_LARGEFILE invokes
AC_PLUGINS.)
config/
* plugins.m4: Test for dlfcn.h or windows.h here to set default
for --enable-plugins. Report error if someone tries to enable
plugins on a host we don't support.
bfd/
* configure.ac: Delete redundant plugin related checks.
* configure: Regenerate.
binutils/
* configure.ac: Move ACX_LARGEFILE after LT_INIT.
* config.in: Regenerate.
* configure: Regenerate.
gas/
* configure.ac: Move ACX_LARGEFILE after LT_INIT.
* config.in: Regenerate.
* configure: Regenerate.
gprof/
* configure.ac: Move ACX_LARGEFILE after LT_INIT.
* configure: Regenerate.
* gconfig.in: Regenerate.
ld/
* configure.ac: Move AC_PROG_CC and other macros earlier. Delete
plugin checks now done in config/plugins.m4.
* config.in: Regenerate.
* configure: Regenerate.
gas/
* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
include/opcode/
* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
(INSN_LOAD_COPROC): New define.
(INSN_COPROC_MOVE_DELAY): Rename to...
(INSN_COPROC_MOVE): New define.
opcodes/
* micromips-opc.c (COD): Rename throughout to...
(CM): New define, update to use INSN_COPROC_MOVE.
(LCD): Rename throughout to...
(LC): New define, update to use INSN_LOAD_COPROC.
* mips-opc.c: Likewise.
* gas/configure.tgt (or1k*-*-rtems*): Ensure a match.
(or1k*-*-*): Use or1k* to match or1knd and or1kZ.
Signed-off-by: Christian Svensson <blue@cmd.nu>
Use size_t in a few places involved with obstacks, and don't include
obstack.h in files that don't use obstacks.
gas/
* config/bfin-parse.y: Don't include obstack.h.
* config/obj-aout.c: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-som.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-tic4x.c: Likewise.
* expr.c: Likewise.
* listing.c: Likewise.
* config/obj-elf.c (elf_file_symbol): Make name_length a size_t.
* config/tc-aarch64.c (symbol_locate): Likewise.
* config/tc-arm.c (symbol_locate): Likewise.
* config/tc-mmix.c (mmix_handle_mmixal): Make len_0 a size_t.
* config/tc-score.c (s3_build_score_ops_hsh): Make len a size_t.
(s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
* frags.c (frag_grow): Make parameter a size_t, and use size_t locals.
(frag_new): Make parameter a size_t.
(frag_var_init): Make max_chars and var parameters size_t.
(frag_var, frag_variant): Likewise.
(frag_room): Return a size_t.
(frag_align_pattern): Make n_fill parameter a size_t.
* frags.h: Update function prototypes.
* symbols.c (save_symbol_name): Make name_length a size_t.
gas/
* config/tc-arm.c (add_to_lit_pool): Use "inst.operands[1].imm" for * sign
extension. Casting the type of imm1 and imm2 to offsetT. Fix one logic
error when checking X_op.
gas/
* read.c (assign_symbol): Don't force "set" symbols local for PE.
gas/testsuite/
* gas/pe/set.s, * gas/pe/set.d: New test.
* gas/pe/pe.exp: Run it.
* config/tc-arm.c (literal_pool): New field "alignment".
(find_or_make_literal_pool): Initialize "alignment" to 2.
(s_ltorg): Align the pool using value of "alignment"
(parse_big_immediate): New parameter "in_exp". Return
parsed expression if "in_exp" is not null.
(parse_address_main): Invoke "parse_big_immediate" for
constant parameter.
(add_to_lit_pool): Add one parameter 'nbytes'.
Split 8 byte entry into two 4 byte entry.
Add padding to align 8 byte entry to 8 byte boundary.
(encode_arm_cp_address): Generate literal pool entry if possible.
(move_or_literal_pool): Generate entry for vldr case.
(enum lit_type): New enum type.
(do_ldst): Use new enum type.
(do_ldstv4): Likewise.
(do_t_ldst): Likewise.
(neon_write_immbits): Support Thumb-2 mode.
* gas/arm/ldconst.s: Add test cases for symbol literal.
* gas/arm/ldconst.d: Likewise.
* gas/arm/vldconst.s: Add test cases for vldr.
* gas/arm/thumb2_vpool.s: Likewise.
* gas/arm/vldconst.d: New pattern for little-endian.
* gas/arm/thumb2_vpool.d: Likewise.
* gas/arm/vldconst_be.d: New pattern for big-endian.
* gas/arm/thumb2_vpool_be.d: Likewise.
* elf32-avr.c: Handle R_AVR_PORT5 and R_AVR_PORT6.
* reloc.c: Add BFD_RELOC_AVR_PORT5 and BFD_RELOC_AVR_PORT6.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* avr.h: Add R_AVR_PORT5 and R_AVR_PORT6.
* config/tc-avr.c (avr_operand): Permit referring to r26-r31 by
name as [xyz][hl]. Permit using a symbol whoes name begins with
`r' to refer to a register.
Allow arbitrary expressions for the P and p operators.
(md_apply_fix): Check the BFD_RELOC_AVR_PORT5 and
BFD_RELOC_AVR_PORT6 relocations.
This removes usage of the obsolete AC_INIT and AM_INIT_AUTOMAKE in all
binutils configure.in files. The BFD version is now in bfd/version.m4
rather than bfd/configure.in, which allows automake to automatically
track this dependency.
bfd/
* version.m4: New file.
* configure.in: Include version.m4.
(AC_INIT): Update.
* Makefile.am (RELEASE): Delete.
(bfdver.h): Depend on development.sh, use instead of RELEASE.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
opcodes/
* configure.in: Include bfd/version.m4.
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
(BFD_VERSION): Delete.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
* configure: Regenerate.
* Makefile.in: Regenerate.
binutils/
* configure.in: Include bfd/version.m4.
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
(BFD_VERSION): Delete.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
* configure: Regenerate.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
gas/
* configure.in: Include bfd/version.m4.
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
(BFD_VERSION): Delete.
* configure.com: Get bfd version from bfd/version.m4.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
* configure: Regenerate.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
gprof/
* configure.in: Include bfd/version.m4.
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
(BFD_VERSION): Delete.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
* configure: Regenerate.
* Makefile.in: Regenerate.
ld/
* configure.in: Include bfd/version.m4.
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
(BFD_VERSION): Delete.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
* configure: Regenerate.
* Makefile.in: Regenerate.
* archures.c: add avrtiny architecture for avr target.
* bfd-in2.h: Regenerate.
* cpu-avr.c (arch_info_struct): add avrtiny arch info.
* elf32-avr.c (elf_avr_howto_table): new relocation R_AVR_LDS_STS_16
added for 16 bit LDS/STS instruction of avrtiny arch.
(avr_reloc_map): reloc R_AVR_LDS_STS_16 is mapped to
BFD_RELOC_AVR_LDS_STS_16.
(bfd_elf_avr_final_write_processing): select machine number avrtiny arch.
(elf32_avr_object_p): set machine number for avrtiny arch.
* libbfd.h: Regenerate.
* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.
* config/tc-avr.c (mcu_types): Add avrtiny arch.
Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
and attiny40.
(md_show_usage): Add avrtiny arch in usage message.
(avr_operand): validate and issue error for invalid register for avrtiny.
add new reloc exp for 16 bit lds/sts instruction.
(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
(md_assemble): check ISA for arch and issue diagnostic.
* include/elf/avr.h (E_AVR_MACH_AVRTINY): define avrtiny machine number.
(R_AVR_LDS_STS_16): define 16 bit lds/sts reloc number.
* include/opcode/avr.h (AVR_ISA_TINY): define avrtiny specific ISA.
(AVR_ISA_2xxxa): define ISA without LPM.
(AVR_ISA_AVRTINY): define avrtiny arch ISA.
Add doc for contraint used in 16 bit lds/sts.
Adjust ISA group for icall, ijmp, pop and push.
Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
* opcodes/avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
(print_insn_avr): do not select opcode if insn ISA is avrtiny and machine
is not avrtiny.
* Makefile.am (ALL_EMULATION_SOURCES): add avrtiny emulation source.
(eavrtiny.c): add rules for avrtiny emulation source.
* Makefile.in: Regenerate.
* configure.tgt: Add avrtiny to avr target emulations.
* scripttempl/avrtiny.sc: New file.
linker script template for avrtiny arch.
* emulparams/avrtiny.sh: New file.
emulation parameters for avrtiny arch.
* config/obj-macho.c (obj_mach_o_set_symbol_qualifier): Don't set
SYM_MACHO_FIELDS_NOT_VALIDATED after reporting an error.
(obj_mach_o_frob_label): Avoid cascading errors.
(obj_mach_o_frob_symbol): Don't set SYM_MACHO_FIELDS_NOT_VALIDATED.
Add sp increment and decrement to ARMv8 IT block deprecate
pattern.
gas/
* config/tc-arm.c (depr_it_insns): New check for inc/dec sp.
gas/testsuite/
* gas/arm/armv8-a-it-bad.s: New check for inc/dec sp.
* gas/arm/armv8-a-it-bad.l: Likewise.
a syntax error is detected in an optional operand.
* config/tc-aarch64.c (END_OF_INSN): New macro.
(parse_operands): Handle operand given and be in wrong
format when operand is optional.
* gas/aarch64/diagnostic.s: New test patterns.
* gas/aarch64/diagnostic.l: Likewise.
This is to fix unitialised memory access when printing listings.
Many targets don't initialise parts of insn frags or data frags that
have fixups, relying on md_apply_fix to finalise the frag. Which is
fine normally, but means we need to run write_object_file after
errors, for listings. Otherwise MALLOC_PERTURB_=1 causes errors like:
x86_64-linux +FAIL: i386 mpx-inval-1
x86_64-linux +FAIL: i386 inval-equ-1
x86_64-linux +FAIL: i386 x86-64-mpx-inval-1
Running write_object_file after errors requires some tweaking to the
testsuite, since we then get extra errors reported from md_apply_fix.
gas/
* write.h (subsegs_finish): Delete declaration.
* write.c (subsegs_finish): Make static.
(write_object_file): Call subsegs_finish from here. Don't print
warning and error count here..
* as.c (main): ..do so here instead. Remove dead code for "no
object file generated". Split out count strings to better support
internationalisation. Don't call subsegs_finish. Tidy setting of
"keep_it". Run write_object_file even after errors.
(keep_it): Make static.
* config/obj-elf.c (elf_frob_symbol): Remove assert.
(elf_frob_file_before_adjust): Likewise.
gas/testsuite/
* gas/elf/bad-group.s: Use %function.
* gas/elf/bad-group.err: Expect correct line number. Allow
other errors.
* gas/elf/bad-size.err: Allow other errors. Match expected
error somewhat more rigorously.
* gas/i386/reloc32.l: Allow other errors.
* gas/i386/mpx-inval-1.l: Match applied relocs.
* gas/i386/x86-64-mpx-inval-1.l: Likewise, and nop padding.
* gas/i386/x86-64-mpx-inval-2.l: Match nop padding, and allow
other errors.
* gas/macros/dot.s: Use .balign.
* gas/macros/dot.l: Update alignment output.
* gas/symver/symver6.l: Allow other errors.
In particular the_insn.reloc must be initialised, otherwise the early
exit cases for bad opcodes will result in cascading errors if
write_object_file is called after an error.
* config/tc-dlx.c (machine_ip): Move initialisation of the_insn
earlier.
MALLOC_PERTURB_=1 results in "FAIL: c54x macros".
* config/tc-tic54x.c (tic54x_mlib): Don't write garbage past
end of archive to temp file.
(tic54x_start_line_hook): Start scan for parallel on next line,
not one char into next line (which may overrun the buffer).
MALLOC_PERTURB_=1 results in "FAIL: VAX ELF relocations", due to object
file being emitted with uninitialised fields. Since these fields had
RELA relocs the field value won't be used at final link time, so the
problem is only seen in relocatable object files.
This rewrite of md_apply_fix clears all fields with relocs, whereas
before some fields had non-zero values.
gas/
* config/tc-vax.c (md_apply_fix): Rewrite.
(tc_gen_reloc, vax_cons, vax_cons_fix_new): Style: Use NO_RELOC
define rather than the equivalent BFD_RELOC_NONE.
gas/testsuite/
* gas/vax/elf-rel.d: Update.
MALLOC_PERTURB_=1 results in "FAIL: PIC" on arm-vxworks, due to garbage
in words with got relocs.
* config/tc-arm.c (s_arm_elf_cons): Initialise after frag_more.
(md_apply_fix): Delete now unnecessary zeroing for BFD_RELOC_ARM_GOT*
and BFD_RELOC_ARM_TLS* relocs. Simplify BFD_RELOC_8 case.
gas/
* config/tc-cris.c (md_create_long_jump): Follow "short" jump
with a nop rather than leaving uninitialised.
gas/testsuite/
* gas/cris/rd-bkw4v32.d: Update.
There are legitimate reasons to allow a signed value in a cmpli insn
field, for example to test for a "stw r1,lock@sdarel(r13)" instruction
in user code, a kernel might use
subis r3,r3,STW_R1_0R13@ha # subtract off high part
cmplwi r3,lock@sdarel # is low part accessing lock?
Since the lock@sdarel may take a range of -32768 to 32767,
the allowed range of cmpli immediate must be at least [-32768,65535].
bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
insn as a bitfield; Use complain_overflow_bitfield.
* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
opcodes/
* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
gas/
* config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
on unsigned fields. Comment on PPC_OPERAND_SIGNOPT signed fields
in 64-bit mode.
gold/
* powerpc.cc (relocate): Treat field of cmpli insn as a bitfield.
The goal of this patch is to provide an easy way to make
--disable-werror the default when building binutils, or the parts
of binutils that need to get built when building GDB. In development
mode, we want to continue making -Werror the default with GCC.
But, when making releases, I think we want to make it as easy as
possible for regular users to successfully build from sources.
GDB already has this kind of feature to turn -Werror as well as
the use of the libmcheck library. As GDB Release Manager, I take
advantage of it to turn those off after having cut the branch.
I'd like to be able to do the same for the binutils bits. And
perhaps Tristan will want to do the same for his releases too
(not sure, binutils builders might be a little savvier than GDB
builders).
This patch introduces a new file, called development.sh, which
just sets a variable called $development. In our development branches
(Eg. "master"), it's set to true. But setting it to false would allow
us to change the default behavior of various development-related
features to be turned off; in this case, it turns off the use of
-Werror by default (use --enable-werror to turn it back on).
bfd/ChangeLog:
* development.sh: New file.
* warning.m4 (AM_BINUTILS_WARNINGS): Source bfd/development.sh.
Make -Werror the default with GCC only if DEVELOPMENT is true.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add
$(srcdir)/development.sh.
* Makefile.in, configure: Regenerate.
binutils/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
bfd's development.sh.
* Makefile.in, configure: Regenerate.
gas/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
bfd's development.sh.
* Makefile.in, configure: Regenerate.
gold/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): New.
* Makefile.in, configure: Regenerate.
gprof/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
bfd's development.sh.
* Makefile.in, configure: Regenerate.
ld/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
bfd's development.sh.
* Makefile.in, configure: Regenerate.
opcodes/ChangeLog:
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
bfd's development.sh.
* Makefile.in, configure: Regenerate.
gdb/ChangeLog:
* development.sh: Delete.
* Makefile.in (config.status): Adjust dependency on development.sh.
* configure.ac: Adjust development.sh source call.
* configure: Regenerate.
gdb/gdbserver/ChangeLog:
* configure.ac: Adjust development.sh source call.
* Makefile.in (config.status): Adjust dependency on development.sh.
* configure: Regenerate.
Tested on x86_64-linux by building two ways: One with DEVELOPMENT
set to true, and one with DEVELOPMENT set to false. In the first
case, I could see the use of -Werror, while it disappeared in
the second case.
* config/tc-msp430.c (OPTION_WARN_INTR_NOPS): Use y instead of z.
(OPTION_NO_WARN_INTR_NOPS): Use Y instead of Z.
* doc/c-msp430.texi: Update command line option description.
* gas/msp430/bad.d: Use -my not -mz.
* config/obj-elf.h (obj_elf_seen_attribute): Declare.
* config/obj-elf.c (recorded_attribute_info): New structure.
(recorded_attributes): New variable.
(record_attribute, obj_elf_seen_attribute): New functions.
(obj_elf_vendor_attribute): Record which attributes have been seen.
* config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter.
Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1.
(msp430_srcoperand): Store vshift value in operand.
* msp430.h (struct msp430_operand_s): Add vshift field.
* gas/elf/struct.d: Expect extra output from some toolchains.
* gas/symver/symver0.d: Likewise.
* gas/symver/symver1.d: Likewise.
handle a ctoff() pseudo-op when running in RH850 ABI mode.
PR gas/16946
* config/tc-v850.c (handle_ctoff): Generate an error if called
when using the RH850 ABI.
or 64-bit doubles. It also makes the linker complain if the user attempts
to link together binaries with different sized doubles.
* elf32-rl78.c (rl78_elf_merge_private_bfd_data): Complain if
64-bit doubles objects mix with 32-bit doubles objects.
(rl78_elf_print_private_bfd_data): Describe 64-bit doubles flag.
* readelf.c (get_machine_flags): Handle RL78 64-bit doubles flag.
* config/tc-rl78.c (enum options): Add OPTION_32BIT_DOUBLES
and OPTION_64BIT_DOUBLES.
(md_longopts): Add -m32bit-doubles and -m64bit-doubles.
(md_parse_option): Parse -m32bit-doubles and -m64bit-doubles.
(md_show_usage): Show all of the RL78 options.
(rl78_float_cons): New static functions.
(md_pseudo_table): Update handler for "double".
gas/
* config/tc-mips.c (mips_set_options): Rename gp32 to gp throughout.
(HAVE_32BIT_GPRS, HAVE_64BIT_GPRS): Remove. Re-implement via GPR_SIZE.
(HAVE_32BIT_FPRS, HAVE_64BIT_FPRS): Remove. Re-implement via FPR_SIZE.
(GPR_SIZE, FPR_SIZE): New macros. Use throughout.
gas/
* config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
(file_mips_gp32, file_mips_fp32, file_mips_soft_float,
file_mips_single_float, file_mips_isa, file_mips_arch): Merge into
one struct...
(file_mips_opts): Here. New static global. Update throughout.
(mips_opts): Update defaults for gp32 and fp.
R_XTENSA_DIFF relocation offsets are in fact signed. Treat them as such.
Add testcase that examines ld behaviour on R_XTENSA_DIFF relocation
changing sign during relaxation.
2014-05-02 Volodymyr Arbatov <arbatov@cadence.com>
David Weatherford <weath@cadence.com>
Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (relax_section): treat R_XTENSA_DIFF* relocations as
signed.
gas/
* config/tc-xtensa.c (md_apply_fix): mark BFD_RELOC_XTENSA_DIFF*
fixups as signed.
ld/testsuite/
* ld-xtensa/diff_overflow.exp, * ld-xtensa/diff_overflow1.s,
* ld-xtensa/diff_overflow2.s: Add test for DIFF* relocation
signedness and overflow checking.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
The problem was that references to weak function symbols were being
incorrectly biased by definition's offset.
PR gas/16858
* config/tc-i386.c (md_apply_fix): Do not adjust value of
pc-relative fixes against weak symbols.
If there is a a trailing align statement in a code section we may
output data padding with a data mapping followed by a code alignment
with a code mapping. The literal pool may then be output with a code
mapping symbol which will cause it to be endian swapped in a big-endian
configuration. When outputting a literal pool make sure that a data
mapping symbol is output in all cases.
gas/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (s_ltorg): Call make_mapping_symbol
directly instead of mapping_state.
gas/testsuite/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* gas/arm/mapmisc.d: Check literal pool mapping with
a trailing .align statement.
* gas/arm/mapmisc.s: Likewise.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
Linking object files produced by partial linking with link-time
relaxation enabled sometimes fails with the following error message:
dangerous relocation: call8: misaligned call target: (.text.unlikely+0x63)
This happens because no basic block with an XTENSA_PROP_ALIGN flag in the
property table is generated for the first basic block, even if the
.align directive is present.
It was believed that the first frag alignment could be derived from the
section alignment, but this was not implemented for the partial linking
case: after partial linking first frag of a section may become not
first, but no additional alignment frag is inserted before it.
Basic block for such frag may be merged with previous basic block into
extended basic block during relaxation pass losing its alignment
restrictions.
Fix this by always recording alignment for the first section frag.
2014-04-22 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_handle_align): record alignment for the
first section frag.
gas/testsuite/
* gas/xtensa/all.exp: Add test for the first section frag alignment.
* gas/xtensa/first_frag_align.d: First section frag alignment expected
dump.
* gas/xtensa/first_frag_align.s: First section frag alignment test
source.
Check 8 and 16 bit PCREL fixes for overflow, since we bypass the
later overflow checks in write.c. Direct relocs are left alone,
as gcc has been known to take advantage of the silent overflows
when comparing addresses to constant ranges.
The problem was that gcc was generating assembler with missing unwind directives in it,
so that a gas_assert was being triggered. The patch replaces the assert with an error
message.
* config/tc-arm.c (create_unwind_entry): Report an error if an
attempt to recreate an unwind directive is encountered.
(enum options): add OPTION_RMW_ISA for -mrmw option.
(struct option md_longopts): Add mrmw option.
(md_show_usage): add -mrmw option description.
(md_parse_option): Update isa details if -mrmw option specified.
* doc/c-avr.texi: Add doc for new option -mrmw.
* gas/avr/avr.exp: Run new tests.
* gas/avr/rmw.d: Add test for additional ISA support.
* gas/avr/rmw.s: Ditto.
a call to sprintf was being made with a non-constant formatting string.
* config/tc-score.c (s3_parse_pce_inst): Add "%s" parameter to
sprintf in order to avoid a compile time warning.
* config/tc-rl78.c (rl78_op): Issue an error message if a 16-bit
relocation is used on an 8-bit operand or vice versa.
(tc_gen_reloc): Use the RL78_16U relocation for RL78_CODE.
(md_apply_fix): Add support for RL78_HI8, RL78_HI16 and RL78_LO16.
suite of ops. It changes the current section back to the code section of the
current function. This is helpful because the code section may not be .text.
* config/obj-coff-seh.c (obj_coff_seh_code): New function -
switches the current segment back to the code segment recorded
when seh_proc was last invoked.
* config/obj-coff-seh.h (SEH_CMDS): Add seh_code.
It turns out that glibc's sysdeps/powerpc/powerpc64/start.S uses this
feature. :-(
* config/tc-ppc.c (ppc_is_toc_sym): Revert 2014-03-05.
(md_assemble): Likewise. Warn.
This patch adds initial in-gas opcode relaxation for the rl78
backend. Specifically, it checks for conditional branches that
are too far and replaces them with inverted branches around longer
fixed branches.
and %hstick_enable to the Sparc assembler.
* config/tc-sparc.c (hpriv_reg_table): Added entries for
%hstick_offset and %hstick_enable.
* doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
%hstick_enable hyperprivileged registers.
* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
%hstick_enable added.
* gas/sparc/rdhpr.s: Test rd %hstick_offset and %hstick_enable.
* gas/sparc/rdhpr.d: Likewise.
* gas/sparc/wrhpr.s: Test wr %hstick_offset and %hstick_enable.
* gas/sparc/wrhpr.d: Likewise.
* config/tc-arm.c (codecomposer_syntax): New flag that states whether the
CCS syntax compatibility mode is on or off.
(asmfunc_states): New enum to represent the asmfunc directive state.
(asmfunc_state): New variable holding the asmfunc directive state.
(comment_chars): Rename to arm_comment_chars.
(line_separator_chars): Rename to arm_line_separator_chars.
(s_ccs_ref): New function that handles the .ref directive.
(asmfunc_debug): New function.
(s_ccs_asmfunc): New function that handles the .asmfunc directive.
(s_ccs_endasmfunc): New function that handles the .endasmfunc directive.
(s_ccs_def): New function that handles the .def directive.
(tc_start_label_without_colon): New function.
(md_pseudo_table): Added new CCS directives.
(arm_ccs_mode): New function that handles the -mccs command line option.
(arm_long_opts): Added new -mccs command line option.
* config/tc-arm.h (LABELS_WITHOUT_COLONS): New macro.
(TC_START_LABEL_WITHOUT_COLON): New macro.
(tc_start_label_without_colon): Added extern function declaration.
(tc_comment_chars): Define.
(tc_line_separator_chars): Define.
* app.c (do_scrub_begin): Use tc_line_separator_chars, if defined.
* read.c (read_begin): Likewise.
* doc/as.texinfo: Add documentation for the -mccs command line
option.
* doc/c-arm.texi: Likewise.
* doc/internals.texi: Document tc_line_separator_chars.
* NEWS: Mention the new feature.
* gas/arm/ccs.s: New test case.
* gas/arm/ccs.d: New expected disassembly.
2014-03-13 Richard Earnshaw <rearnsha@arm.com>
Jiong Wang <Jiong.Wang@arm.com>
* doc/c-aarch64.texi: Clean up some formatting issues.
(AArch64 Options): Document -mcpu and -march.
(AArch64 Extensions): New node.
bfd/
* peicode.h (pe_ILF_object_p): Adjust, as the version number
has been read.
(pe_bfd_object_p): Also read version number to detect ILF.
* pe-x86_64.c (COFF_WITH_PE_BIGOBJ): Define.
(x86_64pe_bigobj_vec): Define
* coffcode.h (bfd_coff_backend_data): Add _bfd_coff_max_nscns field.
(bfd_coff_max_nscns): New macro.
(coff_compute_section_file_positions): Use unsigned int for
target_index. Compare with bfd_coff_max_nscns.
(bfd_coff_std_swap_table, ticoff0_swap_table, ticoff1_swap_table):
Set a value for _bfd_coff_max_nscns.
(header_bigobj_classid): New constant.
(coff_bigobj_swap_filehdr_in, coff_bigobj_swap_filehdr_out)
(coff_bigobj_swap_sym_in, coff_bigobj_swap_sym_out)
(coff_bigobj_swap_aux_in, coff_bigobj_swap_aux_out): New
functions.
(bigobj_swap_table): New table.
* libcoff.h: Regenerate.
* coff-sh.c (bfd_coff_small_swap_table): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Add value for
_bfd_coff_max_nscns.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coff-rs6000.c (bfd_xcoff_backend_data)
(bfd_pmac_xcoff_backend_data): Likewise.
* coff64-rs6000.c (bfd_xcoff_backend_data)
(bfd_xcoff_aix5_backend_data): Likewise.
* targets.c (x86_64pe_bigobj_vec): Declare.
* configure.in (x86_64pe_bigobj_vec): New vector.
* configure: Regenerate.
* config.bfd: Add bigobj object format for Windows targets.
gas/
* config/tc-i386.c (use_big_obj): Declare.
(OPTION_MBIG_OBJ): Define.
(md_longopts): Add -mbig-obj option.
(md_parse_option): Handle it.
(md_show_usage): Display help for this option.
(i386_target_format): Use bigobj for x86-64 if -mbig-obj.
* doc/c-i386.texi: Document the option.
gas/testsuite/
* gas/pe/big-obj.d, gas/pe/big-obj.s: Add test.
* gas/pe/pe.exp: Add test.
include/coff/
* pe.h (struct external_ANON_OBJECT_HEADER_BIGOBJ): Declare.
(FILHSZ_BIGOBJ): Define.
(struct external_SYMBOL_EX): Declare.
(SYMENT_BIGOBJ, SYMESZ_BIGOBJ): Define.
(union external_AUX_SYMBOL_EX): Declare.
(AUXENT_BIGOBJ, AUXESZ_BIGOBJ): Define.
* internal.h (struct internal_filehdr): Change type
of f_nscns.
that if multiple bignum values are encountered only the most recent is valid.
If such expressions are cached, eg to be emitted into a literal pool later on
in the assembly, then only one expression - the last - will be correct. This
patch fixes the problem for the AArch64 target by caching each bignum value
locally.
PR gas/16688
* config/tc-aarch64.c (literal_expression): New structure.
(literal_pool): Replace exp array with literal_expression array.
(add_to_lit_pool): When adding a bignum cache the big value.
(s_ltorg): When emitting a bignum initialise the global bignum
array from the cached value.
* gas/aarch64/litpool.s: New test case.
* gas/aarch64/litpool.d: Expected disassembly.
This adds support for "func@localentry", an expression that returns the
ELFv2 local entry point address of function "func". I've excluded
dynamic relocation support because that obviously would require glibc
changes.
include/elf/
* ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
bfd/
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* Add BFD_RELOC_PPC64_ADDR64_LOCAL.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @localentry.
(md_apply_fix): Support R_PPC64_ADDR64_LOCAL.
ld/testsuite/
* ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files.
* ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files.
* ld-powerpc/powerpc.exp: Run new test.
elfcpp/
* powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::local, global): Support
R_PPC64_ADDR64_LOCAL.
(Target_powerpc::Relocate::relocate): Likewise.
This patch allows gas to assemble a testcase like
li 3,ext_sym
which oddly was not accepted while the following is OK:
li 3,ext_sym@l
* config/tc-ppc.c (md_assemble): Move code adjusting reloc types
later. Merge absolute and relative branch reloc selection.
Generate 16-bit relocs for most 16-bit insn fields given a
non-constant expression.
The XCOFF assembler does some wierd things with instructions like
`lwz 9,sym(30'. See the comment in md_apply_fix. From an ELF
perspective, it's weird even to magically select a TOC16 reloc
when a symbol is in the TOC/GOT. ELF assemblers generally use
modifiers like @toc to select relocs, so remove this "feature"
for ELF. I believe this was to support gcc -m32 -mcall-aixdesc
but that combination of gcc options has been broken for a long
time.
* config/tc-ppc.c (ppc_is_toc_sym): Remove OBJ_ELF support.
(md_assemble): Don't call ppc_is_toc_sym for ELF.
2014-02-04 Heiher <r@hev.cc>
* elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for
Loongson-3A.
(mips_mach_extensions): Make bfd_mach_mips_loongson_3a an
extension of bfd_mach_mipsisa64r2.
opcodes/
2014-02-04 Heiher <r@hev.cc>
* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
gas/
2014-02-04 Heiher <r@hev.cc>
* config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for
Loongson-3A.
generate warning messages about an instruction that changes the interrupt
state not being followed by a NOP instruction.
* config/msp430/msp430.c: Replace known mcu array with known
msp430 ISA mcu name array.
Accept any name for -mmcu option.
Add -mz option to warn about missing NOP following an interrupt
status change.
(check_for_nop): New.
(msp430_operands): Emit a warning, if requested, when an interrupt
changing instruction is not followed by a NOP.
* doc/c-msp430.c: Document -mz option.
* gas/msp430/bad.d: Add -mz option.
* gas/msp430/bad.s: Add more cases where warnings should be
generated.
* gas/msp430/bad.l: Add expected warning messages.
Don't be clever, calculate the length directly as the difference of
two symbols.
* dwarf2dbg.c (out_debug_line): Correct .debug_line header_length
field for 64-bit dwarf.
For each object, if it has a nonempty .data or .bss section,
emit a symbol that could cause the startup code to selectively
link in the code to initialize those sections.
* config/tc-msp430.c (msp430_section): Always flag data sections,
regardless of -md.
(msp430_frob_section): New. Make sure all sections are noticed if
they have content.
(msp430_lcomm): New. Flag bss if .lcomm is seen.
(msp430_comm): New. Likewise.
(md_pseudo_table): Add them.
* config/tc-msp430.h (msp430_frob_section): Declare.
(tc_frob_section): Define.
New MSP430 MCU parts are being created by TI all the time and the
list is basically always out of date. Instead any name will be
accepted by the -mmcu= command line option. ISA selection is now
based upon the -mcpu= command line option, just as is done for GCC.
gas/ChangeLog
* config/tc-msp430.c (show_mcu_list): Delete.
(md_parse_option): Accept any MCU name. Accept several more
variants for the -mcpu option.
(md_show_usage): Do not call show_mcu_list.
* config/tc-msp430.c (msp430_refsym): New: ".refsym <symbol>"
* doc/c-msp430.texi (MSP430 Directives): Document it.
The purpose of this patch is to provide a way for one object file
to require the inclusion of another object, without having to
allocate space for a .word address reference.
Since regzmm can't be used in AVX2 gather instructions, there is no need
to check regzmm in AVX2 gather assert.
2014-01-22 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* config/tc-i386.c (check_VecOperands): Remove regzmm from AVX2
gather assert.
This is to avoid expressions like: %hi(foo) + 1, which will
not do what you expect. The complex relocations can handle it,
but the internal fixups can't.
The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.
gas/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
for the s32.f64 flavours of VCVT.
gas/testsuite/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
binutils/
* version.c (print_version): Update copyright year to 2014.
gas/
* as.c (parse_args): Update copyright year to 2014.
gold/
* version.cc (print_version): Update copyright year to 2014.
ld/
* ldver.c (ldversion): Update copyright year to 2014.
opcodes/
* i386-gen.c (process_copyright): Update copyright year to 2014.
This removes the last uses of the obsolete VA_* macros from binutils.
All the binutils and bfd changes were tested by rebuilding.
I didn't rebuild the gas change but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* elf32-xtensa.c (vsprint_msg): Don't use old VA_* compatibility
wrappers.
2014-01-07 Tom Tromey <tromey@redhat.com>
* bucomm.c (fatal, non_fatal): Replace obsolete VA_* macros with
stdarg macros.
* dlltool.c (inform): Replace obsolete VA_* macros with stdarg
macros.
* dllwrap.c (inform, warn): Replace obsolete VA_* macros with
stdarg macros.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-tic30.c (debug): Avoid old VA_* compatibility
wrappers.
This removes the last uses of PARAMS from binutils.
The two changes in binutils were tested by rebuilding.
I didn't rebuild the gas change but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* coffgrok.h (coff_ofile): Don't use PARAMS.
* nlmheader.y (strerror): Don't use PARAMS.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-microblaze.h (parse_cons_expression_microblaze): Don't
use PARAMS.
This removes the last use of ANSI_PROTOTYPES in the tree.
It appears in gas.
I didn't even rebuild this but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-xc16x.h: Don't use ANSI_PROTOTYPES.
(OPTION_INTR_NOPS): Define.
(gen_interrupt_nops): Default to FALSE.
(md_parse_opton): Add support for OPTION_INTR_NOPS.
(md_longopts): Add -mn.
(md_show_usage): Add -mn.
(msp430_operands): Generate NOPs for all MCUs not just 430Xv2.
* doc/c-msp430.c: Document -mn.
These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Kyrylo Tkachov
Jan Beulich
Alan Modra
Jiong Wang
Nick Clifton
Jiong Wang
Kuan-Lin Chen
Andreas Krebbel
Andrew Burgess
Philipp Tomsich
Anthony Green
Yaakov Selkowitz
Matthew Fortune
H.J. Lu
Chen Gang
Eric Botcazou
Sandra Loosemore
Max Filippov
Terry Guo
Richard Earnshaw
Igor Zamyatin
Ilya Tocar
Marcus Shawcroft
Naveen H.S
Andrew Pinski
Maciej W. Rozycki
Tristan Gingold
Jose E. Marchesi
Andrew Bennett
Jose E. Marchesi
Jan-Benedict Glaw
Richard Henderson
Kaz Kojima
Joel Sherrill
Andreas Schwab
Barney Stratford
DJ Delorie
Hans-Peter Nilsson
Chris Metcalf
Martin Storsjo
Joel Brobecker
Mike Stump
Richard Sandiford
Kaushik Phata
Volodymyr Arbatov
Will Newton
Christian Svensson
Denis Chertykov
David Weatherford
Daniel Gutson
Yufeng Zhang
Richard Earnshaw
Tristan Gingold
Michael Zolotukhin
Tom Tromey
Roland McGrath
Mike Frysinger