Commit Graph

7716 Commits

Author SHA1 Message Date
Pitchumani Sivanupandi b782c63d52 Assume that the GAS testsuite for the AVR is being run without -mlink-relax specified.
* testsuite/gas/lns/lns.exp: Add avr to list of targets using
	DW_LNS_fixed_advance_pc.
2016-05-03 10:56:30 +01:00
Alan Modra 25771140e2 Provide xmemdup0
and some tidies in as.h

	* as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define.
	(xmemdup0): New inline function.
2016-04-27 17:07:17 +09:30
Maciej W. Rozycki 22522f880a MIPS/GAS: Fix an ISA override not lifting ABI restrictions
Correct a regression introduced with commit 919731affb ("Add MIPS
.module directive") causing code like:

	.set	mips3
	dli	$2, 0x9000000080000000

to fail assembly with the following error message produced:

Error: number (0x9000000080000000) larger than 32 bits

if built with `mips3' selected as the global ISA (e.g. `-march=mips3').
This is because a `.set' directive doing an ISA override does not lift
the ABI restriction on register sizes if the ISA remains unchanged.
Previously the directive always set register sizes from the ISA chosen,
which is what some code expects.  Restore the old semantics then.

	gas/
	* config/tc-mips.c (code_option_type): New enum.
	(parse_code_option): Return status indicating option type.
	(s_mipsset): Update `parse_code_option' call site accordingly.
	Always set register sizes from the ISA with ISA overrides.
	(s_module): Update `parse_code_option' call site.
	* testsuite/gas/mips/isa-override-1.d: New test.
	* testsuite/gas/mips/micromips@isa-override-1.d: New test.
	* testsuite/gas/mips/mips1@isa-override-1.d: New test.
	* testsuite/gas/mips/mips2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
	* testsuite/gas/mips/r3000@isa-override-1.d: New test.
	* testsuite/gas/mips/r3900@isa-override-1.d: New test.
	* testsuite/gas/mips/r5900@isa-override-1.d: New test.
	* testsuite/gas/mips/octeon@isa-override-1.d: New test.
	* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
	* testsuite/gas/mips/isa-override-2.l: New list test.
	* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
	* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
	* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
	* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
	* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
	output.
	* testsuite/gas/mips/isa-override-1.s: New test source.
	* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
	* testsuite/gas/mips/isa-override-2.s: New test source.
	* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
	* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
	* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
	* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-22 01:22:29 +01:00
Trevor Saunders e6c7cdec06 update many old style function definitions
This includes regenerating a bunch of files in opcodes/ with trunk cgen.

gprof/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* basic_blocks.c: Update old style function definitions.
	* cg_arcs.c: Likewise.
	* cg_print.c: Likewise.
	* gen-c-prog.awk: Likewise.
	* gmon_io.c: Likewise.
	* hertz.c: Likewise.
	* hist.c: Likewise.
	* sym_ids.c: Likewise.

bfd/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* cache.c: Update old style function definitions.
	* elf32-m68k.c: Likewise.
	* elf64-mmix.c: Likewise.
	* stab-syms.c: Likewise.

opcodes/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* alpha-dis.c: Regenerate.
	* crx-dis.c: Likewise.
	* disassemble.c: Likewise.
	* epiphany-opc.c: Likewise.
	* fr30-opc.c: Likewise.
	* frv-opc.c: Likewise.
	* ip2k-opc.c: Likewise.
	* iq2000-opc.c: Likewise.
	* lm32-opc.c: Likewise.
	* lm32-opinst.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32r-opc.c: Likewise.
	* m32r-opinst.c: Likewise.
	* mep-opc.c: Likewise.
	* mt-opc.c: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opinst.c: Likewise.
	* tic80-opc.c: Likewise.
	* xc16x-opc.c: Likewise.
	* xstormy16-opc.c: Likewise.

ld/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* emultempl/scoreelf.em: Likewise.

binutils/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* resres.c: Likewise.

gas/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* cgen.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-rl78.c: Likewise.
2016-04-20 07:04:49 -04:00
Andrew Burgess 2533af11ba gas/doc/arc: Add nps400 references into the documentation
Add nps400 to the list of acceptable values for the -mcpu command line
switch, and to the .cpu directive.

I've added an extra cross reference from -mcpu to .cpu to improve
navigation of the documentation.

gas/ChangeLog:

	* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
	-mcpu.  Add cross reference to .cpu directive from -mcpu option.
	(ARC Directives): Add NPS400 to .cpu directive list.
2016-04-20 11:49:18 +01:00
Matthew Wahab 50cc854c48 [AArch64] Support RAS extension for ARMv8 onwards.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.

This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.

gas/
2016-04-20  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "ras".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
	* testsuite/gas/aarch64/armv8-ras-1.d: New.
	* testsuite/gas/aarch64/armv8-ras-1.s: New.
	* testsuite/gas/aarch64/illegal-ras-1.d: New.
	* testsuite/gas/aarch64/illegal-ras-1.s: New.

Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-20 09:31:49 +01:00
Andrew Burgess 537aefaf18 opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands.
There's also a test added into the assembler.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-6.d: New file.
	* testsuite/gas/arc/nps400-6.s: New file.

include/ChangeLog:

	* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
	fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp
	instructions.
	* arc-opc.c (insert_nps_bitop_size): Delete.
	(extract_nps_bitop_size): Delete.
	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
	(extract_nps_qcmp_m3): Define.
	(extract_nps_qcmp_m2): Define.
	(extract_nps_qcmp_m1): Define.
	(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
	(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
	(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
	NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
	NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
	NPS_QCMP_M3.
2016-04-19 22:51:27 +01:00
Andrew Burgess c8f785f220 opcodes/arc: Add more nps instructions
Add dctcp, dcip, dcet, and dcacl instructions.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-4.d: New file.
	* testsuite/gas/arc/nps400-4.s: New file.
	* testsuite/gas/arc/nps400-5.d: New file.
	* testsuite/gas/arc/nps400-5.s: New file.

include/ChangeLog:

	* opcode/arc.h (insn_class_t): Add NET and ACL class.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-04-19 22:50:33 +01:00
Martin Galvan 48eac74cb7 .cfi_remember_state/.cfi_restore_state documentation
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve
	documentation.
2016-04-19 14:39:53 +09:30
Andrew Burgess 644aca26b5 Revert "gas/arc: Make .cpu directive case-insensitive"
This reverts commit 9a452709fe.

This change was committed as obvious, but it has been rightly been
pointed out to me that this change is not obvious, and as such I am
reverting it.

gas/ChangeLog:

	Revert prevous change.
	* config/tc-arc.c (arc_option): Make .cpu directive
	case-sensitive again.
2016-04-17 23:22:15 +01:00
Andrew Burgess 9a452709fe gas/arc: Make .cpu directive case-insensitive
gas/ChangeLog:

	* config/tc-arc.c (arc_option): Make .cpu directive
	case-insensitive.
2016-04-16 16:21:32 +01:00
Andrew Burgess 5e001f26ad gas/arc: Support NPS400 in .cpu directive
gas/ChangeLog:

	* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
2016-04-16 16:19:40 +01:00
Trevor Saunders 92fce9bd7a remove pointless assignment
Presumably this was supposed to be regname[sizeof (regname) - 1] but was typoed
to regname[sizeof (rename) - 1].  However that should be unnecessary because
sprintf should null terminate.  As is this assignment is invalid ISO C because
rename refers to the function rename (), and sizeof on functions is undefined.
In GNU C C the size of functions is 1 so the expression is the same as
regname[0].  The following call to sprintf () clearly will over right that, so
the statement either has no effect or is invalid.  Given that it seems safe to
just remove it.  While we are there correct the size of regname, and switch
from snprintf to sprintf since we know the exact length of the result.

gas/ChangeLog:

2016-04-15  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-mips.c (md_begin): Remove useless assignment.
2016-04-15 21:20:36 -04:00
H.J. Lu 6fd8e7c249 Regenerate Makefile.in/aclocal.m4 automake 1.11.6
bfd/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.
	* doc/Makefile.in: Likewise.

binutils/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.
	* doc/Makefile.in: Likewise.

gas/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.
	* doc/Makefile.in: Likewise.

gold/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.
	* testsuite/Makefile.in: Likewise.

gprof/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.

ld/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.

opcodes/

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.
2016-04-15 16:20:55 -07:00
Alan Modra 05f7541ea7 Fix non-ELF powerpc build breakage
* config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
2016-04-15 23:43:20 +09:30
H.J. Lu 0796a6293f Add missing ChangeLog entry for PR gas/19909 fix 2016-04-15 05:59:16 -07:00
Trevor Saunders 4f2a7b5121 make a few variables static
They are only used in one file, so we might as well restrict there scope to
that file, and theoretically this might slightly improve compilers ability to
optimize usage of these variables.

gas/ChangeLog:

2016-04-14  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-nios2.c (nios2_as_options): Make file static.
	* config/tc-ppc.c (toc_reloc_ypes): Likewise.
	* config/tc-sparc.c (native_op_table): Likewise.
2016-04-14 17:06:26 -04:00
Trevor Saunders 85e53f6272 remove some unused globals
gas/ChangeLog:

2016-04-14  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-m32c.c (M32C_Macros): Remove.
	* config/tc-msp430.c (option_numbers): Likewise.
2016-04-14 16:58:01 -04:00
Andrew Burgess 4b0c052e45 arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".

Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.

There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.

bfd/ChangeLog:

	* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-arc.c: Add 'opcode/arc.h' include.
	(struct arc_relocation_data): Add symbol_name.
	(arc_special_overflow_checks): New function.
	(arc_do_relocation): Use arc_special_overflow_checks, reindent as
	required, add an extra comment.
	(elf_arc_relocate_section): Setup symbol_name in reloc_data.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-3.d: New file.
	* testsuite/gas/arc/nps400-3.s: New file.

include/ChangeLog:

	* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
	* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.

ld/ChangeLog:

	* testsuite/ld-arc/arc.exp: New file.
	* testsuite/ld-arc/nps-1.s: New file.
	* testsuite/ld-arc/nps-1a.d: New file.
	* testsuite/ld-arc/nps-1b.d: New file.
	* testsuite/ld-arc/nps-1b.err: New file.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
	instructions.
	* arc-opc.c (insert_nps_cmem_uimm16): New function.
	(extract_nps_cmem_uimm16): New function.
	(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-04-14 17:16:46 +01:00
Andrew Burgess d105775eea gas/arc: Unify tests run on big/little endian arc assembler
We were running a slightly different set of assembler tests on big and
little endian arc targets.  This commit unifies the set of tests run.

gas/ChangeLog:

	* testsuite/gas/arc/add_s-err.s: Update target pattern.
	* testsuite/gas/arc/warn.s: Likewise.
	* testsuite/gas/elf/elf.exp: Run test for arc.
2016-04-14 13:43:27 +01:00
Nick Clifton 8486501545 Fix copying Solaris binaries with objcopy.
PR target/19938
bfd	* elf-bbfd.h (struct elf_backend_data): New field:
	elf_strtab_flags.
	New field: elf_backend_set_special_section_info_and_link
	* elfxx-target.h (elf_backend_strtab_flags): Define if not already
	defined.
	(elf_backend_set_special_section_info_and_link): Define if not
	already defined.
	(elfNN_bed): Use elf_backend_set_special_section_info_and_link and
	elf_backend_strtab_flags macros to initialise fields in structure.
	* elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS
	being set even if SHF_MERGE is not set.
	(elf_fake_sections): Likewise.
	(section_match): New function.  Matches two ELF sections based
	upon fixed characteristics.
	(find_link): New function.  Locates a section in a BFD that
	matches a section in a different BFD.
	(_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link
	fields of reserved sections.
	(bfd_elf_compute_section_file_positions): Set the flags for the
	.shstrtab section based upon the elf_strtab_flags field in the
	elf_backend_data structure.
	(swap_out_syms): Likewise for the .strtab section.
	* elflink.c (bfd_elf_final_link): Set the flags for the
	.strtab section based upon the elf_strtab_flags field in the
	elf_backend_data structure.
	* elf32-i386.c (elf32_i386_set_special_info_link): New function.
	(elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris
	targets.
	(elf_backend_set_special_section_info_and_link): Define for
	Solaris targets.
	* elf32-sparc.c: Likewise.
	* elf64-x86-64.c: Likewise.

binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the
	string sections possibly having the SHF_STRINGS flag bit set.
	* testsuite/binutils-all/i386/compressed-1c.d: Likewise.
	* testsuite/binutils-all/readelf.s: Likewise.
	* testsuite/binutils-all/readelf.s-64: Likewise.
	* testsuite/binutils-all/x86-64/compressed-1b.d: Likewise.
	* testsuite/binutils-all/x86-64/compressed-1c.d: Likewise.

gas	* testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
	sections possibly having the SHF_STRINGS flag bit set.
	* testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-14 12:04:09 +01:00
Claudiu Zissulescu 1adc8a9a7f [ARC] Fix setting private elf flags when parsing .cpu.
gas/
2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (mach_type_specified_p): Change type to
	bfd_boolean.
	(arc_option): Set private flags when parsing cpu pseudo-op.
	(md_parse_option): Set mach_type_specified_p to TRUE.
2016-04-13 16:48:11 +02:00
Nick Clifton e4449be885 oops - omitted from previous delta. 2016-04-13 15:10:48 +01:00
Nick Clifton accc018020 Fix disassembly of the V850's LD.BU instruction.
PR target/19937
opcode	* v850-opc.c (v850_opcodes): Correct masks for long versions of
	the LD.B and LD.BU instructions.

gas	* testsuite/gas/v850/pr19937.s: New test.
	* testsuite/gas/v850/pr19937.d: New test control file.
	* testsuite/gas/v850/basic.exp: Run the new test.
2016-04-13 15:09:25 +01:00
Maciej W. Rozycki 991f40a9fa MIPS/GAS: Correct branch relaxation for weak symbols
Weak symbols can be preempted at link time so always choose the longer
sequence in branch relaxation, according to the relaxation level chosen,
so that any symbol finally used as the branch target is reachable.

2016-04-13  Maciej W. Rozycki  <macro@imgtec.com>
            Andrew Bennett  <andrew.bennett@imgtec.com>

	gas/
	* config/tc-mips.c (relaxed_branch_length): Use the long
	sequence where the target is a weak symbol.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(relaxed_micromips_16bit_branch_length): Likewise.
	* testsuite/gas/mips/branch-weak-1.d: New test.
	* testsuite/gas/mips/branch-weak-2.d: New test.
	* testsuite/gas/mips/branch-weak-3.d: New test.
	* testsuite/gas/mips/branch-weak-4.d: New test.
	* testsuite/gas/mips/branch-weak-5.d: New test.
	* testsuite/gas/mips/branch-weak.l: New stderr output.
	* testsuite/gas/mips/branch-weak.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-13 13:38:50 +01:00
Maciej W. Rozycki c1f61bd2b0 MIPS/GAS: Relax branches to symbols resolved at link time
Where branch relaxation is enabled emit the long sequence for branches
whose distance cannot be determined, i.e. to symbols that are undefined
or in a different segment.  These symbols are only resolved at link time
and therefore the longer sequence ensures the branch target is in range,
which cannot be guaranteed with a direct branch.

This is the opposite to the current implementation, originally proposed
here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>.  The
proposal was then extensively discussed before the final version was
posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html>
and eventually committed:

commit 4a6a3df43d
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Sat Oct 12 05:23:33 2002 +0000

The case considered here was not commented in the review however and the
original version remains.  With branch relaxation enabled it makes more
sense to do it consistently, so that all code impure with respect to
branch distances can be linked.  Direct branches are still produced for
the cases concerned where branch relaxation is disabled, which is the
default.

	gas/
	* config/tc-mips.c (relaxed_branch_length): Use the long
	sequence where the distance cannot be determined.
	(relaxed_micromips_32bit_branch_length): Likewise.
	* testsuite/gas/mips/branch-extern-1.d: New test.
	* testsuite/gas/mips/branch-extern-2.d: New test.
	* testsuite/gas/mips/branch-extern-3.d: New test.
	* testsuite/gas/mips/branch-extern-4.d: New test.
	* testsuite/gas/mips/branch-extern.l: New stderr output.
	* testsuite/gas/mips/branch-extern.s: New test source.
	* testsuite/gas/mips/branch-section-1.d: New test.
	* testsuite/gas/mips/branch-section-2.d: New test.
	* testsuite/gas/mips/branch-section-3.d: New test.
	* testsuite/gas/mips/branch-section-4.d: New test.
	* testsuite/gas/mips/branch-section.l: New stderr output.
	* testsuite/gas/mips/branch-section.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-13 13:32:41 +01:00
Claudiu Zissulescu f36e33dac1 Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textauxregister.d: New file.
	* testsuite/gas/arc/textauxregister.s: Likewise.
	* testsuite/gas/arc/textcondcode.d: Likewise.
	* testsuite/gas/arc/textcondcode.s: Likewise.
	* testsuite/gas/arc/textcoreregister.d: Likewise.
	* testsuite/gas/arc/textcoreregister.s: Likewise.
	* testsuite/gas/arc/textpseudoop.d: Likewise.
	* testsuite/gas/arc/textpseudoop.s: Likewise.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/taux.d: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
	.extCoreRegister and .extAuxRegister documentation.
	* config/tc-arc.c (arc_extcorereg): New function.
	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
	.extAuxRegister pseudo-ops.
	(extRegister_t): New type.
	(ext_condcode, arc_aux_hash): New global variable.
	(find_opcode_match): Check for extensions.
	(preprocess_operands): Likewise.
	(md_begin): Add aux registers in a hash.
	(assemble_insn): Update use arc_flags member.
	(tokenize_extregister): New function.
	(create_extcore_section): Likewise.
	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
	(arc_flags): Delete code, add flgp.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (flag_class_t): Update.
	(ARC_OPCODE_NONE): Define.
	(ARC_OPCODE_ARCALL): Likewise.
	(ARC_OPCODE_ARCFPX): Likewise.
	(ARC_REGISTER_READONLY): Likewise.
	(ARC_REGISTER_WRITEONLY): Likewise.
	(ARC_REGISTER_NOSHORT_CUT): Likewise.
	(arc_aux_reg): Add cpu.

opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:21:06 +02:00
Claudiu Zissulescu 1c2e355e48 Update ARC instruction data-base.
gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/noargs_a7.d: New file.
	* testsuite/gas/arc/noargs_a7.s: Likewise.
	* testsuite/gas/arc/noargs_hs.d: Likewise.
	* testsuite/gas/arc/noargs_hs.s: Likewise.

opcode/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h: Add rtsc, sleep with no arguments.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:08:37 +02:00
Claudiu Zissulescu b99747aeed Add support for .extInstruction pseudo-op.
gas/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textinsn-errors.d: New File.
	* testsuite/gas/arc/textinsn-errors.err: Likewise.
	* testsuite/gas/arc/textinsn-errors.s: Likewise.
	* testsuite/gas/arc/textinsn2op.d: Likewise.
	* testsuite/gas/arc/textinsn2op.s: Likewise.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extInstruction
	documentation.
	* config/tc-arc.c (arcext_section): New variable.
	(arc_extinsn): New function.
	(md_pseudo_table): Add .extInstruction pseudo op.
	(attributes_t): New type.
	(suffixclass, syntaxclass, syntaxclassmod): New constant
	structures.
	(find_opcode_match): Remove arc_num_opcodes.
	(md_begin): Likewise.
	(tokenize_extinsn): New function.
	(arc_set_ext_seg): Likewise.
	(create_extinst_section): Likewise.

include/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (arc_num_opcodes): Remove.
	(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
	(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
	(ARC_SUFFIX_FLAG): Define.
	(flags_none, flags_f, flags_cc, flags_ccf): Declare.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.

opcodes/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	Initialize.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	(arc_opcode arc_opcodes): Null terminate the array.
	(arc_num_opcodes): Remove.
	* arc-ext.h (INSERT_XOP): Define.
	(extInstruction_t): Likewise.
	(arcExtMap_instName): Delete.
	(arcExtMap_insn): New function.
	(arcExtMap_genOpcode): Likewise.
	* arc-ext.c (ExtInstruction): Remove.
	(create_map): Zero initialize instruction fields.
	(arcExtMap_instName): Remove.
	(arcExtMap_insn): New function.
	(dump_ARC_extmap): More info while debuging.
	(arcExtMap_genOpcode): New function.
	* arc-dis.c (find_format): New function.
	(print_insn_arc): Use find_format.
	(arc_get_disassembler): Enable dump_ARC_extmap only when
	debugging.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:06:07 +02:00
Claudiu Zissulescu 37ab977937 Remove unneeded AUX register symbols.
gas/
2016-03-31  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
	(arc_adjust_symtab): New function.
	* config/tc-arc.h (ARC_FLAG_AUX): Define.
	(obj_adjust_symtab): Likewise.
	* testsuite/gas/arc/taux.d: New file.
	* testsuite/gas/arc/taux.s: Likewise.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 09:57:03 +02:00
Maciej W. Rozycki 41a1578ed1 MIPS/GAS: Sanitize `.option picX' pseudo-op
gas/
	* config/tc-mips.c (s_option): Sanitize `.option picX'
	pseudo-op.
	* testsuite/gas/mips/option-pic-1.d: New test.
	* testsuite/gas/mips/option-pic-2.l: New list test.
	* testsuite/gas/mips/option-pic-1.s: New test source.
	* testsuite/gas/mips/option-pic-2.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 21:35:50 +01:00
Maciej W. Rozycki 668c5ebc09 MIPS/GAS: Disallow `.option picX' with VxWorks PIC
gas/
	* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
	PIC.
	* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
	* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
	* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
	* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 21:23:40 +01:00
Maciej W. Rozycki 41065f5e08 MIPS/GAS: Correct call formatting in `can_swap_branch_p'
gas/
	* config/tc-mips.c (can_swap_branch_p): Correct call formatting.
2016-04-09 13:27:30 +01:00
Maciej W. Rozycki 08918cc8c5 GAS: Fix a typo in `as_bad' description
gas/
	* messages.c (as_bad): Fix a typo in description.
2016-04-09 13:22:54 +01:00
Maciej W. Rozycki 1357373c1d MIPS/GAS: Unify messages in `mips_check_options'
gas/
	* config/tc-mips.c (mips_check_options): Unify messages.
2016-04-09 13:19:00 +01:00
Maciej W. Rozycki 5f4678bb69 MIPS/GAS: Use `opts->isa' consistently in `mips_check_options'
gas/
	* config/tc-mips.c (mips_check_options): Use `opts->isa'
	consistently.
2016-04-09 12:55:09 +01:00
Nick Clifton 992dc2c470 Fix regexps in PR19910 test to cope with COFF and AOUT sparc targets.
PR target/19910
	* testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with
	COFF and AOUT sparc targets.
2016-04-08 10:36:49 +01:00
Andrew Burgess a42a4f8400 arc/nps400: Add new instructions
Add some new control instructions to the opcodes library, and a new test
for these new instructions to the assembler.  The new instructions use
an instruction flag longer than any seen before (on arc), and so the max
flag length is extended to accommodate this.

gas/ChangeLog:

	* config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7.
	* testsuite/gas/arc/nps400-2.d: New file.
	* testsuite/gas/arc/nps400-2.s: New file.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
	* arc-opc.c (arc_flag_operands): Add new flags.
	(arc_flag_classes): Add new classes.
2016-04-07 18:36:40 +01:00
Andrew Burgess 1328504b28 gas/arc: Handle multiple arc_opcode chains for same mnemonic
This commit completes support for having multiple instructions with the
same mnemonic in non-contiguous blocks within the arc_opcodes table.

The commit adds an iterator mechanism for the arc_opcode_hash_entry
structure, which is then used in find_opcode_match to consider all
arc_opcode entries with the same mnemonic, even when these instructions
are stored in non-contiguous blocks.

I extend the comment on the arc_opcodes table to discuss how entries
within the table are organised, and to mention how instructions can be
split into multiple groups if needed, but that the table is still
searched in table order.

There should be no user visible changes after this commit.

gas/ChangeLog:

	* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
	structure.
	(arc_opcode_hash_entry_iterator_init): New function.
	(arc_opcode_hash_entry_iterator_next): New function.
	(find_opcode_match): Iterate over all arc_opcode entries
	referenced by the arc_opcode_hash_entry passed in as a parameter.

opcodes/ChangeLog:

	* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
2016-04-07 18:36:09 +01:00
Andrew Burgess b9b47ab79f gas/arc: Additional work to support multiple arc_opcode chains
Building on earlier commits, this commit moves along support for having
multiple arc_opcode entries in the arc_opcodes table that have the same
mnemonic (name) field, but are not stored in a contiguous block in the
table.

In this commit we support looking up the arc_opcode_hash_entry from the
hash table, and passing this along to the find_opcode_match function,
which then finds the specific arc_opcode that we're assembling.  We
still don't actually support the multiple chains of arc_opcode entries
in this commit, but the limitation is now isolated to the
find_opcode_match function.

There is no user visible change after this commit.

gas/ChangeLog:

	* config/tc-arc.c (arc_find_opcode): Now returns
	arc_opcode_hash_entry pointer.
	(find_opcode_match): Update argument type, extract arc_opcode from
	incoming arc_opcode_hash_entry.
	(find_special_case_pseudo): Update return type.
	(find_special_case_flag): Update return type.
	(find_special_case): Update return type.
	(assemble_tokens): Lookup arc_opcode_hash_entry based on
	instruction mnemonic, then use find_opcode_match to identify
	specific arc_opcode.
2016-04-07 18:35:31 +01:00
Andrew Burgess da5be03929 gas/arc: Modify structure used to hold opcodes
The arc assembler builds a hash table to hold references to arc_opcode
entries in the arc_opcodes table.  This hash assumes that each mnemonic
will always appear in a contiguous blocks within the arc_opcodes table;
all ADD instruction will be together, all AND instructions will likewise
be together and so on.

The problem with this is that as different variations of arc are added,
then it is often more convenient to split instructions apart, so all the
base ADD instructions are together, but, variants of ADD specific to one
variation of arc are grouped with other instructions specific to that
arc variant.  The current data structures don't support splitting the
instructions in this way.

This commit is a first step towards addressing this limitation.  In this
commit the hash table that currently holds arc_opcode pointers directly,
instead holds a pointer to a new, intermediate, data structure.  This
new data structure holds the pointer to the arc_opcode.  In this way, we
can, in the future support having the intermediate structure hold
multiple pointers to different arc_opcode groups.

There should be no visible functional change after this commit.

gas/ChangeLog:

	* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
	(arc_find_opcode): New function.
	(find_special_case_pseudo): Use arc_find_opcode.
	(find_special_case_flag): Likewise.
	(assemble_tokens): Likewise.
	(md_begin): Build hash using struct arc_opcode_hash_entry.
2016-04-07 18:35:08 +01:00
Alan Modra abe051ba82 Fix gas/ChangeLog 2016-04-07 23:13:56 +09:30
Claudiu Zissulescu e6ba1cbaf8 [ARC] Prepare strings for automatic translation.
gas/
2016-04-07  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (arc_option): Prepare string for automatic
	translation.
	(declare_register): Likewise.
2016-04-07 15:11:52 +02:00
James Greenhalgh b607cde1aa Update AArch64 documentation regarding architecture extensions.
* doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE.
	Correct entry for RDMA.  Alpha sort entries.
2016-04-07 13:29:50 +01:00
Andrew Burgess 692166c244 gas/arc: Allow greater range of characters into flag names
An upcoming commit will add a new arc instruction flag that uses
characters that have never appeared in an arc instruction flag before.
Currently the assembler is very conservative about which characters can
or cannot appear in an instruction flag.

This commit relaxes these constraints a little.  After this commit all
alpha-numeric characters are now allowed into instruction flags.  This
complete set is not required for the upcoming change, however, having
this slightly larger set does not impact the assemblers ability to
correctly parse input, but does make it easier to add new flag to the
instruction table.

gas/ChangeLog:

	* config/tc-arc.c (tokenize_flags): Allow greater range of
	characters into flag names.
2016-04-07 12:42:58 +01:00
Andrew Burgess 22b92fc42c gas/arc: Remove preprocess_operands function
The preprocess_operands function changes the incoming list of assembler
tokens based on the assumption that the first arc_operand found will be
the same instruction class as all of the arc_operands for the same
mnemonic.

Though this assumption is probably fine, removing this assumption, and
pushing the token change down into assemble_tokens makes the code no
more complex, and might even be easier to follow.

There should be no user visible changes after this commit.

gas/ChangeLog:

	* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
	new de_fault label.
	(preprocess_operands): Delete.
	(assemble_tokens): Remove call to preprocess_operands.
2016-04-07 12:42:58 +01:00
Nick Clifton e140100a5d Allow integer contants to have a U suffix. Improve error reporting for missing closing parentheses.
PR gas/19910
	* config/tc-sparc.c (sparc_ip): Report an error if the expression
	inside a %-macro could not be fully parsed.
	* expr.c (integer_constant): Accept and ignore U suffixes to
	integers.
	(operand): When a missing closing parenthesis is encountered,
	report the character that was found instead.
	* testsuite/gas/mips/tls-ill.l: Update expected error message.
	* testsuite/gas/sparc/pr19910-1.d: New test driver.
	* testsuite/gas/sparc/pr19910-1.s: New test.
	* testsuite/gas/sparc/pr19910-2.l: Expected error output.
	* testsuite/gas/sparc/pr19910-2.s: New test.
	* testsuite/gas/sparc/sparc.exp: Run the new tests.
2016-04-07 12:34:06 +01:00
Nick Clifton 927f2d25ef Fix MSP430 assembler's detection of NOP and EINT.
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding
	an EINT instruction.  Warn/fix as necessary.
	* testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP.
	* testsuite/gas/msp430/bad.l: Update expected messages.
2016-04-06 15:58:30 +01:00
Andrew Burgess 820f03ffe0 arc/nps400: Add additional instructions
Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16,
and crc32 instructions for the nps400 arc machine type.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-1.d: Update expected results.
	* testsuite/gas/arc/nps400-1.s: Additional test cases.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
	encode1, rflt, crc16, and crc32 instructions.
	* arc-opc.c (arc_flag_operands): Add F_NPS_R.
	(arc_flag_classes): Add C_NPS_R.
	(insert_nps_bitop_size_2b): New function.
	(extract_nps_bitop_size_2b): Likewise.
	(insert_nps_bitop_uimm8): Likewise.
	(extract_nps_bitop_uimm8): Likewise.
	(arc_operands): Add new operand entries.
2016-04-05 22:45:55 +01:00
Claudiu Zissulescu 8ddf6b2a13 [ARC] Fix support for double assist instructions.
opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-regs.h: Add a new subclass field.  Add double assist
        accumulator register values.
        * arc-tbl.h: Use DPA subclass to mark the double assist
        instructions.  Use DPX/SPX subclas to mark the FPX instructions.
        * arc-opc.c (RSP): Define instead of SP.
        (arc_aux_regs): Add the subclass field.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
        (ARC_FPUDA): Define.
        (arc_aux_reg): Add new field.

gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/tc-arc.c (is_code_density_p): Compare directly the
        subclass field.
        (is_spfp_p, is_dpfp_p, is_spfp_p): Define.
        (check_cpu_feature): New function.
        (find_opcode_match): Use check_cpu_feature function.
        (preprocess_operands): Likewise.
        (md_parse_option): Use mfpuda, mdpfp, mspfp options.
        * testsuite/gas/arc/tdpfp.d: New file.
        * testsuite/gas/arc/tfpuda.d: Likewise.
        * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 17:37:45 +02:00
Jiong Wang 589a7d8830 [ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)
gas/
  * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.
  * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests.
  * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results.
  * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb.
  * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase.
  * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results.

opcodes/
  * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-04-05 15:54:00 +01:00
Claudiu Zissulescu 6ec1f28285 [ARC] Don't allow pc-rel relocations for J* instructions.
gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for
        JUMP instructions type.
        * testsuite/gas/arc/relocs-errors.d: New file.
        * testsuite/gas/arc/relocs-errors.err: Likewise.
        * testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-05 16:23:02 +02:00
H.J. Lu 5be33403c3 Don't use vec_disp8 encoding with the .d32 suffix
Since the .d32 suffix prefers 32-bit displacement in encoding, try
vec_disp8 encoding only if i.disp_encoding != disp_encoding_32bit.

	PR gas/19909
	* config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding
	only if i.disp_encoding != disp_encoding_32bit.
	* gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32.
	* gas/testsuite/gas/i386/x86-64-disp32.s: Likewise.
	* gas/testsuite/gas/i386/disp32.d: Updated.
	* gas/testsuite/gas/i386/x86-64-disp32.d: Likewise.
2016-04-04 21:19:27 -07:00
H.J. Lu df41fdf4bd Add a testcase for PR gas/19498
PR gas/19498
	* testsuite/gas/i386/i386.exp: Run pr19498.
	* testsuite/gas/i386/pr19498.d: New file.
	* testsuite/gas/i386/pr19498.s: Likewise.
2016-04-04 20:45:30 -07:00
Andrew Burgess 26cdfd9205 gas/arc: Use #define from include/opcode/arc.h
In tc-arc.h we redefine constants that are also defined in the
include/opcode/arc.h header file.  The problem is that changing one
without changing the other resulting in strange crashes.

We could comment both locations to stress the importance of remembering
to update the other location too, or we could just include the
opcode/arc.h header file into the assembler.

Given that other targets include their opcode/ARCH.h header file, and
only having a single definition, where possible, is usually the safest
solution, that's what I switch too with this commit.

gas/ChangeLog:

	* config/tc-arc.h: Include 'opcode/arc.h'.
	(MAX_INSN_ARGS): Delete.
	(MAX_INSN_FLGS): Delete.
2016-04-04 09:09:53 +01:00
Alan Modra 22987cec62 PR19498, Invalid "symbol definition loop"
PR 19498
	* symbols.c (resolve_symbol_value): Clear sy_resolving on exit
	from function on all paths that set sy_resolving.
2016-04-04 16:20:58 +09:30
Trevor Saunders 325801bda4 use XNEW and related macros more
gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* app.c (app_push): use XNEW macro.
	* as.c: Likewise.
	* config/obj-elf.c (obj_elf_change_section): Likewise.
	(elf_copy_symbol_attributes): Likewise.
	(obj_elf_size): Likewise.
	(build_group_lists): Likewise.
	* config/tc-aarch64.c (add_operand_error_record): Likewise.
	(md_assemble): Likewise.
	(tc_gen_reloc): Likewise.
	(get_upper_str): Likewise.
	(aarch64_parse_features): Likewise.
	* config/tc-arm.c (insert_reg_alias): Likewise.
	(insert_neon_reg_alias): Likewise.
	(find_or_make_literal_pool): Likewise.
	(s_arm_elf_cons): Likewise.
	(add_unwind_opcode): Likewise.
	(arm_parse_extension): Likewise.
	* config/tc-avr.c (create_record_for_frag): Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-dlx.c (s_proc): Likewise.
	* config/tc-ft32.c: Likewise.
	* config/tc-h8300.c: Likewise.
	* config/tc-hppa.c (pa_proc): Likewise.
	(create_new_space): Likewise.
	(create_new_subspace): Likewise.
	* config/tc-i860.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-iq2000.c (iq2000_add_macro): Likewise.
	(iq2000_record_hi16): Likewise.
	* config/tc-m32c.c (m32c_indirect_operand): Likewise.
	* config/tc-m32r.c (debug_sym): Likewise.
	(m32r_record_hi16): Likewise.
	* config/tc-m68k.c (m68k_ip): Likewise.
	(md_begin): Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-microblaze.c (check_got): Likewise.
	* config/tc-mips.c (append_insn): Likewise.
	(s_mipsset): Likewise.
	(mips_record_label): Likewise.
	(s_mips_end): Likewise.
	* config/tc-mmix.c (mmix_frob_file): Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-moxie.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-or1k.c: Likewise.
	* config/tc-pdp11.c: Likewise.
	* config/tc-pj.c (fake_opcode): Likewise.
	* config/tc-ppc.c (ppc_apuinfo_section_add): Likewise.
	(ppc_macro): Likewise.
	(ppc_dwsect): Likewise.
	(ppc_machine): Likewise.
	* config/tc-rl78.c (rl78_frag_init): Likewise.
	* config/tc-rx.c (rx_frag_init): Likewise.
	* config/tc-s390.c (s390_lit_suffix): Likewise.
	(s390_machine): Likewise.
	(s390_machinemode): Likewise.
	* config/tc-score.c (s3_insert_reg): Likewise.
	(s3_gen_reloc): Likewise.
	* config/tc-score7.c (s7_insert_reg): Likewise.
	(s7_gen_reloc): Likewise.
	* config/tc-tic30.c (tic30_operand): Likewise.
	* config/tc-tic4x.c (tic4x_inst_make): Likewise.
	* config/tc-tic54x.c (stag_add_field): Likewise.
	(tic54x_struct): Likewise.
	(tic54x_space): Likewise.
	(tic54x_field): Likewise.
	(tic54x_mlib): Likewise.
	(subsym_substitute): Likewise.
	* config/tc-tic6x.c (tic6x_frob_label): Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-xc16x.c: Likewise.
	* config/tc-xtensa.c (xtensa_add_insn_label): Likewise.
	(directive_push): Likewise.
	(xtensa_begin_directive): Likewise.
	(tokenize_arguments): Likewise.
	(xtensa_add_literal_sym): Likewise.
	(new_resource_table): Likewise.
	(resize_resource_table): Likewise.
	(emit_single_op): Likewise.
	(xtensa_create_trampoline_frag): Likewise.
	(xtensa_maybe_create_literal_pool_frag): Likewise.
	(xtensa_add_config_info): Likewise.
	(xtensa_realloc_fixup_cache): Likewise.
	(add_subseg_info): Likewise.
	(cache_literal_section): Likewise.
	(add_xt_block_frags): Likewise.
	(add_xt_prop_frags): Likewise.
	(init_op_placement_info_table): Likewise.
	(build_section_rename): Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* depend.c (register_dependency): Likewise.
	* dwarf2dbg.c (get_line_subseg): Likewise.
	(dwarf2_gen_line_info_1): Likewise.
	(get_filenum): Likewise.
	* ecoff.c (allocate_scope): Likewise.
	(allocate_vlinks): Likewise.
	(allocate_shash): Likewise.
	(allocate_thash): Likewise.
	(allocate_tag): Likewise.
	(allocate_forward): Likewise.
	(allocate_thead): Likewise.
	(allocate_lineno_list): Likewise.
	* expr.c (make_expr_symbol): Likewise.
	* hash.c (hash_new_sized): Likewise.
	* input-file.c (input_file_push): Likewise.
	* listing.c (file_info): Likewise.
	(listing_newline): Likewise.
	* macro.c (new_formal): Likewise.
	(define_macro): Likewise.
	* remap.c (add_debug_prefix_map): Likewise.
	* symbols.c (symbol_find_noref): Likewise.
	(define_dollar_label): Likewise.
	(fb_label_instance_inc): Likewise.
	(symbol_relc_make_value): Likewise.
2016-04-03 20:43:23 -04:00
Trevor Saunders a44e2901c7 use xstrdup and friends more
gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/obj-elf.c (obj_elf_vendor_attribute): Use xstrdup.
	* config/tc-ppc.c (ppc_frob_file_before_adjust): Likewise.
	(ppc_znop): Likewise.
	(ppc_pe_section): Likewise.
	(ppc_frob_symbol): Likewise.
	* config/tc-tic30.c (tic30_operand): Likewise.
	* config/tc-tic4x.c (tic4x_sect): Likewise.
	(tic4x_usect): Likewise.
2016-04-03 19:52:25 -04:00
Trevor Saunders ae2689b09f cleanup FLT_CHARS and EXP_CHARS
Providing declarations in tc.h points out that alpha wasn't properly marking
FLT_CHARS as const.  We can also get rid of the confusing redefinition of
X_CHARS to mmix_x_chars.  Finally we can get rid of some now redundant
declarations of these constants.

gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-alpha.c: Const qualify FLT_CHARS.
	* config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS.
	* config/tc-cris.h: Likewise.
	* expr.c: Likewise.
	* config/tc-mmix.c (md_atof): Adjust comment.
	* config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros.
	* tc.h: Declare FLT_CHARS and EXP_CHARS.
2016-04-03 19:50:02 -04:00
Trevor Saunders a51ef39291 update ChangeLog for previous commit 2016-04-03 19:49:05 -04:00
Trevor Saunders 585ba04089 make score build again
It needs a few more things to be const now.

gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-score.c (s3_gen_reloc): Add const qualifiers.
	* config/tc-score7.c (s7_gen_reloc): Likewise.
2016-04-03 19:46:09 -04:00
Trevor Saunders 2fe882148c arm: change the type of a variable to bfd_reloc_code_real_type
It is only ever assigned values in the enum, and it is passed to functions that
expect the argument's type to be the enum.

gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-arm.c (do_t_branch): Change the type of reloc to
	bfd_reloc_code_real_type.
2016-04-03 19:15:39 -04:00
Trevor Saunders e1ec8109ab bfin: simplify current_inputline
Its not used for anything outside of md_assemble () so it doesn't need to be
extern.  While we are there we can replace free () and xmalloc () with
XRESIZEVEC which should be faster.

gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/bfin-parse.y (current_inputline): Remove definition.
	* config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
2016-04-03 19:13:42 -04:00
Trevor Saunders f73e41ef37 avr: simplify some option parsing with strcasecmp ()
Instead of canonicalizing the argument we can just use a case insensitive
     compare.

gas/ChangeLog:

2016-04-03  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-avr.c (md_parse_option): Use strcasecmp () to compare
	strings.
2016-04-03 19:10:33 -04:00
Alan Modra 62bd6b5fa4 PR19896, Segmentation fault on bad input
PR 19896
	* read.c (assign_symbol): Consume rest of line after an error
	rather than continuing to process the line.
2016-04-02 17:31:36 +10:30
Andrew Burgess 83cda17b6f gas/arc: Change 'LENGHT' to 'LENGTH'
Small spelling mistake in a #define, fixed in this commit.

gas/ChangeLog:

	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to...
	(MAX_FLAG_NAME_LENGTH): ...this.
	(struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH.
	* config/tc-arc.c (tokenize_flags): Likewise.
2016-04-01 15:47:08 +01:00
Alan Modra 6d4af3c269 Constify more
* cgen.c (weak_operand_overflow_check): Return const char*.
	* messages.c (as_internal_value_out_of_range): Formatting.
	(as_warn_value_out_of_range): Consify prefix param.
	(as_bad_value_out_of_range): Likewise.
	* read.c (s_errwarn): Constify msg..
	(s_float_space, float_cons): ..and err.
	* as.h (as_warn_value_out_of_range, as_bad_value_out_of_range,
	ieee_md_atof, vax_md_atof): Update prototypes.
	* tc.h (md_atof): Update prototype.
	* config/atof-ieee.c (ieee_md_atof): Return const char*.
	* config/atof-vax.c (vax_md_atof): Likewise.
	* config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg.
	* config/tc-aarch64.c (md_atof): Return const char*.
	* config/tc-alpha.c (s_alpha_section_name): Likewise.
	(s_alpha_comm): Constify sec_name.
	(section_name): Constify.
	(s_alpha_section): Consify name..
	(alpha_elf_section_letter): ..and ptr_msg param..
	(md_atof): ..and return.
	* config/tc-alpha.h (alpha_elf_section_letter): Update prototype.
	* config/tc-arc.c (md_atof): Return const char*.
	* config/tc-arm.c (md_atof): Likewise.
	* config/tc-avr.c (md_atof): Likewise.
	* config/tc-bfin.c (md_atof): Likewise.
	* config/tc-cr16.c (md_atof): Likewise.
	* config/tc-cris.c (md_atof): Likewise.
	* config/tc-crx.c (md_atof): Likewise.
	* config/tc-d10v.c (md_atof): Likewise.
	* config/tc-d30v.c (md_atof): Likewise.
	* config/tc-dlx.c (md_atof): Likewise.
	* config/tc-epiphany.c (md_atof): Likewise.
	* config/tc-fr30.c (md_atof): Likewise.
	* config/tc-frv.c (md_atof): Likewise.
	* config/tc-ft32.c (md_atof): Likewise.
	* config/tc-h8300.c (md_atof): Likewise.
	* config/tc-hppa.c (struct default_subspace_dict): Constify name.
	(struct default_space_dict): Likewise.
	(create_new_space): Constify name param.
	(create_new_subspace): Likewise.
	(is_defined_space, is_defined_subspace): Likewise.
	(pa_parse_space_stmt): Constify space_name param.
	(md_atof): Return const char*.
	(pa_spaces_begin): Constify name.
	* config/tc-i370.c (md_atof): Return const char*.
	* config/tc-i386.c (md_atof): Likewise.
	(x86_64_section_letter): Constify ptr_msg param.
	* config/tc-i386.h (x86_64_section_letter): Update prototype.
	* config/tc-i860.c (struct i860_it): Constify error.
	(md_atof): Return const char*.
	* config/tc-i960.c (md_atof): Likewise.
	* config/tc-ia64.c (md_atof): Likewise.
	(ia64_elf_section_letter): Constify ptr_msg param.
	* config/tc-ia64.h (ia64_elf_section_letter): Update prototype.
	* config/tc-ip2k.c (md_atof): Return const char*.
	* config/tc-iq2000.c (md_atof): Likewise.
	* config/tc-lm32.c (md_atof): Likewise.
	* config/tc-m32c.c (md_atof): Likewise.
	* config/tc-m32r.c (md_atof): Likewise.
	* config/tc-m68hc11.c (md_atof): Likewise.
	* config/tc-m68k.c (md_atof): Likewise.
	* config/tc-mcore.c (md_atof): Likewise.
	* config/tc-mep.c (md_atof): Likewise.
	(mep_elf_section_letter): Constify ptr_msg param.
	* config/tc-mep.h (mep_elf_section_letter): Update prototype.
	* config/tc-metag.c (md_atof): Return const char*.
	* config/tc-microblaze.c (md_atof): Likewise.
	* config/tc-microblaze.h (md_atof): Delete prototype.
	* config/tc-mips.c (mips_parse_argument_token): Constify err.
	(md_atof): Return const char*.
	* config/tc-mmix.c (md_atof): Likewise.
	* config/tc-mn10200.c (md_atof): Likewise.
	* config/tc-mn10300.c (md_atof): Likewise.
	* config/tc-moxie.c (md_atof): Likewise.
	* config/tc-msp430.c (md_atof): Likewise.
	* config/tc-mt.c (md_atof): Likewise.
	* config/tc-nds32.c (md_atof): Likewise.
	* config/tc-nios2.c (md_atof): Likewise.
	(nios2_elf_section_letter): Constify ptr_msg param.
	* config/tc-nios2.h (nios2_elf_section_letter): Update prototype.
	* config/tc-ns32k.c (md_atof): Return const char*.
	* config/tc-or1k.c (md_atof): Likewise.
	* config/tc-pdp11.c (struct pdp11_code): Constify error.
	(md_atof): Return const char*.
	* config/tc-pj.c (md_atof): Likewise.
	* config/tc-ppc.c (md_atof): Likewise.
	* config/tc-rl78.c (md_atof): Likewise.
	* config/tc-rx.c (md_atof): Likewise.
	* config/tc-s390.c (md_atof): Likewise.
	* config/tc-score.c (s3_atof, md_atof): Likewise.
	* config/tc-sh.c (md_atof): Likewise.
	* config/tc-sparc.c (struct sparc_it): Constify error.
	(md_atof): Return const char*.
	* config/tc-spu.c (md_atof): Likewise.
	* config/tc-tic30.c (md_atof): Likewise.
	* config/tc-tic4x.c (md_atof): Likewise.
	* config/tc-tic54x.c (md_atof): Likewise.
	* config/tc-tic6x.c (md_atof): Likewise.
	* config/tc-tilegx.c (md_atof): Likewise.
	* config/tc-tilepro.c (md_atof): Likewise.
	* config/tc-v850.c (parse_register_list, md_atof): Likewise.
	* config/tc-vax.c (md_atof): Likewise.
	* config/tc-visium.c (md_atof): Likewise.
	* config/tc-xc16x.c (md_atof): Likewise.
	* config/tc-xgate.c (md_atof): Likewise.
	* config/tc-xstormy16.c (md_atof): Likewise.
	* config/tc-xtensa.c (md_atof): Likewise.
	* config/tc-z80.c (md_atof): Likewise.
	* config/tc-z8k.c (md_atof): Likewise.
2016-04-01 23:10:50 +10:30
Trevor Saunders 6757cf5769 enable -Wwrite-strings for gas
We add a new AC_SUBST to warning.m4 so that the test if the warning is
supported is centralized, but the warning can be enabled per directory.

binutils/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.

gprof/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.

ld/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.

opcodes/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.

bfd/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.
	* warning.m4: Add WARN_WRITE_STRINGS AC_SUBST.

gold/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* configure: Regenerate.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* Makefile.am: Add WARN_WRITE_STRINGS to WARN_CFLAGS.
	* Makefile.in: Regenerate.
	* configure: Likewise.
2016-03-31 07:30:56 -04:00
Trevor Saunders e4a0c70877 make xtensa_section_rename () take const char *
Xtensa uses it in several macros passing it a literal string, so its convenient
for the argument type to be const char *.  However some of the code in
symbols.c seems to assume tc_canonicalize_symbol_name () will return a non
const pointer, and some other target's implementations even modify the
argument, so it seems best to return a char * which means casting away const on
the argument when we return it instead of another string.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-xtensa.c (struct rename_section_struct): Make old_name
	const.
	(xtensa_section_rename): Make argument type const char *.
	* config/tc-xtensa.h (xtensa_section_rename): Adjust.
2016-03-31 07:30:41 -04:00
Trevor Saunders e2c7dcae81 tc-i960.c: add some casts when assigning literals to args[i]
parse_ldconst () takes a char ** as a in / out argument, and sometimes points
args[0] to a constant string.  Then in some cases after parse_ldconst ()
     returns md_assemble () twiddles the contents of arg[0].  So it seems like
     it would take some work to avoid these casts, and its not really clear
     that work is worth it.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-i960.c (parse_ldconst): Cast to char * when assigning to
	args[0].
2016-03-31 07:29:51 -04:00
Trevor Saunders f854977c23 cast the arg to md_assemble () to char *
For these targets its not clear how md_assemble can usefully be split up so
that part can take const char *.  There is also a fair number of targets that
need md_assemble () to take a char *, so we can't easily make the argument
const.  So since there isn't many callers it seems easiest to just add a couple
of casts.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to
	char *.
	(m32c_indirect_operand): Likewise.
	* config/tc-nds32.c (do_pseudo_b): Likewise.
	(do_pseudo_bal): Likewise.
	(do_pseudo_ls_bhw): Likewise.
2016-03-31 07:29:00 -04:00
Trevor Saunders 97830986a1 cast to char * when assigning to optarg
gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* as.c (parse_args): Cast literal to char * when assigning to optarg.
2016-03-31 07:28:08 -04:00
Trevor Saunders e87de5136e work around get_symbol_name () in sparc and ia64
get_symbol_name () returns a char * in a out arg, which means we need to cast
to assign a literal to the variable passed to get_symbol_name ().  It seems
like better APIs than get_symbol_name () could be provided, but that seems like
a fair amount of work so just casting seems to be the betterthing to do for
now.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-ia64.c (md_assemble): Add temporary variable to pass to
	get_symbol_name ().
	* config/tc-sparc.c (s_register): Cast a literal to char * in
	assignment.
2016-03-31 07:27:36 -04:00
Trevor Saunders 47990a6ab5 cast literal to char * when assigning to input_line_ptr
various places either directly or indirectly set input_line_pointer to point at
a literal.  Currently lots of places modify the string input_line_pointer
points at, so making it const isn't easy.  Since most if not all of these
places assign to input_line_pointer to parse an expression it would probably be
best to add ways to generate and deal with expressions that doesn't involve
parsing strings, but for now adding some casts seems easiest.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-i960.c (parse_expr): Cast to char * when assigning to
	input_line_pointer.
	* config/tc-m32r.c (expand_debug_syms): Likewise.
	* config/tc-msp430.c (msp430_dstoperand): Likewise.
	* config/tc-z80.c (md_begin): Likewise.
	* stabs.c (stabs_generate_asm_func): Likewise.
2016-03-31 07:23:31 -04:00
Trevor Saunders e046cf801d get rid of K&R style args
gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* cgen.c: Modernize the way functions declare arguments.
	* config/tc-bfin.c: Likewise.
	* config/tc-pdp11.c: Likewise.
	* literal.c: Likewise.
	* read.c: Likewise.
	* stabs.c: Likewise.
2016-03-31 01:04:00 -04:00
Trevor Saunders d923501116 make some variables unsigned
these places define char arrays containing values greater than 0x80 which
doesn't fit in an 8 bit signed char, but does fit in an unsigned one.

gas/ChangeLog:

2016-03-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-aarch64.c (aarch64_handle_align): Make the type of some
	variables unsigned char[].
	* config/tc-alpha.c (alpha_handle_align): Likewise.
	* config/tc-arm.c (arm_handle_align): Likewise.
	* config/tc-z80.c: Likewise.
2016-03-31 00:57:11 -04:00
Nick Clifton c6025a80cc Fix compile time warning about comparison between signed and unsigned values.
PR target/19880
	* config/tc-arm.c (do_t_push_pop): Cast bitmask to unsigned before
	shifting.
2016-03-30 16:18:04 +01:00
Claudiu Zissulescu f89a23cfc9 [ARC] Allow equ redefintion tests for ARC.
gas/
2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>

        * testsuite/gas/all/gas.exp: Don't xfail on ARC.
        * testsuite/gas/elf/elf.exp: Likewise.
        * testsuite/gas/all/redef3.d: Allow execution for ARC.
2016-03-30 16:21:25 +02:00
Claudiu Zissulescu f621ad3c4b [ARC] Fix warn.exp test error.
gas/
2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>

        * testsuite/gas/arc/warn.exp: Fix matching pattern.
2016-03-30 16:09:56 +02:00
Trevor Saunders 4ec9d7d564 use xstrdup and friends more
gas/ChangeLog:

2016-03-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-hppa.c (pa_space): Use xstrdup where appropriate.
	(pa_subspace): Likewise.
	(create_new_space): Likewise.
	(create_new_subspace): Likewise.
	* config/tc-mips.c (mips_lookup_insn): Likewise.
	* config/tc-tic4x.c (tic4x_asg): Likewise.
	* config/tc-tic54x.c (tic54x_eval): Likewise.
	(stag_add_field): Likewise.
	(tic54x_usect): Likewise.
	(tic54x_clink): Likewise.
	(tic54x_set_default_include): Likewise.
	(tic54x_include): Likewise.
	(tic54x_message): Likewise.
	(tic54x_sblock): Likewise.
	(tic54x_var): Likewise.
	(subsym_ismember): Likewise.
	(subsym_substitute): Likewise.
	* config/tc-xtensa.c (xg_replace_opname): Likewise.
	(xg_translate_sysreg_op): Likewise.
	(xg_translate_idioms): Likewise.
	(md_assemble): Likewise.
	(cache_literal_section): Likewise.
2016-03-29 21:48:26 -04:00
Claudiu Zissulescu f2dd88387a [ARC] Add support for Quarkse opcodes.
gas/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * testsuite/gas/arc/ext2op.d: New file.
        * testsuite/gas/arc/ext2op.s: Likewise.
        * testsuite/gas/arc/ext3op.d: Likewise.
        * testsuite/gas/arc/ext3op.s: Likewise.

opcodes/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-tbl.h (invld07): Remove.
        * arc-ext-tbl.h: New file.
        * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
        * arc-opc.c (arc_opcodes): Add ext-tbl include.

include/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
        (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
        (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
        (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
        (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
        (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
        (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
        (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
        (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
        (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
        (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
        (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
        (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
        (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
Trevor Saunders 17b9d67d4e make md_parse_option () take a const char *
This is mostly just adding const in many places, however there are a couple
interesting things.  We need to add casts in tc-s390.c and tc-cris.c because
they have functions that assign to input_line_pointer an argument that
sometimes comes from md_parse_option.  Presumably this is safe because those
targets never pass literals to md_parse_option (), but this code should
probably be improved in the future.  Also xtensa passes the argument to strtoll
which is a rather odd function, it takes a const char * as argument and returns
a pointer into that string as a char * through an out argument, but we can work
around that by adding more variables.

gas/ChangeLog:

2016-03-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-aarch64.c (struct aarch64_long_option_table): Ad const
	qualifier.
	* config/tc-alpha.c (md_parse_option): Likewise.
	* config/tc-arc.c (md_parse_option): Likewise.
	* config/tc-arm.c (struct arm_long_option_table): Likewise.
	(md_parse_option): Likewise.
	* config/tc-avr.c (md_parse_option): Likewise.
	* config/tc-bfin.c (md_parse_option): Likewise.
	* config/tc-cr16.c (md_parse_option): Likewise.
	* config/tc-cris.c (s_cris_arch): Likewise.
	(md_parse_option): Likewise.
	* config/tc-crx.c (md_parse_option): Likewise.
	* config/tc-d10v.c (md_parse_option): Likewise.
	* config/tc-d30v.c (md_parse_option): Likewise.
	* config/tc-dlx.c (md_parse_option): Likewise.
	* config/tc-epiphany.c (md_parse_option): Likewise.
	* config/tc-fr30.c (md_parse_option): Likewise.
	* config/tc-frv.c (md_parse_option): Likewise.
	* config/tc-ft32.c (md_parse_option): Likewise.
	* config/tc-h8300.c (md_parse_option): Likewise.
	* config/tc-hppa.c (md_parse_option): Likewise.
	* config/tc-i370.c (md_parse_option): Likewise.
	* config/tc-i386.c (md_parse_option): Likewise.
	* config/tc-i860.c (md_parse_option): Likewise.
	* config/tc-i960.c (md_parse_option): Likewise.
	* config/tc-ia64.c (md_parse_option): Likewise.
	* config/tc-ip2k.c (md_parse_option): Likewise.
	* config/tc-iq2000.c (md_parse_option): Likewise.
	* config/tc-lm32.c (md_parse_option): Likewise.
	* config/tc-m32c.c (md_parse_option): Likewise.
	* config/tc-m32r.c (md_parse_option): Likewise.
	* config/tc-m68hc11.c (md_parse_option): Likewise.
	* config/tc-m68k.c (md_parse_option): Likewise.
	* config/tc-mcore.c (md_parse_option): Likewise.
	* config/tc-mep.c (md_parse_option): Likewise.
	* config/tc-metag.c (struct metag_long_option): Likewise.
	(md_parse_option): Likewise.
	* config/tc-microblaze.c (md_parse_option): Likewise.
	* config/tc-microblaze.h (md_parse_option): Remove prototype.
	* config/tc-mips.c (md_parse_option): Adjust.
	* config/tc-mmix.c (md_parse_option): Likewise.
	* config/tc-mn10200.c (md_parse_option): Likewise.
	* config/tc-mn10300.c (md_parse_option): Likewise.
	* config/tc-moxie.c (md_parse_option): Likewise.
	* config/tc-msp430.c (md_parse_option): Likewise.
	* config/tc-mt.c (md_parse_option): Likewise.
		* config/tc-nds32.c (md_parse_option): Likewise.
		* config/tc-nds32.h (nds32_parse_option): Likewise.
	* config/tc-nios2.c (md_parse_option): Likewise.
	* config/tc-ns32k.c (md_parse_option): Likewise.
	* config/tc-or1k.c (md_parse_option): Likewise.
	* config/tc-pdp11.c (md_parse_option): Likewise.
	* config/tc-pj.c (md_parse_option): Likewise.
	* config/tc-ppc.c (md_parse_option): Likewise.
	* config/tc-rl78.c (md_parse_option): Likewise.
	* config/tc-rx.c (md_parse_option): Likewise.
	* config/tc-s390.c (s390_parse_cpu): Likewise.
	* config/tc-score.c (md_parse_option): Likewise.
	* config/tc-sh.c (md_parse_option): Likewise.
	* config/tc-sparc.c (md_parse_option): Likewise.
	* config/tc-spu.c (md_parse_option): Likewise.
	* config/tc-tic30.c (md_parse_option): Likewise.
	* config/tc-tic4x.c (md_parse_option): Likewise.
	* config/tc-tic54x.c (md_parse_option): Likewise.
	* config/tc-tic6x.c (md_parse_option): Likewise.
	* config/tc-tilegx.c (md_parse_option): Likewise.
	* config/tc-tilepro.c (md_parse_option): Likewise.
	* config/tc-v850.c (md_parse_option): Likewise.
	* config/tc-vax.c (md_parse_option): Likewise.
	* config/tc-visium.c (struct visium_long_option_table): Likewise.
	* config/tc-xc16x.c (md_parse_option): Likewise.
	* config/tc-xgate.c (md_parse_option): Likewise.
	* config/tc-xstormy16.c (md_parse_option): Likewise.
	* config/tc-xtensa.c (md_parse_option): Likewise.
	* config/tc-z80.c (md_parse_option): Likewise.
	* config/tc-z8k.c (md_parse_option): Likewise.
	* tc.h (md_parse_option): Likewise.
2016-03-29 07:43:25 -04:00
Trevor Saunders 30bd735cb0 apply ChangeLog for previous commit 2016-03-29 07:40:22 -04:00
Trevor Saunders aff7ae12a6 replace some obstack_alloc () calls with the XOBNEW wrapper
gas/ChangeLog:

2016-03-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-bfin.c (gencode): Use XOBNEW obstack_alloc () wrapper.
	* config/tc-hppa.c (fix_new_hppa): Likewise.
	(pa_vtable_entry): Likewise.
	(pa_vtable_inherit): Likewise.
	* config/tc-m68k.c (md_begin): Likewise.
2016-03-29 07:33:25 -04:00
Trevor Saunders 82b8a7851f add more const qualifiers
gas/ChangeLog:

2016-03-28  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/obj-elf.c (obj_elf_section_name): Return const char *.
	* config/obj-elf.h (obj_elf_section_name): Adjust.
	* config/tc-aarch64.c (aarch64_parse_features): Likewise.
	(aarch64_parse_cpu): Likewise.
	(aarch64_parse_arch): Likewise.
	* config/tc-arm.c (arm_parse_extension): Likewise.
	(arm_parse_cpu): Likewise.
	(arm_parse_arch): Likewise.
	* config/tc-nds32.c: Likewise.
	* config/xtensa-relax.c (parse_special_fn): Likewise.
	* stabs.c (generate_asm_file): Likewise.
2016-03-28 20:38:24 -04:00
Trevor Saunders 9202e88a2a split up cr16s md_assemble ()
gas/ChangeLog:

2016-03-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-cr16.c (cr16_assemble): New function.
	(md_assemble): Call cr16_assemble.
2016-03-25 20:26:56 -04:00
Trevor Saunders a90fb5e33b rename flag_size_check to flag_allow_nonconst_size and make it a bool
This name describes what the variable means slightly better, and the enum with
two values that is only used for this one variable is kind of silly.

gas/ChangeLog:

2016-03-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* as.c (parse_args): Adjust.
	* as.h (flag_size_check): Rename to flag_allow_nonconst_size.
	* config/obj-elf.c (elf_frob_symbol): Adjust.
2016-03-25 20:24:57 -04:00
Jose E. Marchesi f65c3d1b26 gas: sparc: allow ASR registers in the 0..31 range in V9 and later
In the SPARC V9 (and later) versions of the SPARC specification, the
section C.1.1 "Register Names" specifies that:

"asr_reg.  An asr_reg is an Ancillary State Register name.  It may have
 one of the following values:

  %asr16-%asr31"

The rationale of having this restriction was that the registers from 16
to 31 are reserved to implementations, and are therefore "non-V9".  It
also assumes that the existing ASR registers in the range 0..31 will
have their own names such as %y, that can be used to access such
registers.

However, this is problematic.  When a new ASR register is introduced,
such as %mcdper a.k.a. %asr14, it is useful to be able to use %asr14 in
order to not depend on the latest version of the assembler.

The Solaris assembler is lax and allows to assembly instructions
referring to %asr0 to %asr31.  This patch makes the GNU assembler to
mimic that behavior.

gas/ChangeLog:

  2016-03-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR
	registers to be in the 16..31 range.
2016-03-24 10:28:41 -07:00
Trevor Saunders e742e119e1 make microblaze build with -Wwrite-strings
frag_var () assigns its last argument to frag::fr_opcode, and it turns out
some targets modify the string that points to.  However it appears niether the
generic code or the microblaze code modifies what fr_opcode points to, so this
code should be safe.  So we unfortunately need to cast to char * when passing
an argument to frag_var () but otherwise microblaze can itself point to these
strings with const char *.

gas/ChangeLog:

2016-03-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-microblaze.c (md_assemble): Cast opc to char * when calling
	frag_var ().
2016-03-24 08:00:44 -04:00
Trevor Saunders eda6e9a4a2 localize string returned from visium's md_atof ()
I'm not sure the string it returns is particularly useful, or better than the
string returned by other atof implementations on failure, but given the others
return a localized string it seems like this one should too.

gas/ChangeLog:

2016-03-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-visium.c (md_atof): Localize the string returned on
	failure.
2016-03-24 07:58:43 -04:00
Trevor Saunders b9bb4a9356 make more variables const
gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-h8300.c (h8300_elf_section): Add const qualifiers.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-m68hc11.c (md_begin): Likewise.
	(print_opcode_list): Likewise.
	* config/tc-msp430.c (msp430_section): Likewise.
	* config/tc-score.c (struct s3_insn_to_dependency): Likewise.
	(s3_build_dependency_insn_hsh): Likewise.
	* config/tc-score7.c (struct s7_insn_to_dependency): Likewise.
	(s7_build_dependency_insn_hsh): Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
	(subsym_get_arg): Likewise.
	* config/tc-xtensa.c (struct suffix_reloc_map): Likewise.
	(get_directive): Likewise.
	(cache_literal_section): Likewise.
	* config/xtensa-relax.c: Likewise.
	* symbols.c (symbol_create): Likewise.
	(local_symbol_make): Likewise.
	(symbol_relc_make_expr): Likewise.

include/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/i960.h: Add const qualifiers.
	* opcode/tic4x.h (struct tic4x_inst): Likewise.
2016-03-22 19:16:06 -04:00
Trevor Saunders 986d894b2a tc-pdp11.c: remove useless code
if the condition is true then we know that str already points to a'\0' in the
string passed to the function.  Since we know the latter part of the function
doesn't modify that string, and str already points to a null byte there's no
point in changing str to point to a literal empty string.

gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-pdp11.c (md_assemble): Remove useless if and assignment to
	str.
2016-03-22 19:14:17 -04:00
Trevor Saunders 74b4e47aa6 tc-sparc.c: get rid of wierd usage of strchr ()
This lets us avoid assigning a literal to a char *, and perhaps more
importantly makes it clearer what is going on here.

gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr ()
	call with a switch.
2016-03-22 19:12:00 -04:00
Trevor Saunders 0a433ebc90 use do_align () directly in tc-ia64.c
gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-ia64.c (ia64_do_align): Remove.
	(ia64_cons_align): Call do_align () directly.
	(dot_proc): Likewise.
	(stmt_float_cons): Likewise.
2016-03-22 19:08:50 -04:00
Trevor Saunders 8860a416a2 replace some raw xmalloc / xrealloc with the XNEW* macros
This increases consistancy of how we allocate memory, and always casting the
result to the proper type.  It also helps make sure we get any use of sizeof on
the result type correct.

gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* listing.c (listing_message): Use XNEW style allocation macros.
	* read.c (read_a_source_file): Likewise.
	(read_symbol_name): Likewise.
	(s_mri_common): Likewise.
	(assign_symbol): Likewise.
	(s_reloc): Likewise.
	(emit_expr_with_reloc): Likewise.
	(s_incbin): Likewise.
	(s_include): Likewise.
	* sb.c (sb_build): Likewise.
	(sb_check): Likewise.
2016-03-22 19:06:39 -04:00
Alan Modra 49636823b0 Fix tic54x regression
One of the tic54x testcases looks for a section alignment of 1.  After
9136aa49 the alignment became 0.  While it happens that an alignment
of 0 is treated as an alignment of 1, there is no reason to not apply
the explicit alignment.

	* write.c (record_alignment): Revert 2016-02-18 change.
2016-03-22 22:48:37 +10:30
Alan Modra 39a0d071ae Remove more alloca calls
* config/tc-alpha.c (load_expression): Replace alloca with xmalloc.
	(emit_jsrjmp, tc_gen_reloc): Likewise.
	* config/tc-i370.c (i370_macro): Likewise.
2016-03-22 22:47:05 +10:30
Nick Clifton 9780e04507 Add -Wstack-usage to the gcc warning flags list, but only if using a sufficiently recent version of gcc.
bfd	* warning.m4 (GCC_WARN_CFLAGS): Only add -Wstack-usage if using a
	sufficiently recent version of GCC.
	* configure: Regenerate.

others	* configure: Regenerate.
2016-03-22 09:41:16 +00:00
Andrew Burgess e23e8ebee3 arc/nps400: Add first nps400 instructions
Adds the first few nps400 instructions.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-0.d: New file.
	* testsuite/gas/arc/nps400-0.s: New file.
	* testsuite/gas/arc/nps400-1.d: New file.
	* testsuite/gas/arc/nps400-1.s: New file.

include/ChangeLog:

	* opcodes/arc.h (insn_class_t): Add BITOP type.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: New file.
	* arc-opc.c: Add top level comment.
	(insert_nps_3bit_dst): New function.
	(extract_nps_3bit_dst): New function.
	(insert_nps_3bit_src2): New function.
	(extract_nps_3bit_src2): New function.
	(insert_nps_bitop_size): New function.
	(extract_nps_bitop_size): New function.
	(arc_flag_operands): Add nps400 entries.
	(arc_flag_classes): Add nps400 entries.
	(arc_operands): Add nps400 entries.
	(arc_opcodes): Add nps400 include.
2016-03-21 16:44:50 +00:00
Andrew Burgess 1ae8ab4714 arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled.  For example:

    adc.n.eq r0,r0,r2

Will assemble without error, yet, upon disassembly, the instruction will
actually be:

    adc.c r0,r0,r2

In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match.  Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.

To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used.  Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags.  However, at present, the class type is never used.  The current
values identify the type of instruction that the flag will be used in,
but this is not required information.

Instead, this commit discards the old flag classes, and introduces 3 new
classes.  The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class.  The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.

The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction.  The
"at most" one means that no flags being present is fine.

The class F_FLAG_REQUIRED is not currently used, but will be soon.  With
this class, exactly one of the flags from this class must be present in
the instruction.  If the flag class contains a single flag, then of
course that flag must be present.  However, if the flag class contained
two or more, then one, and only one of them must be present.

gas/ChangeLog:

	* config/tc-arc.c (find_opcode_match): Move lnflg, and i
	declarations to start of block.  Reset code on all flags before
	attempting to match them.  Handle multiple hits on the same flag.
	Handle flag class.
	* testsuite/gas/arc/asm-errors.d: New file.
	* testsuite/gas/arc/asm-errors.err: New file.
	* testsuite/gas/arc/asm-errors.s: New file.

include/ChangeLog:

	* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
	new classes instead.

opcodes/ChangeLog:

	* arc-opc.c (arc_flag_classes): Convert all flag classes to use
	the new class enum values.
2016-03-21 16:44:50 +00:00
Andrew Burgess 8699fc3e88 arc: Add nps400 machine type, and assembler flag.
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type.  All
other changes are just adding handling of the new machine type into the
relevant places.

The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set.  This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.

bfd/ChangeLog:

	* archures.c (bfd_mach_arc_nps400): Define.
	* bfd-in2.h: Regenerate.
	* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
	some existing entries to make space.
	* elf32-arc.c (arc_elf_object_p): Add nps400 case.
	(arc_elf_final_write_processing): Likewise.

binutils/ChangeLog:

	* readelf.c (decode_ARC_machine_flags): Handle nps400.

gas/ChangeLog:

	* config/tc-arc.c (cpu_types): Add nps400 entry.
	(check_zol): Handle nps400.

include/ChangeLog:

	* elf/arc.h (E_ARC_MACH_NPS400): Define.
	* opcode/arc.h (ARC_OPCODE_NPS400): Define.

opcodes/ChangeLog:

	* arc-dis.c (print_insn_arc): Handle nps400.
2016-03-21 16:44:49 +00:00
Andrew Burgess a9522a2168 arc: Remove EF_ARC_CPU_GENERIC constant.
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.

There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value.  This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.

Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.

After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in.  The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures).  The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2).  However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.

As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI.  This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same.  For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.

bfd/ChangeLog:

	* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
	EF_ARC_CPU_GENERIC.
	(arc_elf_final_write_processing): Don't bother setting cpu field
	in e_flags, this will have been set elsewhere.

binutils/ChangeLog:

	* readelf.c (get_machine_flags): Move arc processing into...
	(decode_ARC_machine_flags): ... new function.  Remove use of
	EF_ARC_CPU_GENERIC, change default case from "generic arc" to
	"unknown arc".  Merged ABI printing between two machine types.

gas/ChangeLog:

	* config/tc-arc.c (arc_select_cpu): Remove use of
	EF_ARC_CPU_GENERIC.

include/ChangeLog:

	* elf/arc.h (EF_ARC_CPU_GENERIC): Delete.  Update related comment.
2016-03-21 16:44:49 +00:00
Andrew Burgess 24740d83e4 arc/gas: default mach is arc700, initialised in md_begin
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice).  This will reduce the amount of change needed in a later
patch.

At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants.  There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.

binutils/ChangeLog:

	* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
	to the architecture list.

gas/ChangeLog:

	* config/tc-arc.c (arc_target): Delay initialisation until
	arc_select_cpu.
	(arc_target_name): Likewise.
	(arc_features): Likewise.
	(arc_mach_type): Likewise.
	(cpu_types): Remove "all" entry.
	(arc_select_cpu): New function, most of the content is from...
	(md_parse_option): ... here.  Call new arc_select_cpu.
	(md_begin): Call arc_select_cpu if needed, default is now arc700.

include/ChangeLog:

	* opcode/arc.h (ARC_OPCODE_BASE): Delete.

opcodes/ChangeLog:

	* arc-opc.c (BASE): Delete.
2016-03-21 16:44:49 +00:00
Andrew Burgess 62f6f9c28a gas/arc: Fix test for big-endian arc
The inline-data test checks the specific bytes laid down by the
assembler, and so relies on the endianness of the target.  I could
change the expected results to be endian agnostic, however, I worried
that a bug in the assembler that gets the endianness wrong would then
slip through.  Instead I add a new test for big-endian arc, and restrict
the existing test to little-endian arc.

gas/ChangeLog:

	* testsuite/gas/arc/inline-data-1.d: Add target restriction.
	* testsuite/gas/arc/inline-data-2.d: New file.
2016-03-21 16:44:11 +00:00
Nick Clifton e1fa016350 Remove use of alloca.
bfd	* warning.m4 (GCC_WARN_CFLAGS): Add -Wstack-usage=262144
	* configure: Regenerate.
	* elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Replace use of
	alloca with call to xmalloc.
	* elf32-nds32.c: Likewise.
	* elf64-hppa.c: Likewise.
	* elfxx-mips.c: Likewise.
	* pef.c: Likewise.
	* pei-x86_64.c: Likewise.
	* som.c: Likewise.
	* xsym.c: Likewise.

binutils * dlltool.c: Replace use of alloca with call to xmalloc.
	* dllwrap.c: Likewise.
	* nlmconv.c: Likewise.
	* objdump.c: Likewise.
	* resrc.c: Likewise.
	* winduni.c: Likewise.
	* configure: Regenerate.

gas	* atof-generic.c: Replace use of alloca with call to xmalloc.
	* cgen.c: Likewise.
	* dwarf2dbg.c: Likewise.
	* macro.c: Likewise.
	* remap.c: Likewise.
	* stabs.c: Likewise.
	* symbols.c: Likewise.
	* config/obj-elf.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-avr.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-ppc.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-tic30.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/te-vms.c: Likewise.
	* configure: Regenerate.

ld	* emultempl/msp430.em: Replace use of alloca with call to xmalloc.
	* plugin.c: Likewise.
	* pe-dll.c: Likewise.
2016-03-21 16:31:46 +00:00
Trevor Saunders bad6e36d96 tc-i386.c: store encoded instructions in unsigned char[]
char can be a signed type, and some of the values in these arrays are greater
than 0x80 which means they are outside of the range a signed char can store.
Fortunately it seems most compilers handle this in the obvious way by storing
the same bits as a negative number, but this is wierd and easily fixed.

gas/ChangeLog:

2016-03-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* tc-i386.c (f32_1): Change type to unsigned char[].
	(f32_2): Likewise.
	(f32_3): Likewise.
	(f32_4): Likewise.
	(f32_5): Likewise.
	(f32_6): Likewise.
	(f32_7): Likewise.
	(f32_8): Likewise.
	(f32_9): Likewise.
	(f32_10): Likewise.
	(f32_11): Likewise.
	(f32_12): Likewise.
	(f32_13): Likewise.
	(f32_14): Likewise.
	(f16_3): Likewise.
	(f16_4): Likewise.
	(f16_5): Likewise.
	(f16_6): Likewise.
	(f16_7): Likewise.
	(f16_8): Likewise.
	(jump_31): Likewise.
	(f32_patt): Likewise.
	(f16_patt): Likewise.
	(alt_3): Likewise.
	(alt_4): Likewise.
	(alt_5): Likewise.
	(alt_6): Likewise.
	(alt_7): Likewise.
	(alt_8): Likewise.
	(alt_9): Likewise.
	(alt_10): Likewise.
	(alt_patt): Likewise.
2016-03-20 13:22:55 -04:00
Nick Clifton 30fab42184 Update description of AArch64 assembler directives.
gas	* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
	.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
	.tlsdescldr and .xword directives.
2016-03-18 17:30:12 +00:00
Nick Clifton 8678914fcb Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.
PR target/19721
opcodes	* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
	of MOV insn that aliases an ORR insn.

gas	* testsuite/gas/aarch64/pr19721.s: New test source file.
	* testsuite/gas/aarch64/pr19721.d: New test driver file.
2016-03-18 17:04:07 +00:00
Nick Clifton 6387924ae3 Fix generation of as.1 manual page so that it can be converted to DocBook format.
gas	* doc/as.texinfo: Place the target specific command line options
	into their own man page section.

etc	* texi2pod.pl: Add TARGET to the list of recognised man page
	sections.
2016-03-18 13:07:33 +00:00
Alan Modra 5dafb246a1 testsuite/ChangeLog is no longer supposed to exist
move entries to main ChangeLog
2016-03-17 09:59:13 +10:30
Jiong Wang cc93330137 [ARM] Support ARMv8.2 FP16 simd instructions
gas/
	* config/tc-arm.c (N_S_32): New.
	(N_F_16_32): Likewise.
	(N_SUF_32): Support N_F16.
	(N_IF_32): Likewise.
	(neon_dyadic_misc): Likewise.
	(do_neon_cmp): Likewise.
	(do_neon_cmp_inv): Likewise.
	(do_neon_mul): Likewise.
	(do_neon_fcmp_absolute): Likewise.
	(do_neon_step): Likewise.
	(do_neon_abs_neg): Likewise.
	(CVT_FLAVOR_VAR): Likewise.
	(do_neon_cvt_1): Likewise.
	(do_neon_recip_est): Likewise.
	(do_vmaxnm): Likewise.
	(do_vrint_1): Likewise.
	(neon_check_type): Check architecture support for FP16 extension.
	(insns): Update comments.
	* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
	* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
	arm mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
	thumb mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
	error file.

opcode/
	* arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-03-16 16:11:59 +00:00
Nick Clifton 5f2b6bc955 Fix checking bignum values that are being inserted into byte sized containers.
* read.c (emit_expr_with_reloc): Add code check a bignum with
	nbytes == 1.
	* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
	other than 32-bits.
	* testsuite/gas/elf/bignum.s: New test source file.
	* testsuite/gas/elf/bignum.d: New test driver file.
	* testsuite/gas/elf/elf.exp: Run the new test.
2016-03-16 11:33:55 +00:00
Ulrich Drepper 4bde3cdd70 Update x86 register name documentation.
* doc/c-i386.texi (Register Naming): Update to details of the
        latest architecture version.
2016-03-15 11:00:28 +00:00
Mickael Guene a9f02af88d PR gas/19744: Thumb-1 pcrop relocations don't work on Thumb-2 targets
gas/
	* config/tc-arm.c (do_arit): Protect against bad relocations usage.
	(do_mov): Likewise.
	(do_t_add_sub): Allow pcrop relocations for Thumb-2 targets.
	(do_t_mov_cmp): Likewise.
	(do_t_add_sub): Protect against bad relocations usage.
	(do_t_mov_cmp): Likewise.

	gas/testsuite/
	* gas/arm/adds-thumb1-reloc-local-armv7-m.s: New.
	* gas/arm/adds-thumb1-reloc-local-armv7-m.d: New.
	* gas/arm/movs-thumb1-reloc-local-armv7-m.s: New.
	* gas/arm/movs-thumb1-reloc-local-armv7-m.d: New.

	ld/
	* testsuite/ld-arm/arm-elf.exp: New tests.
	* testsuite/ld-arm/thumb1-adds-armv7-m.s: New.
	* testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
2016-03-10 17:06:35 +01:00
Trevor Saunders aa8a08637e fixup -Wshadow warnings on gcc-4.7
gcc 4.7 complains about variables that shadow function names, which now happens
in tc-arm.c because there is a global function do_align (), and local variables
do_align.  The simplest fix for this seems to be to rename those variables to
do_alignment.

gas/ChangeLog:

2016-03-09  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-arm.c (neon_alignment_bit): Rename do_align to
	do_alignment.
	(do_neon_ld_st_lane): Likewise.
	(do_neon_ld_dup): Likewise.
2016-03-09 09:29:17 -05:00
Claudiu Zissulescu 72f3b6aae7 [ARC] Allow non-instruction relocations within .text sections
bfd/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32.
	(arc_bfd_put_32): Becomes an alias for bfd_put_32.
	(arc_elf_howto_init): Added assert to validate relocations.
	(get_middle_endian_relocation): Delete.
	(middle_endian_convert): New function.
	(ME): Redefine, now does nothing.
	(IS_ME): New define.
	(arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO'
	definition to call middle_endian_convert.  Add a new local
	variable and make use of this throughout. Added call to
	arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations.

gas/
2016-03-08  Andrew Burgess  <andrew.burgess@embecosm.com>

	* testsuite/gas/arc/inline-data-1.d: New file.
	* testsuite/gas/arc/inline-data-1.s: New file.

include/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf/arc-reloc.def: Add a call to ME within the formula for each
	relocation that requires middle-endian correction.
2016-03-08 14:19:52 +01:00
Thomas Preud'homme 5f47401071 [ARM] Add support for Cortex-R8
2016-03-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

gas/
    * config/tc-arm.c (arm_cpus): Add cortex-r8.
    * doc/c-arm.texi: Add cortex-r8.
2016-03-07 17:35:29 +00:00
Trevor Saunders f86f586366 Add const qualifiers at various places.
opcodes	* mcore-opc.h: Add const qualifiers.
	* microblaze-opc.h (struct op_code_struct): Likewise.
	* sh-opc.h: Likewise.
	* tic4x-dis.c (tic4x_print_indirect): Likewise.
	(tic4x_print_op): Likewise.

include	* opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
	* opcode/h8300.h (struct h8_opcode): Likewise.
	* opcode/hppa.h (struct pa_opcode): Likewise.
	* opcode/msp430.h: Likewise.
	* opcode/spu.h (struct spu_opcode): Likewise.
	* opcode/tic30.h (struct _register): Likewise.
	* opcode/tic4x.h (struct tic4x_register): Likewise.
	(struct tic4x_cond): Likewise.
	(struct tic4x_indirect): Likewise.
	(struct tic4x_inst): Likewise.
	* opcode/visium.h (struct reg_entry): Likewise.

gas	* config/tc-arc.c: Add const qualifiers.
	* config/tc-h8300.c (md_begin): Likewise.
	* config/tc-ia64.c (print_prmask): Likewise.
	* config/tc-msp430.c (msp430_operands): Likewise.
	* config/tc-nds32.c (struct suffix_name): Likewise.
	(struct nds32_parse_option_table): Likewise.
	(struct nds32_set_option_table): Likewise.
	(do_pseudo_pushpopm): Likewise.
	(do_pseudo_pushpop_stack): Likewise.
	(nds32_relax_relocs): Likewise.
	(nds32_flag): Likewise.
	(struct nds32_hint_map): Likewise.
	(nds32_find_reloc_table): Likewise.
	(nds32_match_hint_insn): Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-sh.c (get_specific): Likewise.
	* config/tc-tic30.c: Likewise.
	* config/tc-tic4x.c (tic4x_inst_add): Likewise.
	(tic4x_indirect_parse): Likewise.
	* config/tc-vax.c (vax_cons): Likewise.
	* config/tc-z80.c (struct reg_entry): Likewise.
	* config/tc-epiphany.c (md_assemble): Adjust.
	(epiphany_assemble): New function.
	(epiphany_elf_section_rtn): Call do_align directly.
	(epiphany_elf_section_text): Likewise.
	* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
	(ip2k_elf_section_text): Likewise.
	* read.c (do_align): Make it not static.
	* read.h (do_align): New prototype.
2016-03-07 15:16:28 +00:00
Matthew Wahab 9411fd44aa [ARM] Build attributes for ARMv8.1-A AdvSIMD
binutils/
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* readelf.c (arm_attry_tag_FP_arch): Add "NEON for ARMv8.1".

gas/
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (aeabi_set_public_attributes): Emit attribute
	for ARMv8.1 AdvSIMD use.
	* testsuite/gas/arm/attr-march-armv8-a+rdma.d: New.
	* testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New.

Change-Id: I3c356e0681b97df2f9c0dabd7c0fd1b441cc2755
2016-03-04 14:16:48 +00:00
Matthew Wahab 643afb90da [ARM] Add feature check for ARMv8.1 AdvSIMD instructions.
gas/
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
	feature.
	(record_feature_use): New.
	(mark_feature_used): Use record_feature_use.
	(do_neon_qrdmlah): New.
	(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
	variants.
	(arm_extensions): Put into alphabetical order.  Re-indent "simd"
	and "rdma" entries.  Fix the incorrect merge value for "+rdma".
	* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
	* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
	Make source file explicit.
	* testsuite/gas/arm/armv8-a+rdma.l: New.
	* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
	directives.  Fix white-space.
	* testsuite/gas/arm/armv8_1-a+simd.d: New.

include/opcode
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
	(ARM_CPU_HAS_FEATURE): Add comment.

Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-04 11:32:04 +00:00
H.J. Lu 25aa3689f0 Adjust testsuite/gas/i386/x86_64-intel.d for COFF
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
2016-03-02 05:15:32 -08:00
Claudiu Zissulescu 841fdfcdd9 [ARC] Local symbols relocation cleanup
bfd/
2016-02-29  Cupertino Miranda  <cmiranda@synopsys.com>

	* elf32-arc.c (elf_arc_relocate_section): Added rules to fix the
	relocation addend when sections get merged.

gas/
2016-02-29  Cupertino Miranda  <cmiranda@synopsys.com>
	    Claudiu Zissulescu  <Claudiu.Zissulescu@synopsys.com>

        * config/tc-arc.c (arc_extra_reloc): Change size to 0.
        (tc_arc_fix_adjustable): Changed default return value to 1.
        * testsuite/gas/arc/j.d: Updated expected symbol
        * testsuite/gas/arc/jl.d: Likewise
        * testsuite/gas/arc/relax-avoid1.d: Likewise
        * testsuite/gas/arc/st.d: Likewise

ld/
2016-02-29 Cupertino Miranda  <cmiranda@synopsys.com>

	* testsuite/ld-elf/merge.d: Removed xfail for ARC.
	* testsuite/ld-elf/merge2.d: Likewise.
	* testsuite/ld-elf/merge3.d: Likewise.
2016-02-29 16:51:11 +01:00
Claudiu Zissulescu 7e4588997e [ARC] General fixes.
bfd/
2016-02-29  Cupertino Miranda <Cupertino.Miranda@synopsys.com>

	* elf32-arc.c (arc_elf_final_write_processing): Add condition to
	the flag change.
        (elf_arc_relocate_section): Fixes and conditions to support PIE.
	Assert for code sections dynamic relocs.

gas/
2016-02-29  Claudiu Zissulescu  <Claudiu.Zissulescu@synopsys.com>

	* config/tc-arc.c: Enable code density instructions for ARC EM.

ld/
2016-02-29  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>

	* scripttempl/arclinux.sc: Force .tdata and .tbss to always be
	generated.
2016-02-29 16:07:48 +01:00
Joel Sherrill 12a132db16 Add aarch64-*-rtems* target 2016-02-26 14:07:27 -06:00
H.J. Lu 11e5f1ec54 Add ChangeLog entries for PR ld/19645 2016-02-26 06:44:03 -08:00
H.J. Lu b8871f357f Properly implement STT_COMMON
The BFD configure option, --enable-elf-stt-common, can't be to used to
verify STT_COMMON implementation with the normal binutils build.  Instead,
this patch removes it from BFD.  It adds --elf-stt-common=[no|yes] to ELF
assembler/objcopy and adds -z common/-z nocommon to ld.

A configure option, --enable-elf-stt-common, is added to gas to specify
whether ELF assembler should generate common symbols with the STT_COMMON
type by default.

Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF
common symbols.

bfd/

	PR ld/19645
	* bfd.c (bfd): Change flags to 20 bits.
	(BFD_CONVERT_ELF_COMMON): New.
	(BFD_USE_ELF_STT_COMMON): Likewise.
	(BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.
	(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
	* configure.ac: Remove --enable-elf-stt-common.
	* elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for
	common symbol depending on BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.
	* elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for
	STT_COMMON.
	* elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check
	STT_COMMON.
	(elf_link_convert_common_type): New function.
	(elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for
	common symbol depending on BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.  Set sym.st_info after sym.st_shndx.
	* elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON
	and BFD_USE_ELF_STT_COMMON to object_flags.
	(TARGET_LITTLE_SYM): Likewise.
	* syms.c (BSF_KEEP_G): Renamed to ...
	(BSF_ELF_COMMON): This.
	* bfd-in2.h: Regenerated.
	* config.in: Likewise.
	* configure: Likewise.

binutils/

	PR ld/19645
	* NEWS: Mention --elf-stt-common= for objcopy.
	* doc/binutils.texi: Document --elf-stt-common= for objcopy.
	* objcopy.c (do_elf_stt_common): New.
	(command_line_switch): Add OPTION_ELF_STT_COMMON.
	(copy_options): Add --elf-stt-common=.
	(copy_usage): Add --elf-stt-common=.
	(copy_object): Also check do_elf_stt_common for ELF targets.
	(copy_file): Handle do_elf_stt_common.
	(copy_main): Handle OPTION_ELF_STT_COMMON.
	* readelf.c (apply_relocations): Support STT_COMMON.
	* testsuite/binutils-all/common-1.s: New file.
	* testsuite/binutils-all/common-1a.d: Likewise.
	* testsuite/binutils-all/common-1b.d: Likewise.
	* testsuite/binutils-all/common-1c.d: Likewise.
	* testsuite/binutils-all/common-1d.d: Likewise.
	* testsuite/binutils-all/common-1e.d: Likewise.
	* testsuite/binutils-all/common-1f.d: Likewise.
	* testsuite/binutils-all/common-2.s: Likewise.
	* testsuite/binutils-all/common-2a.d: Likewise.
	* testsuite/binutils-all/common-2b.d: Likewise.
	* testsuite/binutils-all/common-2c.d: Likewise.
	* testsuite/binutils-all/common-2d.d: Likewise.
	* testsuite/binutils-all/common-2e.d: Likewise.
	* testsuite/binutils-all/common-2f.d: Likewise.
	* testsuite/binutils-all/objcopy.exp
	(objcopy_test_elf_common_symbols): New proc.
	Run objcopy_test_elf_common_symbols for ELF targets

gas/

	PR ld/19645
	* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
	for ELF assemblers.
	* as.c (flag_use_elf_stt_common): New.
	(show_usage): Add --elf-stt-common=.
	(option_values): Add OPTION_ELF_STT_COMMON.
	(std_longopts): Add --elf-stt-common=.
	(parse_args): Handle --elf-stt-common=.
	* as.h (flag_use_elf_stt_common): New.
	* config.in: Regenerated.
	* configure: Likewise.
	* configure.ac: Add --enable-elf-stt-common and define
	DEFAULT_GENERATE_ELF_STT_COMMON.
	* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
	and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
	* doc/as.texinfo: Document --elf-stt-common=.
	* testsuite/gas/elf/common3.s: New file.
	* testsuite/gas/elf/common3a.d: Likewise.
	* testsuite/gas/elf/common3b.d: Likewise.
	* testsuite/gas/elf/common4.s: Likewise.
	* testsuite/gas/elf/common4a.d: Likewise.
	* testsuite/gas/elf/common4b.d: Likewise.
	* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
	* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
	* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
	and common4b.
	* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
	* testsuite/gas/i386/dw2-compress-3a.d: This.  Pass
	--elf-stt-common=no to as.
	* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
	* testsuite/gas/i386/dw2-compressed-3a.d: This.  Pass
	--elf-stt-common=no to as.
	* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
	dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
	of dw2-compress-3 and dw2-compressed-3.

include/

	PR ld/19645
	* bfdlink.h (bfd_link_elf_stt_common): New enum.
	(bfd_link_info): Add elf_stt_common.

ld/

	PR ld/19645
	* NEWS: Mention -z common/-z nocommon for ELF targets.
	* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle
	-z common and -z nocommon.
	* ld.texinfo: Document -z common/-z nocommon.
	* lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon.
	* testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and
	--elf-stt-common=yes with assembler.
	* testsuite/ld-elfcomm/common-1.s: New file.
	* testsuite/ld-elfcomm/common-1a.d: Likewise.
	* testsuite/ld-elfcomm/common-1b.d: Likewise.
	* testsuite/ld-elfcomm/common-1c.d: Likewise.
	* testsuite/ld-elfcomm/common-1d.d: Likewise.
	* testsuite/ld-elfcomm/common-1e.d: Likewise.
	* testsuite/ld-elfcomm/common-1f.d: Likewise.
	* testsuite/ld-elfcomm/common-2.s: Likewise.
	* testsuite/ld-elfcomm/common-2a.d: Likewise.
	* testsuite/ld-elfcomm/common-2b.d: Likewise.
	* testsuite/ld-elfcomm/common-2c.d: Likewise.
	* testsuite/ld-elfcomm/common-2d.d: Likewise.
	* testsuite/ld-elfcomm/common-2e.d: Likewise.
	* testsuite/ld-elfcomm/common-2f.d: Likewise.
	* testsuite/ld-elfcomm/common-3a.rd: Likewise.
	* testsuite/ld-elfcomm/common-3b.rd: Likewise.
	* testsuite/ld-i386/pr19645.d: Likewise.
	* testsuite/ld-i386/pr19645.s: Likewise.
	* testsuite/ld-x86-64/largecomm-1.s: Likewise.
	* testsuite/ld-x86-64/largecomm-1a.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1b.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1c.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1d.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1e.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1f.d: Likewise.
	* testsuite/ld-x86-64/pr19645.d: Likewise.
	* testsuite/ld-x86-64/pr19645.s: Likewise.
	* testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes
	with assembler.
	(assembler_generates_commons): Removed.
	Run -z common/-z nocommon tests.  Run *.d tests.
	* testsuite/ld-i386/i386.exp: Run pr19645.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with
	assembler.  Test STT_COMMON with readelf.
2016-02-26 05:01:34 -08:00
Trevor Saunders e0471c16c5 Convert more variables to a constant form.
* as.c (select_emulation_mode): Add const qualifiers.
	* as.h: Likewise.
	* config/bfin-defs.h: Likewise.
	* config/bfin-parse.y: Likewise.
	* config/rx-parse.y: Likewise.
	* config/tc-aarch64.c (struct aarch64_option_table): Likewise.
	(struct aarch64_cpu_option_table): Likewise.
	(struct aarch64_arch_option_table): Likewise.
	(struct aarch64_option_cpu_value_table): Likewise.
	(struct aarch64_long_option_table): Likewise.
	(struct aarch64_option_abi_value_table): Likewise.
	* config/tc-arm.c (struct reloc_entry): Likewise.
	(tc_gen_reloc): Likewise.
	(struct arm_option_table): Likewise.
	(struct arm_legacy_option_table): Likewise.
	(struct arm_cpu_option_table): Likewise.
	(struct arm_arch_option_table): Likewise.
	(struct arm_option_extension_value_table): Likewise.
	(struct arm_option_fpu_value_table): Likewise.
	(struct arm_option_value_table): Likewise.
	(struct arm_long_option_table): Likewise.
	* config/tc-avr.c (struct avr_opcodes_s): Likewise.
	(struct mcu_type_s): Likewise.
	(struct exp_mod_s): Likewise.
	(avr_operand): Likewise.
	(avr_operands): Likewise.
	* config/tc-d10v.c (md_begin): Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-fr30.c (fr30_is_colon_insn): Likewise.
	* config/tc-ft32.c (parse_condition): Likewise.
	* config/tc-h8300.c (do_a_fix_imm): Likewise.
	* config/tc-hppa.c (pa_ip): Likewise.
	(hppa_regname_to_dw2regnum): Likewise.
	* config/tc-i370.c (i370_elf_suffix): Likewise.
	* config/tc-i960.c (struct tabentry): Likewise.
	* config/tc-m32r.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-m68k.h: Likewise.
	* config/tc-mcore.c (parse_psrmod): Likewise.
	* config/tc-metag.c (struct metag_core_option): Likewise.
	(struct metag_long_option): Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c (macro): Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-msp430.c (struct rcodes_s): Likewise.
	(struct hcodes_s): Likewise.
	(md_parse_option): Likewise.
	* config/tc-ns32k.c (struct ns32k_option): Likewise.
	(optlist): Likewise.
	* config/tc-ppc.c (ppc_elf_suffix): Likewise.
	(tc_ppc_regname_to_dw2regnum): Likewise.
	* config/tc-ppc.h: Likewise.
	* config/tc-rl78.c: Likewise.
	* config/tc-rx.c (struct cpu_type): Likewise.
	* config/tc-sh.c (sh_regname_to_dw2regnum): Likewise.
	* config/tc-sparc.c (struct priv_reg_entry): Likewise.
	(sparc_ip): Likewise.
	* config/tc-spu.c (insn_fmt_string): Likewise.
	* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
	* config/tc-v850.c: Likewise.
	* config/tc-visium.c (struct visium_arch_option_table): Likewise.
	(struct visium_long_option_table): Likewise.
	* config/tc-xgate.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* read.c (add_include_dir): Likewise.
	* read.h: Likewise.
2016-02-25 16:55:21 +00:00
Andrew Burgess e6e7b7c49f gas: Update tests for big-endian arc targets
Some gas tests are excluded for arc targets using the pattern arc-*-*,
however this only covers little endian arc targets.  This commit extends
the patter to cover big endian arc targets, the pattern is now arc*-*-*.

gas/ChangeLog:

	* testsuite/gas/all/gas.exp: Change target pattern to cover
	arceb-*.
	* testsuite/gas/all/redef3.d: Likewise.
	* testsuite/gas/elf/elf.exp: Likewise.
2016-02-25 10:46:41 +00:00
Renlin Li 9db2f6b426 [GAS][ARM][3/3]Add armv8.2 fp16 scalar instruction support. Based on SE_H instruction shape.
gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* config/tc-arm.c (BAD_FP16): New error message macro.
	(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
	fp16 scalar instructions.
	(neon_check_type): Allow different size from key.
	(do_vfp_nsyn_add_sub): Add support SE_H shape support.
	(try_vfp_nsyn): Likewise.
	(do_vfp_nsyn_mla_mls): Likewise.
	(do_vfp_nsyn_fma_fms): Likewise.
	(do_vfp_nsyn_ldm_stm): Likewise
	(do_vfp_nsyn_sqrt): Likewise
	(do_vfp_nsyn_div): Likewise
	(do_vfp_nsyn_nmul): Likewise.
	(do_vfp_nsyn_cmp): Likewise.
	(do_neon_shll): Likewise.
	(do_vfp_nsyn_cvt_fpv8): Likewise.
	(do_neon_cvttb_2): Likewise.
	(do_neon_mov): Likewise.
	(do_neon_rshift_round_imm): Likewise.
	(do_neon_ldr_str): Likewise.
	(do_vfp_nsyn_fpv8): Likewise.
	(do_vmaxnm): Likewise.
	(do_vrint_1): Likewise.
	(insns): New entry for vins, vmovx.
	(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
	* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
	* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
	* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
2016-02-24 18:09:02 +00:00
Renlin Li d54af2d070 [GAS][ARM][2/3]Add SE_H shape to represent fp16 type.
gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape.
	(neon_shape_class): New SC_HALF.
	(neon_shape_el): New SE_H.
	(neon_shape_el_size): New size for SE_H.
	(N_F_ALL): New macro to aggregate N_F16, N_F32, N_64.
	(neon_select_shape): Add SE_H support code.
	(el_type_of_type_chk): Use N_F_ALL.
	(do_vfp_nsyn_cvt): Add SE_H shape support.
	(do_neon_cvtz): Likewise.
	(do_neon_cvt_1): Likewise.
	(do_neon_cvttb_1): Likewise.
2016-02-24 14:18:16 +00:00
Renlin Li b0c1177766 [OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
	(print_insn_coprocessor): Support fp16 instruction.

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/copro.d: Adjust output.
	* testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24 14:08:39 +00:00
Renlin Li 3e309328e8 [OPCODES][ARM]Fix mask for a few coprocessor opcodes.
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
	vrint(mpna).

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/mask_1.d: New.
	* testsuite/gas/arm/mask_1.s: New.
2016-02-24 14:02:51 +00:00
Renlin Li 8afc7bea40 [OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
	* testsuite/gas/arm/copro.d: Update.
2016-02-24 14:02:51 +00:00
Kyrylo Tkachov 6735952f7c [ARM][gas] Add support for Cortex-A32
2016-02-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * config/tc-arm.c (arm_cpus): Add entry for cortex-a32.
    * doc/c-arm.texi (ARM Options): Document cortex-a32.
2016-02-24 10:55:09 +00:00
Kyrylo Tkachov ed5491b9a9 [ARM][doc] Document cortex-a17 mcpu option
2016-02-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * doc/c-arm.texi (ARM Options): Document cortex-a17.
2016-02-24 10:53:55 +00:00
H.J. Lu 742e5034ef Skip tests for common directive on hpux
hpux has a non-standard common directive.

	* testsuite/gas/elf/elf.exp: Skip tests for common directive on
	hpux.
2016-02-23 10:40:43 -08:00
Trevor Saunders 3b4dbbbf59 Add more const type qualifiers to GAS sources.
* output-file.c (output_file_create): Make file name argument const.
	(output_file_close): Likewise.
	* output-file.h (output_file_create): Adjust.
	(output_file_close): Likewise.
	* depend.c (quote_string_for_make): Make src argument const char *.
	(register_dependency): Likewise.
	(wrap_output): Likewise.
	* as.h (register_dependency): Adjust.
	* config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to
	as_where ();
	* symbols.c (S_SET_EXTERNAL): Likewise.
	* input-scrub.c (as_where): Return the file name.
	* as.h (as_where): Adjust prototype.
	* app.c (do_scrub_chars): Adjust.
	* cond.c (s_elseif): Likewise.
	(s_else): Likewise.
	(initialize_cframe): Likewise.
	* config/obj-coff.c (obj_coff_init_stab_section): Likewise.
	* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
	* config/obj-som.c (obj_som_init_stab_section): Likewise.
	* config/tc-aarch64.c (output_info): Likewise.
	* config/tc-ia64.c (md_assemble): Likewise.
	(dot_alias): Likewise.
	* config/tc-m68k.c (m68k_frob_label): Likewise.
	* config/tc-mmix.c (s_bspec): Likewise.
	(mmix_handle_mmixal): Likewise.
	* config/tc-rx.c (rx_include): Likewise.
	* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
	(tic54x_adjust_symtab): Likewise.
	* config/tc-xtensa.c (directive_push): Likewise.
	(xtensa_sanity_check): Likewise.
	(xtensa_relax_frag): Likewise.
	(md_convert_frag): Likewise.
	(tinsn_to_slotbuf): Likewise.
	* dwarf2dbg.c (dwarf2_where): Likewise.
	* ecoff.c (add_file): Likewise.
	(ecoff_generate_asm_lineno): Likewise.
	* expr.c (make_expr_symbol): Likewise.
	* frags.c (frag_new): Likewise.
	(frag_var_init): Likewise.
	* listing.c (listing_newline): Likewise.
	* messages.c (identify): Likewise.
	(as_show_where): Likewise.
	(as_warn_internal): Likewise.
	(as_bad_internal): Likewise.
	* read.c (s_irp): Likewise.
	(s_macro): Likewise.
	(s_reloc): Likewise.
	* stabs.c (stabs_generate_asm_file): Likewise.
	(stabs_generate_asm_lineno): Likewise.
	(stabs_generate_asm_func): Likewise.
	* write.c (fix_new_internal): Likewise.
	* as.h (PRINTF_WHERE_LIKE): Make file name argument const.
	(as_warn_value_out_of_range): Adjust prototype.
	(as_bad_value_out_of_range): Adjust prototype.
	* messages.c (identify): Make file name argument const char *.
	(as_warn_internal): Likewise.
	(as_warn_where): Likewise.
	(as_bad_internal): Likewise.
	(as_bad_where): Likewise.
	(as_internal_value_out_of_range): Likewise.
	(as_warn_value_out_of_range): Likewise.
	(as_bad_value_out_of_range): Likewise.
	* as.h (found_comment_file): Change type to const char *.
	* cond.c (file_line::file): Likewise.
	* config/obj-coff.c (obj_coff_init_stab_section): Make variable const.
	* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
	* config/obj-som.c (obj_som_init_stab_section): Likewise.
	* config/tc-aarch64.c (output_info): Likewise.
	* config/tc-alpha.c (insert_operand): Likewise.
	* config/tc-arc.c (insert_operand): Likewise.
	* config/tc-d30v.c (check_size): Likewise.
	* config/tc-ia64.c (struct alias): Likewise.
	* config/tc-m68k.c (struct label_line): Likewise.
	* config/tc-mcore.c (md_apply_fix): Likewise.
	* config/tc-microblaze.c (md_estimate_size_before_relax): Likewise.
	* config/tc-mips.c (mips16_immed): Likewise.
	* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
	* config/tc-ppc.c (ppc_insert_operand): Likewise.
	* config/tc-rx.c (rx_include): Likewise.
	* config/tc-s390.c (s390_insert_operand): Likewise.
	* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
	(tic54x_adjust_symtab): Likewise.
	* config/tc-tilegx.c (insert_operand): Likewise.
	(apply_special_operator): Likewise.
	* config/tc-tilepro.c (insert_operand): Likewise.
	* config/tc-xtensa.c (directive_push): Likewise.
	* ecoff.c (add_file): Likewise.
	(ecoff_generate_asm_lineno): Likewise.
	* listing.c (listing_newline): Likewise.
	* read.c (s_irp): Likewise.
	* write.c (install_reloc): Likewise.
	* write.h (struct fix): Likewise.
	* input-file.c (file_name): Change type to const char *.
	(saved_file::file_name): Likewise.
	(input_file_open): Change type of argument to const char *.
	* input-file.h (input_file_open): Adjust.
	* input-scrub.c (logical_input_file): change type to const char *.
	(physical_input_file): Likewise.
       	(struct input_save): Adjust.
	(input_scrub_push): Adjust.
	(input_scrub_begin): Adjust.
	(as_where): Adjust.
	* input-scrub.c (input_scrub_new_file): Make file name argument const.
	(input_scrub_include_file): Likewise.
	(new_logical_line_flags): Likewise.
	(new_logical_line): Likewise.
	* as.h: Adjust.
	* frags.h (struct frag): Change type of fr_file to const char *.
	* expr.c (expr_symbol_where): Change type of file argument to
	const char **.
	* expr.h (expr_symbol_where): Likewise.
	* config/tc-i370.c (md_apply_fix): adjust.
	* config/tc-mmix.c (mmix_md_end): Likewise.
	* config/tc-ppc.c (md_apply_fix): Likewise.
	* config/tc-s390.c (md_apply_fix): Likewise.
	* symbols.c (report_op_error): Likewise.
	(resolve_symbol_value): Likewise.
	* config/tc-ia64.c (slot::src_file): Change type to const char *.
	(rsrc::file): Likewise.
	* config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to
	const char *.
	(xtensa_relax_frag): Likewise.
	(md_convert_frag): Likewise.
	(tinsn_to_slotbuf): Likewise.
	* expr.c (expr_symbol_line): Likewise.
	* macro.c (define_macro): Likewise.
	* macro.h (macro_struct): Likewise.
	* messages.c (as_show_where): Likewise.
	* read.c (s_macro): Likewise.
	* stabs.c (stabs_generate_asm_file): Likewise.
	(generate_asm_file): Likewise.
	(stabs_generate_asm_lineno): Likewise.
	* write.h (struct reloc_list): Likewise.
	* input-scrub.c (as_where): Change return type to const char *.
	* as.h (as_wheree): Adjust.
2016-02-22 14:11:27 +00:00
H.J. Lu 8ecb73ddd7 Set BFD compression bits in write_object_file
There is no need to set BFD compression bits for each section.  We
should just set it once in write_object_file.

	* write.c (compress_debug): Move BFD compression bits setting
	to ...
	(write_object_file): Here.
2016-02-21 06:46:11 -08:00
H.J. Lu 200cbe0f46 [i386] Check RegVRex in register_number
Increment register number by 16 if RegVRex is set.

	* config/tc-i386.c (register_number): Check RegVRex.
	* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
	with %zmm19 and %zmm3.
	* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
	* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
2016-02-20 09:23:20 -08:00
Nick Clifton b37283a66b Fix snafu - add missing const declaration to 'string' local variable in s_stab_generic. 2016-02-19 16:15:48 +00:00
Jiong Wang b8ec4e871e [ARM] Add FP16 feature extension for ARMv8.2 architecture
include/
  * opcode/arm.h (ARM_EXT2_FP16_INSN): New.

gas/
  * config/tc-arm.c (arm_ext_fp16): New.
  (arm_extensions): New entry for "fp16".
2016-02-19 14:27:23 +00:00
Nick Clifton 3be64886b5 Prevent seg-fault in gas reading a binary input file.
PR 19630
	* read.c (read_a_source_file): Check for assemble_one returning
	with input_line_pointer set to NULL.
2016-02-19 13:19:57 +00:00
Trevor Saunders 3d13c64701 Change the return type of the rebuffer_line function to void.
* listing.c (rebuffer_line): Change return type to void.
2016-02-19 12:13:08 +00:00
Trevor Saunders cd0bbe6ef9 Add const to various variables in the gas sources.
* symbols.c (decode_local_label_name): Make type a const char *.
	* listing.c (print_source): Make type of p const char *.
	(print_line): Make type of string const	char *.
	(buffer_line): Return const char *.
	(title): Make type const char *.
	(subtitle): Likewise.
	(listing_listing): Make type of p const char *.
	* messages.c (as_internal_value_out_of_range): Make type of prefix
	const char *.
	* stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname
	and string const char *.
	* read.c (_bfd_rel): Make type of name const char *.
	* app.c (out_string): Change type to const char *.
       	(struct app_save::out_string): Likewise.
2016-02-19 12:03:08 +00:00
Dan Gisselquist 9136aa49ab Avoid setting or recording negative alignments when the target stores multiple octets in a single byte.
gas	* read.c (finish_bundle): Avoid recording a negative alignment.
	(do_align): Use unsigned values for n, len and max.  Only create
	a frag if the alignment requirement is greater than the minimum
	byte alignment.  Avoid recording a negative alignment.
	(s_align): Use unsigned values where appropriate.
	(bss_alloc): Use an unsigned value for the alignment.
	(sizeof_sleb128): Add a comment noting that we encode one octet
	per byte, regardless of the value of OCTETS_PER_BYTE_POWER.
	(emit_leb129_expr): Abort if the emitted encoding was longer than
	expected.
	* read.h (output_leb128): Update prototype.
	(sizeof_leb128): Update prototype.
	(bss_alloc): Update prototype.
	* write.c (record_alignment): Use an unsigned value for the
	alignment.  Do not record alignments less than the minimum
	alignment for a byte.
	* write.h (record_alignment): Update prototype.
2016-02-18 09:49:04 +00:00
Max Filippov 4111950f36 xtensa: fix .init/.fini literals moving
Despite the documentation and the comment in xtensa_move_literals, in
the presence of --text-section-literals and --auto-litpools literals are
moved from the separate literal sections into .init and .fini, because
the check in the xtensa_move_literals is incorrect.

This moving was broken with introduction of auto litpools: some literals
now may be lost. This happens because literal frags emitted from .init
and .fini are not closed when new .literal_position marks new literal
pool. Then frag_align(2, 0, 0) changes type of the last literal frag to
rs_align. rs_align frags are skipped in the xtensa_move_literals. As a
result fixups against such literals are not moved out of .init.literal/
.fini.literal sections producing the following assembler error:

  test.S: Warning: fixes not all moved from .init.literal
  test.S: Internal error!

Fix check for .init.literal/.fini.literal in the xtensa_move_literals
and don't let it move literals from there in the presence of
--text-section-literals or --auto-litpools.

2016-02-17  Max Filippov  <jcmvbkbc@gmail.com>
gas/
	* config/tc-xtensa.c (xtensa_move_literals): Fix check for
	.init.literal/.fini.literal section name.
	* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
	list of xtensa tests.
	* testsuite/gas/xtensa/init-fini-literals.d: New file:
	init-fini-literals test result patterns.
	* testsuite/gas/xtensa/init-fini-literals.s: New file:
	init-fini-literals test.
2016-02-17 23:08:15 +03:00
Nick Clifton b27c40ec1f Update list of known MSP430 MCUs.
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
	devices.csv file as of March 2016.
2016-02-17 09:55:32 +00:00
Claudiu Zissulescu 726c18e1c8 [ARC] Enable .cfi_* pseudo-ops.
gas/
2016-02-16  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (tc_arc_frame_initial_instructions): New
	function.
	(tc_arc_regname_to_dw2regnum): Likewise.
	* config/tc-arc.h (TARGET_USE_CFIPOP): Define
	(tc_cfi_frame_initial_instructions): Likewise.
	(tc_regname_to_dw2regnum): Likewise.

gas/testsuite
2016-02-16  Claudiu Zissulescu  <claziss@synopsys.com>

	* gas/cfi/cfi-arc-1.d: New file.
	* gas/cfi/cfi-arc-1.s: Likewise.
	* gas/cfi/cfi.exp: Allow running tests for arc.

binutils/
2016-02-16  Claudiu Zissulescu  <claziss@synopsys.com>

	* readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
2016-02-16 15:56:04 +01:00
Trevor Saunders 9406ee731d Remove documentation of deleted function S_IS_EXTERN. 2016-02-16 10:37:32 +00:00
Nick Clifton eda683bbaa Fix formatting problems caused by previous update to as.texinfo.
* doc/as.texinfo (Section): Fix up texinfo snafus in previous
	update.
2016-02-16 10:35:54 +00:00
Renlin Li 671eeb286f [PR19620][GAS][AArch64]Remove mov[z,k,n] relocation symbol name restriction.
In AArch64 gas, register name or string starts with valid register name
is not allowed as symbol name for mov[z,k,n] instruction.
This patch removes the restriction.

gas/
	PR gas/19620
	* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
	* testsuite/gas/aarch64/movw_label.d: New.
	* testsuite/gas/aarch64/movw_label.s: New.
2016-02-16 10:04:41 +00:00
H.J. Lu 804021fbed Fix typos in gas/ChangeLog 2016-02-15 16:11:23 -08:00
Nick Clifton 58cda01864 Fix changelog entry for previous delta. 2016-02-15 16:54:49 +00:00
Vinay Kumar G 6439ea1a88 Correct opcode generated for RX indirect MOVs without an offset.
PR gas/19665
	* config/rx-parse.y (MOV):  Opcode generation for index
	register addressing mode.
	* testsuite/gas/rx/rx.exp: Updated for new testcase.
	* testsuite/gas/rx/pr19665.s: New file.
	* testsuite/gas/rx/pr19665.s: New file.
	* testsuite/gas/rx/mov.d: Update expected output.
2016-02-15 16:34:34 +00:00
Nick Clifton 9fb71ee49f Enhance GAS's .section directive so that it can take numeric values for the flags and type fields. (ELF only)
gas	* doc/as.texinfo (.section): Document that numeric values can now
	be used for the flags and type fields of the ELF target's .section
	directive.  Add notes about the restrictions on setting flags and
	types.
	* config/obj-elf.c (obj_elf_change_section): Allow known sections
	to be given processor specific section types.  Allow processor and
	application specific flags of a section to be set after
	definition.
	(obj_elf_parse_section_letters): Handle parsing numeric values.
	(obj_elf_section_type): Handle parsing numeric values.
	(obj_elf_section): Allow numeric type values.
	* config/obj-elf.h (obj_elf_change_section): Update prototype.
	* testsuite/gas/elf/section10.d: New test.
	* testsuite/gas/elf/section10.s: Source file for new test.
	* testsuite/gas/elf/elf.exp: Run the new test.
	* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
	the description of the flags produced by readelf.
	* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
	* NEWS: Mention the new feature.

bfd	* elf-bfd.h (struct bfd_elf_special_section): Use unsigned values
	for length and type fields.  Use a signed value for the
	suffix_length field.

binutils* readelf.c (get_section_type_name): Add hex prefix to offsets
	printed for LOPROC and LOOS values.  Ensure that a result is
	always returned for the V850 target, even when an unrecognised
	processor specific value is encountered.
	(process_section_headers): Display key values in the order in
	which they appear to the user.  Add the "C (compressed)" value to
	the list.

ld	* testsuite/ld-i386/pr12718.d: Remove dependency upon the
	description of the flags produced by readelf.
	* testsuite/ld-i386/pr12921.d: Likewise.
	* testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsbin.rd: Likewise.
	* testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsbindesc.rd: Likewise.
	* testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsdesc.rd: Likewise.
	* testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsgdesc.rd: Likewise.
	* testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsnopic.rd: Likewise.
	* testsuite/ld-i386/tlspic-nacl.rd: Likewise.
	* testsuite/ld-i386/tlspic.rd: Likewise.
	* testsuite/ld-s390/tlsbin.rd: Likewise.
	* testsuite/ld-s390/tlsbin_64.rd: Likewise.
	* testsuite/ld-s390/tlspic.rd: Likewise.
	* testsuite/ld-s390/tlspic_64.rd: Likewise.
	* testsuite/ld-sh/tlsbin-2.d: Likewise.
	* testsuite/ld-sh/tlspic-2.d: Likewise.
	* testsuite/ld-tic6x/common.d: Likewise.
	* testsuite/ld-tic6x/shlib-1.rd: Likewise.
	* testsuite/ld-tic6x/shlib-1b.rd: Likewise.
	* testsuite/ld-tic6x/shlib-1r.rd: Likewise.
	* testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
	* testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
	* testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
	* testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
	* testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
	* testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
	* testsuite/ld-tic6x/static-app-1.rd: Likewise.
	* testsuite/ld-tic6x/static-app-1b.rd: Likewise.
	* testsuite/ld-tic6x/static-app-1r.rd: Likewise.
	* testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
	* testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
	* testsuite/ld-x86-64/ilp32-4.d: Likewise.
	* testsuite/ld-x86-64/pr12718.d: Likewise.
	* testsuite/ld-x86-64/pr12921.d: Likewise.
	* testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
	* testsuite/ld-x86-64/split-by-file.rd: Likewise.
	* testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsbin.rd: Likewise.
	* testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
	* testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsdesc.rd: Likewise.
	* testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsgdesc.rd: Likewise.
	* testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlspic.rd: Likewise.
	* testsuite/ld-xtensa/tlsbin.rd: Likewise.
	* testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-02-15 11:11:46 +00:00
Nick Clifton bd5608dcc6 Allow the .cfi_sections directive to be reissued provided that CFI generation has not yet started.
PR gas/19614
	* dw2gencfi.c (cfi_sections_set): Delay setting this variable
	until it is actually used.
	(cfi_set_sections): Set cfi_sections_set to true.
	(dot_cfi_startproc): Likewise.
	(dot_cfi_endproc): Likewise.
	(dot_cfi_fde_data): Likewise.
	(cfi_finish): Likewise.
	(dot_cfi_sections): Do not set cfi_sections_set.
	* doc/as.texinfo (.cfi_sections): Note that targets can provide
	their own cfi section name.  Also note that the directive can be
	reissued provided that CFI generation has not started.
	* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
	.cfi_endproc directives so that the redefinition of .cfi_sections
	will trigger the generation of the error message.
	* testsuite/gas/mips/compact-eh-err2.l: Update expected line
	number of error message.
2016-02-11 15:30:55 +00:00
Claudiu Zissulescu 4670103e86 Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot <jvanoirs@synopsys.com>

        * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
        (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
        Define.
        (arc_flags, arc_relax_type): New structure.
        * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
	(RELAX_TABLE_ENTRY_MAX): New define.
        (relaxation_state, md_relax_table, arc_relaxable_insns)
	(arc_num_relaxable_ins): New variable.
	(rlx_operand_type, arc_rlx_types): New enums.
	(arc_relaxable_ins): New structure.
        (OPTION_RELAX): New option.
        (arc_insn): New relax member.
        (arc_flags): Remove.
        (relax_insn_p): New function.
        (apply_fixups): Likewise.
        (relaxable_operand): Likewise.
        (may_relax_expr): Likewise.
        (relaxable_flag): Likewise.
        (arc_pcrel_adjust): Likewise.
        (md_estimate_size_before_relax): Implement.
        (md_convert_frag): Likewise.
        (md_parse_option): Handle new mrelax option.
        (md_show_usage): Likewise.
        (assemble_insn): Set relax member.
        (emit_insn0): New function.
        (emit_insn1): Likewise.
        (emit_insn): Handle relaxation case.
	* NEWS: Mention the new relaxation option.
	* doc/c-arc.texi (ARC Options): Document new mrelax option.

gas/testsuite
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>

        * gas/arc/relax-avoid1.d: New file.
        * gas/arc/relax-avoid1.s: Likewise.
        * gas/arc/relax-avoid2.d: Likewise.
        * gas/arc/relax-avoid2.s: Likewise.
        * gas/arc/relax-avoid3.d: Likewise.
        * gas/arc/relax-avoid3.s: Likewise.
	* gas/arc/relax-b.d: Likewise.
        * gas/arc/relax-b.s: Likewise.

include/opcode/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
        Declare.

opcodes/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
        variable.
2016-02-10 12:09:01 +00:00
Nick Clifton 9264d32548 FIx formatting that triggers a new compile time warning message.
* config/tc-ia64.c (dot_prologue): Fix formatting.
2016-02-08 14:51:10 +00:00
Nick Clifton 3930612461 Remove support for creating ARM NOREAD sections.
gas	* config/obj-elf.c (obj_elf_change_section): Remove support for
	ARM NOREAD sections.
	* config/tc-arm.c (arm_elf_section_letter): Delete.
	* config/tc-arm.h (md_elf_section_letter): Delete.
	* doc/c-arm.texi (ARM Section Attribute): Delete section.
	* testsuite/gas/arm/section-execute-only.d: Delete.
	* testsuite/gas/arm/section-execute-only.s: Delete.

ld	* testsuite/ld-arm/arm-elf.exp: Remove ARM NOREAD section tests.
	* testsuite/ld-arm/thumb1-input-section-flag-match.d: Delete.
	* testsuite/ld-arm/thumb1-input-section-flag-match.s: Delete.
	* testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.d: Delete.
	* testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.s: Delete.
	* testsuite/ld-arm/thumb1-noread-present-one-section.d: Delete.
	* testsuite/ld-arm/thumb1-noread-present-one-section.s: Delete.
	* testsuite/ld-arm/thumb1-noread-present-two-section.d: Delete.
	* testsuite/ld-arm/thumb1-noread-present-two-section.s: Delete.
2016-02-04 11:57:57 +00:00
Nick Clifton c1d9289fef Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

include	* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
	(RRUX): Synthesise using case 2 rather than 7.

gas	* config/tc-msp430.c (msp430_operands): Remove case 7.  Use case 2
	to handle encoding of RRUX instruction.
	* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
	shift instructions.
	* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-04 09:55:10 +00:00
Max Filippov ea173078d2 xtensa: fix signedness of gas relocations
Change 1058c7532d "Use signed data type for R_XTENSA_DIFF* relocation
offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations
substituted for BFD_RELOC_*. This made it impossible to encode arbitrary
8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc
directive. Revert this part and add test.

gas/
2016-02-03  Max Filippov  <jcmvbkbc@gmail.com>
	* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
	substitutions for BFD_RELOC_* as unsigned.
	* gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa
	tests.
	* gas/testsuite/gas/xtensa/loc.d: New file: loc test result
	patterns.
	* gas/testsuite/gas/xtensa/loc.s: New file: loc test.
2016-02-03 20:44:57 +03:00
H.J. Lu 0cb4071ef9 Add -mrelax-relocations= to x86 assembler
The x86 relax relocations introduced in binutils 2.26 aren't supported
by linker on Solaris older than Solaris 12.  To use x86 assembler with
older Solaris linker, this patch adds

1. A command line option -mrelax-relocations= to x86 assembler to
control whether to generate relax relocations.
2. A configure option --enable-x86-relax-relocations to decide whether
x86 assembler should generate relax relocations by default.  It is
defaulted to yes, except for x86 Solaris targets older than Solaris 12.

gas/

	PR gas/19520
	* NEWS: Mention new command line option -mrelax-relocations and
	new configure option --enable-x86-relax-relocations for x86
	target.
	* config.in: Regenerated.
	* configure.ac: Add --enable-x86-relax-relocations.
	(ac_default_x86_relax_relocations): New.  Default to 1 except
	for x86 Solaris targets older than Solaris 12.
	(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
	* configure: Likewise.
	* config/tc-i386.c (generate_relax_relocations): New.
	(OPTION_MRELAX_RELOCATIONS): Likewise.
	(output_disp): Don't generate relax relocations if
	generate_relax_relocations is 0.
	(md_longopts): Add -mrelax-relocations.
	(md_show_usage): Likewise.
	(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
	* doc/c-i386.texi: Document -mrelax-relocations=.
	* testsuite/gas/i386/got-no-relax.d: New file.
	* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
	* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
	* testsuite/gas/i386/localpic.d: Likewise.
	* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
	* testsuite/gas/i386/reloc32.d: Likewise.
	* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
	* testsuite/gas/i386/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run got-no-relax and
	x86-64-gotpcrel-no-relax.

ld/

	PR gas/19520
	* testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as.
	* testsuite/ld-i386/call1.d: Likewise.
	* testsuite/ld-i386/call2.d: Likewise.
	* testsuite/ld-i386/call3a.d: Likewise.
	* testsuite/ld-i386/call3b.d: Likewise.
	* testsuite/ld-i386/call3c.d: Likewise.
	* testsuite/ld-i386/call3d.d: Likewise.
	* testsuite/ld-i386/call3e.d: Likewise.
	* testsuite/ld-i386/call3f.d: Likewise.
	* testsuite/ld-i386/call3g.d: Likewise.
	* testsuite/ld-i386/call3h.d: Likewise.
	* testsuite/ld-i386/jmp1.d: Likewise.
	* testsuite/ld-i386/jmp2.d: Likewise.
	* testsuite/ld-i386/lea1c.d: Likewise.
	* testsuite/ld-i386/load1.d: Likewise.
	* testsuite/ld-i386/load2.d: Likewise.
	* testsuite/ld-i386/load3.d: Likewise.
	* testsuite/ld-i386/load4a.d: Likewise.
	* testsuite/ld-i386/load5a.d: Likewise.
	* testsuite/ld-i386/mov2b.d: Likewise.
	* testsuite/ld-i386/mov3.d: Likewise.
	* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
	* testsuite/ld-x86-64/call1a.d: Likewise.
	* testsuite/ld-x86-64/call1b.d: Likewise.
	* testsuite/ld-x86-64/call1c.d: Likewise.
	* testsuite/ld-x86-64/call1d.d: Likewise.
	* testsuite/ld-x86-64/call1e.d: Likewise.
	* testsuite/ld-x86-64/call1f.d: Likewise.
	* testsuite/ld-x86-64/call1h.d: Likewise.
	* testsuite/ld-x86-64/call1i.d: Likewise.
	* testsuite/ld-x86-64/load1a.d: Likewise.
	* testsuite/ld-x86-64/load1b.d: Likewise.
	* testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it.
	* testsuite/ld-i386/got1.dd: Updated.
	* testsuite/ld-i386/got1d.S (1): Removed.
	* testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-02-03 08:25:15 -08:00
Kevin Buettner 3d8efabf21 msp430: Set DWARF2_ADDR_SIZE to 4.
This change makes gas's notion of the msp430 dwarf2 address size match
that of gcc and gdb.  This is needed so that the format of addresses
generated for DW_LNE_set_address in .debug_line will match the address
size for the compilation unit.

In gcc/config/msp430/msp430.h, it's set to 4:

  #define	DWARF2_ADDR_SIZE			4

Likewise in gdb/msp430-tdep.c:

  set_gdbarch_dwarf2_addr_size (gdbarch, 4);

(As far as I can tell, however, GDB doesn't use this value when decoding
.debug_line.  Instead, GDB uses the Pointer Size from the compilation
unit.)

readelf is able to seamlessly handle mismatches between these various
sizes by using the size of the DW_LNE_set_address instruction to
determine the address size.  Another way to fix this problem is to
make GDB behave in a similar manner.  In my opinion, GDB should detect
and inform the user about these mismatches; it's not clear to me if
it's correct for GDB to go ahead and read the address anyway when a
size mismatch is detected.

Without this change, addresses in .debug_line are encoded in two bytes
for some multilibs.  When GDB reads the address for
DW_LNE_set_address, it uses the pointer size provided by the CU.  When
these values don't match, GDB reads the wrong number of bytes.  In the
cases that I've looked at, GDB is reading 4 bytes from a 2 byte
container, which results in a garbage address.  GDB discards lines
which have a bogus address; the end result is that GDB records no line
number information for CUs which have a mismatch between the address
size (from the CU) and the format of the address used by
DW_LNE_set_address.

gas/ChangeLog:

	* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-02-03 09:21:51 -07:00
H.J. Lu 9d3fc4e190 Mention -mfence-as-lock-add=yes for x86 assembler
* NEWS: Mention new command line option -mfence-as-lock-add=yes
	for x86 target.
2016-02-03 06:42:39 -08:00
H.J. Lu ab71ce8646 Remove duplicated marker for 2.26 in gas/NEWS
* NEWS: Remove duplicated marker for 2.26.
2016-02-03 06:37:21 -08:00
Renlin Li 46d70d04a4 [GAS][ARM]Skip none elf target for testsuite/gas/arm/thumb2_it_search.s
gas/

	* testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
2016-02-02 15:55:21 +00:00
Andrew Burgess 0f99255d74 gas/ip2k: Add all instructions assembler test
Basic all instructions assembler test, auto-generated by CGEN, then
fixed by hand for some cases where CGEN had generated invalid
instruction operands.

gas/ChangeLog:

	* testsuite/gas/ip2k/allinsn.d: New file.
	* testsuite/gas/ip2k/allinsn.s: New file.
	* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
2016-02-02 11:09:17 +00:00
Andrew Burgess 5d7a901176 epiphany/gas: Update expected test results for 0 offset loads
In commit 02a79b89fd some of the load
instructions with a zero offset (where the offset is not mentioned) were
marked as NO-DIS, meaning that the disassembler must display the offset,
even though it is zero.

This change seems a little strange to me as it was only applied to some
loads, not all, and the same change was not applied to the stores.

However, I'm reluctant to revert a specific change to the assembler,
when the output is obviously correct.  With this commit then I simply
bring the expected assembler test results into line with what is
actually produced.

gas/ChangeLog:

	* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
	some load instructions.
	* testsuite/gas/epiphany/allinsn.d: Likewise.
	* testsuite/gas/epiphany/regression.d: Likewise.
2016-02-02 11:09:17 +00:00
Andrew Burgess a012b298ba epiphany/gas: Remove .l suffix from expected test results
In commit 02a79b89fd all instruction
aliases that have a '.l' suffix were marked as NO-DIS, so the
disassembler will not display them, in preference to the instruction
without the suffix.  However, the gas testsuite was not updated at the
time, this commit fixes that oversight.

gas/ChangeLog:

	* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
	suffixes from instruction mnemonics in expected output.
	* testsuite/gas/epiphany/allinsn.d: Likewise.
	* testsuite/gas/epiphany/regression.d: Likewise.
	* testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02 11:09:17 +00:00
Andrew Burgess 2f74d480dd gas/epiphany: Update expected register names in tests
In commit 02a79b89fd the register aliases
sb, sl, and ip were made less preferred than r9, r10, and r12, however,
the expected test results were not updated.  This commit fixes this
oversight and updates the test results.

gas/ChangeLog:

	* testsuite/gas/epiphany/addr-syntax.d: Update expected register
	names.
	* testsuite/gas/epiphany/allinsn.d: Likewise.
	* testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02 11:09:17 +00:00
Andrew Burgess b89807c67b epiphany/disassembler: Improve alignment of output.
Always set the bytes_per_line field (of struct disassemble_info) to the
same constant value, this is inline with the advice contained within
include/dis-asm.h.

Setting this field to a constant value will cause the disassembler
output to be better aligned.

cpu/ChangeLog:

	* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
	a constant to better align disassembler output.

opcodes/ChangeLog:

	* epiphany-dis.c: Regenerated from latest cpu files.

gas/ChangeLog:

	* testsuite/gas/epiphany/sample.d: Update expected output.
2016-02-02 11:09:17 +00:00
Claudiu Zissulescu b125bd1727 Fix ARC TLS support.
* config/tc-arc.c (md_apply_fix): Allow addendum.
        (arc_reloc_op): Allow complex expressions for tpoff.
        (md_apply_fix): Handle resolved TLS local symbol.

	* gas/arc/tls-relocs1.d: New file.
	* gas/arc/tls-relocs1.s: Likewise.
2016-02-01 17:03:56 +00:00
Loria 4f1d62057f Fix a problem building the ARM assembler using LLVM.
PR target/19311
	* config/tc-arm.c (encode_arm_immediate): Recode to improve
	efficiency and avoid an LLVM loop optimization bug.
2016-02-01 14:32:25 +00:00
Nick Clifton ac0d427f4b Fix error building Microblaze assembler on a 32-bit host.
* config/tc-microblaze.c (parse_imm): Fix compile time warning
	message extending a negative 32-bit value into a larger signed
	value on a 32-bit host.
2016-02-01 11:36:59 +00:00
H.J. Lu 348ef89a54 Replace == with = in gas/configure.ac
PR gas/19532
	* configure.ac (compressed_debug_sections): Replace == with =.
	* configure: Regenerated.
2016-01-29 07:49:23 -08:00
H.J. Lu ac2789d7ec Add testsuite/ to the last gas ChangeLog entry 2016-01-29 05:01:07 -08:00
Andrew Senkevich e4e00185b5 Add option -mfence-as-lock-add=[no|yes].
With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded
as lock addl $0x0, (%{r,e}sp).

gas/:

    * config/tc-i386.c (avoid_fence): New.
    (output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
    is true.
    (OPTION_FENCE_AS_LOCK_ADD): New.
    (md_longopts): Add -mfence-as-lock-add.
    (md_parse_option): Handle -mfence-as-lock-add.
    (md_show_usage): Add -mfence-as-lock-add=[no|yes].
    * doc/c-i386.texi (-mfence-as-lock-add): Document.

gas/testsuite/:

    * gas/i386/i386.exp: Run new tests.
    * gas/i386/fence-as-lock-add.s: New.
    * gas/i386/fence-as-lock-add-yes.d: Likewise.
    * gas/i386/fence-as-lock-add-no.d: Likewise.
    * gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
    * gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-29 15:46:50 +03:00
H.J. Lu 27ba7c9497 Remove trailing `]' in --enable-compressed-debug-sections
* configure.ac (compressed_debug_sections): Remove trailing `]'.
	* configure: Regenerated.
2016-01-27 10:24:51 -08:00
Nick Clifton ffd9c127e6 Skip thumb2 conditional backward search test for PE based targets.
* testsuite/gas/arm/thumb2_it_search.d: Skip for PE targets.
2016-01-26 09:13:38 +00:00
H.J. Lu d1982f935e Rename OPTION_OMIT_LOCK_PREFIX to OPTION_MOMIT_LOCK_PREFIX
Use OPTION_MXXX for -mxxx option in x86 assembler.

	* config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ...
	(OPTION_MOMIT_LOCK_PREFIX): This.
	(md_longopts): Updated.
	(md_parse_option): Likewise.
2016-01-25 17:01:11 -08:00
Catherine Moore 00acd688ca Avoid the use of gp-relative addressing when abicalls are in effect. 2016-01-25 12:39:40 -08:00
Renlin Li 5bc5ae8810 [PATCH[ARM]Check mapping symbol while backward searching for IT block.
opcodes/

	* arm-dis.c (mapping_symbol_for_insn): New function.
	(find_ifthen_state): Call mapping_symbol_for_insn().

gas/

	* testsuite/gas/arm/thumb2_it_search.d: New.
	* testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-25 15:14:29 +00:00
Nick Clifton 61e137e281 Fix gas testsuite failures for ARM netbesdelf configuration.
PR gas/19454
	* testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope
	with arm-netbsdelf target.
	* testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
2016-01-21 14:39:34 +00:00
Nick Clifton 74b92a5c75 Fix unexpected failures in GAS testsuite for ARM VxWorks target.
PR 19456
	* testsuite/gas/arm/weakdef-1.d: Skip for VxWorks.
	* testsuite/gas/arm/blx-bl-convert.d
	* testsuite/gas/arm/plt-1.d: Likewise.
	* testsuite/gas/arm/reloc-bad.d: Likewise.
	* testsuite/gas/arm/thumb-w-good.d: Likewise.
	* testsuite/gas/arm/thumb2_pool.d: Likewise.
	* testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks
	* testsuite/gas/arm/tls_vxworks.d: Update expected output.
2016-01-20 17:02:42 +00:00
Nick Clifton 72e0b2547d Upda the documentation on assembler error message generation.
PR 19499
	* doc/as.texinfo (Errors): Correct documentation describing the
	interaction of .file and .line with warning and error messages.
2016-01-20 16:21:34 +00:00
Nick Clifton aed5fc75ef Skip ARM v8 tests for COFF based targets. 2016-01-20 15:00:57 +00:00
Matthew Wahab 0bff6e2d69 [AArch64] Reject invalid immediate operands to MSR UAO
In the instruction to write to the ARMv8.2 PSTATE field UAO,
MSR UAO, #<imm>, the immediate should be either 0 or 1 but GAS accepts
any unsigned 4-bit integer.

This patch implements the constraint on the immediate, generating an
error if the immediate operand is invalid, and adds tests for the
illegal forms.

opcodes/
2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (operand_general_constraint_met_p): Check validity
	of MSR UAO immediate operand.

gas/
2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>

	* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
	* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
	* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.

Change-Id: Ibdec4967c00b1ef3be9dbc43d23b2c70d1a0b28c
2016-01-20 14:25:46 +00:00
Mickael Guene 91f68a68f9 Add support for an ARM specific 'y' section attribute flag to mark the section as NOREAD.
bfd/ChangeLog:
      * elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread
      section using '.text.noread' pattern.

gas/ChangeLog:
      * config/obj-elf.c (obj_elf_change_section) : Allow arm section with
      SHF_ARM_NOREAD section flag.
      * config/tc-arm.h (md_elf_section_letter) : Implement this hook to
      handle letter 'y'.
     (arm_elf_section_letter) : Declare it.
      * config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
      SHF_ARM_NOREAD section flag.
      * doc/c-arm.texi (ARM section attribute 'y'): Document it.

gas/testsuite/ChangeLog:
      * gas/arm/section-execute-only.s: New test case.
      * gas/arm/section-execute-only.d: Expected output.

ld/testsuite/ChangeLog:
      * ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y'
      attribute usage.
      * ld-arm/thumb1-noread-present-one-section.s: Likewise.
      * ld-arm/thumb1-noread-present-two-section.s: Likewise.
      * ld-arm/thumb1-input-section-flag-match.s: Likewise.

binutils/ChangeLog:
      * readelf.c (get_elf_section_flags): Display y letter for section
      with SHF_ARM_NOREAD section flag in readelf section output.
      (process_section_headers): Add y letter in readelf section output
      key mapping for ARM architecture.
2016-01-20 12:53:50 +00:00
Maciej W. Rozycki 100b4f2e9f MIPS: Remove remnants of 48-bit microMIPS instruction support
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.

This complements commit a6c7053929 ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").

References:

[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
    Major Opcode Field", p. 578

	gas/
	* config/tc-mips.c (micromips_insn_length): Remove the mention
	of 48-bit microMIPS instructions.

	gdb/
	* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
	instruction support.
	(micromips_next_pc): Likewise.
	(micromips_scan_prologue): Likewise.
	(micromips_deal_with_atomic_sequence): Likewise.
	(micromips_stack_frame_destroyed_p): Likewise.
	(mips_breakpoint_from_pc): Likewise.

	opcodes/
	* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
	instruction support.
2016-01-18 22:19:54 +00:00
Alan Modra 3d961d0d3a Provide AC_PROG_LEX that copes with LEX=missing from top-level
config/
	PR binutils/19481
	* override.m4 (AC_PROG_LEX): Define.
binutils/
	* configure: Regenerate.
gas/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
2016-01-18 22:17:57 +10:30
Alan Modra 5c14705fb3 Regen configure
Picks up 2016-01-12 libtool.m4 change.

bfd/
	* configure: Regenerate.
binutils/
	* configure: Regenerate.
gas/
	* configure: Regenerate.
gprof/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
opcodes/
	* configure: Regenerate.
2016-01-17 12:28:14 +10:30
Alan Modra b3066ae825 m68hc11/12 and xgate config.sub weirdness
Oddly, config.sub converts a duple ending in -elf for these target to
-unknown-none, which means they aren't seen as elf targets by
binutils.  So, counter that.  This exposes a number of testsuite
issues (ones you would have seen if configuring with a full triple,
say m68hc11-unknown-elf).

binutils/
	* testsuite/lib/binutils-common.exp (is_elf_format): Return true
	for m68hc11/12 and xgate triples.
gas/
	* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
ld/
	* testsuite/lib/ld-lib.exp (check_shared_lib_support): Exclude xgate.
	* testsuite/ld-elf/endsym.d: xfail m68hc11/12 and xgate.
	* testsuite/ld-elf/pr14156a.d: Likewise.
	* testsuite/ld-elf/pr14926.d: Don't run for m68hc11/12 and xgate.
	* testsuite/ld-elf/sec64k.exp: Likewise.
2016-01-17 12:13:43 +10:30
Nick Clifton 4d82fe66e8 Fix display of RL78 MOVW instructions that use the stack pointer.
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
	instructions that can support stack pointer operations.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c: Fix display of stack pointer in MOVW based
	instructions.

	* testsuite/gas/rl78/sp-relative-movw.s: New test.
	* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
	* testsuite/gas/rl78/rl78.exp: Run the new test.
2016-01-14 16:23:35 +00:00
Matthew Wahab 651657fa61 [AArch64] Fix missing architecture checks for ARMv8.2 system registers.
Some of the RAS system registers added to binutils as part of the ARMv8.2
support are missing the feature checks to warn when they aren't
supported by the target.

This patch adds the missing feature checks with a test to check that
the correct warnings are given for all the ARMv8.2 system registers.

gas/
2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>

	* testsuite/gas/aarch64/illegal-sysreg-2.l: New.
	* testsuite/gas/aarch64/illegal-sysreg-2.d: New.

opcodes/
2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
	testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
	erxtatus_el1 and erxaddr_el1.

Change-Id: I66b590ea49c1eb6b0e5c93e0dc2bc9c4e79a52fe
2016-01-14 10:55:11 +00:00
Maciej W. Rozycki 3facb0e9a7 Nios II/GAS: Fix build error in `output_movia'
Fix:

cc1: warnings being treated as errors
.../gas/config/tc-nios2.c: In function 'output_movia':
.../gas/config/tc-nios2.c:3474: warning: 'code' may be used uninitialized in this function
make[4]: *** [tc-nios2.o] Error 1

seen with GCC 4.1.2 and 4.4.7.

	gas/
	* config/tc-nios2.c (output_movia): Preset `code' to 0.
2016-01-13 21:00:01 +00:00
Yoshinori Sato 8a4c286981 Remove spurious condition in test for closing parenthesis.
* config/tc-h8300.c (get_operand): Remove spurious condition in
	test for closing parenthesis.
2016-01-13 17:47:34 +00:00
Matthew Wahab 105bde5771 [ARM] Support ARMv8.2 RAS extension.
The ARMv8.2 architecture includes the RAS extension which adds an
instruction, ESB, and a number of coprocessor registers. This patch adds
the instruction to binutils, making it available when -march=armv8.2-a
is selected. It also adds tests for the instruction and for the
coprocessor registers.

gas/
2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_ext_v8_2): New.
	(insns): Add "esb".
	* testsuite/gas/arm/armv8_2-a.d: New.
	* testsuite/gas/arm/armv8_2-a.s: New.

opcodes/
2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "esb".
	(thumb_opcodes): Likewise.

Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-12 16:41:07 +00:00
Alan Modra 5230aa4dc9 PowerPC gas test vsx3
Tweak for padding, now present for COFF.

	* testsuite/gas/ppc/vsx3.d: Accept nop padding.
2016-01-12 19:20:24 +10:30
Peter Bergner afa8d4054b Delete opcodes that have been removed from ISA 3.0.
opcodes/
	* ppc-opc.c <xscmpnedp>: Delete.
	<xvcmpnedp>: Likewise.
	<xvcmpnedp.>: Likewise.
	<xvcmpnesp>: Likewise.
	<xvcmpnesp.>: Likewise.

gas/
	* testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
	xvcmpnesp, xvcmpnesp.>: Delete tests.
	* testsuite/gas/ppc/power9.s: Likewise.
	* testsuite/gas/ppc/vsx3.d: Likewise.
	* testsuite/gas/ppc/vsx3.s: Likewise.
2016-01-11 11:54:58 -06:00
Andreas Schwab 83c3256ef5 m68k: fix constraints of move.[bw] for ISA_B/C
For ISA_B/C only the combination #,d(An) is allowed in addition to the
ISA_A combinations for move.b and move.w (and pc-relative is never
allowed as destination).

opcodes/
	PR gas/13050
	* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
	addition to ISA_A.

gas/
	PR gas/13050
	* testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2.
	* testsuite/gas/m68k/p13050-1.s: New file.
	* testsuite/gas/m68k/p13050-2.d: New file.
	* testsuite/gas/m68k/p13050-2.s: New file.
2016-01-08 11:42:10 +01:00
Andrew Burgess b05a65d0ad bfd/arc: Add R_ prefix to all relocation names
The convention within for relocation names is that they start with the
string "R_", however, this is not so for ARC for the display names of
relocations, however, internally, the names for the relocations types do
have the 'R_' prefix.  I suspect that the missing 'R_' on the output
strings was an oversight, as I can't see any comment to the contrary.

To bring ARC into line with other targets, this commit adds the 'R_'
prefix to the output strings used for relocation names, and updates all
of the assembler tests where this was exposed.

bfd/ChangeLog:

	* elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to
	place 'R_' before the reloc name returned.
	(elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before
	the relocation string.

gas/ChangeLog:

	* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
	* testsuite/gas/arc/add.d: Likewise.
	* testsuite/gas/arc/and.d: Likewise.
	* testsuite/gas/arc/asl.d: Likewise.
	* testsuite/gas/arc/asr.d: Likewise.
	* testsuite/gas/arc/bic.d: Likewise.
	* testsuite/gas/arc/extb.d: Likewise.
	* testsuite/gas/arc/extw.d: Likewise.
	* testsuite/gas/arc/j.d: Likewise.
	* testsuite/gas/arc/jl.d: Likewise.
	* testsuite/gas/arc/ld2.d: Likewise.
	* testsuite/gas/arc/lsr.d: Likewise.
	* testsuite/gas/arc/mov.d: Likewise.
	* testsuite/gas/arc/or.d: Likewise.
	* testsuite/gas/arc/pcl-relocs.d: Likewise.
	* testsuite/gas/arc/pcrel-relocs.d: Likewise.
	* testsuite/gas/arc/pic-relocs.d: Likewise.
	* testsuite/gas/arc/plt-relocs.d: Likewise.
	* testsuite/gas/arc/rlc.d: Likewise.
	* testsuite/gas/arc/ror.d: Likewise.
	* testsuite/gas/arc/rrc.d: Likewise.
	* testsuite/gas/arc/sbc.d: Likewise.
	* testsuite/gas/arc/sda-relocs.d: Likewise.
	* testsuite/gas/arc/sda-relocs2.d: Likewise.
	* testsuite/gas/arc/sexb.d: Likewise.
	* testsuite/gas/arc/sexw.d: Likewise.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/sub.d: Likewise.
	* testsuite/gas/arc/tls-relocs.d: Likewise.
	* testsuite/gas/arc/xor.d: Likewise.
2016-01-06 14:15:22 +00:00
Alan Modra 6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra 3499769a6a New 2016 binutils ChangeLog files
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog
and include/*/ChangeLog files.
2016-01-01 22:59:42 +10:30
Alan Modra 4120fa118f binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
Alan Modra 331e61312e Fix assorted ChangeLog errors 2015-12-30 11:44:35 +10:30
Thomas Preud'homme ff8646eef8 Add assembler support for ARMv8-M Baseline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
    to merging with ARMv8-M Baseline.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
    value.

gas/
    * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
    shared between ARMv6T2 and ARMv8-M.
    (move_or_literal_pool): Check mov.w/mvn and movw availability against
    arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
    arm_arch_t2.
    (do_t_branch): Error out for wide conditional branch instructions if
    targetting ARMv8-M Baseline.
    (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
    in ARMv8-M Baseline.
    (wide_insn_ok): New function.
    (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
    adapt error message for unsupported wide instruction to ARMv8-M
    Baseline.
    (insns): Reorganize instructions shared by ARMv8-M Baseline and
    ARMv6t2 architecture.
    (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
    marvell-whitney cores.
    (arm_archs): Define armv8-m.base architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
    (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
    ARMv8-M Mainline.  Set Tag_DIV_use for ARMv8-M Baseline as well.

gas/testsuite/
    * gas/arm/archv8m-base.d: New file.
    * gas/arm/attr-march-armv8m.base.d: Likewise.
    * gas/arm/armv8m.base-idiv.d: Likewise.
    * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.

include/opcode/
    * arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
    (ARM_AEXT2_V8A): New architecture extension bitfield.
    (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_AEXT_V8M_BASE): New architecture extension bitfield.
    (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
    (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield.
    (ARM_ARCH_V6KT2): Likewise.
    (ARM_ARCH_V6ZT2): Likewise.
    (ARM_ARCH_V6KZT2): Likewise.
    (ARM_ARCH_V7): Likewise.
    (ARM_ARCH_V7A): Likewise.
    (ARM_ARCH_V7VE): Likewise.
    (ARM_ARCH_V7R): Likewise.
    (ARM_ARCH_V7M): Likewise.
    (ARM_ARCH_V7EM): Likewise.
    (ARM_ARCH_V8A): Likewise.
    (ARM_ARCH_V8M_BASE): New architecture bitfield.
    (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
    (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield and reindent.
    (ARM_ARCH_V7A_MP_SEC): Likewise.
    (ARM_ARCH_V7R_IDIV): Likewise.
    (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
    ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
    ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 17:27:21 +08:00
Thomas Preud'homme 4ed7ed8db2 Add assembler support for ARMv8-M Mainline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
    for new TAG_CPU_ARCH_V4T_PLUS_V6_M value.  Deal with NULL values in
    comb array.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
    value.
    (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
    value.

gas/
    * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
    (arm_ext_v8m): New feature for ARMv8-M.
    (arm_ext_atomics): New feature for ARMv8 atomics.
    (do_tt): New encoding function for TT* instructions.
    (insns): Add new entries for ARMv8-M specific instructions and
    reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
    (arm_archs): Define armv8-m.main architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
    clarify the ordering rule.
    (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
    Tag_CPU_arch values for ARMv7e-M detection.  Add logic to keep setting
    Tag_CPU_arch to ARMv8-A for -march=all.  Also set Tag_CPU_arch_profile
    to 'A' if extension bit for atomic instructions is set, unless it is
    ARMv8-M.  Set Tag_THUMB_ISA_use to 3 for ARMv8-M.  Set Tag_DIV_use to 0
    for ARMv8-M Mainline.

gas/testsuite/
    * gas/arm/archv8m.s: New file.
    * gas/arm/archv8m-main.d: Likewise.
    * gas/arm/attr-march-armv8m.main.d: Likewise.
    * gas/arm/any-armv8m.s: Likewise.
    * gas/arm/any-armv8m.d: Likewise.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
    (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
    (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.

include/opcode/
    * arm.h (ARM_EXT2_ATOMICS): New extension bit.
    (ARM_EXT2_V8M): Likewise.
    (ARM_EXT_V8): Adjust comment with regards to atomics and remove
    mention of legacy use for that bit.
    (ARM_AEXT2_V8_1A): New architecture extension bitfield.
    (ARM_AEXT2_V8_2A): Likewise.
    (ARM_AEXT_V8M_MAIN): Likewise.
    (ARM_AEXT2_V8M): Likewise.
    (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
    (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
    (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
    (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
    (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
    and reindent.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.
    (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
    feature bits.
    (ARM_ARCH_V8_1A_SIMD): Likewise.
    (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
    stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
    ARM_EXT_V8.
    (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 17:26:54 +08:00
Thomas Preud'homme fc289b0a83 Consolidate Thumb-1/Thumb-2 ISA detection
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
    * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
    availability against arm_ext_v6t2 instead of checking arm_arch_t2,
    fixing comments along the way.
    (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
    generate IT instruction.
    (t1_isa_t32_only_insn): New function.
    (md_assemble): Use above new function to check for invalid wide
    instruction for CPU Thumb ISA and to determine what Thumb extension
    bit is necessary for that instruction.
    (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
    branch is out of range.

include/opcode/
    * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
    remove extension bit not including any Thumb-2 instruction.
2015-12-24 17:03:50 +08:00
Thomas Preud'homme 443bfd5a37 Add tests for gas arch autodetection on ARM
2015-12-09  Andre Vieira  <andre.simoesdiasvieira@arm.com>

gas/testsuite/
    * gas/arm/automatic-bw.d: New.
    * gas/arm/automatic-bw.s: New.
    * gas/arm/automatic-cbz.d: New.
    * gas/arm/automatic-cbz.s: New.
    * gas/arm/automatic-clrex.d: New.
    * gas/arm/automatic-clrex.s: New.
    * gas/arm/automatic-lda.d: New.
    * gas/arm/automatic-lda.s: New.
    * gas/arm/automatic-ldaex.d: New.
    * gas/arm/automatic-ldaex.s: New.
    * gas/arm/automatic-ldaexb.d: New.
    * gas/arm/automatic-ldaexb.s: New.
    * gas/arm/automatic-ldrex.d: New.
    * gas/arm/automatic-ldrex.s: New.
    * gas/arm/automatic-ldrexd.d: New.
    * gas/arm/automatic-ldrexd.s: New.
    * gas/arm/automatic-movw.d: New.
    * gas/arm/automatic-movw.s: New.
    * gas/arm/automatic-sdiv.d: New.
    * gas/arm/automatic-sdiv.s: New.
    * gas/arm/automatic-strexb.d: New.
    * gas/arm/automatic-strexb.s: New.
2015-12-24 16:54:21 +08:00
Nick Clifton 361fa3a494 Fix building pdfs of assembler documentation.
PR gas/19386
	* doc/as.texinfo (Strings): Prepend a space to index entries that
	start with a backslash.  This works around a problem in the pdf
	generator.
2015-12-21 12:00:04 +00:00
H.J. Lu a28def7591 Process 64-bit imm/disp only for 64-bit BFD
We only need to store 32-bit immediate in 64-bit and optimize 64-bit
displacement to 32-bit only for 64-bit BFD.

	* config/tc-i386.c (optimize_imm): Store 32-bit immediate in
	64-bit only for 64-bit BFD
	(optimize_disp): Optimize 64-bit displacement to 32-bit only
	for 64-bit BFD.
2015-12-18 14:07:36 -08:00
Ramana Radhakrishnan dea6e325f6 [Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
Add missing ChangeLog entry.
2015-12-17 16:33:24 +00:00
Ramana Radhakrishnan 10c9892b66 [Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.

In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.

This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.

2015-12-17  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
	TAG_ARCH_profile for armv8-a.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
2015-12-17 11:34:39 +00:00
Christophe Lyon 0bef041426 Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:
2015-12-16  Mickael Guene <mickael.guene@st.com>

	bfd/
	* bfd-in2.h: Regenerate.
	* reloc.c: Add new relocations.
	* libbfd.h (bfd_reloc_code_real_names): Add new relocations
	display names.
	* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
	relocations.
	(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
	(elf32_arm_final_link_relocate): Implement new relocations
	resolution.

	gas/
	* doc/c-arm.texi: Add documentation about new directives
	* config/tc-arm.c (group_reloc_table): Add mapping between gas
	syntax and new relocations.
	(do_t_add_sub): Keep new relocations for add operand.
	(do_t_mov_cmp): Keep new relocations for mov operand.
	(insns): Use 'shifter operand with possible group relocation'
	operand parse code for movs operand.
	(md_apply_fix): Implement mov and add encoding when new
	relocations on them.
	(tc_gen_reloc): Add new relocations.
	(arm_fix_adjustable): Since offset has a limited range ([0:255])
	we disable adjust_reloc_syms() for new relocations.

	gas/testsuite/
	* gas/arm/adds-thumb1-reloc-local.d: New
	* gas/arm/adds-thumb1-reloc-local.s: New
	* gas/arm/movs-thumb1-reloc-local.d: New
	* gas/arm/movs-thumb1-reloc-local.s: New

	include/
	* elf/arm.h: Add new arm relocations.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
	tests.
	* ld-arm/thumb1-adds.d: New
	* ld-arm/thumb1-adds.s: New
	* ld-arm/thumb1-movs.d: New
	* ld-arm/thumb1-movs.s: New
2015-12-17 11:14:37 +01:00
Mickael Guene 72d98d16ed [ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and  R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
	movs	r3, #:upper8_15:#foo
	lsls	r3, #8
	adds	r3, #:upper0_7:#foo
	lsls	r3, #8
	adds	r3, #:lower8_15:#foo
	lsls	r3, #8
	adds	r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
   4:	2300      	movs	r3, #0
			4: R_ARM_THM_ALU_ABS_G3_NC	foo
   6:	021b      	lsls	r3, r3, #8
   8:	3300      	adds	r3, #0
			8: R_ARM_THM_ALU_ABS_G2_NC	foo
   a:	021b      	lsls	r3, r3, #8
   c:	3300      	adds	r3, #0
			c: R_ARM_THM_ALU_ABS_G1_NC	foo
   e:	021b      	lsls	r3, r3, #8
  10:	3300      	adds	r3, #0
			10: R_ARM_THM_ALU_ABS_G0_NC	foo
2015-12-16 10:19:51 +01:00
Nick Clifton ff1fe6fad9 Remove refernces to a non-existent silicon errata.
* doc/c-msp430.texi (MSP430 Options): Remove references to a
	non-existent silicon errata.
	* config/tc-msp430.c: Likewise.
2015-12-15 16:21:29 +00:00
Yoshinori Sato a117b0a51c Add support for RX V2 Instruction Set
binutils
	* readelf.c(get_machine_flags): Add v2 flag.

gas
	* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
	* config/tc-rx.c(cpu_type_list): New type lookup table.
	(md_parse_option): Use lookup table for choose cpu.
	(md_show_usage): Add rxv2 for mcpu option.
	* doc/c-rx.texi: Likewise.
	* config/rx-parse.y: Add v2 instructions and ACC register.
	(rx_check_v2): check v2 type.

include/elf
	* rx.h(E_FLAG_RX_V2): New RXv2 type.

include/opcode
	* rx.h: Add new instructions.

opcoes
	* rx-deocde.opc(rx_decode_opcode): Add new instructions pattern.
	* rx-dis.c(register_name): Add new register.

gas/testsuite
	* gas/rx/emaca.d: New.
	* gas/rx/emaca.sm: New.
	* gas/rx/emsba.d: New.
	* gas/rx/emsba.sm: New.
	* gas/rx/emula.d: New.
	* gas/rx/emula.sm: New.
	* gas/rx/fadd.d: Add new pattern.
	* gas/rx/fadd.sm: Add new pattern.
	* gas/rx/fmul.d: Add new pattern.
	* gas/rx/fmul.sm: Add new pattern.
	* gas/rx/fsqrt.d: New.
	* gas/rx/fsqrt.sm: New.
	* gas/rx/fsub.d: Add new pattern.
 	* gas/rx/fsub.sm: Add new pattern.
	* gas/rx/ftou.d: New.
	* gas/rx/ftou.sm: New.
	* gas/rx/maclh.d: New.
	* gas/rx/maclh.sm: New.
	* gas/rx/maclo.d: Add new pattern.
	* gas/rx/maclo.sm: Add new pattern.
	* gas/rx/macros.inc: Add new register.
	* gas/rx/movco.d: New.
	* gas/rx/movco.sm: New.
	* gas/rx/movli.d: New.
	* gas/rx/movli.sm: New.
	* gas/rx/msbhi.d: New.
	* gas/rx/msbhi.sm: New.
	* gas/rx/msblh.d: New.
	* gas/rx/msblh.sm: New.
	* gas/rx/msblo.d: New.
	* gas/rx/msblo.sm: New.
	* gas/rx/mullh.d: New.
	* gas/rx/mullh.sm: New.
	* gas/rx/mvfacgu.d: New.
	* gas/rx/mvfacgu.sm: New.
	* gas/rx/mvfachi.d: Add new pattern.
	* gas/rx/mvfachi.sm: Add new pattern.
	* gas/rx/mvfaclo.d: Add new pattern.
	* gas/rx/mvfaclo.sm: Add new pattern.
	* gas/rx/mvfacmi.d: Add new pattern.
	* gas/rx/mvfacmi.sm: Add new pattern.
	* gas/rx/mvfc.d: Add new pattern.
	* gas/rx/mvtacgu.d: New.
	* gas/rx/mvtacgu.sm: New.
	* gas/rx/mvtc.d: Add new pattern.
	* gas/rx/popc.d: Add new pattern.
	* gas/rx/pushc.d: Add new pattern.
	* gas/rx/racl.d: New.
	* gas/rx/racl.sm: New.
	* gas/rx/racw.d: Add new pattern.
	* gas/rx/racw.sm: Add new pattern.
	* gas/rx/rdacl.d: New.
	* gas/rx/rdacl.sm: New.
	* gas/rx/rdacw.d: New.
	* gas/rx/rdacw.sm: New.
	* gas/rx/rx.exp: Add option.
	* gas/rx/stnz.d: Add new pattern.
	* gas/rx/stnz.sm: Add new pattern.
	* gas/rx/stz.d: Add new pattern.
	* gas/rx/stz.sm: Add new pattern.
	* gas/rx/utof.d: New.
	* gas/rx/utof.sm: New.
2015-12-15 09:26:56 +00:00
Matthew Wahab 4fd0a9fd00 [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
   <OP> <Hd>, <Hs>, #<imm>

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
	by immediate instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SSHIFT_H): New.
	(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
	and fcvtzu to the Adv.SIMD scalar shift by immediate group.

Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
2015-12-14 17:46:21 +00:00
Matthew Wahab b5b0f34c66 [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.

The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
   <OP> <Vd>.<T>, <Vs>.<T>, #<imm>
   where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
	instructions.
	* gas/aarch64/illegal.d: Update expected output.
	* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
	specifier.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_VSHIFT_H): New.
	(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
	and fcvtzu to the Adv.SIMD shift by immediate group.

Change-Id: I3480f63883d54db46562573185da6982f2365ee8
2015-12-14 17:42:16 +00:00
Matthew Wahab b195470dd2 [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP

The general form for these instructions is
   <OP> <Hd>, <V>.<T>
   where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
	Pairwise instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SISD_PAIR_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
	fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.

Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
2015-12-14 17:35:47 +00:00
Matthew Wahab 3067d3b96c [AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

gas/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
	take into account new vector type 2H.
	(vectype_to_qualifier): Likewise.

include/opcode/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (enum aarch64_opnd_qualifier): Add
	AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>

	* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
	and adjust calculation to ignore qualifier for type 2H.
	* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".

Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-14 17:27:52 +00:00
Matthew Wahab 65f2205d60 [AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.

The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.

The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.

This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.

gas/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
	qualifier from per-type base and offet.

Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
2015-12-14 17:25:35 +00:00
Matthew Wahab 4b5fc357a1 [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.

The instruction added is: FMOV.

The form of this instructions is
    <OP> <Hd>, #<imm>

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SIMD_IMM_H): New.
	(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
	modified immediate group.

Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
2015-12-14 17:22:36 +00:00
Matthew Wahab bb515fea4a [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.

The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.

The general form for these instructions is
   <OP> <Hd>, <V>.<T>
   where T is 4h or 8h.

The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
	instructions.
	* gas/aarch64/illegal.d: Update expected output.
	* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
	specifier.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_XLANES_FP_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
	fminnmv, fminv to the Adv.SIMD across lanes group.

Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
2015-12-14 17:18:50 +00:00
Matthew Wahab 5f7728b741 [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
  <OP> <Hd>, <Hs>, <V>.h[<idx>]

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
	fmls, fmul and fmulx to the scalar indexed element group.

Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
2015-12-14 17:08:12 +00:00
Matthew Wahab 42f23f6218 [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
  <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
  where T is 4h or 8h

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
	fmulx to the vector indexed element group.

Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
2015-12-14 17:01:56 +00:00
Matthew Wahab 80776b29d6 [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.

The general form for these instructions is
  <OP> <Hd>, <Hs>
or
  <OP> <Hd>, <Hs>, #0.0

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
	(QL_S_2SAMEH): New.
	(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
	fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
	frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
	fcvtzu and frsqrte to the scalar two register misc. group.

Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 16:57:04 +00:00
Matthew Wahab f3aa142b8b [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.

The general form for these instructions is
  <OP> <Vd>.<T>, <Vs>.<T>
  where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_V2SAMEH): New.
	(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
	fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
	frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
	fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
	and fsqrt to the vector register misc. group.

Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 16:54:38 +00:00
Matthew Wahab 6b4680fbd0 [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.

The general form for these instructions is
  <OP> <Hd>, <Hs>, <Hm>

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
	instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
	fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
	facgt to the scalar three same group.

Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 16:49:34 +00:00
Matthew Wahab 51d543ed93 [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.

The general form for these instructions is
  <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
  where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: New.
	* gas/aarch64/advsimd-fp16.s: New.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_V3SAMEH): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
	fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
	fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
	fcmgt, facgt and fminp to the vector three same group.

Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 16:44:02 +00:00
Jan Beulich 92e18d9343 gas: free allocated symbol name in .cfi_label handling
I've just noticed this further oversights of the original commit.
2015-12-14 09:25:10 +01:00
Alan Modra dafa877d36 Fix SH gas testsuite invalid assembly exposed by ec9ab52c
* gas/sh/tlsd.s: Use .tdata not .tbss.
	* gas/sh/tlsnopic.s: Likewise.
2015-12-12 21:36:39 +10:30
Matthew Wahab 1e6f4800fc [AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.

A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
	(parse_barrier_psb): New.
	(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
	(md_begin): Set up aarch64_hint_opt_hsh.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: Enable the statistical profiling
	extension.  Update the expected output.
	* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
	* gas/aarch64/system.d: Update the expected output.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): Add "csync".
	(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_feature_stat_profile): New.
	(STAT_PROFILE): New.
	(aarch64_opcode_table): Add "psb".
	(AARCH64_OPERANDS): Add "BARRIER_PSB".

Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11 10:22:40 +00:00
Matthew Wahab 55c144e691 [AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
	pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
	pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
	pmscr_el2.
	(aarch64_sys_reg_supported_p): Add architecture feature tests for
	the new registers.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
	system registers.
	* gas/aarch64/sysreg-2.d: Enable the statistical profiling
	extension and update the expected output.

Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
2015-12-11 09:52:11 +00:00
Matthew Wahab 73af8ed6b1 [AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.

The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.

This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "profile".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PROFILE): New.

Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-11 09:30:26 +00:00
Matthew Wahab 22a5455c6c [Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
	AT S1E1WP.
	* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
	(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
	feature test for "s1e1rp" and "s1e1wp".

Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
2015-12-10 17:00:27 +00:00
Matthew Wahab d6bf7ce6c2 [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10 16:40:45 +00:00
Matthew Wahab 6479e48ef9 [AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/uao-directive.d: New.
	* gas/aarch64/uao.d: New.
	* gas/aarch64/uao.s: New.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add "uao".
	(aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
	(aarch64_pstatefields): Add "uao".
	(aarch64_pstatefield_supported_p): Add checks for "uao".

Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
2015-12-10 16:03:56 +00:00
Jose E. Marchesi 7039122d13 gas: documentation for the SPARC %dN and %qN fp registers notation
gas/ChangeLog:

2015-12-10  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
	for floating-point registers.
2015-12-10 11:03:17 -05:00
Matthew Wahab 47f8114261 [AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.

The new registers are:
    erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
    erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
    vdisr_el2.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for new registers.
	* gas/aarch64/sysreg-2.s: Likewise.  Also replace some spaces with
	tabs.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
	"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
	"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
	(aarch64_sys_reg_supported_p): Add architecture feature tests for
	new registers.

Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
2015-12-10 14:10:24 +00:00
Matthew Wahab c8a6db6fa0 [AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: New.
	* gas/aarch64/system-2.s: New.
	* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_RAS): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_feature_ras): New.
	(RAS): New.
	(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10 14:10:15 +00:00
Matthew Wahab af117b3cf1 [AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.

This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

include/opcode
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
	AARCH64_FEATURE_V8_1.
	(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
	AARCH64_FEATURE_V8_1.

Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-10 14:10:06 +00:00
Andrew Burgess c740885937 arc/gas: Accept, but ignore, dummy arguments.
There's a set of legacy command line arguments that the arc assembler
still accepts, however, these arguments not longer have any effect on
the assembler.

Currently we return false from md_parse_option for all of these
arguments, with the result that the assembler terminates with an error
message.

We should return true indicating that the argument has been accepted,
even though we ignore it.

gas/ChangeLog:

	* config/tc-arc.c (md_parse_option): Return 1 in order to accept
	dummy arguments.
2015-12-10 09:23:19 +00:00
H.J. Lu 8eab413676 Implement Intel OSPKE instructions
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.

gas/testsuite/

	* gas/i386/i386.exp: Run ospke and x86-64-ospke.
	* gas/i386/ospke.d: New file.
	* gas/i386/ospke.s: Likewise.
	* gas/i386/x86-64-ospke.d: Likewise.

opcodes/

	* i386-dis.c (MOD_0F01_REG_5): New.
	(RM_0F01_REG_5): Likewise.
	(reg_table): Use MOD_0F01_REG_5.
	(mod_table): Add MOD_0F01_REG_5.
	(rm_table): Add RM_0F01_REG_5.
	* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
	(cpu_flags): Add CpuOSPKE.
	* i386-opc.h (CpuOSPKE): New.
	(i386_cpu_flags): Add cpuospke.
	* i386-opc.tbl: Add rdpkru and wrpkru instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-12-09 08:01:57 -08:00
Jan Beulich fa7cc15f24 gas/ELF: slightly relax elf/file*.d expectations
Despite the re-ordering done for the file symbols, some targets manage
to put section symbols ahead of it.
2015-12-09 14:35:07 +01:00
Jose E. Marchesi ec892a0718 sparc: support %dN and %qN syntax for FP registers.
The SPARC Refence Manual documents the %dN and %qN syntax to
refer to double and quad-precision floating-point registers,
respectively.  See OSA2015 Appendix C, Assembly Language Syntax,
C1.1 Register Names.

This patch adds support for these names to GAS.  This eases the
porting of software from Solaris to GNU/Linux, as these register
names have been supported by the Solaris linker for a long time
and many assembler require that support.

gas/ChangeLog:

2015-12-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
	double and quad-precision floating-point registers.
2015-12-09 07:34:32 -05:00
Nick Clifton c192dad243 Fix compile time warning building RX target. 2015-12-09 12:01:19 +00:00
Jan Beulich ec9ab52c32 gas: consistently emit diagnostics for non-zero data emission to .bss/.struct 2015-12-08 10:14:49 +01:00
Jan Beulich 35c1a43964 gas: don't get confused by .asci{i,z} after .struct
While not allowed, this certainly shouldn't result in confusing the
programmer (by skipping lines in unexpected ways): Without returning,
demand_empty_rest_of_line() (at the end of the function) will demand
the _next_ line to be empty, and without the conditional we would
ignore the next line.
2015-12-08 10:12:54 +01:00
Jan Beulich fbdf9406b0 ELF: don't re-order SHF_FILE symbols
.file directives may be used to identify the scope of local symbols,
the purpose of which gets subverted when re-ordering them. Only allow
the first of them to be moved to the first position.
2015-12-08 10:11:58 +01:00