2017-05-03 01:05:15 +02:00
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2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (append_insn): Call `symbol_append' for any
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expression symbol created for MIPS16 relaxation.
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(match_mips16_insn): Don't encode a constant value as an
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immediate with a PC-relative operand.
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* testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-1.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-2.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New
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test.
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* testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New
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test.
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* testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test.
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* testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New
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test.
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* testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr
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output.
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* testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source.
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* testsuite/gas/mips/mips16-branch-absolute-1.s: New test
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source.
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* testsuite/gas/mips/mips16-branch-absolute-2.s: New test
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source.
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* testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test
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source.
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* testsuite/gas/mips/mips.exp: Run the new tests.
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2017-04-27 03:25:33 +02:00
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2017-04-27 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (mips16_pcrel_val): New function, factored
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out from...
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(mips16_extended_frag): ... here.
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(md_convert_frag): Use `mips16_pcrel_val' rather than repeated
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code in MIPS16 relaxation, with `stretch' hardcoded to 0.
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2017-04-27 03:13:21 +02:00
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2017-04-27 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (RELAX_MIPS16_LONG_BRANCH): Rename to...
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(RELAX_MIPS16_ALWAYS_EXTENDED): ... this.
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(RELAX_MIPS16_MARK_LONG_BRANCH): Rename to...
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(RELAX_MIPS16_MARK_ALWAYS_EXTENDED): ... this.
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(RELAX_MIPS16_CLEAR_LONG_BRANCH): Rename to...
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(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): ... this.
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(mips16_extended_frag): Adjust accordingly.
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2017-04-27 04:50:10 +02:00
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2017-04-27 Alan Modra <amodra@gmail.com>
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* symbols.c (S_FORCE_RELOC): Separate section and symbol tests.
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MIPS/GAS: Fix `.option picX' handling with relaxation
Correct the handling of `.option pic0' and `.option pic2' GAS pseudo-ops
in relaxation and use the setting of `mips_pic' (which these directives
control) as at the time a relaxed frag has been created rather than the
final `mips_pic' setting at the end of the source file processed.
To do so record whether `mips_pic' is NO_PIC or not in the frag itself
and use this information throughout relaxation instead of `mips_pic' to
decide which of NO_PIC or SVR4_PIC to produce machine code for, fixing
code generation and removing a possible fatal failure reproducible with:
$ as -32 --relax-branch -o option-pic-relax-3.o option-pic-relax-3.s
option-pic-relax-3.s: Assembler messages:
option-pic-relax-3.s:7: Warning: relaxed out-of-range branch into a jump
option-pic-relax-3.s: Internal error in cvt_frag_to_fill at .../gas/write.c:490.
Please report this bug.
$
using the test source included, due to a buffer overrun in filling the
variable part of a frag.
Likewise use the `fx_tcbit2' flag of a BFD_RELOC_16_PCREL_S2 fixup to
handle the simple case of substituting an out of range unconditional
branch with an equivalent absolute jump in NO_PIC code.
Retain the current way of VXWORKS_PIC use, which commit 41a1578ed17c
("MIPS/GAS: Sanitize `.option picX' pseudo-op") has forbidden the use of
`.option picX' with.
gas/
* config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag.
(RELAX_PIC): New macro.
(RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO)
(RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT)
(RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND):
Shift bits.
(RELAX_BRANCH_ENCODE): Add `pic' flag.
(RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK)
(RELAX_BRANCH_TOOFAR): Shift bits.
(RELAX_BRANCH_PIC): New macro.
(RELAX_MICROMIPS_ENCODE): Add `pic' flag.
(RELAX_MICROMIPS_PIC): New macro.
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS)
(RELAX_MICROMIPS_RELAX32): Shift bits.
(relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE.
(append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE
and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the
first fixup created.
(md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the
fixup processed rather than `mips_pic' in choosing to relax an
out of range branch to a jump.
(relaxed_branch_length): Use the `pic' flag of the relaxed frag
rather than `mips_pic'.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_estimate_size_before_relax): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/option-pic-relax-0.d: New test.
* testsuite/gas/mips/option-pic-relax-1.d: New test.
* testsuite/gas/mips/option-pic-relax-2.d: New test.
* testsuite/gas/mips/option-pic-relax-3.d: New test.
* testsuite/gas/mips/option-pic-relax-3a.d: New test.
* testsuite/gas/mips/option-pic-relax-4.d: New test.
* testsuite/gas/mips/option-pic-relax-5.d: New test.
* testsuite/gas/mips/option-pic-relax-2.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-3.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-4.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-5.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-0.s: New test source.
* testsuite/gas/mips/option-pic-relax-1.s: New test source.
* testsuite/gas/mips/option-pic-relax-2.s: New test source.
* testsuite/gas/mips/option-pic-relax-3.s: New test source.
* testsuite/gas/mips/option-pic-relax-4.s: New test source.
* testsuite/gas/mips/option-pic-relax-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-27 01:47:15 +02:00
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2017-04-26 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag.
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(RELAX_PIC): New macro.
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(RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO)
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(RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT)
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(RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND):
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Shift bits.
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(RELAX_BRANCH_ENCODE): Add `pic' flag.
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(RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK)
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(RELAX_BRANCH_TOOFAR): Shift bits.
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(RELAX_BRANCH_PIC): New macro.
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(RELAX_MICROMIPS_ENCODE): Add `pic' flag.
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(RELAX_MICROMIPS_PIC): New macro.
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(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
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(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS)
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(RELAX_MICROMIPS_RELAX32): Shift bits.
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(relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE.
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(append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE
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and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the
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first fixup created.
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(md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the
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fixup processed rather than `mips_pic' in choosing to relax an
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out of range branch to a jump.
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(relaxed_branch_length): Use the `pic' flag of the relaxed frag
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rather than `mips_pic'.
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(relaxed_micromips_32bit_branch_length): Likewise.
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(md_estimate_size_before_relax): Likewise.
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(md_convert_frag): Likewise.
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* testsuite/gas/mips/option-pic-relax-0.d: New test.
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* testsuite/gas/mips/option-pic-relax-1.d: New test.
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* testsuite/gas/mips/option-pic-relax-2.d: New test.
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* testsuite/gas/mips/option-pic-relax-3.d: New test.
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* testsuite/gas/mips/option-pic-relax-3a.d: New test.
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* testsuite/gas/mips/option-pic-relax-4.d: New test.
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* testsuite/gas/mips/option-pic-relax-5.d: New test.
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* testsuite/gas/mips/option-pic-relax-2.l: New stderr output.
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* testsuite/gas/mips/option-pic-relax-3.l: New stderr output.
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* testsuite/gas/mips/option-pic-relax-4.l: New stderr output.
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* testsuite/gas/mips/option-pic-relax-5.l: New stderr output.
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* testsuite/gas/mips/option-pic-relax-0.s: New test source.
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* testsuite/gas/mips/option-pic-relax-1.s: New test source.
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* testsuite/gas/mips/option-pic-relax-2.s: New test source.
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* testsuite/gas/mips/option-pic-relax-3.s: New test source.
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* testsuite/gas/mips/option-pic-relax-4.s: New test source.
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* testsuite/gas/mips/option-pic-relax-5.s: New test source.
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* testsuite/gas/mips/mips.exp: Run the new tests.
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2017-04-25 17:07:00 +02:00
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/leave_enter.d: Update test.
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* testsuite/gas/arc/leave_enter.s: Likewise.
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2017-04-25 17:07:00 +02:00
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/b.d: Update test.
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* testsuite/gas/arc/noargs_hs.d: Likewise.
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2017-04-25 11:20:14 +02:00
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2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (md_convert_frag): Correct
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BFD_RELOC_MIPS16_16_PCREL_S1 fixup size.
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* testsuite/gas/mips/mips16-branch-addend-4.d: New test.
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* testsuite/gas/mips/mips16-branch-addend-5.d: New test.
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* testsuite/gas/mips/mips16-branch-addend-5.l: New stderr
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output.
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* testsuite/gas/mips/mips16-branch-addend-4.s: New test source.
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* testsuite/gas/mips/mips16-branch-addend-5.s: New test source.
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* testsuite/gas/mips/mips.exp: Run the new tests.
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2017-04-25 11:40:43 +02:00
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2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com>
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PR gas/21407
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* config/tc-sparc.c (md_apply_fix): Do not transform `call'
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instructions into branch instructions in fixups generating
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additional relocations.
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* testsuite/gas/sparc/call-relax.s: New file.
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* testsuite/gas/sparc/call-relax.d: Likewise.
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* testsuite/gas/sparc/call-relax-aout.d: Likewise.
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* testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
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2017-04-24 15:49:48 +02:00
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2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
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Forbid MOV.W and MOVW if destination is SP or PC.
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* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
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expectation of LDR not generating a MOVS for low registers and small
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constants. Add tests of MOVW generation.
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* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
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expected disassembly.
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2017-04-22 06:39:21 +02:00
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2017-04-22 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
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* testsuite/gas/ppc/vle.d: Update.
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2017-04-21 13:18:06 +02:00
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2017-04-21 Nick Clifton <nickc@redhat.com>
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PR binutils/21380
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* testsuite/gas/aarch64/illegal-3.s: New file.
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* testsuite/gas/aarch64/illegal-3.d: New file.
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2017-04-11 00:10:24 +02:00
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2017-04-11 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
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* testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
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2017-04-10 14:12:52 +02:00
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2017-04-10 Max Filippov <jcmvbkbc@gmail.com>
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* config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag):
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Initialize lps->frag_count with auto_litpool_limit.
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(xg_promote_candidate_litpool): New function.
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(xtensa_move_literals): Extract candidate litpool promotion code
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into separate function. Call it for all possible found
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candidates.
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(xtensa_switch_to_literal_fragment): Drop 'recursive' flag and
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call to xtensa_mark_literal_pool_location that it guards.
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Replace it with call to xtensa_maybe_create_literal_pool_frag.
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Initialize pool_location with created literal pool candidate.
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* testsuite/gas/xtensa/all.exp: Add new tests.
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* testsuite/gas/xtensa/auto-litpools-first1.d: New test results.
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* testsuite/gas/xtensa/auto-litpools-first1.s: New test.
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* testsuite/gas/xtensa/auto-litpools-first2.d: New test results.
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* testsuite/gas/xtensa/auto-litpools-first2.s: New test.
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* testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due
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to additional jump instruction.
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Remove E6500 insns from PPC_OPCODE_ALTIVEC2
This isn't losing anything from the testsuite. All of these insns
appear in testsuite/gas/ppc/e6500.s
opcodes/
* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
vector instructions with E6500 not PPCVEC2.
gas/
* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
* testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07 10:33:46 +02:00
|
|
|
|
2017-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
|
|
|
|
|
|
* testsuite/gas/ppc/altivec2.d: Adjust to suit.
|
|
|
|
|
|
|
2017-04-07 10:28:37 +02:00
|
|
|
|
2017-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/section12a.d: Don't expect alignment of 1
|
|
|
|
|
|
for .mbind.text.
|
|
|
|
|
|
|
2017-04-06 18:17:15 +02:00
|
|
|
|
2017-04-06 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
|
|
|
|
|
|
changes.
|
|
|
|
|
|
* testsuite/gas/wasm32/disass.d: New test.
|
|
|
|
|
|
* testsuite/gas/wasm32/disass.s: New test.
|
|
|
|
|
|
* testsuite/gas/wasm32/disass-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/wasm32/disass-2.s: New test.
|
|
|
|
|
|
* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
|
|
|
|
|
|
names.
|
|
|
|
|
|
* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
|
|
|
|
|
|
syntax.
|
|
|
|
|
|
* testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn
|
|
|
|
|
|
test to succeed.
|
|
|
|
|
|
|
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 18:05:48 +02:00
|
|
|
|
2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Mention support for ELF SHF_GNU_MBIND.
|
|
|
|
|
|
* config/obj-elf.c (section_match): New.
|
|
|
|
|
|
(get_section): Match both sh_info and group name.
|
|
|
|
|
|
(obj_elf_change_section): Add argument for sh_info. Pass both
|
|
|
|
|
|
sh_info and group name to get_section. Issue an error for
|
|
|
|
|
|
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
|
|
|
|
|
|
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
|
|
|
|
|
|
(obj_elf_section): Support SHF_GNU_MBIND section info.
|
|
|
|
|
|
* config/obj-elf.h (obj_elf_change_section): Add argument for
|
|
|
|
|
|
sh_info.
|
|
|
|
|
|
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
|
|
|
|
|
|
obj_elf_change_section.
|
|
|
|
|
|
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (microblaze_s_data): Likewise.
|
|
|
|
|
|
(microblaze_s_sdata): Likewise.
|
|
|
|
|
|
(microblaze_s_rdata): Likewise.
|
|
|
|
|
|
(microblaze_s_bss): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (s_change_section): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_profiler): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (parse_rx_section): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
|
|
|
|
|
|
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
|
|
|
|
|
|
section13.
|
|
|
|
|
|
* testsuite/gas/elf/section10.d: Updated.
|
|
|
|
|
|
* testsuite/gas/elf/section10.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section12.s: New file.
|
|
|
|
|
|
* testsuite/gas/elf/section12a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section12b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section13.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section13.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section13.s: Likewise.
|
|
|
|
|
|
|
2017-04-03 18:03:57 +02:00
|
|
|
|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to
|
|
|
|
|
|
avoid const warnings.
|
|
|
|
|
|
|
2017-03-30 01:05:40 +02:00
|
|
|
|
2017-03-30 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (riscv_clear_subsets): New function.
|
|
|
|
|
|
(riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
|
|
|
|
|
|
clear RVC when it's been previously set.
|
|
|
|
|
|
|
2017-03-31 13:54:38 +02:00
|
|
|
|
2017-03-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/21333
|
|
|
|
|
|
* config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative
|
|
|
|
|
|
fixups in mergeable sections to be adjusted.
|
|
|
|
|
|
|
2017-03-30 11:57:21 +02:00
|
|
|
|
2017-03-30 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
|
|
|
|
|
|
* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
|
|
|
|
|
|
* Makefile.am: Add WebAssembly assembler target.
|
|
|
|
|
|
* configure.tgt: Add WebAssembly assembler target.
|
|
|
|
|
|
* doc/c-wasm32.texi: New file: Start documenting WebAssembly
|
|
|
|
|
|
assembler.
|
|
|
|
|
|
* doc/all.texi: Define WASM32.
|
|
|
|
|
|
* doc/as.texinfo: Add WebAssembly entries.
|
|
|
|
|
|
* NEWS: Mention the new support.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* po/gas.pot: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* testsuite/gas/wasm32: New directory.
|
|
|
|
|
|
* testsuite/gas/wasm32/allinsn.d: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/allinsn.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-2.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-2.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-3.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-3.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-4.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-4.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-5.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-5.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-6.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-6.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-7.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-7.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-8.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-8.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-9.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-9.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-10.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-10.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-11.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-11.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-12.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-12.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-13.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-13.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-14.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-14.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-15.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-15.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-16.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-16.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-17.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-17.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-18.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-18.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-19.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-19.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-20.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-20.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-21.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-21.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-22.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-22.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-24.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-24.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-25.l: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/illegal-25.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/reloc.d: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/reloc.s: New file.
|
|
|
|
|
|
* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
|
|
|
|
|
|
architecture.
|
|
|
|
|
|
|
2017-03-29 05:13:06 +02:00
|
|
|
|
2017-03-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_parse_option): Reject -mraw.
|
|
|
|
|
|
|
2017-03-26 23:49:48 +02:00
|
|
|
|
2017-03-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21303
|
|
|
|
|
|
* testsuite/gas/ppc/pr21303.d,
|
|
|
|
|
|
* testsuite/gas/ppc/pr21303.s: New test
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 12:14:30 +02:00
|
|
|
|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-12.s: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-12.d: New file.
|
|
|
|
|
|
|
2017-03-24 14:22:16 +01:00
|
|
|
|
2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
|
|
|
|
|
|
CPU_DEFAULT is defined.
|
|
|
|
|
|
|
2017-03-21 16:36:44 +01:00
|
|
|
|
2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
|
|
|
|
|
|
-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
|
|
|
|
|
|
print an invalid default ISA string.
|
|
|
|
|
|
* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
|
|
|
|
|
|
|
2017-03-22 18:19:14 +01:00
|
|
|
|
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
|
|
|
|
|
|
reassigned fixup to size of jump instruction (3) and fx_r_type
|
|
|
|
|
|
to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
|
|
|
|
|
|
(add_jump_to_trampoline): Search
|
|
|
|
|
|
origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
|
|
|
|
|
|
symbol and use that slot instead of slot 0.
|
|
|
|
|
|
|
2017-03-21 14:21:02 +01:00
|
|
|
|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
|
|
|
|
|
|
from cpu_table. Remove vx2, and novx2 from cpu_flags.
|
|
|
|
|
|
|
2017-03-21 12:37:33 +01:00
|
|
|
|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-11.s: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-11.d: New file.
|
|
|
|
|
|
|
2017-03-20 17:57:07 +01:00
|
|
|
|
2017-03-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (2byte): Note that if no expressions are present
|
|
|
|
|
|
the directive does nothing. Emphasize that the output is
|
|
|
|
|
|
unaligned, and that this can have an effect on the relocations
|
|
|
|
|
|
generated.
|
|
|
|
|
|
(4byte): Simplify description. Refer back to the 2byte
|
|
|
|
|
|
description.
|
|
|
|
|
|
(8byte): Likewise.
|
|
|
|
|
|
|
2017-03-20 15:56:22 +01:00
|
|
|
|
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_fpus): Note entires that should not be
|
|
|
|
|
|
documented.
|
|
|
|
|
|
* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
|
|
|
|
|
|
neon-fp16. Fix spelling error.
|
|
|
|
|
|
|
2017-03-20 11:03:15 +01:00
|
|
|
|
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
|
|
|
|
|
|
|
2017-03-16 11:05:22 +01:00
|
|
|
|
2017-03-16 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
|
|
|
|
|
|
specially for ARCv2.
|
|
|
|
|
|
|
2017-03-07 11:15:02 +01:00
|
|
|
|
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
|
|
|
|
|
|
encoding format, which can accept 0-valued immediates.
|
|
|
|
|
|
(riscv_ip): Likewise.
|
|
|
|
|
|
|
2017-03-15 10:19:42 +01:00
|
|
|
|
2017-03-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time
|
|
|
|
|
|
warning about discarding a const qualifier.
|
|
|
|
|
|
|
2017-03-02 07:54:32 +01:00
|
|
|
|
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
|
|
|
|
|
|
|
2017-02-10 07:58:52 +01:00
|
|
|
|
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (md_apply_fix): Set fx_frag and
|
|
|
|
|
|
fx_next->fx_frag for CFA_advance_loc relocations.
|
|
|
|
|
|
|
2017-02-02 08:27:18 +01:00
|
|
|
|
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (md_apply_fix): Compute the correct offsets
|
|
|
|
|
|
for CFA relocations.
|
|
|
|
|
|
|
2017-03-13 10:58:04 +01:00
|
|
|
|
2017-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21202
|
|
|
|
|
|
* config/tc-aarch64.c (reloc_table): Rename
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
|
|
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
(aarch64_force_relocation): Likewise.
|
|
|
|
|
|
* testsuite/gas/aarch64/tls.d: Update regexp.
|
|
|
|
|
|
|
2017-03-10 16:42:04 +01:00
|
|
|
|
2017-03-10 Tobin C. Harding <me@tobin.cc>
|
|
|
|
|
|
Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (2byte): Tidy up wording. Add note that
|
|
|
|
|
|
overlarge values will produce a warning message and be trunacted.
|
|
|
|
|
|
(4byte): Likewise.
|
|
|
|
|
|
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
|
|
|
|
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (_i386_insn): Add dir_encoding and
|
|
|
|
|
|
vec_encoding. Remove swap_operand and need_vrex.
|
|
|
|
|
|
(extra_symbol_chars): Add '}'.
|
|
|
|
|
|
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
|
|
|
|
|
|
mnemonic.
|
|
|
|
|
|
(build_vex_prefix): Don't use 2-byte VEX encoding with
|
|
|
|
|
|
{vex3}. Check dir_encoding and load.
|
|
|
|
|
|
(parse_insn): Check pseudo prefixes. Set dir_encoding.
|
|
|
|
|
|
(VEX_check_operands): Likewise.
|
|
|
|
|
|
(match_template): Check dir_encoding and load.
|
|
|
|
|
|
(parse_real_register): Set vec_encoding instead of need_vrex.
|
|
|
|
|
|
(parse_register): Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
|
|
|
|
|
|
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
|
|
|
|
|
|
* testsuite/gas/i386/pseudos.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/pseudos.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
|
|
|
|
|
|
|
2017-03-09 03:49:03 +01:00
|
|
|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
|
|
|
|
|
|
(objdump): Use the -Mpower8 option.
|
|
|
|
|
|
|
2017-03-08 21:00:42 +01:00
|
|
|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <lnia> New test.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
|
2017-03-07 10:09:32 +01:00
|
|
|
|
2017-03-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
|
|
|
|
|
|
|
2017-03-07 07:16:36 +01:00
|
|
|
|
2017-03-07 Tobin C. Harding <me@tobin.cc>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (2byte, 4byte, 8byte): Document.
|
|
|
|
|
|
* doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
|
|
|
|
|
|
|
2017-03-07 00:26:37 +01:00
|
|
|
|
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .cet.
|
|
|
|
|
|
* doc/c-i386.texi: Document cet.
|
|
|
|
|
|
* testsuite/gas/i386/cet-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/cet.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/cet.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-cet.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-cet.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
|
|
|
|
|
|
|
2017-03-07 00:00:52 +01:00
|
|
|
|
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
|
|
|
|
|
|
|
2017-03-05 13:55:16 +01:00
|
|
|
|
2017-03-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dw2gencfi.c (encoding_size): Return unsigned int.
|
|
|
|
|
|
(emit_expr_encoded): Assert size matches reloc bitsize.
|
|
|
|
|
|
(output_fde): Use unsigned for offset_size and addr_size. Set
|
|
|
|
|
|
addr_size earlier and use in place of constant 4 and uses of
|
|
|
|
|
|
DWARF2_FDE_RELOC_SIZE. Assert it matches reloc bitsize.
|
|
|
|
|
|
|
2017-03-05 13:25:29 +01:00
|
|
|
|
2017-03-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dw2gencfi.c: Wrap overlong lines. Add parens for emacs
|
|
|
|
|
|
auto reformat. Formatting and whitespace fixes.
|
|
|
|
|
|
|
2017-03-05 23:37:54 +01:00
|
|
|
|
2017-03-05 Mark Wielaard <mark@klomp.org>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
|
|
|
|
|
|
DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
|
|
|
|
|
|
(out_debug_info): Accept symbols to name, comp_dir and producer in
|
|
|
|
|
|
the .debug_str section and emit those offsets not full strings.
|
|
|
|
|
|
(out_debug_str): New function that outputs the strings for name,
|
|
|
|
|
|
comp_dir and producer in .debug_str and generates symbols to those
|
|
|
|
|
|
strings.
|
|
|
|
|
|
(out_debug_line): Create a .debug_str section if necessary and call
|
|
|
|
|
|
out_debug_str before calling out_debug_info.
|
|
|
|
|
|
* testsuite/gas/aarch64/dwarf.d: Add extra section symbol to expected
|
|
|
|
|
|
output.
|
|
|
|
|
|
|
GAS: Fix bogus "attempt to move .org backwards" relaxation errors
Fix a commit 6afe8e98a664 ("internal error for backwards .org"),
<https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>,
GAS regression that caused legitimate code to fail assembly with an
"attempt to move .org backwards" error.
For example with the `mips-linux' target we get:
$ cat org.s
.set mips16
la $2, foo
.org 0x1000
.align 2
foo:
.half 0
$ as -o org.o org.s
org.s: Assembler messages:
org.s:3: Error: attempt to move .org backwards
$
where the location pointer is obviously not moved backwards with `.org'.
The cause is positive `stretch' in relaxation due to a PC-relative ADDIU
instruction (produced from the LA macro used) getting expanded from 2 to
4 bytes as `foo' is noticed to be out of range for the short encoding.
This in turn triggers logic in `relax_segment' which concludes in the
processing of an `rs_org' frag produced that the location pointer is
moved backwards while in fact only the amount to space forward to the
location requested has shrunk, resulting in a negative growth of the
frag.
Correct the bad logic then and instead verify that the fixed part of an
`rs_org' frag has not overrun the location requested, as per the comment
already included with the error message:
/* Growth may be negative, but variable part of frag
cannot have fewer than 0 chars. That is, we can't
.org backwards. */
which accurately describes the regression scenario. Move the comment
ahead the conditional noted, for clarity.
Add generic and MIPS test cases for the `.org' pseudo-op, including the
test case discussed though not integrated with the offending commit in
particular, adjusted to work across all targets.
gas/
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
part of the frag has overrun the location requested.
* testsuite/gas/all/org-1.d: New test.
* testsuite/gas/all/org-2.d: New test.
* testsuite/gas/all/org-3.d: New test.
* testsuite/gas/all/org-4.d: New test.
* testsuite/gas/all/org-5.d: New test.
* testsuite/gas/all/org-6.d: New test.
* testsuite/gas/all/org-1.l: New stderr output.
* testsuite/gas/all/org-2.l: New stderr output.
* testsuite/gas/all/org-3.l: New stderr output.
* testsuite/gas/all/org-1.s: New test source.
* testsuite/gas/all/org-2.s: New test source.
* testsuite/gas/all/org-3.s: New test source.
* testsuite/gas/all/org-4.s: New test source.
* testsuite/gas/all/org-5.s: New test source.
* testsuite/gas/all/org-6.s: New test source.
* testsuite/gas/all/gas.exp: Run the new tests.
* testsuite/gas/mips/org-1.d: New test.
* testsuite/gas/mips/org-2.d: New test.
* testsuite/gas/mips/org-3.d: New test.
* testsuite/gas/mips/org-4.d: New test.
* testsuite/gas/mips/org-5.d: New test.
* testsuite/gas/mips/org-6.d: New test.
* testsuite/gas/mips/org-7.d: New test.
* testsuite/gas/mips/org-8.d: New test.
* testsuite/gas/mips/org-9.d: New test.
* testsuite/gas/mips/org-10.d: New test.
* testsuite/gas/mips/org-11.d: New test.
* testsuite/gas/mips/org-12.d: New test.
* testsuite/gas/mips/org-1.l: New stderr output.
* testsuite/gas/mips/org-4.l: New stderr output.
* testsuite/gas/mips/org-5.l: New stderr output.
* testsuite/gas/mips/org-6.l: New stderr output.
* testsuite/gas/mips/org-10.l: New stderr output.
* testsuite/gas/mips/org-1.s: New test source.
* testsuite/gas/mips/org-2.s: New test source.
* testsuite/gas/mips/org-3.s: New test source.
* testsuite/gas/mips/org-4.s: New test source.
* testsuite/gas/mips/org-5.s: New test source.
* testsuite/gas/mips/org-6.s: New test source.
* testsuite/gas/mips/org-7.s: New test source.
* testsuite/gas/mips/org-8.s: New test source.
* testsuite/gas/mips/org-9.s: New test source.
* testsuite/gas/mips/org-10.s: New test source.
* testsuite/gas/mips/org-11.s: New test source.
* testsuite/gas/mips/org-12.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-03-02 02:24:15 +01:00
|
|
|
|
2017-03-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
|
|
|
|
|
|
part of the frag has overrun the location requested.
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/org-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-6.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/org-1.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/all/org-2.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/all/org-3.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/all/org-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/org-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/org-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/org-4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/org-5.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/org-6.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Run the new tests.
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/org-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-7.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-8.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-9.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-10.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-11.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-12.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/org-1.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/org-4.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/org-5.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/org-6.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/org-10.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/org-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-5.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-6.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-7.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-8.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-9.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-10.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-11.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/org-12.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2017-03-01 15:51:13 +01:00
|
|
|
|
2017-03-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
|
|
|
|
|
|
|
2017-02-28 10:53:35 +01:00
|
|
|
|
2017-02-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx.s: Add suffixed variants of
|
|
|
|
|
|
VPCMPESTR{I,M}.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sse2avx.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sse4_2.s: Add suffixed variants
|
|
|
|
|
|
of PCMPESTR{I,M}.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-sse4_2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sse4_2-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sse4_2.d: Likewise.
|
|
|
|
|
|
|
2017-02-28 01:08:51 +01:00
|
|
|
|
2017-02-28 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
|
|
|
|
|
|
|
2017-02-27 23:02:36 +01:00
|
|
|
|
2017-02-28 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
|
|
|
|
|
|
(md_apply_fix): Remove fx_subsy check. Move code converting to
|
|
|
|
|
|
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
|
|
|
|
|
|
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
|
|
|
|
|
|
that is done now by the generic code via..
|
|
|
|
|
|
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
|
|
|
|
|
|
(TC_VALIDATE_FIX_SUB): Define.
|
|
|
|
|
|
|
2017-02-28 01:14:08 +01:00
|
|
|
|
2017-02-28 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
|
|
|
|
|
|
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
|
|
|
|
|
|
encoding patterns.
|
|
|
|
|
|
* testsuite/gas/mips/jalr4-n64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
|
|
|
|
|
|
|
2017-02-24 14:32:27 +01:00
|
|
|
|
2017-02-25 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/strtab.s: Don't put directives on first
|
|
|
|
|
|
column or continuation with labels not in first column.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
|
|
|
|
|
|
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
|
|
|
|
|
|
to be used with SVE registers.
|
|
|
|
|
|
(parse_operands): Handle new SVE operands.
|
|
|
|
|
|
(aarch64_features): Make "sve" require F16 rather than FP. Also
|
|
|
|
|
|
require COMPNUM.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
|
|
|
|
|
|
Include compnum tests.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve.d: Update accordingly.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
|
|
|
|
|
|
update expected output for new FMOV and MOV alternatives.
|
|
|
|
|
|
|
2017-02-24 19:27:26 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-aarch64.texi: Add a "compnum" entry.
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_features): Likewise,
|
|
|
|
|
|
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
|
|
|
|
|
|
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
|
|
|
|
|
|
|
2017-02-24 10:04:26 +01:00
|
|
|
|
2017-02-24 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-opcode.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/opcode.d: Adjust accordingly.
|
|
|
|
|
|
* testsuite/gas/i386/opcode-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
|
|
|
|
|
|
|
2017-02-24 09:23:50 +01:00
|
|
|
|
2017-02-24 Sheldon Lobo <sheldon.lobo@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
Test cases for the architecture level aware SPARC ASI work.
|
|
|
|
|
|
* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
|
|
|
|
|
|
* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
|
|
|
|
|
|
* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
|
|
|
|
|
|
* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
|
|
|
|
|
|
* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
|
|
|
|
|
|
|
2017-02-23 20:26:53 +01:00
|
|
|
|
2017-02-23 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/jalr4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalr4-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalr4-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalr4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2017-02-23 16:49:37 +01:00
|
|
|
|
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
Add support for associating SPARC ASIs with an architecture level.
|
|
|
|
|
|
* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.
|
|
|
|
|
|
|
2017-02-23 11:21:10 +01:00
|
|
|
|
2017-02-23 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/err-sizeof.s: Don't use sums or differences
|
|
|
|
|
|
of symbols as expression.
|
|
|
|
|
|
|
|
|
|
|
|
2017-02-23 Jan Beulich <jbeulich@suse.com>
|
2017-02-23 11:00:44 +01:00
|
|
|
|
|
|
|
|
|
|
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.d: Add 32- and 16-
|
|
|
|
|
|
bit GPR forms of BNDCL, BNDCU, and BNDCN. Add RSP-as-index
|
|
|
|
|
|
Intel syntax forms of BNDMK, BNDSTX, and BNDLDX.
|
|
|
|
|
|
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust.
|
|
|
|
|
|
|
GAS: Consistently fix labels at the `.end' pseudo-op
Fix a functional regression with the `.end' pseudo-op, introduced with
commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit
dcd410fe1544 ("GNU as 2.14 on IRIX 6: crashes with shared libs"),
<https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused
symbol values for labels placed between the end of a function's contents
and its terminating `.end' followed by one of the alignment pseudo-ops
to be different depending on whether either `-mdebug', or `-mno-pdr', or
neither of the command-line options is in effect, be it implied or
specified.
Given debug-label-end.s as follows and the `mips-linux' target we have:
$ cat debug-label-end.s
.text
.globl foo
.globl bar
.align 4, 0
.ent foo
foo:
nop
.aent bar
bar:
.insn
.end foo
.align 4, 0
.space 16
.globl baz
.ent baz
baz:
nop
.end baz
.align 4, 0
.space 16
$ as -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mdebug -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mno-pdr -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$
The reason is the call to `md_flush_pending_output', which in the case
of `mips*-*-*' targets expands to `mips_emit_delays', which in turn
calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which
clears the list of outstanding labels. That list is in turn consulted
in `mips_align', called in the interpretation of alignment directives,
and the labels adjusted to the current location.
A call to `md_flush_pending_output' is only made from `s_mips_end' and
then only if `-mpdr' is in effect, which is the default for `*-*-linux*'
and some other `mips*-*-*' targets. A call to `md_flush_pending_output'
is never made from `ecoff_directive_end', which is used in place of
`s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or
`-mdebug' is in effect the list of outstanding labels makes it through
to any alignment directive that follows and the labels are differently
interpreted depending on the command-lines options used. And we want
code produced to be always the same.
Call `md_flush_pending_output' unconditionally then in `s_mips_end' and
add such a call from `ecoff_directive_end' as well, as long as the macro
is defined. While `ecoff_directive_end' is shared among targets, the
only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it
does not define `md_flush_pending_output'. So the semantics isn't going
to change for it and neither it has to have its `s_alpha_end' updated
or have code in `ecoff_directive_end' conditionalized.
gas/
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
`md_flush_pending_output'.
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
`md_flush_pending_output' unconditionally.
* testsuite/gas/mips/debug-label-end-1.d: New test.
* testsuite/gas/mips/debug-label-end-2.d: New test.
* testsuite/gas/mips/debug-label-end-3.d: New test.
* testsuite/gas/mips/debug-label-end.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-17 21:30:55 +01:00
|
|
|
|
2017-02-22 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
|
|
|
|
|
|
`md_flush_pending_output'.
|
|
|
|
|
|
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
|
|
|
|
|
|
`md_flush_pending_output' unconditionally.
|
|
|
|
|
|
* testsuite/gas/mips/debug-label-end-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/debug-label-end-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/debug-label-end-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/debug-label-end.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2017-02-22 14:17:33 +01:00
|
|
|
|
2017-02-22 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/err-sizeof.s: Include cris*-*-* in the list of
|
|
|
|
|
|
targets yielding an error message matching "too complex".
|
|
|
|
|
|
|
2017-02-22 12:57:49 +01:00
|
|
|
|
2017-02-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/vcmp-noprefix-imm.d: Skip for non-ELF targets.
|
|
|
|
|
|
|
2017-02-22 10:37:52 +01:00
|
|
|
|
2017-02-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* expr.c (operand): Handle missing operand to .startof.() and
|
|
|
|
|
|
.sizeof.().
|
|
|
|
|
|
* testsuite/gas/all/err-sizeof.s: New.
|
|
|
|
|
|
|
2017-02-20 02:36:52 +01:00
|
|
|
|
2017-02-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* NEWS: Revise powerpc register check.
|
|
|
|
|
|
* config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid
|
|
|
|
|
|
register expression" a warning.
|
|
|
|
|
|
|
GAS: Add ECOFF `.aent' pseudo-op support
Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section
support with ELF objects and, for consistency, also with ECOFF objects.
This is so that the same MIPS source can be assembled without and with
`.mdebug' section generation enabled.
Taking the `gas/testsuite/gas/mips/aent.s' test case source as an
example and the `mips-linux' target we have:
$ as -o aent.o aent.s
$ as -mdebug -o aent.o aent.s
aent.s: Assembler messages:
aent.s:10: Error: unknown pseudo-op: `.aent'
$
because for the !ECOFF_DEBUGGING case (which is the default) the
pseudo-op is already handled by the MIPS backend with `s_mips_ent',
however no handler is present for the opposite case.
For the MIPS target this is a functional regression introduced with
commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where
support for the `.mdebug' section was added along with its associated
`-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency
between the assembly syntax supported for each of these options as far
as the `.aent' pseudo-op is concerned.
Assembly language documentation available describes the pseudo-op
respectively as follows[1]:
"
.aent name, symno Sets an alternate entry point for the current
procedure. Use this information when you want
to generate information for the debugger. It must
appear inside an .ent/.end pair."
and[2]:
"
.aent name [,symno]
Sets an alternate entry point for the current procedure. Use this
information when you want to generate information for the debugger.
This directive must appear between a pair of .ent and .end directives.
(The optional symno is for compiler use only. It refers to a dense
number in a .T file (symbol table).)"
Copy the approach from `s_mips_ent' then and add `.aent' support to the
`.ent' pseudo-op handler shared between the ELF and ECOFF object file
format backends, by setting BSF_FUNCTION for the symbol requested.
References:
[1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics,
Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96
<http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf>
[2] "Digital UNIX Assembly Language Programmer's Guide", Digital
Equipment Corporation, Order Number: AA-PS31D-TE, March 1996,
Chapter 5 "Assembler Directives", p. 5-2
<http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF>
gas/
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
* testsuite/gas/mips/aent-2.d: New test.
* testsuite/gas/mips/aent-mdebug.d: New test.
* testsuite/gas/mips/aent-mdebug-2.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-16 02:50:29 +01:00
|
|
|
|
2017-02-17 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
|
|
|
|
|
|
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
|
|
|
|
|
|
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/aent-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/aent-mdebug.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/aent-mdebug-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2017-02-15 17:54:21 +01:00
|
|
|
|
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-sysreg.s,
|
|
|
|
|
|
testsuite/gas/aarch64/sve-sysreg.d,
|
|
|
|
|
|
testsuite/gas/aarch64/sve-sysreg-invalid.d,
|
|
|
|
|
|
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
|
|
|
|
|
|
|
2017-02-15 17:51:17 +01:00
|
|
|
|
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-aarch64.texi: Fix sve entry.
|
|
|
|
|
|
|
2017-02-15 11:57:51 +01:00
|
|
|
|
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
|
|
|
|
|
|
information from input expression.
|
|
|
|
|
|
(assemble_insn): Make sure pcrel is correctly set.
|
|
|
|
|
|
(arc_pcrel_adjust): Compensate for PCL rounding.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add01.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add02.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add03.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add03.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add04.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-add04.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-ld01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-ld01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-ld02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-ld02.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mov01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mov01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mov02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mov02.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mpy01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-mpy01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub02.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub03.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub03.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub04.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-sub04.s: Likewise.
|
|
|
|
|
|
|
2017-02-15 09:52:53 +01:00
|
|
|
|
2017-02-09 Vineet Gupta <vgupta@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/st.d: Update for 0xe having a name now
|
|
|
|
|
|
|
2017-02-14 11:08:21 +01:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* NEWS: Mention powerpc register checks.
|
|
|
|
|
|
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
|
|
|
|
|
|
(pre_defined_registers): Delete fpscr and pmr entries. Set
|
|
|
|
|
|
register type in flags.
|
|
|
|
|
|
(cr_names): Set type in flags.
|
|
|
|
|
|
(reg_name_search): Return pointer to struct pd_reg rather than value.
|
|
|
|
|
|
(register_name): Adjust to suit. Set X_md from flags.
|
|
|
|
|
|
(ppc_parse_name): Likewise.
|
|
|
|
|
|
(ppc_optimize_expr): New function.
|
|
|
|
|
|
(md_assemble): Verify expresion reg flags match operand.
|
|
|
|
|
|
* config/tc-ppc.h (md_optimize_expr): Define.
|
|
|
|
|
|
(ppc_optimize_expr): Declare.
|
|
|
|
|
|
|
2017-02-14 11:00:27 +01:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/cell.s: Correct invalid registers.
|
|
|
|
|
|
* testsuite/gas/ppc/vle-simple-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/vle-simple-2.s: Likewise.
|
|
|
|
|
|
|
2017-02-13 18:46:59 +01:00
|
|
|
|
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
|
|
|
|
|
|
syntax.
|
|
|
|
|
|
* testsuite/gas/arm/vcmp-noprefix-imm.d: New file.
|
|
|
|
|
|
* testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
|
|
|
|
|
|
|
2017-02-10 05:18:23 +01:00
|
|
|
|
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
|
|
|
|
|
|
|
2017-02-02 17:23:21 +01:00
|
|
|
|
2017-02-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Overview): Select MIPS options for man page
|
|
|
|
|
|
inclusion.
|
|
|
|
|
|
|
2017-01-30 18:11:22 +01:00
|
|
|
|
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
|
|
|
|
|
|
(options): Add OPTION_IGNORE_BRANCH_ISA and
|
|
|
|
|
|
OPTION_NO_IGNORE_BRANCH_ISA enum values.
|
|
|
|
|
|
(md_longopts): Add "mignore-branch-isa" and
|
|
|
|
|
|
"mno-ignore-branch-isa" options.
|
|
|
|
|
|
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
|
|
|
|
|
|
OPTION_NO_IGNORE_BRANCH_ISA.
|
|
|
|
|
|
(fix_bad_cross_mode_branch_p): Return FALSE if
|
|
|
|
|
|
`mips_ignore_branch_isa' has been set.
|
|
|
|
|
|
(md_show_usage): Add `-mignore-branch-isa' and
|
|
|
|
|
|
`-mno-ignore-branch-isa'.
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Target MIPS options): Add
|
|
|
|
|
|
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
|
|
|
|
|
|
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
|
|
|
|
|
|
`-mno-ignore-branch-isa' options.
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2017-01-30 18:10:31 +01:00
|
|
|
|
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n32-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n32-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n64-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n64-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Fold corresponding list tests
|
|
|
|
|
|
into the new tests.
|
|
|
|
|
|
|
2017-01-27 13:00:55 +01:00
|
|
|
|
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21056
|
|
|
|
|
|
* testsuite/gas/tic6x/insns16-parallel.s: New test case.
|
|
|
|
|
|
* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
|
|
|
|
|
|
|
2017-01-25 08:24:47 +01:00
|
|
|
|
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (aarch64*-*-rtems*): Remove.
|
|
|
|
|
|
(bfin-*-rtems*): Likewise.
|
|
|
|
|
|
(h8300-*-rtems*): Likewise.
|
|
|
|
|
|
(i386-*-rtems*): Likewise.
|
|
|
|
|
|
(m32c-*-rtems*): Likewise.
|
|
|
|
|
|
(m32r-*-rtems*): Likewise.
|
|
|
|
|
|
(m68k-*-rtems*): Likewise.
|
|
|
|
|
|
(mips-*-rtems*): Likewise.
|
|
|
|
|
|
(nios2-*-rtems*): Likewise.
|
|
|
|
|
|
(ppc-*-rtems*): Likewise.
|
|
|
|
|
|
(sh-*-rtems*): Likewise.
|
|
|
|
|
|
(sparc64-*-rtems*): Likewise.
|
|
|
|
|
|
(sparc-*-rtems*): Likewise.
|
|
|
|
|
|
(*-*-rtems*) Use ELF format.
|
|
|
|
|
|
|
2017-01-25 08:23:44 +01:00
|
|
|
|
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (arm-*-rtems*): Move to (arm-*-eabi*).
|
|
|
|
|
|
|
2017-01-25 08:22:27 +01:00
|
|
|
|
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (sh-*-rtemscoff*): Remove.
|
|
|
|
|
|
|
2017-01-19 09:10:51 +01:00
|
|
|
|
2017-01-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (riscv*-*-*): Remove em=linux.
|
|
|
|
|
|
|
2017-01-23 16:23:07 +01:00
|
|
|
|
2017-01-23 Sebastian Rasmussen <sebras@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/21072
|
|
|
|
|
|
* asintl.h: Fix spelling mistakes and typos.
|
|
|
|
|
|
* atof-generic.c: Likewise.
|
|
|
|
|
|
* bit_fix.h: Likewise.
|
|
|
|
|
|
* config/atof-ieee.c: Likewise.
|
|
|
|
|
|
* config/bfin-defs.h: Likewise.
|
|
|
|
|
|
* config/bfin-parse.y: Likewise.
|
|
|
|
|
|
* config/obj-coff-seh.h: Likewise.
|
|
|
|
|
|
* config/obj-coff.c: Likewise.
|
|
|
|
|
|
* config/obj-evax.c: Likewise.
|
|
|
|
|
|
* config/obj-macho.c: Likewise.
|
|
|
|
|
|
* config/rx-parse.y: Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c: Likewise.
|
|
|
|
|
|
* config/tc-alpha.c: Likewise.
|
|
|
|
|
|
* config/tc-arc.c: Likewise.
|
|
|
|
|
|
* config/tc-arm.c: Likewise.
|
|
|
|
|
|
* config/tc-avr.c: Likewise.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-cr16.c: Likewise.
|
|
|
|
|
|
* config/tc-cris.c: Likewise.
|
|
|
|
|
|
* config/tc-crx.c: Likewise.
|
|
|
|
|
|
* config/tc-d10v.c: Likewise.
|
|
|
|
|
|
* config/tc-d30v.c: Likewise.
|
|
|
|
|
|
* config/tc-dlx.c: Likewise.
|
|
|
|
|
|
* config/tc-epiphany.c: Likewise.
|
|
|
|
|
|
* config/tc-frv.c: Likewise.
|
|
|
|
|
|
* config/tc-hppa.c: Likewise.
|
|
|
|
|
|
* config/tc-i370.c: Likewise.
|
|
|
|
|
|
* config/tc-i386-intel.c: Likewise.
|
|
|
|
|
|
* config/tc-i386.c: Likewise.
|
|
|
|
|
|
* config/tc-i960.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-m32r.c: Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c: Likewise.
|
|
|
|
|
|
* config/tc-m68k.c: Likewise.
|
|
|
|
|
|
* config/tc-mcore.c: Likewise.
|
|
|
|
|
|
* config/tc-mep.c: Likewise.
|
|
|
|
|
|
* config/tc-mep.h: Likewise.
|
|
|
|
|
|
* config/tc-metag.c: Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c: Likewise.
|
|
|
|
|
|
* config/tc-mips.c: Likewise.
|
|
|
|
|
|
* config/tc-mmix.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.h: Likewise.
|
|
|
|
|
|
* config/tc-nds32.c: Likewise.
|
|
|
|
|
|
* config/tc-nds32.h: Likewise.
|
|
|
|
|
|
* config/tc-nios2.c: Likewise.
|
|
|
|
|
|
* config/tc-nios2.h: Likewise.
|
|
|
|
|
|
* config/tc-ns32k.c: Likewise.
|
|
|
|
|
|
* config/tc-pdp11.c: Likewise.
|
|
|
|
|
|
* config/tc-ppc.c: Likewise.
|
|
|
|
|
|
* config/tc-pru.c: Likewise.
|
|
|
|
|
|
* config/tc-rx.c: Likewise.
|
|
|
|
|
|
* config/tc-s390.c: Likewise.
|
|
|
|
|
|
* config/tc-score.c: Likewise.
|
|
|
|
|
|
* config/tc-score7.c: Likewise.
|
|
|
|
|
|
* config/tc-sh.c: Likewise.
|
|
|
|
|
|
* config/tc-sh64.c: Likewise.
|
|
|
|
|
|
* config/tc-sparc.c: Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c: Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c: Likewise.
|
|
|
|
|
|
* config/tc-v850.c: Likewise.
|
|
|
|
|
|
* config/tc-vax.c: Likewise.
|
|
|
|
|
|
* config/tc-visium.c: Likewise.
|
|
|
|
|
|
* config/tc-xgate.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c: Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
* config/tc-z8k.c: Likewise.
|
|
|
|
|
|
* config/te-vms.c: Likewise.
|
|
|
|
|
|
* config/xtensa-relax.c: Likewise.
|
|
|
|
|
|
* doc/as.texinfo: Likewise.
|
|
|
|
|
|
* doc/c-arm.texi: Likewise.
|
|
|
|
|
|
* doc/c-hppa.texi: Likewise.
|
|
|
|
|
|
* doc/c-i370.texi: Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Likewise.
|
|
|
|
|
|
* doc/c-m32r.texi: Likewise.
|
|
|
|
|
|
* doc/c-m68k.texi: Likewise.
|
|
|
|
|
|
* doc/c-mmix.texi: Likewise.
|
|
|
|
|
|
* doc/c-msp430.texi: Likewise.
|
|
|
|
|
|
* doc/c-nds32.texi: Likewise.
|
|
|
|
|
|
* doc/c-ns32k.texi: Likewise.
|
|
|
|
|
|
* doc/c-riscv.texi: Likewise.
|
|
|
|
|
|
* doc/c-rx.texi: Likewise.
|
|
|
|
|
|
* doc/c-s390.texi: Likewise.
|
|
|
|
|
|
* doc/c-tic6x.texi: Likewise.
|
|
|
|
|
|
* doc/c-tilegx.texi: Likewise.
|
|
|
|
|
|
* doc/c-tilepro.texi: Likewise.
|
|
|
|
|
|
* doc/c-v850.texi: Likewise.
|
|
|
|
|
|
* doc/c-xgate.texi: Likewise.
|
|
|
|
|
|
* doc/c-xtensa.texi: Likewise.
|
|
|
|
|
|
* dwarf2dbg.c: Likewise.
|
|
|
|
|
|
* ecoff.c: Likewise.
|
|
|
|
|
|
* itbl-ops.c: Likewise.
|
|
|
|
|
|
* listing.c: Likewise.
|
|
|
|
|
|
* macro.c: Likewise.
|
|
|
|
|
|
* po/gas.pot: Likewise.
|
|
|
|
|
|
* read.c: Likewise.
|
|
|
|
|
|
* struc-symbol.h: Likewise.
|
|
|
|
|
|
* symbols.h: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relocs-errors.err: Likewise.
|
|
|
|
|
|
* write.c: Likewise.
|
|
|
|
|
|
|
2017-01-23 14:32:12 +01:00
|
|
|
|
2017-01-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2017-01-20 11:32:25 +01:00
|
|
|
|
2017-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (parse_operands): Check for operand overflow
|
|
|
|
|
|
before setting the unspecified bit.
|
|
|
|
|
|
|
PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sections
Correct a regression from commit 8614eeee67f9 ("Traditional MIPS
patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>,
which caused symbols in linkonce or what is these days known as comdat
sections to be treated as external for the purpose of PIC relocation
generation even if their binding remains STB_LOCAL. This in turn
disabled GOT16/LO16 relocation pairing with references to such symbols,
as no complementing LO16 relocation is expected for external GOT16
references in the o32 ABI, which ultimately leads to link errors, e.g.:
ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]'
as with the LD test case included with this change.
Revert the special case for symbols in comdat sections then, making code
actually match `adjust_reloc_syms' as indicated in its explanatory
comment, and adjust calling code accordingly. Also bring back the
corresponding description of what now is `s_is_linkonce', lost with
commit 5f0fe04bc550 ("Improved MIPS16/MIPS32 code intermixing for
gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>.
gas/
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
PR gas/20649
* testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16
relocation pairing link test.
2017-01-18 19:18:21 +01:00
|
|
|
|
2017-01-18 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20649
|
|
|
|
|
|
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
|
|
|
|
|
|
symbols, remove the `segtype' parameter.
|
|
|
|
|
|
(mips_frob_file, md_estimate_size_before_relax): Adjust
|
|
|
|
|
|
accordingly.
|
|
|
|
|
|
(s_is_linkonce): Add an explanatory comment.
|
|
|
|
|
|
* testsuite/gas/mips/comdat-reloc.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/comdat-reloc.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new test.
|
|
|
|
|
|
|
2017-01-18 18:08:34 +01:00
|
|
|
|
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
|
|
|
|
|
|
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
|
|
|
|
|
|
|
2017-01-18 14:38:27 +01:00
|
|
|
|
2017-01-18 Bernhard Rosenkranzer <bero@lindev.ch>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21059
|
|
|
|
|
|
* config/bfin-lex.l: Support processing with flex 2.6.3.
|
|
|
|
|
|
* itbl-lex.l: Likewise.
|
|
|
|
|
|
|
2017-01-18 14:23:10 +01:00
|
|
|
|
2017-01-18 Nathan Sidwell <nathan@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* as.h (gas_assert): Use abort.
|
|
|
|
|
|
(as_assert): Remove.
|
|
|
|
|
|
(signal_init): Declare.
|
|
|
|
|
|
* as.c (main): Call signal_init.
|
|
|
|
|
|
* messages.c: #include <signal.h>
|
|
|
|
|
|
(as_assert): Delete.
|
|
|
|
|
|
(as_abort): Allow NULL FILE.
|
|
|
|
|
|
(signal_crash): New.
|
|
|
|
|
|
(signal_init): Register fatal signal handlers.
|
|
|
|
|
|
* configure.ac: Check for strsignal.
|
|
|
|
|
|
* config.in: Rebuilt.
|
|
|
|
|
|
* configure: Rebuilt.
|
|
|
|
|
|
|
2017-01-18 12:35:29 +01:00
|
|
|
|
2017-01-17 Nick Clifton <nickc@redhat.com>
|
2017-01-16 11:59:23 +01:00
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2017-01-12 17:42:17 +01:00
|
|
|
|
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
|
|
|
|
|
|
(cpu_noarch): Add noavx512_vpopcntdq.
|
|
|
|
|
|
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
|
|
|
|
|
|
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
|
|
|
|
|
|
|
2017-01-12 15:56:13 +01:00
|
|
|
|
2017-01-12 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (temp_ilp): New function. Installs a temporary input
|
|
|
|
|
|
line pointer.
|
|
|
|
|
|
(restore_ilp): New function. Restores the original input line
|
|
|
|
|
|
pointer.
|
|
|
|
|
|
* read.h (temp_ilp): Prototype.
|
|
|
|
|
|
(restore_ilp): Prototype.
|
|
|
|
|
|
* stabs.c (dot_func_p): Use bfd_boolean type.
|
|
|
|
|
|
(generate_asm_file): Use temp_ilp and restore_ilp.
|
|
|
|
|
|
(stabs_generate_asm_lineno): Likewise.
|
|
|
|
|
|
(stabs_generate_asm_endfunc): Likewise.
|
|
|
|
|
|
|
2017-01-11 16:05:53 +01:00
|
|
|
|
2017-01-11 Jeremy Soller <jackpot51@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Add entry for i386-redox.
|
|
|
|
|
|
|
2017-01-10 12:28:36 +01:00
|
|
|
|
2017-01-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2017-01-10 14:43:01 +01:00
|
|
|
|
2017-01-10 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/sleb128-8.d: Adjust test.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp (test_cond): Likewise.
|
|
|
|
|
|
|
2017-01-09 15:50:32 +01:00
|
|
|
|
2017-01-10 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (emit_leb128_expr): Extended unsigned big number for
|
|
|
|
|
|
sleb128.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
|
|
|
|
|
|
* testsuite/gas/all/sleb128.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/sleb128.s: New test source.
|
|
|
|
|
|
|
2016-12-22 03:05:28 +01:00
|
|
|
|
2017-01-09 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
|
|
|
|
|
|
against constants.
|
|
|
|
|
|
(md_apply_fix): Mark relocations against constants as "done."
|
|
|
|
|
|
|
2016-12-21 21:47:13 +01:00
|
|
|
|
2017-01-09 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
|
|
|
|
|
|
against constants.
|
|
|
|
|
|
(md_apply_fix): Mark relocations against constants as "done."
|
|
|
|
|
|
|
2016-12-30 02:29:53 +01:00
|
|
|
|
2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
|
|
|
|
|
|
Removed.
|
|
|
|
|
|
(SDATA_START_SYMBOLS): Likewise.
|
|
|
|
|
|
|
2017-01-09 11:11:50 +01:00
|
|
|
|
2017-01-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
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* po/sv.po: New Swedish translation.
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* configure.ac (ALL_LINGUAS): Add sv.
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* configure: Regenerate.
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2017-01-09 10:22:33 +01:00
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2017-01-09 Andrew Waterman <andrew@sifive.com>
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* config/tc-riscv.c (relaxed_branch_length): Use the long
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sequence when the target is a weak symbol.
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2017-01-04 13:27:10 +01:00
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add rcpc.
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* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.d: This.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.s: This.
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* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
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2017-01-04 12:49:00 +01:00
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2017-01-04 Norm Jacobs <norm.jacobs@oracle.com>
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PR gas/20992
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* configure.tgt: Treat sparcv9 as sparc64.
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2017-01-03 18:42:01 +01:00
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
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extension.
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(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
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enabled and no other ABI is specified.
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2017-01-02 17:20:21 +01:00
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2017-01-03 Dimitar Dimitrov <dimitar@dinux.eu>
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* config/tc-pru.c (md_number_to_chars): Fix parameter to be
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valueT, as declared in tc.h.
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(md_apply_fix): Fix to work on 32-bit hosts.
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2017-01-02 04:36:43 +01:00
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2017-01-02 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2017-01-02 04:25:05 +01:00
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For older changes see ChangeLog-2016
|
2016-01-01 11:44:31 +01:00
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2017-01-02 04:25:05 +01:00
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Copyright (C) 2017 Free Software Foundation, Inc.
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2016-01-01 11:44:31 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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