1994-04-12 00:20:53 +02:00
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;; Machine description for DEC Alpha for GNU C compiler
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2017-01-01 13:07:43 +01:00
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;; Copyright (C) 1992-2017 Free Software Foundation, Inc.
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1994-04-12 00:20:53 +02:00
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;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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2000-10-24 02:06:18 +02:00
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;;
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2003-09-27 06:48:30 +02:00
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;; This file is part of GCC.
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2000-10-24 02:06:18 +02:00
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;;
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2003-09-27 06:48:30 +02:00
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;; GCC is free software; you can redistribute it and/or modify
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1992-10-24 15:33:28 +01:00
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;; it under the terms of the GNU General Public License as published by
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host-hpux.c: Change copyright header to refer to version 3 of the GNU General Public License...
* config/host-hpux.c: Change copyright header to refer to version 3 of the GNU
General Public License and to point readers at the COPYING3 file and the FSF's
license web page.
* config/alpha/predicates.md, config/alpha/vms-ld.c,
config/alpha/linux.h, config/alpha/alpha.opt,
config/alpha/linux-elf.h, config/alpha/vms.h, config/alpha/elf.h,
config/alpha/vms-unwind.h, config/alpha/ev4.md,
config/alpha/ev6.md, config/alpha/alpha.c, config/alpha/vms-cc.c,
config/alpha/alpha.h, config/alpha/sync.md,
config/alpha/openbsd.h, config/alpha/alpha.md,
config/alpha/alpha-modes.def, config/alpha/ev5.md,
config/alpha/alpha-protos.h, config/alpha/freebsd.h,
config/alpha/osf5.h, config/alpha/netbsd.h, config/alpha/vms64.h,
config/alpha/constraints.md, config/alpha/osf.h,
config/alpha/xm-vms.h, config/alpha/unicosmk.h, config/linux.h,
config/frv/predicates.md, config/frv/frv.h, config/frv/linux.h,
config/frv/frv.md, config/frv/frv.opt, config/frv/frv-modes.def,
config/frv/frv-asm.h, config/frv/frv-protos.h,
config/frv/frv-abi.h, config/frv/frv.c, config/s390/tpf.h,
config/s390/s390.c, config/s390/predicates.md, config/s390/s390.h,
config/s390/linux.h, config/s390/tpf.md, config/s390/tpf.opt,
config/s390/2064.md, config/s390/2084.md, config/s390/s390.md,
config/s390/s390.opt, config/s390/s390-modes.def,
config/s390/fixdfdi.h, config/s390/constraints.md,
config/s390/s390-protos.h, config/s390/s390x.h, config/elfos.h,
config/dbxcoff.h, config/m32c/predicates.md, config/m32c/cond.md,
config/m32c/m32c.c, config/m32c/minmax.md, config/m32c/blkmov.md,
config/m32c/m32c-pragma.c, config/m32c/m32c.h,
config/m32c/prologue.md, config/m32c/m32c.abi,
config/m32c/muldiv.md, config/m32c/bitops.md, config/m32c/mov.md,
config/m32c/addsub.md, config/m32c/m32c.md, config/m32c/m32c.opt,
config/m32c/t-m32c, config/m32c/m32c-modes.def,
config/m32c/jump.md, config/m32c/shift.md,
config/m32c/m32c-protos.h, config/libgloss.h,
config/spu/spu-protos.h, config/spu/predicates.md,
config/spu/spu-builtins.h, config/spu/spu.c,
config/spu/spu-builtins.def, config/spu/spu-builtins.md,
config/spu/spu.h, config/spu/spu-elf.h, config/spu/constraints.md,
config/spu/spu.md, config/spu/spu-c.c, config/spu/spu.opt,
config/spu/spu-modes.def, config/spu/t-spu-elf, config/interix.h,
config/sparc/hypersparc.md, config/sparc/predicates.md,
config/sparc/linux.h, config/sparc/sp64-elf.h,
config/sparc/supersparc.md, config/sparc/cypress.md,
config/sparc/openbsd1-64.h, config/sparc/openbsd64.h,
config/sparc/niagara.md, config/sparc/sparc.md,
config/sparc/long-double-switch.opt, config/sparc/ultra3.md,
config/sparc/sparc.opt, config/sparc/sync.md,
config/sparc/sp-elf.h, config/sparc/sparc-protos.h,
config/sparc/ultra1_2.md, config/sparc/biarch64.h,
config/sparc/sparc.c, config/sparc/little-endian.opt,
config/sparc/sysv4-only.h, config/sparc/sparc.h,
config/sparc/linux64.h, config/sparc/freebsd.h,
config/sparc/sol2.h, config/sparc/rtemself.h,
config/sparc/netbsd-elf.h, config/sparc/vxworks.h,
config/sparc/sparc-modes.def, config/sparc/sparclet.md,
config/sparc/sysv4.h, config/vx-common.h, config/netbsd-aout.h,
config/flat.h, config/m32r/m32r.md, config/m32r/predicates.md,
config/m32r/little.h, config/m32r/m32r.c, config/m32r/m32r.opt,
config/m32r/linux.h, config/m32r/constraints.md,
config/m32r/m32r.h, config/m32r/m32r-protos.h, config/vxworks.opt,
config/darwin-c.c, config/darwin.opt, config/i386/i386.h,
config/i386/cygming.h, config/i386/linux.h, config/i386/cygwin.h,
config/i386/i386.md, config/i386/netware-crt0.c,
config/i386/sco5.h, config/i386/mmx.md, config/i386/vx-common.h,
config/i386/kaos-i386.h, config/i386/winnt-stubs.c,
config/i386/netbsd64.h, config/i386/djgpp.h, config/i386/gas.h,
config/i386/sol2.h, config/i386/constraints.md,
config/i386/netware-libgcc.c, config/i386/sysv5.h,
config/i386/predicates.md, config/i386/geode.md,
config/i386/x86-64.h, config/i386/kfreebsd-gnu.h,
config/i386/freebsd64.h, config/i386/vxworksae.h,
config/i386/pentium.md, config/i386/lynx.h, config/i386/i386elf.h,
config/i386/rtemself.h, config/i386/netbsd-elf.h,
config/i386/ppro.md, config/i386/k6.md, config/i386/netware.c,
config/i386/netware.h, config/i386/i386-modes.def,
config/i386/sysv4-cpp.h, config/i386/i386-interix.h,
config/i386/cygwin1.c, config/i386/djgpp.opt, config/i386/uwin.h,
config/i386/unix.h, config/i386/ptx4-i.h, config/i386/xm-djgpp.h,
config/i386/att.h, config/i386/winnt.c, config/i386/beos-elf.h,
config/i386/sol2-10.h, config/i386/darwin64.h, config/i386/sse.md,
config/i386/i386.opt, config/i386/bsd.h, config/i386/cygming.opt,
config/i386/xm-mingw32.h, config/i386/linux64.h,
config/i386/openbsdelf.h, config/i386/xm-cygwin.h,
config/i386/sco5.opt, config/i386/darwin.h, config/i386/mingw32.h,
config/i386/winnt-cxx.c, config/i386/i386-interix3.h,
config/i386/nwld.c, config/i386/nwld.h, config/i386/host-cygwin.c,
config/i386/cygwin2.c, config/i386/i386-protos.h,
config/i386/sync.md, config/i386/openbsd.h,
config/i386/host-mingw32.c, config/i386/i386-aout.h,
config/i386/nto.h, config/i386/biarch64.h,
config/i386/i386-coff.h, config/i386/freebsd.h,
config/i386/driver-i386.c, config/i386/knetbsd-gnu.h,
config/i386/host-i386-darwin.c, config/i386/vxworks.h,
config/i386/crtdll.h, config/i386/i386.c, config/i386/sysv4.h,
config/darwin-protos.h, config/linux.opt, config/sol2.c,
config/sol2.h, config/sh/symbian.c, config/sh/sh-protos.h,
config/sh/linux.h, config/sh/elf.h, config/sh/superh.h,
config/sh/sh4.md, config/sh/coff.h, config/sh/newlib.h,
config/sh/embed-elf.h, config/sh/symbian-pre.h, config/sh/rtems.h,
config/sh/kaos-sh.h, config/sh/sh4a.md, config/sh/constraints.md,
config/sh/sh64.h, config/sh/sh.opt, config/sh/symbian-post.h,
config/sh/sh-c.c, config/sh/predicates.md, config/sh/sh.c,
config/sh/sh.h, config/sh/shmedia.md, config/sh/sh-modes.def,
config/sh/little.h, config/sh/sh1.md, config/sh/sh4-300.md,
config/sh/superh64.h, config/sh/rtemself.h,
config/sh/netbsd-elf.h, config/sh/sh.md, config/sh/vxworks.h,
config/usegas.h, config/svr3.h, config/pdp11/pdp11-protos.h,
config/pdp11/2bsd.h, config/pdp11/pdp11.md, config/pdp11/pdp11.c,
config/pdp11/pdp11.opt, config/pdp11/pdp11-modes.def,
config/pdp11/pdp11.h, config/avr/rtems.h, config/avr/avr-protos.h,
config/avr/predicates.md, config/avr/constraints.md,
config/avr/avr.md, config/avr/avr.c, config/avr/avr.opt,
config/avr/avr.h, config/sol2-protos.h, config/dbxelf.h,
config/lynx.opt, config/crx/crx.h, config/crx/crx-protos.h,
config/crx/crx.md, config/crx/crx.c, config/crx/crx.opt,
config/c4x/c4x-c.c, config/c4x/c4x.c, config/c4x/c4x.opt,
config/c4x/c4x-modes.def, config/c4x/rtems.h,
config/c4x/predicates.md, config/c4x/c4x.h,
config/c4x/c4x-protos.h, config/c4x/c4x.md, config/kfreebsd-gnu.h,
config/xtensa/predicates.md, config/xtensa/xtensa.c,
config/xtensa/linux.h, config/xtensa/xtensa.h,
config/xtensa/elf.h, config/xtensa/xtensa.md,
config/xtensa/xtensa.opt, config/xtensa/constraints.md,
config/xtensa/xtensa-protos.h, config/dbx.h,
config/stormy16/predicates.md, config/stormy16/stormy16.md,
config/stormy16/stormy16.c, config/stormy16/stormy16.opt,
config/stormy16/stormy16.h, config/stormy16/stormy16-protos.h,
config/host-solaris.c, config/fr30/fr30.h,
config/fr30/predicates.md, config/fr30/fr30-protos.h,
config/fr30/fr30.md, config/fr30/fr30.c, config/fr30/fr30.opt,
config/vxworksae.h, config/sol2-c.c, config/lynx.h,
config/m68hc11/m68hc11-protos.h, config/m68hc11/predicates.md,
config/m68hc11/m68hc11.md, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.opt, config/m68hc11/m68hc11.h,
config/m68hc11/m68hc12.h, config/openbsd-oldgas.h,
config/host-linux.c, config/interix3.h, config/cris/cris.c,
config/cris/predicates.md, config/cris/linux.h,
config/cris/cris.h, config/cris/aout.h, config/cris/cris.md,
config/cris/linux.opt, config/cris/cris.opt, config/cris/elf.opt,
config/cris/aout.opt, config/cris/cris-protos.h,
config/vxworks-dummy.h, config/netbsd.h, config/netbsd-elf.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/iq2000/iq2000-protos.h, config/iq2000/iq2000.md,
config/iq2000/iq2000.c, config/iq2000/iq2000.opt,
config/host-darwin.c, config/mt/mt.md, config/mt/mt.c,
config/mt/mt.opt, config/mt/t-mt, config/mt/mt.h,
config/mt/mt-protos.h, config/svr4.h, config/host-darwin.h,
config/chorus.h, config/mn10300/mn10300.c,
config/mn10300/mn10300.opt, config/mn10300/predicates.md,
config/mn10300/mn10300.h, config/mn10300/linux.h,
config/mn10300/constraints.md, config/mn10300/mn10300-protos.h,
config/mn10300/mn10300.md, config/ia64/predicates.md,
config/ia64/itanium1.md, config/ia64/unwind-ia64.h,
config/ia64/ia64-c.c, config/ia64/sync.md, config/ia64/ia64.c,
config/ia64/itanium2.md, config/ia64/ia64.h, config/ia64/vect.md,
config/ia64/freebsd.h, config/ia64/ia64.md,
config/ia64/ia64-modes.def, config/ia64/constraints.md,
config/ia64/hpux.h, config/ia64/ia64-protos.h, config/windiss.h,
config/gofast.h, config/rtems.h, config/sol2-10.h,
config/m68k/predicates.md, config/m68k/m68k.md,
config/m68k/linux.h, config/m68k/m68k-modes.def,
config/m68k/print-sysroot-suffix.sh, config/m68k/m68k-protos.h,
config/m68k/coff.h, config/m68k/m68k-none.h, config/m68k/ieee.opt,
config/m68k/openbsd.h, config/m68k/m68k-aout.h,
config/m68k/m68k.opt, config/m68k/m68020-elf.h,
config/m68k/m68kelf.h, config/m68k/m68k-devices.def,
config/m68k/uclinux-oldabi.h, config/m68k/m68k.c,
config/m68k/constraints.md, config/m68k/rtemself.h,
config/m68k/netbsd-elf.h, config/m68k/m68k.h,
config/m68k/uclinux.h, config/rs6000/power4.md,
config/rs6000/host-darwin.c, config/rs6000/6xx.md,
config/rs6000/linux.h, config/rs6000/eabi.h,
config/rs6000/aix41.opt, config/rs6000/xcoff.h,
config/rs6000/secureplt.h, config/rs6000/linuxspe.h,
config/rs6000/eabialtivec.h, config/rs6000/8540.md,
config/rs6000/darwin8.h, config/rs6000/kaos-ppc.h,
config/rs6000/windiss.h, config/rs6000/603.md,
config/rs6000/aix41.h, config/rs6000/cell.md,
config/rs6000/mpc.md, config/rs6000/aix43.h, config/rs6000/beos.h,
config/rs6000/gnu.h, config/rs6000/rtems.h, config/rs6000/aix.opt,
config/rs6000/darwin.md, config/rs6000/darwin64.h,
config/rs6000/default64.h, config/rs6000/7xx.md,
config/rs6000/darwin.opt, config/rs6000/spe.md,
config/rs6000/rs6000.opt, config/rs6000/rs6000-c.c,
config/rs6000/rios2.md, config/rs6000/linuxaltivec.h,
config/rs6000/7450.md, config/rs6000/linux64.h,
config/rs6000/constraints.md, config/rs6000/440.md,
config/rs6000/darwin.h, config/rs6000/host-ppc64-darwin.c,
config/rs6000/rs6000.c, config/rs6000/aix52.h,
config/rs6000/rs6000.h, config/rs6000/power6.md,
config/rs6000/predicates.md, config/rs6000/altivec.md,
config/rs6000/aix64.opt, config/rs6000/rios1.md,
config/rs6000/rs6000-modes.def, config/rs6000/rs64.md,
config/rs6000/eabisim.h, config/rs6000/sysv4le.h,
config/rs6000/darwin7.h, config/rs6000/dfp.md,
config/rs6000/linux64.opt, config/rs6000/sync.md,
config/rs6000/vxworksae.h, config/rs6000/power5.md,
config/rs6000/lynx.h, config/rs6000/biarch64.h,
config/rs6000/rs6000.md, config/rs6000/sysv4.opt,
config/rs6000/eabispe.h, config/rs6000/e500.h,
config/rs6000/freebsd.h, config/rs6000/rs6000-protos.h,
config/rs6000/netbsd.h, config/rs6000/e500-double.h,
config/rs6000/aix.h, config/rs6000/vxworks.h,
config/rs6000/40x.md, config/rs6000/aix51.h,
config/rs6000/sysv4.h, config/arc/arc-protos.h, config/arc/arc.md,
config/arc/arc.c, config/arc/arc.opt, config/arc/arc-modes.def,
config/arc/arc.h, config/mcore/mcore-elf.h,
config/mcore/mcore-protos.h, config/mcore/predicates.md,
config/mcore/mcore.md, config/mcore/mcore.c,
config/mcore/mcore.opt, config/mcore/mcore.h,
config/mcore/mcore-pe.h, config/darwin.c, config/freebsd-nthr.h,
config/score/predicates.md, config/score/score-version.h,
config/score/score-protos.h, config/score/misc.md,
config/score/elf.h, config/score/score.c, config/score/mac.md,
config/score/score7.md, config/score/score.h,
config/score/score-conv.h, config/score/score-mdaux.c,
config/score/score.md, config/score/score.opt,
config/score/score-modes.def, config/score/score-mdaux.h,
config/score/mul-div.S, config/arm/uclinux-elf.h,
config/arm/semi.h, config/arm/ecos-elf.h, config/arm/arm1020e.md,
config/arm/symbian.h, config/arm/linux-elf.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/elf.h, config/arm/aout.h, config/arm/arm.c,
config/arm/thumb2.md, config/arm/vec-common.md, config/arm/coff.h,
config/arm/strongarm-pe.h, config/arm/arm.h,
config/arm/cortex-a8-neon.md, config/arm/semiaof.h,
config/arm/cortex-a8.md, config/arm/uclinux-eabi.h,
config/arm/arm-modes.def, config/arm/linux-eabi.h,
config/arm/rtems-elf.h, config/arm/neon-schedgen.ml,
config/arm/arm-cores.def, config/arm/arm-protos.h,
config/arm/vfp.md, config/arm/aof.h, config/arm/linux-gas.h,
config/arm/wince-pe.h, config/arm/neon.md,
config/arm/constraints.md, config/arm/neon.ml,
config/arm/xscale-elf.h, config/arm/strongarm-coff.h,
config/arm/arm.opt, config/arm/arm926ejs.md,
config/arm/predicates.md, config/arm/iwmmxt.md,
config/arm/arm_neon.h, config/arm/unknown-elf.h,
config/arm/kaos-arm.h, config/arm/bpabi.h, config/arm/pe.opt,
config/arm/neon-testgen.ml, config/arm/arm.md,
config/arm/xscale-coff.h, config/arm/pe.c,
config/arm/arm-generic.md, config/arm/pe.h,
config/arm/kaos-strongarm.h, config/arm/freebsd.h,
config/arm/neon-docgen.ml, config/arm/netbsd.h, config/arm/fpa.md,
config/arm/strongarm-elf.h, config/arm/cirrus.md,
config/arm/netbsd-elf.h, config/arm/vxworks.h,
config/arm/neon-gen.ml, config/kaos.h, config/darwin-driver.c,
config/pa/predicates.md, config/pa/pa64-hpux.h,
config/pa/pa-hpux.opt, config/pa/som.h, config/pa/pa-hpux1010.opt,
config/pa/pa-hpux1111.opt, config/pa/pa-pro-end.h,
config/pa/elf.h, config/pa/fptr.c, config/pa/pa64-linux.h,
config/pa/pa.md, config/pa/pa.opt, config/pa/pa-hpux.h,
config/pa/pa-hpux10.h, config/pa/pa-hpux11.h,
config/pa/pa-hpux1010.h, config/pa/pa-protos.h,
config/pa/pa-osf.h, config/pa/pa-hpux1111.h, config/pa/pa-64.h,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa-linux.h,
config/pa/pa.h, config/pa/pa32-linux.h, config/pa/pa64-hpux.opt,
config/pa/pa64-regs.h, config/pa/pa-modes.def,
config/pa/constraints.md, config/darwin9.h, config/mips/4100.md,
config/mips/linux.h, config/mips/elfoabi.h, config/mips/elf.h,
config/mips/sdb.h, config/mips/windiss.h, config/mips/rtems.h,
config/mips/3000.md, config/mips/iris5.h, config/mips/5000.md,
config/mips/7000.md, config/mips/9000.md, config/mips/4600.md,
config/mips/linux64.h, config/mips/elforion.h,
config/mips/constraints.md, config/mips/generic.md,
config/mips/predicates.md, config/mips/4300.md,
config/mips/mips-ps-3d.md, config/mips/iris.h, config/mips/24k.md,
config/mips/mips.md, config/mips/mips.opt, config/mips/4k.md,
config/mips/5k.md, config/mips/vr4120-div.S,
config/mips/openbsd.h, config/mips/iris6.h, config/mips/4000.md,
config/mips/mips-protos.h, config/mips/6000.md,
config/mips/mips.c, config/mips/mips.h, config/mips/r3900.h,
config/mips/74k.md, config/mips/netbsd.h, config/mips/vxworks.h,
config/mips/mips-modes.def, config/mips/vr.h,
config/soft-fp/t-softfp, config/openbsd.h, config/ptx4.h,
config/freebsd-spec.h, config/vax/vax.c, config/vax/openbsd.h,
config/vax/vax.h, config/vax/elf.h, config/vax/vax.md,
config/vax/bsd.h, config/vax/vax.opt, config/vax/vax-modes.def,
config/vax/openbsd1.h, config/vax/netbsd.h,
config/vax/vax-protos.h, config/vax/netbsd-elf.h,
config/vax/vaxv.h, config/vax/ultrix.h, config/freebsd.h,
config/h8300/rtems.h, config/h8300/predicates.md,
config/h8300/h8300.c, config/h8300/h8300.h, config/h8300/elf.h,
config/h8300/h8300.md, config/h8300/h8300.opt,
config/h8300/coff.h, config/h8300/h8300-protos.h,
config/v850/v850.md, config/v850/predicates.md,
config/v850/v850-c.c, config/v850/v850.c, config/v850/v850.opt,
config/v850/v850.h, config/v850/v850-protos.h, config/vxworks.c,
config/knetbsd-gnu.h, config/sol2-6.h, config/vxworks.h,
config/mmix/mmix.h, config/mmix/predicates.md,
config/mmix/mmix-protos.h, config/mmix/mmix.md,
config/mmix/mmix.c, config/mmix/mmix.opt,
config/mmix/mmix-modes.def, config/bfin/bfin.opt,
config/bfin/rtems.h, config/bfin/bfin-modes.def,
config/bfin/predicates.md, config/bfin/bfin-protos.h,
config/bfin/bfin.c, config/bfin/bfin.h, config/bfin/bfin.md: Likewise.
From-SVN: r127157
2007-08-02 12:49:31 +02:00
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;; the Free Software Foundation; either version 3, or (at your option)
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1992-10-24 15:33:28 +01:00
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;; any later version.
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2000-10-24 02:06:18 +02:00
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;;
|
2003-09-27 06:48:30 +02:00
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;; GCC is distributed in the hope that it will be useful,
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1992-10-24 15:33:28 +01:00
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|
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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;; GNU General Public License for more details.
|
2000-10-24 02:06:18 +02:00
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;;
|
1992-10-24 15:33:28 +01:00
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;; You should have received a copy of the GNU General Public License
|
host-hpux.c: Change copyright header to refer to version 3 of the GNU General Public License...
* config/host-hpux.c: Change copyright header to refer to version 3 of the GNU
General Public License and to point readers at the COPYING3 file and the FSF's
license web page.
* config/alpha/predicates.md, config/alpha/vms-ld.c,
config/alpha/linux.h, config/alpha/alpha.opt,
config/alpha/linux-elf.h, config/alpha/vms.h, config/alpha/elf.h,
config/alpha/vms-unwind.h, config/alpha/ev4.md,
config/alpha/ev6.md, config/alpha/alpha.c, config/alpha/vms-cc.c,
config/alpha/alpha.h, config/alpha/sync.md,
config/alpha/openbsd.h, config/alpha/alpha.md,
config/alpha/alpha-modes.def, config/alpha/ev5.md,
config/alpha/alpha-protos.h, config/alpha/freebsd.h,
config/alpha/osf5.h, config/alpha/netbsd.h, config/alpha/vms64.h,
config/alpha/constraints.md, config/alpha/osf.h,
config/alpha/xm-vms.h, config/alpha/unicosmk.h, config/linux.h,
config/frv/predicates.md, config/frv/frv.h, config/frv/linux.h,
config/frv/frv.md, config/frv/frv.opt, config/frv/frv-modes.def,
config/frv/frv-asm.h, config/frv/frv-protos.h,
config/frv/frv-abi.h, config/frv/frv.c, config/s390/tpf.h,
config/s390/s390.c, config/s390/predicates.md, config/s390/s390.h,
config/s390/linux.h, config/s390/tpf.md, config/s390/tpf.opt,
config/s390/2064.md, config/s390/2084.md, config/s390/s390.md,
config/s390/s390.opt, config/s390/s390-modes.def,
config/s390/fixdfdi.h, config/s390/constraints.md,
config/s390/s390-protos.h, config/s390/s390x.h, config/elfos.h,
config/dbxcoff.h, config/m32c/predicates.md, config/m32c/cond.md,
config/m32c/m32c.c, config/m32c/minmax.md, config/m32c/blkmov.md,
config/m32c/m32c-pragma.c, config/m32c/m32c.h,
config/m32c/prologue.md, config/m32c/m32c.abi,
config/m32c/muldiv.md, config/m32c/bitops.md, config/m32c/mov.md,
config/m32c/addsub.md, config/m32c/m32c.md, config/m32c/m32c.opt,
config/m32c/t-m32c, config/m32c/m32c-modes.def,
config/m32c/jump.md, config/m32c/shift.md,
config/m32c/m32c-protos.h, config/libgloss.h,
config/spu/spu-protos.h, config/spu/predicates.md,
config/spu/spu-builtins.h, config/spu/spu.c,
config/spu/spu-builtins.def, config/spu/spu-builtins.md,
config/spu/spu.h, config/spu/spu-elf.h, config/spu/constraints.md,
config/spu/spu.md, config/spu/spu-c.c, config/spu/spu.opt,
config/spu/spu-modes.def, config/spu/t-spu-elf, config/interix.h,
config/sparc/hypersparc.md, config/sparc/predicates.md,
config/sparc/linux.h, config/sparc/sp64-elf.h,
config/sparc/supersparc.md, config/sparc/cypress.md,
config/sparc/openbsd1-64.h, config/sparc/openbsd64.h,
config/sparc/niagara.md, config/sparc/sparc.md,
config/sparc/long-double-switch.opt, config/sparc/ultra3.md,
config/sparc/sparc.opt, config/sparc/sync.md,
config/sparc/sp-elf.h, config/sparc/sparc-protos.h,
config/sparc/ultra1_2.md, config/sparc/biarch64.h,
config/sparc/sparc.c, config/sparc/little-endian.opt,
config/sparc/sysv4-only.h, config/sparc/sparc.h,
config/sparc/linux64.h, config/sparc/freebsd.h,
config/sparc/sol2.h, config/sparc/rtemself.h,
config/sparc/netbsd-elf.h, config/sparc/vxworks.h,
config/sparc/sparc-modes.def, config/sparc/sparclet.md,
config/sparc/sysv4.h, config/vx-common.h, config/netbsd-aout.h,
config/flat.h, config/m32r/m32r.md, config/m32r/predicates.md,
config/m32r/little.h, config/m32r/m32r.c, config/m32r/m32r.opt,
config/m32r/linux.h, config/m32r/constraints.md,
config/m32r/m32r.h, config/m32r/m32r-protos.h, config/vxworks.opt,
config/darwin-c.c, config/darwin.opt, config/i386/i386.h,
config/i386/cygming.h, config/i386/linux.h, config/i386/cygwin.h,
config/i386/i386.md, config/i386/netware-crt0.c,
config/i386/sco5.h, config/i386/mmx.md, config/i386/vx-common.h,
config/i386/kaos-i386.h, config/i386/winnt-stubs.c,
config/i386/netbsd64.h, config/i386/djgpp.h, config/i386/gas.h,
config/i386/sol2.h, config/i386/constraints.md,
config/i386/netware-libgcc.c, config/i386/sysv5.h,
config/i386/predicates.md, config/i386/geode.md,
config/i386/x86-64.h, config/i386/kfreebsd-gnu.h,
config/i386/freebsd64.h, config/i386/vxworksae.h,
config/i386/pentium.md, config/i386/lynx.h, config/i386/i386elf.h,
config/i386/rtemself.h, config/i386/netbsd-elf.h,
config/i386/ppro.md, config/i386/k6.md, config/i386/netware.c,
config/i386/netware.h, config/i386/i386-modes.def,
config/i386/sysv4-cpp.h, config/i386/i386-interix.h,
config/i386/cygwin1.c, config/i386/djgpp.opt, config/i386/uwin.h,
config/i386/unix.h, config/i386/ptx4-i.h, config/i386/xm-djgpp.h,
config/i386/att.h, config/i386/winnt.c, config/i386/beos-elf.h,
config/i386/sol2-10.h, config/i386/darwin64.h, config/i386/sse.md,
config/i386/i386.opt, config/i386/bsd.h, config/i386/cygming.opt,
config/i386/xm-mingw32.h, config/i386/linux64.h,
config/i386/openbsdelf.h, config/i386/xm-cygwin.h,
config/i386/sco5.opt, config/i386/darwin.h, config/i386/mingw32.h,
config/i386/winnt-cxx.c, config/i386/i386-interix3.h,
config/i386/nwld.c, config/i386/nwld.h, config/i386/host-cygwin.c,
config/i386/cygwin2.c, config/i386/i386-protos.h,
config/i386/sync.md, config/i386/openbsd.h,
config/i386/host-mingw32.c, config/i386/i386-aout.h,
config/i386/nto.h, config/i386/biarch64.h,
config/i386/i386-coff.h, config/i386/freebsd.h,
config/i386/driver-i386.c, config/i386/knetbsd-gnu.h,
config/i386/host-i386-darwin.c, config/i386/vxworks.h,
config/i386/crtdll.h, config/i386/i386.c, config/i386/sysv4.h,
config/darwin-protos.h, config/linux.opt, config/sol2.c,
config/sol2.h, config/sh/symbian.c, config/sh/sh-protos.h,
config/sh/linux.h, config/sh/elf.h, config/sh/superh.h,
config/sh/sh4.md, config/sh/coff.h, config/sh/newlib.h,
config/sh/embed-elf.h, config/sh/symbian-pre.h, config/sh/rtems.h,
config/sh/kaos-sh.h, config/sh/sh4a.md, config/sh/constraints.md,
config/sh/sh64.h, config/sh/sh.opt, config/sh/symbian-post.h,
config/sh/sh-c.c, config/sh/predicates.md, config/sh/sh.c,
config/sh/sh.h, config/sh/shmedia.md, config/sh/sh-modes.def,
config/sh/little.h, config/sh/sh1.md, config/sh/sh4-300.md,
config/sh/superh64.h, config/sh/rtemself.h,
config/sh/netbsd-elf.h, config/sh/sh.md, config/sh/vxworks.h,
config/usegas.h, config/svr3.h, config/pdp11/pdp11-protos.h,
config/pdp11/2bsd.h, config/pdp11/pdp11.md, config/pdp11/pdp11.c,
config/pdp11/pdp11.opt, config/pdp11/pdp11-modes.def,
config/pdp11/pdp11.h, config/avr/rtems.h, config/avr/avr-protos.h,
config/avr/predicates.md, config/avr/constraints.md,
config/avr/avr.md, config/avr/avr.c, config/avr/avr.opt,
config/avr/avr.h, config/sol2-protos.h, config/dbxelf.h,
config/lynx.opt, config/crx/crx.h, config/crx/crx-protos.h,
config/crx/crx.md, config/crx/crx.c, config/crx/crx.opt,
config/c4x/c4x-c.c, config/c4x/c4x.c, config/c4x/c4x.opt,
config/c4x/c4x-modes.def, config/c4x/rtems.h,
config/c4x/predicates.md, config/c4x/c4x.h,
config/c4x/c4x-protos.h, config/c4x/c4x.md, config/kfreebsd-gnu.h,
config/xtensa/predicates.md, config/xtensa/xtensa.c,
config/xtensa/linux.h, config/xtensa/xtensa.h,
config/xtensa/elf.h, config/xtensa/xtensa.md,
config/xtensa/xtensa.opt, config/xtensa/constraints.md,
config/xtensa/xtensa-protos.h, config/dbx.h,
config/stormy16/predicates.md, config/stormy16/stormy16.md,
config/stormy16/stormy16.c, config/stormy16/stormy16.opt,
config/stormy16/stormy16.h, config/stormy16/stormy16-protos.h,
config/host-solaris.c, config/fr30/fr30.h,
config/fr30/predicates.md, config/fr30/fr30-protos.h,
config/fr30/fr30.md, config/fr30/fr30.c, config/fr30/fr30.opt,
config/vxworksae.h, config/sol2-c.c, config/lynx.h,
config/m68hc11/m68hc11-protos.h, config/m68hc11/predicates.md,
config/m68hc11/m68hc11.md, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.opt, config/m68hc11/m68hc11.h,
config/m68hc11/m68hc12.h, config/openbsd-oldgas.h,
config/host-linux.c, config/interix3.h, config/cris/cris.c,
config/cris/predicates.md, config/cris/linux.h,
config/cris/cris.h, config/cris/aout.h, config/cris/cris.md,
config/cris/linux.opt, config/cris/cris.opt, config/cris/elf.opt,
config/cris/aout.opt, config/cris/cris-protos.h,
config/vxworks-dummy.h, config/netbsd.h, config/netbsd-elf.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/iq2000/iq2000-protos.h, config/iq2000/iq2000.md,
config/iq2000/iq2000.c, config/iq2000/iq2000.opt,
config/host-darwin.c, config/mt/mt.md, config/mt/mt.c,
config/mt/mt.opt, config/mt/t-mt, config/mt/mt.h,
config/mt/mt-protos.h, config/svr4.h, config/host-darwin.h,
config/chorus.h, config/mn10300/mn10300.c,
config/mn10300/mn10300.opt, config/mn10300/predicates.md,
config/mn10300/mn10300.h, config/mn10300/linux.h,
config/mn10300/constraints.md, config/mn10300/mn10300-protos.h,
config/mn10300/mn10300.md, config/ia64/predicates.md,
config/ia64/itanium1.md, config/ia64/unwind-ia64.h,
config/ia64/ia64-c.c, config/ia64/sync.md, config/ia64/ia64.c,
config/ia64/itanium2.md, config/ia64/ia64.h, config/ia64/vect.md,
config/ia64/freebsd.h, config/ia64/ia64.md,
config/ia64/ia64-modes.def, config/ia64/constraints.md,
config/ia64/hpux.h, config/ia64/ia64-protos.h, config/windiss.h,
config/gofast.h, config/rtems.h, config/sol2-10.h,
config/m68k/predicates.md, config/m68k/m68k.md,
config/m68k/linux.h, config/m68k/m68k-modes.def,
config/m68k/print-sysroot-suffix.sh, config/m68k/m68k-protos.h,
config/m68k/coff.h, config/m68k/m68k-none.h, config/m68k/ieee.opt,
config/m68k/openbsd.h, config/m68k/m68k-aout.h,
config/m68k/m68k.opt, config/m68k/m68020-elf.h,
config/m68k/m68kelf.h, config/m68k/m68k-devices.def,
config/m68k/uclinux-oldabi.h, config/m68k/m68k.c,
config/m68k/constraints.md, config/m68k/rtemself.h,
config/m68k/netbsd-elf.h, config/m68k/m68k.h,
config/m68k/uclinux.h, config/rs6000/power4.md,
config/rs6000/host-darwin.c, config/rs6000/6xx.md,
config/rs6000/linux.h, config/rs6000/eabi.h,
config/rs6000/aix41.opt, config/rs6000/xcoff.h,
config/rs6000/secureplt.h, config/rs6000/linuxspe.h,
config/rs6000/eabialtivec.h, config/rs6000/8540.md,
config/rs6000/darwin8.h, config/rs6000/kaos-ppc.h,
config/rs6000/windiss.h, config/rs6000/603.md,
config/rs6000/aix41.h, config/rs6000/cell.md,
config/rs6000/mpc.md, config/rs6000/aix43.h, config/rs6000/beos.h,
config/rs6000/gnu.h, config/rs6000/rtems.h, config/rs6000/aix.opt,
config/rs6000/darwin.md, config/rs6000/darwin64.h,
config/rs6000/default64.h, config/rs6000/7xx.md,
config/rs6000/darwin.opt, config/rs6000/spe.md,
config/rs6000/rs6000.opt, config/rs6000/rs6000-c.c,
config/rs6000/rios2.md, config/rs6000/linuxaltivec.h,
config/rs6000/7450.md, config/rs6000/linux64.h,
config/rs6000/constraints.md, config/rs6000/440.md,
config/rs6000/darwin.h, config/rs6000/host-ppc64-darwin.c,
config/rs6000/rs6000.c, config/rs6000/aix52.h,
config/rs6000/rs6000.h, config/rs6000/power6.md,
config/rs6000/predicates.md, config/rs6000/altivec.md,
config/rs6000/aix64.opt, config/rs6000/rios1.md,
config/rs6000/rs6000-modes.def, config/rs6000/rs64.md,
config/rs6000/eabisim.h, config/rs6000/sysv4le.h,
config/rs6000/darwin7.h, config/rs6000/dfp.md,
config/rs6000/linux64.opt, config/rs6000/sync.md,
config/rs6000/vxworksae.h, config/rs6000/power5.md,
config/rs6000/lynx.h, config/rs6000/biarch64.h,
config/rs6000/rs6000.md, config/rs6000/sysv4.opt,
config/rs6000/eabispe.h, config/rs6000/e500.h,
config/rs6000/freebsd.h, config/rs6000/rs6000-protos.h,
config/rs6000/netbsd.h, config/rs6000/e500-double.h,
config/rs6000/aix.h, config/rs6000/vxworks.h,
config/rs6000/40x.md, config/rs6000/aix51.h,
config/rs6000/sysv4.h, config/arc/arc-protos.h, config/arc/arc.md,
config/arc/arc.c, config/arc/arc.opt, config/arc/arc-modes.def,
config/arc/arc.h, config/mcore/mcore-elf.h,
config/mcore/mcore-protos.h, config/mcore/predicates.md,
config/mcore/mcore.md, config/mcore/mcore.c,
config/mcore/mcore.opt, config/mcore/mcore.h,
config/mcore/mcore-pe.h, config/darwin.c, config/freebsd-nthr.h,
config/score/predicates.md, config/score/score-version.h,
config/score/score-protos.h, config/score/misc.md,
config/score/elf.h, config/score/score.c, config/score/mac.md,
config/score/score7.md, config/score/score.h,
config/score/score-conv.h, config/score/score-mdaux.c,
config/score/score.md, config/score/score.opt,
config/score/score-modes.def, config/score/score-mdaux.h,
config/score/mul-div.S, config/arm/uclinux-elf.h,
config/arm/semi.h, config/arm/ecos-elf.h, config/arm/arm1020e.md,
config/arm/symbian.h, config/arm/linux-elf.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/elf.h, config/arm/aout.h, config/arm/arm.c,
config/arm/thumb2.md, config/arm/vec-common.md, config/arm/coff.h,
config/arm/strongarm-pe.h, config/arm/arm.h,
config/arm/cortex-a8-neon.md, config/arm/semiaof.h,
config/arm/cortex-a8.md, config/arm/uclinux-eabi.h,
config/arm/arm-modes.def, config/arm/linux-eabi.h,
config/arm/rtems-elf.h, config/arm/neon-schedgen.ml,
config/arm/arm-cores.def, config/arm/arm-protos.h,
config/arm/vfp.md, config/arm/aof.h, config/arm/linux-gas.h,
config/arm/wince-pe.h, config/arm/neon.md,
config/arm/constraints.md, config/arm/neon.ml,
config/arm/xscale-elf.h, config/arm/strongarm-coff.h,
config/arm/arm.opt, config/arm/arm926ejs.md,
config/arm/predicates.md, config/arm/iwmmxt.md,
config/arm/arm_neon.h, config/arm/unknown-elf.h,
config/arm/kaos-arm.h, config/arm/bpabi.h, config/arm/pe.opt,
config/arm/neon-testgen.ml, config/arm/arm.md,
config/arm/xscale-coff.h, config/arm/pe.c,
config/arm/arm-generic.md, config/arm/pe.h,
config/arm/kaos-strongarm.h, config/arm/freebsd.h,
config/arm/neon-docgen.ml, config/arm/netbsd.h, config/arm/fpa.md,
config/arm/strongarm-elf.h, config/arm/cirrus.md,
config/arm/netbsd-elf.h, config/arm/vxworks.h,
config/arm/neon-gen.ml, config/kaos.h, config/darwin-driver.c,
config/pa/predicates.md, config/pa/pa64-hpux.h,
config/pa/pa-hpux.opt, config/pa/som.h, config/pa/pa-hpux1010.opt,
config/pa/pa-hpux1111.opt, config/pa/pa-pro-end.h,
config/pa/elf.h, config/pa/fptr.c, config/pa/pa64-linux.h,
config/pa/pa.md, config/pa/pa.opt, config/pa/pa-hpux.h,
config/pa/pa-hpux10.h, config/pa/pa-hpux11.h,
config/pa/pa-hpux1010.h, config/pa/pa-protos.h,
config/pa/pa-osf.h, config/pa/pa-hpux1111.h, config/pa/pa-64.h,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa-linux.h,
config/pa/pa.h, config/pa/pa32-linux.h, config/pa/pa64-hpux.opt,
config/pa/pa64-regs.h, config/pa/pa-modes.def,
config/pa/constraints.md, config/darwin9.h, config/mips/4100.md,
config/mips/linux.h, config/mips/elfoabi.h, config/mips/elf.h,
config/mips/sdb.h, config/mips/windiss.h, config/mips/rtems.h,
config/mips/3000.md, config/mips/iris5.h, config/mips/5000.md,
config/mips/7000.md, config/mips/9000.md, config/mips/4600.md,
config/mips/linux64.h, config/mips/elforion.h,
config/mips/constraints.md, config/mips/generic.md,
config/mips/predicates.md, config/mips/4300.md,
config/mips/mips-ps-3d.md, config/mips/iris.h, config/mips/24k.md,
config/mips/mips.md, config/mips/mips.opt, config/mips/4k.md,
config/mips/5k.md, config/mips/vr4120-div.S,
config/mips/openbsd.h, config/mips/iris6.h, config/mips/4000.md,
config/mips/mips-protos.h, config/mips/6000.md,
config/mips/mips.c, config/mips/mips.h, config/mips/r3900.h,
config/mips/74k.md, config/mips/netbsd.h, config/mips/vxworks.h,
config/mips/mips-modes.def, config/mips/vr.h,
config/soft-fp/t-softfp, config/openbsd.h, config/ptx4.h,
config/freebsd-spec.h, config/vax/vax.c, config/vax/openbsd.h,
config/vax/vax.h, config/vax/elf.h, config/vax/vax.md,
config/vax/bsd.h, config/vax/vax.opt, config/vax/vax-modes.def,
config/vax/openbsd1.h, config/vax/netbsd.h,
config/vax/vax-protos.h, config/vax/netbsd-elf.h,
config/vax/vaxv.h, config/vax/ultrix.h, config/freebsd.h,
config/h8300/rtems.h, config/h8300/predicates.md,
config/h8300/h8300.c, config/h8300/h8300.h, config/h8300/elf.h,
config/h8300/h8300.md, config/h8300/h8300.opt,
config/h8300/coff.h, config/h8300/h8300-protos.h,
config/v850/v850.md, config/v850/predicates.md,
config/v850/v850-c.c, config/v850/v850.c, config/v850/v850.opt,
config/v850/v850.h, config/v850/v850-protos.h, config/vxworks.c,
config/knetbsd-gnu.h, config/sol2-6.h, config/vxworks.h,
config/mmix/mmix.h, config/mmix/predicates.md,
config/mmix/mmix-protos.h, config/mmix/mmix.md,
config/mmix/mmix.c, config/mmix/mmix.opt,
config/mmix/mmix-modes.def, config/bfin/bfin.opt,
config/bfin/rtems.h, config/bfin/bfin-modes.def,
config/bfin/predicates.md, config/bfin/bfin-protos.h,
config/bfin/bfin.c, config/bfin/bfin.h, config/bfin/bfin.md: Likewise.
From-SVN: r127157
2007-08-02 12:49:31 +02:00
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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1992-10-24 15:33:28 +01:00
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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1998-04-04 15:54:32 +02:00
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;; Uses of UNSPEC in this file:
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2001-07-15 08:25:01 +02:00
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2011-03-21 21:50:35 +01:00
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(define_c_enum "unspec" [
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2013-05-23 20:32:12 +02:00
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UNSPEC_XFLT_COMPARE
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2011-03-21 21:50:35 +01:00
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UNSPEC_ARG_HOME
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UNSPEC_LDGP1
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UNSPEC_INSXH
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UNSPEC_MSKXH
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UNSPEC_CVTQL
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UNSPEC_CVTLQ
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UNSPEC_LDGP2
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UNSPEC_LITERAL
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UNSPEC_LITUSE
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UNSPEC_SIBCALL
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UNSPEC_SYMBOL
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configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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2011-03-21 21:50:35 +01:00
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;; TLS Support
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UNSPEC_TLSGD_CALL
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UNSPEC_TLSLDM_CALL
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UNSPEC_TLSGD
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UNSPEC_TLSLDM
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UNSPEC_DTPREL
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UNSPEC_TPREL
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UNSPEC_TP
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alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
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2011-03-21 21:50:35 +01:00
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;; Builtins
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UNSPEC_CMPBGE
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UNSPEC_ZAP
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UNSPEC_AMASK
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UNSPEC_IMPLVER
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UNSPEC_PERR
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UNSPEC_COPYSIGN
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alpha.c (emit_insxl, [...]): New functions.
* config/alpha/alpha.c (emit_insxl, alpha_expand_compare_and_swap_12,
alpha_split_compare_and_swap_12, alpha_expand_lock_test_and_set_12,
alpha_split_lock_test_and_set_12): New functions.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_MB, UNSPEC_ATOMIC,
UNSPEC_CMPXCHG, UNSPEC_XCHG): Rename from UNSPECV_FOO.
* config/alpha/sync.md (I12MODE): New.
(memory_barrier, mb_internal): Use unspec instead of unspec_volatile.
(sync_<fetchop_name><I48MODE>): Likewise.
(sync_nand<I48MODE>): Likewise.
(sync_old_<fetchop_name><I48MODE>): Likewise.
(sync_new_<fetchop_name><I48MODE>): Likewise.
(sync_old_nand<I48MODE>, sync_new_nand<I48MODE>): Likewise.
(sync_compare_and_swap<I48MODE>): Likewise.
(sync_lock_test_and_set<I48MODE>): Likewise.
(sync_compare_and_swap<I12MODE>): New.
(sync_compare_and_swap<I12MODE>_1): New.
(sync_lock_test_and_set<I12MODE>): New.
(sync_lock_test_and_set<I12MODE>_1): New.
* lib/target-supports.exp (check_effective_target_sync_char_short):
Add alpha.
From-SVN: r101833
2005-07-09 20:28:23 +02:00
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2011-03-21 21:50:35 +01:00
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;; Atomic operations
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UNSPEC_MB
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UNSPEC_ATOMIC
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UNSPEC_CMPXCHG
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UNSPEC_XCHG
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])
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2001-07-15 08:25:01 +02:00
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1998-04-04 15:54:32 +02:00
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;; UNSPEC_VOLATILE:
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2001-07-15 08:25:01 +02:00
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2011-03-21 21:50:35 +01:00
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(define_c_enum "unspecv" [
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UNSPECV_IMB
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UNSPECV_BLOCKAGE
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UNSPECV_SETJMPR ; builtin_setjmp_receiver
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UNSPECV_LONGJMP ; builtin_longjmp
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UNSPECV_TRAPB
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UNSPECV_PSPL ; prologue_stack_probe_loop
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UNSPECV_REALIGN
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UNSPECV_EHR ; exception_receiver
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UNSPECV_MCOUNT
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UNSPECV_FORCE_MOV
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UNSPECV_LDGP1
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UNSPECV_PLDGP2 ; prologue ldgp
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UNSPECV_SET_TP
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UNSPECV_RPCC
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UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment
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UNSPECV_LL ; load-locked
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UNSPECV_SC ; store-conditional
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2011-11-16 00:43:08 +01:00
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UNSPECV_CMPXCHG
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2011-03-21 21:50:35 +01:00
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])
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2001-09-11 10:52:39 +02:00
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predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
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;; On non-BWX targets, CQImode must be handled the similarly to HImode
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;; when generating reloads.
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator RELOAD12 [QI HI CQI])
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predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
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(define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
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md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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;; Other mode iterators
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alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
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(define_mode_iterator IMODE [QI HI SI DI])
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_mode_iterator I12MODE [QI HI])
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_mode_iterator I124MODE [QI HI SI])
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_mode_iterator I24MODE [HI SI])
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_mode_iterator I248MODE [HI SI DI])
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
|
(define_mode_iterator I48MODE [SI DI])
|
2012-10-12 13:32:02 +02:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_mode_attr DWI [(SI "DI") (DI "TI")])
|
2012-10-12 13:32:02 +02:00
|
|
|
|
(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(V8QI "b8") (V4HI "w4")
|
|
|
|
|
(SF "%,") (DF "%-")])
|
2012-10-12 13:32:02 +02:00
|
|
|
|
(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")])
|
|
|
|
|
|
|
|
|
|
(define_code_iterator any_maxmin [smax smin umax umin])
|
|
|
|
|
|
|
|
|
|
(define_code_attr maxmin [(smax "maxs") (smin "mins")
|
|
|
|
|
(umax "maxu") (umin "minu")])
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; Where necessary, the suffixes _le and _be are used to distinguish between
|
|
|
|
|
;; little-endian and big-endian patterns.
|
|
|
|
|
;;
|
|
|
|
|
;; Note that the Unicos/Mk assembler does not support the following
|
|
|
|
|
;; opcodes: mov, fmov, nop, fnop, unop.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1996-06-13 03:47:01 +02:00
|
|
|
|
;; Processor type -- this attribute must exactly match the processor_type
|
|
|
|
|
;; enumeration in alpha.h.
|
|
|
|
|
|
alpha.opt: New file.
* config/alpha/alpha.opt: New file.
* config/alpha/alpha.c (alpha_tune): New. Rename all existing uses
of alpha_cpu.
(alpha_cpu_string, alpha_tune_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string): Make static.
(alpha_tls_size_string): Remove.
(alpha_handle_option): New.
(override_options): Update for alpha_cpu/alpha_tune split.
(alpha_file_start): Likewise.
(TARGET_DEFAULT_TARGET_FLAGS): New.
(TARGET_HANDLE_OPTION): New.
* config/alpha/alpha.h (alpha_tune): Declare.
(MASK_FP, MASK_FPREGS, TARGET_FPREGS, MASK_GAS, TARGET_GAS,
MASK_IEEE_CONFORMANT, TARGET_IEEE_CONFORMANT, MASK_IEEE, TARGET_IEEE,
MASK_IEEE_WITH_INEXACT, TARGET_IEEE_WITH_INEXACT, MASK_BUILD_CONSTANTS,
TARGET_BUILD_CONSTANTS, MASK_FLOAT_VAX, TARGET_FLOAT_VAX, MASK_BWX,
TARGET_BWX, MASK_MAX, TARGET_MAX, MASK_FIX, TARGET_FIX, MASK_CIX,
TARGET_CIX, MASK_EXPLICIT_RELOCS, TARGET_EXPLICIT_RELOCS,
MASK_SMALL_DATA, TARGET_SMALL_DATA, MASK_TLS_KERNEL, TARGET_TLS_KERNEL,
MASK_SMALL_TEXT, TARGET_SMALL_TEXT, MASK_LONG_DOUBLE_128,
TARGET_LONG_DOUBLE_128, MASK_CPU_EV5, TARGET_CPU_EV5, MASK_CPU_EV6,
TARGET_CPU_EV6, MASK_SUPPORT_ARCH): Remove.
(TARGET_SWITCHES, TARGET_OPTIONS): Remove.
(TARGET_DEFAULT): Remove MASK_FP.
(TARGET_FP): Redefined based on TARGET_SOFT_FP.
(TARGET_SUPPORT_ARCH): Default on if HAVE_AS_EXPLICIT_RELOCS.
(alpha_cpu_string, alpha_tune_string, alpha_fprm_string,
alpha_fptm_string, alpha_tp_string, alpha_mlat_string,
alpha_tls_size_string): Remove.
* config/alpha/alpha.md (prefetch): Use alpha_cpu.
(attribute tune): Rename from attribute cpu.
* config/alpha/ev4.md: Update to match.
* config/alpha/ev5.md, config/alpha/ev6.md: Likewise.
* config/alpha/freebsd.h (TARGET_DEFAULT): Remove MASK_FP.
* config/alpha/linux.h (TARGET_DEFAULT): Likewise.
* config/alpha/netbsd.h (TARGET_DEFAULT): Likewise.
* config/alpha/osf5.h (TARGET_DEFAULT): Likewise.
* config/alpha/vms.h (TARGET_DEFAULT): Likewise.
From-SVN: r96602
2005-03-17 11:43:19 +01:00
|
|
|
|
(define_attr "tune" "ev4,ev5,ev6"
|
2009-04-21 10:44:25 +02:00
|
|
|
|
(const (symbol_ref "((enum attr_tune) alpha_tune)")))
|
1996-06-13 03:47:01 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; Define an insn type attribute. This is used in function unit delay
|
|
|
|
|
;; computations, among other purposes. For the most part, we use the names
|
|
|
|
|
;; defined in the EV4 documentation, but add a few that we have to know about
|
|
|
|
|
;; separately.
|
|
|
|
|
|
|
|
|
|
(define_attr "type"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
"ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
|
|
|
|
|
multi,none"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
(const_string "iadd"))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1998-08-26 20:48:21 +02:00
|
|
|
|
;; Describe a user's asm statement.
|
|
|
|
|
(define_asm_attributes
|
|
|
|
|
[(set_attr "type" "multi")])
|
|
|
|
|
|
1998-06-16 19:08:48 +02:00
|
|
|
|
;; Define the operand size an insn operates on. Used primarily by mul
|
ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.4, ChangeLog.5, ChangeLog,
FSFChangeLog.10, FSFChangeLog.11, alias.c, attribs.c,
caller-save.c, calls.c, cfg.c, cfganal.c, cfgcleanup.c, cfgrtl.c,
cppmacro.c, fold-const.c, ifcvt.c, local-alloc.c, profile.c,
sched-int.h, toplev.c, config/alpha/alpha.c,
config/alpha/alpha.md, config/c4x/c4x.h, config/cris/cris.h,
config/cris/cris.md, config/i370/i370.md, config/i386/i386.c,
config/i386/i386.h, config/i386/i386.md, config/i386/xm-djgpp.h,
config/ia64/ia64.c, config/m68hc11/m68hc11.c, config/m68k/m68k.md,
config/mcore/mcore.h, config/mmix/mmix.c, config/ns32k/ns32k.h,
config/ns32k/ns32k.md, config/rs6000/rs6000.c,
config/rs6000/sysv4.h, config/sh/sh.md: Fix spelling errors.
From-SVN: r46760
2001-11-04 03:51:28 +01:00
|
|
|
|
;; and div operations that have size dependent timings.
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(define_attr "opsize" "si,di,udi"
|
|
|
|
|
(const_string "di"))
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
|
2001-07-22 18:02:06 +02:00
|
|
|
|
;; The TRAP attribute marks instructions that may generate traps
|
1997-12-07 01:31:01 +01:00
|
|
|
|
;; (which are imprecise and may need a trapb if software completion
|
1996-03-17 01:33:14 +01:00
|
|
|
|
;; is desired).
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(define_attr "trap" "no,yes"
|
|
|
|
|
(const_string "no"))
|
|
|
|
|
|
|
|
|
|
;; The ROUND_SUFFIX attribute marks which instructions require a
|
|
|
|
|
;; rounding-mode suffix. The value NONE indicates no suffix,
|
2003-07-13 01:02:23 +02:00
|
|
|
|
;; the value NORMAL indicates a suffix controlled by alpha_fprm.
|
2001-07-22 18:02:06 +02:00
|
|
|
|
|
|
|
|
|
(define_attr "round_suffix" "none,normal,c"
|
|
|
|
|
(const_string "none"))
|
|
|
|
|
|
|
|
|
|
;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
|
|
|
|
|
;; NONE no suffix
|
|
|
|
|
;; SU accepts only /su (cmpt et al)
|
|
|
|
|
;; SUI accepts only /sui (cvtqt and cvtqs)
|
|
|
|
|
;; V_SV accepts /v and /sv (cvtql only)
|
|
|
|
|
;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
|
|
|
|
|
;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
|
|
|
|
|
;;
|
2003-07-13 01:02:23 +02:00
|
|
|
|
;; The actual suffix emitted is controlled by alpha_fptm.
|
2001-07-22 18:02:06 +02:00
|
|
|
|
|
|
|
|
|
(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
|
|
|
|
|
(const_string "none"))
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
1998-06-16 19:08:48 +02:00
|
|
|
|
;; The length of an instruction sequence in bytes.
|
|
|
|
|
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(define_attr "length" ""
|
|
|
|
|
(const_int 4))
|
2003-01-16 02:50:54 +01:00
|
|
|
|
|
|
|
|
|
;; The USEGP attribute marks instructions that have relocations that use
|
|
|
|
|
;; the GP.
|
|
|
|
|
|
|
|
|
|
(define_attr "usegp" "no,yes"
|
|
|
|
|
(cond [(eq_attr "type" "ldsym,jsr")
|
|
|
|
|
(const_string "yes")
|
|
|
|
|
(eq_attr "type" "ild,fld,ist,fst")
|
2009-04-28 21:58:17 +02:00
|
|
|
|
(symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))")
|
2003-01-16 02:50:54 +01:00
|
|
|
|
]
|
|
|
|
|
(const_string "no")))
|
|
|
|
|
|
2003-10-27 07:49:41 +01:00
|
|
|
|
;; The CANNOT_COPY attribute marks instructions with relocations that
|
|
|
|
|
;; cannot easily be duplicated. This includes insns with gpdisp relocs
|
|
|
|
|
;; since they have to stay in 1-1 correspondence with one another. This
|
|
|
|
|
;; also includes jsr insns, since they must stay in correspondence with
|
|
|
|
|
;; the immediately following gpdisp instructions.
|
|
|
|
|
|
|
|
|
|
(define_attr "cannot_copy" "false,true"
|
|
|
|
|
(const_string "false"))
|
2011-03-25 01:09:36 +01:00
|
|
|
|
|
|
|
|
|
;; Used to control the "enabled" attribute on a per-instruction basis.
|
2011-03-25 01:34:56 +01:00
|
|
|
|
;; For convenience, conflate ABI issues re loading of addresses with
|
|
|
|
|
;; an "isa".
|
2011-03-25 01:35:01 +01:00
|
|
|
|
(define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er"
|
2011-03-25 01:09:36 +01:00
|
|
|
|
(const_string "base"))
|
|
|
|
|
|
|
|
|
|
(define_attr "enabled" ""
|
|
|
|
|
(cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX")
|
|
|
|
|
(eq_attr "isa" "max") (symbol_ref "TARGET_MAX")
|
|
|
|
|
(eq_attr "isa" "fix") (symbol_ref "TARGET_FIX")
|
|
|
|
|
(eq_attr "isa" "cix") (symbol_ref "TARGET_CIX")
|
2011-03-25 01:35:01 +01:00
|
|
|
|
(eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS")
|
|
|
|
|
(eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS")
|
|
|
|
|
(eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS")
|
2011-03-25 01:09:36 +01:00
|
|
|
|
]
|
|
|
|
|
(const_int 1)))
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
|
2002-05-05 23:54:39 +02:00
|
|
|
|
;; Include scheduling descriptions.
|
|
|
|
|
|
|
|
|
|
(include "ev4.md")
|
|
|
|
|
(include "ev5.md")
|
|
|
|
|
(include "ev6.md")
|
Makefile.in (insn-preds.o): Depend on TREE_H.
* Makefile.in (insn-preds.o): Depend on TREE_H.
* genpreds.c (write_insn_preds_c): Include tree.h.
* config/alpha/alpha.c (reg_or_0_operand, reg_or_6bit_operand,
reg_or_8bit_operand, cint8_operand, add_operand, sext_add_operand,
const48_operand, and_operand, or_operand, mode_width_operand,
mode_mask_operand, mul8_operand, const0_operand,
hard_fp_register_operand, hard_int_register_operand,
reg_or_cint_operand, some_operand, some_ni_operand, input_operand,
samegp_function_operand, direct_call_operand, small_symbolic_operand,
global_symbolic_operand, call_operand, symbolic_operand,
dtp16_symbolic_operand, dtp32_symbolic_operand,
gotdtp_symbolic_operand, tp16_symbolic_operand, tp32_symbolic_operand,
gottp_symbolic_operand, alpha_comparison_operator,
alpha_zero_comparison_operator, alpha_swapped_comparison_operator,
signed_comparison_operator, alpha_fp_comparison_operator,
divmod_operator, fix_operator, aligned_memory_operand,
unaligned_memory_operand, reg_or_unaligned_mem_operand,
any_memory_operand, reg_not_elim_operand, normal_memory_operand,
reg_no_subreg_operand, addition_operation): Move to predicates.md.
(reg_or_const_int_operand): Remove. Replace all users with
reg_or_cint_operand.
(tls_symbolic_operand_1): Export. Don't check mode or for CONST.
(resolve_reload_operand): Split out of aligned_memory_operand.
* config/alpha/alpha-protos.h: Update for exports.
* config/alpha/alpha.h (PREDICATE_CODES): Remove.
* config/alpha/alpha.md: Include predicates.md.
* config/alpha/predicates.md: New file.
From-SVN: r85953
2004-08-13 21:11:35 +02:00
|
|
|
|
|
|
|
|
|
|
2007-02-12 17:10:15 +01:00
|
|
|
|
;; Operand and operator predicates and constraints
|
Makefile.in (insn-preds.o): Depend on TREE_H.
* Makefile.in (insn-preds.o): Depend on TREE_H.
* genpreds.c (write_insn_preds_c): Include tree.h.
* config/alpha/alpha.c (reg_or_0_operand, reg_or_6bit_operand,
reg_or_8bit_operand, cint8_operand, add_operand, sext_add_operand,
const48_operand, and_operand, or_operand, mode_width_operand,
mode_mask_operand, mul8_operand, const0_operand,
hard_fp_register_operand, hard_int_register_operand,
reg_or_cint_operand, some_operand, some_ni_operand, input_operand,
samegp_function_operand, direct_call_operand, small_symbolic_operand,
global_symbolic_operand, call_operand, symbolic_operand,
dtp16_symbolic_operand, dtp32_symbolic_operand,
gotdtp_symbolic_operand, tp16_symbolic_operand, tp32_symbolic_operand,
gottp_symbolic_operand, alpha_comparison_operator,
alpha_zero_comparison_operator, alpha_swapped_comparison_operator,
signed_comparison_operator, alpha_fp_comparison_operator,
divmod_operator, fix_operator, aligned_memory_operand,
unaligned_memory_operand, reg_or_unaligned_mem_operand,
any_memory_operand, reg_not_elim_operand, normal_memory_operand,
reg_no_subreg_operand, addition_operation): Move to predicates.md.
(reg_or_const_int_operand): Remove. Replace all users with
reg_or_cint_operand.
(tls_symbolic_operand_1): Export. Don't check mode or for CONST.
(resolve_reload_operand): Split out of aligned_memory_operand.
* config/alpha/alpha-protos.h: Update for exports.
* config/alpha/alpha.h (PREDICATE_CODES): Remove.
* config/alpha/alpha.md: Include predicates.md.
* config/alpha/predicates.md: New file.
From-SVN: r85953
2004-08-13 21:11:35 +02:00
|
|
|
|
|
|
|
|
|
(include "predicates.md")
|
2007-02-12 17:10:15 +01:00
|
|
|
|
(include "constraints.md")
|
Makefile.in (insn-preds.o): Depend on TREE_H.
* Makefile.in (insn-preds.o): Depend on TREE_H.
* genpreds.c (write_insn_preds_c): Include tree.h.
* config/alpha/alpha.c (reg_or_0_operand, reg_or_6bit_operand,
reg_or_8bit_operand, cint8_operand, add_operand, sext_add_operand,
const48_operand, and_operand, or_operand, mode_width_operand,
mode_mask_operand, mul8_operand, const0_operand,
hard_fp_register_operand, hard_int_register_operand,
reg_or_cint_operand, some_operand, some_ni_operand, input_operand,
samegp_function_operand, direct_call_operand, small_symbolic_operand,
global_symbolic_operand, call_operand, symbolic_operand,
dtp16_symbolic_operand, dtp32_symbolic_operand,
gotdtp_symbolic_operand, tp16_symbolic_operand, tp32_symbolic_operand,
gottp_symbolic_operand, alpha_comparison_operator,
alpha_zero_comparison_operator, alpha_swapped_comparison_operator,
signed_comparison_operator, alpha_fp_comparison_operator,
divmod_operator, fix_operator, aligned_memory_operand,
unaligned_memory_operand, reg_or_unaligned_mem_operand,
any_memory_operand, reg_not_elim_operand, normal_memory_operand,
reg_no_subreg_operand, addition_operation): Move to predicates.md.
(reg_or_const_int_operand): Remove. Replace all users with
reg_or_cint_operand.
(tls_symbolic_operand_1): Export. Don't check mode or for CONST.
(resolve_reload_operand): Split out of aligned_memory_operand.
* config/alpha/alpha-protos.h: Update for exports.
* config/alpha/alpha.h (PREDICATE_CODES): Remove.
* config/alpha/alpha.md: Include predicates.md.
* config/alpha/predicates.md: New file.
From-SVN: r85953
2004-08-13 21:11:35 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; First define the arithmetic insns. Note that the 32-bit forms also
|
|
|
|
|
;; sign-extend.
|
|
|
|
|
|
1998-04-04 15:54:32 +02:00
|
|
|
|
;; Handle 32-64 bit extension from memory to a floating point register
|
ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.4, ChangeLog.5, ChangeLog,
FSFChangeLog.10, FSFChangeLog.11, alias.c, attribs.c,
caller-save.c, calls.c, cfg.c, cfganal.c, cfgcleanup.c, cfgrtl.c,
cppmacro.c, fold-const.c, ifcvt.c, local-alloc.c, profile.c,
sched-int.h, toplev.c, config/alpha/alpha.c,
config/alpha/alpha.md, config/c4x/c4x.h, config/cris/cris.h,
config/cris/cris.md, config/i370/i370.md, config/i386/i386.c,
config/i386/i386.h, config/i386/i386.md, config/i386/xm-djgpp.h,
config/ia64/ia64.c, config/m68hc11/m68hc11.c, config/m68k/m68k.md,
config/mcore/mcore.h, config/mmix/mmix.c, config/ns32k/ns32k.h,
config/ns32k/ns32k.md, config/rs6000/rs6000.c,
config/rs6000/sysv4.h, config/sh/sh.md: Fix spelling errors.
From-SVN: r46760
2001-11-04 03:51:28 +01:00
|
|
|
|
;; specially, since this occurs frequently in int->double conversions.
|
1998-04-04 15:54:32 +02:00
|
|
|
|
;;
|
|
|
|
|
;; Note that while we must retain the =f case in the insn for reload's
|
|
|
|
|
;; benefit, it should be eliminated after reload, so we should never emit
|
|
|
|
|
;; code for that case. But we don't reject the possibility.
|
|
|
|
|
|
1999-10-09 22:18:48 +02:00
|
|
|
|
(define_expand "extendsidi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
|
1999-10-09 22:18:48 +02:00
|
|
|
|
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(define_insn "*cvtlq"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=f")
|
|
|
|
|
(unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
|
|
|
|
|
UNSPEC_CVTLQ))]
|
|
|
|
|
""
|
|
|
|
|
"cvtlq %1,%0"
|
|
|
|
|
[(set_attr "type" "fadd")])
|
1999-10-09 22:18:48 +02:00
|
|
|
|
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(define_insn "*extendsidi2_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
|
1999-10-09 22:18:48 +02:00
|
|
|
|
(sign_extend:DI
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
|
|
|
|
|
""
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"@
|
2002-10-14 21:57:18 +02:00
|
|
|
|
addl $31,%1,%0
|
1992-10-24 15:33:28 +01:00
|
|
|
|
ldl %0,%1
|
1998-04-04 15:54:32 +02:00
|
|
|
|
lds %0,%1\;cvtlq %0,%0"
|
2004-01-19 10:55:42 +01:00
|
|
|
|
[(set_attr "type" "iadd,ild,fld")
|
|
|
|
|
(set_attr "length" "*,*,8")])
|
1998-04-04 15:54:32 +02:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "hard_fp_register_operand")
|
|
|
|
|
(sign_extend:DI (match_operand:SI 1 "memory_operand")))]
|
1998-04-04 15:54:32 +02:00
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (match_dup 1))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
|
|
|
|
|
{
|
|
|
|
|
operands[1] = adjust_address (operands[1], SFmode, 0);
|
|
|
|
|
operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
|
|
|
|
|
})
|
1998-04-04 15:54:32 +02:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
;; Optimize sign-extension of SImode loads. This shows up in the wake of
|
|
|
|
|
;; reload when converting fp->int.
|
|
|
|
|
|
|
|
|
|
(define_peephole2
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 0 "hard_int_register_operand")
|
|
|
|
|
(match_operand:SI 1 "memory_operand"))
|
|
|
|
|
(set (match_operand:DI 2 "hard_int_register_operand")
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(sign_extend:DI (match_dup 0)))]
|
|
|
|
|
"true_regnum (operands[0]) == true_regnum (operands[2])
|
|
|
|
|
|| peep2_reg_dead_p (2, operands[0])"
|
|
|
|
|
[(set (match_dup 2)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(sign_extend:DI (match_dup 1)))])
|
2000-10-24 02:06:18 +02:00
|
|
|
|
|
2009-08-11 19:05:38 +02:00
|
|
|
|
(define_insn "addsi3"
|
1993-04-10 16:56:02 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
1993-10-07 13:56:20 +01:00
|
|
|
|
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
|
1993-04-10 16:56:02 +02:00
|
|
|
|
(match_operand:SI 2 "add_operand" "rI,O,K,L")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
addl %r1,%2,%0
|
1993-04-10 16:56:02 +02:00
|
|
|
|
subl %r1,%n2,%0
|
1992-10-24 15:33:28 +01:00
|
|
|
|
lda %0,%2(%r1)
|
1996-06-13 03:47:01 +02:00
|
|
|
|
ldah %0,%h2(%r1)")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(plus:SI (match_operand:SI 1 "register_operand")
|
|
|
|
|
(match_operand:SI 2 "const_int_operand")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"! add_operand (operands[2], SImode)"
|
|
|
|
|
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
|
|
|
|
|
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
|
|
|
|
|
{
|
|
|
|
|
HOST_WIDE_INT val = INTVAL (operands[2]);
|
|
|
|
|
HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
|
|
|
|
|
HOST_WIDE_INT rest = val - low;
|
|
|
|
|
|
|
|
|
|
operands[3] = GEN_INT (rest);
|
|
|
|
|
operands[4] = GEN_INT (low);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*addsi_se"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:SI 2 "sext_add_operand" "rI,O"))))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
addl %r1,%2,%0
|
1996-06-13 03:47:01 +02:00
|
|
|
|
subl %r1,%n2,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2002-02-24 13:46:52 +01:00
|
|
|
|
(define_insn "*addsi_se2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:DI 2 "sext_add_operand" "rI,O"))
|
|
|
|
|
0)))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
addl %r1,%2,%0
|
|
|
|
|
subl %r1,%n2,%0")
|
|
|
|
|
|
1993-03-06 00:41:22 +01:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1993-03-06 00:41:22 +01:00
|
|
|
|
(sign_extend:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(plus:SI (match_operand:SI 1 "reg_not_elim_operand")
|
|
|
|
|
(match_operand:SI 2 "const_int_operand"))))
|
|
|
|
|
(clobber (match_operand:SI 3 "reg_not_elim_operand"))]
|
1993-04-10 16:56:02 +02:00
|
|
|
|
"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
|
1993-03-06 00:41:22 +01:00
|
|
|
|
&& INTVAL (operands[2]) % 4 == 0"
|
|
|
|
|
[(set (match_dup 3) (match_dup 4))
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3)
|
|
|
|
|
(match_dup 5))
|
1993-03-06 00:41:22 +01:00
|
|
|
|
(match_dup 1))))]
|
|
|
|
|
{
|
|
|
|
|
HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
|
|
|
|
|
int mult = 4;
|
|
|
|
|
|
|
|
|
|
if (val % 2 == 0)
|
|
|
|
|
val /= 2, mult = 8;
|
|
|
|
|
|
|
|
|
|
operands[4] = GEN_INT (val);
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[5] = GEN_INT (exact_log2 (mult));
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1993-03-06 00:41:22 +01:00
|
|
|
|
|
1994-05-27 13:26:20 +02:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1994-05-27 13:26:20 +02:00
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(plus:SI (match_operator:SI 1 "comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand 2)
|
|
|
|
|
(match_operand 3)])
|
|
|
|
|
(match_operand:SI 4 "add_operand"))))
|
|
|
|
|
(clobber (match_operand:DI 5 "register_operand"))]
|
1994-05-27 13:26:20 +02:00
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 5) (match_dup 6))
|
|
|
|
|
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
|
|
|
|
|
{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
|
|
|
|
|
operands[2], operands[3]);
|
1994-05-27 13:26:20 +02:00
|
|
|
|
operands[7] = gen_lowpart (SImode, operands[5]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1994-05-27 13:26:20 +02:00
|
|
|
|
|
1999-10-30 23:46:57 +02:00
|
|
|
|
(define_expand "adddi3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "add_operand")))])
|
1999-10-30 23:46:57 +02:00
|
|
|
|
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(define_insn "*adddi_er_lo16_dtp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "dtp16_symbolic_operand")))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"lda %0,%2(%1)\t\t!dtprel")
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddi_er_hi32_dtp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"ldah %0,%2(%1)\t\t!dtprelhi")
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddi_er_lo32_dtp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "dtp32_symbolic_operand")))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"lda %0,%2(%1)\t\t!dtprello")
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddi_er_lo16_tp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "tp16_symbolic_operand")))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"lda %0,%2(%1)\t\t!tprel")
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddi_er_hi32_tp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"ldah %0,%2(%1)\t\t!tprelhi")
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddi_er_lo32_tp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "tp32_symbolic_operand")))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"lda %0,%2(%1)\t\t!tprello")
|
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(define_insn "*adddi_er_high_l"
|
2001-09-13 10:42:20 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
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|
(high:DI (match_operand:DI 2 "local_symbolic_operand"))))]
|
2003-03-28 06:14:36 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && reload_completed"
|
2003-01-16 02:50:54 +01:00
|
|
|
|
"ldah %0,%2(%1)\t\t!gprelhigh"
|
|
|
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|
[(set_attr "usegp" "yes")])
|
2001-09-13 10:42:20 +02:00
|
|
|
|
|
2002-01-04 09:15:22 +01:00
|
|
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(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
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[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(high:DI (match_operand:DI 1 "local_symbolic_operand")))]
|
2002-01-04 09:15:22 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(plus:DI (match_dup 2) (high:DI (match_dup 1))))]
|
|
|
|
|
"operands[2] = pic_offset_table_rtx;")
|
|
|
|
|
|
1999-10-30 23:46:57 +02:00
|
|
|
|
;; We used to expend quite a lot of effort choosing addq/subq/lda.
|
|
|
|
|
;; With complications like
|
|
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|
|
;;
|
|
|
|
|
;; The NT stack unwind code can't handle a subq to adjust the stack
|
|
|
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;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
|
|
|
|
|
;; the exception handling code will loop if a subq is used and an
|
|
|
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|
;; exception occurs.
|
2001-07-15 09:17:29 +02:00
|
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;;
|
1999-10-30 23:46:57 +02:00
|
|
|
|
;; The 19980616 change to emit prologues as RTL also confused some
|
|
|
|
|
;; versions of GDB, which also interprets prologues. This has been
|
|
|
|
|
;; fixed as of GDB 4.18, but it does not harm to unconditionally
|
|
|
|
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;; use lda here.
|
|
|
|
|
;;
|
|
|
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;; and the fact that the three insns schedule exactly the same, it's
|
|
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|
;; just not worth the effort.
|
|
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|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*adddi_internal"
|
1999-10-30 23:46:57 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
|
|
|
|
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(match_operand:DI 2 "add_operand" "r,K,L")))]
|
|
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|
""
|
|
|
|
|
"@
|
|
|
|
|
addq %1,%2,%0
|
|
|
|
|
lda %0,%2(%1)
|
|
|
|
|
ldah %0,%h2(%1)")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1999-04-18 01:31:34 +02:00
|
|
|
|
;; ??? Allow large constants when basing off the frame pointer or some
|
|
|
|
|
;; virtual register that may eliminate to the frame pointer. This is
|
|
|
|
|
;; done because register elimination offsets will change the hi/lo split,
|
|
|
|
|
;; and if we split before reload, we will require additional instructions.
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*adddi_fp_hack"
|
2004-08-26 12:03:38 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand" "K,L,n")))]
|
2001-09-05 10:43:13 +02:00
|
|
|
|
"NONSTRICT_REG_OK_FP_BASE_P (operands[1])
|
2000-01-07 02:46:25 +01:00
|
|
|
|
&& INTVAL (operands[2]) >= 0
|
|
|
|
|
/* This is the largest constant an lda+ldah pair can add, minus
|
|
|
|
|
an upper bound on the displacement between SP and AP during
|
|
|
|
|
register elimination. See INITIAL_ELIMINATION_OFFSET. */
|
|
|
|
|
&& INTVAL (operands[2])
|
|
|
|
|
< (0x7fff8000
|
|
|
|
|
- FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
|
2008-04-08 10:59:34 +02:00
|
|
|
|
- ALPHA_ROUND(crtl->outgoing_args_size)
|
2000-01-07 02:46:25 +01:00
|
|
|
|
- (ALPHA_ROUND (get_frame_size ()
|
|
|
|
|
+ max_reg_num () * UNITS_PER_WORD
|
2008-04-08 10:59:34 +02:00
|
|
|
|
+ crtl->args.pretend_args_size)
|
|
|
|
|
- crtl->args.pretend_args_size))"
|
2004-08-26 12:03:38 +02:00
|
|
|
|
"@
|
|
|
|
|
lda %0,%2(%1)
|
|
|
|
|
ldah %0,%h2(%1)
|
|
|
|
|
#")
|
1999-04-18 01:31:34 +02:00
|
|
|
|
|
|
|
|
|
;; Don't do this if we are adjusting SP since we don't want to do it
|
|
|
|
|
;; in two steps. Don't split FP sources for the reason listed above.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")))]
|
1993-04-10 16:56:02 +02:00
|
|
|
|
"! add_operand (operands[2], DImode)
|
1999-04-18 01:31:34 +02:00
|
|
|
|
&& operands[0] != stack_pointer_rtx
|
|
|
|
|
&& operands[1] != frame_pointer_rtx
|
|
|
|
|
&& operands[1] != arg_pointer_rtx"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
|
|
|
|
|
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
|
|
|
|
|
{
|
|
|
|
|
HOST_WIDE_INT val = INTVAL (operands[2]);
|
|
|
|
|
HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
|
|
|
|
|
HOST_WIDE_INT rest = val - low;
|
2007-02-12 17:10:15 +01:00
|
|
|
|
rtx rest_rtx = GEN_INT (rest);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
operands[4] = GEN_INT (low);
|
2007-02-12 17:10:15 +01:00
|
|
|
|
if (satisfies_constraint_L (rest_rtx))
|
|
|
|
|
operands[3] = rest_rtx;
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
else if (can_create_pseudo_p ())
|
2000-01-07 02:46:25 +01:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
|
|
emit_move_insn (operands[3], operands[2]);
|
|
|
|
|
emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "*sadd<modesuffix>"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
|
|
|
|
|
(plus:I48MODE
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
|
|
|
|
|
(match_operand:I48MODE 2 "const23_operand" "I,I"))
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1993-04-10 16:56:02 +02:00
|
|
|
|
"@
|
2018-01-07 20:14:55 +01:00
|
|
|
|
s%P2add<modesuffix> %1,%3,%0
|
|
|
|
|
s%P2sub<modesuffix> %1,%n3,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(define_insn_and_split "*saddsi_1"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
|
|
(plus:SI
|
|
|
|
|
(subreg:SI
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
|
|
|
|
|
(match_operand:DI 2 "const23_operand" "I,I")) 0)
|
|
|
|
|
(match_operand:SI 3 "sext_add_operand" "rI,O")))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(plus:SI (ashift:SI (match_dup 1) (match_dup 2))
|
|
|
|
|
(match_dup 3)))]
|
|
|
|
|
"operands[1] = gen_lowpart (SImode, operands[1]);")
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*saddl_se"
|
1993-04-10 16:56:02 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(sign_extend:DI
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(plus:SI
|
|
|
|
|
(ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
|
|
|
|
|
(match_operand:SI 2 "const23_operand" "I,I"))
|
|
|
|
|
(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1993-04-10 16:56:02 +02:00
|
|
|
|
"@
|
2018-01-07 20:14:55 +01:00
|
|
|
|
s%P2addl %1,%3,%0
|
|
|
|
|
s%P2subl %1,%n3,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(define_insn_and_split "*saddl_se_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(plus:SI
|
|
|
|
|
(subreg:SI
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
|
|
|
|
|
(match_operand:DI 2 "const23_operand" "I,I")) 0)
|
|
|
|
|
(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(plus:SI (ashift:SI (match_dup 1) (match_dup 2))
|
|
|
|
|
(match_dup 3))))]
|
|
|
|
|
"operands[1] = gen_lowpart (SImode, operands[1]);")
|
|
|
|
|
|
1994-05-27 20:15:25 +02:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1994-05-27 20:15:25 +02:00
|
|
|
|
(sign_extend:DI
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand 2)
|
|
|
|
|
(match_operand 3)])
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(match_operand:SI 4 "const23_operand"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:SI 5 "sext_add_operand"))))
|
|
|
|
|
(clobber (match_operand:DI 6 "reg_not_elim_operand"))]
|
1994-05-27 20:15:25 +02:00
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 6) (match_dup 7))
|
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4))
|
1994-05-27 20:15:25 +02:00
|
|
|
|
(match_dup 5))))]
|
|
|
|
|
{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
|
|
|
|
|
operands[2], operands[3]);
|
1994-05-27 20:15:25 +02:00
|
|
|
|
operands[8] = gen_lowpart (SImode, operands[6]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1994-05-27 20:15:25 +02:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "addv<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
|
|
|
|
|
(plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "sext_add_operand" "rI,O")))
|
|
|
|
|
(trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1))
|
|
|
|
|
(sign_extend:<DWI> (match_dup 2)))
|
|
|
|
|
(sign_extend:<DWI> (plus:I48MODE (match_dup 1)
|
|
|
|
|
(match_dup 2))))
|
2001-01-03 23:52:42 +01:00
|
|
|
|
(const_int 0))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
2012-10-11 17:44:54 +02:00
|
|
|
|
add<modesuffix>v %r1,%2,%0
|
|
|
|
|
sub<modesuffix>v %r1,%n2,%0")
|
2001-01-03 23:52:42 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "neg<mode>2"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"sub<modesuffix> $31,%1,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*negsi_se"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI (neg:SI
|
|
|
|
|
(match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
|
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"subl $31,%1,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "negv<mode>2"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r")))
|
|
|
|
|
(trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1)))
|
|
|
|
|
(sign_extend:<DWI> (neg:I48MODE (match_dup 1))))
|
2001-01-03 23:52:42 +01:00
|
|
|
|
(const_int 0))]
|
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"sub<modesuffix>v $31,%1,%0")
|
2001-01-03 23:52:42 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "sub<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"sub<modesuffix> %r1,%2,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*subsi_se"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"subl %r1,%2,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2002-02-24 13:46:52 +01:00
|
|
|
|
(define_insn "*subsi_se2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rI"))
|
|
|
|
|
0)))]
|
|
|
|
|
""
|
|
|
|
|
"subl %r1,%2,%0")
|
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "*ssub<modesuffix>"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(minus:I48MODE
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
|
|
|
|
|
(match_operand:I48MODE 2 "const23_operand" "I"))
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2018-01-07 20:14:55 +01:00
|
|
|
|
"s%P2sub<modesuffix> %1,%3,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(define_insn_and_split "*ssubsi_1"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
|
(minus:SI
|
|
|
|
|
(subreg:SI
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
|
|
|
|
|
(match_operand:DI 2 "const23_operand" "I")) 0)
|
|
|
|
|
(match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(minus:SI (ashift:SI (match_dup 1) (match_dup 2))
|
|
|
|
|
(match_dup 3)))]
|
|
|
|
|
"operands[1] = gen_lowpart (SImode, operands[1]);")
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*ssubl_se"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(minus:SI
|
|
|
|
|
(ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
|
|
|
|
|
(match_operand:SI 2 "const23_operand" "I"))
|
|
|
|
|
(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2018-01-07 20:14:55 +01:00
|
|
|
|
"s%P2subl %1,%3,%0")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2018-01-14 16:45:38 +01:00
|
|
|
|
(define_insn_and_split "*ssubl_se_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(minus:SI
|
|
|
|
|
(subreg:SI
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
|
|
|
|
|
(match_operand:DI 2 "const23_operand" "I")) 0)
|
|
|
|
|
(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(minus:SI (ashift:SI (match_dup 1) (match_dup 2))
|
|
|
|
|
(match_dup 3))))]
|
|
|
|
|
"operands[1] = gen_lowpart (SImode, operands[1]);")
|
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "subv<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
|
|
|
|
|
(trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1))
|
|
|
|
|
(sign_extend:<DWI> (match_dup 2)))
|
|
|
|
|
(sign_extend:<DWI> (minus:I48MODE (match_dup 1)
|
|
|
|
|
(match_dup 2))))
|
2001-01-03 23:52:42 +01:00
|
|
|
|
(const_int 0))]
|
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"sub<modesuffix>v %r1,%2,%0")
|
2001-01-03 23:52:42 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "mul<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
|
2011-03-22 23:24:28 +01:00
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"mul<modesuffix> %r1,%2,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "imul")
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(set_attr "opsize" "<mode>")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*mulsi_se"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1998-11-06 20:43:53 +01:00
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
|
|
|
|
|
(match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
|
2011-03-22 23:24:28 +01:00
|
|
|
|
""
|
1998-11-06 20:43:53 +01:00
|
|
|
|
"mull %r1,%2,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "imul")
|
|
|
|
|
(set_attr "opsize" "si")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "mulv<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
|
|
|
|
|
(trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1))
|
|
|
|
|
(sign_extend:<DWI> (match_dup 2)))
|
|
|
|
|
(sign_extend:<DWI> (mult:I48MODE (match_dup 1)
|
|
|
|
|
(match_dup 2))))
|
2001-01-03 23:52:42 +01:00
|
|
|
|
(const_int 0))]
|
2011-03-22 23:24:28 +01:00
|
|
|
|
""
|
2012-10-11 17:44:54 +02:00
|
|
|
|
"mul<modesuffix>v %r1,%2,%0"
|
2001-01-03 23:52:42 +01:00
|
|
|
|
[(set_attr "type" "imul")
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(set_attr "opsize" "<mode>")])
|
2001-01-03 23:52:42 +01:00
|
|
|
|
|
2003-03-30 21:00:12 +02:00
|
|
|
|
(define_expand "umuldi3_highpart"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
2003-03-30 21:00:12 +02:00
|
|
|
|
(truncate:DI
|
|
|
|
|
(lshiftrt:TI
|
|
|
|
|
(mult:TI (zero_extend:TI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand"))
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand"))
|
2003-03-30 21:00:12 +02:00
|
|
|
|
(const_int 64))))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (REG_P (operands[2]))
|
|
|
|
|
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*umuldi3_highpart_reg"
|
1994-06-29 02:19:15 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(truncate:DI
|
|
|
|
|
(lshiftrt:TI
|
1998-11-06 20:43:53 +01:00
|
|
|
|
(mult:TI (zero_extend:TI
|
2003-03-30 21:00:12 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand" "r"))
|
1998-11-06 20:43:53 +01:00
|
|
|
|
(zero_extend:TI
|
2003-03-30 21:00:12 +02:00
|
|
|
|
(match_operand:DI 2 "register_operand" "r")))
|
1994-06-29 02:19:15 +02:00
|
|
|
|
(const_int 64))))]
|
|
|
|
|
""
|
2003-03-30 21:00:12 +02:00
|
|
|
|
"umulh %1,%2,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "imul")
|
|
|
|
|
(set_attr "opsize" "udi")])
|
1994-06-29 02:19:15 +02:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*umuldi3_highpart_const"
|
1994-06-29 02:19:15 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(truncate:DI
|
|
|
|
|
(lshiftrt:TI
|
|
|
|
|
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
|
|
|
|
|
(match_operand:TI 2 "cint8_operand" "I"))
|
|
|
|
|
(const_int 64))))]
|
|
|
|
|
""
|
|
|
|
|
"umulh %1,%2,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "imul")
|
|
|
|
|
(set_attr "opsize" "udi")])
|
2013-02-01 17:34:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "umulditi3"
|
|
|
|
|
[(set (match_operand:TI 0 "register_operand")
|
|
|
|
|
(mult:TI
|
|
|
|
|
(zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand"))
|
|
|
|
|
(zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
|
|
|
|
|
emit_insn (gen_muldi3 (l, operands[1], operands[2]));
|
|
|
|
|
emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
|
|
|
|
|
emit_move_insn (gen_lowpart (DImode, operands[0]), l);
|
|
|
|
|
emit_move_insn (gen_highpart (DImode, operands[0]), h);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; The divide and remainder operations take their inputs from r24 and
|
2011-03-22 23:24:28 +01:00
|
|
|
|
;; r25, put their output in r27, and clobber r23 and r28 on all systems.
|
|
|
|
|
;;
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; ??? Force sign-extension here because some versions of OSF/1 and
|
|
|
|
|
;; Interix/NT don't do the right thing if the inputs are not properly
|
|
|
|
|
;; sign-extended. But Linux, for instance, does not have this
|
|
|
|
|
;; problem. Is it worth the complication here to eliminate the sign
|
|
|
|
|
;; extension?
|
1998-06-02 17:37:34 +02:00
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_code_iterator any_divmod [div mod udiv umod])
|
1998-06-02 17:37:34 +02:00
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_expand "<code>si3"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
(set (match_dup 4)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand")))
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
(parallel [(set (match_dup 5)
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(any_divmod:SI (match_dup 3) (match_dup 4))))
|
1998-06-02 17:37:34 +02:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))])
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:SI 0 "nonimmediate_operand")
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
(subreg:SI (match_dup 5) 0))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_ABI_OSF"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
|
|
operands[4] = gen_reg_rtx (DImode);
|
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_expand "<code>di3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:DI 0 "register_operand")
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(any_divmod:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "register_operand")))
|
1993-01-07 02:52:42 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
(clobber (reg:DI 28))])]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"TARGET_ABI_OSF")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1998-06-16 19:08:48 +02:00
|
|
|
|
;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
|
|
|
|
|
;; expanded by the assembler.
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(define_insn_and_split "*divmodsi_internal_er"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")])))
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2005-06-01 10:19:44 +02:00
|
|
|
|
"#"
|
2001-12-12 03:53:38 +01:00
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(parallel [(set (match_dup 0)
|
|
|
|
|
(sign_extend:DI (match_dup 3)))
|
|
|
|
|
(use (match_dup 0))
|
2002-01-23 00:13:58 +01:00
|
|
|
|
(use (match_dup 4))
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))])]
|
|
|
|
|
{
|
|
|
|
|
const char *str;
|
|
|
|
|
switch (GET_CODE (operands[3]))
|
|
|
|
|
{
|
|
|
|
|
case DIV:
|
|
|
|
|
str = "__divl";
|
|
|
|
|
break;
|
|
|
|
|
case UDIV:
|
|
|
|
|
str = "__divlu";
|
|
|
|
|
break;
|
|
|
|
|
case MOD:
|
|
|
|
|
str = "__reml";
|
|
|
|
|
break;
|
|
|
|
|
case UMOD:
|
|
|
|
|
str = "__remlu";
|
|
|
|
|
break;
|
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2001-12-12 03:53:38 +01:00
|
|
|
|
}
|
2002-01-23 00:13:58 +01:00
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
|
|
|
|
|
gen_rtx_SYMBOL_REF (DImode, str),
|
|
|
|
|
operands[4]));
|
2001-12-12 03:53:38 +01:00
|
|
|
|
}
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "8")])
|
|
|
|
|
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(define_insn "*divmodsi_internal_er_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")])))
|
|
|
|
|
(use (match_operand:DI 4 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 5 "const_int_operand"))
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2005-06-01 10:19:44 +02:00
|
|
|
|
"jsr $23,($27),__%E3%j5"
|
2001-12-12 03:53:38 +01:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*divmodsi_internal"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")])))
|
1998-06-02 17:37:34 +02:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_ABI_OSF"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
"%E3 %1,%2,%0"
|
1998-06-16 19:08:48 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "8")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(define_insn_and_split "*divmoddi_internal_er"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(match_operator:DI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")]))
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2005-06-01 10:19:44 +02:00
|
|
|
|
"#"
|
2001-12-12 03:53:38 +01:00
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(parallel [(set (match_dup 0) (match_dup 3))
|
|
|
|
|
(use (match_dup 0))
|
2002-01-23 00:13:58 +01:00
|
|
|
|
(use (match_dup 4))
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))])]
|
|
|
|
|
{
|
|
|
|
|
const char *str;
|
|
|
|
|
switch (GET_CODE (operands[3]))
|
|
|
|
|
{
|
|
|
|
|
case DIV:
|
|
|
|
|
str = "__divq";
|
|
|
|
|
break;
|
|
|
|
|
case UDIV:
|
|
|
|
|
str = "__divqu";
|
|
|
|
|
break;
|
|
|
|
|
case MOD:
|
|
|
|
|
str = "__remq";
|
|
|
|
|
break;
|
|
|
|
|
case UMOD:
|
|
|
|
|
str = "__remqu";
|
|
|
|
|
break;
|
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2001-12-12 03:53:38 +01:00
|
|
|
|
}
|
2002-01-23 00:13:58 +01:00
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
|
|
|
|
|
gen_rtx_SYMBOL_REF (DImode, str),
|
|
|
|
|
operands[4]));
|
2001-12-12 03:53:38 +01:00
|
|
|
|
}
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "8")])
|
|
|
|
|
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(define_insn "*divmoddi_internal_er_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(match_operator:DI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")]))
|
|
|
|
|
(use (match_operand:DI 4 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 5 "const_int_operand"))
|
2001-12-12 03:53:38 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2005-06-01 10:19:44 +02:00
|
|
|
|
"jsr $23,($27),__%E3%j5"
|
2001-12-12 03:53:38 +01:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*divmoddi_internal"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=c")
|
|
|
|
|
(match_operator:DI 3 "divmod_operator"
|
|
|
|
|
[(match_operand:DI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "b")]))
|
1993-01-07 02:38:58 +01:00
|
|
|
|
(clobber (reg:DI 23))
|
|
|
|
|
(clobber (reg:DI 28))]
|
2011-03-23 00:08:16 +01:00
|
|
|
|
"TARGET_ABI_OSF"
|
alpha.h (enum reg_class): Add R24_REG, R25_REG; rename PV_REG to R27_REG.
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
From-SVN: r46535
2001-10-26 10:01:13 +02:00
|
|
|
|
"%E3 %1,%2,%0"
|
1998-06-16 19:08:48 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "8")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
;; Next are the basic logical operations. We only expose the DImode operations
|
|
|
|
|
;; to the rtl expanders, but SImode versions exist for combine as well as for
|
|
|
|
|
;; the atomic operation splitters.
|
|
|
|
|
|
|
|
|
|
(define_insn "*andsi_internal"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
|
|
|
|
(and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
|
2015-05-12 22:05:23 +02:00
|
|
|
|
(match_operand:SI 2 "and_operand" "rI,N,M")))]
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
and %r1,%2,%0
|
|
|
|
|
bic %r1,%N2,%0
|
|
|
|
|
zapnot %r1,%m2,%0"
|
|
|
|
|
[(set_attr "type" "ilog,ilog,shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "anddi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
|
|
|
|
|
(and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
|
2015-05-12 22:05:23 +02:00
|
|
|
|
(match_operand:DI 2 "and_operand" "rI,N,M")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
and %r1,%2,%0
|
|
|
|
|
bic %r1,%N2,%0
|
|
|
|
|
zapnot %r1,%m2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog,ilog,shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1996-02-18 19:44:00 +01:00
|
|
|
|
;; There are times when we can split an AND into two AND insns. This occurs
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; when we can first clear any bytes and then clear anything else. For
|
|
|
|
|
;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
|
1996-02-18 19:44:00 +01:00
|
|
|
|
;; Only do this when running on 64-bit host since the computations are
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; too messy otherwise.
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(and:DI (match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")))]
|
2015-05-11 09:21:19 +02:00
|
|
|
|
"! and_operand (operands[2], DImode)"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
|
|
|
|
|
(set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
|
|
|
|
|
{
|
|
|
|
|
unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
|
|
|
|
|
unsigned HOST_WIDE_INT mask2 = mask1;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* For each byte that isn't all zeros, make it all ones. */
|
|
|
|
|
for (i = 0; i < 64; i += 8)
|
|
|
|
|
if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
|
|
|
|
|
mask1 |= (HOST_WIDE_INT) 0xff << i;
|
|
|
|
|
|
|
|
|
|
/* Now turn on any bits we've just turned off. */
|
|
|
|
|
mask2 |= ~ mask1;
|
|
|
|
|
|
|
|
|
|
operands[3] = GEN_INT (mask1);
|
|
|
|
|
operands[4] = GEN_INT (mask2);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "zero_extendqi<mode>2"
|
|
|
|
|
[(set (match_operand:I248MODE 0 "register_operand" "=r,r")
|
|
|
|
|
(zero_extend:I248MODE
|
2011-03-25 01:09:36 +01:00
|
|
|
|
(match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
|
|
|
|
|
""
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"@
|
|
|
|
|
and %1,0xff,%0
|
|
|
|
|
ldbu %0,%1"
|
2011-03-25 01:09:36 +01:00
|
|
|
|
[(set_attr "type" "ilog,ild")
|
|
|
|
|
(set_attr "isa" "*,bwx")])
|
2000-10-24 02:06:18 +02:00
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "zero_extendhi<mode>2"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
|
|
|
|
|
(zero_extend:I48MODE
|
2011-03-25 01:09:36 +01:00
|
|
|
|
(match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))]
|
|
|
|
|
""
|
1996-11-12 23:53:16 +01:00
|
|
|
|
"@
|
|
|
|
|
zapnot %1,3,%0
|
|
|
|
|
ldwu %0,%1"
|
2011-03-25 01:09:36 +01:00
|
|
|
|
[(set_attr "type" "shift,ild")
|
|
|
|
|
(set_attr "isa" "*,bwx")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "zero_extendsidi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"zapnot %1,15,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "andnot<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(and:I48MODE
|
|
|
|
|
(not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"bic %r2,%1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
(define_insn "*iorsi_internal"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
|
|
(ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:SI 2 "or_operand" "rI,N")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
bis %r1,%2,%0
|
|
|
|
|
ornot %r1,%N2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "iordi3"
|
1993-12-27 12:28:38 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
|
1994-05-27 22:38:54 +02:00
|
|
|
|
(match_operand:DI 2 "or_operand" "rI,N")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1993-12-27 12:28:38 +01:00
|
|
|
|
"@
|
|
|
|
|
bis %r1,%2,%0
|
|
|
|
|
ornot %r1,%N2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
(define_insn "*one_cmplsi_internal"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
|
(not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
|
|
|
|
|
""
|
|
|
|
|
"ornot $31,%1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "one_cmpldi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
|
|
|
|
|
""
|
|
|
|
|
"ornot $31,%1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "*iornot<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(ior:I48MODE
|
|
|
|
|
(not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"ornot %r2,%1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
(define_insn "*xorsi_internal"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
|
|
(xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:SI 2 "or_operand" "rI,N")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
xor %r1,%2,%0
|
|
|
|
|
eqv %r1,%N2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "xordi3"
|
1994-05-27 22:38:54 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
|
|
|
|
|
(match_operand:DI 2 "or_operand" "rI,N")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1994-05-27 22:38:54 +02:00
|
|
|
|
"@
|
|
|
|
|
xor %r1,%2,%0
|
|
|
|
|
eqv %r1,%N2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-11 17:44:54 +02:00
|
|
|
|
(define_insn "*xornot<mode>3"
|
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
|
|
|
|
(not:I48MODE (xor:I48MODE
|
|
|
|
|
(match_operand:I48MODE 1 "register_operand" "%rJ")
|
|
|
|
|
(match_operand:I48MODE 2 "register_operand" "rI"))))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"eqv %r1,%2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
[multiple changes]
2003-02-01 Richard Henderson <rth@redhat.com>
* optabs.c (expand_unop): Use word_mode for outmode of bit scaners.
* libgcc2.c (__ffsdi2, __clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2): Change
return type to Wtype.
* libgcc-std.ver (GCC_3.4): Fix inheritance.
* config/i386/i386.md (ffssi2): Use nonimmediate_operand for
expander input constraint.
2003-02-01 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de>
* optabs.h (optab_index): Add OTI_clz, OTI_ctz, OTI_popcount and
OTI_parity.
(clz_optab, ctz_optab, popcount_optab, parity_optab): New.
* optabs.c (widen_clz, expand_parity): New.
(expand_unop): Handle clz and parity. Hardcode SImode as outmode
for libcalls to clz, ctz, popcount, and parity.
(init_optabs): Init clz_optab, ctz_optab, popcount_optab and
parity_optab, and set up libfunc handlers.
* libgcc2.c (__clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2,
__popcount_tab): New.
* libgcc2.h: Declare them.
* libgcc-std.ver (GCC_3.4): Add new functions from libgcc2.c.
* genopinit.c (optabs): Add clz_optab, ctz_optab, popcount_optab
and parity_optab.
* builtin-types.def (BT_FN_INT_LONG, BT_FN_INT_LONGLONG): New.
* builtins.def (BUILT_IN_CLZ, BUILT_IN_CTZ, BUILT_IN_POPCOUNT,
BUILT_IN_PARITY, BUILT_IN_FFSL, BUILT_IN_CLZL, BUILT_IN_CTZL,
BUILT_IN_POPCOUNTL, BUILT_IN_PARITYL, BUILT_IN_FFSLL,
BUILT_IN_CLZLL, BUILT_IN_CTZLL, BUILT_IN_POPCOUNTLL,
BUILT_IN_PARITYLL): New.
* builtins.c (expand_builtin_unop): Rename from expand_builtin_ffs
and add optab argument.
(expand_builtin): Expand BUILT_IN_{FFS,CLZ,POPCOUNT,PARITY}*.
* tree.def (CLZ_EXPR, CTZ_EXPR, POPCOUNT_EXPR, PARITY_EXPR): New.
* expr.c (expand_expr): Handle them.
* fold-const.c (tree_expr_nonnegative_p): Likewise.
* rtl.def (CLZ, CTZ, POPCOUNT, PARITY): New.
* reload1.c (eliminate_regs): Handle them.
(elimination_effects): Likewise.
* function.c (instantiate_virtual_regs_1): Likewise
* genattrtab.c (check_attr_value): Likewise.
* simplify-rtx.c (simplify_unary_operation): Likewise.
* c-common.c (c_common_truthvalue_conversion): Handle POPCOUNT_EXPR.
* combine.c (combine_simplify_rtx): Handle POPCOUNT and PARITY.
(nonzero_bits): Handle CLZ, CTZ, POPCOUNT and PARITY.
* config/alpha/alpha.md (clzdi2, ctzdi2, popcountdi2): New.
* config/arm/arm.c (arm_init_builtins): Rename __builtin_clz to
__builtin_arm_clz.
* Makefile.in (LIB2FUNCS_1, LIB2FUNCS_2): Move...
* mklibgcc.in (lib2funcs): ...here and merge. Add new members.
* doc/extend.texi (Other Builtins): Add new builtins.
* doc/md.texi (Standard Names): Add new patterns.
From-SVN: r62252
2003-02-01 20:00:02 +01:00
|
|
|
|
;; Handle FFS and related insns iff we support CIX.
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "ffsdi2"
|
|
|
|
|
[(set (match_dup 2)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(ctz:DI (match_operand:DI 1 "register_operand")))
|
1997-11-02 22:19:36 +01:00
|
|
|
|
(set (match_dup 3)
|
|
|
|
|
(plus:DI (match_dup 2) (const_int 1)))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1997-11-02 22:19:36 +01:00
|
|
|
|
(if_then_else:DI (eq (match_dup 1) (const_int 0))
|
|
|
|
|
(const_int 0) (match_dup 3)))]
|
|
|
|
|
"TARGET_CIX"
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_reg_rtx (DImode);
|
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
[multiple changes]
2003-02-01 Richard Henderson <rth@redhat.com>
* optabs.c (expand_unop): Use word_mode for outmode of bit scaners.
* libgcc2.c (__ffsdi2, __clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2): Change
return type to Wtype.
* libgcc-std.ver (GCC_3.4): Fix inheritance.
* config/i386/i386.md (ffssi2): Use nonimmediate_operand for
expander input constraint.
2003-02-01 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de>
* optabs.h (optab_index): Add OTI_clz, OTI_ctz, OTI_popcount and
OTI_parity.
(clz_optab, ctz_optab, popcount_optab, parity_optab): New.
* optabs.c (widen_clz, expand_parity): New.
(expand_unop): Handle clz and parity. Hardcode SImode as outmode
for libcalls to clz, ctz, popcount, and parity.
(init_optabs): Init clz_optab, ctz_optab, popcount_optab and
parity_optab, and set up libfunc handlers.
* libgcc2.c (__clzsi2, __clzdi2, __ctzsi2, __ctzdi2,
__popcountsi2, __popcountdi2, __paritysi2 __paritydi2,
__popcount_tab): New.
* libgcc2.h: Declare them.
* libgcc-std.ver (GCC_3.4): Add new functions from libgcc2.c.
* genopinit.c (optabs): Add clz_optab, ctz_optab, popcount_optab
and parity_optab.
* builtin-types.def (BT_FN_INT_LONG, BT_FN_INT_LONGLONG): New.
* builtins.def (BUILT_IN_CLZ, BUILT_IN_CTZ, BUILT_IN_POPCOUNT,
BUILT_IN_PARITY, BUILT_IN_FFSL, BUILT_IN_CLZL, BUILT_IN_CTZL,
BUILT_IN_POPCOUNTL, BUILT_IN_PARITYL, BUILT_IN_FFSLL,
BUILT_IN_CLZLL, BUILT_IN_CTZLL, BUILT_IN_POPCOUNTLL,
BUILT_IN_PARITYLL): New.
* builtins.c (expand_builtin_unop): Rename from expand_builtin_ffs
and add optab argument.
(expand_builtin): Expand BUILT_IN_{FFS,CLZ,POPCOUNT,PARITY}*.
* tree.def (CLZ_EXPR, CTZ_EXPR, POPCOUNT_EXPR, PARITY_EXPR): New.
* expr.c (expand_expr): Handle them.
* fold-const.c (tree_expr_nonnegative_p): Likewise.
* rtl.def (CLZ, CTZ, POPCOUNT, PARITY): New.
* reload1.c (eliminate_regs): Handle them.
(elimination_effects): Likewise.
* function.c (instantiate_virtual_regs_1): Likewise
* genattrtab.c (check_attr_value): Likewise.
* simplify-rtx.c (simplify_unary_operation): Likewise.
* c-common.c (c_common_truthvalue_conversion): Handle POPCOUNT_EXPR.
* combine.c (combine_simplify_rtx): Handle POPCOUNT and PARITY.
(nonzero_bits): Handle CLZ, CTZ, POPCOUNT and PARITY.
* config/alpha/alpha.md (clzdi2, ctzdi2, popcountdi2): New.
* config/arm/arm.c (arm_init_builtins): Rename __builtin_clz to
__builtin_arm_clz.
* Makefile.in (LIB2FUNCS_1, LIB2FUNCS_2): Move...
* mklibgcc.in (lib2funcs): ...here and merge. Add new members.
* doc/extend.texi (Other Builtins): Add new builtins.
* doc/md.texi (Standard Names): Add new patterns.
From-SVN: r62252
2003-02-01 20:00:02 +01:00
|
|
|
|
(define_insn "clzdi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(clz:DI (match_operand:DI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_CIX"
|
|
|
|
|
"ctlz %1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_insn "ctzdi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ctz:DI (match_operand:DI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_CIX"
|
|
|
|
|
"cttz %1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_insn "popcountdi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(popcount:DI (match_operand:DI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_CIX"
|
|
|
|
|
"ctpop %1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
2007-02-12 19:53:22 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "bswapsi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(bswap:SI (match_operand:SI 1 "register_operand")))]
|
2007-02-12 19:53:22 +01:00
|
|
|
|
"!optimize_size"
|
|
|
|
|
{
|
|
|
|
|
rtx t0, t1;
|
|
|
|
|
|
|
|
|
|
t0 = gen_reg_rtx (DImode);
|
|
|
|
|
t1 = gen_reg_rtx (DImode);
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7)));
|
2007-02-12 19:53:22 +01:00
|
|
|
|
emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
|
|
|
|
|
GEN_INT (24)));
|
|
|
|
|
emit_insn (gen_iordi3 (t1, t0, t1));
|
|
|
|
|
emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
|
|
|
|
|
emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
|
|
|
|
|
emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
|
|
|
|
|
gen_lowpart (SImode, t1)));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "bswapdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(bswap:DI (match_operand:DI 1 "register_operand")))]
|
2007-02-12 19:53:22 +01:00
|
|
|
|
"!optimize_size"
|
|
|
|
|
{
|
|
|
|
|
rtx t0, t1;
|
|
|
|
|
|
|
|
|
|
t0 = gen_reg_rtx (DImode);
|
|
|
|
|
t1 = gen_reg_rtx (DImode);
|
|
|
|
|
|
|
|
|
|
/* This method of shifting and masking is not specific to Alpha, but
|
|
|
|
|
is only profitable on Alpha because of our handy byte zap insn. */
|
|
|
|
|
|
|
|
|
|
emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
|
|
|
|
|
emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
|
|
|
|
|
emit_insn (gen_iordi3 (t1, t0, t1));
|
|
|
|
|
|
|
|
|
|
emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
|
|
|
|
|
emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
|
|
|
|
|
emit_insn (gen_iordi3 (t1, t0, t1));
|
|
|
|
|
|
|
|
|
|
emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
|
|
|
|
|
emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
|
|
|
|
|
emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
|
|
|
|
|
emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
|
|
|
|
|
emit_insn (gen_iordi3 (operands[0], t0, t1));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; Next come the shifts and the various extract and insert operations.
|
|
|
|
|
|
|
|
|
|
(define_insn "ashldi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
|
1998-06-29 23:40:49 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
switch (which_alternative)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
if (operands[2] == const1_rtx)
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "addq %r1,%r1,%0";
|
1992-10-24 15:33:28 +01:00
|
|
|
|
else
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "s%P2addq %r1,0,%0";
|
1992-10-24 15:33:28 +01:00
|
|
|
|
case 1:
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "sll %r1,%2,%0";
|
1998-06-26 08:41:04 +02:00
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
}
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "iadd,shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2002-02-27 02:52:18 +01:00
|
|
|
|
(define_insn "*ashldi_se"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand" "P"))
|
|
|
|
|
0)))]
|
2018-01-14 16:45:38 +01:00
|
|
|
|
"IN_RANGE (INTVAL (operands[2]), 1, 3)"
|
2002-02-27 02:52:18 +01:00
|
|
|
|
{
|
|
|
|
|
if (operands[2] == const1_rtx)
|
|
|
|
|
return "addl %r1,%r1,%0";
|
|
|
|
|
else
|
|
|
|
|
return "s%P2addl %r1,0,%0";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "iadd")])
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "lshrdi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
1998-06-29 23:40:49 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"srl %r1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "ashrdi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
1998-06-29 23:40:49 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"sra %r1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_insn "extendqi<mode>2"
|
|
|
|
|
[(set (match_operand:I24MODE 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:I24MODE
|
|
|
|
|
(match_operand:QI 1 "register_operand" "r")))]
|
1997-11-02 22:19:36 +01:00
|
|
|
|
"TARGET_BWX"
|
1997-07-19 23:59:58 +02:00
|
|
|
|
"sextb %1,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_expand "extendqidi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
2015-05-15 07:04:32 +02:00
|
|
|
|
(sign_extend:DI (match_operand:QI 1 "general_operand")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
1997-11-02 22:19:36 +01:00
|
|
|
|
if (TARGET_BWX)
|
2011-03-25 01:34:46 +01:00
|
|
|
|
operands[1] = force_reg (QImode, operands[1]);
|
|
|
|
|
else
|
1996-11-12 23:53:16 +01:00
|
|
|
|
{
|
2011-03-25 01:34:46 +01:00
|
|
|
|
rtx x, t1, t2, i56;
|
|
|
|
|
|
|
|
|
|
if (unaligned_memory_operand (operands[1], QImode))
|
|
|
|
|
{
|
|
|
|
|
x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
|
|
|
|
|
alpha_set_memflags (x, operands[1]);
|
|
|
|
|
emit_insn (x);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
t1 = gen_reg_rtx (DImode);
|
|
|
|
|
t2 = gen_reg_rtx (DImode);
|
|
|
|
|
i56 = GEN_INT (56);
|
|
|
|
|
|
|
|
|
|
x = gen_lowpart (DImode, force_reg (QImode, operands[1]));
|
|
|
|
|
emit_move_insn (t1, x);
|
|
|
|
|
emit_insn (gen_ashldi3 (t2, t1, i56));
|
|
|
|
|
emit_insn (gen_ashrdi3 (operands[0], t2, i56));
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
DONE;
|
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2011-03-25 01:34:46 +01:00
|
|
|
|
(define_insn "*extendqidi2_bwx"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_BWX"
|
|
|
|
|
"sextb %1,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
|
2011-03-25 01:34:46 +01:00
|
|
|
|
(define_insn "extendhisi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_BWX"
|
|
|
|
|
"sextw %1,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "extendhidi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
2015-05-15 07:04:32 +02:00
|
|
|
|
(sign_extend:DI (match_operand:HI 1 "general_operand")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
1997-11-02 22:19:36 +01:00
|
|
|
|
if (TARGET_BWX)
|
2011-03-25 01:34:46 +01:00
|
|
|
|
operands[1] = force_reg (HImode, operands[1]);
|
|
|
|
|
else
|
1996-11-12 23:53:16 +01:00
|
|
|
|
{
|
2011-03-25 01:34:46 +01:00
|
|
|
|
rtx x, t1, t2, i48;
|
|
|
|
|
|
|
|
|
|
if (unaligned_memory_operand (operands[1], HImode))
|
|
|
|
|
{
|
|
|
|
|
x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
|
|
|
|
|
alpha_set_memflags (x, operands[1]);
|
|
|
|
|
emit_insn (x);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
t1 = gen_reg_rtx (DImode);
|
|
|
|
|
t2 = gen_reg_rtx (DImode);
|
|
|
|
|
i48 = GEN_INT (48);
|
|
|
|
|
|
|
|
|
|
x = gen_lowpart (DImode, force_reg (HImode, operands[1]));
|
|
|
|
|
emit_move_insn (t1, x);
|
|
|
|
|
emit_insn (gen_ashldi3 (t2, t1, i48));
|
|
|
|
|
emit_insn (gen_ashrdi3 (operands[0], t2, i48));
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
DONE;
|
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2011-03-25 01:34:46 +01:00
|
|
|
|
(define_insn "*extendhidi2_bwx"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
|
|
|
|
|
"TARGET_BWX"
|
|
|
|
|
"sextw %1,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
;; Here's how we sign extend an unaligned byte and halfword. Doing this
|
|
|
|
|
;; as a pattern saves one instruction. The code is similar to that for
|
|
|
|
|
;; the unaligned loads (see below).
|
|
|
|
|
;;
|
2007-04-20 21:35:55 +02:00
|
|
|
|
;; Operand 1 is the address, operand 0 is the result.
|
2001-09-11 10:52:39 +02:00
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "unaligned_extendqidi"
|
2007-04-20 21:35:55 +02:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(set (match_dup 4)
|
|
|
|
|
(ashift:DI (match_dup 3)
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(minus:DI (const_int 64)
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(and:DI (match_dup 2) (const_int 7))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int 3)))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:QI 0 "register_operand")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashiftrt:DI (match_dup 4) (const_int 56)))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
operands[0] = gen_lowpart (DImode, operands[0]);
|
2007-04-20 21:35:55 +02:00
|
|
|
|
operands[2] = get_unaligned_offset (operands[1], 1);
|
2001-09-11 10:52:39 +02:00
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
|
|
operands[4] = gen_reg_rtx (DImode);
|
|
|
|
|
})
|
|
|
|
|
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(define_expand "unaligned_extendhidi"
|
2007-04-20 21:35:55 +02:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(set (match_dup 4)
|
|
|
|
|
(ashift:DI (match_dup 3)
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(minus:DI (const_int 64)
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(and:DI (match_dup 2) (const_int 7))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int 3)))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:HI 0 "register_operand")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashiftrt:DI (match_dup 4) (const_int 48)))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
operands[0] = gen_lowpart (DImode, operands[0]);
|
2007-04-20 21:35:55 +02:00
|
|
|
|
operands[2] = get_unaligned_offset (operands[1], 2);
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
|
|
operands[4] = gen_reg_rtx (DImode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*extxl_const"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:DI 2 "mode_width_operand" "n")
|
|
|
|
|
(match_operand:DI 3 "mul8_operand" "I")))]
|
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"ext%M2l %r1,%s3,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "extxl"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(zero_extract:DI
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:DI 2 "mode_width_operand" "n")
|
|
|
|
|
(ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"ext%M2l %r1,%3,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2002-09-18 01:10:04 +02:00
|
|
|
|
;; Combine has some strange notion of preserving existing undefined behavior
|
2001-07-15 09:17:29 +02:00
|
|
|
|
;; in shifts larger than a word size. So capture these patterns that it
|
1998-08-10 03:23:59 +02:00
|
|
|
|
;; should have turned into zero_extracts.
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "*extxl_1"
|
1998-08-10 03:23:59 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1999-10-01 02:45:07 +02:00
|
|
|
|
(and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3)))
|
1998-08-10 03:23:59 +02:00
|
|
|
|
(match_operand:DI 3 "mode_mask_operand" "n")))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"ext%U3l %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "*extql_2"
|
1998-08-10 03:23:59 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"extql %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "extqh"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ashift:DI
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand" "rJ")
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(minus:DI (const_int 64)
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI
|
|
|
|
|
(and:DI
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int 7))
|
|
|
|
|
(const_int 3)))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"extqh %r1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "extwh"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ashift:DI
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(const_int 65535))
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(minus:DI (const_int 64)
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI
|
|
|
|
|
(and:DI
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int 7))
|
|
|
|
|
(const_int 3)))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
"extwh %r1,%2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "extlh"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ashift:DI
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(const_int 2147483647))
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(minus:DI (const_int 64)
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI
|
|
|
|
|
(and:DI
|
1999-07-01 22:54:41 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int 7))
|
|
|
|
|
(const_int 3)))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
"extlh %r1,%2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "shift")])
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
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1992-10-24 15:33:28 +01:00
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;; This converts an extXl into an extXh with an appropriate adjustment
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;; to the address calculation.
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(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
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;;(define_split
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2012-10-14 14:50:45 +02:00
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;; [(set (match_operand:DI 0 "register_operand")
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;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand")
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;; (match_operand:DI 2 "mode_width_operand")
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;; (ashift:DI (match_operand:DI 3)
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(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
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;; (const_int 3)))
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2012-10-14 14:50:45 +02:00
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;; (match_operand:DI 4 "const_int_operand")))
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;; (clobber (match_operand:DI 5 "register_operand"))]
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(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
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;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
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;; [(set (match_dup 5) (match_dup 6))
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;; (set (match_dup 0)
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;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
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;; (ashift:DI (plus:DI (match_dup 5)
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;; (match_dup 7))
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;; (const_int 3)))
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;; (match_dup 4)))]
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;; "
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;;{
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rtl.h (plus_constant, [...]): Merge into a single plus_constant function.
gcc/
* rtl.h (plus_constant, plus_constant_mode): Merge into a single
plus_constant function.
* explow.c (plus_constant, plus_constant_mode): Likewise. Assert
that the mode is sensible.
(use_anchored_address, round_push, allocate_dynamic_stack_space)
(probe_stack_range, anti_adjust_stack_and_probe): Update calls to
plus_constant.
* alias.c (canon_rtx): Likewise.
(init_alias_analysis): Likewise.
* builtins.c (expand_builtin_return_addr)
(expand_builtin_setjmp_setup, expand_builtin_longjmp)
(expand_builtin_nonlocal_goto, expand_builtin_update_setjmp_buf)
(expand_builtin_apply_args_1, expand_builtin_apply, expand_movstr)
(expand_builtin_stpcpy): Likewise.
* calls.c (save_fixed_argument_area, restore_fixed_argument_area)
(compute_argument_addresses, internal_arg_pointer_based_exp)
(expand_call, emit_library_call_value_1): Likewise.
* cfgexpand.c (expand_one_stack_var_at, expand_debug_expr): Likewise.
* combine-stack-adj.c (try_apply_stack_adjustment): Likewise.
* combine.c (combine_simplify_rtx, force_to_mode): Likewise.
* cse.c (insert_const_anchor, find_reg_offset_for_const)
(use_related_value, fold_rtx): Likewise.
* cselib.c (cselib_subst_to_values): Likewise.
* dse.c (record_store, check_mem_read_rtx): Likewise.
* dwarf2out.c (rtl_for_decl_location, gen_variable_die): Likewise.
* emit-rtl.c (adjust_address_1): Likewise.
* except.c (sjlj_emit_function_enter)
(expand_builtin_extract_return_addr)
(expand_builtin_frob_return_addr): Likewise.
* expmed.c (expand_divmod): Likewise.
* expr.c (move_by_pieces, store_by_pieces, store_by_pieces_1)
(emit_move_resolve_push, push_block, emit_push_insn, store_expr)
(expand_expr_addr_expr_1, expand_expr_real_1): Likewise.
* function.c (assign_stack_local_1)
(instantiate_virtual_regs_in_rtx): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* reload.c (find_reloads_address, form_sum)
(find_reloads_subreg_address): Likewise.
* reload1.c (init_reload, eliminate_regs_1)
(eliminate_regs_in_insn): Likewise.
* simplify-rtx.c (simplify_unary_operation_1)
(simplify_binary_operation_1, simplify_plus_minus): Likewise.
* var-tracking.c (compute_cfa_pointer, prepare_call_arguments)
(vt_add_function_parameter): Likewise.
* config/alpha/alpha.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/vms.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address_1)
(get_unaligned_address, alpha_expand_unaligned_load)
(alpha_expand_unaligned_store, alpha_expand_unaligned_load_words)
(alpha_expand_unaligned_store_words, alpha_expand_block_clear)
(alpha_expand_builtin_establish_vms_condition_handler)
(alpha_setup_incoming_varargs, emit_frame_store_1)
(alpha_expand_prologue, alpha_expand_epilogue)
(alpha_use_linkage): Likewise.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c (arm_trampoline_init, legitimize_pic_address)
(arm_load_pic_register, arm_pic_static_addr, arm_legitimize_address)
(thumb_legitimize_address, arm_gen_load_multiple_1)
(arm_gen_store_multiple_1, arm_gen_multiple_op, gen_ldm_seq)
(gen_stm_seq, gen_const_stm_seq, arm_block_move_unaligned_straight)
(arm_block_move_unaligned_loop, arm_gen_movmemqi, arm_reload_in_hi)
(arm_reload_out_hi, arm_reorg, vfp_emit_fstmd, emit_multi_reg_push)
(emit_sfm, thumb_set_frame_pointer, arm_expand_prologue)
(thumb1_emit_multi_reg_push, thumb1_expand_prologue)
(thumb_expand_movmemqi, arm_set_return_address)
(thumb_set_return_address): Likewise.
* config/arm/arm.md: Likewise.
* config/avr/avr.c (avr_incoming_return_addr_rtx)
(avr_prologue_setup_frame, expand_epilogue)
(avr_const_address_lo16): Likewise.
* config/bfin/bfin.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/bfin/bfin.c (setup_incoming_varargs, bfin_load_pic_reg)
(bfin_expand_prologue, bfin_trampoline_init, bfin_expand_call)
(bfin_output_mi_thunk): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline)
(c6x_output_mi_thunk): Likewise.
* config/cr16/cr16.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
* config/cris/cris.c (cris_return_addr_rtx, cris_split_movdx)
(cris_expand_prologue, cris_expand_epilogue, cris_gen_movem_load)
(cris_emit_movem_store, cris_trampoline_init): Likewise.
* config/cris/cris.md: Likewise.
* config/darwin.c (machopic_indirect_data_reference)
(machopic_legitimize_pic_address): Likewise.
* config/epiphany/epiphany.c (epiphany_emit_save_restore)
(epiphany_expand_prologue, epiphany_expand_epilogue)
(epiphany_trampoline_init): Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/fr30/fr30.c (fr30_move_double): Likewise.
* config/frv/frv.c (frv_dwarf_store, frv_expand_prologue)
(frv_expand_block_move, frv_expand_block_clear, frv_return_addr_rtx)
(frv_index_memory, unspec_got_name, frv_find_base_term)
(frv_output_dwarf_dtprel): Likewise.
* config/h8300/h8300.c (h8300_push_pop, h8300_return_addr_rtx)
(h8300_swap_into_er6, h8300_swap_out_of_er6): Likewise.
* config/i386/i386.h (RETURN_ADDR_RTX): Likewise.
* config/i386/i386.c (setup_incoming_varargs_64)
(setup_incoming_varargs_ms_64, choose_baseaddr)
(ix86_emit_save_reg_using_mov, ix86_adjust_stack_and_probe)
(ix86_emit_probe_stack_range, ix86_expand_prologue)
(ix86_emit_restore_reg_using_pop, ix86_emit_leave)
(ix86_expand_epilogue, legitimize_pic_address, ix86_legitimize_address)
(ix86_split_long_move, ix86_expand_movmem, ix86_expand_setmem)
(ix86_static_chain, ix86_trampoline_init, x86_this_parameter)
(x86_output_mi_thunk): Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (ia64_expand_load_address)
(ia64_expand_tls_address, ia64_expand_move, ia64_split_tmode)
(do_spill, ia64_trampoline_init): Likewise.
* config/iq2000/iq2000.c (iq2000_va_start)
(iq2000_emit_frame_related_store, iq2000_expand_prologue)
(iq2000_expand_eh_return, iq2000_setup_incoming_varargs)
(iq2000_print_operand, iq2000_legitimize_address): Likewise.
* config/lm32/lm32.c (lm32_setup_incoming_varargs): Likewise.
* config/m32c/m32c.c (m32c_return_addr_rtx)
(m32c_expand_insv): Likewise.
* config/m32r/m32r.c (m32r_setup_incoming_varargs)
(m32r_legitimize_pic_address, m32r_print_operand)
(m32r_print_operand_address): Likewise.
* config/m68k/linux.h (FINALIZE_TRAMPOLINE): Likewise.
* config/m68k/m68k.h (RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/m68k/m68k.c (m68k_emit_movem, m68k_expand_prologue)
(m68k_expand_epilogue, legitimize_pic_address)
(m68k_output_mi_thunk): Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c (mcore_expand_prolog): Likewise.
(mcore_expand_epilog): Likewise.
* config/mcore/mcore.md: Likewise.
* config/mep/mep.c (mep_allocate_initial_value)
(mep_expand_prologue, mep_expand_epilogue): Likewise.
* config/microblaze/microblaze.c (double_memory_operand)
(microblaze_block_move_loop): Likewise.
* config/mips/mips.c (mips_strip_unspec_address, mips_add_offset)
(mips_setup_incoming_varargs, mips_va_start, mips_block_move_loop)
(mips_print_operand, mips16e_save_restore_reg, mips_save_restore_reg)
(mips_expand_prologue, mips_epilogue_set_cfa)
(mips_expand_epilogue): Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c (mmix_dynamic_chain_address, mmix_return_addr_rtx)
(mmix_expand_prologue, mmix_expand_epilogue): Likewise.
* config/mn10300/mn10300.c (mn10300_gen_multiple_store)
(mn10300_builtin_saveregs, mn10300_trampoline_init): Likewise.
* config/moxie/moxie.h (INCOMING_RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/moxie/moxie.c (moxie_static_chain): Likewise.
* config/pa/pa.c (legitimize_pic_address, hppa_legitimize_address)
(store_reg, set_reg_plus_d, pa_expand_prologue, load_reg)
(pa_return_addr_rtx, hppa_builtin_saveregs)
(pa_trampoline_init): Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c (pdp11_expand_epilogue): Likewise.
* config/picochip/picochip.c (picochip_static_chain): Likewise.
* config/rs6000/rs6000.h (RS6000_SAVE_TOC): Likewise.
* config/rs6000/rs6000.c (rs6000_legitimize_address)
(setup_incoming_varargs, print_operand, rs6000_return_addr)
(rs6000_emit_eh_reg_restore, rs6000_emit_probe_stack_range)
(rs6000_emit_epilogue)
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rx/rx.c (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
* config/s390/s390.h (INITIAL_FRAME_ADDRESS_RTX): Likewise.
(DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/s390/s390.c (s390_decompose_address, legitimize_pic_address)
(s390_delegitimize_address, print_operand, annotate_constant_pool_refs)
(replace_constant_pool_ref, s390_return_addr_rtx, s390_back_chain_rtx)
(save_fpr, restore_fpr, save_gprs, restore_gprs, s390_emit_prologue)
(s390_emit_epilogue, s390_function_profiler): Likewise.
* config/s390/s390.md: Likewise.
* config/score/score.c (score_add_offset, score_prologue): Likewise.
* config/sh/sh.c (expand_block_move, push_regs, sh_builtin_saveregs)
(sh_output_mi_thunk): Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/sparc.h (DYNAMIC_CHAIN_ADDRESS, FRAME_ADDR_RTX)
(RETURN_ADDR_RTX, INCOMING_RETURN_ADDR_RTX): Likewise.
* config/sparc/sparc.c (sparc_legitimize_pic_address)
(sparc_emit_probe_stack_range, emit_save_or_restore_regs)
(emit_window_save, sparc_flat_expand_prologue, sparc_struct_value_rtx)
(emit_and_preserve): Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/spu/spu.c (spu_expand_insv, spu_machine_dependent_reorg)
(spu_setup_incoming_varargs, ea_load_store_inline)
(spu_expand_load): Likewise.
* config/stormy16/stormy16.c (xstormy16_expand_prologue)
(combine_bnp): Likewise.
* config/tilegx/tilegx.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilegx/tilegx.c (tilegx_setup_incoming_varargs)
(tilegx_expand_unaligned_load, tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilepro/tilepro.c (tilepro_setup_incoming_varargs)
(tilepro_expand_unaligned_load, tilepro_trampoline_init): Likewise.
* config/v850/v850.c (expand_prologue, expand_epilogue): Likewise.
* config/v850/v850.md: Likewise.
* config/vax/elf.h (EH_RETURN_STACKADJ_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/vax/vax.h (DYNAMIC_CHAIN_ADDRESS, RETURN_ADDR_RTX): Likewise.
* config/vax/vax.c (vax_add_reg_cfa_offset, vax_expand_prologue)
(print_operand_address, vax_trampoline_init): Likewise.
* config/xtensa/xtensa.c (xtensa_expand_prologue, xtensa_return_addr)
(xtensa_function_value_regno_p): Likewise.
From-SVN: r187199
2012-05-05 19:41:49 +02:00
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;; operands[6] = plus_constant (DImode, operands[3],
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(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
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;; INTVAL (operands[2]) / BITS_PER_UNIT);
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;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
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;;}")
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2001-07-15 09:17:29 +02:00
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alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
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(define_insn "ins<modesuffix>l_const"
|
1992-10-24 15:33:28 +01:00
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[(set (match_operand:DI 0 "register_operand" "=r")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
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(ashift:DI (zero_extend:DI
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(match_operand:I124MODE 1 "register_operand" "r"))
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1992-10-24 15:33:28 +01:00
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(match_operand:DI 2 "mul8_operand" "I")))]
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""
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
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"ins<modesuffix>l %1,%s2,%0"
|
2001-09-11 10:52:39 +02:00
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[(set_attr "type" "shift")])
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|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "ins<modesuffix>l"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(ashift:DI (zero_extend:DI
|
|
|
|
|
(match_operand:I124MODE 1 "register_operand" "r"))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
"ins<modesuffix>l %1,%2,%0"
|
2001-09-11 10:52:39 +02:00
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "insql"
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "register_operand" "r")
|
|
|
|
|
(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3))))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
"insql %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
1998-06-05 05:10:46 +02:00
|
|
|
|
;; Combine has this sometimes habit of moving the and outside of the
|
|
|
|
|
;; shift, making life more interesting.
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*insxl"
|
1998-06-05 05:10:46 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
|
|
|
|
|
(match_operand:DI 2 "mul8_operand" "I"))
|
2015-05-11 09:21:19 +02:00
|
|
|
|
(match_operand:DI 3 "const_int_operand" "i")))]
|
|
|
|
|
"((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
|
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|
|
|
|
|
|| ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
|
alpha.c (alpha_cpu_name, [...]): Add the `const' keyword.
* alpha.c (alpha_cpu_name, alpha_cpu_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string, alpha_mlat_string,
current_function_file): Add the `const' keyword.
(normal_memory_operand): Mark parameter `mode' with
ATTRIBUTE_UNUSED.
(alpha_expand_unaligned_load): Add a default case to a switch.
* alpha.h (alpha_cpu_string, alpha_fprm_string, alpha_fptm_string,
alpha_tp_string, alpha_mlat_string): Add the `const' keyword.
(normal_memory_operand): Add prototype.
* alpha.md: Cast an expression to `unsigned HOST_WIDE_INT' when
comparing against one.
From-SVN: r25532
1999-03-02 08:21:47 +01:00
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|
2015-05-11 09:21:19 +02:00
|
|
|
|
|| ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
|
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))"
|
1998-06-05 05:10:46 +02:00
|
|
|
|
{
|
|
|
|
|
if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
|
alpha.c (alpha_cpu_name, [...]): Add the `const' keyword.
* alpha.c (alpha_cpu_name, alpha_cpu_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string, alpha_mlat_string,
current_function_file): Add the `const' keyword.
(normal_memory_operand): Mark parameter `mode' with
ATTRIBUTE_UNUSED.
(alpha_expand_unaligned_load): Add a default case to a switch.
* alpha.h (alpha_cpu_string, alpha_fprm_string, alpha_fptm_string,
alpha_tp_string, alpha_mlat_string): Add the `const' keyword.
(normal_memory_operand): Add prototype.
* alpha.md: Cast an expression to `unsigned HOST_WIDE_INT' when
comparing against one.
From-SVN: r25532
1999-03-02 08:21:47 +01:00
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "insbl %1,%s2,%0";
|
1998-06-05 05:10:46 +02:00
|
|
|
|
if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
|
alpha.c (alpha_cpu_name, [...]): Add the `const' keyword.
* alpha.c (alpha_cpu_name, alpha_cpu_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string, alpha_mlat_string,
current_function_file): Add the `const' keyword.
(normal_memory_operand): Mark parameter `mode' with
ATTRIBUTE_UNUSED.
(alpha_expand_unaligned_load): Add a default case to a switch.
* alpha.h (alpha_cpu_string, alpha_fprm_string, alpha_fptm_string,
alpha_tp_string, alpha_mlat_string): Add the `const' keyword.
(normal_memory_operand): Add prototype.
* alpha.md: Cast an expression to `unsigned HOST_WIDE_INT' when
comparing against one.
From-SVN: r25532
1999-03-02 08:21:47 +01:00
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "inswl %1,%s2,%0";
|
1998-06-05 05:10:46 +02:00
|
|
|
|
if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
|
alpha.c (alpha_cpu_name, [...]): Add the `const' keyword.
* alpha.c (alpha_cpu_name, alpha_cpu_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string, alpha_mlat_string,
current_function_file): Add the `const' keyword.
(normal_memory_operand): Mark parameter `mode' with
ATTRIBUTE_UNUSED.
(alpha_expand_unaligned_load): Add a default case to a switch.
* alpha.h (alpha_cpu_string, alpha_fprm_string, alpha_fptm_string,
alpha_tp_string, alpha_mlat_string): Add the `const' keyword.
(normal_memory_operand): Add prototype.
* alpha.md: Cast an expression to `unsigned HOST_WIDE_INT' when
comparing against one.
From-SVN: r25532
1999-03-02 08:21:47 +01:00
|
|
|
|
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "insll %1,%s2,%0";
|
2015-05-11 09:21:19 +02:00
|
|
|
|
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2001-07-15 17:38:52 +02:00
|
|
|
|
}
|
1998-06-05 05:10:46 +02:00
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; We do not include the insXh insns because they are complex to express
|
|
|
|
|
;; and it does not appear that we would ever want to generate them.
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
;;
|
|
|
|
|
;; Since we need them for block moves, though, cop out and use unspec.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
(define_insn "insxh"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1999-10-01 02:45:07 +02:00
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
|
|
|
|
(match_operand:DI 2 "mode_width_operand" "n")
|
2001-07-15 08:25:01 +02:00
|
|
|
|
(match_operand:DI 3 "reg_or_8bit_operand" "rI")]
|
|
|
|
|
UNSPEC_INSXH))]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
"ins%M2h %1,%3,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_insn "mskxl"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1994-03-04 00:11:36 +01:00
|
|
|
|
(and:DI (not:DI (ashift:DI
|
|
|
|
|
(match_operand:DI 2 "mode_mask_operand" "n")
|
|
|
|
|
(ashift:DI
|
|
|
|
|
(match_operand:DI 3 "reg_or_8bit_operand" "rI")
|
|
|
|
|
(const_int 3))))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"msk%U2l %r1,%3,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
;; We do not include the mskXh insns because it does not appear we would
|
|
|
|
|
;; ever generate one.
|
|
|
|
|
;;
|
|
|
|
|
;; Again, we do for block moves and we use unspec again.
|
|
|
|
|
|
|
|
|
|
(define_insn "mskxh"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1999-10-01 02:45:07 +02:00
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
|
|
|
|
(match_operand:DI 2 "mode_width_operand" "n")
|
2001-07-15 08:25:01 +02:00
|
|
|
|
(match_operand:DI 3 "reg_or_8bit_operand" "rI")]
|
|
|
|
|
UNSPEC_MSKXH))]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
"msk%M2h %1,%3,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
;; Prefer AND + NE over LSHIFTRT + AND.
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*ze_and_ne"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand 2 "const_int_operand" "I")))]
|
|
|
|
|
"(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
|
|
|
|
|
"#"
|
2001-01-02 09:07:17 +01:00
|
|
|
|
"(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(and:DI (match_dup 1) (match_dup 3)))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(ne:DI (match_dup 0) (const_int 0)))]
|
|
|
|
|
"operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; Floating-point operations. All the double-precision insns can extend
|
|
|
|
|
;; from single, so indicate that. The exception are the ones that simply
|
|
|
|
|
;; play with the sign bits; it's not clear what to do there.
|
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_mode_iterator FMODE [SF DF])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_mode_attr opmode [(SF "si") (DF "di")])
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "abs<mode>2"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
|
1998-01-27 04:23:31 +01:00
|
|
|
|
"TARGET_FP"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"cpys $f31,%R1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fcpys")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*nabs<mode>2"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(neg:FMODE
|
|
|
|
|
(abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"cpysn $f31,%R1,%0"
|
|
|
|
|
[(set_attr "type" "fadd")])
|
|
|
|
|
|
2000-01-26 23:08:59 +01:00
|
|
|
|
(define_expand "abstf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:TF 0 "register_operand")
|
|
|
|
|
(abs:TF (match_operand:TF 1 "reg_or_0_operand")))
|
2000-01-26 23:08:59 +01:00
|
|
|
|
(use (match_dup 2))])]
|
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2015-05-11 09:21:19 +02:00
|
|
|
|
"operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
|
2000-01-26 23:08:59 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*abstf_internal"
|
2000-01-26 23:08:59 +01:00
|
|
|
|
[(set (match_operand:TF 0 "register_operand" "=r")
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
|
2000-11-22 01:59:12 +01:00
|
|
|
|
(use (match_operand:DI 2 "register_operand" "r"))]
|
2000-01-26 23:08:59 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
2000-01-26 23:08:59 +01:00
|
|
|
|
[(const_int 0)]
|
2000-11-22 01:59:12 +01:00
|
|
|
|
"alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
|
2000-01-26 23:08:59 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "neg<mode>2"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
1994-02-25 13:34:38 +01:00
|
|
|
|
"cpysn %R1,%R1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-01-26 23:08:59 +01:00
|
|
|
|
(define_expand "negtf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:TF 0 "register_operand")
|
|
|
|
|
(neg:TF (match_operand:TF 1 "reg_or_0_operand")))
|
2000-01-26 23:08:59 +01:00
|
|
|
|
(use (match_dup 2))])]
|
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2015-05-11 09:21:19 +02:00
|
|
|
|
"operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
|
2000-01-26 23:08:59 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*negtf_internal"
|
2000-01-26 23:08:59 +01:00
|
|
|
|
[(set (match_operand:TF 0 "register_operand" "=r")
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
|
2000-11-22 01:59:12 +01:00
|
|
|
|
(use (match_operand:DI 2 "register_operand" "r"))]
|
2000-01-26 23:08:59 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
2000-01-26 23:08:59 +01:00
|
|
|
|
[(const_int 0)]
|
2000-11-22 01:59:12 +01:00
|
|
|
|
"alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
|
2000-01-26 23:08:59 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "copysign<mode>3"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")]
|
|
|
|
|
UNSPEC_COPYSIGN))]
|
2005-01-28 01:55:07 +01:00
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"cpys %R2,%R1,%0"
|
|
|
|
|
[(set_attr "type" "fadd")])
|
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*ncopysign<mode>3"
|
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|
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|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
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|
(neg:FMODE
|
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|
(unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
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|
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|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")]
|
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|
|
UNSPEC_COPYSIGN)))]
|
2005-01-28 01:55:07 +01:00
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"cpysn %R2,%R1,%0"
|
|
|
|
|
[(set_attr "type" "fadd")])
|
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*add<mode>3_ieee"
|
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|
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|
[(set (match_operand:FMODE 0 "register_operand" "=&f")
|
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|
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|
(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
|
|
|
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|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"add<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "add<mode>3"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
2005-01-28 01:55:07 +01:00
|
|
|
|
"TARGET_FP"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"add<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
2005-01-28 01:55:07 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*adddf_ext1"
|
2005-01-28 01:55:07 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(plus:DF (float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"add%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
2005-01-28 01:55:07 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*adddf_ext2"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(plus:DF (float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "%fG"))
|
|
|
|
|
(float_extend:DF
|
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"add%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_expand "addtf3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))
|
|
|
|
|
(use (match_operand:TF 2 "general_operand"))]
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
|
|
|
|
"alpha_emit_xfloating_arith (PLUS, operands); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_insn "*sub<mode>3_ieee"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=&f")
|
|
|
|
|
(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"sub<modesuffix>%/ %R1,%R2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "sub<mode>3"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"sub<modesuffix>%/ %R1,%R2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*subdf_ext1"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(minus:DF (float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"sub%-%/ %R1,%R2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*subdf_ext2"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(float_extend:DF
|
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"sub%-%/ %R1,%R2,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*subdf_ext3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(minus:DF (float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(float_extend:DF
|
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"sub%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_expand "subtf3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))
|
|
|
|
|
(use (match_operand:TF 2 "general_operand"))]
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
|
|
|
|
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_insn "*mul<mode>3_ieee"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=&f")
|
|
|
|
|
(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"mul<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fmul")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "mul<mode>3"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"mul<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fmul")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*muldf_ext1"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(mult:DF (float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"mul%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fmul")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*muldf_ext2"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(mult:DF (float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "%fG"))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"mul%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fmul")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_expand "multf3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))
|
|
|
|
|
(use (match_operand:TF 2 "general_operand"))]
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"alpha_emit_xfloating_arith (MULT, operands); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_insn "*div<mode>3_ieee"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=&f")
|
|
|
|
|
(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"div<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fdiv")
|
|
|
|
|
(set_attr "opsize" "<opmode>")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "div<mode>3"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"div<modesuffix>%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fdiv")
|
|
|
|
|
(set_attr "opsize" "<opmode>")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*divdf_ext1"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"div%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fdiv")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*divdf_ext2"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
|
|
|
|
|
(float_extend:DF
|
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"div%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fdiv")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*divdf_ext3"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(div:DF (float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))
|
|
|
|
|
(float_extend:DF
|
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
|
|
|
|
"div%-%/ %R1,%R2,%0"
|
|
|
|
|
[(set_attr "type" "fdiv")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_expand "divtf3"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))
|
|
|
|
|
(use (match_operand:TF 2 "general_operand"))]
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
|
|
|
|
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_insn "*sqrt<mode>2_ieee"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=&f")
|
|
|
|
|
(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"sqrt<modesuffix>%/ %R1,%0"
|
|
|
|
|
[(set_attr "type" "fsqrt")
|
|
|
|
|
(set_attr "opsize" "<opmode>")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sqrt<mode>2"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f")
|
|
|
|
|
(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
|
|
|
|
|
"TARGET_FP && TARGET_FIX"
|
|
|
|
|
"sqrt<modesuffix>%/ %R1,%0"
|
|
|
|
|
[(set_attr "type" "fsqrt")
|
|
|
|
|
(set_attr "opsize" "<opmode>")
|
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
2000-01-24 05:02:40 +01:00
|
|
|
|
|
1998-05-11 10:31:20 +02:00
|
|
|
|
;; Define conversion operators between DFmode and SImode, using the cvtql
|
|
|
|
|
;; instruction. To allow combine et al to do useful things, we keep the
|
|
|
|
|
;; operation as a unit until after reload, at which point we split the
|
|
|
|
|
;; instructions.
|
1998-07-21 10:57:27 +02:00
|
|
|
|
;;
|
|
|
|
|
;; Note that we (attempt to) only consider this optimization when the
|
|
|
|
|
;; ultimate destination is memory. If we will be doing further integer
|
|
|
|
|
;; processing, it is cheaper to do the truncation in the int regs.
|
|
|
|
|
|
|
|
|
|
(define_insn "*cvtql"
|
2004-01-19 10:55:42 +01:00
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
|
|
(unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
|
2001-07-15 08:25:01 +02:00
|
|
|
|
UNSPEC_CVTQL))]
|
1998-07-21 10:57:27 +02:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvtql%/ %R1,%0"
|
1998-07-21 10:57:27 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "v_sv")])
|
1998-05-11 10:31:20 +02:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*fix_truncdfsi_ieee"
|
1998-07-21 10:57:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "memory_operand" "=m")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(subreg:SI
|
|
|
|
|
(match_operator:DI 4 "fix_operator"
|
|
|
|
|
[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
|
1998-07-21 10:57:27 +02:00
|
|
|
|
(clobber (match_scratch:DI 2 "=&f"))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(clobber (match_scratch:SF 3 "=&f"))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
1998-05-11 10:31:20 +02:00
|
|
|
|
"#"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"&& reload_completed"
|
2003-10-19 13:10:59 +02:00
|
|
|
|
[(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
|
|
|
|
|
(set (match_dup 5) (match_dup 3))]
|
|
|
|
|
{
|
|
|
|
|
operands[5] = adjust_address (operands[0], SFmode, 0);
|
|
|
|
|
}
|
1998-05-11 10:31:20 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*fix_truncdfsi_internal"
|
1998-07-21 10:57:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "memory_operand" "=m")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(subreg:SI
|
|
|
|
|
(match_operator:DI 3 "fix_operator"
|
|
|
|
|
[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
|
1998-07-21 10:57:27 +02:00
|
|
|
|
(clobber (match_scratch:DI 2 "=f"))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1998-05-11 10:31:20 +02:00
|
|
|
|
"#"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"&& reload_completed"
|
2003-10-19 13:10:59 +02:00
|
|
|
|
[(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
|
|
|
|
|
(set (match_dup 5) (match_dup 4))]
|
|
|
|
|
{
|
|
|
|
|
operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
|
|
|
|
|
operands[5] = adjust_address (operands[0], SFmode, 0);
|
|
|
|
|
}
|
1998-05-11 10:31:20 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*fix_truncdfdi_ieee"
|
1999-04-26 03:05:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(match_operator:DI 2 "fix_operator"
|
|
|
|
|
[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-q%/ %R1,%0"
|
1998-04-04 20:20:59 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "c")
|
|
|
|
|
(set_attr "trap_suffix" "v_sv_svi")])
|
1998-04-04 20:20:59 +02:00
|
|
|
|
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(define_insn "*fix_truncdfdi2"
|
1999-04-26 03:05:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(match_operator:DI 2 "fix_operator"
|
|
|
|
|
[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-q%/ %R1,%0"
|
1998-04-04 20:20:59 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "c")
|
|
|
|
|
(set_attr "trap_suffix" "v_sv_svi")])
|
1998-04-04 20:20:59 +02:00
|
|
|
|
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(define_expand "fix_truncdfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
|
|
|
|
(fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
|
|
|
|
|
"TARGET_FP")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "fixuns_truncdfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
|
|
|
|
(unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
|
|
|
|
|
"TARGET_FP")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
|
1998-05-11 10:31:20 +02:00
|
|
|
|
;; Likewise between SFmode and SImode.
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*fix_truncsfsi_ieee"
|
1998-07-21 10:57:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "memory_operand" "=m")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(subreg:SI
|
|
|
|
|
(match_operator:DI 4 "fix_operator"
|
|
|
|
|
[(float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
|
1998-07-21 10:57:27 +02:00
|
|
|
|
(clobber (match_scratch:DI 2 "=&f"))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(clobber (match_scratch:SF 3 "=&f"))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
1998-05-11 10:31:20 +02:00
|
|
|
|
"#"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"&& reload_completed"
|
2003-10-19 13:10:59 +02:00
|
|
|
|
[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
|
2004-02-20 23:13:16 +01:00
|
|
|
|
(set (match_dup 5) (match_dup 3))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[5] = adjust_address (operands[0], SFmode, 0);"
|
1998-05-11 10:31:20 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn_and_split "*fix_truncsfsi_internal"
|
1998-07-21 10:57:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "memory_operand" "=m")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(subreg:SI
|
|
|
|
|
(match_operator:DI 3 "fix_operator"
|
|
|
|
|
[(float_extend:DF
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
|
1998-07-21 10:57:27 +02:00
|
|
|
|
(clobber (match_scratch:DI 2 "=f"))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1998-05-11 10:31:20 +02:00
|
|
|
|
"#"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"&& reload_completed"
|
2003-10-19 13:10:59 +02:00
|
|
|
|
[(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
|
|
|
|
|
(set (match_dup 5) (match_dup 4))]
|
|
|
|
|
{
|
|
|
|
|
operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
|
|
|
|
|
operands[5] = adjust_address (operands[0], SFmode, 0);
|
|
|
|
|
}
|
1998-05-11 10:31:20 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
|
|
|
|
(set_attr "trap" "yes")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*fix_truncsfdi_ieee"
|
1999-04-26 03:05:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(match_operator:DI 2 "fix_operator"
|
|
|
|
|
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-q%/ %R1,%0"
|
1998-04-04 20:20:59 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "c")
|
|
|
|
|
(set_attr "trap_suffix" "v_sv_svi")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(define_insn "*fix_truncsfdi2"
|
1999-04-26 03:05:13 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(match_operator:DI 2 "fix_operator"
|
|
|
|
|
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-q%/ %R1,%0"
|
1998-04-04 20:20:59 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "c")
|
|
|
|
|
(set_attr "trap_suffix" "v_sv_svi")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(define_expand "fix_truncsfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
|
|
|
|
(fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
|
|
|
|
|
"TARGET_FP")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "fixuns_truncsfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(unsigned_fix:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
|
|
|
|
|
"TARGET_FP")
|
2003-10-19 13:10:59 +02:00
|
|
|
|
|
2000-01-24 05:02:40 +01:00
|
|
|
|
(define_expand "fix_trunctfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:DI 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
|
|
|
|
|
|
2003-10-19 13:10:59 +02:00
|
|
|
|
(define_expand "fixuns_trunctfdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:DI 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))]
|
2003-10-19 13:10:59 +02:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
|
|
|
|
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*floatdisf_ieee"
|
1997-09-03 03:27:01 +02:00
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=&f")
|
1999-04-07 05:18:52 +02:00
|
|
|
|
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvtq%,%/ %1,%0"
|
1997-09-03 03:27:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "sui")])
|
1997-09-03 03:27:01 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "floatdisf2"
|
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
1999-04-07 05:18:52 +02:00
|
|
|
|
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvtq%,%/ %1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(define_insn_and_split "*floatsisf2_ieee"
|
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=&f")
|
|
|
|
|
(float:SF (match_operand:SI 1 "memory_operand" "m")))
|
|
|
|
|
(clobber (match_scratch:DI 2 "=&f"))
|
|
|
|
|
(clobber (match_scratch:SF 3 "=&f"))]
|
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(set (match_dup 3) (match_dup 1))
|
|
|
|
|
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
|
|
|
|
|
(set (match_dup 0) (float:SF (match_dup 2)))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[1] = adjust_address (operands[1], SFmode, 0);")
|
2004-01-19 10:55:42 +01:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*floatsisf2"
|
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
|
|
(float:SF (match_operand:SI 1 "memory_operand" "m")))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(set (match_dup 0) (match_dup 1))
|
|
|
|
|
(set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
|
|
|
|
|
(set (match_dup 0) (float:SF (match_dup 2)))]
|
|
|
|
|
{
|
|
|
|
|
operands[1] = adjust_address (operands[1], SFmode, 0);
|
|
|
|
|
operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
|
|
|
|
|
})
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*floatdidf_ieee"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=&f")
|
1999-04-07 05:18:52 +02:00
|
|
|
|
(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvtq%-%/ %1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "sui")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "floatdidf2"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
1999-04-07 05:18:52 +02:00
|
|
|
|
(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvtq%-%/ %1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(define_insn_and_split "*floatsidf2_ieee"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=&f")
|
|
|
|
|
(float:DF (match_operand:SI 1 "memory_operand" "m")))
|
|
|
|
|
(clobber (match_scratch:DI 2 "=&f"))
|
|
|
|
|
(clobber (match_scratch:SF 3 "=&f"))]
|
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(set (match_dup 3) (match_dup 1))
|
|
|
|
|
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
|
|
|
|
|
(set (match_dup 0) (float:DF (match_dup 2)))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[1] = adjust_address (operands[1], SFmode, 0);")
|
2004-01-19 10:55:42 +01:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*floatsidf2"
|
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
|
|
|
|
(float:DF (match_operand:SI 1 "memory_operand" "m")))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"#"
|
|
|
|
|
"&& reload_completed"
|
|
|
|
|
[(set (match_dup 3) (match_dup 1))
|
|
|
|
|
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
|
|
|
|
|
(set (match_dup 0) (float:DF (match_dup 2)))]
|
|
|
|
|
{
|
|
|
|
|
operands[1] = adjust_address (operands[1], SFmode, 0);
|
|
|
|
|
operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
|
|
|
|
|
operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
|
|
|
|
|
})
|
|
|
|
|
|
2000-01-24 05:02:40 +01:00
|
|
|
|
(define_expand "floatditf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "general_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
|
|
|
|
|
|
2000-01-27 11:17:37 +01:00
|
|
|
|
(define_expand "floatunsdisf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:SF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "register_operand"))]
|
2000-03-21 19:54:16 +01:00
|
|
|
|
"TARGET_FP"
|
2000-01-27 11:17:37 +01:00
|
|
|
|
"alpha_emit_floatuns (operands); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_expand "floatunsdidf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:DF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "register_operand"))]
|
2000-03-21 19:54:16 +01:00
|
|
|
|
"TARGET_FP"
|
2000-01-27 11:17:37 +01:00
|
|
|
|
"alpha_emit_floatuns (operands); DONE;")
|
|
|
|
|
|
2000-01-24 05:02:40 +01:00
|
|
|
|
(define_expand "floatunsditf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "general_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
|
|
|
|
|
|
1996-06-18 13:37:17 +02:00
|
|
|
|
(define_expand "extendsfdf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand")
|
|
|
|
|
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))]
|
1996-06-18 13:37:17 +02:00
|
|
|
|
"TARGET_FP"
|
|
|
|
|
{
|
1999-08-02 21:37:58 +02:00
|
|
|
|
if (alpha_fptm >= ALPHA_FPTM_SU)
|
2000-01-27 11:17:37 +01:00
|
|
|
|
operands[1] = force_reg (SFmode, operands[1]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-01-27 11:17:37 +01:00
|
|
|
|
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; The Unicos/Mk assembler doesn't support cvtst, but we've already
|
|
|
|
|
;; asserted that alpha_fptm == ALPHA_FPTM_N.
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*extendsfdf2_ieee"
|
1996-06-18 13:37:17 +02:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=&f")
|
|
|
|
|
(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
1996-06-18 13:37:17 +02:00
|
|
|
|
"cvtsts %1,%0"
|
|
|
|
|
[(set_attr "type" "fadd")
|
1996-03-17 01:33:14 +01:00
|
|
|
|
(set_attr "trap" "yes")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*extendsfdf2_internal"
|
1997-07-02 12:45:21 +02:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f,m")
|
|
|
|
|
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"@
|
2001-09-11 10:52:39 +02:00
|
|
|
|
cpys %1,%1,%0
|
1997-07-02 12:45:21 +02:00
|
|
|
|
ld%, %0,%1
|
|
|
|
|
st%- %1,%0"
|
2000-01-27 11:17:37 +01:00
|
|
|
|
[(set_attr "type" "fcpys,fld,fst")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2004-03-12 08:14:56 +01:00
|
|
|
|
;; Use register_operand for operand 1 to prevent compress_float_constant
|
|
|
|
|
;; from doing something silly. When optimizing we'll put things back
|
|
|
|
|
;; together anyway.
|
2000-01-30 21:14:40 +01:00
|
|
|
|
(define_expand "extendsftf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:SF 1 "register_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-30 21:14:40 +01:00
|
|
|
|
{
|
|
|
|
|
rtx tmp = gen_reg_rtx (DFmode);
|
|
|
|
|
emit_insn (gen_extendsfdf2 (tmp, operands[1]));
|
|
|
|
|
emit_insn (gen_extenddftf2 (operands[0], tmp));
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-01-30 21:14:40 +01:00
|
|
|
|
|
2000-01-24 05:02:40 +01:00
|
|
|
|
(define_expand "extenddftf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:TF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DF 1 "register_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*truncdfsf2_ieee"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=&f")
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-%,%/ %R1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "truncdfsf2"
|
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cvt%-%,%/ %R1,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "round_suffix" "normal")
|
|
|
|
|
(set_attr "trap_suffix" "u_su_sui")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2000-01-24 05:02:40 +01:00
|
|
|
|
(define_expand "trunctfdf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:DF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2000-01-24 05:02:40 +01:00
|
|
|
|
"alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
|
|
|
|
|
|
2000-01-28 05:36:43 +01:00
|
|
|
|
(define_expand "trunctfsf2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:SF 0 "register_operand"))
|
|
|
|
|
(use (match_operand:TF 1 "general_operand"))]
|
2000-03-21 19:54:16 +01:00
|
|
|
|
"TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
|
2000-01-28 05:36:43 +01:00
|
|
|
|
{
|
2000-01-30 21:14:40 +01:00
|
|
|
|
rtx tmpf, sticky, arg, lo, hi;
|
|
|
|
|
|
|
|
|
|
tmpf = gen_reg_rtx (DFmode);
|
|
|
|
|
sticky = gen_reg_rtx (DImode);
|
|
|
|
|
arg = copy_to_mode_reg (TFmode, operands[1]);
|
|
|
|
|
lo = gen_lowpart (DImode, arg);
|
|
|
|
|
hi = gen_highpart (DImode, arg);
|
|
|
|
|
|
|
|
|
|
/* Convert the low word of the TFmode value into a sticky rounding bit,
|
|
|
|
|
then or it into the low bit of the high word. This leaves the sticky
|
|
|
|
|
bit at bit 48 of the fraction, which is representable in DFmode,
|
|
|
|
|
which prevents rounding error in the final conversion to SFmode. */
|
|
|
|
|
|
rtl.h (always_void_p): New function.
gcc/
* rtl.h (always_void_p): New function.
* gengenrtl.c (always_void_p): Likewise.
(genmacro): Don't add a mode parameter to gen_rtx_foo if rtxes
with code foo are always VOIDmode.
* genemit.c (gen_exp): Update gen_rtx_foo calls accordingly.
* builtins.c, caller-save.c, calls.c, cfgexpand.c, combine.c,
compare-elim.c, config/aarch64/aarch64.c,
config/aarch64/aarch64.md, config/alpha/alpha.c,
config/alpha/alpha.md, config/arc/arc.c, config/arc/arc.md,
config/arm/arm-fixed.md, config/arm/arm.c, config/arm/arm.md,
config/arm/ldrdstrd.md, config/arm/thumb2.md, config/arm/vfp.md,
config/avr/avr.c, config/bfin/bfin.c, config/c6x/c6x.c,
config/c6x/c6x.md, config/cr16/cr16.c, config/cris/cris.c,
config/cris/cris.md, config/darwin.c, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c, config/frv/frv.c,
config/frv/frv.md, config/h8300/h8300.c, config/i386/i386.c,
config/i386/i386.md, config/i386/sse.md, config/ia64/ia64.c,
config/ia64/vect.md, config/iq2000/iq2000.c,
config/iq2000/iq2000.md, config/lm32/lm32.c, config/lm32/lm32.md,
config/m32c/m32c.c, config/m32r/m32r.c, config/m68k/m68k.c,
config/m68k/m68k.md, config/mcore/mcore.c, config/mcore/mcore.md,
config/mep/mep.c, config/microblaze/microblaze.c,
config/mips/mips.c, config/mips/mips.md, config/mmix/mmix.c,
config/mn10300/mn10300.c, config/msp430/msp430.c,
config/nds32/nds32-memory-manipulation.c, config/nds32/nds32.c,
config/nds32/nds32.md, config/nios2/nios2.c, config/nvptx/nvptx.c,
config/pa/pa.c, config/pa/pa.md, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000.c,
config/rs6000/rs6000.md, config/rs6000/vector.md,
config/rs6000/vsx.md, config/rx/rx.c, config/rx/rx.md,
config/s390/s390.c, config/s390/s390.md, config/sh/sh.c,
config/sh/sh.md, config/sh/sh_treg_combine.cc,
config/sparc/sparc.c, config/sparc/sparc.md, config/spu/spu.c,
config/spu/spu.md, config/stormy16/stormy16.c,
config/tilegx/tilegx.c, config/tilegx/tilegx.md,
config/tilepro/tilepro.c, config/tilepro/tilepro.md,
config/v850/v850.c, config/v850/v850.md, config/vax/vax.c,
config/visium/visium.c, config/xtensa/xtensa.c, cprop.c, dse.c,
expr.c, gcse.c, ifcvt.c, ira.c, jump.c, lower-subreg.c,
lra-constraints.c, lra-eliminations.c, lra.c, postreload.c, ree.c,
reg-stack.c, reload.c, reload1.c, reorg.c, sel-sched.c,
var-tracking.c: Update calls accordingly.
From-SVN: r222883
2015-05-07 18:58:46 +02:00
|
|
|
|
emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx)));
|
2000-01-30 21:14:40 +01:00
|
|
|
|
emit_insn (gen_iordi3 (hi, hi, sticky));
|
|
|
|
|
emit_insn (gen_trunctfdf2 (tmpf, arg));
|
|
|
|
|
emit_insn (gen_truncdfsf2 (operands[0], tmpf));
|
2000-01-28 05:36:43 +01:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; Next are all the integer comparisons, and conditional moves and branches
|
|
|
|
|
;; and some of the related define_expand's and define_split's.
|
|
|
|
|
|
2000-05-26 09:04:21 +02:00
|
|
|
|
(define_insn "*setcc_internal"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=r")
|
|
|
|
|
(match_operator 1 "alpha_comparison_operator"
|
2000-10-06 07:19:40 +02:00
|
|
|
|
[(match_operand:DI 2 "register_operand" "r")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
|
2000-05-26 09:04:21 +02:00
|
|
|
|
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
|
|
|
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
|
|
|
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
|
2000-10-06 07:19:40 +02:00
|
|
|
|
"cmp%C1 %2,%3,%0"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set_attr "type" "icmp")])
|
|
|
|
|
|
2000-10-06 07:19:40 +02:00
|
|
|
|
;; Yes, we can technically support reg_or_8bit_operand in operand 2,
|
|
|
|
|
;; but that's non-canonical rtl and allowing that causes inefficiencies
|
|
|
|
|
;; from cse on.
|
2000-05-26 09:04:21 +02:00
|
|
|
|
(define_insn "*setcc_swapped_internal"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=r")
|
|
|
|
|
(match_operator 1 "alpha_swapped_comparison_operator"
|
2000-10-06 07:19:40 +02:00
|
|
|
|
[(match_operand:DI 2 "register_operand" "r")
|
1996-09-18 23:47:46 +02:00
|
|
|
|
(match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
|
2000-05-26 09:04:21 +02:00
|
|
|
|
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
|
|
|
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
|
|
|
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
|
1996-09-21 23:59:55 +02:00
|
|
|
|
"cmp%c1 %r3,%2,%0"
|
1993-03-01 13:29:39 +01:00
|
|
|
|
[(set_attr "type" "icmp")])
|
|
|
|
|
|
2000-10-06 07:19:40 +02:00
|
|
|
|
;; Use match_operator rather than ne directly so that we can match
|
|
|
|
|
;; multiple integer modes.
|
2000-05-30 17:52:03 +02:00
|
|
|
|
(define_insn "*setne_internal"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=r")
|
|
|
|
|
(match_operator 1 "signed_comparison_operator"
|
2000-10-06 07:19:40 +02:00
|
|
|
|
[(match_operand:DI 2 "register_operand" "r")
|
2000-05-30 17:52:03 +02:00
|
|
|
|
(const_int 0)]))]
|
|
|
|
|
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
|
|
|
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
|
|
|
|
|
&& GET_CODE (operands[1]) == NE
|
|
|
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
|
|
|
|
|
"cmpult $31,%2,%0"
|
|
|
|
|
[(set_attr "type" "icmp")])
|
|
|
|
|
|
2000-05-26 09:04:21 +02:00
|
|
|
|
;; The mode folding trick can't be used with const_int operands, since
|
|
|
|
|
;; reload needs to know the proper mode.
|
2000-05-29 09:52:26 +02:00
|
|
|
|
;;
|
|
|
|
|
;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
|
|
|
|
|
;; in order to create more pairs of constants. As long as we're allowing
|
|
|
|
|
;; two constants at the same time, and will have to reload one of them...
|
1995-01-25 05:11:29 +01:00
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "*mov<mode>cc_internal"
|
|
|
|
|
[(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r")
|
|
|
|
|
(if_then_else:IMODE
|
2000-05-26 09:04:21 +02:00
|
|
|
|
(match_operator 2 "signed_comparison_operator"
|
|
|
|
|
[(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
|
|
|
|
|
(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(match_operand:IMODE 1 "add_operand" "rI,0,rI,0")
|
|
|
|
|
(match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))]
|
2004-10-28 19:21:00 +02:00
|
|
|
|
"(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
|
2000-05-26 09:04:21 +02:00
|
|
|
|
"@
|
|
|
|
|
cmov%C2 %r3,%1,%0
|
|
|
|
|
cmov%D2 %r3,%5,%0
|
|
|
|
|
cmov%c2 %r4,%1,%0
|
|
|
|
|
cmov%d2 %r4,%5,%0"
|
|
|
|
|
[(set_attr "type" "icmov")])
|
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "*mov<mode>cc_lbc"
|
|
|
|
|
[(set (match_operand:IMODE 0 "register_operand" "=r,r")
|
|
|
|
|
(if_then_else:IMODE
|
2000-05-26 09:04:21 +02:00
|
|
|
|
(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(const_int 0))
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0")
|
|
|
|
|
(match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))]
|
2000-05-26 09:04:21 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
cmovlbc %r2,%1,%0
|
|
|
|
|
cmovlbs %r2,%3,%0"
|
|
|
|
|
[(set_attr "type" "icmov")])
|
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_insn "*mov<mode>cc_lbs"
|
|
|
|
|
[(set (match_operand:IMODE 0 "register_operand" "=r,r")
|
|
|
|
|
(if_then_else:IMODE
|
2000-05-26 09:04:21 +02:00
|
|
|
|
(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(const_int 0))
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0")
|
|
|
|
|
(match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
cmovlbs %r2,%1,%0
|
1996-06-13 03:47:01 +02:00
|
|
|
|
cmovlbc %r2,%3,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "icmov")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; For ABS, we have two choices, depending on whether the input and output
|
|
|
|
|
;; registers are the same or not.
|
|
|
|
|
(define_expand "absdi2"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(abs:DI (match_operand:DI 1 "register_operand")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
if (rtx_equal_p (operands[0], operands[1]))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
|
|
|
|
|
else
|
|
|
|
|
emit_insn (gen_absdi2_diff (operands[0], operands[1]));
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "absdi2_same"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 1 "register_operand")
|
|
|
|
|
(neg:DI (match_operand:DI 0 "register_operand")))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(if_then_else:DI (ge (match_dup 0) (const_int 0))
|
|
|
|
|
(match_dup 0)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "absdi2_diff"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(neg:DI (match_operand:DI 1 "register_operand")))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(if_then_else:DI (lt (match_dup 1) (const_int 0))
|
|
|
|
|
(match_dup 0)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(abs:DI (match_dup 0)))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(clobber (match_operand:DI 1 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 1) (neg:DI (match_dup 0)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 0) (match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(abs:DI (match_operand:DI 1 "register_operand")))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"! rtx_equal_p (operands[0], operands[1])"
|
|
|
|
|
[(set (match_dup 0) (neg:DI (match_dup 1)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 0) (match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(neg:DI (abs:DI (match_dup 0))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(clobber (match_operand:DI 1 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 1) (neg:DI (match_dup 0)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 0) (match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"! rtx_equal_p (operands[0], operands[1])"
|
|
|
|
|
[(set (match_dup 0) (neg:DI (match_dup 1)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 0) (match_dup 1)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2012-10-12 13:32:02 +02:00
|
|
|
|
(define_insn "<code><mode>3"
|
|
|
|
|
[(set (match_operand:I12MODE 0 "register_operand" "=r")
|
|
|
|
|
(any_maxmin:I12MODE
|
|
|
|
|
(match_operand:I12MODE 1 "reg_or_0_operand" "%rJ")
|
|
|
|
|
(match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))]
|
1997-11-02 22:19:36 +01:00
|
|
|
|
"TARGET_MAX"
|
2012-10-12 13:32:02 +02:00
|
|
|
|
"<maxmin><vecmodesuffix> %r1,%2,%0"
|
2002-10-14 21:57:18 +02:00
|
|
|
|
[(set_attr "type" "mvi")])
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
1993-11-11 00:49:56 +01:00
|
|
|
|
(define_expand "smaxdi3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(le:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI (eq (match_dup 3) (const_int 0))
|
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[3] = gen_reg_rtx (DImode);")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(smax:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(clobber (match_operand:DI 3 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"operands[2] != const0_rtx"
|
|
|
|
|
[(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1) (match_dup 2)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*smax_const0"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(smax:DI (match_operand:DI 1 "register_operand" "0")
|
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"cmovlt %0,0,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "icmov")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "smindi3"
|
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(lt:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI (ne (match_dup 3) (const_int 0))
|
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[3] = gen_reg_rtx (DImode);")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(smin:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(clobber (match_operand:DI 3 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"operands[2] != const0_rtx"
|
|
|
|
|
[(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1) (match_dup 2)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*smin_const0"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(smin:DI (match_operand:DI 1 "register_operand" "0")
|
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"cmovgt %0,0,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "icmov")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "umaxdi3"
|
2001-07-15 09:17:29 +02:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(leu:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI (eq (match_dup 3) (const_int 0))
|
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
""
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"operands[3] = gen_reg_rtx (DImode);")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(umax:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(clobber (match_operand:DI 3 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"operands[2] != const0_rtx"
|
|
|
|
|
[(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1) (match_dup 2)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "umindi3"
|
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(ltu:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI (ne (match_dup 3) (const_int 0))
|
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
""
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"operands[3] = gen_reg_rtx (DImode);")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(umin:DI (match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")))
|
|
|
|
|
(clobber (match_operand:DI 3 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"operands[2] != const0_rtx"
|
|
|
|
|
[(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
|
|
|
|
|
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_dup 1) (match_dup 2)))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*bcc_normal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(match_operator 1 "signed_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))]
|
|
|
|
|
""
|
|
|
|
|
"b%C1 %r2,%0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*bcc_reverse"
|
1996-09-18 23:47:46 +02:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(match_operator 1 "signed_comparison_operator"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
[(match_operand:DI 2 "register_operand" "r")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
|
|
|
|
|
(pc)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))))]
|
1996-09-18 23:47:46 +02:00
|
|
|
|
""
|
|
|
|
|
"b%c1 %2,%0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*blbs_normal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))]
|
|
|
|
|
""
|
|
|
|
|
"blbs %r1,%0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*blbc_normal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))]
|
|
|
|
|
""
|
|
|
|
|
"blbc %r1,%0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
|
[(parallel
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(match_operator 1 "comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(zero_extract:DI (match_operand:DI 2 "register_operand")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand:DI 3 "const_int_operand"))
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(clobber (match_operand:DI 4 "register_operand"))])]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"INTVAL (operands[3]) != 0"
|
|
|
|
|
[(set (match_dup 4)
|
|
|
|
|
(lshiftrt:DI (match_dup 2) (match_dup 3)))
|
|
|
|
|
(set (pc)
|
|
|
|
|
(if_then_else (match_op_dup 1
|
|
|
|
|
[(zero_extract:DI (match_dup 4)
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(label_ref (match_dup 0))
|
|
|
|
|
(pc)))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
)
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; The following are the corresponding floating-point insns. Recall
|
2000-01-24 21:10:04 +01:00
|
|
|
|
;; we need to have variants that expand the arguments from SFmode
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; to DFmode.
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*cmpdf_ieee"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=&f")
|
2000-01-24 21:10:04 +01:00
|
|
|
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cmp%-%C1%/ %R2,%R3,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "su")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*cmpdf_internal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
2000-01-24 21:10:04 +01:00
|
|
|
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
|
2009-08-25 20:58:11 +02:00
|
|
|
|
"TARGET_FP"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cmp%-%C1%/ %R2,%R3,%0"
|
1998-07-30 21:16:39 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "su")])
|
1998-07-30 21:16:39 +02:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*cmpdf_ext1"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
2000-01-24 21:10:04 +01:00
|
|
|
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cmp%-%C1%/ %R2,%R3,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "su")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*cmpdf_ext2"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
2000-01-24 21:10:04 +01:00
|
|
|
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cmp%-%C1%/ %R2,%R3,%0"
|
1996-06-13 03:47:01 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "su")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*cmpdf_ext3"
|
1998-07-30 21:16:39 +02:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
2000-01-24 21:10:04 +01:00
|
|
|
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
1998-07-30 21:16:39 +02:00
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))
|
1998-07-30 21:16:39 +02:00
|
|
|
|
(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
|
1999-08-02 21:37:58 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
2001-07-22 18:02:06 +02:00
|
|
|
|
"cmp%-%C1%/ %R2,%R3,%0"
|
1998-07-30 21:16:39 +02:00
|
|
|
|
[(set_attr "type" "fadd")
|
2001-07-22 18:02:06 +02:00
|
|
|
|
(set_attr "trap" "yes")
|
|
|
|
|
(set_attr "trap_suffix" "su")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_insn "*mov<mode>cc_internal"
|
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand" "=f,f")
|
|
|
|
|
(if_then_else:FMODE
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operator 3 "signed_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
|
|
|
|
|
(match_operand:DF 2 "const0_operand" "G,G")])
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(match_operand:FMODE 1 "reg_or_0_operand" "fG,0")
|
|
|
|
|
(match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))]
|
1998-07-30 21:16:39 +02:00
|
|
|
|
"TARGET_FP"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
"@
|
|
|
|
|
fcmov%C3 %R4,%R1,%0
|
|
|
|
|
fcmov%D3 %R4,%R5,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "fcmov")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*movdfcc_ext1"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
2001-07-15 09:17:29 +02:00
|
|
|
|
(if_then_else:DF
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operator 3 "signed_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
|
|
|
|
|
(match_operand:DF 2 "const0_operand" "G,G")])
|
|
|
|
|
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
|
|
|
|
|
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
|
2009-08-25 20:58:11 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"@
|
|
|
|
|
fcmov%C3 %R4,%R1,%0
|
|
|
|
|
fcmov%D3 %R4,%R5,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "fcmov")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*movdfcc_ext2"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
2001-07-15 09:17:29 +02:00
|
|
|
|
(if_then_else:DF
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operator 3 "signed_comparison_operator"
|
2001-07-15 09:17:29 +02:00
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
|
|
|
|
|
(match_operand:DF 2 "const0_operand" "G,G")])
|
|
|
|
|
(match_operand:DF 1 "reg_or_0_operand" "fG,0")
|
|
|
|
|
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
|
2009-08-25 20:58:11 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
"@
|
|
|
|
|
fcmov%C3 %R4,%R1,%0
|
|
|
|
|
fcmov%D3 %R4,%R5,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "fcmov")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*movdfcc_ext3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "=f,f")
|
2001-07-15 09:17:29 +02:00
|
|
|
|
(if_then_else:SF
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operator 3 "signed_comparison_operator"
|
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
|
|
|
|
|
(match_operand:DF 2 "const0_operand" "G,G")])
|
|
|
|
|
(match_operand:SF 1 "reg_or_0_operand" "fG,0")
|
|
|
|
|
(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
|
2009-08-25 20:58:11 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1996-03-17 01:33:14 +01:00
|
|
|
|
"@
|
|
|
|
|
fcmov%C3 %R4,%R1,%0
|
|
|
|
|
fcmov%D3 %R4,%R5,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "fcmov")])
|
1996-03-17 01:33:14 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*movdfcc_ext4"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
2001-07-15 09:17:29 +02:00
|
|
|
|
(if_then_else:DF
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operator 3 "signed_comparison_operator"
|
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
|
|
|
|
|
(match_operand:DF 2 "const0_operand" "G,G")])
|
|
|
|
|
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
|
|
|
|
|
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
|
2009-08-25 20:58:11 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"@
|
|
|
|
|
fcmov%C3 %R4,%R1,%0
|
|
|
|
|
fcmov%D3 %R4,%R5,%0"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
[(set_attr "type" "fcmov")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
|
(define_expand "smaxdf3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(le:DF (match_operand:DF 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand")))
|
|
|
|
|
(set (match_operand:DF 0 "register_operand")
|
1994-02-01 12:06:13 +01:00
|
|
|
|
(if_then_else:DF (eq (match_dup 3) (match_dup 4))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
"TARGET_FP"
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
1994-02-01 12:06:13 +01:00
|
|
|
|
operands[4] = CONST0_RTX (DFmode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
|
(define_expand "smindf3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(lt:DF (match_operand:DF 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand")))
|
|
|
|
|
(set (match_operand:DF 0 "register_operand")
|
1994-02-01 12:06:13 +01:00
|
|
|
|
(if_then_else:DF (ne (match_dup 3) (match_dup 4))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
|
|
|
|
"TARGET_FP"
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
1994-02-01 12:06:13 +01:00
|
|
|
|
operands[4] = CONST0_RTX (DFmode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
|
(define_expand "smaxsf3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
|
|
|
|
|
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
|
|
|
|
|
(set (match_operand:SF 0 "register_operand")
|
1993-12-27 18:02:09 +01:00
|
|
|
|
(if_then_else:SF (eq (match_dup 3) (match_dup 4))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
2009-09-15 08:29:43 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
1993-12-27 18:02:09 +01:00
|
|
|
|
operands[4] = CONST0_RTX (DFmode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
genopinit.c (optabs): Use smin/smax for floating point too.
* genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN.
* doc/rtl.texi: Likewise.
* rtl.def (SMIN, SMAX): Likewise
* tree.def (MIN_EXPR, MAX_EXPR): Likewise.
* config/alpha/alpha.md (smaxdf3, smindf3, smaxsf3, sminsf3): Add
leading 's' to the name.
* config/ia64/ia64.md (smaxsf3, sminsf3, smaxdf3, smindf3,
smaxxf3, sminxf3): Likewise.
* config/rs6000/rs6000.md (smaxdf3, smindf3, smaxsf3, sminsf3):
Likewise.
From-SVN: r94083
2005-01-22 23:49:06 +01:00
|
|
|
|
(define_expand "sminsf3"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 3)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
|
|
|
|
|
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
|
|
|
|
|
(set (match_operand:SF 0 "register_operand")
|
1994-02-01 12:06:13 +01:00
|
|
|
|
(if_then_else:SF (ne (match_dup 3) (match_dup 4))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 1) (match_dup 2)))]
|
2009-09-15 08:29:43 +02:00
|
|
|
|
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
1993-12-27 18:02:09 +01:00
|
|
|
|
operands[4] = CONST0_RTX (DFmode);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*fbcc_normal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(match_operator 1 "signed_comparison_operator"
|
2002-06-04 04:28:40 +02:00
|
|
|
|
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
|
|
|
|
(match_operand:DF 3 "const0_operand" "G")])
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"fb%C1 %R2,%0"
|
|
|
|
|
[(set_attr "type" "fbr")])
|
|
|
|
|
|
2000-10-24 02:06:18 +02:00
|
|
|
|
(define_insn "*fbcc_ext_normal"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
|
|
|
|
(match_operator 1 "signed_comparison_operator"
|
|
|
|
|
[(float_extend:DF
|
2002-06-04 04:28:40 +02:00
|
|
|
|
(match_operand:SF 2 "reg_or_0_operand" "fG"))
|
|
|
|
|
(match_operand:DF 3 "const0_operand" "G")])
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(pc)))]
|
|
|
|
|
"TARGET_FP"
|
|
|
|
|
"fb%C1 %R2,%0"
|
|
|
|
|
[(set_attr "type" "fbr")])
|
|
|
|
|
|
|
|
|
|
;; These are the main define_expand's used to make conditional branches
|
|
|
|
|
;; and compares.
|
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cbranchdf4"
|
|
|
|
|
[(use (match_operator 0 "alpha_cbranch_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DF 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DF 2 "reg_or_0_operand")]))
|
|
|
|
|
(use (match_operand 3))]
|
1995-10-21 19:16:31 +01:00
|
|
|
|
"TARGET_FP"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_emit_conditional_branch (operands, DFmode); DONE;")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cbranchtf4"
|
|
|
|
|
[(use (match_operator 0 "alpha_cbranch_operator"
|
|
|
|
|
[(match_operand:TF 1 "general_operand")
|
|
|
|
|
(match_operand:TF 2 "general_operand")]))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 3))]
|
2000-03-24 03:05:09 +01:00
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_emit_conditional_branch (operands, TFmode); DONE;")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cbranchdi4"
|
|
|
|
|
[(use (match_operator 0 "alpha_cbranch_operator"
|
2015-05-15 07:04:32 +02:00
|
|
|
|
[(match_operand:DI 1 "general_operand")
|
|
|
|
|
(match_operand:DI 2 "general_operand")]))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 3))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_emit_conditional_branch (operands, DImode); DONE;")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cstoredf4"
|
|
|
|
|
[(use (match_operator:DI 1 "alpha_cbranch_operator"
|
|
|
|
|
[(match_operand:DF 2 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DF 3 "reg_or_0_operand")]))
|
|
|
|
|
(clobber (match_operand:DI 0 "register_operand"))]
|
|
|
|
|
"TARGET_FP"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
{
|
|
|
|
|
if (alpha_emit_setcc (operands, DFmode))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cstoretf4"
|
|
|
|
|
[(use (match_operator:DI 1 "alpha_cbranch_operator"
|
|
|
|
|
[(match_operand:TF 2 "general_operand")
|
|
|
|
|
(match_operand:TF 3 "general_operand")]))
|
|
|
|
|
(clobber (match_operand:DI 0 "register_operand"))]
|
|
|
|
|
"TARGET_HAS_XFLOATING_LIBS"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
{
|
|
|
|
|
if (alpha_emit_setcc (operands, TFmode))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
2000-09-25 06:02:20 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cstoredi4"
|
|
|
|
|
[(use (match_operator:DI 1 "alpha_cbranch_operator"
|
2015-05-15 07:04:32 +02:00
|
|
|
|
[(match_operand:DI 2 "general_operand")
|
|
|
|
|
(match_operand:DI 3 "general_operand")]))
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(clobber (match_operand:DI 0 "register_operand"))]
|
2000-09-25 06:02:20 +02:00
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
{
|
|
|
|
|
if (alpha_emit_setcc (operands, DImode))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1995-01-25 05:11:29 +01:00
|
|
|
|
;; These are the main define_expand's used to make conditional moves.
|
|
|
|
|
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(define_expand "mov<mode>cc"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:I48MODE 0 "register_operand")
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
(if_then_else:I48MODE
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1 "comparison_operator")
|
|
|
|
|
(match_operand:I48MODE 2 "reg_or_8bit_operand")
|
|
|
|
|
(match_operand:I48MODE 3 "reg_or_8bit_operand")))]
|
1995-01-25 05:11:29 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
alpha.md (IMODE): New mode iterator.
* config/alpha/alpha.md (IMODE): New mode iterator.
(I124MODE): Ditto.
(I248MODE): Ditto.
(modesuffix): Handle QI and HI modes.
(zero_extendqi<mode>2): Macroize insn from zero_extendqi{hi,si,di}2
using I248MODE mode iterator.
(zero_extendhi<mode>2): Macroize insn from zero_extendhi{si,di}2
using I48MODE mode iterator.
(andnot<mode>3): Macroize insn from andnot{si,di}3 using
I48MODE mode iterator.
(ins<modesuffix>l_const): Macroize insn from ins{b,w,l}l_const
using I248MODE mode iterator.
(ins<modesuffix>l): Macroize insn from ins{b,w,l}l
using I248MODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from
*mov{qi,hi,si,di}cc_internal using IMODE mode iterator.
(*mov<mode>cc_lbc): Macroize insn from
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
using I48MODE mode iterator.
From-SVN: r192379
2012-10-11 22:44:30 +02:00
|
|
|
|
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
|
|
|
|
|
if (operands[1] == 0)
|
1995-01-25 05:11:29 +01:00
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1995-01-25 05:11:29 +01:00
|
|
|
|
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(define_expand "mov<mode>cc"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:FMODE 0 "register_operand")
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
(if_then_else:FMODE
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1 "comparison_operator")
|
|
|
|
|
(match_operand:FMODE 2 "reg_or_8bit_operand")
|
|
|
|
|
(match_operand:FMODE 3 "reg_or_8bit_operand")))]
|
1995-01-25 05:11:29 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
alpha.md (FMODE): New mode iterator.
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
From-SVN: r192421
2012-10-13 10:36:21 +02:00
|
|
|
|
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
|
|
|
|
|
if (operands[1] == 0)
|
1995-01-25 05:11:29 +01:00
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1995-01-25 05:11:29 +01:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; These define_split definitions are used in cases when comparisons have
|
|
|
|
|
;; not be stated in the correct way and we need to reverse the second
|
|
|
|
|
;; comparison. For example, x >= 7 has to be done as x < 6 with the
|
|
|
|
|
;; comparison that tests the result being reversed. We have one define_split
|
|
|
|
|
;; for each use of a comparison. They do not match valid insns and need
|
|
|
|
|
;; not generate valid insns.
|
|
|
|
|
;;
|
|
|
|
|
;; We can also handle equality comparisons (and inequality comparisons in
|
1993-04-10 16:56:02 +02:00
|
|
|
|
;; cases where the resulting add cannot overflow) by doing an add followed by
|
|
|
|
|
;; a comparison with zero. This is faster since the addition takes one
|
|
|
|
|
;; less cycle than a compare when feeding into a conditional move.
|
|
|
|
|
;; For this case, we also have an SImode pattern since we can merge the add
|
|
|
|
|
;; and sign extend and the order doesn't matter.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;;
|
|
|
|
|
;; We do not do this for floating-point, since it isn't clear how the "wrong"
|
|
|
|
|
;; operation could have been generated.
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI
|
|
|
|
|
(match_operator 1 "comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 3 "reg_or_cint_operand")])
|
|
|
|
|
(match_operand:DI 4 "reg_or_cint_operand")
|
|
|
|
|
(match_operand:DI 5 "reg_or_cint_operand")))
|
|
|
|
|
(clobber (match_operand:DI 6 "register_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
"operands[3] != const0_rtx"
|
|
|
|
|
[(set (match_dup 6) (match_dup 7))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
enum rtx_code code = GET_CODE (operands[1]);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
|
|
|
|
|
|
|
|
|
|
/* If we are comparing for equality with a constant and that constant
|
|
|
|
|
appears in the arm when the register equals the constant, use the
|
|
|
|
|
register since that is more likely to match (and to produce better code
|
|
|
|
|
if both would). */
|
|
|
|
|
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (code == EQ && CONST_INT_P (operands[3])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
&& rtx_equal_p (operands[4], operands[3]))
|
|
|
|
|
operands[4] = operands[2];
|
|
|
|
|
|
2009-04-22 10:19:54 +02:00
|
|
|
|
else if (code == NE && CONST_INT_P (operands[3])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
&& rtx_equal_p (operands[5], operands[3]))
|
|
|
|
|
operands[5] = operands[2];
|
|
|
|
|
|
1993-04-10 16:56:02 +02:00
|
|
|
|
if (code == NE || code == EQ
|
|
|
|
|
|| (extended_count (operands[2], DImode, unsignedp) >= 1
|
|
|
|
|
&& extended_count (operands[3], DImode, unsignedp) >= 1))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (CONST_INT_P (operands[3]))
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_PLUS (DImode, operands[2],
|
|
|
|
|
GEN_INT (- INTVAL (operands[3])));
|
1993-04-10 16:56:02 +02:00
|
|
|
|
else
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
|
1993-04-10 16:56:02 +02:00
|
|
|
|
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
else if (code == EQ || code == LE || code == LT
|
|
|
|
|
|| code == LEU || code == LTU)
|
|
|
|
|
{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
|
|
|
|
|
operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
|
|
|
|
|
operands[2], operands[3]);
|
|
|
|
|
operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(if_then_else:DI
|
|
|
|
|
(match_operator 1 "comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:SI 2 "reg_or_0_operand")
|
|
|
|
|
(match_operand:SI 3 "reg_or_cint_operand")])
|
|
|
|
|
(match_operand:DI 4 "reg_or_8bit_operand")
|
|
|
|
|
(match_operand:DI 5 "reg_or_8bit_operand")))
|
|
|
|
|
(clobber (match_operand:DI 6 "register_operand"))]
|
1993-04-10 16:56:02 +02:00
|
|
|
|
"operands[3] != const0_rtx
|
|
|
|
|
&& (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(set (match_dup 6) (match_dup 7))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
enum rtx_code code = GET_CODE (operands[1]);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
|
1993-04-10 16:56:02 +02:00
|
|
|
|
rtx tem;
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
if ((code != NE && code != EQ
|
|
|
|
|
&& ! (extended_count (operands[2], DImode, unsignedp) >= 1
|
|
|
|
|
&& extended_count (operands[3], DImode, unsignedp) >= 1)))
|
|
|
|
|
FAIL;
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (CONST_INT_P (operands[3]))
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
tem = gen_rtx_PLUS (SImode, operands[2],
|
|
|
|
|
GEN_INT (- INTVAL (operands[3])));
|
1993-04-10 16:56:02 +02:00
|
|
|
|
else
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
|
1993-04-10 16:56:02 +02:00
|
|
|
|
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
|
|
|
|
|
operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
|
|
|
|
|
operands[6], const0_rtx);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-05-29 09:52:26 +02:00
|
|
|
|
;; Prefer to use cmp and arithmetic when possible instead of a cmove.
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0 "register_operand")
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(if_then_else (match_operator 1 "signed_comparison_operator"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand")
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(const_int 0)])
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 3 "const_int_operand")
|
|
|
|
|
(match_operand 4 "const_int_operand")))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
|
|
|
|
|
operands[2], operands[3], operands[4]))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
|
|
|
|
|
;; Oh well, we match it in movcc, so it must be partially our fault.
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0 "register_operand")
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(if_then_else (match_operator 1 "signed_comparison_operator"
|
|
|
|
|
[(const_int 0)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")])
|
|
|
|
|
(match_operand 3 "const_int_operand")
|
|
|
|
|
(match_operand 4 "const_int_operand")))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
|
|
|
|
|
operands[0], operands[2], operands[3],
|
|
|
|
|
operands[4]))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_sadd_di"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(plus:DI (if_then_else:DI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:DI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:DI 4 "sext_add_operand" "rIO")))
|
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(plus:DI (ashift:DI (match_dup 5) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4)))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2000-05-29 09:52:26 +02:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
|
|
|
|
operands[5] = operands[0];
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_sadd_si"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
|
(plus:SI (if_then_else:SI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:SI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:SI 4 "sext_add_operand" "rIO")))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(plus:SI (ashift:SI (match_dup 6) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4)))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
2000-05-29 09:52:26 +02:00
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_lowpart (DImode, operands[0]);
|
|
|
|
|
|
|
|
|
|
operands[6] = gen_lowpart (SImode, operands[5]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_sadd_sidi"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(plus:SI (if_then_else:SI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:SI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:SI 4 "sext_add_operand" "rIO"))))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4))))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
2000-05-29 09:52:26 +02:00
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = operands[0];
|
|
|
|
|
|
|
|
|
|
operands[6] = gen_lowpart (SImode, operands[5]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_ssub_di"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(minus:DI (if_then_else:DI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:DI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:DI 4 "reg_or_8bit_operand" "rI")))
|
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(minus:DI (ashift:DI (match_dup 5) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4)))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2000-05-29 09:52:26 +02:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
|
|
|
|
operands[5] = operands[0];
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_ssub_si"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
|
|
(minus:SI (if_then_else:SI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:SI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:SI 4 "reg_or_8bit_operand" "rI")))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(minus:SI (ashift:SI (match_dup 6) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4)))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
2000-05-29 09:52:26 +02:00
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_lowpart (DImode, operands[0]);
|
|
|
|
|
|
|
|
|
|
operands[6] = gen_lowpart (SImode, operands[5]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-29 09:52:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*cmp_ssub_sidi"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(minus:SI (if_then_else:SI
|
|
|
|
|
(match_operator 1 "alpha_zero_comparison_operator"
|
|
|
|
|
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
|
|
|
|
|
(const_int 0)])
|
|
|
|
|
(match_operand:SI 3 "const48_operand" "I")
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(clobber (match_scratch:DI 5 "=r"))]
|
2000-05-29 09:52:26 +02:00
|
|
|
|
""
|
|
|
|
|
"#"
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
""
|
2000-05-29 09:52:26 +02:00
|
|
|
|
[(set (match_dup 5)
|
2010-03-26 19:45:56 +01:00
|
|
|
|
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(set (match_dup 0)
|
2018-01-07 20:14:55 +01:00
|
|
|
|
(sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
|
2000-05-29 09:52:26 +02:00
|
|
|
|
(match_dup 4))))]
|
|
|
|
|
{
|
2018-01-07 20:14:55 +01:00
|
|
|
|
operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
if (can_create_pseudo_p ())
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = gen_reg_rtx (DImode);
|
2000-05-29 09:52:26 +02:00
|
|
|
|
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
|
2010-03-26 19:45:56 +01:00
|
|
|
|
operands[5] = operands[0];
|
|
|
|
|
|
|
|
|
|
operands[6] = gen_lowpart (SImode, operands[5]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1995-04-13 14:46:37 +02:00
|
|
|
|
;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
|
|
|
|
|
;; work differently, so we have different patterns for each.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "call"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(use (match_operand:DI 0))
|
|
|
|
|
(use (match_operand 1))
|
|
|
|
|
(use (match_operand 2))
|
|
|
|
|
(use (match_operand 3))]
|
1995-04-13 14:46:37 +02:00
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2011-03-22 23:28:18 +01:00
|
|
|
|
if (TARGET_ABI_OPEN_VMS)
|
1996-11-16 12:07:51 +01:00
|
|
|
|
emit_call_insn (gen_call_vms (operands[0], operands[2]));
|
1995-04-13 14:46:37 +02:00
|
|
|
|
else
|
|
|
|
|
emit_call_insn (gen_call_osf (operands[0], operands[1]));
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1995-04-13 14:46:37 +02:00
|
|
|
|
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_expand "sibcall"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_operand 0))
|
|
|
|
|
(match_operand 1))
|
2001-12-24 04:08:23 +01:00
|
|
|
|
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OSF"
|
2000-03-17 23:41:25 +01:00
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
gcc_assert (MEM_P (operands[0]));
|
2000-03-17 23:41:25 +01:00
|
|
|
|
operands[0] = XEXP (operands[0], 0);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-03-17 23:41:25 +01:00
|
|
|
|
|
1995-04-13 14:46:37 +02:00
|
|
|
|
(define_expand "call_osf"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_operand 0))
|
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(clobber (reg:DI 26))])]
|
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
gcc_assert (MEM_P (operands[0]));
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1994-08-24 23:15:04 +02:00
|
|
|
|
operands[0] = XEXP (operands[0], 0);
|
2001-09-19 20:55:22 +02:00
|
|
|
|
if (! call_operand (operands[0], Pmode))
|
2001-12-21 01:22:39 +01:00
|
|
|
|
operands[0] = copy_to_mode_reg (Pmode, operands[0]);
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
1996-11-16 12:07:51 +01:00
|
|
|
|
;;
|
|
|
|
|
;; call openvms/alpha
|
|
|
|
|
;; op 0: symbol ref for called function
|
|
|
|
|
;; op 1: next_arg_reg (argument information value for R25)
|
|
|
|
|
;;
|
|
|
|
|
(define_expand "call_vms"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_operand 0))
|
|
|
|
|
(match_operand 1))
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(use (match_dup 2))
|
|
|
|
|
(use (reg:DI 25))
|
|
|
|
|
(use (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))])]
|
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
gcc_assert (MEM_P (operands[0]));
|
1996-11-16 12:07:51 +01:00
|
|
|
|
|
|
|
|
|
operands[0] = XEXP (operands[0], 0);
|
|
|
|
|
|
|
|
|
|
/* Always load AI with argument information, then handle symbolic and
|
|
|
|
|
indirect call differently. Load RA and set operands[2] to PV in
|
|
|
|
|
both cases. */
|
|
|
|
|
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
|
1996-11-16 12:07:51 +01:00
|
|
|
|
if (GET_CODE (operands[0]) == SYMBOL_REF)
|
|
|
|
|
{
|
2002-08-15 07:04:27 +02:00
|
|
|
|
operands[2] = const0_rtx;
|
1996-11-16 12:07:51 +01:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
emit_move_insn (gen_rtx_REG (Pmode, 26),
|
rtl.h (plus_constant, [...]): Merge into a single plus_constant function.
gcc/
* rtl.h (plus_constant, plus_constant_mode): Merge into a single
plus_constant function.
* explow.c (plus_constant, plus_constant_mode): Likewise. Assert
that the mode is sensible.
(use_anchored_address, round_push, allocate_dynamic_stack_space)
(probe_stack_range, anti_adjust_stack_and_probe): Update calls to
plus_constant.
* alias.c (canon_rtx): Likewise.
(init_alias_analysis): Likewise.
* builtins.c (expand_builtin_return_addr)
(expand_builtin_setjmp_setup, expand_builtin_longjmp)
(expand_builtin_nonlocal_goto, expand_builtin_update_setjmp_buf)
(expand_builtin_apply_args_1, expand_builtin_apply, expand_movstr)
(expand_builtin_stpcpy): Likewise.
* calls.c (save_fixed_argument_area, restore_fixed_argument_area)
(compute_argument_addresses, internal_arg_pointer_based_exp)
(expand_call, emit_library_call_value_1): Likewise.
* cfgexpand.c (expand_one_stack_var_at, expand_debug_expr): Likewise.
* combine-stack-adj.c (try_apply_stack_adjustment): Likewise.
* combine.c (combine_simplify_rtx, force_to_mode): Likewise.
* cse.c (insert_const_anchor, find_reg_offset_for_const)
(use_related_value, fold_rtx): Likewise.
* cselib.c (cselib_subst_to_values): Likewise.
* dse.c (record_store, check_mem_read_rtx): Likewise.
* dwarf2out.c (rtl_for_decl_location, gen_variable_die): Likewise.
* emit-rtl.c (adjust_address_1): Likewise.
* except.c (sjlj_emit_function_enter)
(expand_builtin_extract_return_addr)
(expand_builtin_frob_return_addr): Likewise.
* expmed.c (expand_divmod): Likewise.
* expr.c (move_by_pieces, store_by_pieces, store_by_pieces_1)
(emit_move_resolve_push, push_block, emit_push_insn, store_expr)
(expand_expr_addr_expr_1, expand_expr_real_1): Likewise.
* function.c (assign_stack_local_1)
(instantiate_virtual_regs_in_rtx): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* reload.c (find_reloads_address, form_sum)
(find_reloads_subreg_address): Likewise.
* reload1.c (init_reload, eliminate_regs_1)
(eliminate_regs_in_insn): Likewise.
* simplify-rtx.c (simplify_unary_operation_1)
(simplify_binary_operation_1, simplify_plus_minus): Likewise.
* var-tracking.c (compute_cfa_pointer, prepare_call_arguments)
(vt_add_function_parameter): Likewise.
* config/alpha/alpha.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/vms.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address_1)
(get_unaligned_address, alpha_expand_unaligned_load)
(alpha_expand_unaligned_store, alpha_expand_unaligned_load_words)
(alpha_expand_unaligned_store_words, alpha_expand_block_clear)
(alpha_expand_builtin_establish_vms_condition_handler)
(alpha_setup_incoming_varargs, emit_frame_store_1)
(alpha_expand_prologue, alpha_expand_epilogue)
(alpha_use_linkage): Likewise.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c (arm_trampoline_init, legitimize_pic_address)
(arm_load_pic_register, arm_pic_static_addr, arm_legitimize_address)
(thumb_legitimize_address, arm_gen_load_multiple_1)
(arm_gen_store_multiple_1, arm_gen_multiple_op, gen_ldm_seq)
(gen_stm_seq, gen_const_stm_seq, arm_block_move_unaligned_straight)
(arm_block_move_unaligned_loop, arm_gen_movmemqi, arm_reload_in_hi)
(arm_reload_out_hi, arm_reorg, vfp_emit_fstmd, emit_multi_reg_push)
(emit_sfm, thumb_set_frame_pointer, arm_expand_prologue)
(thumb1_emit_multi_reg_push, thumb1_expand_prologue)
(thumb_expand_movmemqi, arm_set_return_address)
(thumb_set_return_address): Likewise.
* config/arm/arm.md: Likewise.
* config/avr/avr.c (avr_incoming_return_addr_rtx)
(avr_prologue_setup_frame, expand_epilogue)
(avr_const_address_lo16): Likewise.
* config/bfin/bfin.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/bfin/bfin.c (setup_incoming_varargs, bfin_load_pic_reg)
(bfin_expand_prologue, bfin_trampoline_init, bfin_expand_call)
(bfin_output_mi_thunk): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline)
(c6x_output_mi_thunk): Likewise.
* config/cr16/cr16.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
* config/cris/cris.c (cris_return_addr_rtx, cris_split_movdx)
(cris_expand_prologue, cris_expand_epilogue, cris_gen_movem_load)
(cris_emit_movem_store, cris_trampoline_init): Likewise.
* config/cris/cris.md: Likewise.
* config/darwin.c (machopic_indirect_data_reference)
(machopic_legitimize_pic_address): Likewise.
* config/epiphany/epiphany.c (epiphany_emit_save_restore)
(epiphany_expand_prologue, epiphany_expand_epilogue)
(epiphany_trampoline_init): Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/fr30/fr30.c (fr30_move_double): Likewise.
* config/frv/frv.c (frv_dwarf_store, frv_expand_prologue)
(frv_expand_block_move, frv_expand_block_clear, frv_return_addr_rtx)
(frv_index_memory, unspec_got_name, frv_find_base_term)
(frv_output_dwarf_dtprel): Likewise.
* config/h8300/h8300.c (h8300_push_pop, h8300_return_addr_rtx)
(h8300_swap_into_er6, h8300_swap_out_of_er6): Likewise.
* config/i386/i386.h (RETURN_ADDR_RTX): Likewise.
* config/i386/i386.c (setup_incoming_varargs_64)
(setup_incoming_varargs_ms_64, choose_baseaddr)
(ix86_emit_save_reg_using_mov, ix86_adjust_stack_and_probe)
(ix86_emit_probe_stack_range, ix86_expand_prologue)
(ix86_emit_restore_reg_using_pop, ix86_emit_leave)
(ix86_expand_epilogue, legitimize_pic_address, ix86_legitimize_address)
(ix86_split_long_move, ix86_expand_movmem, ix86_expand_setmem)
(ix86_static_chain, ix86_trampoline_init, x86_this_parameter)
(x86_output_mi_thunk): Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (ia64_expand_load_address)
(ia64_expand_tls_address, ia64_expand_move, ia64_split_tmode)
(do_spill, ia64_trampoline_init): Likewise.
* config/iq2000/iq2000.c (iq2000_va_start)
(iq2000_emit_frame_related_store, iq2000_expand_prologue)
(iq2000_expand_eh_return, iq2000_setup_incoming_varargs)
(iq2000_print_operand, iq2000_legitimize_address): Likewise.
* config/lm32/lm32.c (lm32_setup_incoming_varargs): Likewise.
* config/m32c/m32c.c (m32c_return_addr_rtx)
(m32c_expand_insv): Likewise.
* config/m32r/m32r.c (m32r_setup_incoming_varargs)
(m32r_legitimize_pic_address, m32r_print_operand)
(m32r_print_operand_address): Likewise.
* config/m68k/linux.h (FINALIZE_TRAMPOLINE): Likewise.
* config/m68k/m68k.h (RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/m68k/m68k.c (m68k_emit_movem, m68k_expand_prologue)
(m68k_expand_epilogue, legitimize_pic_address)
(m68k_output_mi_thunk): Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c (mcore_expand_prolog): Likewise.
(mcore_expand_epilog): Likewise.
* config/mcore/mcore.md: Likewise.
* config/mep/mep.c (mep_allocate_initial_value)
(mep_expand_prologue, mep_expand_epilogue): Likewise.
* config/microblaze/microblaze.c (double_memory_operand)
(microblaze_block_move_loop): Likewise.
* config/mips/mips.c (mips_strip_unspec_address, mips_add_offset)
(mips_setup_incoming_varargs, mips_va_start, mips_block_move_loop)
(mips_print_operand, mips16e_save_restore_reg, mips_save_restore_reg)
(mips_expand_prologue, mips_epilogue_set_cfa)
(mips_expand_epilogue): Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c (mmix_dynamic_chain_address, mmix_return_addr_rtx)
(mmix_expand_prologue, mmix_expand_epilogue): Likewise.
* config/mn10300/mn10300.c (mn10300_gen_multiple_store)
(mn10300_builtin_saveregs, mn10300_trampoline_init): Likewise.
* config/moxie/moxie.h (INCOMING_RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/moxie/moxie.c (moxie_static_chain): Likewise.
* config/pa/pa.c (legitimize_pic_address, hppa_legitimize_address)
(store_reg, set_reg_plus_d, pa_expand_prologue, load_reg)
(pa_return_addr_rtx, hppa_builtin_saveregs)
(pa_trampoline_init): Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c (pdp11_expand_epilogue): Likewise.
* config/picochip/picochip.c (picochip_static_chain): Likewise.
* config/rs6000/rs6000.h (RS6000_SAVE_TOC): Likewise.
* config/rs6000/rs6000.c (rs6000_legitimize_address)
(setup_incoming_varargs, print_operand, rs6000_return_addr)
(rs6000_emit_eh_reg_restore, rs6000_emit_probe_stack_range)
(rs6000_emit_epilogue)
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rx/rx.c (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
* config/s390/s390.h (INITIAL_FRAME_ADDRESS_RTX): Likewise.
(DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/s390/s390.c (s390_decompose_address, legitimize_pic_address)
(s390_delegitimize_address, print_operand, annotate_constant_pool_refs)
(replace_constant_pool_ref, s390_return_addr_rtx, s390_back_chain_rtx)
(save_fpr, restore_fpr, save_gprs, restore_gprs, s390_emit_prologue)
(s390_emit_epilogue, s390_function_profiler): Likewise.
* config/s390/s390.md: Likewise.
* config/score/score.c (score_add_offset, score_prologue): Likewise.
* config/sh/sh.c (expand_block_move, push_regs, sh_builtin_saveregs)
(sh_output_mi_thunk): Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/sparc.h (DYNAMIC_CHAIN_ADDRESS, FRAME_ADDR_RTX)
(RETURN_ADDR_RTX, INCOMING_RETURN_ADDR_RTX): Likewise.
* config/sparc/sparc.c (sparc_legitimize_pic_address)
(sparc_emit_probe_stack_range, emit_save_or_restore_regs)
(emit_window_save, sparc_flat_expand_prologue, sparc_struct_value_rtx)
(emit_and_preserve): Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/spu/spu.c (spu_expand_insv, spu_machine_dependent_reorg)
(spu_setup_incoming_varargs, ea_load_store_inline)
(spu_expand_load): Likewise.
* config/stormy16/stormy16.c (xstormy16_expand_prologue)
(combine_bnp): Likewise.
* config/tilegx/tilegx.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilegx/tilegx.c (tilegx_setup_incoming_varargs)
(tilegx_expand_unaligned_load, tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilepro/tilepro.c (tilepro_setup_incoming_varargs)
(tilepro_expand_unaligned_load, tilepro_trampoline_init): Likewise.
* config/v850/v850.c (expand_prologue, expand_epilogue): Likewise.
* config/v850/v850.md: Likewise.
* config/vax/elf.h (EH_RETURN_STACKADJ_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/vax/vax.h (DYNAMIC_CHAIN_ADDRESS, RETURN_ADDR_RTX): Likewise.
* config/vax/vax.c (vax_add_reg_cfa_offset, vax_expand_prologue)
(print_operand_address, vax_trampoline_init): Likewise.
* config/xtensa/xtensa.c (xtensa_expand_prologue, xtensa_return_addr)
(xtensa_function_value_regno_p): Likewise.
From-SVN: r187199
2012-05-05 19:41:49 +02:00
|
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gen_rtx_MEM (Pmode, plus_constant (Pmode,
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operands[0], 8)));
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1996-11-16 12:07:51 +01:00
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operands[2] = operands[0];
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}
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2001-07-15 17:38:52 +02:00
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})
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1996-11-16 12:07:51 +01:00
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1992-10-24 15:33:28 +01:00
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(define_expand "call_value"
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2012-10-14 14:50:45 +02:00
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[(use (match_operand 0))
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(use (match_operand:DI 1))
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(use (match_operand 2))
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(use (match_operand 3))
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(use (match_operand 4))]
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1995-04-13 14:46:37 +02:00
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""
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2001-07-15 09:17:29 +02:00
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{
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2011-03-22 23:28:18 +01:00
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if (TARGET_ABI_OPEN_VMS)
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1996-11-16 12:07:51 +01:00
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emit_call_insn (gen_call_value_vms (operands[0], operands[1],
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operands[3]));
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1995-04-13 14:46:37 +02:00
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else
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emit_call_insn (gen_call_value_osf (operands[0], operands[1],
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operands[2]));
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DONE;
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2001-07-15 17:38:52 +02:00
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})
|
1995-04-13 14:46:37 +02:00
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2000-03-17 23:41:25 +01:00
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(define_expand "sibcall_value"
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2012-10-14 14:50:45 +02:00
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[(parallel [(set (match_operand 0)
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(call (mem:DI (match_operand 1))
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(match_operand 2)))
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2001-12-24 04:08:23 +01:00
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(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
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2001-07-15 09:17:29 +02:00
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"TARGET_ABI_OSF"
|
2000-03-17 23:41:25 +01:00
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{
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2009-04-22 10:19:54 +02:00
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gcc_assert (MEM_P (operands[1]));
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2000-03-17 23:41:25 +01:00
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operands[1] = XEXP (operands[1], 0);
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2001-07-15 17:38:52 +02:00
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})
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2000-03-17 23:41:25 +01:00
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1995-04-13 14:46:37 +02:00
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(define_expand "call_value_osf"
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2012-10-14 14:50:45 +02:00
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[(parallel [(set (match_operand 0)
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(call (mem:DI (match_operand 1))
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(match_operand 2)))
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2001-09-19 20:55:22 +02:00
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(use (reg:DI 29))
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1992-10-24 15:33:28 +01:00
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(clobber (reg:DI 26))])]
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""
|
2001-07-15 17:38:52 +02:00
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{
|
2009-04-22 10:19:54 +02:00
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gcc_assert (MEM_P (operands[1]));
|
1992-10-24 15:33:28 +01:00
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operands[1] = XEXP (operands[1], 0);
|
2001-09-19 20:55:22 +02:00
|
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if (! call_operand (operands[1], Pmode))
|
2001-12-21 01:22:39 +01:00
|
|
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|
operands[1] = copy_to_mode_reg (Pmode, operands[1]);
|
2001-07-15 17:38:52 +02:00
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|
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})
|
1992-10-24 15:33:28 +01:00
|
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1996-11-16 12:07:51 +01:00
|
|
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(define_expand "call_value_vms"
|
2012-10-14 14:50:45 +02:00
|
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[(parallel [(set (match_operand 0)
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(call (mem:DI (match_operand:DI 1))
|
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(match_operand 2)))
|
1996-11-16 12:07:51 +01:00
|
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(use (match_dup 3))
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|
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|
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(use (reg:DI 25))
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|
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(use (reg:DI 26))
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|
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(clobber (reg:DI 27))])]
|
|
|
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""
|
2001-07-15 17:38:52 +02:00
|
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{
|
2009-04-22 10:19:54 +02:00
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gcc_assert (MEM_P (operands[1]));
|
1996-11-16 12:07:51 +01:00
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operands[1] = XEXP (operands[1], 0);
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/* Always load AI with argument information, then handle symbolic and
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indirect call differently. Load RA and set operands[3] to PV in
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both cases. */
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alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
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emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
|
1996-11-16 12:07:51 +01:00
|
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if (GET_CODE (operands[1]) == SYMBOL_REF)
|
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{
|
2002-08-15 07:04:27 +02:00
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operands[3] = const0_rtx;
|
1996-11-16 12:07:51 +01:00
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}
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else
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{
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
emit_move_insn (gen_rtx_REG (Pmode, 26),
|
rtl.h (plus_constant, [...]): Merge into a single plus_constant function.
gcc/
* rtl.h (plus_constant, plus_constant_mode): Merge into a single
plus_constant function.
* explow.c (plus_constant, plus_constant_mode): Likewise. Assert
that the mode is sensible.
(use_anchored_address, round_push, allocate_dynamic_stack_space)
(probe_stack_range, anti_adjust_stack_and_probe): Update calls to
plus_constant.
* alias.c (canon_rtx): Likewise.
(init_alias_analysis): Likewise.
* builtins.c (expand_builtin_return_addr)
(expand_builtin_setjmp_setup, expand_builtin_longjmp)
(expand_builtin_nonlocal_goto, expand_builtin_update_setjmp_buf)
(expand_builtin_apply_args_1, expand_builtin_apply, expand_movstr)
(expand_builtin_stpcpy): Likewise.
* calls.c (save_fixed_argument_area, restore_fixed_argument_area)
(compute_argument_addresses, internal_arg_pointer_based_exp)
(expand_call, emit_library_call_value_1): Likewise.
* cfgexpand.c (expand_one_stack_var_at, expand_debug_expr): Likewise.
* combine-stack-adj.c (try_apply_stack_adjustment): Likewise.
* combine.c (combine_simplify_rtx, force_to_mode): Likewise.
* cse.c (insert_const_anchor, find_reg_offset_for_const)
(use_related_value, fold_rtx): Likewise.
* cselib.c (cselib_subst_to_values): Likewise.
* dse.c (record_store, check_mem_read_rtx): Likewise.
* dwarf2out.c (rtl_for_decl_location, gen_variable_die): Likewise.
* emit-rtl.c (adjust_address_1): Likewise.
* except.c (sjlj_emit_function_enter)
(expand_builtin_extract_return_addr)
(expand_builtin_frob_return_addr): Likewise.
* expmed.c (expand_divmod): Likewise.
* expr.c (move_by_pieces, store_by_pieces, store_by_pieces_1)
(emit_move_resolve_push, push_block, emit_push_insn, store_expr)
(expand_expr_addr_expr_1, expand_expr_real_1): Likewise.
* function.c (assign_stack_local_1)
(instantiate_virtual_regs_in_rtx): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* reload.c (find_reloads_address, form_sum)
(find_reloads_subreg_address): Likewise.
* reload1.c (init_reload, eliminate_regs_1)
(eliminate_regs_in_insn): Likewise.
* simplify-rtx.c (simplify_unary_operation_1)
(simplify_binary_operation_1, simplify_plus_minus): Likewise.
* var-tracking.c (compute_cfa_pointer, prepare_call_arguments)
(vt_add_function_parameter): Likewise.
* config/alpha/alpha.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/vms.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address_1)
(get_unaligned_address, alpha_expand_unaligned_load)
(alpha_expand_unaligned_store, alpha_expand_unaligned_load_words)
(alpha_expand_unaligned_store_words, alpha_expand_block_clear)
(alpha_expand_builtin_establish_vms_condition_handler)
(alpha_setup_incoming_varargs, emit_frame_store_1)
(alpha_expand_prologue, alpha_expand_epilogue)
(alpha_use_linkage): Likewise.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c (arm_trampoline_init, legitimize_pic_address)
(arm_load_pic_register, arm_pic_static_addr, arm_legitimize_address)
(thumb_legitimize_address, arm_gen_load_multiple_1)
(arm_gen_store_multiple_1, arm_gen_multiple_op, gen_ldm_seq)
(gen_stm_seq, gen_const_stm_seq, arm_block_move_unaligned_straight)
(arm_block_move_unaligned_loop, arm_gen_movmemqi, arm_reload_in_hi)
(arm_reload_out_hi, arm_reorg, vfp_emit_fstmd, emit_multi_reg_push)
(emit_sfm, thumb_set_frame_pointer, arm_expand_prologue)
(thumb1_emit_multi_reg_push, thumb1_expand_prologue)
(thumb_expand_movmemqi, arm_set_return_address)
(thumb_set_return_address): Likewise.
* config/arm/arm.md: Likewise.
* config/avr/avr.c (avr_incoming_return_addr_rtx)
(avr_prologue_setup_frame, expand_epilogue)
(avr_const_address_lo16): Likewise.
* config/bfin/bfin.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/bfin/bfin.c (setup_incoming_varargs, bfin_load_pic_reg)
(bfin_expand_prologue, bfin_trampoline_init, bfin_expand_call)
(bfin_output_mi_thunk): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline)
(c6x_output_mi_thunk): Likewise.
* config/cr16/cr16.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
* config/cris/cris.c (cris_return_addr_rtx, cris_split_movdx)
(cris_expand_prologue, cris_expand_epilogue, cris_gen_movem_load)
(cris_emit_movem_store, cris_trampoline_init): Likewise.
* config/cris/cris.md: Likewise.
* config/darwin.c (machopic_indirect_data_reference)
(machopic_legitimize_pic_address): Likewise.
* config/epiphany/epiphany.c (epiphany_emit_save_restore)
(epiphany_expand_prologue, epiphany_expand_epilogue)
(epiphany_trampoline_init): Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/fr30/fr30.c (fr30_move_double): Likewise.
* config/frv/frv.c (frv_dwarf_store, frv_expand_prologue)
(frv_expand_block_move, frv_expand_block_clear, frv_return_addr_rtx)
(frv_index_memory, unspec_got_name, frv_find_base_term)
(frv_output_dwarf_dtprel): Likewise.
* config/h8300/h8300.c (h8300_push_pop, h8300_return_addr_rtx)
(h8300_swap_into_er6, h8300_swap_out_of_er6): Likewise.
* config/i386/i386.h (RETURN_ADDR_RTX): Likewise.
* config/i386/i386.c (setup_incoming_varargs_64)
(setup_incoming_varargs_ms_64, choose_baseaddr)
(ix86_emit_save_reg_using_mov, ix86_adjust_stack_and_probe)
(ix86_emit_probe_stack_range, ix86_expand_prologue)
(ix86_emit_restore_reg_using_pop, ix86_emit_leave)
(ix86_expand_epilogue, legitimize_pic_address, ix86_legitimize_address)
(ix86_split_long_move, ix86_expand_movmem, ix86_expand_setmem)
(ix86_static_chain, ix86_trampoline_init, x86_this_parameter)
(x86_output_mi_thunk): Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (ia64_expand_load_address)
(ia64_expand_tls_address, ia64_expand_move, ia64_split_tmode)
(do_spill, ia64_trampoline_init): Likewise.
* config/iq2000/iq2000.c (iq2000_va_start)
(iq2000_emit_frame_related_store, iq2000_expand_prologue)
(iq2000_expand_eh_return, iq2000_setup_incoming_varargs)
(iq2000_print_operand, iq2000_legitimize_address): Likewise.
* config/lm32/lm32.c (lm32_setup_incoming_varargs): Likewise.
* config/m32c/m32c.c (m32c_return_addr_rtx)
(m32c_expand_insv): Likewise.
* config/m32r/m32r.c (m32r_setup_incoming_varargs)
(m32r_legitimize_pic_address, m32r_print_operand)
(m32r_print_operand_address): Likewise.
* config/m68k/linux.h (FINALIZE_TRAMPOLINE): Likewise.
* config/m68k/m68k.h (RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/m68k/m68k.c (m68k_emit_movem, m68k_expand_prologue)
(m68k_expand_epilogue, legitimize_pic_address)
(m68k_output_mi_thunk): Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c (mcore_expand_prolog): Likewise.
(mcore_expand_epilog): Likewise.
* config/mcore/mcore.md: Likewise.
* config/mep/mep.c (mep_allocate_initial_value)
(mep_expand_prologue, mep_expand_epilogue): Likewise.
* config/microblaze/microblaze.c (double_memory_operand)
(microblaze_block_move_loop): Likewise.
* config/mips/mips.c (mips_strip_unspec_address, mips_add_offset)
(mips_setup_incoming_varargs, mips_va_start, mips_block_move_loop)
(mips_print_operand, mips16e_save_restore_reg, mips_save_restore_reg)
(mips_expand_prologue, mips_epilogue_set_cfa)
(mips_expand_epilogue): Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c (mmix_dynamic_chain_address, mmix_return_addr_rtx)
(mmix_expand_prologue, mmix_expand_epilogue): Likewise.
* config/mn10300/mn10300.c (mn10300_gen_multiple_store)
(mn10300_builtin_saveregs, mn10300_trampoline_init): Likewise.
* config/moxie/moxie.h (INCOMING_RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/moxie/moxie.c (moxie_static_chain): Likewise.
* config/pa/pa.c (legitimize_pic_address, hppa_legitimize_address)
(store_reg, set_reg_plus_d, pa_expand_prologue, load_reg)
(pa_return_addr_rtx, hppa_builtin_saveregs)
(pa_trampoline_init): Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c (pdp11_expand_epilogue): Likewise.
* config/picochip/picochip.c (picochip_static_chain): Likewise.
* config/rs6000/rs6000.h (RS6000_SAVE_TOC): Likewise.
* config/rs6000/rs6000.c (rs6000_legitimize_address)
(setup_incoming_varargs, print_operand, rs6000_return_addr)
(rs6000_emit_eh_reg_restore, rs6000_emit_probe_stack_range)
(rs6000_emit_epilogue)
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rx/rx.c (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
* config/s390/s390.h (INITIAL_FRAME_ADDRESS_RTX): Likewise.
(DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/s390/s390.c (s390_decompose_address, legitimize_pic_address)
(s390_delegitimize_address, print_operand, annotate_constant_pool_refs)
(replace_constant_pool_ref, s390_return_addr_rtx, s390_back_chain_rtx)
(save_fpr, restore_fpr, save_gprs, restore_gprs, s390_emit_prologue)
(s390_emit_epilogue, s390_function_profiler): Likewise.
* config/s390/s390.md: Likewise.
* config/score/score.c (score_add_offset, score_prologue): Likewise.
* config/sh/sh.c (expand_block_move, push_regs, sh_builtin_saveregs)
(sh_output_mi_thunk): Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/sparc.h (DYNAMIC_CHAIN_ADDRESS, FRAME_ADDR_RTX)
(RETURN_ADDR_RTX, INCOMING_RETURN_ADDR_RTX): Likewise.
* config/sparc/sparc.c (sparc_legitimize_pic_address)
(sparc_emit_probe_stack_range, emit_save_or_restore_regs)
(emit_window_save, sparc_flat_expand_prologue, sparc_struct_value_rtx)
(emit_and_preserve): Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/spu/spu.c (spu_expand_insv, spu_machine_dependent_reorg)
(spu_setup_incoming_varargs, ea_load_store_inline)
(spu_expand_load): Likewise.
* config/stormy16/stormy16.c (xstormy16_expand_prologue)
(combine_bnp): Likewise.
* config/tilegx/tilegx.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilegx/tilegx.c (tilegx_setup_incoming_varargs)
(tilegx_expand_unaligned_load, tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilepro/tilepro.c (tilepro_setup_incoming_varargs)
(tilepro_expand_unaligned_load, tilepro_trampoline_init): Likewise.
* config/v850/v850.c (expand_prologue, expand_epilogue): Likewise.
* config/v850/v850.md: Likewise.
* config/vax/elf.h (EH_RETURN_STACKADJ_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/vax/vax.h (DYNAMIC_CHAIN_ADDRESS, RETURN_ADDR_RTX): Likewise.
* config/vax/vax.c (vax_add_reg_cfa_offset, vax_expand_prologue)
(print_operand_address, vax_trampoline_init): Likewise.
* config/xtensa/xtensa.c (xtensa_expand_prologue, xtensa_return_addr)
(xtensa_function_value_regno_p): Likewise.
From-SVN: r187199
2012-05-05 19:41:49 +02:00
|
|
|
|
gen_rtx_MEM (Pmode, plus_constant (Pmode,
|
|
|
|
|
operands[1], 8)));
|
1996-11-16 12:07:51 +01:00
|
|
|
|
operands[3] = operands[1];
|
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1996-11-16 12:07:51 +01:00
|
|
|
|
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(define_insn "*call_osf_1_er_noreturn"
|
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
|
|
|
|
|
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
|
|
|
|
|
"@
|
|
|
|
|
jsr $26,($27),0
|
|
|
|
|
bsr $26,%0\t\t!samegp
|
|
|
|
|
ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,*,8")])
|
|
|
|
|
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
(define_insn "*call_osf_1_er"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"@
|
2001-09-19 20:55:22 +02:00
|
|
|
|
jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
|
2002-12-20 20:42:41 +01:00
|
|
|
|
bsr $26,%0\t\t!samegp
|
2001-12-16 06:40:26 +01:00
|
|
|
|
ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "12,*,16")])
|
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
;; We must use peep2 instead of a split because we need accurate life
|
|
|
|
|
;; information for $gp. Consider the case of { bar(); while (1); }.
|
|
|
|
|
(define_peephole2
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
|
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
|
2002-12-20 20:42:41 +01:00
|
|
|
|
&& ! samegp_function_operand (operands[0], Pmode)
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
&& (peep2_regno_dead_p (1, 29)
|
|
|
|
|
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_dup 2))
|
|
|
|
|
(match_dup 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
2002-01-11 04:47:24 +01:00
|
|
|
|
(use (match_dup 0))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (match_dup 3))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
{
|
|
|
|
|
if (CONSTANT_P (operands[0]))
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_rtx_REG (Pmode, 27);
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[3] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
|
|
|
|
|
operands[0], operands[3]));
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[2] = operands[0];
|
|
|
|
|
operands[0] = const0_rtx;
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[3] = const0_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_peephole2
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
|
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
|
2002-12-20 20:42:41 +01:00
|
|
|
|
&& ! samegp_function_operand (operands[0], Pmode)
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
&& ! (peep2_regno_dead_p (1, 29)
|
|
|
|
|
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(parallel [(call (mem:DI (match_dup 2))
|
|
|
|
|
(match_dup 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set (match_dup 5)
|
|
|
|
|
(unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
|
2002-01-11 04:47:24 +01:00
|
|
|
|
(use (match_dup 0))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (match_dup 4))
|
|
|
|
|
(clobber (reg:DI 26))])
|
|
|
|
|
(set (match_dup 5)
|
|
|
|
|
(unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
{
|
|
|
|
|
if (CONSTANT_P (operands[0]))
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_rtx_REG (Pmode, 27);
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
|
|
|
|
|
operands[0], operands[4]));
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[2] = operands[0];
|
|
|
|
|
operands[0] = const0_rtx;
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[4] = const0_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
operands[3] = GEN_INT (alpha_next_sequence_number++);
|
2007-04-06 00:39:56 +02:00
|
|
|
|
operands[5] = pic_offset_table_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
})
|
|
|
|
|
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(define_insn "*call_osf_2_er_nogp"
|
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 2))
|
|
|
|
|
(use (match_operand 3 "const_int_operand"))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"jsr $26,(%0),%2%J3"
|
|
|
|
|
[(set_attr "type" "jsr")])
|
2001-09-19 20:55:22 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "*call_osf_2_er"
|
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set (reg:DI 29)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")]
|
2007-04-06 00:39:56 +02:00
|
|
|
|
UNSPEC_LDGP1))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 2))
|
|
|
|
|
(use (match_operand 3 "const_int_operand"))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2007-04-06 00:39:56 +02:00
|
|
|
|
"jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
[(set_attr "type" "jsr")
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set_attr "cannot_copy" "true")
|
|
|
|
|
(set_attr "length" "8")])
|
2003-03-06 01:32:29 +01:00
|
|
|
|
|
2001-03-07 19:50:26 +01:00
|
|
|
|
(define_insn "*call_osf_1_noreturn"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
2001-03-07 19:50:26 +01:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
|
|
|
|
|
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
|
2001-03-07 19:50:26 +01:00
|
|
|
|
"@
|
2007-04-06 00:39:56 +02:00
|
|
|
|
jsr $26,($27),0
|
|
|
|
|
bsr $26,$%0..ng
|
|
|
|
|
jsr $26,%0"
|
2001-03-07 19:50:26 +01:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,*,8")])
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*call_osf_1"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
1994-08-24 23:15:04 +02:00
|
|
|
|
"@
|
|
|
|
|
jsr $26,($27),0\;ldgp $29,0($26)
|
1997-11-14 15:43:14 +01:00
|
|
|
|
bsr $26,$%0..ng
|
1994-08-24 23:15:04 +02:00
|
|
|
|
jsr $26,%0\;ldgp $29,0($26)"
|
1998-06-16 19:08:48 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
1998-11-09 01:40:57 +01:00
|
|
|
|
(set_attr "length" "12,*,16")])
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
2001-12-16 06:40:26 +01:00
|
|
|
|
(define_insn "*sibcall_osf_1_er"
|
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2001-12-24 04:08:23 +01:00
|
|
|
|
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
|
2001-12-16 06:40:26 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"@
|
2002-12-20 20:42:41 +01:00
|
|
|
|
br $31,%0\t\t!samegp
|
2001-12-16 06:40:26 +01:00
|
|
|
|
ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,8")])
|
|
|
|
|
|
2007-04-06 00:39:56 +02:00
|
|
|
|
;; Note that the DEC assembler expands "jmp foo" with $at, which
|
|
|
|
|
;; doesn't do what we want.
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*sibcall_osf_1"
|
2001-11-28 19:36:14 +01:00
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2001-12-24 04:08:23 +01:00
|
|
|
|
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
|
2001-12-16 06:40:26 +01:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2001-10-17 00:44:39 +02:00
|
|
|
|
"@
|
|
|
|
|
br $31,$%0..ng
|
2001-10-19 07:04:54 +02:00
|
|
|
|
lda $27,%0\;jmp $31,($27),%0"
|
2001-10-17 00:44:39 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,8")])
|
2000-03-17 23:41:25 +01:00
|
|
|
|
|
2002-08-15 07:04:27 +02:00
|
|
|
|
; GAS relies on the order and position of instructions output below in order
|
|
|
|
|
; to generate relocs for VMS link to potentially optimize the call.
|
|
|
|
|
; Please do not molest.
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*call_vms_1"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1))
|
2002-08-15 07:04:27 +02:00
|
|
|
|
(use (match_operand:DI 2 "nonmemory_operand" "r,n"))
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(use (reg:DI 25))
|
|
|
|
|
(use (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
2002-08-15 07:04:27 +02:00
|
|
|
|
{
|
|
|
|
|
switch (which_alternative)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
2002-12-16 19:23:00 +01:00
|
|
|
|
return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
|
2002-08-15 07:04:27 +02:00
|
|
|
|
case 1:
|
2011-11-04 10:11:27 +01:00
|
|
|
|
operands [2] = alpha_use_linkage (operands [0], true, false);
|
|
|
|
|
operands [3] = alpha_use_linkage (operands [0], false, false);
|
2002-12-16 19:23:00 +01:00
|
|
|
|
return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
|
2002-08-15 07:04:27 +02:00
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2002-08-15 07:04:27 +02:00
|
|
|
|
}
|
2002-12-16 19:23:00 +01:00
|
|
|
|
}
|
1998-06-16 19:08:48 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "12,16")])
|
1996-11-16 12:07:51 +01:00
|
|
|
|
|
1993-04-17 02:26:58 +02:00
|
|
|
|
;; Call subroutine returning any type.
|
|
|
|
|
|
|
|
|
|
(define_expand "untyped_call"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(call (match_operand 0)
|
1993-04-17 02:26:58 +02:00
|
|
|
|
(const_int 0))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 1)
|
|
|
|
|
(match_operand 2)])]
|
1993-04-17 02:26:58 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
2015-08-24 19:59:51 +02:00
|
|
|
|
emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
|
1993-04-17 02:26:58 +02:00
|
|
|
|
|
|
|
|
|
for (i = 0; i < XVECLEN (operands[2], 0); i++)
|
|
|
|
|
{
|
|
|
|
|
rtx set = XVECEXP (operands[2], 0, i);
|
|
|
|
|
emit_move_insn (SET_DEST (set), SET_SRC (set));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The optimizer does not know that the call sets the function value
|
|
|
|
|
registers we stored in the result block. We avoid problems by
|
|
|
|
|
claiming that all hard registers are used and clobbered at this
|
|
|
|
|
point. */
|
|
|
|
|
emit_insn (gen_blockage ());
|
|
|
|
|
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1993-04-17 02:26:58 +02:00
|
|
|
|
|
|
|
|
|
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
|
|
|
|
|
;; all of memory. This blocks insns from being moved across this point.
|
|
|
|
|
|
|
|
|
|
(define_insn "blockage"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
|
1993-04-17 02:26:58 +02:00
|
|
|
|
""
|
1998-06-16 19:08:48 +02:00
|
|
|
|
""
|
2002-05-05 23:54:39 +02:00
|
|
|
|
[(set_attr "length" "0")
|
|
|
|
|
(set_attr "type" "none")])
|
1993-04-17 02:26:58 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "jump"
|
|
|
|
|
[(set (pc)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(label_ref (match_operand 0)))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
"br $31,%l0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
2000-01-30 21:27:57 +01:00
|
|
|
|
(define_expand "return"
|
1992-10-24 15:33:28 +01:00
|
|
|
|
[(return)]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"direct_return ()")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2000-01-30 21:27:57 +01:00
|
|
|
|
(define_insn "*return_internal"
|
|
|
|
|
[(return)]
|
2000-01-31 02:16:21 +01:00
|
|
|
|
"reload_completed"
|
1998-06-16 19:08:48 +02:00
|
|
|
|
"ret $31,($26),1"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_insn "indirect_jump"
|
|
|
|
|
[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
|
|
|
|
|
""
|
|
|
|
|
"jmp $31,(%0),0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
|
|
|
|
(define_expand "tablejump"
|
2001-09-11 10:52:39 +02:00
|
|
|
|
[(parallel [(set (pc)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 0 "register_operand"))
|
|
|
|
|
(use (label_ref:DI (match_operand 1)))])]
|
1995-04-13 14:46:37 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-22 23:28:18 +01:00
|
|
|
|
if (TARGET_ABI_OSF)
|
2001-09-11 10:52:39 +02:00
|
|
|
|
{
|
|
|
|
|
rtx dest = gen_reg_rtx (DImode);
|
|
|
|
|
emit_insn (gen_extendsidi2 (dest, operands[0]));
|
2001-11-29 06:26:31 +01:00
|
|
|
|
emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
|
2001-09-11 10:52:39 +02:00
|
|
|
|
operands[0] = dest;
|
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1995-04-13 14:46:37 +02:00
|
|
|
|
|
2001-09-11 10:52:39 +02:00
|
|
|
|
(define_insn "*tablejump_internal"
|
1996-11-16 12:07:51 +01:00
|
|
|
|
[(set (pc)
|
2001-09-11 10:52:39 +02:00
|
|
|
|
(match_operand:DI 0 "register_operand" "r"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (label_ref (match_operand 1)))]
|
2001-09-11 10:52:39 +02:00
|
|
|
|
""
|
1996-11-16 12:07:51 +01:00
|
|
|
|
"jmp $31,(%0),0"
|
|
|
|
|
[(set_attr "type" "ibr")])
|
|
|
|
|
|
2009-09-22 17:11:45 +02:00
|
|
|
|
;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't
|
1992-12-15 23:41:56 +01:00
|
|
|
|
;; want to have to include pal.h in our .s file.
|
1998-07-01 05:56:35 +02:00
|
|
|
|
(define_insn "imb"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
|
1992-12-15 23:41:56 +01:00
|
|
|
|
""
|
1996-06-13 03:47:01 +02:00
|
|
|
|
"call_pal 0x86"
|
2002-09-13 20:01:09 +02:00
|
|
|
|
[(set_attr "type" "callpal")])
|
2002-03-31 13:09:48 +02:00
|
|
|
|
|
2012-05-07 17:55:11 +02:00
|
|
|
|
(define_expand "clear_cache"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0) ; region start
|
|
|
|
|
(match_operand:DI 1)] ; region end
|
2012-05-07 17:55:11 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_imb ());
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2002-03-31 13:09:48 +02:00
|
|
|
|
;; BUGCHK is documented common to OSF/1 and VMS PALcode.
|
|
|
|
|
(define_insn "trap"
|
2016-05-18 21:15:22 +02:00
|
|
|
|
[(trap_if (const_int 1) (const_int 0))
|
|
|
|
|
(use (reg:DI 29))]
|
2011-03-22 23:28:18 +01:00
|
|
|
|
""
|
2002-03-31 13:09:48 +02:00
|
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"call_pal 0x81"
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2002-09-13 20:01:09 +02:00
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[(set_attr "type" "callpal")])
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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;; For userland, we load the thread pointer from the TCB.
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;; For the kernel, we load the per-cpu private value.
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|
builtins.c (expand_builtin_thread_pointer): New.
2012-10-11 Chung-Lin Tang <cltang@codesourcery.com>
* builtins.c (expand_builtin_thread_pointer): New.
(expand_builtin_set_thread_pointer): New.
(expand_builtin): Add BUILT_IN_THREAD_POINTER,
BUILT_IN_SET_THREAD_POINTER expand cases.
* builtins.def (BUILT_IN_THREAD_POINTER):
New __builtin_thread_pointer builtin.
(BUILT_IN_SET_THREAD_POINTER):
New __builtin_set_thread_pointer builtin.
* optabs.def (get_thread_pointer,set_thread_pointer):
New standard names.
* doc/md.texi (Standard Names): Document get_thread_pointer and
set_thread_pointer patterns.
* config/alpha/alpha.md (get_thread_pointerdi): Rename from load_tp.
(set_thread_pointerdi): Rename from set_tp.
* config/alpha/alpha.c (alpha_legitimize_address_1): Change
gen_load_tp calls to gen_get_thread_pointerdi.
(alpha_builtin): Remove ALPHA_BUILTIN_THREAD_POINTER,
ALPHA_BUILTIN_SET_THREAD_POINTER.
(code_for_builtin): Remove CODE_FOR_load_tp, CODE_FOR_set_tp.
(alpha_init_builtins): Remove __builtin_thread_pointer,
__builtin_set_thread_pointer machine-specific builtins.
(alpha_expand_builtin_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_THREAD_POINTER.
(alpha_expand_builtin_set_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_SET_THREAD_POINTER.
(alpha_fold_builtin): Remove ALPHA_BUILTIN_THREAD_POINTER,
ALPHA_BUILTIN_SET_THREAD_POINTER cases.
* config/arm/arm.md (get_thread_pointersi): New pattern.
* config/arm/arm-protos.h (arm_load_tp): Add extern declaration.
* config/arm/arm.c (arm_load_tp): Remove static.
(arm_builtins): Remove ARM_BUILTIN_THREAD_POINTER.
(arm_init_tls_builtins): Remove function.
(arm_init_builtins): Remove call to arm_init_tls_builtins().
(arm_expand_builtin): Remove ARM_BUILTIN_THREAD_POINTER case.
* config/mips/mips.md (get_thread_pointer<mode>): New pattern.
* config/mips/mips-protos.h (mips_expand_thread_pointer):
Add extern declaration.
* config/mips/mips.c (mips_expand_thread_pointer):
Renamed from mips_get_tp.
(mips_get_tp): New stub calling mips_expand_thread_pointer.
* config/s390/s390.c (s390_builtin,code_for_builtin_64,
code_for_builtin_31,s390_init_builtins,s390_expand_builtin): Remove.
* config/s390/s390.md (get_tp_64,get_tp_31,set_tp_64,set_tp_31):
Remove.
(get_thread_pointer<mode>,set_thread_pointer<mode>):
New, adapted from removed patterns.
* config/xtensa/xtensa.md (get_thread_pointersi):
Renamed from load_tp.
(set_thread_pointersi): Renamed from set_tp.
* config/xtensa/xtensa.c (xtensa_legitimize_tls_address):
Change gen_load_tp calls to gen_get_thread_pointersi.
(xtensa_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER and
XTENSA_BUILTIN_SET_THREAD_POINTER.
(xtensa_init_builtins): Remove __builtin_thread_pointer,
__builtin_set_thread_pointer machine-specific builtins.
(xtensa_fold_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER,
XTENSA_BUILTIN_SET_THREAD_POINTER cases.
(xtensa_expand_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER,
XTENSA_BUILTIN_SET_THREAD_POINTER cases.
From-SVN: r192364
2012-10-11 17:05:44 +02:00
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(define_insn "get_thread_pointerdi"
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configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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[(set (match_operand:DI 0 "register_operand" "=v")
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(unspec:DI [(const_int 0)] UNSPEC_TP))]
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"TARGET_ABI_OSF"
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{
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if (TARGET_TLS_KERNEL)
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return "call_pal 0x32";
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else
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return "call_pal 0x9e";
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}
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2002-09-13 20:01:09 +02:00
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[(set_attr "type" "callpal")])
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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;; For completeness, and possibly a __builtin function, here's how to
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;; set the thread pointer. Since we don't describe enough of this
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;; quantity for CSE, we have to use a volatile unspec, and then there's
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;; not much point in creating an R16_REG register class.
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builtins.c (expand_builtin_thread_pointer): New.
2012-10-11 Chung-Lin Tang <cltang@codesourcery.com>
* builtins.c (expand_builtin_thread_pointer): New.
(expand_builtin_set_thread_pointer): New.
(expand_builtin): Add BUILT_IN_THREAD_POINTER,
BUILT_IN_SET_THREAD_POINTER expand cases.
* builtins.def (BUILT_IN_THREAD_POINTER):
New __builtin_thread_pointer builtin.
(BUILT_IN_SET_THREAD_POINTER):
New __builtin_set_thread_pointer builtin.
* optabs.def (get_thread_pointer,set_thread_pointer):
New standard names.
* doc/md.texi (Standard Names): Document get_thread_pointer and
set_thread_pointer patterns.
* config/alpha/alpha.md (get_thread_pointerdi): Rename from load_tp.
(set_thread_pointerdi): Rename from set_tp.
* config/alpha/alpha.c (alpha_legitimize_address_1): Change
gen_load_tp calls to gen_get_thread_pointerdi.
(alpha_builtin): Remove ALPHA_BUILTIN_THREAD_POINTER,
ALPHA_BUILTIN_SET_THREAD_POINTER.
(code_for_builtin): Remove CODE_FOR_load_tp, CODE_FOR_set_tp.
(alpha_init_builtins): Remove __builtin_thread_pointer,
__builtin_set_thread_pointer machine-specific builtins.
(alpha_expand_builtin_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_THREAD_POINTER.
(alpha_expand_builtin_set_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_SET_THREAD_POINTER.
(alpha_fold_builtin): Remove ALPHA_BUILTIN_THREAD_POINTER,
ALPHA_BUILTIN_SET_THREAD_POINTER cases.
* config/arm/arm.md (get_thread_pointersi): New pattern.
* config/arm/arm-protos.h (arm_load_tp): Add extern declaration.
* config/arm/arm.c (arm_load_tp): Remove static.
(arm_builtins): Remove ARM_BUILTIN_THREAD_POINTER.
(arm_init_tls_builtins): Remove function.
(arm_init_builtins): Remove call to arm_init_tls_builtins().
(arm_expand_builtin): Remove ARM_BUILTIN_THREAD_POINTER case.
* config/mips/mips.md (get_thread_pointer<mode>): New pattern.
* config/mips/mips-protos.h (mips_expand_thread_pointer):
Add extern declaration.
* config/mips/mips.c (mips_expand_thread_pointer):
Renamed from mips_get_tp.
(mips_get_tp): New stub calling mips_expand_thread_pointer.
* config/s390/s390.c (s390_builtin,code_for_builtin_64,
code_for_builtin_31,s390_init_builtins,s390_expand_builtin): Remove.
* config/s390/s390.md (get_tp_64,get_tp_31,set_tp_64,set_tp_31):
Remove.
(get_thread_pointer<mode>,set_thread_pointer<mode>):
New, adapted from removed patterns.
* config/xtensa/xtensa.md (get_thread_pointersi):
Renamed from load_tp.
(set_thread_pointersi): Renamed from set_tp.
* config/xtensa/xtensa.c (xtensa_legitimize_tls_address):
Change gen_load_tp calls to gen_get_thread_pointersi.
(xtensa_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER and
XTENSA_BUILTIN_SET_THREAD_POINTER.
(xtensa_init_builtins): Remove __builtin_thread_pointer,
__builtin_set_thread_pointer machine-specific builtins.
(xtensa_fold_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER,
XTENSA_BUILTIN_SET_THREAD_POINTER cases.
(xtensa_expand_builtin): Remove XTENSA_BUILTIN_THREAD_POINTER,
XTENSA_BUILTIN_SET_THREAD_POINTER cases.
From-SVN: r192364
2012-10-11 17:05:44 +02:00
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(define_expand "set_thread_pointerdi"
|
2012-10-14 14:50:45 +02:00
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[(set (reg:DI 16) (match_operand:DI 0 "input_operand"))
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
|
2012-10-14 14:50:45 +02:00
|
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"TARGET_ABI_OSF")
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
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(define_insn "*set_tp"
|
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[(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
|
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"TARGET_ABI_OSF"
|
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{
|
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|
|
if (TARGET_TLS_KERNEL)
|
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|
return "call_pal 0x31";
|
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|
else
|
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|
return "call_pal 0x9f";
|
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}
|
2002-09-13 20:01:09 +02:00
|
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|
[(set_attr "type" "callpal")])
|
2009-08-10 06:38:02 +02:00
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|
|
;; Special builtins for establishing and reverting VMS condition handlers.
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_establish_vms_condition_handler"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (reg:DI 0) (match_operand:DI 0 "register_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "address_operand"))]
|
2009-08-10 06:38:02 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_establish_vms_condition_handler (operands[0],
|
|
|
|
|
operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_revert_vms_condition_handler"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (reg:DI 0) (match_operand:DI 0 "register_operand"))]
|
2009-08-10 06:38:02 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_expand_builtin_revert_vms_condition_handler (operands[0]);")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; Finally, we have the basic data motion insns. The byte and word insns
|
|
|
|
|
;; are done via define_expand. Start with the floating-point insns, since
|
|
|
|
|
;; they are simpler.
|
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_expand "movsf"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SF 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:SF 1 "general_operand"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (MEM_P (operands[0])
|
|
|
|
|
&& ! reg_or_0_operand (operands[1], SFmode))
|
|
|
|
|
operands[1] = force_reg (SFmode, operands[1]);
|
|
|
|
|
})
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_insn "*movsf"
|
1999-10-30 23:46:57 +02:00
|
|
|
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
|
|
|
|
|
(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
"register_operand (operands[0], SFmode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], SFmode)"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
"@
|
2001-09-11 10:52:39 +02:00
|
|
|
|
cpys %R1,%R1,%0
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
ld%, %0,%1
|
2001-09-11 10:52:39 +02:00
|
|
|
|
bis $31,%r1,%0
|
1999-04-26 03:05:13 +02:00
|
|
|
|
ldl %0,%1
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
st%, %R1,%0
|
1999-04-26 03:05:13 +02:00
|
|
|
|
stl %r1,%0
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
itofs %1,%0
|
|
|
|
|
ftois %1,%0"
|
2011-03-25 01:34:56 +01:00
|
|
|
|
[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
|
|
|
|
|
(set_attr "isa" "*,*,*,*,*,*,fix,fix")])
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_expand "movdf"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:DF 1 "general_operand"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (MEM_P (operands[0])
|
|
|
|
|
&& ! reg_or_0_operand (operands[1], DFmode))
|
|
|
|
|
operands[1] = force_reg (DFmode, operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*movdf"
|
1999-10-30 23:46:57 +02:00
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
|
|
|
|
|
(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
"register_operand (operands[0], DFmode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], DFmode)"
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
"@
|
2001-09-11 10:52:39 +02:00
|
|
|
|
cpys %R1,%R1,%0
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
ld%- %0,%1
|
2001-09-11 10:52:39 +02:00
|
|
|
|
bis $31,%r1,%0
|
1999-04-26 03:05:13 +02:00
|
|
|
|
ldq %0,%1
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
st%- %R1,%0
|
1999-04-26 03:05:13 +02:00
|
|
|
|
stq %r1,%0
|
genattrtab.c (expand_units): For large nr opclasses, expand function_units_used with ORX to prevent blowups.
* genattrtab.c (expand_units): For large nr opclasses, expand
function_units_used with ORX to prevent blowups. Tag with FFS.
(num_unit_opclasses): New variable.
(gen_unit): Update it.
(enum operator): Add ORX_OP.
(operate_exp): Treat ORX as or, except don't expand across an if.
Reuse number rtx's after operating on them.
(check_attr_value): Accept IOR, AND, & FFS.
(write_test_expr): Transmute `in_comparison' to `flags'. Allow
for attribute value caching. Handle CONST_STRING, IF_THEN_ELSE.
(write_expr_attr_cache, write_toplevel_expr): New functions.
(write_attr_get): Handle FFS-tagged expressions.
(make_canonical): Don't expand const attributes.
(convert_const_symbol_ref): Dike out.
(evaluate_eq_attr): Handle SYMBOL_REF.
(main): Don't emit get_attr_foo for const attributes.
* alpha.c (override_options): Reinstate PROCESSOR_EV6.
(alpha_adjust_cost): Add EV6 tuning; streamline EV5 tests.
* alpha.h (REGISTER_MOVE_COST): Increase ftoi/itof cost slightly.
* alpha.md: Redo all of the scheduling, adding EV6 support, and
combining function units where possible.
(attr "type"): Split loads, stores, cmov into int/fp. Combine
multiplies and divides. Add EV6 sqrt, ftoi, itof.
(attr "opsize"): New attribute.
(sqrtsf2-1, sqrtdf2-1): Provide proper TP_INSN patterns.
(movsf2-[12], movdf2-[12]): Provide CIX varients; don't allow CIX
to control register allocation.
(movsi2-1, movdi2-1): Likewise.
From-SVN: r17212
1997-12-23 06:34:27 +01:00
|
|
|
|
itoft %1,%0
|
|
|
|
|
ftoit %1,%0"
|
2011-03-25 01:34:56 +01:00
|
|
|
|
[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
|
|
|
|
|
(set_attr "isa" "*,*,*,*,*,*,fix,fix")])
|
2000-03-21 19:54:16 +01:00
|
|
|
|
|
2000-01-24 20:51:09 +01:00
|
|
|
|
;; Subregs suck for register allocation. Pretend we can move TFmode
|
|
|
|
|
;; data between general registers until after reload.
|
2011-03-25 01:34:56 +01:00
|
|
|
|
;; ??? Is this still true now that we have the lower-subreg pass?
|
2000-10-24 02:06:18 +02:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_expand "movtf"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:TF 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:TF 1 "general_operand"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (MEM_P (operands[0])
|
|
|
|
|
&& ! reg_or_0_operand (operands[1], TFmode))
|
|
|
|
|
operands[1] = force_reg (TFmode, operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
2015-05-13 17:02:26 +02:00
|
|
|
|
(define_insn_and_split "*movtf_internal"
|
2000-01-24 20:51:09 +01:00
|
|
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
|
2000-11-22 01:59:12 +01:00
|
|
|
|
(match_operand:TF 1 "input_operand" "roG,rG"))]
|
2000-01-24 20:51:09 +01:00
|
|
|
|
"register_operand (operands[0], TFmode)
|
2002-06-04 04:28:40 +02:00
|
|
|
|
|| reg_or_0_operand (operands[1], TFmode)"
|
2000-10-24 02:06:18 +02:00
|
|
|
|
"#"
|
2000-01-24 20:51:09 +01:00
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 0) (match_dup 2))
|
|
|
|
|
(set (match_dup 1) (match_dup 3))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_split_tmode_pair (operands, TFmode, true);")
|
2000-01-24 20:51:09 +01:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
;; We do two major things here: handle mem->mem and construct long
|
|
|
|
|
;; constants.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_expand "movsi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:SI 1 "general_operand"))]
|
2000-01-24 20:51:09 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:34:56 +01:00
|
|
|
|
if (alpha_expand_mov (SImode, operands))
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-01-24 20:51:09 +01:00
|
|
|
|
|
2004-01-19 10:55:42 +01:00
|
|
|
|
(define_insn "*movsi"
|
2011-03-25 01:34:56 +01:00
|
|
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r")
|
|
|
|
|
(match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))]
|
|
|
|
|
"register_operand (operands[0], SImode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], SImode)"
|
1997-11-02 22:19:36 +01:00
|
|
|
|
"@
|
2001-09-11 10:52:39 +02:00
|
|
|
|
bis $31,%r1,%0
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
lda %0,%1($31)
|
|
|
|
|
ldah %0,%h1($31)
|
2005-01-20 04:59:00 +01:00
|
|
|
|
#
|
1997-11-02 22:19:36 +01:00
|
|
|
|
ldl %0,%1
|
2011-03-25 01:34:56 +01:00
|
|
|
|
stl %r1,%0
|
|
|
|
|
lda %0,%1"
|
|
|
|
|
[(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym")
|
|
|
|
|
(set_attr "isa" "*,*,*,*,*,*,vms")])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; Split a load of a large constant into the appropriate two-insn
|
|
|
|
|
;; sequence.
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(match_operand:SI 1 "non_add_const_operand"))]
|
2005-01-20 04:59:00 +01:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2005-01-20 04:59:00 +01:00
|
|
|
|
if (alpha_split_const_mov (SImode, operands))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(define_insn "*movdi_er_low_l"
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "local_symbolic_operand")))]
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS"
|
2001-09-13 10:42:20 +02:00
|
|
|
|
{
|
|
|
|
|
if (true_regnum (operands[1]) == 29)
|
|
|
|
|
return "lda %0,%2(%1)\t\t!gprel";
|
|
|
|
|
else
|
|
|
|
|
return "lda %0,%2(%1)\t\t!gprellow";
|
2003-01-16 02:50:54 +01:00
|
|
|
|
}
|
|
|
|
|
[(set_attr "usegp" "yes")])
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
|
2002-01-04 09:15:22 +01:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "small_symbolic_operand"))]
|
2002-01-04 09:15:22 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(lo_sum:DI (match_dup 2) (match_dup 1)))]
|
|
|
|
|
"operands[2] = pic_offset_table_rtx;")
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "local_symbolic_operand"))]
|
2002-01-04 09:15:22 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(plus:DI (match_dup 2) (high:DI (match_dup 1))))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(lo_sum:DI (match_dup 0) (match_dup 1)))]
|
|
|
|
|
"operands[2] = pic_offset_table_rtx;")
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand 0 "some_small_symbolic_operand")]
|
2004-09-20 22:13:39 +02:00
|
|
|
|
""
|
2002-01-23 00:23:46 +01:00
|
|
|
|
[(match_dup 0)]
|
2002-02-18 02:07:52 +01:00
|
|
|
|
"operands[0] = split_small_symbolic_operand (operands[0]);")
|
2002-01-04 09:15:22 +01:00
|
|
|
|
|
2003-01-06 23:59:25 +01:00
|
|
|
|
;; Accepts any symbolic, not just global, since function calls that
|
|
|
|
|
;; don't go via bsr still use !literal in hopes of linker relaxation.
|
2002-01-11 04:47:24 +01:00
|
|
|
|
(define_insn "movdi_er_high_g"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "symbolic_operand")
|
|
|
|
|
(match_operand 3 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPEC_LITERAL))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS"
|
2002-01-11 04:47:24 +01:00
|
|
|
|
{
|
|
|
|
|
if (INTVAL (operands[3]) == 0)
|
|
|
|
|
return "ldq %0,%2(%1)\t\t!literal";
|
|
|
|
|
else
|
|
|
|
|
return "ldq %0,%2(%1)\t\t!literal!%3";
|
|
|
|
|
}
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(set_attr "type" "ldsym")])
|
|
|
|
|
|
2002-01-04 09:15:22 +01:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "global_symbolic_operand"))]
|
2002-01-04 09:15:22 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(unspec:DI [(match_dup 2)
|
|
|
|
|
(match_dup 1)
|
|
|
|
|
(const_int 0)] UNSPEC_LITERAL))]
|
|
|
|
|
"operands[2] = pic_offset_table_rtx;")
|
|
|
|
|
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(define_insn "movdi_er_tlsgd"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "symbolic_operand")
|
|
|
|
|
(match_operand 3 "const_int_operand")]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
UNSPEC_TLSGD))]
|
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
{
|
|
|
|
|
if (INTVAL (operands[3]) == 0)
|
|
|
|
|
return "lda %0,%2(%1)\t\t!tlsgd";
|
|
|
|
|
else
|
|
|
|
|
return "lda %0,%2(%1)\t\t!tlsgd!%3";
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "movdi_er_tlsldm"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
UNSPEC_TLSLDM))]
|
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
{
|
|
|
|
|
if (INTVAL (operands[2]) == 0)
|
|
|
|
|
return "lda %0,%&(%1)\t\t!tlsldm";
|
|
|
|
|
else
|
|
|
|
|
return "lda %0,%&(%1)\t\t!tlsldm!%2";
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*movdi_er_gotdtp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "symbolic_operand")]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
UNSPEC_DTPREL))]
|
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"ldq %0,%2(%1)\t\t!gotdtprel"
|
2003-01-16 02:50:54 +01:00
|
|
|
|
[(set_attr "type" "ild")
|
|
|
|
|
(set_attr "usegp" "yes")])
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "gotdtp_symbolic_operand"))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(unspec:DI [(match_dup 2)
|
|
|
|
|
(match_dup 1)] UNSPEC_DTPREL))]
|
|
|
|
|
{
|
|
|
|
|
operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
|
|
|
|
|
operands[2] = pic_offset_table_rtx;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*movdi_er_gottp"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "symbolic_operand")]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
UNSPEC_TPREL))]
|
|
|
|
|
"HAVE_AS_TLS"
|
|
|
|
|
"ldq %0,%2(%1)\t\t!gottprel"
|
2003-01-16 02:50:54 +01:00
|
|
|
|
[(set_attr "type" "ild")
|
|
|
|
|
(set_attr "usegp" "yes")])
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "gottp_symbolic_operand"))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
"HAVE_AS_TLS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(unspec:DI [(match_dup 2)
|
|
|
|
|
(match_dup 1)] UNSPEC_TPREL))]
|
|
|
|
|
{
|
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|
|
operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
|
|
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|
|
operands[2] = pic_offset_table_rtx;
|
|
|
|
|
})
|
|
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|
2011-03-25 01:35:01 +01:00
|
|
|
|
(define_insn "*movdi"
|
2002-01-04 09:15:22 +01:00
|
|
|
|
[(set (match_operand:DI 0 "nonimmediate_operand"
|
2011-03-25 01:35:01 +01:00
|
|
|
|
"=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
|
2002-01-04 09:15:22 +01:00
|
|
|
|
(match_operand:DI 1 "input_operand"
|
2011-03-25 01:35:01 +01:00
|
|
|
|
"rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))]
|
|
|
|
|
"register_operand (operands[0], DImode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], DImode)"
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
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|
"@
|
|
|
|
|
mov %r1,%0
|
|
|
|
|
lda %0,%1($31)
|
|
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|
ldah %0,%h1($31)
|
2002-01-04 09:15:22 +01:00
|
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|
|
#
|
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|
|
|
#
|
2005-01-20 04:59:00 +01:00
|
|
|
|
#
|
1997-11-02 22:19:36 +01:00
|
|
|
|
lda %0,%1
|
|
|
|
|
ldq%A1 %0,%1
|
|
|
|
|
stq%A0 %r1,%0
|
2011-03-25 01:35:01 +01:00
|
|
|
|
fmov %R1,%0
|
1997-11-02 22:19:36 +01:00
|
|
|
|
ldt %0,%1
|
|
|
|
|
stt %R1,%0
|
|
|
|
|
ftoit %1,%0
|
|
|
|
|
itoft %1,%0"
|
2011-03-25 01:35:01 +01:00
|
|
|
|
[(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
|
|
|
|
|
(set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix")
|
|
|
|
|
(set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")])
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
2001-08-03 10:23:54 +02:00
|
|
|
|
;; VMS needs to set up "vms_base_regno" for unwinding. This move
|
|
|
|
|
;; often appears dead to the life analysis code, at which point we
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
;; die for emitting dead prologue instructions. Force this live.
|
2001-08-03 10:23:54 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "force_movdi"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
|
|
|
|
|
UNSPECV_FORCE_MOV))]
|
|
|
|
|
""
|
|
|
|
|
"mov %1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; We do three major things here: handle mem->mem, put 64-bit constants in
|
|
|
|
|
;; memory, and construct long 32-bit constants.
|
|
|
|
|
|
|
|
|
|
(define_expand "movdi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:DI 1 "general_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2001-09-05 09:46:54 +02:00
|
|
|
|
if (alpha_expand_mov (DImode, operands))
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
;; Split a load of a large constant into the appropriate two-insn
|
|
|
|
|
;; sequence.
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "non_add_const_operand"))]
|
2005-01-20 04:59:00 +01:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
2005-01-20 04:59:00 +01:00
|
|
|
|
if (alpha_split_const_mov (DImode, operands))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2006-01-18 12:20:51 +01:00
|
|
|
|
;; We need to prevent reload from splitting TImode moves, because it
|
|
|
|
|
;; might decide to overwrite a pointer with the value it points to.
|
|
|
|
|
;; In that case we have to do the loads in the appropriate order so
|
|
|
|
|
;; that the pointer is not destroyed too early.
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*movti_internal"
|
|
|
|
|
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
|
|
|
|
|
(match_operand:TI 1 "input_operand" "roJ,rJ"))]
|
|
|
|
|
"(register_operand (operands[0], TImode)
|
|
|
|
|
/* Prevent rematerialization of constants. */
|
|
|
|
|
&& ! CONSTANT_P (operands[1]))
|
|
|
|
|
|| reg_or_0_operand (operands[1], TImode)"
|
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 0) (match_dup 2))
|
|
|
|
|
(set (match_dup 1) (match_dup 3))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_split_tmode_pair (operands, TImode, true);")
|
2006-01-18 12:20:51 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "movti"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:TI 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:TI 1 "general_operand"))]
|
2006-01-18 12:20:51 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (MEM_P (operands[0])
|
2006-01-18 12:20:51 +01:00
|
|
|
|
&& ! reg_or_0_operand (operands[1], TImode))
|
|
|
|
|
operands[1] = force_reg (TImode, operands[1]);
|
|
|
|
|
|
|
|
|
|
if (operands[1] == const0_rtx)
|
|
|
|
|
;
|
|
|
|
|
/* We must put 64-bit constants in memory. We could keep the
|
|
|
|
|
32-bit constants in TImode and rely on the splitter, but
|
|
|
|
|
this doesn't seem to be worth the pain. */
|
2015-05-19 17:09:09 +02:00
|
|
|
|
else if (CONST_SCALAR_INT_P (operands[1]))
|
2006-01-18 12:20:51 +01:00
|
|
|
|
{
|
|
|
|
|
rtx in[2], out[2], target;
|
|
|
|
|
|
Replace no_new_pseudos in backends.
* rtl.h (can_create_pseudo_p): Define.
* config/darwin.c (machopic_indirect_data_reference): Use
can_create_pseudo_p () instead of no_new_pseudos.
(machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address): Likewise.
(alpha_emit_set_const_1): Likewise.
(alpha_emit_set_const): Likewise.
(alpha_emit_conditional_move): Likewise.
(alpha_split_conditional_move): Likewise.
* config/alpha/alpha.md (various splitters): Likewise.
(movti): Likewise.
* config/arm/arm.c (legitimize_pic_address): Likewise.
(arm_load_pic_register): Likewise.
* config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise.
(movdi, movsi, movhi, movqi, movsf, movdf): Likewise.
* config/bfin/bfin.c (legitimize_pic_address): Likewise.
* config/cris/cris.c (cris_expand_pic_call_address): Likewise.
* config/cris/cris.md (movsi): Likewise.
* config/frv/frv.md (symGOT2reg_hilo): Likewise.
(symGOTOFF2reg_hilo): Likewise.
(symGPREL2reg, symGPREL2reg_hilo): Likewise.
* config/h8300/h8300.md (insv, extzv): Likewise.
* config/i386/i386.c (ix86_expand_move): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_prepare_fp_compare_args): Likewise.
(ix86_expand_carry_flag_compare): Likewise.
* config/i386/i386.md (tls_dynamic_gnu2_32): Likewise.
(tls_dynamic_gnu2_combine_32): Likewise.
(tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise.
* config/ia64/ia64.c (ia64_expand_move): Likewise.
(ia64_expand_movxf_movrf): Likewise.
* config/m32c/m32c.c (m32c_prepare_move): Likewise.
(m32c_split_move): Likewise.
(m32c_expand_insv): Likewise.
* config/m68k/m68k.md (movsi): Likewise.
* config/mips/mips.c (mips_force_temporary): Likewise.
(mips_split_symbol): Likewise.
(mips_move_integer): Likewise.
(mips_legitimize_const_move): Likewise.
* config/mn10300/mn10300.md (movsi): Likewise.
* config/pa/pa.c (emit_move_sequence): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
(rs6000_got_register): Likewise.
(create_TOC_reference): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rs6000/rs6000.md (add<mode>3): Likewise.
(various splitters): Likewise.
(iorsi3, xorsi3, iordi3, xordi3): Likewise.
(movsi_got): Likewise.
* config/s390/s390.c (emit_symbolic_move): Likewise.
* config/s390/s390.md (movhi, movqi): Likewise.
(load_multiple, store_multiple): Likewise.
* config/score/score.c (score_force_temporary): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(prepare_cbranch_operands): Likewise.
(emit_fpu_switch): Likewise.
(fpscr_set_from_mem): Likewise.
* config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise.
(adddi3, subsi3): Likewise.
(various splitters): Likewise.
(divsi_inv_fp_combine): Likewise.
(symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise.
(seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise.
(sne): Likewise.
* config/sh/predicates.md (xor_operand): Likewise.
* config/sparc/sparc.c (legitimize_tls_address): Likewise.
* config/sparc/sparc.md (movsi_pic_label_ref): Likewise.
(movdi_pic_label_ref): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
* config/alpha/alpha.md (various splitters): Remove test
!no_new_pseudos || reload_completed.
* config/ia64/ia64.c (ia64_output_mi_thunk): Don't set
no_new_pseudos.
* config/m68k/m68k.c (m68k_output_mi_thunk): Likewise.
* config/mips/mips.c (mips_output_mi_thunk): Likewise.
* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
* config/score/score.c (th_output_mi_thunk): Likewise.
* config/sh/sh.c (sh_output_mi_thunk): Likewise.
* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
From-SVN: r126517
2007-07-10 19:23:11 +02:00
|
|
|
|
gcc_assert (can_create_pseudo_p ());
|
2006-01-18 12:20:51 +01:00
|
|
|
|
|
|
|
|
|
split_double (operands[1], &in[0], &in[1]);
|
|
|
|
|
|
|
|
|
|
if (in[0] == const0_rtx)
|
|
|
|
|
out[0] = const0_rtx;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
out[0] = gen_reg_rtx (DImode);
|
|
|
|
|
emit_insn (gen_movdi (out[0], in[0]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (in[1] == const0_rtx)
|
|
|
|
|
out[1] = const0_rtx;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
out[1] = gen_reg_rtx (DImode);
|
|
|
|
|
emit_insn (gen_movdi (out[1], in[1]));
|
|
|
|
|
}
|
|
|
|
|
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (!REG_P (operands[0]))
|
2006-01-18 12:20:51 +01:00
|
|
|
|
target = gen_reg_rtx (TImode);
|
|
|
|
|
else
|
|
|
|
|
target = operands[0];
|
|
|
|
|
|
2007-09-23 16:53:06 +02:00
|
|
|
|
emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0]));
|
|
|
|
|
emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1]));
|
2006-01-18 12:20:51 +01:00
|
|
|
|
|
|
|
|
|
if (target != operands[0])
|
rtl.h (always_void_p): New function.
gcc/
* rtl.h (always_void_p): New function.
* gengenrtl.c (always_void_p): Likewise.
(genmacro): Don't add a mode parameter to gen_rtx_foo if rtxes
with code foo are always VOIDmode.
* genemit.c (gen_exp): Update gen_rtx_foo calls accordingly.
* builtins.c, caller-save.c, calls.c, cfgexpand.c, combine.c,
compare-elim.c, config/aarch64/aarch64.c,
config/aarch64/aarch64.md, config/alpha/alpha.c,
config/alpha/alpha.md, config/arc/arc.c, config/arc/arc.md,
config/arm/arm-fixed.md, config/arm/arm.c, config/arm/arm.md,
config/arm/ldrdstrd.md, config/arm/thumb2.md, config/arm/vfp.md,
config/avr/avr.c, config/bfin/bfin.c, config/c6x/c6x.c,
config/c6x/c6x.md, config/cr16/cr16.c, config/cris/cris.c,
config/cris/cris.md, config/darwin.c, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c, config/frv/frv.c,
config/frv/frv.md, config/h8300/h8300.c, config/i386/i386.c,
config/i386/i386.md, config/i386/sse.md, config/ia64/ia64.c,
config/ia64/vect.md, config/iq2000/iq2000.c,
config/iq2000/iq2000.md, config/lm32/lm32.c, config/lm32/lm32.md,
config/m32c/m32c.c, config/m32r/m32r.c, config/m68k/m68k.c,
config/m68k/m68k.md, config/mcore/mcore.c, config/mcore/mcore.md,
config/mep/mep.c, config/microblaze/microblaze.c,
config/mips/mips.c, config/mips/mips.md, config/mmix/mmix.c,
config/mn10300/mn10300.c, config/msp430/msp430.c,
config/nds32/nds32-memory-manipulation.c, config/nds32/nds32.c,
config/nds32/nds32.md, config/nios2/nios2.c, config/nvptx/nvptx.c,
config/pa/pa.c, config/pa/pa.md, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000.c,
config/rs6000/rs6000.md, config/rs6000/vector.md,
config/rs6000/vsx.md, config/rx/rx.c, config/rx/rx.md,
config/s390/s390.c, config/s390/s390.md, config/sh/sh.c,
config/sh/sh.md, config/sh/sh_treg_combine.cc,
config/sparc/sparc.c, config/sparc/sparc.md, config/spu/spu.c,
config/spu/spu.md, config/stormy16/stormy16.c,
config/tilegx/tilegx.c, config/tilegx/tilegx.md,
config/tilepro/tilepro.c, config/tilepro/tilepro.md,
config/v850/v850.c, config/v850/v850.md, config/vax/vax.c,
config/visium/visium.c, config/xtensa/xtensa.c, cprop.c, dse.c,
expr.c, gcse.c, ifcvt.c, ira.c, jump.c, lower-subreg.c,
lra-constraints.c, lra-eliminations.c, lra.c, postreload.c, ree.c,
reg-stack.c, reload.c, reload1.c, reorg.c, sel-sched.c,
var-tracking.c: Update calls accordingly.
From-SVN: r222883
2015-05-07 18:58:46 +02:00
|
|
|
|
emit_insn (gen_rtx_SET (operands[0], target));
|
2006-01-18 12:20:51 +01:00
|
|
|
|
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; These are the partial-word cases.
|
|
|
|
|
;;
|
|
|
|
|
;; First we have the code to load an aligned word. Operand 0 is the register
|
|
|
|
|
;; in which to place the result. It's mode is QImode or HImode. Operand 1
|
|
|
|
|
;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
|
|
|
|
|
;; number of bits within the word that the value is. Operand 3 is an SImode
|
|
|
|
|
;; scratch register. If operand 0 is a hard register, operand 3 may be the
|
|
|
|
|
;; same register. It is allowed to conflict with operand 1 as well.
|
|
|
|
|
|
|
|
|
|
(define_expand "aligned_loadqi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 3 "register_operand")
|
|
|
|
|
(match_operand:SI 1 "memory_operand"))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(zero_extract:DI (subreg:DI (match_dup 3) 0)
|
|
|
|
|
(const_int 8)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "const_int_operand")))])
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(define_expand "aligned_loadhi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 3 "register_operand")
|
|
|
|
|
(match_operand:SI 1 "memory_operand"))
|
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(zero_extract:DI (subreg:DI (match_dup 3) 0)
|
|
|
|
|
(const_int 16)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 2 "const_int_operand")))])
|
2001-07-15 09:17:29 +02:00
|
|
|
|
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
;; Similar for unaligned loads, where we use the sequence from the
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; Alpha Architecture manual. We have to distinguish between little-endian
|
|
|
|
|
;; and big-endian systems as the sequences are different.
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;;
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; operand 3 can overlap the input and output registers.
|
|
|
|
|
|
|
|
|
|
(define_expand "unaligned_loadqi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 2 "register_operand")
|
|
|
|
|
(mem:DI (and:DI (match_operand:DI 1 "address_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(const_int -8))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 3 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 1))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(zero_extract:DI (match_dup 2)
|
|
|
|
|
(const_int 8)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(ashift:DI (match_dup 3) (const_int 3))))])
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
|
|
|
|
(define_expand "unaligned_loadhi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 2 "register_operand")
|
|
|
|
|
(mem:DI (and:DI (match_operand:DI 1 "address_operand")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(const_int -8))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 3 "register_operand")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(match_dup 1))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 0 "register_operand")
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(zero_extract:DI (match_dup 2)
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(const_int 16)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(ashift:DI (match_dup 3) (const_int 3))))])
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
|
2001-07-15 09:17:29 +02:00
|
|
|
|
;; aligned SImode MEM. Operand 1 is the register containing the
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; byte or word to store. Operand 2 is the number of bits within the word that
|
|
|
|
|
;; the value should be placed. Operands 3 and 4 are SImode temporaries.
|
|
|
|
|
|
|
|
|
|
(define_expand "aligned_store"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:SI 3 "register_operand")
|
|
|
|
|
(match_operand:SI 0 "memory_operand"))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(set (subreg:DI (match_dup 3) 0)
|
|
|
|
|
(and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (subreg:DI (match_operand:SI 4 "register_operand") 0)
|
|
|
|
|
(ashift:DI (zero_extend:DI (match_operand 1 "register_operand"))
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(set (subreg:DI (match_dup 4) 0)
|
|
|
|
|
(ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
|
|
|
|
|
(set (match_dup 0) (match_dup 4))]
|
|
|
|
|
""
|
2001-07-15 17:38:52 +02:00
|
|
|
|
{
|
|
|
|
|
operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
<< INTVAL (operands[2])));
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
;; For the unaligned byte and halfword cases, we use code similar to that
|
|
|
|
|
;; in the ;; Architecture book, but reordered to lower the number of registers
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; required. Operand 0 is the address. Operand 1 is the data to store.
|
1994-07-07 23:35:26 +02:00
|
|
|
|
;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; be the same temporary, if desired. If the address is in a register,
|
|
|
|
|
;; operand 2 can be that register.
|
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_expand "unaligned_store<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 3 "register_operand")
|
|
|
|
|
(mem:DI (and:DI (match_operand:DI 0 "address_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(const_int -8))))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 2 "register_operand")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 0))
|
|
|
|
|
(set (match_dup 3)
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(and:DI (not:DI (ashift:DI (match_dup 5)
|
1994-03-04 00:11:36 +01:00
|
|
|
|
(ashift:DI (match_dup 2) (const_int 3))))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_dup 3)))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(set (match_operand:DI 4 "register_operand")
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(ashift:DI (zero_extend:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:I12MODE 1 "register_operand"))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
(ashift:DI (match_dup 2) (const_int 3))))
|
|
|
|
|
(set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
|
|
|
|
|
(set (mem:DI (and:DI (match_dup 0) (const_int -8)))
|
|
|
|
|
(match_dup 4))]
|
2011-03-25 01:52:34 +01:00
|
|
|
|
""
|
2012-10-13 23:39:29 +02:00
|
|
|
|
"operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));")
|
2001-09-11 10:52:39 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
;; Here are the define_expand's for QI and HI moves that use the above
|
|
|
|
|
;; patterns. We have the normal sets, plus the ones that need scratch
|
|
|
|
|
;; registers for reload.
|
|
|
|
|
|
2012-10-13 23:39:29 +02:00
|
|
|
|
(define_expand "mov<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:I12MODE 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:I12MODE 1 "general_operand"))]
|
1992-10-24 15:33:28 +01:00
|
|
|
|
""
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
2001-09-05 09:46:54 +02:00
|
|
|
|
if (TARGET_BWX
|
2012-10-13 23:39:29 +02:00
|
|
|
|
? alpha_expand_mov (<MODE>mode, operands)
|
|
|
|
|
: alpha_expand_mov_nobwx (<MODE>mode, operands))
|
2001-09-05 09:46:54 +02:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
2011-03-25 01:34:56 +01:00
|
|
|
|
(define_insn "*movqi"
|
|
|
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
|
|
|
|
|
(match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
|
|
|
|
|
"register_operand (operands[0], QImode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], QImode)"
|
|
|
|
|
"@
|
|
|
|
|
bis $31,%r1,%0
|
|
|
|
|
lda %0,%L1($31)
|
|
|
|
|
ldbu %0,%1
|
|
|
|
|
stb %r1,%0"
|
|
|
|
|
[(set_attr "type" "ilog,iadd,ild,ist")
|
|
|
|
|
(set_attr "isa" "*,*,bwx,bwx")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*movhi"
|
|
|
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
|
|
|
|
|
(match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
|
|
|
|
|
"register_operand (operands[0], HImode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], HImode)"
|
|
|
|
|
"@
|
|
|
|
|
bis $31,%r1,%0
|
|
|
|
|
lda %0,%L1($31)
|
|
|
|
|
ldwu %0,%1
|
|
|
|
|
stw %r1,%0"
|
|
|
|
|
[(set_attr "type" "ilog,iadd,ild,ist")
|
|
|
|
|
(set_attr "isa" "*,*,bwx,bwx")])
|
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
;; We need to hook into the extra support that we have for HImode
|
|
|
|
|
;; reloads when BWX insns are not available.
|
|
|
|
|
(define_expand "movcqi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:CQI 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:CQI 1 "general_operand"))]
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
"!TARGET_BWX"
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
|
|
|
|
|
;
|
|
|
|
|
else if (!any_memory_operand (operands[0], CQImode))
|
1999-04-12 05:11:37 +02:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
if (!any_memory_operand (operands[1], CQImode))
|
|
|
|
|
{
|
|
|
|
|
emit_move_insn (gen_lowpart (HImode, operands[0]),
|
|
|
|
|
gen_lowpart (HImode, operands[1]));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
if (aligned_memory_operand (operands[1], CQImode))
|
|
|
|
|
{
|
|
|
|
|
bool done;
|
|
|
|
|
do_aligned1:
|
|
|
|
|
operands[1] = gen_lowpart (HImode, operands[1]);
|
|
|
|
|
do_aligned2:
|
|
|
|
|
operands[0] = gen_lowpart (HImode, operands[0]);
|
|
|
|
|
done = alpha_expand_mov_nobwx (HImode, operands);
|
|
|
|
|
gcc_assert (done);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
1999-04-12 05:11:37 +02:00
|
|
|
|
}
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
else if (aligned_memory_operand (operands[0], CQImode))
|
1999-04-12 05:11:37 +02:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
if (MEM_P (operands[1]))
|
|
|
|
|
{
|
|
|
|
|
rtx x = gen_reg_rtx (HImode);
|
|
|
|
|
emit_move_insn (gen_lowpart (CQImode, x), operands[1]);
|
|
|
|
|
operands[1] = x;
|
|
|
|
|
goto do_aligned2;
|
|
|
|
|
}
|
|
|
|
|
goto do_aligned1;
|
1999-04-12 05:11:37 +02:00
|
|
|
|
}
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
|
|
|
|
|
gcc_assert (!reload_in_progress);
|
|
|
|
|
emit_move_complex_parts (operands[0], operands[1]);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
;; Here are the versions for reload.
|
|
|
|
|
;;
|
|
|
|
|
;; The aligned input case is recognized early in alpha_secondary_reload
|
|
|
|
|
;; in order to avoid allocating an unnecessary scratch register.
|
|
|
|
|
;;
|
|
|
|
|
;; Note that in the unaligned cases we know that the operand must not be
|
|
|
|
|
;; a pseudo-register because stack slots are always aligned references.
|
|
|
|
|
|
|
|
|
|
(define_expand "reload_in<mode>"
|
|
|
|
|
[(parallel [(match_operand:RELOAD12 0 "register_operand" "=r")
|
|
|
|
|
(match_operand:RELOAD12 1 "any_memory_operand" "m")
|
2000-08-29 05:59:00 +02:00
|
|
|
|
(match_operand:TI 2 "register_operand" "=&r")])]
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
"!TARGET_BWX"
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
rtx scratch, seq, addr;
|
|
|
|
|
unsigned regno = REGNO (operands[2]);
|
1997-10-28 06:28:29 +01:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
/* It is possible that one of the registers we got for operands[2]
|
|
|
|
|
might coincide with that of operands[0] (which is why we made
|
|
|
|
|
it TImode). Pick the other one to use as our scratch. */
|
|
|
|
|
if (regno == REGNO (operands[0]))
|
|
|
|
|
regno++;
|
|
|
|
|
scratch = gen_rtx_REG (DImode, regno);
|
1999-04-12 05:11:37 +02:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
addr = get_unaligned_address (operands[1]);
|
|
|
|
|
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
|
|
|
|
|
seq = gen_unaligned_load<reloadmode> (operands[0], addr,
|
|
|
|
|
scratch, operands[0]);
|
|
|
|
|
alpha_set_memflags (seq, operands[1]);
|
2000-08-29 05:59:00 +02:00
|
|
|
|
|
1992-10-24 15:33:28 +01:00
|
|
|
|
emit_insn (seq);
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
(define_expand "reload_out<mode>"
|
|
|
|
|
[(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
|
|
|
|
|
(match_operand:RELOAD12 1 "register_operand" "r")
|
1992-10-24 15:33:28 +01:00
|
|
|
|
(match_operand:TI 2 "register_operand" "=&r")])]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
"!TARGET_BWX"
|
1998-04-15 01:50:17 +02:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
unsigned regno = REGNO (operands[2]);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
if (<MODE>mode == CQImode)
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (HImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (HImode, operands[1]);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
if (aligned_memory_operand (operands[0], <MODE>mode))
|
1992-10-24 15:33:28 +01:00
|
|
|
|
{
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
emit_insn (gen_reload_out<reloadmode>_aligned
|
1999-05-31 17:29:17 +02:00
|
|
|
|
(operands[0], operands[1],
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
gen_rtx_REG (SImode, regno),
|
|
|
|
|
gen_rtx_REG (SImode, regno + 1)));
|
1992-10-24 15:33:28 +01:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2007-04-20 21:35:55 +02:00
|
|
|
|
rtx addr = get_unaligned_address (operands[0]);
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
rtx scratch1 = gen_rtx_REG (DImode, regno);
|
|
|
|
|
rtx scratch2 = gen_rtx_REG (DImode, regno + 1);
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
rtx scratch3 = scratch1;
|
1992-10-24 15:33:28 +01:00
|
|
|
|
rtx seq;
|
|
|
|
|
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (REG_P (addr))
|
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to extend_{q,h}idi2.
(extend{qihi,qisi,hisi}2): Allow unaligned memory as arg 1 and pass to
extend_{q,h}idi2.
(unaligned_extend{q,h}idi): New patterns.
(extend{q,h}idi2): If unaligned memory, call above new patterns.
(ext{q,l,w}h recognizer): Update to proper RTL.
(ext define_split): Comment out for now; wrong and maybe useless.
(unaligned_{load,store}hi): Do similarly to QImode.
(movhi, reload_{in,out}hi): Call unaligned case differently.
From-SVN: r10882
1995-12-27 21:29:50 +01:00
|
|
|
|
scratch1 = addr;
|
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
|
|
|
|
|
scratch2, scratch3);
|
1992-10-24 15:33:28 +01:00
|
|
|
|
alpha_set_memflags (seq, operands[0]);
|
|
|
|
|
emit_insn (seq);
|
|
|
|
|
}
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1999-05-31 17:29:17 +02:00
|
|
|
|
|
|
|
|
|
;; Helpers for the above. The way reload is structured, we can't
|
|
|
|
|
;; always get a proper address for a stack slot during reload_foo
|
|
|
|
|
;; expansion, so we must delay our address manipulations until after.
|
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
(define_insn_and_split "reload_in<mode>_aligned"
|
|
|
|
|
[(set (match_operand:I12MODE 0 "register_operand" "=r")
|
|
|
|
|
(match_operand:I12MODE 1 "memory_operand" "m"))]
|
|
|
|
|
"!TARGET_BWX && (reload_in_progress || reload_completed)"
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
"#"
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
"!TARGET_BWX && reload_completed"
|
1999-05-31 17:29:17 +02:00
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
rtx aligned_mem, bitnum;
|
|
|
|
|
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
emit_insn (gen_aligned_load<reloadmode>
|
|
|
|
|
(gen_lowpart (DImode, operands[0]), aligned_mem, bitnum,
|
|
|
|
|
gen_rtx_REG (SImode, REGNO (operands[0]))));
|
1999-05-31 17:29:17 +02:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1999-05-31 17:29:17 +02:00
|
|
|
|
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
(define_insn_and_split "reload_out<mode>_aligned"
|
|
|
|
|
[(set (match_operand:I12MODE 0 "memory_operand" "=m")
|
|
|
|
|
(match_operand:I12MODE 1 "register_operand" "r"))
|
2015-02-10 18:49:45 +01:00
|
|
|
|
(clobber (match_operand:SI 2 "register_operand" "=&r"))
|
|
|
|
|
(clobber (match_operand:SI 3 "register_operand" "=&r"))]
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
"!TARGET_BWX && (reload_in_progress || reload_completed)"
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
"#"
|
predicates.md (aligned_memory_operand): Mark as define_special_predicate.
* config/alpha/predicates.md (aligned_memory_operand): Mark
as define_special_predicate.
(unaligned_memory_operand, normal_memory_operand): Likewise.
(reg_or_unaligned_mem_operand): Remove.
(any_memory_operand): Match the documentation and check for
non-renumbered pseudos during reload.
* config/alpha/alpha.c (alpha_secondary_reload): Rename from
alpha_secondary_reload_class, update to new interface, make static.
Handle CQImode like HImode. Remove FP subreg check.
(alpha_expand_mov): Use replace_equiv_address.
(alpha_expand_mov_nobwx): Use any_memory_operand.
(TARGET_SECONDARY_RELOAD): New.
* config/alpha/alpha.h (SECONDARY_INPUT_RELOAD_CLASS): Remove.
(SECONDARY_OUTPUT_RELOAD_CLASS): Remove.
* config/alpha/sync.md (I12MODE, I48MODE, modesuffix): Move ...
* config/alpha/alpha.md: ... here.
(RELOAD12, reloadmode): New.
(movcqi): New.
(reload_in<RELOAD12>): Macro-ize from reload_inqi, reload_inhi.
Don't handle the aligned case here.
(reload_out<RELOAD12>): Macro-ize from reload_outqi, reload_outhi.
(reload_in<I12MODE>_aligned): Macro-ize from reload_inqi_help,
reload_inhi_help. Don't expect a scratch register.
(reload_out<I12MODE>_aligned): Macro-ize from reload_outqi_help,
reload_outhi_help.
* config/alpha/alpha-protos.h (alpha_secondary_reload_class): Remove.
From-SVN: r124220
2007-04-27 16:47:57 +02:00
|
|
|
|
"!TARGET_BWX && reload_completed"
|
1999-05-31 17:29:17 +02:00
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
rtx aligned_mem, bitnum;
|
|
|
|
|
get_aligned_mem (operands[0], &aligned_mem, &bitnum);
|
|
|
|
|
emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
|
|
|
|
|
operands[2], operands[3]));
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1993-04-10 16:56:02 +02:00
|
|
|
|
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
;; Vector operations
|
|
|
|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
|
(define_mode_iterator VEC [V8QI V4HI V2SI])
|
2012-10-12 13:32:02 +02:00
|
|
|
|
(define_mode_iterator VEC12 [V8QI V4HI])
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
|
2004-12-23 09:08:59 +01:00
|
|
|
|
(define_expand "mov<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:VEC 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:VEC 1 "general_operand"))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2004-12-23 09:08:59 +01:00
|
|
|
|
if (alpha_expand_mov (<MODE>mode, operands))
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2005-01-20 04:59:00 +01:00
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:VEC 0 "register_operand")
|
|
|
|
|
(match_operand:VEC 1 "non_zero_const_operand"))]
|
2005-01-20 04:59:00 +01:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
if (alpha_split_const_mov (<MODE>mode, operands))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
|
2004-12-23 09:08:59 +01:00
|
|
|
|
(define_expand "movmisalign<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:VEC 0 "nonimmediate_operand")
|
|
|
|
|
(match_operand:VEC 1 "general_operand"))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2004-12-23 09:08:59 +01:00
|
|
|
|
alpha_expand_movmisalign (<MODE>mode, operands);
|
|
|
|
|
DONE;
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
})
|
|
|
|
|
|
2004-12-23 09:08:59 +01:00
|
|
|
|
(define_insn "*mov<mode>_fix"
|
2005-01-20 04:59:00 +01:00
|
|
|
|
[(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
|
|
|
|
|
(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
|
2011-03-25 01:34:56 +01:00
|
|
|
|
"register_operand (operands[0], <MODE>mode)
|
|
|
|
|
|| reg_or_0_operand (operands[1], <MODE>mode)"
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"@
|
|
|
|
|
bis $31,%r1,%0
|
2005-01-20 04:59:00 +01:00
|
|
|
|
#
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
ldq %0,%1
|
|
|
|
|
stq %r1,%0
|
|
|
|
|
cpys %R1,%R1,%0
|
|
|
|
|
ldt %0,%1
|
|
|
|
|
stt %R1,%0
|
|
|
|
|
ftoit %1,%0
|
|
|
|
|
itoft %1,%0"
|
2011-03-25 01:34:56 +01:00
|
|
|
|
[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
|
|
|
|
|
(set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
|
2012-10-12 13:32:02 +02:00
|
|
|
|
(define_insn "<code><mode>3"
|
|
|
|
|
[(set (match_operand:VEC12 0 "register_operand" "=r")
|
|
|
|
|
(any_maxmin:VEC12
|
|
|
|
|
(match_operand:VEC12 1 "reg_or_0_operand" "rW")
|
|
|
|
|
(match_operand:VEC12 2 "reg_or_0_operand" "rW")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
2012-10-12 13:32:02 +02:00
|
|
|
|
"<maxmin><modesuffix> %r1,%r2,%0"
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
[(set_attr "type" "mvi")])
|
2004-12-23 11:32:42 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "one_cmpl<mode>2"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(not:VEC (match_operand:VEC 1 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"ornot $31,%1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "and<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(and:VEC (match_operand:VEC 1 "register_operand" "r")
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"and %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*andnot<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"bic %2,%1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "ior<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(ior:VEC (match_operand:VEC 1 "register_operand" "r")
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"bis %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*iornot<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"ornot %2,%1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "xor<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(xor:VEC (match_operand:VEC 1 "register_operand" "r")
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r")))]
|
|
|
|
|
""
|
|
|
|
|
"xor %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*xornot<mode>3"
|
|
|
|
|
[(set (match_operand:VEC 0 "register_operand" "=r")
|
|
|
|
|
(not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
|
|
|
|
|
(match_operand:VEC 2 "register_operand" "r"))))]
|
|
|
|
|
""
|
|
|
|
|
"eqv %1,%2,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
2005-06-29 20:22:06 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "vec_shl_<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:VEC 0 "register_operand")
|
|
|
|
|
(ashift:DI (match_operand:VEC 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_6bit_operand")))]
|
2005-06-29 20:22:06 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (DImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (DImode, operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "vec_shr_<mode>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:VEC 0 "register_operand")
|
|
|
|
|
(lshiftrt:DI (match_operand:VEC 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_6bit_operand")))]
|
2005-06-29 20:22:06 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (DImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (DImode, operands[1]);
|
|
|
|
|
})
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
;; Bit field extract patterns which use ext[wlq][lh]
|
|
|
|
|
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(define_expand "extvmisaligndi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(sign_extract:DI (match_operand:BLK 1 "memory_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")
|
|
|
|
|
(match_operand:DI 3 "const_int_operand")))]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
|
|
|
|
|
if (INTVAL (operands[3]) % 8 != 0
|
|
|
|
|
|| (INTVAL (operands[2]) != 16
|
|
|
|
|
&& INTVAL (operands[2]) != 32
|
|
|
|
|
&& INTVAL (operands[2]) != 64))
|
|
|
|
|
FAIL;
|
|
|
|
|
|
|
|
|
|
alpha_expand_unaligned_load (operands[0], operands[1],
|
|
|
|
|
INTVAL (operands[2]) / 8,
|
2012-11-21 23:10:01 +01:00
|
|
|
|
INTVAL (operands[3]) / 8, 1);
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(define_expand "extzvdi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(zero_extract:DI (match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")
|
|
|
|
|
(match_operand:DI 3 "const_int_operand")))]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
1998-03-18 17:21:14 +01:00
|
|
|
|
/* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
|
1998-03-31 21:20:08 +02:00
|
|
|
|
if (INTVAL (operands[3]) % 8 != 0
|
|
|
|
|
|| (INTVAL (operands[2]) != 8
|
2012-11-21 23:10:01 +01:00
|
|
|
|
&& INTVAL (operands[2]) != 16
|
1998-03-31 21:20:08 +02:00
|
|
|
|
&& INTVAL (operands[2]) != 32
|
|
|
|
|
&& INTVAL (operands[2]) != 64))
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
FAIL;
|
2012-11-21 23:10:01 +01:00
|
|
|
|
})
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(define_expand "extzvmisaligndi"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
|
|
|
|
(zero_extract:DI (match_operand:BLK 1 "memory_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand")
|
|
|
|
|
(match_operand:DI 3 "const_int_operand")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.
|
|
|
|
|
We fail 8-bit fields, falling back on a simple byte load. */
|
|
|
|
|
if (INTVAL (operands[3]) % 8 != 0
|
|
|
|
|
|| (INTVAL (operands[2]) != 16
|
|
|
|
|
&& INTVAL (operands[2]) != 32
|
|
|
|
|
&& INTVAL (operands[2]) != 64))
|
|
|
|
|
FAIL;
|
2001-09-11 10:52:39 +02:00
|
|
|
|
|
2012-11-21 23:10:01 +01:00
|
|
|
|
alpha_expand_unaligned_load (operands[0], operands[1],
|
|
|
|
|
INTVAL (operands[2]) / 8,
|
|
|
|
|
INTVAL (operands[3]) / 8, 0);
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
|
2012-11-21 23:10:01 +01:00
|
|
|
|
(define_expand "insvmisaligndi"
|
|
|
|
|
[(set (zero_extract:DI (match_operand:BLK 0 "memory_operand")
|
|
|
|
|
(match_operand:DI 1 "const_int_operand")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 3 "register_operand"))]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
|
|
|
|
|
if (INTVAL (operands[2]) % 8 != 0
|
|
|
|
|
|| (INTVAL (operands[1]) != 16
|
|
|
|
|
&& INTVAL (operands[1]) != 32
|
|
|
|
|
&& INTVAL (operands[1]) != 64))
|
|
|
|
|
FAIL;
|
|
|
|
|
|
|
|
|
|
alpha_expand_unaligned_store (operands[0], operands[3],
|
2012-11-21 23:10:01 +01:00
|
|
|
|
INTVAL (operands[1]) / 8,
|
|
|
|
|
INTVAL (operands[2]) / 8);
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
|
|
|
|
|
;; Block move/clear, see alpha.c for more details.
|
|
|
|
|
;; Argument 0 is the destination
|
|
|
|
|
;; Argument 1 is the source
|
|
|
|
|
;; Argument 2 is the length
|
|
|
|
|
;; Argument 3 is the alignment
|
|
|
|
|
|
2004-07-07 21:25:01 +02:00
|
|
|
|
(define_expand "movmemqi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:BLK 0 "memory_operand")
|
|
|
|
|
(match_operand:BLK 1 "memory_operand"))
|
|
|
|
|
(use (match_operand:DI 2 "immediate_operand"))
|
|
|
|
|
(use (match_operand:DI 3 "immediate_operand"))])]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (alpha_expand_block_move (operands))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
|
2004-07-07 21:25:01 +02:00
|
|
|
|
(define_expand "movmemdi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:BLK 0 "memory_operand")
|
|
|
|
|
(match_operand:BLK 1 "memory_operand"))
|
|
|
|
|
(use (match_operand:DI 2 "immediate_operand"))
|
|
|
|
|
(use (match_operand:DI 3 "immediate_operand"))
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(use (match_dup 4))
|
|
|
|
|
(clobber (reg:DI 25))
|
|
|
|
|
(clobber (reg:DI 16))
|
|
|
|
|
(clobber (reg:DI 17))
|
|
|
|
|
(clobber (reg:DI 18))
|
|
|
|
|
(clobber (reg:DI 19))
|
|
|
|
|
(clobber (reg:DI 20))
|
|
|
|
|
(clobber (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))])]
|
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
|
2002-12-16 19:23:00 +01:00
|
|
|
|
|
2004-07-07 21:25:01 +02:00
|
|
|
|
(define_insn "*movmemdi_1"
|
md.texi: Document that the % constraint character must be at the beginning of the string.
gcc/
* doc/md.texi: Document that the % constraint character must
be at the beginning of the string.
* genoutput.c (validate_insn_alternatives): Check that '=',
'+' and '%' only appear at the beginning of a constraint.
* ira.c (commutative_constraint_p): Delete.
(ira_get_dup_out_num): Expect the '%' commutativity marker to be
at the start of the string.
* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
duplicate '='s.
* config/arm/neon.md (bicdi3_neon): Likewise.
* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
(slt_si, sltu_si): Likewise.
* config/vax/vax.md (sbcdi3): Likewise.
* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
(mul64): Move '%' to beginning of constraint.
* config/arm/arm.md (*xordi3_insn): Likewise.
* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
(xorsi3): Likewise.
From-SVN: r211031
2014-05-28 21:49:18 +02:00
|
|
|
|
[(set (match_operand:BLK 0 "memory_operand" "=m,m")
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(match_operand:BLK 1 "memory_operand" "m,m"))
|
|
|
|
|
(use (match_operand:DI 2 "nonmemory_operand" "r,i"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand:DI 3 "immediate_operand"))
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(use (match_operand:DI 4 "call_operand" "i,i"))
|
|
|
|
|
(clobber (reg:DI 25))
|
|
|
|
|
(clobber (reg:DI 16))
|
|
|
|
|
(clobber (reg:DI 17))
|
|
|
|
|
(clobber (reg:DI 18))
|
|
|
|
|
(clobber (reg:DI 19))
|
|
|
|
|
(clobber (reg:DI 20))
|
|
|
|
|
(clobber (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))]
|
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
|
|
|
|
{
|
2011-11-04 10:11:27 +01:00
|
|
|
|
operands [5] = alpha_use_linkage (operands [4], false, true);
|
2002-12-16 19:23:00 +01:00
|
|
|
|
switch (which_alternative)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
|
|
|
|
|
case 1:
|
|
|
|
|
return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
|
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2002-12-16 19:23:00 +01:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "multi")
|
|
|
|
|
(set_attr "length" "28")])
|
|
|
|
|
|
2005-06-28 21:56:23 +02:00
|
|
|
|
(define_expand "setmemqi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:BLK 0 "memory_operand")
|
|
|
|
|
(match_operand 2 "const_int_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "immediate_operand"))
|
|
|
|
|
(use (match_operand:DI 3 "immediate_operand"))])]
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2005-06-28 21:56:23 +02:00
|
|
|
|
/* If value to set is not zero, use the library routine. */
|
|
|
|
|
if (operands[2] != const0_rtx)
|
|
|
|
|
FAIL;
|
|
|
|
|
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
|
|
|
|
if (alpha_expand_block_clear (operands))
|
|
|
|
|
DONE;
|
|
|
|
|
else
|
|
|
|
|
FAIL;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2002-12-16 19:23:00 +01:00
|
|
|
|
|
2005-06-28 21:56:23 +02:00
|
|
|
|
(define_expand "setmemdi"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand:BLK 0 "memory_operand")
|
|
|
|
|
(match_operand 2 "const_int_operand"))
|
|
|
|
|
(use (match_operand:DI 1 "immediate_operand"))
|
|
|
|
|
(use (match_operand:DI 3 "immediate_operand"))
|
2005-06-28 21:56:23 +02:00
|
|
|
|
(use (match_dup 4))
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(clobber (reg:DI 25))
|
|
|
|
|
(clobber (reg:DI 16))
|
|
|
|
|
(clobber (reg:DI 17))
|
|
|
|
|
(clobber (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))])]
|
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
|
|
|
|
{
|
2005-06-28 21:56:23 +02:00
|
|
|
|
/* If value to set is not zero, use the library routine. */
|
|
|
|
|
if (operands[2] != const0_rtx)
|
|
|
|
|
FAIL;
|
|
|
|
|
|
2011-11-04 10:11:27 +01:00
|
|
|
|
operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
|
2002-12-16 19:23:00 +01:00
|
|
|
|
})
|
|
|
|
|
|
2004-07-07 21:25:01 +02:00
|
|
|
|
(define_insn "*clrmemdi_1"
|
md.texi: Document that the % constraint character must be at the beginning of the string.
gcc/
* doc/md.texi: Document that the % constraint character must
be at the beginning of the string.
* genoutput.c (validate_insn_alternatives): Check that '=',
'+' and '%' only appear at the beginning of a constraint.
* ira.c (commutative_constraint_p): Delete.
(ira_get_dup_out_num): Expect the '%' commutativity marker to be
at the start of the string.
* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
duplicate '='s.
* config/arm/neon.md (bicdi3_neon): Likewise.
* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
(slt_si, sltu_si): Likewise.
* config/vax/vax.md (sbcdi3): Likewise.
* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
(mul64): Move '%' to beginning of constraint.
* config/arm/arm.md (*xordi3_insn): Likewise.
* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
(xorsi3): Likewise.
From-SVN: r211031
2014-05-28 21:49:18 +02:00
|
|
|
|
[(set (match_operand:BLK 0 "memory_operand" "=m,m")
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(const_int 0))
|
|
|
|
|
(use (match_operand:DI 1 "nonmemory_operand" "r,i"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand:DI 2 "immediate_operand"))
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(use (match_operand:DI 3 "call_operand" "i,i"))
|
|
|
|
|
(clobber (reg:DI 25))
|
|
|
|
|
(clobber (reg:DI 16))
|
|
|
|
|
(clobber (reg:DI 17))
|
|
|
|
|
(clobber (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))]
|
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
|
|
|
|
{
|
2011-11-04 10:11:27 +01:00
|
|
|
|
operands [4] = alpha_use_linkage (operands [3], false, true);
|
2002-12-16 19:23:00 +01:00
|
|
|
|
switch (which_alternative)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
|
|
|
|
|
case 1:
|
|
|
|
|
return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
|
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2002-12-16 19:23:00 +01:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "multi")
|
|
|
|
|
(set_attr "length" "24")])
|
|
|
|
|
|
c-decl.c (init_decl_processing): Provide proper fallback symbol for __builtin_memset.
* c-decl.c (init_decl_processing): Provide proper fallback symbol
for __builtin_memset.
* expr.c (expand_builtin) [MEMSET]: Arg 3 type code is INTEGER_TYPE
not INTEGER_CST. Assert arg 3 is a constant.
* alpha.c (mode_width_operand): Accept 64-bit modes.
(mode_mask_operand): Likewise.
(print_operand): Likewise for 'M' and 'U' codes.
(alpha_expand_unaligned_load): New function.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_move): Likewise.
(alpha_expand_block_clear): Likewise.
* alpha.h (MOVE_RATIO): New define.
* alpha.md (extxl, ext*h, ins*l, mskxl): Name them.
(insql, insxh, mskxh, extv, extzv, insv, movstrqi, clrstrqi): New.
* alpha.h (ASM_OUTPUT_LOOP_ALIGN, ASM_OUTPUT_ALIGN_CODE): Set to 3.
(CONSTANT_ALIGNMENT, DATA_ALIGNMENT): Disable.
From-SVN: r17278
1998-01-02 05:48:04 +01:00
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1993-04-10 16:56:02 +02:00
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;; Subroutine of stack space allocation. Perform a stack probe.
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(define_expand "probe_stack"
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2012-10-14 14:50:45 +02:00
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[(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))]
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1993-04-10 16:56:02 +02:00
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""
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{
|
rtl.h (plus_constant, [...]): Merge into a single plus_constant function.
gcc/
* rtl.h (plus_constant, plus_constant_mode): Merge into a single
plus_constant function.
* explow.c (plus_constant, plus_constant_mode): Likewise. Assert
that the mode is sensible.
(use_anchored_address, round_push, allocate_dynamic_stack_space)
(probe_stack_range, anti_adjust_stack_and_probe): Update calls to
plus_constant.
* alias.c (canon_rtx): Likewise.
(init_alias_analysis): Likewise.
* builtins.c (expand_builtin_return_addr)
(expand_builtin_setjmp_setup, expand_builtin_longjmp)
(expand_builtin_nonlocal_goto, expand_builtin_update_setjmp_buf)
(expand_builtin_apply_args_1, expand_builtin_apply, expand_movstr)
(expand_builtin_stpcpy): Likewise.
* calls.c (save_fixed_argument_area, restore_fixed_argument_area)
(compute_argument_addresses, internal_arg_pointer_based_exp)
(expand_call, emit_library_call_value_1): Likewise.
* cfgexpand.c (expand_one_stack_var_at, expand_debug_expr): Likewise.
* combine-stack-adj.c (try_apply_stack_adjustment): Likewise.
* combine.c (combine_simplify_rtx, force_to_mode): Likewise.
* cse.c (insert_const_anchor, find_reg_offset_for_const)
(use_related_value, fold_rtx): Likewise.
* cselib.c (cselib_subst_to_values): Likewise.
* dse.c (record_store, check_mem_read_rtx): Likewise.
* dwarf2out.c (rtl_for_decl_location, gen_variable_die): Likewise.
* emit-rtl.c (adjust_address_1): Likewise.
* except.c (sjlj_emit_function_enter)
(expand_builtin_extract_return_addr)
(expand_builtin_frob_return_addr): Likewise.
* expmed.c (expand_divmod): Likewise.
* expr.c (move_by_pieces, store_by_pieces, store_by_pieces_1)
(emit_move_resolve_push, push_block, emit_push_insn, store_expr)
(expand_expr_addr_expr_1, expand_expr_real_1): Likewise.
* function.c (assign_stack_local_1)
(instantiate_virtual_regs_in_rtx): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* reload.c (find_reloads_address, form_sum)
(find_reloads_subreg_address): Likewise.
* reload1.c (init_reload, eliminate_regs_1)
(eliminate_regs_in_insn): Likewise.
* simplify-rtx.c (simplify_unary_operation_1)
(simplify_binary_operation_1, simplify_plus_minus): Likewise.
* var-tracking.c (compute_cfa_pointer, prepare_call_arguments)
(vt_add_function_parameter): Likewise.
* config/alpha/alpha.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/vms.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address_1)
(get_unaligned_address, alpha_expand_unaligned_load)
(alpha_expand_unaligned_store, alpha_expand_unaligned_load_words)
(alpha_expand_unaligned_store_words, alpha_expand_block_clear)
(alpha_expand_builtin_establish_vms_condition_handler)
(alpha_setup_incoming_varargs, emit_frame_store_1)
(alpha_expand_prologue, alpha_expand_epilogue)
(alpha_use_linkage): Likewise.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c (arm_trampoline_init, legitimize_pic_address)
(arm_load_pic_register, arm_pic_static_addr, arm_legitimize_address)
(thumb_legitimize_address, arm_gen_load_multiple_1)
(arm_gen_store_multiple_1, arm_gen_multiple_op, gen_ldm_seq)
(gen_stm_seq, gen_const_stm_seq, arm_block_move_unaligned_straight)
(arm_block_move_unaligned_loop, arm_gen_movmemqi, arm_reload_in_hi)
(arm_reload_out_hi, arm_reorg, vfp_emit_fstmd, emit_multi_reg_push)
(emit_sfm, thumb_set_frame_pointer, arm_expand_prologue)
(thumb1_emit_multi_reg_push, thumb1_expand_prologue)
(thumb_expand_movmemqi, arm_set_return_address)
(thumb_set_return_address): Likewise.
* config/arm/arm.md: Likewise.
* config/avr/avr.c (avr_incoming_return_addr_rtx)
(avr_prologue_setup_frame, expand_epilogue)
(avr_const_address_lo16): Likewise.
* config/bfin/bfin.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/bfin/bfin.c (setup_incoming_varargs, bfin_load_pic_reg)
(bfin_expand_prologue, bfin_trampoline_init, bfin_expand_call)
(bfin_output_mi_thunk): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline)
(c6x_output_mi_thunk): Likewise.
* config/cr16/cr16.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
* config/cris/cris.c (cris_return_addr_rtx, cris_split_movdx)
(cris_expand_prologue, cris_expand_epilogue, cris_gen_movem_load)
(cris_emit_movem_store, cris_trampoline_init): Likewise.
* config/cris/cris.md: Likewise.
* config/darwin.c (machopic_indirect_data_reference)
(machopic_legitimize_pic_address): Likewise.
* config/epiphany/epiphany.c (epiphany_emit_save_restore)
(epiphany_expand_prologue, epiphany_expand_epilogue)
(epiphany_trampoline_init): Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/fr30/fr30.c (fr30_move_double): Likewise.
* config/frv/frv.c (frv_dwarf_store, frv_expand_prologue)
(frv_expand_block_move, frv_expand_block_clear, frv_return_addr_rtx)
(frv_index_memory, unspec_got_name, frv_find_base_term)
(frv_output_dwarf_dtprel): Likewise.
* config/h8300/h8300.c (h8300_push_pop, h8300_return_addr_rtx)
(h8300_swap_into_er6, h8300_swap_out_of_er6): Likewise.
* config/i386/i386.h (RETURN_ADDR_RTX): Likewise.
* config/i386/i386.c (setup_incoming_varargs_64)
(setup_incoming_varargs_ms_64, choose_baseaddr)
(ix86_emit_save_reg_using_mov, ix86_adjust_stack_and_probe)
(ix86_emit_probe_stack_range, ix86_expand_prologue)
(ix86_emit_restore_reg_using_pop, ix86_emit_leave)
(ix86_expand_epilogue, legitimize_pic_address, ix86_legitimize_address)
(ix86_split_long_move, ix86_expand_movmem, ix86_expand_setmem)
(ix86_static_chain, ix86_trampoline_init, x86_this_parameter)
(x86_output_mi_thunk): Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (ia64_expand_load_address)
(ia64_expand_tls_address, ia64_expand_move, ia64_split_tmode)
(do_spill, ia64_trampoline_init): Likewise.
* config/iq2000/iq2000.c (iq2000_va_start)
(iq2000_emit_frame_related_store, iq2000_expand_prologue)
(iq2000_expand_eh_return, iq2000_setup_incoming_varargs)
(iq2000_print_operand, iq2000_legitimize_address): Likewise.
* config/lm32/lm32.c (lm32_setup_incoming_varargs): Likewise.
* config/m32c/m32c.c (m32c_return_addr_rtx)
(m32c_expand_insv): Likewise.
* config/m32r/m32r.c (m32r_setup_incoming_varargs)
(m32r_legitimize_pic_address, m32r_print_operand)
(m32r_print_operand_address): Likewise.
* config/m68k/linux.h (FINALIZE_TRAMPOLINE): Likewise.
* config/m68k/m68k.h (RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/m68k/m68k.c (m68k_emit_movem, m68k_expand_prologue)
(m68k_expand_epilogue, legitimize_pic_address)
(m68k_output_mi_thunk): Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c (mcore_expand_prolog): Likewise.
(mcore_expand_epilog): Likewise.
* config/mcore/mcore.md: Likewise.
* config/mep/mep.c (mep_allocate_initial_value)
(mep_expand_prologue, mep_expand_epilogue): Likewise.
* config/microblaze/microblaze.c (double_memory_operand)
(microblaze_block_move_loop): Likewise.
* config/mips/mips.c (mips_strip_unspec_address, mips_add_offset)
(mips_setup_incoming_varargs, mips_va_start, mips_block_move_loop)
(mips_print_operand, mips16e_save_restore_reg, mips_save_restore_reg)
(mips_expand_prologue, mips_epilogue_set_cfa)
(mips_expand_epilogue): Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c (mmix_dynamic_chain_address, mmix_return_addr_rtx)
(mmix_expand_prologue, mmix_expand_epilogue): Likewise.
* config/mn10300/mn10300.c (mn10300_gen_multiple_store)
(mn10300_builtin_saveregs, mn10300_trampoline_init): Likewise.
* config/moxie/moxie.h (INCOMING_RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/moxie/moxie.c (moxie_static_chain): Likewise.
* config/pa/pa.c (legitimize_pic_address, hppa_legitimize_address)
(store_reg, set_reg_plus_d, pa_expand_prologue, load_reg)
(pa_return_addr_rtx, hppa_builtin_saveregs)
(pa_trampoline_init): Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c (pdp11_expand_epilogue): Likewise.
* config/picochip/picochip.c (picochip_static_chain): Likewise.
* config/rs6000/rs6000.h (RS6000_SAVE_TOC): Likewise.
* config/rs6000/rs6000.c (rs6000_legitimize_address)
(setup_incoming_varargs, print_operand, rs6000_return_addr)
(rs6000_emit_eh_reg_restore, rs6000_emit_probe_stack_range)
(rs6000_emit_epilogue)
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rx/rx.c (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
* config/s390/s390.h (INITIAL_FRAME_ADDRESS_RTX): Likewise.
(DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/s390/s390.c (s390_decompose_address, legitimize_pic_address)
(s390_delegitimize_address, print_operand, annotate_constant_pool_refs)
(replace_constant_pool_ref, s390_return_addr_rtx, s390_back_chain_rtx)
(save_fpr, restore_fpr, save_gprs, restore_gprs, s390_emit_prologue)
(s390_emit_epilogue, s390_function_profiler): Likewise.
* config/s390/s390.md: Likewise.
* config/score/score.c (score_add_offset, score_prologue): Likewise.
* config/sh/sh.c (expand_block_move, push_regs, sh_builtin_saveregs)
(sh_output_mi_thunk): Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/sparc.h (DYNAMIC_CHAIN_ADDRESS, FRAME_ADDR_RTX)
(RETURN_ADDR_RTX, INCOMING_RETURN_ADDR_RTX): Likewise.
* config/sparc/sparc.c (sparc_legitimize_pic_address)
(sparc_emit_probe_stack_range, emit_save_or_restore_regs)
(emit_window_save, sparc_flat_expand_prologue, sparc_struct_value_rtx)
(emit_and_preserve): Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/spu/spu.c (spu_expand_insv, spu_machine_dependent_reorg)
(spu_setup_incoming_varargs, ea_load_store_inline)
(spu_expand_load): Likewise.
* config/stormy16/stormy16.c (xstormy16_expand_prologue)
(combine_bnp): Likewise.
* config/tilegx/tilegx.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilegx/tilegx.c (tilegx_setup_incoming_varargs)
(tilegx_expand_unaligned_load, tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilepro/tilepro.c (tilepro_setup_incoming_varargs)
(tilepro_expand_unaligned_load, tilepro_trampoline_init): Likewise.
* config/v850/v850.c (expand_prologue, expand_epilogue): Likewise.
* config/v850/v850.md: Likewise.
* config/vax/elf.h (EH_RETURN_STACKADJ_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/vax/vax.h (DYNAMIC_CHAIN_ADDRESS, RETURN_ADDR_RTX): Likewise.
* config/vax/vax.c (vax_add_reg_cfa_offset, vax_expand_prologue)
(print_operand_address, vax_trampoline_init): Likewise.
* config/xtensa/xtensa.c (xtensa_expand_prologue, xtensa_return_addr)
(xtensa_function_value_regno_p): Likewise.
From-SVN: r187199
2012-05-05 19:41:49 +02:00
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operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx,
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
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INTVAL (operands[0])));
|
1995-04-15 00:48:49 +02:00
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MEM_VOLATILE_P (operands[1]) = 1;
|
1993-04-10 16:56:02 +02:00
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1995-04-15 00:48:49 +02:00
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operands[0] = const0_rtx;
|
2001-07-15 17:38:52 +02:00
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})
|
1993-04-10 16:56:02 +02:00
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;; This is how we allocate stack space. If we are allocating a
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;; constant amount of space and we know it is less than 4096
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;; bytes, we need do nothing.
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;;
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;; If it is more than 4096 bytes, we need to probe the stack
|
2001-07-15 09:17:29 +02:00
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;; periodically.
|
1993-04-10 16:56:02 +02:00
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(define_expand "allocate_stack"
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[(set (reg:DI 30)
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(plus:DI (reg:DI 30)
|
2012-10-14 14:50:45 +02:00
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(match_operand:DI 1 "reg_or_cint_operand")))
|
1997-11-02 22:19:36 +01:00
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(set (match_operand:DI 0 "register_operand" "=r")
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(match_dup 2))]
|
1993-04-10 16:56:02 +02:00
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""
|
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{
|
2009-04-22 10:19:54 +02:00
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if (CONST_INT_P (operands[1])
|
1997-11-02 22:19:36 +01:00
|
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&& INTVAL (operands[1]) < 32768)
|
1993-04-10 16:56:02 +02:00
|
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{
|
1997-11-02 22:19:36 +01:00
|
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if (INTVAL (operands[1]) >= 4096)
|
1993-04-10 16:56:02 +02:00
|
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{
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/* We do this the same way as in the prologue and generate explicit
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probes. Then we update the stack by the constant. */
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int probed = 4096;
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emit_insn (gen_probe_stack (GEN_INT (- probed)));
|
1997-11-02 22:19:36 +01:00
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while (probed + 8192 < INTVAL (operands[1]))
|
1993-04-10 16:56:02 +02:00
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emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
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1997-11-02 22:19:36 +01:00
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if (probed + 4096 < INTVAL (operands[1]))
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emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
|
1993-04-10 16:56:02 +02:00
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}
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1997-11-02 22:19:36 +01:00
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operands[1] = GEN_INT (- INTVAL (operands[1]));
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operands[2] = virtual_stack_dynamic_rtx;
|
1993-04-10 16:56:02 +02:00
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}
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else
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{
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use rtx_code_label more
gcc/
* asan.c, cfgexpand.c, config/alpha/alpha.md, config/arm/arm.c,
config/epiphany/epiphany.md, config/h8300/h8300.c, config/i386/i386.md,
config/m32r/m32r.c, config/mcore/mcore.md, config/mips/mips.c,
config/mips/mips.md, config/nios2/nios2.c, config/pa/pa.c,
config/s390/s390.c, config/s390/s390.md, config/sh/sh-mem.cc,
config/sh/sh.c, config/sparc/sparc.c, dojump.c, function.c, optabs.c,
stmt.c: Assign the result of gen_label_rtx to rtx_code_label * instead
of rtx.
From-SVN: r214841
2014-09-03 02:52:11 +02:00
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rtx_code_label *out_label = 0;
|
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rtx_code_label *loop_label = gen_label_rtx ();
|
1995-04-15 00:48:49 +02:00
|
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rtx want = gen_reg_rtx (Pmode);
|
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rtx tmp = gen_reg_rtx (Pmode);
|
2009-05-12 11:43:48 +02:00
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rtx memref, test;
|
1993-04-10 16:56:02 +02:00
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1995-04-15 00:48:49 +02:00
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emit_insn (gen_subdi3 (want, stack_pointer_rtx,
|
1997-11-02 22:19:36 +01:00
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force_reg (Pmode, operands[1])));
|
1993-04-10 16:56:02 +02:00
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2009-04-22 10:19:54 +02:00
|
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if (!CONST_INT_P (operands[1]))
|
1993-04-10 16:56:02 +02:00
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{
|
2010-09-28 09:50:02 +02:00
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rtx limit = GEN_INT (4096);
|
1993-04-10 16:56:02 +02:00
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out_label = gen_label_rtx ();
|
2010-09-28 09:50:02 +02:00
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test = gen_rtx_LTU (VOIDmode, operands[1], limit);
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emit_jump_insn
|
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(gen_cbranchdi4 (test, operands[1], limit, out_label));
|
1993-04-10 16:56:02 +02:00
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}
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2010-09-28 09:50:02 +02:00
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emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
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1993-04-10 16:56:02 +02:00
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emit_label (loop_label);
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
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memref = gen_rtx_MEM (DImode, tmp);
|
1995-04-15 00:48:49 +02:00
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|
|
MEM_VOLATILE_P (memref) = 1;
|
|
|
|
|
emit_move_insn (memref, const0_rtx);
|
|
|
|
|
emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
|
2009-05-12 11:43:48 +02:00
|
|
|
|
test = gen_rtx_GTU (VOIDmode, tmp, want);
|
|
|
|
|
emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label));
|
1997-11-02 22:19:36 +01:00
|
|
|
|
|
alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO...
* alias.c: Change all uses of gen_rtx(FOO...) to gen_rtx_FOO;
change gen_rtx(expr...) to gen_rtx_fmt_foo(expr...).
* caller-save.c, calls.c, combine.c, cse.c: Likewise.
* dwarf2out.c, except.c, explow.c, expmed.c, expr.c: Likewise.
* final.c, flow.c, function.c, genpeep.c, haifa-sched.c: Likewise.
* halfpic.c, integrate.c, jump.c, local-alloc.c, loop.c: Likewise.
* profile.c, recog.c, reg-stack.c, regclass.c, regmove.c: Likewise.
* reload.c, reload1.c, reorg.c, sched.c, stmt.c, stupid.c: Likewise.
* unroll.c, varasm.c: Likewise.
* config/alpha/alpha.c, config/alpha/alpha.md: Likewise.
From-SVN: r17357
1998-01-15 00:10:50 +01:00
|
|
|
|
memref = gen_rtx_MEM (DImode, want);
|
1995-04-15 00:48:49 +02:00
|
|
|
|
MEM_VOLATILE_P (memref) = 1;
|
|
|
|
|
emit_move_insn (memref, const0_rtx);
|
1993-04-10 16:56:02 +02:00
|
|
|
|
|
|
|
|
|
if (out_label)
|
|
|
|
|
emit_label (out_label);
|
|
|
|
|
|
1995-04-15 00:48:49 +02:00
|
|
|
|
emit_move_insn (stack_pointer_rtx, want);
|
1997-11-02 22:19:36 +01:00
|
|
|
|
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
|
1993-04-10 16:56:02 +02:00
|
|
|
|
DONE;
|
|
|
|
|
}
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
1996-11-16 12:07:51 +01:00
|
|
|
|
|
1998-06-16 19:08:48 +02:00
|
|
|
|
;; This is used by alpha_expand_prolog to do the same thing as above,
|
|
|
|
|
;; except we cannot at that time generate new basic blocks, so we hide
|
|
|
|
|
;; the loop in this one insn.
|
|
|
|
|
|
|
|
|
|
(define_insn "prologue_stack_probe_loop"
|
1999-10-01 02:45:07 +02:00
|
|
|
|
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
|
2001-07-15 08:25:01 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand" "r")]
|
|
|
|
|
UNSPECV_PSPL)]
|
1998-06-16 19:08:48 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
1999-01-21 21:32:21 +01:00
|
|
|
|
operands[2] = gen_label_rtx ();
|
2002-12-16 19:23:00 +01:00
|
|
|
|
(*targetm.asm_out.internal_label) (asm_out_file, "L",
|
1999-01-21 21:32:21 +01:00
|
|
|
|
CODE_LABEL_NUMBER (operands[2]));
|
|
|
|
|
|
2001-07-15 17:38:52 +02:00
|
|
|
|
return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
|
|
|
|
|
}
|
1998-08-26 20:48:21 +02:00
|
|
|
|
[(set_attr "length" "16")
|
|
|
|
|
(set_attr "type" "multi")])
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "prologue"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(const_int 0)]
|
1998-06-16 19:08:48 +02:00
|
|
|
|
""
|
2000-05-23 03:44:05 +02:00
|
|
|
|
{
|
|
|
|
|
alpha_expand_prologue ();
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-05-23 03:44:05 +02:00
|
|
|
|
|
2000-05-23 12:42:56 +02:00
|
|
|
|
;; These take care of emitting the ldgp insn in the prologue. This will be
|
|
|
|
|
;; an lda/ldah pair and we want to align them properly. So we have two
|
|
|
|
|
;; unspec_volatile insns, the first of which emits the ldgp assembler macro
|
|
|
|
|
;; and the second of which emits nothing. However, both are marked as type
|
|
|
|
|
;; IADD (the default) so the alignment code in alpha.c does the right thing
|
|
|
|
|
;; with them.
|
|
|
|
|
|
|
|
|
|
(define_expand "prologue_ldgp"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
|
2000-05-23 03:44:05 +02:00
|
|
|
|
""
|
2001-09-19 20:55:22 +02:00
|
|
|
|
{
|
|
|
|
|
operands[0] = pic_offset_table_rtx;
|
|
|
|
|
operands[1] = gen_rtx_REG (Pmode, 27);
|
|
|
|
|
operands[2] = (TARGET_EXPLICIT_RELOCS
|
|
|
|
|
? GEN_INT (alpha_next_sequence_number++)
|
|
|
|
|
: const0_rtx);
|
|
|
|
|
})
|
2000-05-23 12:42:56 +02:00
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(define_insn "*ldgp_er_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPECV_LDGP1))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
"ldah %0,0(%1)\t\t!gpdisp!%2"
|
|
|
|
|
[(set_attr "cannot_copy" "true")])
|
2001-09-19 20:55:22 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "*ldgp_er_2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPEC_LDGP2))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
"lda %0,0(%1)\t\t!gpdisp!%2"
|
|
|
|
|
[(set_attr "cannot_copy" "true")])
|
2001-09-19 20:55:22 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "*prologue_ldgp_er_2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPECV_PLDGP2))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
"lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
|
|
|
|
|
[(set_attr "cannot_copy" "true")])
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
|
2000-05-23 12:42:56 +02:00
|
|
|
|
(define_insn "*prologue_ldgp_1"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPECV_LDGP1))]
|
2001-07-15 08:25:01 +02:00
|
|
|
|
""
|
2003-10-27 07:49:41 +01:00
|
|
|
|
"ldgp %0,0(%1)\n$%~..ng:"
|
|
|
|
|
[(set_attr "cannot_copy" "true")])
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
2000-05-23 12:42:56 +02:00
|
|
|
|
(define_insn "*prologue_ldgp_2"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2 "const_int_operand")]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
UNSPECV_PLDGP2))]
|
2001-07-15 08:25:01 +02:00
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
)
|
2000-05-23 12:42:56 +02:00
|
|
|
|
|
2000-05-28 04:25:46 +02:00
|
|
|
|
;; The _mcount profiling hook has special calling conventions, and
|
|
|
|
|
;; does not clobber all the registers that a normal call would. So
|
|
|
|
|
;; hide the fact this is a call at all.
|
|
|
|
|
|
|
|
|
|
(define_insn "prologue_mcount"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
|
2000-05-28 04:25:46 +02:00
|
|
|
|
""
|
2001-12-21 01:33:29 +01:00
|
|
|
|
{
|
|
|
|
|
if (TARGET_EXPLICIT_RELOCS)
|
2002-01-10 03:07:46 +01:00
|
|
|
|
/* Note that we cannot use a lituse_jsr reloc, since _mcount
|
|
|
|
|
cannot be called via the PLT. */
|
|
|
|
|
return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
|
2001-12-21 01:33:29 +01:00
|
|
|
|
else
|
|
|
|
|
return "lda $28,_mcount\;jsr $28,($28),_mcount";
|
|
|
|
|
}
|
2000-05-28 04:25:46 +02:00
|
|
|
|
[(set_attr "type" "multi")
|
|
|
|
|
(set_attr "length" "8")])
|
|
|
|
|
|
1998-06-16 19:08:48 +02:00
|
|
|
|
(define_insn "init_fp"
|
1999-10-14 12:27:50 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
1998-06-16 19:08:48 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand" "r"))
|
1999-10-14 12:27:50 +02:00
|
|
|
|
(clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
|
1998-06-16 19:08:48 +02:00
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"bis $31,%1,%0")
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "epilogue"
|
2000-01-30 21:27:57 +01:00
|
|
|
|
[(return)]
|
1998-06-16 19:08:48 +02:00
|
|
|
|
""
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"alpha_expand_epilogue ();")
|
1998-06-16 19:08:48 +02:00
|
|
|
|
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_expand "sibcall_epilogue"
|
|
|
|
|
[(return)]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OSF"
|
2000-05-23 12:42:56 +02:00
|
|
|
|
{
|
|
|
|
|
alpha_expand_epilogue ();
|
|
|
|
|
DONE;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2000-03-17 23:41:25 +01:00
|
|
|
|
|
1998-02-02 20:28:57 +01:00
|
|
|
|
(define_expand "builtin_longjmp"
|
2001-01-24 10:00:02 +01:00
|
|
|
|
[(use (match_operand:DI 0 "register_operand" "r"))]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OSF"
|
1998-02-02 20:28:57 +01:00
|
|
|
|
{
|
|
|
|
|
/* The elements of the buffer are, in order: */
|
|
|
|
|
rtx fp = gen_rtx_MEM (Pmode, operands[0]);
|
rtl.h (plus_constant, [...]): Merge into a single plus_constant function.
gcc/
* rtl.h (plus_constant, plus_constant_mode): Merge into a single
plus_constant function.
* explow.c (plus_constant, plus_constant_mode): Likewise. Assert
that the mode is sensible.
(use_anchored_address, round_push, allocate_dynamic_stack_space)
(probe_stack_range, anti_adjust_stack_and_probe): Update calls to
plus_constant.
* alias.c (canon_rtx): Likewise.
(init_alias_analysis): Likewise.
* builtins.c (expand_builtin_return_addr)
(expand_builtin_setjmp_setup, expand_builtin_longjmp)
(expand_builtin_nonlocal_goto, expand_builtin_update_setjmp_buf)
(expand_builtin_apply_args_1, expand_builtin_apply, expand_movstr)
(expand_builtin_stpcpy): Likewise.
* calls.c (save_fixed_argument_area, restore_fixed_argument_area)
(compute_argument_addresses, internal_arg_pointer_based_exp)
(expand_call, emit_library_call_value_1): Likewise.
* cfgexpand.c (expand_one_stack_var_at, expand_debug_expr): Likewise.
* combine-stack-adj.c (try_apply_stack_adjustment): Likewise.
* combine.c (combine_simplify_rtx, force_to_mode): Likewise.
* cse.c (insert_const_anchor, find_reg_offset_for_const)
(use_related_value, fold_rtx): Likewise.
* cselib.c (cselib_subst_to_values): Likewise.
* dse.c (record_store, check_mem_read_rtx): Likewise.
* dwarf2out.c (rtl_for_decl_location, gen_variable_die): Likewise.
* emit-rtl.c (adjust_address_1): Likewise.
* except.c (sjlj_emit_function_enter)
(expand_builtin_extract_return_addr)
(expand_builtin_frob_return_addr): Likewise.
* expmed.c (expand_divmod): Likewise.
* expr.c (move_by_pieces, store_by_pieces, store_by_pieces_1)
(emit_move_resolve_push, push_block, emit_push_insn, store_expr)
(expand_expr_addr_expr_1, expand_expr_real_1): Likewise.
* function.c (assign_stack_local_1)
(instantiate_virtual_regs_in_rtx): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* reload.c (find_reloads_address, form_sum)
(find_reloads_subreg_address): Likewise.
* reload1.c (init_reload, eliminate_regs_1)
(eliminate_regs_in_insn): Likewise.
* simplify-rtx.c (simplify_unary_operation_1)
(simplify_binary_operation_1, simplify_plus_minus): Likewise.
* var-tracking.c (compute_cfa_pointer, prepare_call_arguments)
(vt_add_function_parameter): Likewise.
* config/alpha/alpha.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/vms.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/alpha/alpha.c (alpha_legitimize_address_1)
(get_unaligned_address, alpha_expand_unaligned_load)
(alpha_expand_unaligned_store, alpha_expand_unaligned_load_words)
(alpha_expand_unaligned_store_words, alpha_expand_block_clear)
(alpha_expand_builtin_establish_vms_condition_handler)
(alpha_setup_incoming_varargs, emit_frame_store_1)
(alpha_expand_prologue, alpha_expand_epilogue)
(alpha_use_linkage): Likewise.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c (arm_trampoline_init, legitimize_pic_address)
(arm_load_pic_register, arm_pic_static_addr, arm_legitimize_address)
(thumb_legitimize_address, arm_gen_load_multiple_1)
(arm_gen_store_multiple_1, arm_gen_multiple_op, gen_ldm_seq)
(gen_stm_seq, gen_const_stm_seq, arm_block_move_unaligned_straight)
(arm_block_move_unaligned_loop, arm_gen_movmemqi, arm_reload_in_hi)
(arm_reload_out_hi, arm_reorg, vfp_emit_fstmd, emit_multi_reg_push)
(emit_sfm, thumb_set_frame_pointer, arm_expand_prologue)
(thumb1_emit_multi_reg_push, thumb1_expand_prologue)
(thumb_expand_movmemqi, arm_set_return_address)
(thumb_set_return_address): Likewise.
* config/arm/arm.md: Likewise.
* config/avr/avr.c (avr_incoming_return_addr_rtx)
(avr_prologue_setup_frame, expand_epilogue)
(avr_const_address_lo16): Likewise.
* config/bfin/bfin.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/bfin/bfin.c (setup_incoming_varargs, bfin_load_pic_reg)
(bfin_expand_prologue, bfin_trampoline_init, bfin_expand_call)
(bfin_output_mi_thunk): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline)
(c6x_output_mi_thunk): Likewise.
* config/cr16/cr16.h (EH_RETURN_HANDLER_RTX): Likewise.
* config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
* config/cris/cris.c (cris_return_addr_rtx, cris_split_movdx)
(cris_expand_prologue, cris_expand_epilogue, cris_gen_movem_load)
(cris_emit_movem_store, cris_trampoline_init): Likewise.
* config/cris/cris.md: Likewise.
* config/darwin.c (machopic_indirect_data_reference)
(machopic_legitimize_pic_address): Likewise.
* config/epiphany/epiphany.c (epiphany_emit_save_restore)
(epiphany_expand_prologue, epiphany_expand_epilogue)
(epiphany_trampoline_init): Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/fr30/fr30.c (fr30_move_double): Likewise.
* config/frv/frv.c (frv_dwarf_store, frv_expand_prologue)
(frv_expand_block_move, frv_expand_block_clear, frv_return_addr_rtx)
(frv_index_memory, unspec_got_name, frv_find_base_term)
(frv_output_dwarf_dtprel): Likewise.
* config/h8300/h8300.c (h8300_push_pop, h8300_return_addr_rtx)
(h8300_swap_into_er6, h8300_swap_out_of_er6): Likewise.
* config/i386/i386.h (RETURN_ADDR_RTX): Likewise.
* config/i386/i386.c (setup_incoming_varargs_64)
(setup_incoming_varargs_ms_64, choose_baseaddr)
(ix86_emit_save_reg_using_mov, ix86_adjust_stack_and_probe)
(ix86_emit_probe_stack_range, ix86_expand_prologue)
(ix86_emit_restore_reg_using_pop, ix86_emit_leave)
(ix86_expand_epilogue, legitimize_pic_address, ix86_legitimize_address)
(ix86_split_long_move, ix86_expand_movmem, ix86_expand_setmem)
(ix86_static_chain, ix86_trampoline_init, x86_this_parameter)
(x86_output_mi_thunk): Likewise.
* config/i386/i386.md: Likewise.
* config/ia64/ia64.c (ia64_expand_load_address)
(ia64_expand_tls_address, ia64_expand_move, ia64_split_tmode)
(do_spill, ia64_trampoline_init): Likewise.
* config/iq2000/iq2000.c (iq2000_va_start)
(iq2000_emit_frame_related_store, iq2000_expand_prologue)
(iq2000_expand_eh_return, iq2000_setup_incoming_varargs)
(iq2000_print_operand, iq2000_legitimize_address): Likewise.
* config/lm32/lm32.c (lm32_setup_incoming_varargs): Likewise.
* config/m32c/m32c.c (m32c_return_addr_rtx)
(m32c_expand_insv): Likewise.
* config/m32r/m32r.c (m32r_setup_incoming_varargs)
(m32r_legitimize_pic_address, m32r_print_operand)
(m32r_print_operand_address): Likewise.
* config/m68k/linux.h (FINALIZE_TRAMPOLINE): Likewise.
* config/m68k/m68k.h (RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/m68k/m68k.c (m68k_emit_movem, m68k_expand_prologue)
(m68k_expand_epilogue, legitimize_pic_address)
(m68k_output_mi_thunk): Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c (mcore_expand_prolog): Likewise.
(mcore_expand_epilog): Likewise.
* config/mcore/mcore.md: Likewise.
* config/mep/mep.c (mep_allocate_initial_value)
(mep_expand_prologue, mep_expand_epilogue): Likewise.
* config/microblaze/microblaze.c (double_memory_operand)
(microblaze_block_move_loop): Likewise.
* config/mips/mips.c (mips_strip_unspec_address, mips_add_offset)
(mips_setup_incoming_varargs, mips_va_start, mips_block_move_loop)
(mips_print_operand, mips16e_save_restore_reg, mips_save_restore_reg)
(mips_expand_prologue, mips_epilogue_set_cfa)
(mips_expand_epilogue): Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c (mmix_dynamic_chain_address, mmix_return_addr_rtx)
(mmix_expand_prologue, mmix_expand_epilogue): Likewise.
* config/mn10300/mn10300.c (mn10300_gen_multiple_store)
(mn10300_builtin_saveregs, mn10300_trampoline_init): Likewise.
* config/moxie/moxie.h (INCOMING_RETURN_ADDR_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/moxie/moxie.c (moxie_static_chain): Likewise.
* config/pa/pa.c (legitimize_pic_address, hppa_legitimize_address)
(store_reg, set_reg_plus_d, pa_expand_prologue, load_reg)
(pa_return_addr_rtx, hppa_builtin_saveregs)
(pa_trampoline_init): Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c (pdp11_expand_epilogue): Likewise.
* config/picochip/picochip.c (picochip_static_chain): Likewise.
* config/rs6000/rs6000.h (RS6000_SAVE_TOC): Likewise.
* config/rs6000/rs6000.c (rs6000_legitimize_address)
(setup_incoming_varargs, print_operand, rs6000_return_addr)
(rs6000_emit_eh_reg_restore, rs6000_emit_probe_stack_range)
(rs6000_emit_epilogue)
(rs6000_machopic_legitimize_pic_address): Likewise.
* config/rx/rx.c (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
* config/s390/s390.h (INITIAL_FRAME_ADDRESS_RTX): Likewise.
(DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/s390/s390.c (s390_decompose_address, legitimize_pic_address)
(s390_delegitimize_address, print_operand, annotate_constant_pool_refs)
(replace_constant_pool_ref, s390_return_addr_rtx, s390_back_chain_rtx)
(save_fpr, restore_fpr, save_gprs, restore_gprs, s390_emit_prologue)
(s390_emit_epilogue, s390_function_profiler): Likewise.
* config/s390/s390.md: Likewise.
* config/score/score.c (score_add_offset, score_prologue): Likewise.
* config/sh/sh.c (expand_block_move, push_regs, sh_builtin_saveregs)
(sh_output_mi_thunk): Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/sparc.h (DYNAMIC_CHAIN_ADDRESS, FRAME_ADDR_RTX)
(RETURN_ADDR_RTX, INCOMING_RETURN_ADDR_RTX): Likewise.
* config/sparc/sparc.c (sparc_legitimize_pic_address)
(sparc_emit_probe_stack_range, emit_save_or_restore_regs)
(emit_window_save, sparc_flat_expand_prologue, sparc_struct_value_rtx)
(emit_and_preserve): Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/spu/spu.c (spu_expand_insv, spu_machine_dependent_reorg)
(spu_setup_incoming_varargs, ea_load_store_inline)
(spu_expand_load): Likewise.
* config/stormy16/stormy16.c (xstormy16_expand_prologue)
(combine_bnp): Likewise.
* config/tilegx/tilegx.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilegx/tilegx.c (tilegx_setup_incoming_varargs)
(tilegx_expand_unaligned_load, tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.h (DYNAMIC_CHAIN_ADDRESS): Likewise.
* config/tilepro/tilepro.c (tilepro_setup_incoming_varargs)
(tilepro_expand_unaligned_load, tilepro_trampoline_init): Likewise.
* config/v850/v850.c (expand_prologue, expand_epilogue): Likewise.
* config/v850/v850.md: Likewise.
* config/vax/elf.h (EH_RETURN_STACKADJ_RTX): Likewise.
(EH_RETURN_HANDLER_RTX): Likewise.
* config/vax/vax.h (DYNAMIC_CHAIN_ADDRESS, RETURN_ADDR_RTX): Likewise.
* config/vax/vax.c (vax_add_reg_cfa_offset, vax_expand_prologue)
(print_operand_address, vax_trampoline_init): Likewise.
* config/xtensa/xtensa.c (xtensa_expand_prologue, xtensa_return_addr)
(xtensa_function_value_regno_p): Likewise.
From-SVN: r187199
2012-05-05 19:41:49 +02:00
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rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8));
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rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16));
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1998-02-02 20:28:57 +01:00
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rtx pv = gen_rtx_REG (Pmode, 27);
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/* This bit is the same as expand_builtin_longjmp. */
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emit_move_insn (hard_frame_pointer_rtx, fp);
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emit_move_insn (pv, lab);
|
2011-03-03 22:56:58 +01:00
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emit_stack_restore (SAVE_NONLOCAL, stack);
|
rtl.h (emit_clobber, [...]): Declare.
gcc/
* rtl.h (emit_clobber, gen_clobber, emit_use, gen_use): Declare.
* emit-rtl.c (emit_clobber, gen_clobber, emit_use, gen_use): New
functions. Do not emit uses and clobbers of CONCATs; individually
use and clobber their operands.
* builtins.c (expand_builtin_setjmp_receiver): Use emit_clobber,
gen_clobber, emit_use and gen_use.
(expand_builtin_longjmp, expand_builtin_nonlocal_goto): Likewise.
(expand_builtin_return): Likewise.
* cfgbuild.c (count_basic_blocks): Likewise.
* cfgrtl.c (rtl_flow_call_edges_add): Likewise.
* explow.c (emit_stack_restore): Likewise.
* expmed.c (extract_bit_field_1): Likewise.
* expr.c (convert_move, emit_move_complex_parts): Likewise.
(emit_move_multi_word, store_constructor): Likewise.
* function.c (do_clobber_return_reg, do_use_return_reg): Likewise.
(thread_prologue_and_epilogue_insns): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* optabs.c (widen_operand, expand_binop): Likewise.
(expand_doubleword_bswap, emit_no_conflict_block): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (eliminate_regs_in_insn): Likewise.
* stmt.c (expand_nl_goto_receiver): Likewise.
* config/alpha/alpha.md (builtin_longjmp): Likewise.
* config/arc/arc.md (*movdi_insn, *movdf_insn): Likewise.
* config/arm/arm.c (arm_load_pic_register): Likewise.
(thumb1_expand_epilogue, thumb_set_return_address): Likewise.
* config/arm/arm.md (untyped_return): Likewise.
* config/arm/linux-elf.h (PROFILE_HOOK): Likewise.
* config/avr/avr.c (expand_prologue): Likewise.
* config/bfin/bfin.c (do_unlink): Likewise.
* config/bfin/bfin.md (<optab>di3, adddi3, subdi3): Likewise.
* config/cris/cris.c (cris_expand_prologue): Likewise.
* config/darwin.c (machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/frv/frv.c (frv_frame_access, frv_expand_epilogue): Likewise.
(frv_ifcvt_modify_insn, frv_expand_mdpackh_builtin): Likewise.
* config/i386/i386.c (ix86_expand_vector_move_misalign): Likewise.
(ix86_expand_convert_uns_didf_sse): Likewise.
(ix86_expand_vector_init_general): Likewise.
* config/ia64/ia64.md (eh_epilogue): Likewise.
* config/iq2000/iq2000.c (iq2000_expand_epilogue): Likewise.
* config/m32c/m32c.c (m32c_emit_eh_epilogue): Likewise.
* config/m32r/m32r.c (m32r_reload_lr): Likewise.
(config/iq2000/iq2000.c): Likewise.
* config/mips/mips.md (fixuns_truncdfsi2): Likewise.
(fixuns_truncdfdi2, fixuns_truncsfsi2, fixuns_truncsfdi2): Likewise.
(builtin_longjmp): Likewise.
* config/mn10300/mn10300.md (call, call_value): Likewise.
* config/pa/pa.md (nonlocal_goto, nonlocal_longjmp): Likewise.
* config/pdp11/pdp11.md (abshi2): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
* config/s390/s390.c (s390_emit_prologue): Likewise.
* config/s390/s390.md (movmem_long, setmem_long): Likewise.
(cmpmem_long, extendsidi2, zero_extendsidi2, udivmoddi4): Likewise.
(builtin_setjmp_receiver, restore_stack_nonlocal): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(output_stack_adjust, sh_expand_epilogue): Likewise.
(sh_set_return_address, sh_expand_t_scc): Likewise.
* config/sparc/sparc.c (load_pic_register): Likewise.
* config/sparc/sparc.md (untyped_return, nonlocal_goto): Likewise.
* config/spu/spu.c (spu_expand_epilogue): Likewise.
* config/v850/v850.c (expand_epilogue): Likewise.
From-SVN: r136251
2008-06-01 11:47:28 +02:00
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emit_use (hard_frame_pointer_rtx);
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emit_use (stack_pointer_rtx);
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1998-02-02 20:28:57 +01:00
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/* Load the label we are jumping through into $27 so that we know
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where to look for it when we get back to setjmp's function for
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restoring the gp. */
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2001-01-24 10:00:02 +01:00
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emit_jump_insn (gen_builtin_longjmp_internal (pv));
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emit_barrier ();
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1998-12-25 23:08:13 +01:00
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DONE;
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2001-07-15 17:38:52 +02:00
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})
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1997-05-16 03:00:58 +02:00
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2001-01-24 10:00:02 +01:00
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;; This is effectively a copy of indirect_jump, but constrained such
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;; that register renaming cannot foil our cunning plan with $27.
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(define_insn "builtin_longjmp_internal"
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[(set (pc)
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2001-07-15 08:25:01 +02:00
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(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
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UNSPECV_LONGJMP))]
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2001-01-24 10:00:02 +01:00
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""
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"jmp $31,(%0),0"
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[(set_attr "type" "ibr")])
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2004-12-05 20:52:24 +01:00
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(define_expand "builtin_setjmp_receiver"
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2012-10-14 14:50:45 +02:00
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[(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)]
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"TARGET_ABI_OSF")
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alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
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2004-12-05 20:52:24 +01:00
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(define_insn_and_split "*builtin_setjmp_receiver_1"
|
2012-10-14 14:50:45 +02:00
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[(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)]
|
2004-12-05 20:52:24 +01:00
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"TARGET_ABI_OSF"
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{
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if (TARGET_EXPLICIT_RELOCS)
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return "#";
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else
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return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
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}
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"&& TARGET_EXPLICIT_RELOCS && reload_completed"
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[(set (match_dup 1)
|
2001-09-19 20:55:22 +02:00
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(unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
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(set (match_dup 1)
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(unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
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{
|
2004-12-05 20:52:24 +01:00
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if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
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emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
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UNSPECV_SETJMPR_ER));
|
2001-09-19 20:55:22 +02:00
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operands[1] = pic_offset_table_rtx;
|
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operands[2] = gen_rtx_REG (Pmode, 27);
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operands[3] = GEN_INT (alpha_next_sequence_number++);
|
2004-12-05 20:52:24 +01:00
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}
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[(set_attr "length" "12")
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(set_attr "type" "multi")])
|
2001-09-19 20:55:22 +02:00
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2004-12-05 20:52:24 +01:00
|
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(define_insn "*builtin_setjmp_receiver_er_sl_1"
|
2012-10-14 14:50:45 +02:00
|
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[(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)]
|
2012-03-14 18:58:35 +01:00
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"TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
|
2004-12-05 20:52:24 +01:00
|
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"lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
|
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2009-08-21 08:01:23 +02:00
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;; When flag_reorder_blocks_and_partition is in effect, compiler puts
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;; exception landing pads in a cold section. To prevent inter-section offset
|
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;; calculation, a jump to original landing pad is emitted in the place of the
|
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;; original landing pad. Since landing pad is moved, RA-relative GP
|
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;; calculation in the prologue of landing pad breaks. To solve this problem,
|
Remove obsolete Tru64 UNIX V5.1B support
libstdc++-v3:
* configure.host: Remove osf* handling.
* config/os/osf: Remove.
* doc/xml/manual/using.xml: Remove OSF reference.
* testsuite/18_support/pthread_guard.cc: Remove alpha*-*-osf*
handling.
* testsuite/20_util/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* testsuite/20_util/shared_ptr/thread/mutex_weaktoshared.cc:
Likewise.
* testsuite/21_strings/basic_string/pthread18185.cc: Likewise.
* testsuite/21_strings/basic_string/pthread4.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-1.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-2.cc: Likewise.
* testsuite/23_containers/list/pthread1.cc: Likewise.
* testsuite/23_containers/list/pthread5.cc: Likewise.
* testsuite/23_containers/map/pthread6.cc: Likewise.
* testsuite/23_containers/vector/debug/multithreaded_swap.cc:
Likewise.
* testsuite/27_io/basic_ofstream/pthread2.cc: Likewise.
* testsuite/27_io/basic_ostringstream/pthread3.cc: Likewise.
* testsuite/30_threads/async/42819.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/any.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/async.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/launch.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/sync.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/39909.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/call_once1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/50862.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/45133.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/share.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/valid.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock_guard/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/swap.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/7.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/8.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/9.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/moveable.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/hardware_concurrency.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/thread/swap/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/2.cc:
Likewise.
* libstdc++-v3/testsuite/ext/rope/pthread7-rope.cc: Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/mutex_weaktoshared.cc: Likewise.
libobjc:
* configure.ac (enable_objc_gc): Remove alpha*-dec-osf* handling.
* configure: Regenerate.
* thr.c (_XOPEN_SOURCE): Define unconditionally.
libjava:
* configure.ac (alpha*-dec-osf*): Remove.
* configure: Regenerate.
* configure.host (alpha*-dec-osf*): Remove.
* gnu/java/net/natPlainDatagramSocketImplPosix.cc (setOption): Use
IPV6_MULTICAST_IF unconditionally.
* gnu/java/net/natPlainDatagramSocketImplWin32.cc (setOption):
Likewise.
* gnu/java/net/natPlainSocketImplPosix.cc
(gnu::java::net::PlainSocketImpl::accept): Use ::accept instead of
_Jv_accept.
* include/posix-signal.h [__alpha__ && __osf__]: Remove.
* include/posix.h (_POSIX_PII_SOCKET): Don't define.
(_Jv_accept): Remove.
* java/io/File.java (File._access): Rename to access.
Change callers.
(File._stat): Likewise.
* java/io/File.h: Regenerate.
* classpath/lib/java/io/File.class: Regenerate.
* java/io/natFilePosix.cc (java::io::File::_access): Rename to
access.
(java::io::File::_stat): Rename to stat.
* java/io/natFileWin32.cc: Likewise.
* testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation):
Remove alpha*-dec-osf* handling.
* testsuite/libjava.jvmti/jvmti-interp.exp
(gcj_jni_compile_c_to_so): Likewise.
* testsuite/libjava.jvmti/jvmti.exp (gcj_jvmti_compile_cxx_to_o):
Likewise.
libitm:
* configure.tgt (*-*-osf*): Remove.
* configure: Regenerate.
libgomp:
* configure.tgt (alpha*-dec-osf*): Remove.
* config/osf/sem.h: Remove.
* config/posix/lock.c (_XOPEN_SOURCE): Define unconditionally.
libgfortran:
* configure.ac: Remove Tru64 reference.
* acinclude.m4 (LIBGFOR_GTHREAD_WEAK): Remove alpha*-dec-osf*
handling.
* configure: Regenerate.
* intrinsics/c99_functions.c [__osf__]: Remove.
libgcc:
* config.host: Remove alpha*-dec-osf5.1* handling.
* config/alpha/gthr-posix.c: Remove.
* config/alpha/libgcc-osf5.ver: Remove.
* config/alpha/osf5-unwind.h: Remove.
* config/alpha/t-osf-pthread: Remove.
* config/alpha/t-slibgcc-osf: Remove.
* config/t-crtfm (crtfastmath.o): Remove -frandom-seed.
* gthr-posix.h [!_REENTRANT && __osf__] (_REENTRANT): Don't define.
[__osf__ && _PTHREAD_USE_MANGLED_NAMES_]: Remove.
* mkmap-flat.awk: Remove osf_export handling.
gnattools:
* configure.ac: Remove alpha*-dec-osf* handling.
* configure: Regenerate.
gcc/testsuite:
* g++.dg/abi/rtti3.C: Remove alpha*-dec-osf* handling.
* g++.dg/abi/thunk4.C: Likewise.
* g++.dg/cdce3.C: Don't skip on*-dec-osf5*.
Adapt line numbers.
* g++.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* g++.dg/cpp0x/constexpr-rom.C: Likewise.
* g++.dg/eh/spbp.C: Likewise.
* g++.dg/ext/label13.C: Likewise.
* g++.dg/guality/guality.exp: Likewise.
* g++.dg/other/anon5.C: Likewise.
* g++.dg/other/pragma-ep-1.C: Remove.
* g++.dg/warn/miss-format-1.C: Remove alpha*-dec-osf* handling.
* g++.dg/warn/pr31246.C: Likewise.
* g++.dg/warn/weak1.C: Likewise.
* g++.old-deja/g++.eh/badalloc1.C: Likewise.
* g++.old-deja/g++.ext/attrib5.C: Likewise.
* gcc.c-torture/compile/limits-declparen.c: Likewise.
* gcc.c-torture/compile/limits-pointer.c: Likewise.
* gcc.c-torture/execute/20001229-1.c: Remove __osf__ handling.
* gcc.dg/attr-weakref-1.c: Remove alpha*-dec-osf* handling.
* gcc.dg/c99-stdint-6.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/c99-tgmath-1.c: Likewise.
* gcc.dg/c99-tgmath-2.c: Likewise.
* gcc.dg/c99-tgmath-3.c: Likewise.
* gcc.dg/c99-tgmath-4.c: Likewise.
* gcc.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* gcc.dg/debug/pr49032.c: Likewise.
* gcc.dg/guality/guality.exp: Likewise.
* gcc.dg/intmax_t-1.c: Likewise.
* gcc.dg/pr48616.c: Likewise.
* gcc.dg/pragma-ep-1.c: Remove.
* gcc.dg/pragma-ep-2.c: Remove.
* gcc.dg/pragma-ep-3.c: Remove.
* gcc.dg/torture/pr47917.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/tree-ssa/pr42585.c: Remove alpha*-dec-osf* handling.
* gcc.misc-tests/gcov-14.c: Likewise.
* gfortran.dg/guality/guality.exp: Likewise.
* lib/target-supports.exp (check_weak_available): Likewise.
(add_options_for_tls): Likewise.
(check_ascii_locale_available): Likewise.
* obj-c++.dg/dwarf-2.mm: Likewise.
* objc.dg/dwarf-1.m: Likewise.
* objc.dg/dwarf-2.m: Likewise.
gcc/c-family:
* c-cppbuiltin.c (c_cpp_builtins): Remove #pragma extern_prefix
handling.
* c-pragma.c (handle_pragma_extern_prefix): Remove.
(init_pragma): Don't register extern_prefix.
gcc/po:
* EXCLUDES (mips-tdump.c, mips-tfile.c): Remove.
gcc:
* config.gcc (alpha*-dec-osf5.1*): Remove.
* config.host (alpha*-dec-osf*): Remove.
* configure.ac (*-*-osf*): Remove.
(alpha*-dec-osf*): Remove.
* configure: Regenerate.
* config/alpha/host-osf.c, config/alpha/osf5.h,
config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf:
Remove.
* config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove.
* config/alpha/alpha.c (struct machine_function): Update comment.
(alpha_start_function): Remove Tru64 UNIX as handling for
max_frame_size.
* config/alpha/alpha.md ("exception_receiver"): Remove
TARGET_LD_BUGGY_LDGP.
("*exception_receiver_2"): Likewise.
* except.c (finish_eh_generation): Remove Tru64 reference.
* ginclude/stdarg.h [_HIDDEN_VA_LIST]: Don't undef _VA_LIST.
* system.h (TARGET_HANDLE_PRAGMA_EXTERN_PREFIX): Poison.
* target.def (handle_pragma_extern_prefix): Remove.
* Makefile.in (mips-tfile.o-warn): Remove.
(ALL_HOST_BACKEND_OBJS): Remove mips-tfile.o, mips-tdump.o.
(mips-tfile, mips-tfile.o, mips-tdump, mips-tdump.o): Remove.
* mips-tdump.c, mips-tfile.c: Remove.
* doc/extend.texi (Symbol-Renaming Pragmas): Remove #pragma
extern_prefix.
* doc/install.texi (Binaries): Remove Tru64 UNIX reference.
(Specific, alpha*-dec-osf5.1): Note removal.
* doc/tm.texi.in (Misc, TARGET_HANDLE_PRAGMA_EXTERN_PREFIX):
Remove.
* doc/tm.texi: Regenerate.
* doc/trouble.texi (Cross-Compiler Problems): Remove.
gcc/ada:
* gcc-interface/Makefile.in (alpha*-dec-osf*): Remove.
* a-intnam-tru64.ads, mlib-tgt-specific-tru64.adb,
s-mastop-tru64.adb, s-osinte-tru64.adb, s-osinte-tru64.ads,
s-taprop-tru64.adb, s-tasinf-tru64.ads, s-taspri-tru64.ads,
system-tru64.ads: Remove.
* adaint.c (__gnat_number_of_cpus) [__alpha__ && __osf__]:
Remove.
[IS_CROSS] [!(__alpha__ && __osf__)]: Remove.
* env.c [__alpha__ && __osf__]: Remove.
* gsocket.h (_OSF_SOURCE): Remove.
(HAVE_THREAD_SAFE_GETxxxBYyyy) [__osf__]: Remove.
* init.c [__alpha__ && __osf__]: Remove.
* link.c [__osf__]: Remove.
* s-oscons-tmplt.c [__alpha__ && __osf__]: Remove.
[__osf__ && !_SS_MAXSIZE]: Remove.
* sysdep.c [__osf__]: Remove.
* terminals.c [__alpha__ && __osf__]: Remove.
[OSF1]: Remove.
* g-traceb.ads: Remove Tru64 reference.
* g-trasym.ads: Likewise.
* gnat_ugn.texi (Linking a Mixed C++ & Ada Program): Likewise.
(Summary of Run-Time Configurations): Likewise.
* memtrack.adb: Likewise.
fixincludes:
* inclhack.def (alpha___extern_prefix): Remove.
(alpha___extern_prefix_standards): Remove.
(alpha___extern_prefix_sys_stat): Remove.
(alpha_bad_lval): Remove.
(alpha_pthread): Remove.
(alpha_pthread_gcc): Remove.
(alpha_pthread_init): Remove.
* fixincl.x: Regenerate.
* tests/base/pthread.h [ALPHA_PTHREAD_CHECK]: Remove.
[ALPHA_PTHREAD_GCC_CHECK]: Remove.
[ALPHA_PTHREAD_INIT_CHECK]: Remove.
* tests/base/standards.h: Remove.
* tests/base/sys/stat.h [ALPHA___EXTERN_PREFIX_SYS_STAT_CHECK]:
Remove.
* tests/base/testing.h [ALPHA___EXTERN_PREFIX_CHECK]: Remove.
[ALPHA_BAD_LVAL_CHECK]: Remove.
contrib:
* config-list.mk (LIST): Remove alpha-dec-osf5.1.
config:
* weakref.m4 (GCC_CHECK_ELF_STYLE_WEAKREF): Remove
alpha*-dec-osf*.
toplevel:
* MAINTAINERS (OS Port Maintainers): Remove osf.
* configure.ac (enable_libgomp): Remove *-*-osf*.
(with_stabs): Remove alpha*-*-osf*.
* configure: Regenerate.
From-SVN: r185240
2012-03-12 16:35:56 +01:00
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;; we use alternative GP load approach.
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2009-08-21 08:01:23 +02:00
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2001-06-11 18:27:26 +02:00
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(define_expand "exception_receiver"
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2001-07-15 08:25:01 +02:00
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[(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
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2001-07-15 09:17:29 +02:00
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"TARGET_ABI_OSF"
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2001-06-11 18:27:26 +02:00
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{
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Remove obsolete Tru64 UNIX V5.1B support
libstdc++-v3:
* configure.host: Remove osf* handling.
* config/os/osf: Remove.
* doc/xml/manual/using.xml: Remove OSF reference.
* testsuite/18_support/pthread_guard.cc: Remove alpha*-*-osf*
handling.
* testsuite/20_util/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* testsuite/20_util/shared_ptr/thread/mutex_weaktoshared.cc:
Likewise.
* testsuite/21_strings/basic_string/pthread18185.cc: Likewise.
* testsuite/21_strings/basic_string/pthread4.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-1.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-2.cc: Likewise.
* testsuite/23_containers/list/pthread1.cc: Likewise.
* testsuite/23_containers/list/pthread5.cc: Likewise.
* testsuite/23_containers/map/pthread6.cc: Likewise.
* testsuite/23_containers/vector/debug/multithreaded_swap.cc:
Likewise.
* testsuite/27_io/basic_ofstream/pthread2.cc: Likewise.
* testsuite/27_io/basic_ostringstream/pthread3.cc: Likewise.
* testsuite/30_threads/async/42819.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/any.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/async.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/launch.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/sync.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/39909.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/call_once1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/50862.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/45133.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/share.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/valid.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock_guard/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/swap.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/7.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/8.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/9.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/moveable.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/hardware_concurrency.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/thread/swap/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/2.cc:
Likewise.
* libstdc++-v3/testsuite/ext/rope/pthread7-rope.cc: Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/mutex_weaktoshared.cc: Likewise.
libobjc:
* configure.ac (enable_objc_gc): Remove alpha*-dec-osf* handling.
* configure: Regenerate.
* thr.c (_XOPEN_SOURCE): Define unconditionally.
libjava:
* configure.ac (alpha*-dec-osf*): Remove.
* configure: Regenerate.
* configure.host (alpha*-dec-osf*): Remove.
* gnu/java/net/natPlainDatagramSocketImplPosix.cc (setOption): Use
IPV6_MULTICAST_IF unconditionally.
* gnu/java/net/natPlainDatagramSocketImplWin32.cc (setOption):
Likewise.
* gnu/java/net/natPlainSocketImplPosix.cc
(gnu::java::net::PlainSocketImpl::accept): Use ::accept instead of
_Jv_accept.
* include/posix-signal.h [__alpha__ && __osf__]: Remove.
* include/posix.h (_POSIX_PII_SOCKET): Don't define.
(_Jv_accept): Remove.
* java/io/File.java (File._access): Rename to access.
Change callers.
(File._stat): Likewise.
* java/io/File.h: Regenerate.
* classpath/lib/java/io/File.class: Regenerate.
* java/io/natFilePosix.cc (java::io::File::_access): Rename to
access.
(java::io::File::_stat): Rename to stat.
* java/io/natFileWin32.cc: Likewise.
* testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation):
Remove alpha*-dec-osf* handling.
* testsuite/libjava.jvmti/jvmti-interp.exp
(gcj_jni_compile_c_to_so): Likewise.
* testsuite/libjava.jvmti/jvmti.exp (gcj_jvmti_compile_cxx_to_o):
Likewise.
libitm:
* configure.tgt (*-*-osf*): Remove.
* configure: Regenerate.
libgomp:
* configure.tgt (alpha*-dec-osf*): Remove.
* config/osf/sem.h: Remove.
* config/posix/lock.c (_XOPEN_SOURCE): Define unconditionally.
libgfortran:
* configure.ac: Remove Tru64 reference.
* acinclude.m4 (LIBGFOR_GTHREAD_WEAK): Remove alpha*-dec-osf*
handling.
* configure: Regenerate.
* intrinsics/c99_functions.c [__osf__]: Remove.
libgcc:
* config.host: Remove alpha*-dec-osf5.1* handling.
* config/alpha/gthr-posix.c: Remove.
* config/alpha/libgcc-osf5.ver: Remove.
* config/alpha/osf5-unwind.h: Remove.
* config/alpha/t-osf-pthread: Remove.
* config/alpha/t-slibgcc-osf: Remove.
* config/t-crtfm (crtfastmath.o): Remove -frandom-seed.
* gthr-posix.h [!_REENTRANT && __osf__] (_REENTRANT): Don't define.
[__osf__ && _PTHREAD_USE_MANGLED_NAMES_]: Remove.
* mkmap-flat.awk: Remove osf_export handling.
gnattools:
* configure.ac: Remove alpha*-dec-osf* handling.
* configure: Regenerate.
gcc/testsuite:
* g++.dg/abi/rtti3.C: Remove alpha*-dec-osf* handling.
* g++.dg/abi/thunk4.C: Likewise.
* g++.dg/cdce3.C: Don't skip on*-dec-osf5*.
Adapt line numbers.
* g++.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* g++.dg/cpp0x/constexpr-rom.C: Likewise.
* g++.dg/eh/spbp.C: Likewise.
* g++.dg/ext/label13.C: Likewise.
* g++.dg/guality/guality.exp: Likewise.
* g++.dg/other/anon5.C: Likewise.
* g++.dg/other/pragma-ep-1.C: Remove.
* g++.dg/warn/miss-format-1.C: Remove alpha*-dec-osf* handling.
* g++.dg/warn/pr31246.C: Likewise.
* g++.dg/warn/weak1.C: Likewise.
* g++.old-deja/g++.eh/badalloc1.C: Likewise.
* g++.old-deja/g++.ext/attrib5.C: Likewise.
* gcc.c-torture/compile/limits-declparen.c: Likewise.
* gcc.c-torture/compile/limits-pointer.c: Likewise.
* gcc.c-torture/execute/20001229-1.c: Remove __osf__ handling.
* gcc.dg/attr-weakref-1.c: Remove alpha*-dec-osf* handling.
* gcc.dg/c99-stdint-6.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/c99-tgmath-1.c: Likewise.
* gcc.dg/c99-tgmath-2.c: Likewise.
* gcc.dg/c99-tgmath-3.c: Likewise.
* gcc.dg/c99-tgmath-4.c: Likewise.
* gcc.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* gcc.dg/debug/pr49032.c: Likewise.
* gcc.dg/guality/guality.exp: Likewise.
* gcc.dg/intmax_t-1.c: Likewise.
* gcc.dg/pr48616.c: Likewise.
* gcc.dg/pragma-ep-1.c: Remove.
* gcc.dg/pragma-ep-2.c: Remove.
* gcc.dg/pragma-ep-3.c: Remove.
* gcc.dg/torture/pr47917.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/tree-ssa/pr42585.c: Remove alpha*-dec-osf* handling.
* gcc.misc-tests/gcov-14.c: Likewise.
* gfortran.dg/guality/guality.exp: Likewise.
* lib/target-supports.exp (check_weak_available): Likewise.
(add_options_for_tls): Likewise.
(check_ascii_locale_available): Likewise.
* obj-c++.dg/dwarf-2.mm: Likewise.
* objc.dg/dwarf-1.m: Likewise.
* objc.dg/dwarf-2.m: Likewise.
gcc/c-family:
* c-cppbuiltin.c (c_cpp_builtins): Remove #pragma extern_prefix
handling.
* c-pragma.c (handle_pragma_extern_prefix): Remove.
(init_pragma): Don't register extern_prefix.
gcc/po:
* EXCLUDES (mips-tdump.c, mips-tfile.c): Remove.
gcc:
* config.gcc (alpha*-dec-osf5.1*): Remove.
* config.host (alpha*-dec-osf*): Remove.
* configure.ac (*-*-osf*): Remove.
(alpha*-dec-osf*): Remove.
* configure: Regenerate.
* config/alpha/host-osf.c, config/alpha/osf5.h,
config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf:
Remove.
* config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove.
* config/alpha/alpha.c (struct machine_function): Update comment.
(alpha_start_function): Remove Tru64 UNIX as handling for
max_frame_size.
* config/alpha/alpha.md ("exception_receiver"): Remove
TARGET_LD_BUGGY_LDGP.
("*exception_receiver_2"): Likewise.
* except.c (finish_eh_generation): Remove Tru64 reference.
* ginclude/stdarg.h [_HIDDEN_VA_LIST]: Don't undef _VA_LIST.
* system.h (TARGET_HANDLE_PRAGMA_EXTERN_PREFIX): Poison.
* target.def (handle_pragma_extern_prefix): Remove.
* Makefile.in (mips-tfile.o-warn): Remove.
(ALL_HOST_BACKEND_OBJS): Remove mips-tfile.o, mips-tdump.o.
(mips-tfile, mips-tfile.o, mips-tdump, mips-tdump.o): Remove.
* mips-tdump.c, mips-tfile.c: Remove.
* doc/extend.texi (Symbol-Renaming Pragmas): Remove #pragma
extern_prefix.
* doc/install.texi (Binaries): Remove Tru64 UNIX reference.
(Specific, alpha*-dec-osf5.1): Note removal.
* doc/tm.texi.in (Misc, TARGET_HANDLE_PRAGMA_EXTERN_PREFIX):
Remove.
* doc/tm.texi: Regenerate.
* doc/trouble.texi (Cross-Compiler Problems): Remove.
gcc/ada:
* gcc-interface/Makefile.in (alpha*-dec-osf*): Remove.
* a-intnam-tru64.ads, mlib-tgt-specific-tru64.adb,
s-mastop-tru64.adb, s-osinte-tru64.adb, s-osinte-tru64.ads,
s-taprop-tru64.adb, s-tasinf-tru64.ads, s-taspri-tru64.ads,
system-tru64.ads: Remove.
* adaint.c (__gnat_number_of_cpus) [__alpha__ && __osf__]:
Remove.
[IS_CROSS] [!(__alpha__ && __osf__)]: Remove.
* env.c [__alpha__ && __osf__]: Remove.
* gsocket.h (_OSF_SOURCE): Remove.
(HAVE_THREAD_SAFE_GETxxxBYyyy) [__osf__]: Remove.
* init.c [__alpha__ && __osf__]: Remove.
* link.c [__osf__]: Remove.
* s-oscons-tmplt.c [__alpha__ && __osf__]: Remove.
[__osf__ && !_SS_MAXSIZE]: Remove.
* sysdep.c [__osf__]: Remove.
* terminals.c [__alpha__ && __osf__]: Remove.
[OSF1]: Remove.
* g-traceb.ads: Remove Tru64 reference.
* g-trasym.ads: Likewise.
* gnat_ugn.texi (Linking a Mixed C++ & Ada Program): Likewise.
(Summary of Run-Time Configurations): Likewise.
* memtrack.adb: Likewise.
fixincludes:
* inclhack.def (alpha___extern_prefix): Remove.
(alpha___extern_prefix_standards): Remove.
(alpha___extern_prefix_sys_stat): Remove.
(alpha_bad_lval): Remove.
(alpha_pthread): Remove.
(alpha_pthread_gcc): Remove.
(alpha_pthread_init): Remove.
* fixincl.x: Regenerate.
* tests/base/pthread.h [ALPHA_PTHREAD_CHECK]: Remove.
[ALPHA_PTHREAD_GCC_CHECK]: Remove.
[ALPHA_PTHREAD_INIT_CHECK]: Remove.
* tests/base/standards.h: Remove.
* tests/base/sys/stat.h [ALPHA___EXTERN_PREFIX_SYS_STAT_CHECK]:
Remove.
* tests/base/testing.h [ALPHA___EXTERN_PREFIX_CHECK]: Remove.
[ALPHA_BAD_LVAL_CHECK]: Remove.
contrib:
* config-list.mk (LIST): Remove alpha-dec-osf5.1.
config:
* weakref.m4 (GCC_CHECK_ELF_STYLE_WEAKREF): Remove
alpha*-dec-osf*.
toplevel:
* MAINTAINERS (OS Port Maintainers): Remove osf.
* configure.ac (enable_libgomp): Remove *-*-osf*.
(with_stabs): Remove alpha*-*-osf*.
* configure: Regenerate.
From-SVN: r185240
2012-03-12 16:35:56 +01:00
|
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|
|
if (flag_reorder_blocks_and_partition)
|
2016-12-02 17:53:23 +01:00
|
|
|
|
operands[0] = copy_rtx (alpha_gp_save_rtx ());
|
2001-06-11 18:27:26 +02:00
|
|
|
|
else
|
|
|
|
|
operands[0] = const0_rtx;
|
2001-07-15 17:38:52 +02:00
|
|
|
|
})
|
2001-06-11 18:27:26 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "*exception_receiver_2"
|
2002-03-26 23:07:47 +01:00
|
|
|
|
[(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
|
Remove obsolete Tru64 UNIX V5.1B support
libstdc++-v3:
* configure.host: Remove osf* handling.
* config/os/osf: Remove.
* doc/xml/manual/using.xml: Remove OSF reference.
* testsuite/18_support/pthread_guard.cc: Remove alpha*-*-osf*
handling.
* testsuite/20_util/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* testsuite/20_util/shared_ptr/thread/mutex_weaktoshared.cc:
Likewise.
* testsuite/21_strings/basic_string/pthread18185.cc: Likewise.
* testsuite/21_strings/basic_string/pthread4.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-1.cc: Likewise.
* testsuite/22_locale/locale/cons/12658_thread-2.cc: Likewise.
* testsuite/23_containers/list/pthread1.cc: Likewise.
* testsuite/23_containers/list/pthread5.cc: Likewise.
* testsuite/23_containers/map/pthread6.cc: Likewise.
* testsuite/23_containers/vector/debug/multithreaded_swap.cc:
Likewise.
* testsuite/27_io/basic_ofstream/pthread2.cc: Likewise.
* testsuite/27_io/basic_ostringstream/pthread3.cc: Likewise.
* testsuite/30_threads/async/42819.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/any.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/async.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/launch.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/async/sync.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/39909.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/call_once/call_once1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/50862.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/condition_variable_any/members/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/45133.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/get2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/share.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/valid.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/lock_guard/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/promise/members/swap.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/cons/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/unlock/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/this_thread/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/49668.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/7.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/8.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/9.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/cons/moveable.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/thread/members/hardware_concurrency.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/thread/swap/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/dest/destructor_locked.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/native_handle/typesizes.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/timed_mutex/unlock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/try_lock/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/5.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/cons/6.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/1.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/2.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/3.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/locking/4.cc: Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/1.cc:
Likewise.
* libstdc++-v3/testsuite/30_threads/unique_lock/modifiers/2.cc:
Likewise.
* libstdc++-v3/testsuite/ext/rope/pthread7-rope.cc: Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/default_weaktoshared.cc:
Likewise.
* libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/thread/mutex_weaktoshared.cc: Likewise.
libobjc:
* configure.ac (enable_objc_gc): Remove alpha*-dec-osf* handling.
* configure: Regenerate.
* thr.c (_XOPEN_SOURCE): Define unconditionally.
libjava:
* configure.ac (alpha*-dec-osf*): Remove.
* configure: Regenerate.
* configure.host (alpha*-dec-osf*): Remove.
* gnu/java/net/natPlainDatagramSocketImplPosix.cc (setOption): Use
IPV6_MULTICAST_IF unconditionally.
* gnu/java/net/natPlainDatagramSocketImplWin32.cc (setOption):
Likewise.
* gnu/java/net/natPlainSocketImplPosix.cc
(gnu::java::net::PlainSocketImpl::accept): Use ::accept instead of
_Jv_accept.
* include/posix-signal.h [__alpha__ && __osf__]: Remove.
* include/posix.h (_POSIX_PII_SOCKET): Don't define.
(_Jv_accept): Remove.
* java/io/File.java (File._access): Rename to access.
Change callers.
(File._stat): Likewise.
* java/io/File.h: Regenerate.
* classpath/lib/java/io/File.class: Regenerate.
* java/io/natFilePosix.cc (java::io::File::_access): Rename to
access.
(java::io::File::_stat): Rename to stat.
* java/io/natFileWin32.cc: Likewise.
* testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation):
Remove alpha*-dec-osf* handling.
* testsuite/libjava.jvmti/jvmti-interp.exp
(gcj_jni_compile_c_to_so): Likewise.
* testsuite/libjava.jvmti/jvmti.exp (gcj_jvmti_compile_cxx_to_o):
Likewise.
libitm:
* configure.tgt (*-*-osf*): Remove.
* configure: Regenerate.
libgomp:
* configure.tgt (alpha*-dec-osf*): Remove.
* config/osf/sem.h: Remove.
* config/posix/lock.c (_XOPEN_SOURCE): Define unconditionally.
libgfortran:
* configure.ac: Remove Tru64 reference.
* acinclude.m4 (LIBGFOR_GTHREAD_WEAK): Remove alpha*-dec-osf*
handling.
* configure: Regenerate.
* intrinsics/c99_functions.c [__osf__]: Remove.
libgcc:
* config.host: Remove alpha*-dec-osf5.1* handling.
* config/alpha/gthr-posix.c: Remove.
* config/alpha/libgcc-osf5.ver: Remove.
* config/alpha/osf5-unwind.h: Remove.
* config/alpha/t-osf-pthread: Remove.
* config/alpha/t-slibgcc-osf: Remove.
* config/t-crtfm (crtfastmath.o): Remove -frandom-seed.
* gthr-posix.h [!_REENTRANT && __osf__] (_REENTRANT): Don't define.
[__osf__ && _PTHREAD_USE_MANGLED_NAMES_]: Remove.
* mkmap-flat.awk: Remove osf_export handling.
gnattools:
* configure.ac: Remove alpha*-dec-osf* handling.
* configure: Regenerate.
gcc/testsuite:
* g++.dg/abi/rtti3.C: Remove alpha*-dec-osf* handling.
* g++.dg/abi/thunk4.C: Likewise.
* g++.dg/cdce3.C: Don't skip on*-dec-osf5*.
Adapt line numbers.
* g++.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* g++.dg/cpp0x/constexpr-rom.C: Likewise.
* g++.dg/eh/spbp.C: Likewise.
* g++.dg/ext/label13.C: Likewise.
* g++.dg/guality/guality.exp: Likewise.
* g++.dg/other/anon5.C: Likewise.
* g++.dg/other/pragma-ep-1.C: Remove.
* g++.dg/warn/miss-format-1.C: Remove alpha*-dec-osf* handling.
* g++.dg/warn/pr31246.C: Likewise.
* g++.dg/warn/weak1.C: Likewise.
* g++.old-deja/g++.eh/badalloc1.C: Likewise.
* g++.old-deja/g++.ext/attrib5.C: Likewise.
* gcc.c-torture/compile/limits-declparen.c: Likewise.
* gcc.c-torture/compile/limits-pointer.c: Likewise.
* gcc.c-torture/execute/20001229-1.c: Remove __osf__ handling.
* gcc.dg/attr-weakref-1.c: Remove alpha*-dec-osf* handling.
* gcc.dg/c99-stdint-6.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/c99-tgmath-1.c: Likewise.
* gcc.dg/c99-tgmath-2.c: Likewise.
* gcc.dg/c99-tgmath-3.c: Likewise.
* gcc.dg/c99-tgmath-4.c: Likewise.
* gcc.dg/compat/struct-layout-1_generate.c: Remove alpha*-dec-osf*
handling.
* gcc.dg/debug/pr49032.c: Likewise.
* gcc.dg/guality/guality.exp: Likewise.
* gcc.dg/intmax_t-1.c: Likewise.
* gcc.dg/pr48616.c: Likewise.
* gcc.dg/pragma-ep-1.c: Remove.
* gcc.dg/pragma-ep-2.c: Remove.
* gcc.dg/pragma-ep-3.c: Remove.
* gcc.dg/torture/pr47917.c: Remove alpha*-dec-osf5* handling.
* gcc.dg/tree-ssa/pr42585.c: Remove alpha*-dec-osf* handling.
* gcc.misc-tests/gcov-14.c: Likewise.
* gfortran.dg/guality/guality.exp: Likewise.
* lib/target-supports.exp (check_weak_available): Likewise.
(add_options_for_tls): Likewise.
(check_ascii_locale_available): Likewise.
* obj-c++.dg/dwarf-2.mm: Likewise.
* objc.dg/dwarf-1.m: Likewise.
* objc.dg/dwarf-2.m: Likewise.
gcc/c-family:
* c-cppbuiltin.c (c_cpp_builtins): Remove #pragma extern_prefix
handling.
* c-pragma.c (handle_pragma_extern_prefix): Remove.
(init_pragma): Don't register extern_prefix.
gcc/po:
* EXCLUDES (mips-tdump.c, mips-tfile.c): Remove.
gcc:
* config.gcc (alpha*-dec-osf5.1*): Remove.
* config.host (alpha*-dec-osf*): Remove.
* configure.ac (*-*-osf*): Remove.
(alpha*-dec-osf*): Remove.
* configure: Regenerate.
* config/alpha/host-osf.c, config/alpha/osf5.h,
config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf:
Remove.
* config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove.
* config/alpha/alpha.c (struct machine_function): Update comment.
(alpha_start_function): Remove Tru64 UNIX as handling for
max_frame_size.
* config/alpha/alpha.md ("exception_receiver"): Remove
TARGET_LD_BUGGY_LDGP.
("*exception_receiver_2"): Likewise.
* except.c (finish_eh_generation): Remove Tru64 reference.
* ginclude/stdarg.h [_HIDDEN_VA_LIST]: Don't undef _VA_LIST.
* system.h (TARGET_HANDLE_PRAGMA_EXTERN_PREFIX): Poison.
* target.def (handle_pragma_extern_prefix): Remove.
* Makefile.in (mips-tfile.o-warn): Remove.
(ALL_HOST_BACKEND_OBJS): Remove mips-tfile.o, mips-tdump.o.
(mips-tfile, mips-tfile.o, mips-tdump, mips-tdump.o): Remove.
* mips-tdump.c, mips-tfile.c: Remove.
* doc/extend.texi (Symbol-Renaming Pragmas): Remove #pragma
extern_prefix.
* doc/install.texi (Binaries): Remove Tru64 UNIX reference.
(Specific, alpha*-dec-osf5.1): Note removal.
* doc/tm.texi.in (Misc, TARGET_HANDLE_PRAGMA_EXTERN_PREFIX):
Remove.
* doc/tm.texi: Regenerate.
* doc/trouble.texi (Cross-Compiler Problems): Remove.
gcc/ada:
* gcc-interface/Makefile.in (alpha*-dec-osf*): Remove.
* a-intnam-tru64.ads, mlib-tgt-specific-tru64.adb,
s-mastop-tru64.adb, s-osinte-tru64.adb, s-osinte-tru64.ads,
s-taprop-tru64.adb, s-tasinf-tru64.ads, s-taspri-tru64.ads,
system-tru64.ads: Remove.
* adaint.c (__gnat_number_of_cpus) [__alpha__ && __osf__]:
Remove.
[IS_CROSS] [!(__alpha__ && __osf__)]: Remove.
* env.c [__alpha__ && __osf__]: Remove.
* gsocket.h (_OSF_SOURCE): Remove.
(HAVE_THREAD_SAFE_GETxxxBYyyy) [__osf__]: Remove.
* init.c [__alpha__ && __osf__]: Remove.
* link.c [__osf__]: Remove.
* s-oscons-tmplt.c [__alpha__ && __osf__]: Remove.
[__osf__ && !_SS_MAXSIZE]: Remove.
* sysdep.c [__osf__]: Remove.
* terminals.c [__alpha__ && __osf__]: Remove.
[OSF1]: Remove.
* g-traceb.ads: Remove Tru64 reference.
* g-trasym.ads: Likewise.
* gnat_ugn.texi (Linking a Mixed C++ & Ada Program): Likewise.
(Summary of Run-Time Configurations): Likewise.
* memtrack.adb: Likewise.
fixincludes:
* inclhack.def (alpha___extern_prefix): Remove.
(alpha___extern_prefix_standards): Remove.
(alpha___extern_prefix_sys_stat): Remove.
(alpha_bad_lval): Remove.
(alpha_pthread): Remove.
(alpha_pthread_gcc): Remove.
(alpha_pthread_init): Remove.
* fixincl.x: Regenerate.
* tests/base/pthread.h [ALPHA_PTHREAD_CHECK]: Remove.
[ALPHA_PTHREAD_GCC_CHECK]: Remove.
[ALPHA_PTHREAD_INIT_CHECK]: Remove.
* tests/base/standards.h: Remove.
* tests/base/sys/stat.h [ALPHA___EXTERN_PREFIX_SYS_STAT_CHECK]:
Remove.
* tests/base/testing.h [ALPHA___EXTERN_PREFIX_CHECK]: Remove.
[ALPHA_BAD_LVAL_CHECK]: Remove.
contrib:
* config-list.mk (LIST): Remove alpha-dec-osf5.1.
config:
* weakref.m4 (GCC_CHECK_ELF_STYLE_WEAKREF): Remove
alpha*-dec-osf*.
toplevel:
* MAINTAINERS (OS Port Maintainers): Remove osf.
* configure.ac (enable_libgomp): Remove *-*-osf*.
(with_stabs): Remove alpha*-*-osf*.
* configure: Regenerate.
From-SVN: r185240
2012-03-12 16:35:56 +01:00
|
|
|
|
"TARGET_ABI_OSF && flag_reorder_blocks_and_partition"
|
2002-03-26 23:07:47 +01:00
|
|
|
|
"ldq $29,%0"
|
|
|
|
|
[(set_attr "type" "ild")])
|
2001-06-11 18:27:26 +02:00
|
|
|
|
|
2004-12-05 20:52:24 +01:00
|
|
|
|
(define_insn_and_split "*exception_receiver_1"
|
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
|
|
|
|
|
"TARGET_ABI_OSF"
|
|
|
|
|
{
|
|
|
|
|
if (TARGET_EXPLICIT_RELOCS)
|
2016-05-18 21:15:22 +02:00
|
|
|
|
return "#";
|
2004-12-05 20:52:24 +01:00
|
|
|
|
else
|
|
|
|
|
return "ldgp $29,0($26)";
|
|
|
|
|
}
|
|
|
|
|
"&& TARGET_EXPLICIT_RELOCS && reload_completed"
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
|
|
|
|
|
{
|
|
|
|
|
operands[0] = pic_offset_table_rtx;
|
|
|
|
|
operands[1] = gen_rtx_REG (Pmode, 26);
|
|
|
|
|
operands[2] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "length" "8")
|
|
|
|
|
(set_attr "type" "multi")])
|
|
|
|
|
|
1998-02-02 20:28:57 +01:00
|
|
|
|
(define_expand "nonlocal_goto_receiver"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(set (reg:DI 27) (mem:DI (reg:DI 29)))
|
2001-07-15 08:25:01 +02:00
|
|
|
|
(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(use (reg:DI 27))]
|
2012-10-14 14:50:45 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS")
|
1996-11-16 12:07:51 +01:00
|
|
|
|
|
|
|
|
|
(define_insn "arg_home"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec [(const_int 0)] UNSPEC_ARG_HOME)
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(use (reg:DI 1))
|
|
|
|
|
(use (reg:DI 25))
|
1997-01-20 03:31:13 +01:00
|
|
|
|
(use (reg:DI 16))
|
|
|
|
|
(use (reg:DI 17))
|
|
|
|
|
(use (reg:DI 18))
|
|
|
|
|
(use (reg:DI 19))
|
|
|
|
|
(use (reg:DI 20))
|
|
|
|
|
(use (reg:DI 21))
|
|
|
|
|
(use (reg:DI 48))
|
|
|
|
|
(use (reg:DI 49))
|
|
|
|
|
(use (reg:DI 50))
|
|
|
|
|
(use (reg:DI 51))
|
|
|
|
|
(use (reg:DI 52))
|
|
|
|
|
(use (reg:DI 53))
|
|
|
|
|
(clobber (mem:BLK (const_int 0)))
|
1996-11-16 12:07:51 +01:00
|
|
|
|
(clobber (reg:DI 24))
|
|
|
|
|
(clobber (reg:DI 25))
|
|
|
|
|
(clobber (reg:DI 0))]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
1998-06-16 19:08:48 +02:00
|
|
|
|
"lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
|
1998-08-26 20:48:21 +02:00
|
|
|
|
[(set_attr "length" "16")
|
|
|
|
|
(set_attr "type" "multi")])
|
1997-10-16 03:23:23 +02:00
|
|
|
|
|
2001-12-12 07:40:27 +01:00
|
|
|
|
;; Prefetch data.
|
|
|
|
|
;;
|
|
|
|
|
;; On EV4, these instructions are nops -- no load occurs.
|
|
|
|
|
;;
|
|
|
|
|
;; On EV5, these instructions act as a normal load, and thus can trap
|
|
|
|
|
;; if the address is invalid. The OS may (or may not) handle this in
|
|
|
|
|
;; the entMM fault handler and suppress the fault. If so, then this
|
|
|
|
|
;; has the effect of a read prefetch instruction.
|
|
|
|
|
;;
|
|
|
|
|
;; On EV6, these become official prefetch instructions.
|
|
|
|
|
|
|
|
|
|
(define_insn "prefetch"
|
|
|
|
|
[(prefetch (match_operand:DI 0 "address_operand" "p")
|
|
|
|
|
(match_operand:DI 1 "const_int_operand" "n")
|
|
|
|
|
(match_operand:DI 2 "const_int_operand" "n"))]
|
alpha.opt: New file.
* config/alpha/alpha.opt: New file.
* config/alpha/alpha.c (alpha_tune): New. Rename all existing uses
of alpha_cpu.
(alpha_cpu_string, alpha_tune_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string): Make static.
(alpha_tls_size_string): Remove.
(alpha_handle_option): New.
(override_options): Update for alpha_cpu/alpha_tune split.
(alpha_file_start): Likewise.
(TARGET_DEFAULT_TARGET_FLAGS): New.
(TARGET_HANDLE_OPTION): New.
* config/alpha/alpha.h (alpha_tune): Declare.
(MASK_FP, MASK_FPREGS, TARGET_FPREGS, MASK_GAS, TARGET_GAS,
MASK_IEEE_CONFORMANT, TARGET_IEEE_CONFORMANT, MASK_IEEE, TARGET_IEEE,
MASK_IEEE_WITH_INEXACT, TARGET_IEEE_WITH_INEXACT, MASK_BUILD_CONSTANTS,
TARGET_BUILD_CONSTANTS, MASK_FLOAT_VAX, TARGET_FLOAT_VAX, MASK_BWX,
TARGET_BWX, MASK_MAX, TARGET_MAX, MASK_FIX, TARGET_FIX, MASK_CIX,
TARGET_CIX, MASK_EXPLICIT_RELOCS, TARGET_EXPLICIT_RELOCS,
MASK_SMALL_DATA, TARGET_SMALL_DATA, MASK_TLS_KERNEL, TARGET_TLS_KERNEL,
MASK_SMALL_TEXT, TARGET_SMALL_TEXT, MASK_LONG_DOUBLE_128,
TARGET_LONG_DOUBLE_128, MASK_CPU_EV5, TARGET_CPU_EV5, MASK_CPU_EV6,
TARGET_CPU_EV6, MASK_SUPPORT_ARCH): Remove.
(TARGET_SWITCHES, TARGET_OPTIONS): Remove.
(TARGET_DEFAULT): Remove MASK_FP.
(TARGET_FP): Redefined based on TARGET_SOFT_FP.
(TARGET_SUPPORT_ARCH): Default on if HAVE_AS_EXPLICIT_RELOCS.
(alpha_cpu_string, alpha_tune_string, alpha_fprm_string,
alpha_fptm_string, alpha_tp_string, alpha_mlat_string,
alpha_tls_size_string): Remove.
* config/alpha/alpha.md (prefetch): Use alpha_cpu.
(attribute tune): Rename from attribute cpu.
* config/alpha/ev4.md: Update to match.
* config/alpha/ev5.md, config/alpha/ev6.md: Likewise.
* config/alpha/freebsd.h (TARGET_DEFAULT): Remove MASK_FP.
* config/alpha/linux.h (TARGET_DEFAULT): Likewise.
* config/alpha/netbsd.h (TARGET_DEFAULT): Likewise.
* config/alpha/osf5.h (TARGET_DEFAULT): Likewise.
* config/alpha/vms.h (TARGET_DEFAULT): Likewise.
From-SVN: r96602
2005-03-17 11:43:19 +01:00
|
|
|
|
"TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
|
2001-12-12 07:40:27 +01:00
|
|
|
|
{
|
|
|
|
|
/* Interpret "no temporal locality" as this data should be evicted once
|
|
|
|
|
it is used. The "evict next" alternatives load the data into the cache
|
|
|
|
|
and leave the LRU eviction counter pointing to that block. */
|
|
|
|
|
static const char * const alt[2][2] = {
|
|
|
|
|
{
|
2002-10-14 21:57:18 +02:00
|
|
|
|
"ldq $31,%a0", /* read, evict next */
|
2001-12-12 07:40:27 +01:00
|
|
|
|
"ldl $31,%a0", /* read, evict last */
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"ldt $f31,%a0", /* write, evict next */
|
2002-10-14 21:57:18 +02:00
|
|
|
|
"lds $f31,%a0", /* write, evict last */
|
2001-12-12 07:40:27 +01:00
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bool write = INTVAL (operands[1]) != 0;
|
|
|
|
|
bool lru = INTVAL (operands[2]) != 0;
|
|
|
|
|
|
|
|
|
|
return alt[write][lru];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "ild")])
|
|
|
|
|
|
ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.3, ChangeLog.5, ChangeLog, alias.c,
cfgbuild.c, expmed.c, expr.c, final.c, flow.c, fold-const.c,
function.c, config/alpha/alpha.md, config/alpha/vms-ld.c,
config/arm/arm.c, config/arm/arm.h, config/c4x/libgcc.S,
config/i370/i370.c, config/i386/i386.c,
config/i386/i386-interix.h, config/i386/i386.md,
config/i386/i386.h, config/i386/netbsd-elf.h, config/ia64/ia64.c,
config/m32r/m32r-protos.h, config/mcore/mcore.h,
config/rs6000/rs6000.h, config/sparc/linux64.h,
config/sparc/sparc.c, config/v850/v850-protos.h,
config/cris/cris.h, config/s390/s390.md, config/elfos.h: Fix
spelling errors.
From-SVN: r47815
2001-12-09 21:13:19 +01:00
|
|
|
|
;; Close the trap shadow of preceding instructions. This is generated
|
1997-10-16 03:23:23 +02:00
|
|
|
|
;; by alpha_reorg.
|
|
|
|
|
|
|
|
|
|
(define_insn "trapb"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
|
1997-10-16 03:23:23 +02:00
|
|
|
|
""
|
|
|
|
|
"trapb"
|
|
|
|
|
[(set_attr "type" "misc")])
|
1998-08-26 20:48:21 +02:00
|
|
|
|
|
ChangeLog.2, [...]: Fix spelling errors.
* ChangeLog.2, ChangeLog.4, ChangeLog.5, ChangeLog,
FSFChangeLog.10, FSFChangeLog.11, alias.c, attribs.c,
caller-save.c, calls.c, cfg.c, cfganal.c, cfgcleanup.c, cfgrtl.c,
cppmacro.c, fold-const.c, ifcvt.c, local-alloc.c, profile.c,
sched-int.h, toplev.c, config/alpha/alpha.c,
config/alpha/alpha.md, config/c4x/c4x.h, config/cris/cris.h,
config/cris/cris.md, config/i370/i370.md, config/i386/i386.c,
config/i386/i386.h, config/i386/i386.md, config/i386/xm-djgpp.h,
config/ia64/ia64.c, config/m68hc11/m68hc11.c, config/m68k/m68k.md,
config/mcore/mcore.h, config/mmix/mmix.c, config/ns32k/ns32k.h,
config/ns32k/ns32k.md, config/rs6000/rs6000.c,
config/rs6000/sysv4.h, config/sh/sh.md: Fix spelling errors.
From-SVN: r46760
2001-11-04 03:51:28 +01:00
|
|
|
|
;; No-op instructions used by machine-dependent reorg to preserve
|
1998-08-26 20:48:21 +02:00
|
|
|
|
;; alignment for instruction issue.
|
2001-09-11 10:52:39 +02:00
|
|
|
|
;; The Unicos/Mk assembler does not support these opcodes.
|
1998-08-26 20:48:21 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "nop"
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
""
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"bis $31,$31,$31"
|
1998-08-26 20:48:21 +02:00
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "fnop"
|
|
|
|
|
[(const_int 1)]
|
|
|
|
|
"TARGET_FP"
|
2001-09-11 10:52:39 +02:00
|
|
|
|
"cpys $f31,$f31,$f31"
|
1998-08-26 20:48:21 +02:00
|
|
|
|
[(set_attr "type" "fcpys")])
|
|
|
|
|
|
|
|
|
|
(define_insn "unop"
|
|
|
|
|
[(const_int 2)]
|
|
|
|
|
""
|
2001-12-18 01:26:56 +01:00
|
|
|
|
"ldq_u $31,0($30)")
|
2001-09-11 10:52:39 +02:00
|
|
|
|
|
1998-08-26 20:48:21 +02:00
|
|
|
|
(define_insn "realign"
|
2001-07-15 08:25:01 +02:00
|
|
|
|
[(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
|
|
|
|
|
UNSPECV_REALIGN)]
|
1998-08-26 20:48:21 +02:00
|
|
|
|
""
|
2011-03-22 23:24:28 +01:00
|
|
|
|
".align %0 #realign")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
|
|
|
|
|
;; Instructions to be emitted from __builtins.
|
|
|
|
|
|
|
|
|
|
(define_insn "builtin_cmpbge"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rI")]
|
|
|
|
|
UNSPEC_CMPBGE))]
|
|
|
|
|
""
|
|
|
|
|
"cmpbge %r1,%2,%0"
|
|
|
|
|
;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
|
|
|
|
|
;; actually differentiate between ILOG and ICMP in the schedule.
|
|
|
|
|
[(set_attr "type" "icmp")])
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "extbl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "extwl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2]));
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "extll"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "extql"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2]));
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
1999-10-01 02:45:07 +02:00
|
|
|
|
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
(define_expand "builtin_insbl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[1] = gen_lowpart (QImode, operands[1]);
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_insbl (operands[0], operands[1], operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_inswl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[1] = gen_lowpart (HImode, operands[1]);
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_inswl (operands[0], operands[1], operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_insll"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_insll (operands[0], operands[1], operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "inswh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "inslh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "insqh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskbl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
rtx mask = GEN_INT (0xff);
|
|
|
|
|
emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskwl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
rtx mask = GEN_INT (0xffff);
|
|
|
|
|
emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskll"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2015-05-11 09:21:19 +02:00
|
|
|
|
rtx mask = gen_int_mode (0xffffffff, DImode);
|
2011-03-25 01:52:34 +01:00
|
|
|
|
emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskql"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-03-25 01:52:34 +01:00
|
|
|
|
rtx mask = constm1_rtx;
|
|
|
|
|
emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskwh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "msklh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2011-03-25 01:52:34 +01:00
|
|
|
|
(define_expand "mskqh"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "register_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand")]
|
alpha.c (mode_mask_operand): Simplify without ifdefs.
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
2002-06-05 00:46:00 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(define_expand "builtin_zap"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(and:DI (unspec:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 2 "reg_or_cint_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
UNSPEC_ZAP)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "reg_or_cint_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (CONST_INT_P (operands[2]))
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
|
|
|
|
|
|
2002-06-10 23:04:29 +02:00
|
|
|
|
if (mask == const0_rtx)
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], const0_rtx);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
2002-06-10 23:04:29 +02:00
|
|
|
|
if (mask == constm1_rtx)
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
operands[1] = force_reg (DImode, operands[1]);
|
|
|
|
|
emit_insn (gen_anddi3 (operands[0], operands[1], mask));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
operands[1] = force_reg (DImode, operands[1]);
|
|
|
|
|
operands[2] = gen_lowpart (QImode, operands[2]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*builtin_zap_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
|
|
|
|
|
(and:DI (unspec:DI
|
Makefile.in (insn-preds.o): Depend on TREE_H.
* Makefile.in (insn-preds.o): Depend on TREE_H.
* genpreds.c (write_insn_preds_c): Include tree.h.
* config/alpha/alpha.c (reg_or_0_operand, reg_or_6bit_operand,
reg_or_8bit_operand, cint8_operand, add_operand, sext_add_operand,
const48_operand, and_operand, or_operand, mode_width_operand,
mode_mask_operand, mul8_operand, const0_operand,
hard_fp_register_operand, hard_int_register_operand,
reg_or_cint_operand, some_operand, some_ni_operand, input_operand,
samegp_function_operand, direct_call_operand, small_symbolic_operand,
global_symbolic_operand, call_operand, symbolic_operand,
dtp16_symbolic_operand, dtp32_symbolic_operand,
gotdtp_symbolic_operand, tp16_symbolic_operand, tp32_symbolic_operand,
gottp_symbolic_operand, alpha_comparison_operator,
alpha_zero_comparison_operator, alpha_swapped_comparison_operator,
signed_comparison_operator, alpha_fp_comparison_operator,
divmod_operator, fix_operator, aligned_memory_operand,
unaligned_memory_operand, reg_or_unaligned_mem_operand,
any_memory_operand, reg_not_elim_operand, normal_memory_operand,
reg_no_subreg_operand, addition_operation): Move to predicates.md.
(reg_or_const_int_operand): Remove. Replace all users with
reg_or_cint_operand.
(tls_symbolic_operand_1): Export. Don't check mode or for CONST.
(resolve_reload_operand): Split out of aligned_memory_operand.
* config/alpha/alpha-protos.h: Update for exports.
* config/alpha/alpha.h (PREDICATE_CODES): Remove.
* config/alpha/alpha.md: Include predicates.md.
* config/alpha/predicates.md: New file.
From-SVN: r85953
2004-08-13 21:11:35 +02:00
|
|
|
|
[(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
UNSPEC_ZAP)
|
Makefile.in (insn-preds.o): Depend on TREE_H.
* Makefile.in (insn-preds.o): Depend on TREE_H.
* genpreds.c (write_insn_preds_c): Include tree.h.
* config/alpha/alpha.c (reg_or_0_operand, reg_or_6bit_operand,
reg_or_8bit_operand, cint8_operand, add_operand, sext_add_operand,
const48_operand, and_operand, or_operand, mode_width_operand,
mode_mask_operand, mul8_operand, const0_operand,
hard_fp_register_operand, hard_int_register_operand,
reg_or_cint_operand, some_operand, some_ni_operand, input_operand,
samegp_function_operand, direct_call_operand, small_symbolic_operand,
global_symbolic_operand, call_operand, symbolic_operand,
dtp16_symbolic_operand, dtp32_symbolic_operand,
gotdtp_symbolic_operand, tp16_symbolic_operand, tp32_symbolic_operand,
gottp_symbolic_operand, alpha_comparison_operator,
alpha_zero_comparison_operator, alpha_swapped_comparison_operator,
signed_comparison_operator, alpha_fp_comparison_operator,
divmod_operator, fix_operator, aligned_memory_operand,
unaligned_memory_operand, reg_or_unaligned_mem_operand,
any_memory_operand, reg_not_elim_operand, normal_memory_operand,
reg_no_subreg_operand, addition_operation): Move to predicates.md.
(reg_or_const_int_operand): Remove. Replace all users with
reg_or_cint_operand.
(tls_symbolic_operand_1): Export. Don't check mode or for CONST.
(resolve_reload_operand): Split out of aligned_memory_operand.
* config/alpha/alpha-protos.h: Update for exports.
* config/alpha/alpha.h (PREDICATE_CODES): Remove.
* config/alpha/alpha.md: Include predicates.md.
* config/alpha/predicates.md: New file.
From-SVN: r85953
2004-08-13 21:11:35 +02:00
|
|
|
|
(match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
#
|
|
|
|
|
#
|
|
|
|
|
bis $31,$31,%0
|
|
|
|
|
zap %r1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift,shift,ilog,shift")])
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(and:DI (unspec:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:QI 2 "const_int_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
UNSPEC_ZAP)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "const_int_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
{
|
|
|
|
|
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
|
2015-05-11 09:21:19 +02:00
|
|
|
|
|
|
|
|
|
operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_split
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(and:DI (unspec:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:QI 2 "const_int_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
UNSPEC_ZAP)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "register_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
[(set (match_dup 0)
|
|
|
|
|
(and:DI (match_dup 1) (match_dup 2)))]
|
|
|
|
|
{
|
|
|
|
|
operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
|
|
|
|
|
if (operands[2] == const0_rtx)
|
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], const0_rtx);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
if (operands[2] == constm1_rtx)
|
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_zapnot"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(and:DI (unspec:DI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(not:QI (match_operand:DI 2 "reg_or_cint_operand"))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
UNSPEC_ZAP)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:DI 1 "reg_or_cint_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-04-22 10:19:54 +02:00
|
|
|
|
if (CONST_INT_P (operands[2]))
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
|
|
|
|
|
|
2002-06-10 23:04:29 +02:00
|
|
|
|
if (mask == const0_rtx)
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], const0_rtx);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
2002-06-10 23:04:29 +02:00
|
|
|
|
if (mask == constm1_rtx)
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
{
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
operands[1] = force_reg (DImode, operands[1]);
|
|
|
|
|
emit_insn (gen_anddi3 (operands[0], operands[1], mask));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
operands[1] = force_reg (DImode, operands[1]);
|
|
|
|
|
operands[2] = gen_lowpart (QImode, operands[2]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*builtin_zapnot_1"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(and:DI (unspec:DI
|
|
|
|
|
[(not:QI (match_operand:QI 2 "register_operand" "r"))]
|
|
|
|
|
UNSPEC_ZAP)
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
|
|
|
|
|
""
|
|
|
|
|
"zapnot %r1,%2,%0"
|
|
|
|
|
[(set_attr "type" "shift")])
|
|
|
|
|
|
|
|
|
|
(define_insn "builtin_amask"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
|
|
|
|
|
UNSPEC_AMASK))]
|
|
|
|
|
""
|
|
|
|
|
"amask %1,%0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "builtin_implver"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
|
|
|
|
|
""
|
|
|
|
|
"implver %0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_insn "builtin_rpcc"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
|
|
|
|
|
""
|
|
|
|
|
"rpcc %0"
|
|
|
|
|
[(set_attr "type" "ilog")])
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_minub8"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_minsb8"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_minuw4"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_minsw4"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_maxub8"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_maxsb8"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_maxuw4"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_maxsw4"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(match_operand:DI 0 "register_operand")
|
|
|
|
|
(match_operand:DI 1 "reg_or_0_operand")
|
|
|
|
|
(match_operand:DI 2 "reg_or_0_operand")]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
|
|
|
|
|
operands[1], operands[2]);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "builtin_perr"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
|
|
(unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
|
|
|
|
|
(match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
|
|
|
|
|
UNSPEC_PERR))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
"perr %r1,%r2,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_pklb"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(vec_concat:V8QI
|
|
|
|
|
(vec_concat:V4QI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(truncate:V2QI (match_operand:DI 1 "register_operand"))
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(match_dup 2))
|
|
|
|
|
(match_dup 3)))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (V8QImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (V2SImode, operands[1]);
|
|
|
|
|
operands[2] = CONST0_RTX (V2QImode);
|
|
|
|
|
operands[3] = CONST0_RTX (V4QImode);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*pklb"
|
|
|
|
|
[(set (match_operand:V8QI 0 "register_operand" "=r")
|
|
|
|
|
(vec_concat:V8QI
|
|
|
|
|
(vec_concat:V4QI
|
|
|
|
|
(truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:V2QI 2 "const0_operand"))
|
|
|
|
|
(match_operand:V4QI 3 "const0_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
"pklb %r1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_pkwb"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(vec_concat:V8QI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(truncate:V4QI (match_operand:DI 1 "register_operand"))
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(match_dup 2)))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (V8QImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (V4HImode, operands[1]);
|
|
|
|
|
operands[2] = CONST0_RTX (V4QImode);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*pkwb"
|
2002-10-14 21:57:18 +02:00
|
|
|
|
[(set (match_operand:V8QI 0 "register_operand" "=r")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(vec_concat:V8QI
|
2002-10-14 21:57:18 +02:00
|
|
|
|
(truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand:V4QI 2 "const0_operand")))]
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
"pkwb %r1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_unpkbl"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(zero_extend:V2SI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(vec_select:V2QI (match_operand:DI 1 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(parallel [(const_int 0) (const_int 1)]))))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (V2SImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (V8QImode, operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*unpkbl"
|
|
|
|
|
[(set (match_operand:V2SI 0 "register_operand" "=r")
|
|
|
|
|
(zero_extend:V2SI
|
|
|
|
|
(vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
|
|
|
|
|
(parallel [(const_int 0) (const_int 1)]))))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
"unpkbl %r1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
|
|
|
|
(define_expand "builtin_unpkbw"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand:DI 0 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(zero_extend:V4HI
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(vec_select:V4QI (match_operand:DI 1 "register_operand")
|
alpha.c (reg_or_const_int_operand): New.
* config/alpha/alpha.c (reg_or_const_int_operand): New.
(some_operand, input_operand): Accept CONST_VECTOR.
(alpha_extra_constraint): Add 'W'.
(alpha_expand_zap_mask): New.
(alpha_expand_builtin_vector_binop): New.
(enum alpha_builtin): New.
(zero_arg_builtins, one_arg_builtins, two_arg_builtins): New.
(alpha_init_builtins, alpha_expand_builtin): New.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): New.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): New.
(PREDICATE_CODES): Update.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPEC_CMPBGE, UNSPEC_ZAP,
UNSPEC_AMASK, UNSPEC_IMPLVER, UNSPEC_PERR, UNSPECV_RPCC): New.
(movv8qi, movv8qi_fix, movv8qi_nofix): New.
(movv4hi, movv4hi_fix, movv4hi_nofix): New.
(movv2si, movv2si_fix, movv2si_nofix): New.
(uminv8qi3, sminv8qi3, uminv4hi3, sminv4hi3): New.
(umaxv8qi3, smaxv8qi3, umaxv4hi3, smaxv4hi3): New.
(builtin_cmpbge, builtin_extql, builtin_extqh, builtin_zap,
builtin_zap_1, builtin_zapnot, builtin_zapnot_1, builtin_amask,
builtin_implver, builtin_rpcc, builtin_minub8, builtin_minsb8,
builtin_minuw4, builtin_minsw4, builtin_maxub8, builtin_maxsb8,
builtin_maxuw4, builtin_maxsw4, builtin_perr, builtin_pklb,
pklb, builtin_pkwb, pkwb, builtin_unpkbl, unpkbl,
builtin_unpkbw, unpkbw): New.
* doc/extend.texi (Alpha Built-in Functions): New.
* gcc.dg/alpha-base-1.c, gcc.dg/alpha-base-2.c: New.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: New.
From-SVN: r54229
2002-06-04 06:06:38 +02:00
|
|
|
|
(parallel [(const_int 0)
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 2)
|
|
|
|
|
(const_int 3)]))))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
{
|
|
|
|
|
operands[0] = gen_lowpart (V4HImode, operands[0]);
|
|
|
|
|
operands[1] = gen_lowpart (V8QImode, operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*unpkbw"
|
|
|
|
|
[(set (match_operand:V4HI 0 "register_operand" "=r")
|
|
|
|
|
(zero_extend:V4HI
|
|
|
|
|
(vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
|
|
|
|
|
(parallel [(const_int 0)
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(const_int 2)
|
|
|
|
|
(const_int 3)]))))]
|
|
|
|
|
"TARGET_MAX"
|
|
|
|
|
"unpkbw %r1,%0"
|
|
|
|
|
[(set_attr "type" "mvi")])
|
|
|
|
|
|
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
2005-04-18 18:13:00 +02:00
|
|
|
|
(include "sync.md")
|
|
|
|
|
|
1999-10-01 02:45:07 +02:00
|
|
|
|
;; The call patterns are at the end of the file because their
|
|
|
|
|
;; wildcard operand0 interferes with nice recognition.
|
|
|
|
|
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(define_insn "*call_value_osf_1_er_noreturn"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
|
|
|
|
|
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
|
|
|
|
|
"@
|
|
|
|
|
jsr $26,($27),0
|
|
|
|
|
bsr $26,%1\t\t!samegp
|
|
|
|
|
ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,*,8")])
|
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(define_insn "*call_value_osf_1_er"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
2001-09-11 10:52:39 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"@
|
|
|
|
|
jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
|
2002-12-20 20:42:41 +01:00
|
|
|
|
bsr $26,%1\t\t!samegp
|
2001-09-19 20:55:22 +02:00
|
|
|
|
ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "12,*,16")])
|
|
|
|
|
|
|
|
|
|
;; We must use peep2 instead of a split because we need accurate life
|
|
|
|
|
;; information for $gp. Consider the case of { bar(); while (1); }.
|
|
|
|
|
(define_peephole2
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand 0)
|
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand"))
|
|
|
|
|
(match_operand 2)))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
2002-01-24 05:01:11 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
|
2002-12-20 20:42:41 +01:00
|
|
|
|
&& ! samegp_function_operand (operands[1], Pmode)
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
&& (peep2_regno_dead_p (1, 29)
|
|
|
|
|
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(parallel [(set (match_dup 0)
|
|
|
|
|
(call (mem:DI (match_dup 3))
|
|
|
|
|
(match_dup 2)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
2002-01-11 04:47:24 +01:00
|
|
|
|
(use (match_dup 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (match_dup 4))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
{
|
|
|
|
|
if (CONSTANT_P (operands[1]))
|
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_rtx_REG (Pmode, 27);
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
|
|
|
|
|
operands[1], operands[4]));
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[3] = operands[1];
|
|
|
|
|
operands[1] = const0_rtx;
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[4] = const0_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_peephole2
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(parallel [(set (match_operand 0)
|
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand"))
|
|
|
|
|
(match_operand 2)))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
2002-01-24 05:01:11 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
|
2002-12-20 20:42:41 +01:00
|
|
|
|
&& ! samegp_function_operand (operands[1], Pmode)
|
alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode.
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
From-SVN: r76172
2004-01-19 20:49:33 +01:00
|
|
|
|
&& ! (peep2_regno_dead_p (1, 29)
|
|
|
|
|
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
|
2001-09-19 20:55:22 +02:00
|
|
|
|
[(parallel [(set (match_dup 0)
|
|
|
|
|
(call (mem:DI (match_dup 3))
|
|
|
|
|
(match_dup 2)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set (match_dup 6)
|
|
|
|
|
(unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
|
2002-01-11 04:47:24 +01:00
|
|
|
|
(use (match_dup 1))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (match_dup 5))
|
|
|
|
|
(clobber (reg:DI 26))])
|
|
|
|
|
(set (match_dup 6)
|
|
|
|
|
(unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
{
|
|
|
|
|
if (CONSTANT_P (operands[1]))
|
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_rtx_REG (Pmode, 27);
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[5] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
|
|
|
|
|
operands[1], operands[5]));
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[3] = operands[1];
|
|
|
|
|
operands[1] = const0_rtx;
|
2002-01-11 04:47:24 +01:00
|
|
|
|
operands[5] = const0_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
}
|
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
2007-04-06 00:39:56 +02:00
|
|
|
|
operands[6] = pic_offset_table_rtx;
|
2001-09-19 20:55:22 +02:00
|
|
|
|
})
|
|
|
|
|
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(define_insn "*call_value_osf_2_er_nogp"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(use (reg:DI 29))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 3))
|
|
|
|
|
(use (match_operand 4))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2002-01-11 04:47:24 +01:00
|
|
|
|
"jsr $26,(%1),%3%J4"
|
2007-04-06 00:39:56 +02:00
|
|
|
|
[(set_attr "type" "jsr")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_value_osf_2_er"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "register_operand" "c"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set (reg:DI 29)
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")]
|
2007-04-06 00:39:56 +02:00
|
|
|
|
UNSPEC_LDGP1))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(use (match_operand 3))
|
|
|
|
|
(use (match_operand 4))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
|
2003-10-27 07:49:41 +01:00
|
|
|
|
[(set_attr "type" "jsr")
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set_attr "cannot_copy" "true")
|
|
|
|
|
(set_attr "length" "8")])
|
2001-09-11 10:52:39 +02:00
|
|
|
|
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(define_insn "*call_value_osf_1_noreturn"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
|
|
|
|
|
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
"@
|
2007-04-06 00:39:56 +02:00
|
|
|
|
jsr $26,($27),0
|
|
|
|
|
bsr $26,$%1..ng
|
|
|
|
|
jsr $26,%1"
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(set_attr "length" "*,*,8")])
|
alpha.c (alpha_next_sequence_number): New.
* config/alpha/alpha.c (alpha_next_sequence_number): New.
(alpha_this_literal_sequence_number): New.
(alpha_this_gpdisp_sequence_number): New.
(some_operand, input_operand): Add HIGH.
(local_symbolic_operand): New.
(alpha_encode_section_info): New.
(alpha_legitimate_address_p): Allow LO_SUM.
(alpha_legitimize_address): Generate HIGH+LO_SUM.
(alpha_expand_mov): Likewise.
(secondary_reload_class): Check memory_operand not general_operand
for FP_REGS test.
(alpha_expand_unaligned_load): Force LO_SUM addresses into a register.
(alpha_expand_unaligned_store): Likewise.
(alpha_expand_unaligned_load_words): Likewise.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_block_clear): Likewise.
(print_operand): Handle %#, %*, %H.
(print_operand_address): Handle LO_SUM.
(find_lo_sum): New.
(alpha_does_function_need_gp): Use it.
(alpha_expand_block_move): Fix signed compare warnings.
(alpha_sa_mask, alpha_align_insns): Likewise.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.h (TARGET_EXPLICIT_RELOCS): New.
(MASK_EXPLICIT_RELOCS): New.
(TARGET_SWITCHES): Add -mexplicit-relocs.
(EXTRA_CONSTRAINT): Add 'T'.
(PREFERRED_RELOAD_CLASS): HIGH goes in GENERAL_REGS.
(ASM_APP_ON, ASM_APP_OFF): Turn on and off asm macro expansion.
(ENCODE_SECTION_INFO): Out line.
(REDO_SECTION_INFO_P): New.
(STRIP_NAME_ENCODING): New.
(ASM_OUTPUT_LABELREF): New.
(PRINT_OPERAND_PUNCT_VALID_P): Add #, *.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (divmodsi_internal_er, divmoddi_internal_er,
call_osf_1_er_noreturn, call_osf_1_er, movdi_er_low, movdi_er_nofix,
movdi_er_fix, prologue_ldgp_1_er, builtin_setjmp_receiver_sub_label_er,
builtin_setjmp_receiver_er, exception_receiver_1_er,
call_value_osf_1_er): New patterns.
(sibcall_osf_1, sibcall_value_osf_1): Remove register alternative.
(movqi, movhi, movsi): Add explicit $31 base register to lda.
* config/alpha/elf.h (ASM_FILE_START): Set nomacro if explicit relocs.
(FINAL_PRESCAN_INSN): New.
From-SVN: r45493
2001-09-09 10:42:40 +02:00
|
|
|
|
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(define_int_iterator TLS_CALL
|
|
|
|
|
[UNSPEC_TLSGD_CALL
|
|
|
|
|
UNSPEC_TLSLDM_CALL])
|
|
|
|
|
|
|
|
|
|
(define_int_attr tls
|
|
|
|
|
[(UNSPEC_TLSGD_CALL "tlsgd")
|
|
|
|
|
(UNSPEC_TLSLDM_CALL "tlsldm")])
|
|
|
|
|
|
|
|
|
|
(define_insn "call_value_osf_<tls>"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
|
|
|
|
(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(const_int 0)))
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))]
|
|
|
|
|
"HAVE_AS_TLS"
|
2014-12-02 11:04:14 +01:00
|
|
|
|
"ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "16")])
|
|
|
|
|
|
|
|
|
|
;; We must use peep2 instead of a split because we need accurate life
|
|
|
|
|
;; information for $gp.
|
|
|
|
|
(define_peephole2
|
|
|
|
|
[(parallel
|
|
|
|
|
[(set (match_operand 0)
|
|
|
|
|
(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
|
|
|
|
|
(const_int 0)))
|
|
|
|
|
(unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
|
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
|
|
|
|
"HAVE_AS_TLS && reload_completed
|
|
|
|
|
&& peep2_regno_dead_p (1, 29)"
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
[(set (match_dup 3)
|
|
|
|
|
(unspec:DI [(match_dup 5)
|
|
|
|
|
(match_dup 1)
|
|
|
|
|
(match_dup 2)] UNSPEC_LITERAL))
|
|
|
|
|
(parallel [(set (match_dup 0)
|
|
|
|
|
(call (mem:DI (match_dup 3))
|
|
|
|
|
(const_int 0)))
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(use (match_dup 5))
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(use (match_dup 1))
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(use (unspec [(match_dup 2)] TLS_CALL))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))])
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(set (match_dup 5)
|
|
|
|
|
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
|
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_rtx_REG (Pmode, 27);
|
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
operands[5] = pic_offset_table_rtx;
|
2014-12-02 11:04:14 +01:00
|
|
|
|
})
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(define_peephole2
|
|
|
|
|
[(parallel
|
|
|
|
|
[(set (match_operand 0)
|
|
|
|
|
(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
|
|
|
|
|
(const_int 0)))
|
|
|
|
|
(unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
|
|
|
|
|
(use (reg:DI 29))
|
|
|
|
|
(clobber (reg:DI 26))])]
|
|
|
|
|
"HAVE_AS_TLS && reload_completed
|
|
|
|
|
&& !peep2_regno_dead_p (1, 29)"
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
[(set (match_dup 3)
|
|
|
|
|
(unspec:DI [(match_dup 5)
|
|
|
|
|
(match_dup 1)
|
|
|
|
|
(match_dup 2)] UNSPEC_LITERAL))
|
|
|
|
|
(parallel [(set (match_dup 0)
|
|
|
|
|
(call (mem:DI (match_dup 3))
|
|
|
|
|
(const_int 0)))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(set (match_dup 5)
|
|
|
|
|
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
(use (match_dup 1))
|
2014-12-02 11:04:14 +01:00
|
|
|
|
(use (unspec [(match_dup 2)] TLS_CALL))
|
2007-04-06 00:39:56 +02:00
|
|
|
|
(clobber (reg:DI 26))])
|
|
|
|
|
(set (match_dup 5)
|
|
|
|
|
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_rtx_REG (Pmode, 27);
|
|
|
|
|
operands[4] = GEN_INT (alpha_next_sequence_number++);
|
|
|
|
|
operands[5] = pic_offset_table_rtx;
|
2014-12-02 11:04:14 +01:00
|
|
|
|
})
|
configure.in (HAVE_AS_TLS): Add alpha tests.
* configure.in (HAVE_AS_TLS): Add alpha tests.
* configure: Rebuild.
* config/alpha/alpha.c (TARGET_AS_TLS): New.
(alpha_tls_size, alpha_tls_size_string): New.
(overide_options): Set it. Always install machine_status hooks.
(input_operand): Accept got tls predicates.
(local_symbol_p): Merge into ...
(local_symbolic_operand): ... here. Reject tls symbols.
(global_symbolic_operand): Likewise.
(tls_symbolic_operand_1, dtp16_symbolic_operand): New.
(dtp32_symbolic_operand, gotdtp_symbolic_operand): New.
(tp16_symbolic_operand, tp32_symbolic_operand): New.
(gottp_symbolic_operand, tls_symbolic_operand_type): New.
(alpha_encode_section_info): Handle TLS symbols.
(alpha_strip_name_encoding): Likewise.
(alpha_legitimate_address_p): Likewise.
(alpha_legitimize_address): Likewise.
(alpha_expand_mov): Early exit to avoid nop moves.
(struct machine_function): Move from unicosmk.h. Add some_ld_name.
(alpha_init_machine_status, alpha_mark_machine_status,
alpha_free_machine_status): Always define.
(get_some_local_dynamic_name, get_some_local_dynamic_name_1): New.
(print_operand, print_operand_address): Add TLS relocs.
* config/alpha/alpha.h (HAVE_AS_TLS): Default 0.
(MASK_TLS_KERNEL, TARGET_TLS_KERNEL): New.
(TARGET_SWITCHES): Add -mtls-kernel.
(alpha_tls_size, alpha_tls_size_string): New.
(TARGET_OPTIONS): Add -mtls-size=.
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REGNO_REG_CLASS, REG_CLASS_FROM_LETTER): Add R0_REG.
(ASM_OUTPUT_LABELREF): Skip %.
(PRINT_OPERAND_PUNCT_VALID_P): Add &.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (UNSPEC_TLSGD_CALL, UNSPEC_TLSLDM_CALL,
UNSPEC_TLSGD, UNSPEC_TLSLDM, UNSPEC_DTPREL, UNSPEC_TPREL,
UNSPEC_TP, UNSPECV_SET_TP): New.
(adddi_er_lo16_dtp, adddi_er_hi32_dtp, adddi_er_lo32_dtp,
adddi_er_lo16_tp, adddi_er_hi32_tp, adddi_er_lo32_tp, load_tp,
set_tp, movdi_er_tlsgd, movdi_er_tlsldm, movdi_er_gotdtp,
movdi_er_gottp, call_value_osf_tlsgd, call_value_osf_tlsldm): New.
(call_value_osf_2_er): Accept anything as op4.
* config/alpha/alpha-protos.h: Update.
* config/alpha/unicosmk.h (struct machine_function): Move to alpha.c.
From-SVN: r54125
2002-06-01 02:19:10 +02:00
|
|
|
|
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*call_value_osf_1"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(use (reg:DI 29))
|
1999-10-01 02:45:07 +02:00
|
|
|
|
(clobber (reg:DI 26))]
|
2001-09-19 20:55:22 +02:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
1999-10-01 02:45:07 +02:00
|
|
|
|
"@
|
|
|
|
|
jsr $26,($27),0\;ldgp $29,0($26)
|
|
|
|
|
bsr $26,$%1..ng
|
|
|
|
|
jsr $26,%1\;ldgp $29,0($26)"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "12,*,16")])
|
|
|
|
|
|
2001-12-16 06:40:26 +01:00
|
|
|
|
(define_insn "*sibcall_value_osf_1_er"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-12-16 06:40:26 +01:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2001-12-24 04:08:23 +01:00
|
|
|
|
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
|
2001-12-16 06:40:26 +01:00
|
|
|
|
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
|
|
|
|
"@
|
2002-12-20 20:42:41 +01:00
|
|
|
|
br $31,%1\t\t!samegp
|
2001-12-16 06:40:26 +01:00
|
|
|
|
ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
|
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,8")])
|
|
|
|
|
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*sibcall_value_osf_1"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-11-28 19:36:14 +01:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2001-12-24 04:08:23 +01:00
|
|
|
|
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
|
2001-12-16 06:40:26 +01:00
|
|
|
|
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
|
2001-10-17 00:44:39 +02:00
|
|
|
|
"@
|
|
|
|
|
br $31,$%1..ng
|
2001-10-19 07:04:54 +02:00
|
|
|
|
lda $27,%1\;jmp $31,($27),%1"
|
2001-10-17 00:44:39 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "*,8")])
|
2000-03-17 23:41:25 +01:00
|
|
|
|
|
2002-08-15 07:04:27 +02:00
|
|
|
|
; GAS relies on the order and position of instructions output below in order
|
|
|
|
|
; to generate relocs for VMS link to potentially optimize the call.
|
|
|
|
|
; Please do not molest.
|
2000-03-17 23:41:25 +01:00
|
|
|
|
(define_insn "*call_value_vms_1"
|
2012-10-14 14:50:45 +02:00
|
|
|
|
[(set (match_operand 0)
|
2001-09-19 20:55:22 +02:00
|
|
|
|
(call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
|
2012-10-14 14:50:45 +02:00
|
|
|
|
(match_operand 2)))
|
2002-08-15 07:04:27 +02:00
|
|
|
|
(use (match_operand:DI 3 "nonmemory_operand" "r,n"))
|
1999-10-01 02:45:07 +02:00
|
|
|
|
(use (reg:DI 25))
|
|
|
|
|
(use (reg:DI 26))
|
|
|
|
|
(clobber (reg:DI 27))]
|
2001-07-15 09:17:29 +02:00
|
|
|
|
"TARGET_ABI_OPEN_VMS"
|
2002-08-15 07:04:27 +02:00
|
|
|
|
{
|
|
|
|
|
switch (which_alternative)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
2002-12-16 19:23:00 +01:00
|
|
|
|
return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
|
2002-08-15 07:04:27 +02:00
|
|
|
|
case 1:
|
2011-11-04 10:11:27 +01:00
|
|
|
|
operands [3] = alpha_use_linkage (operands [1], true, false);
|
|
|
|
|
operands [4] = alpha_use_linkage (operands [1], false, false);
|
2002-12-16 19:23:00 +01:00
|
|
|
|
return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
|
2002-08-15 07:04:27 +02:00
|
|
|
|
default:
|
alpha.c (tls_symbolic_operand_1): Use gcc_assert and gcc_unreachable as appropriate.
* config/alpha/alpha.c (tls_symbolic_operand_1): Use gcc_assert
and gcc_unreachable as appropriate.
(get_aligned_mem, get_unaligned_address,
alpha_emit_set_long_const, alpha_emit_conditional_branch,
alpha_emit_setcc, alpha_emit_conditional_move,
alpha_lookup_xfloating_lib_func, alpha_compute_xfloating_mode_arg,
alpha_emit_xfloating_libcall, alpha_split_tfmode_pair,
alpha_expand_unaligned_load, alpha_expand_block_move,
alpha_expand_zap_mask, get_trap_mode_suffix,
get_round_mode_suffix, get_some_local_dynamic_name,
print_operand_address, function_arg, alpha_return_in_memory,
function_value, alpha_expand_builtin,
alpha_initial_elimination_offset, alpha_expand_epilogue,
summarize_insn, alpha_handle_trap_shadows, alphaev5_insn_pipe,
alphaev5_next_group, alpha_align_insns,
unicosmk_initial_elimination_offset, unicosmk_unique_section,
unicosmk_ssib_name): Likewise.
* config/alpha/alpha.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
* config/alpha/unicosmk.h (TRAMPOLINE_TEMPLATE,
ASM_OUTPUT_ADDR_DIFF_ELT, ASM_OUTPUT_ADDR_DIFF_VEC): Likewise.
* config/alpha/vms.h (INITIAL_ELIMINATION_OFFSET,
ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
* config/alpha/alpha.md (*divmodsi_internal_er,
*divmoddi_internal_er, ashldi3, *insxl, sibcall, call_osf,
call_nt, call_umk, call_vms, call_value, sibcall_value,
call_value_osf, call_value_nt, call_value_vms, call_value_umk,
*call_vms_1, *movmemdi_1, *clrmemdi_1, *call_value_vms_1): Likewise.
* config/alpha/predicates.md (input_operand): Likewise.
Co-Authored-By: Falk Hueffner <falk@debian.org>
From-SVN: r99384
2005-05-08 11:48:22 +02:00
|
|
|
|
gcc_unreachable ();
|
2002-08-15 07:04:27 +02:00
|
|
|
|
}
|
2002-12-16 19:23:00 +01:00
|
|
|
|
}
|
1999-10-01 02:45:07 +02:00
|
|
|
|
[(set_attr "type" "jsr")
|
|
|
|
|
(set_attr "length" "12,16")])
|