Other than the nice advantage of all sims having to declare one fewer
common function, this also fixes leakage in pretty much every sim.
Many were not freeing any resources, and a few were inconsistent as
to the ones they did. Now we have a single module that takes care of
all the logic for us.
Most of the non-cgen based ones could be deleted outright. The cgen
ones required adding a callback to the arch-specific cleanup func.
The few that still have close callbacks are to manage their internal
state.
We do not convert erc32, m32c, ppc, rl78, or rx as they do not use
the common sim core.
Sometimes in tests, we need supplemental files like linker scripts or
board helper files. There's no way to set those flags in the tests
currently and relative paths don't work (breaks out of tree builds).
Update the main option parser to replace some strings on the fly. Now
tests can do things like:
Long term we'll want to switch the framework to use the dejagnu helpers
like dg-xxx that gcc & gdb utilize. But that'll require more rework.
When handling left saturated ashifts with negative immediates, they
should be treated as right ashifts. This matches hardware behavior.
Reported-by: Igor Rayak <igorr@gitatechnologies.com>
The FT32 simulator was not correctly simulating the behavior of the
program memory (PM) write port. When it is locked, writes to the
data register do nothing.
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
The FT32 simulator has character output, of course. This patch
adds character input, which lets the simulator run interactive
FT32 applications, e.g. language interpreters.
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.
This helper macro has largely the same behavior as libiberty's lbasename.
There is a slight nuance related to colons, but it's not clear what the
point of that is, and the code implies that it just wants the basename.
Since --trace-debug is for people hacking on the sim sources rather than
people just using the sim, default it to off. This matches the behavior
of other debug knobs we have.
Since we always include the raw syscall number when tracing, also
including it in the name when it's unknown is redundant. Simplify
the code by using a constant string.
The new helpers for walking the maps tested the wrong value for exiting
the for loop. This caused crashes when looking up entries that were not
in the map.
Many ports have the same sim syscall logic, so add some helpers to handle
all the common details. The arches still have to deal with the unpacking
and packing of the syscall arguments, but the rest of the sim<->callback
glue is now shared.
When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
The Blackfin port had some TRACE_xxx macros for easily logging trace data.
Use these as a base for common ones that have a simple form and match the
existing sets of helper macros.
The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
This is the only sim that sets up its own WITH_TRACE mask and it conflicts
with the user setting their own list at configure time. Drop it to match
all the other sims.
The syscall path was the only code checking the custom exception state
after recent cleanups. Once we change that to the common engine halt
function, we can delete that state entirely.
This also helps highlight some other dead code that we can cull.
These printf statements are showing "word" objects which are typedefed
from long, so make sure to use l with %x when printing them to avoid
warnings from gcc.
Re-use the existing memory core that handles reads/writes.
The verbose command is converted to the common --verbose flag
since only a few call sites use it now.
In preparation for converting to the common memory framework, the custom
commands get in our way. But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.
So lets disable watchpoint support until it can be converted to the common
watchpoint logic. There's already an ifdef to let us do that.
We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).
We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources. We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree. It sucks, but better than the status quo (no workie).
Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
Now that we've unified sim-cpu, we can delete the duplicate sim-engine
hooks -- these targets defined these only because they didn't fully
implement the sim-cpu callbacks.
Since every target typedefs this the same way, move it to the common code.
We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size. The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense. We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
Re-use the existing memory core that handles reads/writes.
This drops support for the dumpmem command, but gdb itself has
support for dumping memory regions.
The verbose command is converted to the common --verbose flag
since only two call sites use it now.
Support for the clearstats command is dropped entirely, but no
other sim really does this, and the same thing can be done by
reloading. If it's important (clearing cycle stats) to someone,
we can add a common function for it.
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
This sets up the sim_state structure and the cpu member to match what we
do in most other sims, and what the common code suggests. This is a step
to unifying on the sim-cpu.o object.
The old run frontend had a --version option, but the new common
sim-options file does not. Restore support for that so we can
get version info out of `run` when using the new frontend.
With sim-hrw.o being built & linked in the common list, some people are
getting linking errors now for these targets. Move the main objects that
provide these functions before the common list to avoid that.
The nrun conversion was slightly incorrect in how it stopped when an
exception occurred. We still set cpu.asregs.exception, but nothing
was checking it anymore. Convert all of that to sim_engine_halt.
To keep things from regressing again, add a basic testsuite too.
Way back in aba6488e0b, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx. For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set. Which meant in some cases, the sim would never
actually stop.
Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
Now that all targets have been converted to nrun, we can finally punt
this old inconsistent interface.
A few stray references to the old run were sprinkled about; clean them
up in the process.
We leave behind the run(1) man page mostly so that we get it updated for
the new nrun interface.
With newer versions of gcc (5.x), the extern inline we're using with the
cgen-{mem,ops} modules no longer work. Since this code really wants the
gnu inline semantics, use that attribute explicitly.
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
In preparation for converting to nrun, call the common functions that
are needed. This doesn't produce any new warnings, and the generated
code should be the same.
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
In preparation for converting to nrun, call the common functions that
are needed. This doesn't produce any new warnings, and the generated
code should be the same.
Looks like historical restructuring in this dir lost the d10v-elf subdir
and no one noticed in the meantime. Re-add it to the testsuite.
There are some failures, but better some tests get run than none at all.
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
In preparation for converting to nrun, call the common functions that
are needed. This doesn't produce any new warnings, and the generated
code should be the same.
This port already was storing its cpu state in the sim_cpu structure, so
converting it over was pretty easy. It is allocating memory itself still,
but we'll fix that up in the future at some point.
The mcore port had a few structs/defines that were never used.
Similarly, the microblaze port, because it was copied from mcore, has
that same dead code, and more. The watchpoint logic was never actually
used. Punt it all.
Since the sim doesn't have any debug support in it, we can only exit
cleanly. But this is still better than nothing.
Change the default microblaze sim to not dump the debug load output
when running. No other does this, and it breaks the testsuite.
If a test doesn't write anything at all to stdout, the current test
framework can't support that. Even if you put a blank output line:
# output:
the setup happily clobbers that with a default pass/fail string.
Tweak the parsing logic so we only set the output to pass/fail when
the test has no output marker.
With newer versions of gcc (5.x), the extern inline we're using with the
sim-arange module no longer works. Since this code really wants the gnu
inline semantics, use that attribute explicitly.
Reported-by: DJ Delorie <dj@redhat.com>
Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
Since the testsuite subdir has to handle dynamic arch values already,
there's no real value in requiring arches to opt in to it. Most have
a testsuite now anyways, and we're requiring it in the future.
In preparation for converting to nrun, call the common functions that
are needed. This doesn't produce any new warnings, and the generated
code should be the same.
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
In preparation for converting to nrun, call the common functions that
are needed. This doesn't produce any new warnings, and the generated
code should be the same.
The sbrk syscall assumes the sbrk region starts after the bss and the
current implementation requires a bss section to exist. Since there
is no requirement for programs to have a bss in general, we want to
drop this check. However, there is still the sbrk syscall that wants
to know about the region.
Since libgloss doesn't actually use the sbrk syscall (it implements
sbrk in its own way), and the sim really shouldn't enforce a specific
memory layout on programs, lets simply delete sbrk support. Now it
always returns an error.
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
The build line was missing the normal BUILD_xxx flags. Once we added
that, we get warnings that weren't shown before. As we fix those, we
notice that the -d option segfaults because it tries to write readonly
memory. Fix that too as part of the const/prototype clean up.
The previous profile change broke these sims that use sim-profile but
not sim-cpu (due to missing model support). Add simple funcs until we
can convert these over properly.
The profile code was using STATE_WATCHPOINTS to get access to the PC, but
we already have a standard method for getting the pc, so switch to that.
This assumes that sizeof_pc is the same size as sim_cia, but we already
assume this in places by way of sim_pc_{get,set}, and this is how it's
documented in the sim-base.h API.
This partially reverts commits:
105dd264de3df3af7c3fc4892a6b379e3042ec07
Now that dv-sockser is handled entirely by the common build logic, the
failure these targets were hitting isn't really possible anymore. Lets
reset their hardware status back to defaulting to on. Some of these
were set to "always" previously, but we don't support that anymore.
The current default handling for the --enable-sim-hardware option ends up
forcing the value to whatever is set as the first argument when calling
the macro (by virtue of how autoconf works). Relocate the setup code to
the 4th parameter of the AC_ARG_ENABLE macro to fix it.
This was caused by the simplification work in 1517bd2742.
Reported-by: Hans-Peter Nilsson <hans-peter.nilsson@axis.com>
Since no sim is using the "always" option to SIM_AC_OPTION_HARDWARE, and
we don't want to require hw support to always be enabled, drop the option.
This leads to a slight simplification in the macro too as we can collapse
the sim_hw_p variable.
This looks like copy & paste logic from the m32r port (and history
suggests this as well). Since building with hw & device support
enabled leads to failures:
sim/frv/devices.c: In function 'device_io_read_buffer':
sim/frv/devices.c:39:15: error: 'UART_INCHAR_ADDR' undeclared (first use in this function)
Delete it entirely. We leave device support in place as it is used
to flush the scache.
If dv-sockser is available, lets add it to the common SIM_HW_OBJS
variable so it is always included automatically. Now ports do not
have to shoe horn it in directly themselves. It does mean it will
be compiled for targets that don't explicitly use it, but that's
really what we want anyways.
This lets ports assume that the dv-sockser API is always available if
they want to. This way we don't have to do an abort at configure time
and it makes the resulting code a bit simpler.
* load.c (rl78_load): If the G10, G13 or G14 flag bits are set in
the ELF header use them to select the proper emulation mode.
* mem.c (mem_put_byte): Use mem_put_hi to store a value into the
MDB register.
(mem_get_byte): Use mem_get_hi to extract a value from the MDB
register.
Rather than manually include tconfig.h when we think we'll need it (which
is error prone as it can define symbols we expect from config.h), have it
be included directly by config.h. Since we know we have to include that
header everywhere already, this will make sure tconfig.h isn't missed.
It should also be fine as tconfig.h is supposed to be simple and only set
up a few core defines for the target.
This allows us to stop symlinking it in place all the time and just use
it straight out of the respective source directory.
Pull out the duplicated dv_sockser_install prototype from the tconfig.in
files and put it in the one place it gets used -- sim-module.c. This is
still arguably incorrect, but it's better than the status quo where the
tconfig.in has to include header files and duplicate the dv-sockser func.
The tconfig header is meant to be simple and contain a target defines.
This dates back to the start of the repo, but has never really been used.
The sim-inline.c file has been checked in to the source, and attempts to
build it in the build tree leads to a circular dep warning from make. It
also doesn't produce a file that is usable -- it can't be compiled. Punt!
We want people to stop using the run.c frontend, but it's hard to notice
when it's still set as the default. Lets flip things so nrun.c is the
default, and users of run.c will get an error by default. We turn that
error into a warning for existing sims so we don't break them -- this is
mostly meant for people starting new ports.
Since sim-endian.c doesn't actually use sim_io funcs, it's weird to
include the sim-io.h header here. It's doing so only for the assert
header. So lets relocate the include to the right place.
Add a trailing semi-colon to the sed print command as the BSD sed
implementation wants it. It's a nop otherwise and works fine on
GNU/etc... implementations too.
The use of $< ends up picking the wrong object out of the depend
list. Specify the input name directly to avoid fragility.
On BSD systems, we need to make sure all options come before the
non-options (i.e. the files).
Reported-by: Chris Johns <chrisj@rtems.org>
URL: https://sourceware.org/bugzilla/show_bug.cgi?id=13160
* v850.igen: Add more e3v5 support.
(FMAF.S): New pattern.
(FMSF.S): New pattern.
(FNMAF.S): New pattern.
(FNMSF.S): New pattern.
(cnvq15q30): New pattern.
(cnvq30q15): New pattern.
(cnvq31q62): New pattern.
(cnvq62q31): New pattern.
(dup.h): New pattern.
(dup.w): New pattern.
(expq31): New pattern.
(modadd): New pattern.
(mov.dw): New pattern.
(mov.h): New pattern.
(mov.w): New pattern.
(pki16i32): New pattern.
(pki16ui8): New pattern.
(pki32i16): New pattern.
(pki64i32): New pattern.
(pkq15q31): New pattern.
(pkq30q31): New pattern.
(pkq31q15): New pattern.
(pkui8i16): New pattern.
(vabs.h): New pattern.
(vabs.w): New pattern.
(vadd.dw): New placeholder pattern.
(vadd.h): New placeholder pattern.
(vadd.w): New placeholder pattern.
(vadds.h): New placeholder pattern.
(vadds.w): New placeholder pattern.
(vaddsat.h): New placeholder pattern.
(vaddsat.w): New placeholder pattern.
(vand): New pattern.
(vbiq.h): New placeholder pattern.
(vbswap.dw): New placeholder pattern.
(vbswap.h): New placeholder pattern.
(vbswap.w): New placeholder pattern.
(vcalc.h): New placeholder pattern.
(vcalc.w): New placeholder pattern.
(vcmov): New placeholder pattern.
* msp430-sim.c (sim_open): Allocate memory regions matching those
declared in the libgloss/msp430 linker scripts.
Allow sim_load_file to fail.
(get_op): Test the correct address bit when checking for out of
range addresses.
Include the address in the error message when an illegal access to
the hardware multiplier is detected.
(put_op): Test the correct address bit when checking for out of
range addresses.
Binaries produced by most erc32 tool-chains do not include
system initialization. sis will detect this and initialize
necessary registers for memory and timer control.
These look like left over hacks from the days where we had to protect
ourselves from the compiler and C library. None of these checks are
relevant, and we have common configure logic to do header tests. Punt
them all now.
Commit 07774fccc3 update the microblaze
opcodes table to avoid C++ collisions, but missed updating the sim.
That caused it to fail to build due to missing keywords.
After successfully call buildargv(), the code need to be sure of calling
freeargv() in any cases.
2015-02-02 Chen Gang <gang.chen.5i5j@gmail.com>
* common/sim-options.c (sim_args_command): Call freeargv() when
failure occurs.
This should fix a build failure reported on x86_64-mingw32 by Daniel
Calcoen due to conflicting declarations of "open". This patch just
renames the static global in sim/rx/gdb-if.c into "rx_sim_is_open".
sim/rx/ChangeLog:
* gdb-if.c (open): Rename to...
(rx_sim_is_open): This. Replace all uses of "open" by uses of
"rx_sim_is_open" throughout.
Tested by rebuilding on x86_64-linux.
... using automake 1.11.1, which is the version we're currently
using throughout, instead of 1.11.3. This should be a no-op in
practice, but will help automake/aclocal version-related
differences to cloud real changes being made.
sim/common/ChangeLog:
* aclocal.m4, configure: Regenerate using automake 1.11.1.
On Windows, a recent gnulib update imported the lstat module, and
this caused a remote-sim.c build failure in struct host_callback_struct:
In file included from /[...]/gdb/remote-sim.c:34:0:
/[...]/gdb/../include/gdb/callback.h:93:9: error: duplicate member '_stati64'
int (*lstat) (host_callback *, const char *, struct stat *);
^
What happens it that gnulib's stat.h makes the following defines:
/* Large File Support on native Windows. */
#if 1
# define stat _stati64
#endif
and then:
#if 1
# if ! 0
/* mingw does not support symlinks, therefore it does not have lstat. But
without links, stat does just fine. */
# if !(defined __cplusplus && defined GNULIB_NAMESPACE)
# define lstat stat
# endif
So, the following fields in struct host_callback_struct...
int (*stat) (host_callback *, const char *, struct stat *);
int (*fstat) (host_callback *, int, struct stat *);
int (*lstat) (host_callback *, const char *, struct stat *);
... get translated to...
int (*_stati64) (host_callback *, const char *, struct _stati64 *);
int (*_fstati64) (host_callback *, int, struct _stati64 *);
int (*_stati64) (host_callback *, const char *, struct _stati64 *);
... which causes two fields to have the same name.
This patch fixes the issue by renaming the stat-related fields
by adding a "to_" prefix, similar to what is done in GDB's
target_ops vector.
include/gdb/ChangeLog:
* callback.h (struct host_callback_struct) <to_stat>: Renamed
from "stat".
<to_fstat>: Renamed from "fstat".
<to_lstat>: Renamed from "lstat".
sim/common/ChangeLog:
* sim-io.c (sim_io_stat, sim_io_fstat): Adjust calls to "stat"
and "fstat" callbacks by calls to "to_stat" and "to_fstat" (resp)
callbacks following renaming in callback.h.
* syscall.c (cb_syscall): Likewise. Adjust calls to "lstat"
callback by call to "to_lstat" callback
sim/cris/ChangeLog:
* traps.c (cris_break_13_handler): Adjust call to "fstat" callback
by call to "to_fstat" following renaming in callback.h.
sim/h8300/ChangeLog:
* compile.c (sim_resume): Adjust calls to "stat" and "fstat"
callbacks by calls to "to_stat" and "to_fstat" (resp) callbacks
following renaming in callback.h.
It seems that the implementation of the SH fabs and fneg insns in the
simulator is not correct. They use the FP_UNARY macro which checks the
FPSCR.PR setting and raises an exception if PR = 1 (double precision)
and the register number is not even (i.e. a valid DF reg number).
For normal unary FP insns this is fine. However, fneg and fabs perform
the same (integer) operations regardless of the FPSCR.PR setting.
This issue initially popped up here
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63260
I've checked some of the failing tests mentioned in GCC PR 63260 above
with the patch applied and the failures go away.
sim/sh/ChangeLog (tiny patch):
* gencode.c (fabs, fneg): Implement as integer operation
instead of using the FP_UNARY macro.
GDB and SIM both have functions called "debug_printf", which conflicts
at link time. This commit shadows SIM's debug_printf with a macro so
that SIM's symbol ends up being called "sim_debug_printf".
sim/common/ChangeLog:
* sim-trace.h (debug_printf): New define.
The situation here is similar to that of the other nearby (previous)
sims fixed; it fails at the dv_sockser_install declaration in
sim/m32r/tconfig.in. But, as opposed to e.g. frv, this *does* have a
definition of UART_INCHAR_ADDR et al. It's somewhat tempting to keep
sim-hardware enabled here but, I'm disabling it for the same reasons
as for frv. Unsurprisingly (as m32r seems to be the template), the
same confusing lines are in sim/m32r/Makefile.in as in
sim/frv/Makefile.in at that time, deleted in 73e76d20. Again, commit
73e76d20 (for m32r as well as for frv) attempted to move the
non-existing dv-sockser.o use to $(m32r_extra_objs) but missed that
AC_SUBST would only affect @m32r_extra_objs@ and not
$(m32r_extra_objs) per se so nothing happened. As for frv, I'm
removing the $(m32r_extra_objs) too, to avoid confusion. Make
check-sim for m32r-elf shows no regressions (5 failures; 100 expected
passes) compared to bf3d9781ec (before the recent config.in regen,
after sim-hardware mostly-enabled) and eed23bb4a1 (before the
sim-hardware mostly-enabled; 2013-03-23).
sim/m32r:
* configure.ac: Default simulator hardware to off again. Remove
dead m32r_extra_objs substitution.
* configure: Regenerate.
* Makefile.in: Remove unused frv_extra_objs.
See nearby (previous) commit for the iq2000 sim; this similarly fails
at the dv_sockser_install declaration in sim/sh64/tconfig.in. I'm
disabling simulator hardware to be consistent with the state before
94c63d78f (2013-03-23) and with the actions for the frv sim and the
iq2000 sim. Make check-sim for sh64-elf shows no regressions (25
failures; 357 expected passes) compared to bf3d9781ec (before the
recent config.in regen, after sim-hardware mostly-enabled) and
eed23bb4a1 (before the sim-hardware mostly-enabled; 2013-03-23).
sim/sh64:
* configure.ac: Default simulator hardware to off again
without emitting errors when off or dv-sockser.o unavailable.
* configure: Regenerate.
See nearby (previous) commit for the frv sim; this similarly fails at
the dv_sockser_install declaration in sim/iq2000/tconfig.in. There's
no HAVE_DV_SOCKSER conditionals here and no other dv-sockser.o
artefacts so maybe there is no further fallout, but I'm going to
disable sim-hardware just be consistent with the state before
94c63d78f (2013-03-23) and with the actions for the frv sim. Make
check-sim for iq2000-elf shows no failures but that's in no small part
because it has no test-suite.
sim/iq2000:
* configure.ac: Default simulator hardware to off again
without emitting errors when off or dv-sockser.o unavailable.
* configure: Regenerate.
At 2974be626, frv-elf fails at the dv_sockser_install declaration in
sim/frv/tconfig.in. But, with the trivial #include's added (see other
sims tconfig.in, like cris or mn10300), it *still* fails building
sim/frv/devices.c because of a missing UART_INCHAR_ADDR. I have no
insight into what'd be a valid value, except that there's a definition
in m32r, which was probably used as a template with frv not finished.
Simulated hardware should not have been be enabled, and was indeed not
enabled by default before 94c63d78f (2013-03-23), where it seems to
have been enabled for no simulator-specific reason. Except
dv-sockser.o wasn't enabled even then: sim/frv/config.in wasn't
regenerated, so HAVE_DV_SOCKSER was never defined. Maybe people were
fooled by this in sim/frv/Makefile.in at that time (these two lines
were later deleted, in 73e76d20):
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
(As it seems people have missed it before: the second line overrides
the first...) I'm guessing these lines were part of the
never-completed hardware-support. Commit 73e76d20 attempted to move
the imagined dv-sockser.o from $(CONFIG_DEVICES) to $(frv_extra_objs)
but missed that AC_SUBST would only affect @frv_extra_objs@ (not
$(frv_extra_objs) per se) so nothing happened regarding sockser:
dv-sockser.o was not compiled and HAVE_DV_SOCKSER was not defined.
I'm removing the $(frv_extra_objs) too, to avoid confusion. The best
action seems to be disabling all hardware support by default again
until a specific sim maintainer finishes the work.
Make check-sim for frv-elf shows no failures after this.
sim/frv:
* configure.ac: Default simulator hardware to off again. Remove
dead frv_extra_objs substitution.
* configure: Regenerate.
* Makefile.in: Remove unused frv_extra_objs.
Directories that don't use libtool need to add -ldl (on most *nix
hosts) to provide dlopen for libbfd.
config/
* plugins.m4 (AC_PLUGINS): If plugins are enabled, add -ldl to
LIBS via AC_SEARCH_LIBS.
gdb/
* acinclude.m4 (GDB_AC_CHECK_BFD): Don't add -ldl.
* config.in: Regenerate.
sim/ppc/
* configure.ac: Invoke AC_PLUGINS.
* config.in: Regenerate.
and regen lots of configure files.
* msp430-sim.c: Move static hardware multiply support variables
from here...
* msp430-sim.h (msp430_cpu_state): ... into here ...
* msp430-sim.c (get_op, put_op): ... and update references to use
the msp430_cpu_state structure.
* msp430-sim.c (get_op): Handle reads of low result register when
in MAC mode.
(put_op): Copy MAC result into result words.
Handle writes to the low result register.
* msp430-sim.c (sim_open): Do not allocate memory over the
hardware multiply registers.
(get_op): Add support for reads from the hardware multiply
registers.
(put_op): Add support for writes to the hardware multiply
registers.
(msp430_step_once): Add support for the RETI instruction used by
the CPUX architecture.
PR sim/8388
* armemu.c (WriteR15Load): New function. Determines if the state
can be changed upon a write to R15.
(LoadMult): Use WriteR15Load.
* armemu.h (WRITEDESTB): Use WriteR15Load.
This fix is simple:
msp430-sim.c: In function 'maybe_perform_syscall':
msp430-sim.c:898:10: warning: format '%d' expects argument of type 'int',
but argument 5 has type 'long int' [-Wformat]
This one we change to use casts like everyone else does in the code base:
msp430-sim.c: In function 'msp430_step_once':
msp430-sim.c:985:7: warning: passing argument 3 of 'init_disassemble_info'
from incompatible pointer type [enabled by default]
include/dis-asm.h:368:13: note: expected 'fprintf_ftype' but argument is
of type 'int (*)(struct FILE * __restrict__, const char * __restrict__)'
It is rare for people to want to modify the cmd arg. In general, they
really shouldn't be, but a few still do. For those who misbehave, dupe
the string locally so they can bang on it.
sim/rx/gdb-if.c had a function named `rx_signal_to_host'. This
function mapped signal numbers used by the BSP to host signal
numbers which, at one time a while back, were used by GDB
as target signal numbers. This change updates the signal
numbers returned to be those names prefixed with "GDB_SIGNAL_"
as defined in include/gdb/signals.h.
It also changes the name of the function somewhat to better
match what the function currently does. I noticed that this
function is not static - and there's no reason for it not
to be - so I made it static too.
* gdb-if.c (rx_signal_to_host): Rename to
`rx_signal_to_gdb_signal'. Make static. Update all callers
to use new name. Use signal names from include/gdb/signals.h.
Many of the simulators change the SIGINT handler.
E.g., moxie/interp.c:
sigsave = signal (SIGINT, interrupt);
However, this is unnecessary.
remote-sim.h already provides an API for asynchronously stopping
a sim; and both gdb and the drivers (run.c and nrun.c at least,
I didn't check the others) install a SIGINT handler which
calls this method.
URL: https://sourceware.org/bugzilla/show_bug.cgi?id=16450
Reported-by: Tom Tromey <tromey@redhat.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When cross-compiling GDB for PPC, there's a prerequisite "-lz" for psim
that results in a build failure. With such prerequisite, GNU Make will
try to search the library from build machine's /usr/lib which is wrong.
On 64-bit Linux build machines the compilation will fail because of this.
URL: https://sourceware.org/bugzilla/show_bug.cgi?id=12202
This removes the last uses of PARAMS from sim.
2014-01-06 Tom Tromey <tromey@redhat.com>
* README-HACKING: Don't use PARAMS.
* arm/wrapper.c: Don't use PARAMS.
* bfin/sim-main.h: Don't use PARAMS.
* common/callback.c: Don't use PARAMS.
* common/cgen-trace.c: Don't use PARAMS.
* common/run-sim.h: Don't use PARAMS.
* common/run.c: Don't use PARAMS.
* common/sim-base.h: Don't use PARAMS.
* common/sim-load.c: Don't use PARAMS.
* common/sim-options.h: Don't use PARAMS.
* common/sim-trace.c: Don't use PARAMS.
* common/sim-trace.h: Don't use PARAMS.
* common/sim-utils.h: Don't use PARAMS.
* cr16/cr16_sim.h: Don't use PARAMS.
* cr16/gencode.c: Don't use PARAMS.
* cr16/interp.c: Don't use PARAMS.
* cr16/simops.c: Don't use PARAMS.
* d10v/d10v_sim.h: Don't use PARAMS.
* d10v/gencode.c: Don't use PARAMS.
* d10v/interp.c: Don't use PARAMS.
* d10v/simops.c: Don't use PARAMS.
* erc32/erc32.c: Don't use PARAMS.
* erc32/exec.c: Don't use PARAMS.
* erc32/float.c: Don't use PARAMS.
* erc32/func.c: Don't use PARAMS.
* erc32/sis.c: Don't use PARAMS.
* erc32/sis.h: Don't use PARAMS.
* mips/interp.c: Don't use PARAMS.
* mips/sim-main.h: Don't use PARAMS.
* sh/interp.c: Don't use PARAMS.
* v850/sim-main.h: Don't use PARAMS.
* v850/v850_sim.h: Don't use PARAMS.
I meant for this script to be +x, but missed when doing the initial CVS
commit. It wasn't possible to fix w/CVS, but it is w/git, so do it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-12-03 Mike Frysinger <vapier@gentoo.org>
* run-tests.sh: Add +x file mode.
These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This reverts part of the earlier version.in change. It moves
version.in back to the gdb directory. This works around the CVS bug
we've found.
gdb
* Makefile.in (version.c): Use version.in, not
common/version.in.
* common/create-version.sh: Likewise.
* common/version.in: Move...
* version.in: ...here.
gdb/doc
* Makefile.in (version.subst): Use version.in, not
common/version.in.
* gdbint.texinfo (Versions and Branches, Releasing GDB):
Likewise.
gdb/gdbserver
* Makefile.in (version.c): Use version.in, not
common/version.in.
sim/common
* Make-common.in (version.c): Use version.in, not
common/version.in.
* create-version.sh: Likewise.
sim/ppc:
* Make-common.in (version.c): Use version.in, not
common/version.in.
This change is required now that gdb/version.in has been moved to
gdb/common/version.in and now that the date needs to be fetched
from bfd/version.h.
sim/common/ChangeLog:
* create-version.sh: New script. Adapted from
gdb/commong/create-version.sh.
* Make-common.in (version.c): Update rule dependencies,
and re-implement using create-version.sh.
sim/ppc/ChangeLog:
* Makefile.in (srccom): New variable.
(version.c): Update rule dependencies, and re-implement using
sim/common/create-version.sh.
The SEARCH insn is an oddball when it comes to parallel usage. It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this). Add a note for now in case we get around to it.
For many of the 32bit dsp shift related insns, we were just ignoring the HLs
field. The hardware does not though and will reject the insn if it's set
incorrectly. Update the sim to match.
Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them. Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns. On the
hardware, these are proper invalid insns, and the table catches that.
The main body of the "all insn" test is executed once per tested insn, and
we test millions of insns here. Any shrinkage we can do in this loop will
speed things up nicely (since it's multiplied per tested insn).
To that end, simplify the end-of-table test into one less insn, and omit
the SSYNC when we build for the sim. When we build to run on the hardware,
this insn matters, but the sim doesn't have write store buffers in the chip
that might get in the way (memory writes are atomic).
We wrote a test case that tries every single 32bit opcode on the hardware
and compared it to the sim. There were a bunch of places in the sim where
we weren't strict enough (requiring certain parts of the opcode be set) so
we were treating a lot of invalid opcodes as valid ones. This sprinkles
out a lot additional checks in the dsp32alu class.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Since these insns run in usermode, there should be no need to setup
RET[ENI] to safe values. They won't be dereferenced, and any insn
that returns via them are valid only in supervisor mode. Since this
is in the main exception code path, saving any insn at all is good
as it gets multiplied quickly (as in O(n^2) times).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Since many people don't have a Blackfin toolchain available, only try to
regenerate the header file when in maintainer mode. This file rarely changes,
and when it does, we commit the generated output, so there's almost never a
need to run directly on an end system.
I noticed the sim code is using an old implementation of the maintainer logic.
I cut it over to the new macro (like gdb has been doing). In practice, it
makes no difference currently as nothing in the sim tree uses it, but I have a
follow up commit for the Blackfin tree that needs it.
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com>
This patch adds simulator support for handling the armv7 instructions
'movw (immediate)' and 'movt'.
Compiler frequently use these instructions to load the 32bit addresses of
global variables, string pointers etc. into the general registers.
In absence of support of these instructions:
1. GDB run simulator fails to print even simple "hello world" string
on console.
2. Loading of global variable addresses into the registers fail causing
arithmetic operation failures.
Patch has been regression tested for arm-none-eabi (-march=armv7-a).
These sims have optional support for the dv-sockser model, so do not make
them hard failures. The Makefile made it seem like they didn't actually
support things dynamically, but a further code dive into the source and
the Makefile shows that things work out.
There's no need to put the majority of the logic into the 3rd arg of the
AC_ARG_ENABLE. Coupled with the lack of indentation, it makes it hard to
follow, error prone to update, and duplicates code (with the 4th arg).
So pull the logic out of the 3rd arg and outside of the AC_ARG_ENABLE
macro. This allows us to gut the 4th arg entirely, merge with the code
that followed the macro, and fix bugs related to the new dv-sockser in
the process.
Hopefully building the various sims with the default sim-hardware
settings, as well as with explicit --{dis,en}able-sim-hardware flags,
should all just work now.
Mike Frysinger
Nick Clifton
James Bowman
Andrew Bennett
H.J. Lu
Joel Brobecker
Mike Stump
DJ Delorie
Senthil Kumar Selvaraj
Jiri Gaisler
Hans-Peter Nilsson
Chen Gang
Anthony Green
Oleg Endo
Joel Sherrill
Gary Benson
Alan Modra
Roland McGrath
Michael Eager
David McQuillan
Kevin Buettner
Aaro Koskinen
Tom Tromey
Steve Ellcey
Will Newton
Hans-Peter Nilsson
Sergio Durigan Junior
Joel Brobecker
Hafiz Abid Qadeer