963f35869d
Add clflushopt, xsaves, xsavec, xrstors
...
gas/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
* doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
clflushopt/.clfushopt.
gas/testsuite/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* gas/i386/clflushopt-intel.d: New.
* gas/i386/clflushopt.d: Ditto.
* gas/i386/clflushopt.s: Ditto.
* gas/i386/i386.exp: Run new tests.
* gas/i386/x86-64-clflushopt-intel.d: New.
* gas/i386/x86-64-clflushopt.d: Ditto.
* gas/i386/x86-64-clflushopt.s: Ditto.
* gas/i386/x86-64-xsavec-intel.d: Ditto.
* gas/i386/x86-64-xsavec.d: Ditto.
* gas/i386/x86-64-xsavec.s: Ditto.
* gas/i386/x86-64-xsaves-intel.d: Ditto.
* gas/i386/x86-64-xsaves.d: Ditto.
* gas/i386/x86-64-xsaves.s: Ditto.
* gas/i386/xsavec-intel.d: Ditto.
* gas/i386/xsavec.d: Ditto.
* gas/i386/xsavec.s: Ditto.
* gas/i386/xsaves-intel.d: Ditto.
* gas/i386/xsaves.d: Ditto.
* gas/i386/xsaves.s: Ditto.
opcodes/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
MOD_0FC7_REG_5.
(PREFIX enum): Add PREFIX_0FAE_REG_7.
(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
(prefix_table): Add clflusopt.
(mod_table): Add xrstors, xsavec, xsaves.
* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
* i386-init.h: Regenerate.
* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
xsaves64, xsavec, xsavec64.
* i386-tbl.h: Regenerate.
2014-02-12 07:50:24 -08:00
43234a1e14
Add Intel AVX-512 support
...
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
2013-07-26 17:20:25 +00:00
a004640857
Support Intel SHA
...
gas/
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386.c (cpu_arch): Add .sha.
* doc/c-i386.texi: Document sha/.sha.
gas/testsuite/
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/i386/sha.d: New.
* gas/i386/sha.s: New.
* gas/i386/x86-64-sha.d: New.
* gas/i386/x86-64-sha.s: New.
* gas/i386/i386.exp: Run new SHA tests.
opcodes/
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
PREFIX_0F3ACC.
(prefix_table): Updated.
(three_byte_table): Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
(cpu_flags): Add CpuSHA.
(i386_cpu_flags): Add cpusha.
* i386-init.h: Regenerate.
* i386-opc.h (CpuSHA): New.
(CpuUnused): Restored.
(i386_cpu_flags): Add cpusha.
* i386-opc.tbl: Add SHA instructions.
* i386-tbl.h: Regenerate.
2013-07-25 16:16:35 +00:00
7e8b059be6
Support Intel MPX
...
gas/
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386.c (BND_PREFIX): New.
(struct _i386_insn): Add new field bnd_prefix.
(add_bnd_prefix): New.
(cpu_arch): Add MPX.
(i386_operand_type): Add regbnd.
(md_assemble): Handle BND prefixes.
(parse_insn): Likewise.
(output_branch): Likewise.
(output_jump): Likewise.
(build_modrm_byte): Handle regbnd.
(OPTION_MADD_BND_PREFIX): New.
(md_longopts): Add entry for 'madd-bnd-prefix'.
(md_parse_option): Handle madd-bnd-prefix option.
(md_show_usage): Add description for madd-bnd-prefix
option.
* doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
gas/testsuite/
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/i386/mpx-add-bnd-prefix.s: New.
* gas/i386/mpx-add-bnd-prefix.d: New.
* gas/i386/mpx-inval-1.l: New.
* gas/i386/mpx-inval-1.s: New.
* gas/i386/mpx.d: New.
* gas/i386/mpx.s: New.
* gas/i386/x86-64-mpx-add-bnd-prefix.d: New.
* gas/i386/x86-64-mpx-add-bnd-prefix.s: New.
* gas/i386/x86-64-mpx-addr32.d: New.
* gas/i386/x86-64-mpx-addr32.s: New.
* gas/i386/x86-64-mpx-inval-1.l: New.
* gas/i386/x86-64-mpx-inval-1.s: New.
* gas/i386/x86-64-mpx-inval-2.l: New.
* gas/i386/x86-64-mpx-inval-2.s: New.
* gas/i386/x86-64-mpx.d: New.
* gas/i386/x86-64-mpx.s: New.
* gas/i386/nops.d: Adjust to MPX changes.
* gas/i386/nops.s: Likewise.
* gas/i386/x86-64-nops.d: Likewise.
* gas/i386/x86-64-nops.s: Likewise.
* gas/i386/ilp32/x86-64-nops.d: Likewise.
* gas/i386/i386.exp: Run new MPX tests.
include/opcode/
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386.h (BND_PREFIX_OPCODE): New.
opcodes/
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis.c (BND_Fixup): New.
(Ebnd): New.
(Ev_bnd): New.
(Gbnd): New.
(BND): New.
(v_bnd_mode): New.
(bnd_mode): New.
(MOD enum): Add new entries.
(PREFIX enum): Likewise.
(dis tables): Replace XX with BND for near branch and call
instructions.
(prefix_table): Add new entries.
(mod_table): Likewise.
(names_bnd): New.
(intel_names_bnd): New.
(att_names_bnd): New.
(BND_PREFIX): New.
(prefix_name): Handle BND_PREFIX.
(print_insn): Initialize names_bnd.
(intel_operand_size): Handle new modes.
(OP_E_register): Likewise.
(OP_E_memory): Likewise.
(OP_G): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuMPX.
(cpu_flags): Add CpuMPX.
(operand_type_init): Add RegBND.
(opcode_modifiers): Add BNDPrefixOk.
(operand_types): Add RegBND.
* i386-init.h: Regenerate.
* i386-opc.h (CpuMPX): New.
(CpuUnused): Comment out.
(i386_cpu_flags): Add cpumpx.
(BNDPrefixOk): New.
(i386_opcode_modifier): Add bndprefixok.
(RegBND): New.
(i386_operand_type): Add regbnd.
* i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
Add MPX instructions and bnd prefix.
* i386-reg.tbl: Add bnd0-bnd3 registers.
* i386-tbl.h: Regenerate.
2013-07-24 15:47:25 +00:00
5c111e3769
Implement Intel SMAP instructions
...
gas/
PR gas/15159
* config/tc-i386.c (cpu_arch): Add ".smap".
* doc/c-i386.texi: Document smap.
gas/testsuite/
PR gas/15159
* gas/i386/i386.exp: Run smap and x86-64-smap.
* gas/i386/smap.d: New file.
* gas/i386/smap.s: likewise.
* gas/i386/x86-64-smap.d: likewise.
opcodes/
PR gas/15159
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
(cpu_flags): Add CpuSMAP.
* i386-opc.h (CpuSMAP): New.
(i386_cpu_flags): Add cpusmap.
* i386-opc.tbl: Add clac and stac.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2013-02-19 19:10:31 +00:00
60aa667ec4
Replace CpuSSE3 with CpuCX16 for cmpxchg16b
...
gas/
* config/tc-i386.c (cpu_arch): Add .cx16.
* doc/c-i386.texi: Document .cx16.
gas/testsuite/
* gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b.
* gas/i386/x86-64-arch-2.d: Update correspondingly.
* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
* gas/i386/x86-64-arch-2-btver1.d: Likewise.
* gas/i386/x86-64-arch-2-btver2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
(cpu_flags): Add CpuCX16.
* i386-opc.h (CpuCX16): New.
(i386_cpu_flags): Add cpucx16.
* i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-09-20 11:53:33 +00:00
7b458c12dc
Add AMD btver1 and btver2 support
...
gas/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
(i386_align_code): Add case for PROCESSOR_BT.
* config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
* doc/c-i386.texi: Add -march={btver1, btver2} options.
gas/testsuite/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* gas/i386/i386.exp: Run btver1 and btver2 test cases.
* gas/i386/nops-1-btver1.d: New.
* gas/i386/nops-1-btver2.d: New.
* gas/i386/arch-10-btver1.d: New.
* gas/i386/arch-10-btver2.d: New.
* gas/i386/x86-64-nops-1-btver1.d: New.
* gas/i386/x86-64-nops-1-btver2.d: New.
* gas/i386/x86-64-arch-2-btver1.d: New.
* gas/i386/x86-64-arch-2-btver2.d: New.
opcodes/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
* i386-opc.h: Update CpuPRFCHW comment.
* i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-08-17 17:12:36 +00:00
e2e1fcde62
Implement RDRSEED, ADX and PRFCHW instructions
...
gas/
* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
* doc/c-i386.texi: Document the new directives.
gas/testsuite/
* gas/i386/i386.exp: Run adx, rdseed and prefetchw tests.
* gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10-1.l: Changed correspondingly.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
* gas/i386/arch-10-prefetchw.d: New file.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/rdseed.s: Likewise.
* gas/i386/rdseed.d: Likewise.
* gas/i386/rdseed-intel.d: Likewise.
* gas/i386/adx.s: Likewise.
* gas/i386/adx.d: Likewise.
* gas/i386/adx-intel.d: Likewise.
* gas/i386/x86-64-rdseed.s: Likewise.
* gas/i386/x86-64-rdseed.d: Likewise.
* gas/i386/x86-64-rdseed-intel.d: Likewise.
* gas/i386/x86-64-adx.s: Likewise.
* gas/i386/x86-64-adx.d: Likewise.
* gas/i386/x86-64-adx-intel.d: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F38F6): New.
(prefix_table): Add adcx, adox instructions.
(three_byte_table): Use PREFIX_0F38F6.
(mod_table): Add rdseed instruction.
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
(cpu_flags): Likewise.
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
prefetchw.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-07-16 12:58:29 +00:00
29c048b696
gas/
...
* config/tc-i386.c (parse_insn): Don't complain about REP prefix
when the template has opcode_modifier.repprefixok set.
* NEWS: Mention the change.
gas/testsuite/
* gas/i386/rep-bsf.d: New file.
* gas/i386/rep-bsf.s: New file.
* gas/i386/i386.exp: Add the new test.
opcodes/
* i386-opc.h (RepPrefixOk): New enum constant.
(i386_opcode_modifier): New bitfield 'repprefixok'.
* i386-gen.c (opcode_modifiers): Add RepPrefixOk.
* i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
instructions that have IsString.
* i386-tbl.h: Regenerate.
2012-06-22 16:42:08 +00:00
82c2def5ff
Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixRelease
...
gas/
2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_hle): Use HLEPrefixNone, HLEPrefixLock,
HLEPrefixAny and HLEPrefixRelease.
opcodes/
2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (HLEPrefixNone): New.
(HLEPrefixLock): Likewise.
(HLEPrefixAny): Likewise.
(HLEPrefixRelease): Likewise.
2012-02-21 18:09:48 +00:00
42164a7195
Implement Intel Transactional Synchronization Extensions
...
gas/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (HLE_PREFIX): New.
(check_hle): Likewise.
(_i386_insn): Add have_hle.
(cpu_arch): Add .hle and .rtm.
(md_assemble): Call check_hle if i.have_hle isn't zero.
(parse_insn): Set i.have_hle to 1 for HLE prefix.
(output_jump): Support up to 2 byte opcode.
* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.
gas/testsuite/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/hle-intel.d: New.
* gas/i386/hle.d: Likewise.
* gas/i386/hle.s: Likewise.
* gas/i386/hlebad.l: Likewise.
* gas/i386/hlebad.s: Likewise.
* gas/i386/rtm-intel.d: Likewise.
* gas/i386/rtm.d: Likewise.
* gas/i386/rtm.s: Likewise.
* gas/i386/x86-64-hle-intel.d: Likewise.
* gas/i386/x86-64-hle.d: Likewise.
* gas/i386/x86-64-hle.s: Likewise.
* gas/i386/x86-64-hlebad.l: Likewise.
* gas/i386/x86-64-hlebad.s: Likewise.
* gas/i386/x86-64-rtm-intel.d: Likewise.
* gas/i386/x86-64-rtm.d: Likewise.
* gas/i386/x86-64-rtm.s: Likewise.
* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
x86-64-rtm-intel.
include/opcode/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (XACQUIRE_PREFIX_OPCODE): New.
(XRELEASE_PREFIX_OPCODE): Likewise.
opcodes/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (HLE_Fixup1): New.
(HLE_Fixup2): Likewise.
(HLE_Fixup3): Likewise.
(Ebh1): Likewise.
(Evh1): Likewise.
(Ebh2): Likewise.
(Evh2): Likewise.
(Ebh3): Likewise.
(Evh3): Likewise.
(MOD_C6_REG_7): Likewise.
(MOD_C7_REG_7): Likewise.
(RM_C6_REG_7): Likewise.
(RM_C7_REG_7): Likewise.
(XACQUIRE_PREFIX): Likewise.
(XRELEASE_PREFIX): Likewise.
(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
MOD_C6_REG_7 and MOD_C7_REG_7.
(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
xtest.
(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
CPU_RTM_FLAGS.
(cpu_flags): Add CpuHLE and CpuRTM.
(opcode_modifiers): Add HLEPrefixOk.
* i386-opc.h (CpuHLE): New.
(CpuRTM): Likewise.
(HLEPrefixOk): Likewise.
(i386_cpu_flags): Add cpuhle and cpurtm.
(i386_opcode_modifier): Add hleprefixok.
* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
operand. Add xacquire, xrelease, xabort, xbegin, xend and
xtest.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-02-08 18:20:41 +00:00
8729a6f6a5
Add vmfunc
...
gas/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add ".vmfunc".
* doc/c-i386.texi: Document vmfunc.
gas/testsuite/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc.
* gas/i386/vmfunc.d: New.
* gas/i386/vmfunc.s: Likewise.
* gas/i386/x86-64-vmfunc.d: Likewise.
opcodes/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (mod_table): Add vmfunc.
* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
(cpu_flags): CpuVMFUNC.
* i386-opc.h (CpuVMFUNC): New.
(i386_cpu_flags): Add cpuvmfunc.
* i386-opc.tbl: Add vmfunc.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-01-13 22:19:32 +00:00
7a9068fe16
Add initial Intel K1OM support.
...
bfd/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ALL_MACHINES): Add cpu-k1om.lo.
(ALL_MACHINES_CFILES): Add cpu-k1om.c.
* Makefile.in: Regenerated.
* archures.c (bfd_architecture): Add bfd_arch_k1om.
(bfd_k1om_arch): New.
(bfd_archures_list): Add &bfd_k1om_arch.
* bfd-in2.h: Regenerated.
* config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if
bfd_elf64_x86_64_vec is supported. Add bfd_elf64_k1om_freebsd_vec
if bfd_elf64_x86_64_freebsd_vec is supported.
(targ_selvecs): Likewise.
* configure.in: Support bfd_elf64_k1om_vec and
bfd_elf64_k1om_freebsd_vec.
* configure: Regenerated.
* cpu-k1om.c: New.
* elf64-x86-64.c (elf64_k1om_elf_object_p): New.
(bfd_elf64_k1om_vec): Likewise.
(bfd_elf64_k1om_freebsd_vec): Likewise.
* targets.c (bfd_elf64_k1om_vec): New.
(bfd_elf64_k1om_freebsd_vec): Likewise.
(_bfd_target_vector): Add bfd_elf64_k1om_vec and
bfd_elf64_k1om_freebsd_vec.
binutils/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (init_dwarf_regnames): Handle EM_K1OM.
* elfedit.c (elf_machine): Support EM_K1OM.
(elf_class): Likewise.
* readelf.c (guess_is_rela): Handle EM_K1OM.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(get_section_type_name): Likewise.
(get_elf_section_flags): Likewise.
(process_section_headers): Likewise.
(get_symbol_index_type): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_32bit_pcrel_reloc): Likewise.
(is_64bit_abs_reloc): Likewise.
(is_64bit_pcrel_reloc): Likewise.
(is_none_reloc): Likewise.
* doc/binutils.texi: Mention K1OM for elfedit.
binutils/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* binutils-all/elfedit.exp: Run elfedit-4.
* binutils-all/elfedit-4.d: New.
gas/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add k1om.
(i386_align_code): Handle PROCESSOR_K1OM.
(check_cpu_arch_compatible): Check EM_K1OM.
(i386_arch): Handle Intel K1OM.
(i386_mach): Return bfd_mach_k1om for Intel K1OM.
(i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel
K1OM.
* config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New.
(processor_type): Add PROCESSOR_K1OM.
* doc/c-i386.texi: Document k1om.
gas/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/k1om.d: New.
* gas/i386/k1om-inval.l: Likewise.
* gas/i386/k1om-inval.s: Likewise.
* gas/i386/i386.exp: Run k1om-inval and k1om.
include/elf/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* common.h (EM_K1OM): New.
ld/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and
eelf_k1om_fbsd.o
(eelf_k1om.c): New.
(eelf_k1om_fbsd.c): Likewise.
* Makefile.in: Regenerated.
* configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64
is supported. Add elf_k1om_fbsd if elf_x86_64_fbsd is supported.
(targ_extra_emuls): Likewise.
* emulparams/elf_k1om.sh: New.
* emulparams/elf_k1om_fbsd.sh: Likewise.
ld/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/abs-k1om.d: New.
* ld-x86-64/protected2-k1om.d: Likewise.
* ld-x86-64/protected3-k1om.d: Likewise.
* ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and
protected3-k1om.
opcodes/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* configure.in: Handle bfd_k1om_arch.
* configure: Regenerated.
* disassemble.c (disassembler): Handle bfd_k1om_arch.
* i386-dis.c (print_insn): Handle bfd_mach_k1om and
bfd_mach_k1om_intel_syntax.
* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
(cpu_flags): Add CpuK1OM.
* i386-opc.h (CpuK1OM): New.
(i386_cpu_flags): Add cpuk1om.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-07-22 20:22:38 +00:00
6c30d220f1
Support AVX Programming Reference (June, 2011).
...
gas/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* config/tc-i386.c (i386_error): Add invalid_vsib_address and
unsupported_vector_index_register.
(cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid.
(check_VecOperands): New.
(match_template): Call check_VecOperands. Handle
invalid_vsib_address and unsupported_vector_index_register.
(build_modrm_byte): Support VecSIB. Check register-only source
operand when two source operands are swapped.
(i386_index_check): Allow Xmm/Ymm index registers.
* doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt
and invpcid./invpcid.
gas/testsuite/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/arch-10-1.l: Updated.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Add LZCNT to comments.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10-lzcnt.d: New.
* gas/i386/avx-gather-intel.d: Likewise.
* gas/i386/avx-gather.d: Likewise.
* gas/i386/avx-gather.s: Likewise.
* gas/i386/avx2-intel.d: Likewise.
* gas/i386/avx2.d: Likewise.
* gas/i386/avx2.s: Likewise
* gas/i386/avx256int-intel.d: Likewise.
* gas/i386/avx256int.d: Likewise.
* gas/i386/avx256int.s: Likewise.
* gas/i386/bmi2-intel.d: Likewise.
* gas/i386/bmi2.d: Likewise.
* gas/i386/bmi2.s: Likewise.
* gas/i386/inval-invpcid.l:Likewise.
* gas/i386/inval-invpcid.s: Likewise.
* gas/i386/invpcid-intel.d: Likewise.
* gas/i386/invpcid.d: Likewise.
* gas/i386/invpcid.s: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-avx-gather-intel.d: Likewise.
* gas/i386/x86-64-avx-gather.d: Likewise.
* gas/i386/x86-64-avx-gather.s: Likewise.
* gas/i386/x86-64-avx2-intel.d: Likewise.
* gas/i386/x86-64-avx2.d: Likewise.
* gas/i386/x86-64-avx2.s: Likewise.
* gas/i386/x86-64-avx256int-intel.d: Likewise.
* gas/i386/x86-64-avx256int.d: Likewise.
* gas/i386/x86-64-avx256int.s: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/x86-64-inval-invpcid.l: Likewise.
* gas/i386/x86-64-inval-invpcid.s: Likewise.
* gas/i386/x86-64-invpcid-intel.d: Likewise.
* gas/i386/x86-64-invpcid.d: Likewise.
* gas/i386/x86-64-invpcid.s: Likewise.
opcodes/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (XMGatherQ): New.
* i386-dis.c (EXxmm_mb): New.
(EXxmm_mb): Likewise.
(EXxmm_mw): Likewise.
(EXxmm_md): Likewise.
(EXxmm_mq): Likewise.
(EXxmmdw): Likewise.
(EXxmmqd): Likewise.
(VexGatherQ): Likewise.
(MVexVSIBDWpX): Likewise.
(MVexVSIBQWpX): Likewise.
(xmm_mb_mode): Likewise.
(xmm_mw_mode): Likewise.
(xmm_md_mode): Likewise.
(xmm_mq_mode): Likewise.
(xmmdw_mode): Likewise.
(xmmqd_mode): Likewise.
(ymmxmm_mode): Likewise.
(vex_vsib_d_w_dq_mode): Likewise.
(vex_vsib_q_w_dq_mode): Likewise.
(MOD_VEX_0F385A_PREFIX_2): Likewise.
(MOD_VEX_0F388C_PREFIX_2): Likewise.
(MOD_VEX_0F388E_PREFIX_2): Likewise.
(PREFIX_0F3882): Likewise.
(PREFIX_VEX_0F3816): Likewise.
(PREFIX_VEX_0F3836): Likewise.
(PREFIX_VEX_0F3845): Likewise.
(PREFIX_VEX_0F3846): Likewise.
(PREFIX_VEX_0F3847): Likewise.
(PREFIX_VEX_0F3858): Likewise.
(PREFIX_VEX_0F3859): Likewise.
(PREFIX_VEX_0F385A): Likewise.
(PREFIX_VEX_0F3878): Likewise.
(PREFIX_VEX_0F3879): Likewise.
(PREFIX_VEX_0F388C): Likewise.
(PREFIX_VEX_0F388E): Likewise.
(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
(PREFIX_VEX_0F38F5): Likewise.
(PREFIX_VEX_0F38F6): Likewise.
(PREFIX_VEX_0F3A00): Likewise.
(PREFIX_VEX_0F3A01): Likewise.
(PREFIX_VEX_0F3A02): Likewise.
(PREFIX_VEX_0F3A38): Likewise.
(PREFIX_VEX_0F3A39): Likewise.
(PREFIX_VEX_0F3A46): Likewise.
(PREFIX_VEX_0F3AF0): Likewise.
(VEX_LEN_0F3816_P_2): Likewise.
(VEX_LEN_0F3819_P_2): Likewise.
(VEX_LEN_0F3836_P_2): Likewise.
(VEX_LEN_0F385A_P_2_M_0): Likewise.
(VEX_LEN_0F38F5_P_0): Likewise.
(VEX_LEN_0F38F5_P_1): Likewise.
(VEX_LEN_0F38F5_P_3): Likewise.
(VEX_LEN_0F38F6_P_3): Likewise.
(VEX_LEN_0F38F7_P_1): Likewise.
(VEX_LEN_0F38F7_P_2): Likewise.
(VEX_LEN_0F38F7_P_3): Likewise.
(VEX_LEN_0F3A00_P_2): Likewise.
(VEX_LEN_0F3A01_P_2): Likewise.
(VEX_LEN_0F3A38_P_2): Likewise.
(VEX_LEN_0F3A39_P_2): Likewise.
(VEX_LEN_0F3A46_P_2): Likewise.
(VEX_LEN_0F3AF0_P_3): Likewise.
(VEX_W_0F3816_P_2): Likewise.
(VEX_W_0F3818_P_2): Likewise.
(VEX_W_0F3819_P_2): Likewise.
(VEX_W_0F3836_P_2): Likewise.
(VEX_W_0F3846_P_2): Likewise.
(VEX_W_0F3858_P_2): Likewise.
(VEX_W_0F3859_P_2): Likewise.
(VEX_W_0F385A_P_2_M_0): Likewise.
(VEX_W_0F3878_P_2): Likewise.
(VEX_W_0F3879_P_2): Likewise.
(VEX_W_0F3A00_P_2): Likewise.
(VEX_W_0F3A01_P_2): Likewise.
(VEX_W_0F3A02_P_2): Likewise.
(VEX_W_0F3A38_P_2): Likewise.
(VEX_W_0F3A39_P_2): Likewise.
(VEX_W_0F3A46_P_2): Likewise.
(MOD_VEX_0F3818_PREFIX_2): Removed.
(MOD_VEX_0F3819_PREFIX_2): Likewise.
(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
(VEX_LEN_0F3A0E_P_2): Likewise.
(VEX_LEN_0F3A0F_P_2): Likewise.
(VEX_LEN_0F3A42_P_2): Likewise.
(VEX_LEN_0F3A4C_P_2): Likewise.
(VEX_W_0F3818_P_2_M_0): Likewise.
(VEX_W_0F3819_P_2_M_0): Likewise.
(prefix_table): Updated.
(three_byte_table): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(vex_w_table): Likewise.
(mod_table): Likewise.
(putop): Handle "LW".
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
(OP_EX): Likewise.
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
vex_vsib_q_w_dq_mode.
(OP_XMM): Handle vex_vsib_q_w_dq_mode.
(OP_VEX): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
(opcode_modifiers): Add VecSIB.
* i386-opc.h (CpuAVX2): New.
(CpuBMI2): Likewise.
(CpuLZCNT): Likewise.
(CpuINVPCID): Likewise.
(VecSIB128): Likewise.
(VecSIB256): Likewise.
(VecSIB): Likewise.
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
(i386_opcode_modifier): Add vecsib.
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-06-10 21:27:40 +00:00
2a2a0f38e7
Add support for TBM instructions.
...
gas/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
* doc/c-i386.texi (i386-TBM): New section.
opcodes/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
gas/testsuite
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* gas/i386/tbm.s: New.
* gas/i386/tbm.d: New.
* gas/i386/tbm-intel.d: New.
* gas/i386/x86-64-tbm.s: New.
* gas/i386/x86-64-tbm.d: New.
* gas/i386/x86-64-tbm-intel.d: New.
* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
* gas/i386/arch-10.s: Add a TBM instruction.
* gas/i386/arch-10-1.l: Add TBM instruction pattern.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
2011-01-17 18:40:36 +00:00
f12dc42220
Implement BMI instructions.
2011-01-05 00:16:57 +00:00
56ffb74112
Add CheckRegSize to instructions which require register size check.
...
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check checkregsize
instead of w for register size check.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run inval-reg.
* gas/i386/inval-reg.l: New.
* gas/i386/inval-reg.s: Likewise.
opcodes/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add CheckRegSize.
* i386-opc.h (CheckRegSize): New.
(i386_opcode_modifier): Add checkregsize.
* i386-opc.tbl: Add CheckRegSize to instructions which
require register size check.
* i386-tbl.h: Regenerated.
2010-10-14 18:45:10 +00:00
2210942396
Don't generate multi-byte NOPs for i686.
...
gas/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (arch_entry): Add negated bit to
disambiguate flag names starting with "no".
(cpu_arch): Add negated bit definitions. Add
".nop" CPU extension.
(i386_align_code): Use new .cpunop bit to decide
when to generate alignment using nops.
(set_cpu_arch): Use negated bit instead to decide
when to use cpu_flags or vs. cpu_flags_and_not.
(md_parse_option): Likewise.
gas/testsuite/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* gas/i386/arch-10-1.l: Add nopl instruction.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10.d: Add nopl instruction, and +nopl extension
flag to as flags.
* gas/i386/nops-5-i686.d: Change alignment code generated for
-mtune=i686.
* gas/i386/nops-5.d: Change alignment code generated for
.arch i686.
* gas/i386/x86-64-nops-5-k8.d: Likewise.
* gas/i386/x86-64-nops-5.d: Likewise.
opcodes/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
to processor flags for PENTIUMPRO processors and later.
* i386-opc.h (enum): Add CpuNop.
(i386_cpu_flags): Add cpunop bit.
* i386-opc.tbl: Change nop cpu_flags.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2010-08-06 18:22:50 +00:00
b49dfb4a38
Fix typos in comments in i386-opc.h.
...
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* i386-opc.h (enum): Fix typos in comments.
2010-08-06 16:33:43 +00:00
77321f5360
Fix a typo in comments for CpuFSGSBase.
...
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
2010-07-05 16:40:32 +00:00
c7b8aa3a72
Support AVX Programming Reference (June, 2010)
...
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-01 21:55:02 +00:00
c75ef631bd
Update copyright.
...
gas/
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c: Update copyright.
opcodes/
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c: Update copyright.
* i386-gen.c: Likewise.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
2010-02-11 13:41:19 +00:00
a683cc34e4
2010-02-10 Quentin Neill <quentin.neill@amd.com>
...
Sebastian Pop <sebastian.pop@amd.com>
gas:
* config/tc-i386.c (vec_imm4) New operand type.
(fits_in_imm4): New.
(VEX_check_operands): New.
(check_reverse): Call VEX_check_operands.
(build_modrm_byte): Reintroduce code for 5
operand insns. Fix whitespace.
gas/testsuite:
* gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
* gas/i386/x86-64-xop.s: Likewise.
* gas/i386/xop.d: Likewise.
* gas/i386/xop.s: Likewise.
opcodes:
* i386-dis.c (OP_EX_VexImmW): Reintroduced
function to handle 5th imm8 operand.
(PREFIX_VEX_3A48): Added.
(PREFIX_VEX_3A49): Added.
(VEX_W_3A48_P_2): Added.
(VEX_W_3A49_P_2): Added.
(prefix table): Added entries for PREFIX_VEX_3A48
and PREFIX_VEX_3A49.
(vex table): Added entries for VEX_W_3A48_P_2 and
and VEX_W_3A49_P_2.
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
for Vec_Imm4 operands.
* i386-opc.h (enum): Added Vec_Imm4.
(i386_operand_type): Added vec_imm4.
* i386-opc.tbl: Add entries for vpermilp[ds].
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2010-02-11 05:06:14 +00:00
712366da0a
Replace "Vex" with "Vex=3" on AVX scalar instructions.
...
2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEXScalar): New.
* i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
instructions.
* i386-tbl.h: Regenerated.
2010-01-24 00:59:13 +00:00
a2a7d12cfc
Replace VEX.DNS with VEX.NDS in comments.
...
2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
comments.
2010-01-14 19:35:36 +00:00
2426c15ff8
Replace VexNDS, VexNDD and VexLWP with VexVVVV.
...
gas/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexvvvv instead
of vexnds and vexndd.
(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
and vexlwp.
opcodes/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
VexLWP. Add VexVVVV.
* i386-opc.h (VexNDS): Removed.
(VexNDD): Likewise.
(VexLWP): Likewise.
(VEXXDS): New.
(VEXNDD): Likewise.
(VEXLWP): Likewise.
(VexVVVV): Likewise.
(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
Add vexvvvv.
* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
VexVVVV=2 and VexLWP with VexVVVV=3.
* i386-tbl.h: Regenerated.
2009-12-19 18:36:27 +00:00
2eb952a4d9
Remove ByteOkIntel.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
Intel syntax if size is ignored and b/l/w suffixes are
illegal.
(check_byte_reg): Remove byteokintel check.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove ByteOkIntel.
* i386-opc.h (ByteOkIntel): Removed.
(i386_opcode_modifier): Remove byteokintel.
* i386-opc.tbl: Remove ByteOkIntel.
* i386-tbl.h: Regenerated.
2009-12-16 20:08:32 +00:00
7f399153c6
Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38,
vex0f3a, xop08, xop09 and xop0a with vexopcode.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38,
Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode.
* i386-opc.h (Vex0F): Removed.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(VexOpcode): New.
(VEX0F): Likewise.
(VEX0F38): Likewise.
(VEX0F3A): Likewise.
(XOP08): Defined as a macro.
(XOP09): Likewise.
(XOP0A): Likewise.
(i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08,
xop09 and xop0a. Add vexopcode.
* i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3,
XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5.
* i386-tbl.h: Regenerated.
2009-12-16 15:43:16 +00:00
8c43a48b28
Replace VEX2SOURCES with XOP2SOURCES.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES
instead VEX2SOURCES.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEX2SOURCES): Renamed to ...
(XOP2SOURCES): This.
2009-12-16 05:18:11 +00:00
8cd7925b45
Replace Vex2Sources and Vex3Sources with VexSources.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexsources
instead of vex3sources.
(build_modrm_byte): Check vexsources instead of vex2sources
and vex3sources.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex3Sources and
Vex2Sources. Add VexSources.
* i386-opc.h ()Vex2Sources: Removed.
(Vex3Sources): Likewise.
(VEX2SOURCES): New.
(VEX3SOURCES): Likewise.
(VexSources): Likewise.
(i386_opcode_modifier): Remove vex2sources and vex3sources.
Add vexsources.
* i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
Vex3Sourceswith VexSources=2.
* i386-tbl.h: Regenerated.
2009-12-16 04:00:35 +00:00
1ef99a7be9
Remove VexW0 and VexW1. Add VexW.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1
with vexw.
(build_modrm_byte): Likewise.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add
VexW.
* i386-opc.h (VexW0): Removed.
(VexW1): Likewise.
(VEXW0): New.
(VEXW1): Likewise.
(VexW): Likewise.
(i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw.
* i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with
Vex=2.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-12-16 02:10:45 +00:00
e3c58833bf
Define VEX128 and VEX256.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Use VEX256.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEX128): New.
(VEX256): Likewise.
2009-12-15 16:36:59 +00:00
f0ae4a24b0
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
...
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 20:28:59 +00:00
5dd85c9970
2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
(build_vex_prefix): Handle xop08.
(md_assemble): Don't special case the constant 3 for insns using MODRM.
(build_modrm_byte): Handle vex2sources.
(md_show_usage): Add xop and cvt16.
* doc/c-i386.texi: Document fma4, xop, and cvt16.
gas/testsuite/
* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
* gas/i386/lwp.d: Update name of the testcase.
* gas/i386/x86-64-xop.d: New.
* gas/i386/x86-64-xop.s: New.
* gas/i386/xop.d: New.
* gas/i386/xop.s: New.
* gas/i386/cvt16.d: New.
* gas/i386/cvt16.s: New.
opcodes/
* i386-dis.c (OP_Vex_2src_1): New.
(OP_Vex_2src_2): New.
(Vex_2src_1): New.
(Vex_2src_2): New.
(XOP_08): Added.
(VEX_LEN_XOP_08_A0): Added.
(VEX_LEN_XOP_08_A1): Added.
(VEX_LEN_XOP_09_80): Added.
(VEX_LEN_XOP_09_81): Added.
(xop_table): Added an entry for XOP_08. Handle xop instructions.
(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
(get_valid_dis386): Handle XOP_08.
(OP_Vex_2src): New.
* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
(cpu_flags): Add CpuXOP and CpuCVT16.
(opcode_modifiers): Add XOP08, Vex2Sources.
* i386-opc.h (CpuXOP): Added.
(CpuCVT16): Added.
(i386_cpu_flags): Add cpuxop and cpucvt16.
(XOP08): Added.
(Vex2Sources): Added.
(i386_opcode_modifier): Add xop08, vex2sources.
* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 04:04:17 +00:00
c32fa91d70
gas/
...
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (LOCKREP_PREFIX): Removed.
(REP_PREFIX): New.
(LOCK_PREFIX): Likewise.
(PREFIX_GROUP): Likewise.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(add_prefix): Updated. Return enum PREFIX_GROUP.
(md_assemble): Check for lock without a lockable instruction.
(parse_insn): Updated.
(output_insn): Likewise.
gas/testsuite/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.
* gas/i386/lock-1-intel.d: New.
* gas/i386/lock-1.d: Likewise.
* gas/i386/lock-1.s: Likewise.
* gas/i386/lockbad-1.l: Likewise.
* gas/i386/lockbad-1.s: Likewise.
* gas/i386/x86-64-lock-1-intel.d: Likewise.
* gas/i386/x86-64-lock-1.d: Likewise.
* gas/i386/x86-64-lock-1.s: Likewise.
* gas/i386/x86-64-lockbad-1.l: Likewise.
* gas/i386/x86-64-lockbad-1.s: Likewise.
opcodes/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IsLockable.
* i386-opc.h (IsLockable): New.
(i386_opcode_modifier): Add islockable.
* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
xor, xadd and xchg.
* i386-tbl.h: Regenerated.
2009-11-12 18:57:14 +00:00
f88c9eb030
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
2009-11-05 23:40:05 +00:00
52a6c1fedd
2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.h: Use enum instead of nested macros.
2009-10-16 15:50:52 +00:00
2bf05e5730
gas/
...
2009-09-24 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Check vex == 2 instead
of vex256.
opcodes/
2009-09-24 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex256.
(set_bitfield): Handle XXX=V.
* i386-opc.h (Vex): Update comments.
(Vex256): Removed.
(VexNDS): Updated.
(i386_opcode_modifier): Change vex to 2 bits. Remove vex256.
* i386-opc.tbl: Replace "Vex|Vex256" with Vex=2.
* i386-tbl.h: Regenerated.
2009-09-24 16:37:09 +00:00
d3ce72d070
Updated sources to avoid using the identifier name "new", which is a
...
keyword in c++.
* bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable
new to new_symbol.
* bfd/coffgen.c (coff_make_empty_symbol)
(coff_bfd_make_debug_symbol): Rename variable new to new_symbol.
* bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable
new to new_insn.
* bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to
new_d.
* bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new
to new_symbol.
* bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument
new to new_reloc.
* bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string.
* bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to
new_symbol.
* bfd/linker.c (bfd_new_link_order): Rename variable new to
new_lo.
* bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to
symbol.
* bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to
new_symbol_type.
* bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable
new to new_symbol_type.
* bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new
to new_symbol.
* bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to
new_dump.
(read_hdr, rs6000coff_core_p)
(rs6000coff_core_file_matches_executable_p)
(rs6000coff_core_file_failing_command)
(rs6000coff_core_file_failing_signal): Updated function to use new
union member name.
* bfd/som.c (som_make_empty_symbol): Rename variable new to
new_symbol_type.
* bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new
to new_symbol.
* bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename
variable new to new_symbol.
* binutils/nlmconv.c (main): Rename variable new to new_name.
* gas/config/tc-arm.c (insert_reg_alias): Rename variable new to
new_reg.
* gas/config/tc-dlx.c (parse_operand): Rename variable new to
new_pos.
* gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable
new to newr.
* gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable
new to new_pointer.
* gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got):
Change name from new to new_pointer.
* gas/config/tc-or32.c (parse_operand): Rename variable new to
new_pointer.
* gas/config/tc-pdp11.c (md_assemble): Rename variable new to
new_pointer.
* gas/config/tc-pj.c (alias): Change argument new to new_name.
* gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable
new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable
new to new_i2n. (s3_convert): Rename variables old and new to
r_old and r_new.
* gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable
new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable
new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename
variables old and new to r_old and r_new.
* gas/config/tc-sh.c (parse_exp): Rename variable new to
new_pointer.
* gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to
new_pointer.
* gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new
to new_pointer.
* gas/config/tc-z8k.c (parse_exp): Rename variable new to
new_pointer.
* gas/listing.c (listing_newline): Rename variable new to new_i.
* ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop)
(exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new
to new_e.
* ld/ldfile.c (ldfile_add_library_path): Rename variable new to
new_dirs. (ldfile_add_arch): Rename variable new to new_arch.
* ld/ldlang.c (new_statement, lang_final, lang_add_wild)
(lang_target, lang_add_fill, lang_add_data, lang_add_assignment)
(lang_add_insert): Rename variable new to new_stmt. (new_afile):
Added missing cast. (lang_memory_region_lookup): Rename variable
new to new_region. (init_os): Rename variable new to
new_userdata. (lang_add_section): Rename variable new to
new_section. (ldlang_add_undef): Rename variable new to
new_undef. (realsymbol): Rename variable new to new_name.
* opcodes/z8kgen.c (internal, gas): Rename variable new to new_op.
Updated sources to avoid using the identifier name "template",
which is a keyword in c++.
* bfd/elf32-arm.c (struct stub_def): Rename member template to
template_sequence. (arm_build_one_stub,
find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub):
Rename variable template to template_sequence.
* bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl):
Rename variable template to template_val.
* gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct
asm_barrier_opt): Change member template to
template_name. (md_begin): Update code to reflect new member
names.
* gas/config/tc-i386.c (struct templates, struct _i386_insn)
(match_template, cpu_flags_match, match_reg_size, match_mem_size)
(operand_size_match, md_begin, i386_print_statistics, pi)
(build_vex_prefix, md_assemble, parse_insn, optimize_imm)
(optimize_disp): Updated code to use new names. (parse_insn):
Added casts.
* gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated
code to use new names.
* gas/config/tc-score.c (struct s3_asm_opcode): Renamed member
template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst,
s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to
use new names.
* gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member
template to template_name. (s7_parse_16_32_inst,
s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to
use new names.
* gas/config/tc-tic30.c (md_begin, struct tic30_insn)
(md_assemble): Update code to use new names.
* gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin)
(optimize_insn, tic54x_parse_insn, next_line_shows_parallel):
Update code to use new names.
* include/opcode/tic30.h (template): Rename type template to
insn_template. Updated code to use new name.
* include/opcode/tic54x.h (template): Rename type template to
insn_template.
* opcodes/cris-dis.c (bytes_to_skip): Update code to use new name.
* opcodes/i386-dis.c (putop): Update code to use new name.
* opcodes/i386-gen.c (process_i386_opcodes): Update code to use
new name.
* opcodes/i386-opc.h (struct template): Rename struct template to
insn_template. Update code accordingly.
* opcodes/i386-tbl.h (i386_optab): Update type to use new name.
* opcodes/ia64-dis.c (print_insn_ia64): Rename variable template
to template_val.
* opcodes/tic30-dis.c (struct instruction, get_tic30_instruction):
Update code to use new name.
* opcodes/tic54x-dis.c (has_lkaddr, get_insn_size)
(print_parallel_instruction, print_insn_tic54x, tic54x_get_insn):
Update code to use new name.
* opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab):
Update type to new name.
2009-08-29 22:11:02 +00:00
8a9036a406
bfd/
...
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* archures.c (bfd_architecture): Add bfd_arch_l1om.
(bfd_l1om_arch): New.
(bfd_archures_list): Add &bfd_l1om_arch.
* bfd-in2.h: Regenerated.
* config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if
bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec
if bfd_elf64_x86_64_freebsd_vec is supported.
(targ_selvecs): Likewise.
* configure.in: Support bfd_elf64_l1om_vec and
bfd_elf64_l1om_freebsd_vec.
* configure: Regenerated.
* cpu-l1om.c: New.
* elf64-x86-64.c (elf64_l1om_elf_object_p): New.
(bfd_elf64_l1om_vec): Likewise.
(bfd_elf64_l1om_freebsd_vec): Likewise.
* Makefile.am (ALL_MACHINES): Add cpu-l1om.lo.
(ALL_MACHINES_CFILES): Add cpu-l1om.c.
* Makefile.in: Regenerated.
* targets.c (bfd_elf64_l1om_vec): New.
(bfd_elf64_l1om_freebsd_vec): Likewise.
(_bfd_target_vector): Add bfd_elf64_l1om_vec and
bfd_elf64_l1om_freebsd_vec.
binutils/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* readelf.c (guess_is_rela): Handle EM_L1OM.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(get_section_type_name): Likewise.
(get_elf_section_flags): Likewise.
(get_symbol_index_type): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_32bit_pcrel_reloc): Likewise.
(is_64bit_abs_reloc): Likewise.
(is_64bit_pcrel_reloc): Likewise.
(is_none_reloc): Likewise.
gas/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add l1om.
(check_cpu_arch_compatible): New.
(set_cpu_arch): Use it.
(i386_arch): New.
(i386_mach): Return bfd_mach_l1om for Intel L1OM.
(md_show_usage): Display l1om.
(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
cpu_arch_isa_flags.bitfield.cpul1om is set.
* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
(i386_arch): New.
(ELF_TARGET_L1OM_FORMAT): Likewise.
* doc/c-i386.texi: Document l1om.
gas/testsuite/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/l1om.d: New.
* gas/i386/l1om-inval.l: Likewise.
* gas/i386/l1om-inval.s: Likewise.
* gas/i386/i386.exp: Run l1om-inval and l1om.
include/elf/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* common.h (EM_L1OM): New.
ld/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64
is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported.
(targ_extra_emuls): Likewise.
* Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and
eelf_l1om_fbsd.o
(eelf_l1om.c): New.
(eelf_l1om_fbsd.c): Likewise.
* Makefile.in: Regenerated.
* emulparams/elf_l1om.sh: New.
* emulparams/elf_l1om_fbsd.sh: Likewise.
ld/testsuite/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/abs-l1om.d: New.
* ld-x86-64/protected2-l1om.d: Likewise.
* ld-x86-64/protected3-l1om.d: Likewise.
* ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and
protected3-l1om.
opcodes/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* configure.in: Handle bfd_l1om_arch.
* disassemble.c (disassembler): Likewise.
* configure: Regenerated.
* i386-dis.c (print_insn): Handle bfd_mach_l1om and
bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM.
* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM.
Add CPU_L1OM_FLAGS.
(cpu_flags): Add CpuL1OM.
(set_bitfield): Take an argument to set the value field.
(process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY).
(process_i386_opcode_modifier): Updated.
(process_i386_operand_type): Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
* i386-opc.h (CpuL1OM): New.
(CpuXsave): Updated.
(i386_cpu_flags): Add cpul1om.
2009-07-25 14:58:58 +00:00
309d33736f
gas/
...
2009-07-24 Jan Beulich <jbeulich@novell.com>
* tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx,
.nosse, and .noavx.
(cpu_flags_and_not): New.
(set_cpu_arch): Check whether sub-architecture specified is a
feature disable.
(md_parse_option): Likewise.
(parse_real_register): Don't return floating point register
when x87 functionality is disabled.
(md_show_usage): Add new sub-options.
* doc/c-i386.texi: Update with new command line sub-options.
gas/testsuite/
2009-07-24 Jan Beulich <jbeulich@novell.com>
* gas/i386/8087.[ds]: New.
* gas/i386/287.[ds]: New.
* gas/i386/387.[ds]: New.
* gas/i386/no87.[ls]: New.
* gas/i386/no87-2.[ls]: New.
* gas/i386/i386.exp: Run new tests.
* gas/i386/att-regs.s: Also check FPU register access.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Adjust expectations.
* gas/i386/intel-regs.d: Likewise.
opcodes/
2009-07-24 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add
frstpm.
* i386-gen.c (cpu_flag_init): Add FP enabling flags where needed.
(cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP.
(set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387.
* i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP):
Define.
(union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687,
and cpufisttp.
* i386-opc.tbl: Qualify floating point instructions by their
respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos,
and fsincos to be avilable only on 387. Fix fstsw ax to be
available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm,
and frstpm.
* i386-init.h, i386-tbl.h: Regenerate.
2009-07-24 15:41:20 +00:00
922d8de8c1
<gas changes>
...
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
(build_modrm_byte): Add support to handle FMA4 instructions.
(md_show_usage): Add fma4.
<gas/testsuite changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Add FMA4 tests.
* gas/i386/x86-64-fma4.d: Ditto.
* gas/i386/fma4.d: Ditto.
* gas/i386/x86-64-fma4.s: Ditto.
* gas/i386/fma4.s: Ditto.
<opcodes changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (CpuFMA4): Add CpuFMA4.
(i386_cpu_flags): New.
* i386-gen.c: Add CPU_FMA4_FLAGS.
* i386-opc.tbl: Add FMA4 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
(OP_XMM_VexW): Ditto.
(OP_EX_VexW): Ditto.
(VEXI4_Fixup): Ditto.
(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
(get_vex_imm8): New. handle FMA4.
(OP_EX_VexReg): Ditto.
2009-07-06 19:34:30 +00:00
c1e679ec0a
<gas changes>
...
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (process_drex): Delete. Remove SSE5 support.
(build_modrm_byte): Remove DREX handling support.
(DREX_*): Delete.
(drex_byte): Delete.
(md_assemble): Remove DREX handling support.
(process_operands): Remove DREX, SSE5 support.
(i386_insn): Remove DREX.
<gas/testsuite changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Remove SSE5 tests.
* gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests.
* gas/i386/x86-64-sse5.d: Ditto.
* gas/i386/arch-10-1.l: Remove SSE5 tests.
* gas/i386/arch-10-2.l: Ditto.
* gas/i386/arch-10-3.l: Ditto.
* gas/i386/arch-10-4.l: Ditto.
* gas/i386/arch-10.d: Ditto.
* gas/i386/arch-10.s: Ditto.
* gas/i386/arch-4.s: Delete. Remove SSE5 tests.
* gas/i386/arch-4.d: Ditto.
* gas/i386/arch-8.s: Ditto.
* gas/i386/arch-8.d: Ditto.
* gas/i386/arch-2.s: Remove SSE5 tests.
* gas/i386/arch-2.d: Remove SSE5 tests.
* gas/i386/x86-64-arch-2.s: Ditto.
<opcodes changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (Cpusse5): Delete.
(i386_cpu_flags): Delete.
* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
* i386-opc.tbl: Remove SSE5 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
(print_drex_arg): Delete.
(OP_DREX4): Delete.
(OP_DREX3): Delete.
(OP_DREX_ICMP): Delete.
(OP_DREX_FCMP): Delete.
(DREX_*): Delete.
(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
2009-05-22 15:57:25 +00:00
4c664d7bf7
gas/
...
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (vex_imm4): Removed.
(VEX_check_operands): Likewise.
(match_template): Updated.
opcodes/
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
(operand_types): Remove Vex_Imm4.
* i386-opc.h (Vex_Imm4): Removed.
(OTMax): Updated.
(i386_operand_type): Remove vex_imm4.
* i386-opc.tbl: Remove Vex_Imm4 comments.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-02-23 20:41:46 +00:00
bd5295b282
gas/
...
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-10 17:25:52 +00:00
1b7f3fb0dd
gas/
...
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .rdtscp.
(md_show_usage): Display rdtscp.
* doc/c-i386.texi: Document rdtscp.
gas/testsuite/
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add rdtscp.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS.
(cpu_flags): Add CpuRdtscp.
(set_bitfield): Remove CpuSledgehammer check.
* i386-opc.h (CpuRdtscp): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpurdtscp.
* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-09 20:32:32 +00:00
0bfee64967
gas/
...
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* config/tc-i386.c (build_modrm_byte): Remove 5 operand instruction
support. Don't swap REG and NDS for FMA.
gas/testsuite/
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* gas/i386/arch-10.s: Replace vfmaddpd with vfmadd132pd.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/avx.s: Remove vpermil2ps/vpermil2pd and FMA
instructions. Update tests.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/fma.d: New.
* gas/i386/fma.s: Likewise.
* gas/i386/fma-intel.d: Likewise.
* gas/i386/x86-64-fma.d: Likewise.
* gas/i386/x86-64-fma.s: Likewise.
* gas/i386/x86-64-fma-intel.d: Likewise.
* gas/i386/i386.exp: Run fma, fma-intel, x86-64-fma and
x86-64-fma-intel.
opcodes/
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* i386-dis.c (OP_VEX_FMA): Removed.
(OP_EX_VexW): Likewise.
(OP_EX_VexImmW): Likewise.
(OP_XMM_VexW): Likewise.
(VEXI4_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(VexI4): Likewise.
(VexFMA): Likewise.
(Vex128FMA): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(EXVexImmW): Likewise.
(XMVexW): Likewise.
(VPERMIL2): Likewise.
(PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise.
(PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise.
(PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise.
(PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise.
(VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise.
(VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise.
(get_vex_imm8): Likewise.
(OP_EX_VexReg): Likewise.
vpermil2_op): Likewise.
(EXVexWdq): New.
(vex_w_dq_mode): Likewise.
(PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise.
(PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise.
(PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise.
(es_reg): Updated.
(PREFIX_VEX_38DB): Likewise.
(PREFIX_VEX_3A4A): Likewise.
(PREFIX_VEX_3A60): Likewise.
(PREFIX_VEX_3ADF): Likewise.
(VEX_LEN_3ADF_P_2): Likewise.
(prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A,
PREFIX_VEX_3A5C...PREFIX_VEX_3A5F,
PREFIX_VEX_3A68...PREFIX_VEX_3A6F and
PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add
PREFIX_VEX_3896...PREFIX_VEX_389F,
PREFIX_VEX_38A6...PREFIX_VEX_38AF and
PREFIX_VEX_38B6...PREFIX_VEX_38BF.
(vex_table): Likewise.
(vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2
and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2.
(putop): Support "%XW".
(intel_operand_size): Handle vex_w_dq_mode.
* i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS.
* i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA
instructions. Add new FMA instructions.
* i386-tbl.h: Regenerated.
2009-01-06 01:03:27 +00:00
fa99fab222
gas/
...
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Changed to return
const template *. Handle i.swap_operand for 3 operands.
(build_vex_prefix): Take const template *. Swap operand for
2-byte VEX prefix if possible.
(md_assemble): Updated.
(build_modrm_byte): Handle RegMem bit for SSE2AVX.
gas/testsuite/
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.
* gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
vmovss.
* gas/i386/x86-64-opts.s: Likewise.
* gas/i386/opts.d: Updated.
* gas/i386/opts-intel.d: Likewise.
* gas/i386/sse2avx-opts.d: Likewise.
* gas/i386/sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.d: Likewise.
* gas/i386/x86-64-opts-intel.d: Likewise.
* gas/i386/x86-64-sse2avx-opts.d: Likewise.
* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-avx-swap.d: New.
* gas/i386/x86-64-avx-swap.s: Likewise.
* gas/i386/x86-64-avx-swap-intel.d: Likewise.
opcodes/
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EXdS): New.
(EXdVexS): Likewise.
(EXqVexS): Likewise.
(d_swap_mode): Likewise.
(q_mode): Updated.
(prefix_table): Use EXdS on movss and EXqS on movsd.
(vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
(intel_operand_size): Handle d_swap_mode.
(OP_EX): Likewise.
* i386-opc.h (S): Update comments.
* i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
* i386-tbl.h: Regenerated.
2008-12-23 15:14:15 +00:00
b6169b206a
gas/
...
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add swap_operand.
(parse_insn): Handle ".s".
(match_template): Handle swap_operand.
* doc/c-i386.texi: Document .s suffix.
gas/testsuite/
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.
* gas/i386/opts.d: New.
* gas/i386/opts-intel.d: Likewise.
* gas/i386/opts.s: Likewise.
* gas/i386/sse2avx-opts.d: Likewise.
* gas/i386/sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.d: Likewise.
* gas/i386/x86-64-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.s: Likewise.
* gas/i386/x86-64-sse2avx-opts.d: Likewise.
* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
opcodes/
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EbS): New.
(EvS): Likewise.
(EMS): Likewise.
(EXqS): Likewise.
(EXxS): Likewise.
(b_swap_mode): Likewise.
(v_swap_mode): Likewise.
(q_swap_mode): Likewise.
(x_swap_mode): Likewise.
(v_mode): Updated.
(w_mode): Likewise.
(t_mode): Likewise.
(xmm_mode): Likewise.
(swap_operand): Likewise.
(dis386): Use EbS on movB. Use EvS on moveS.
(dis386_twobyte): Use EXxS on movapX.
(prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
(vex_table): Use EXxS on vmovapX.
(vex_len_table): Use EXqS on vmovq.
(intel_operand_size): Handle b_swap_mode, v_swap_mode,
q_swap_mode and x_swap_mode.
(OP_E_register): Handle b_swap_mode and v_swap_mode.
(OP_EM): Handle v_swap_mode.
(OP_EX): x_swap_mode and q_swap_mode.
* i386-gen.c (opcode_modifiers): Add S.
* i386-opc.h (S): New.
(Modrm): Updated.
(i386_opcode_modifier): Add s.
* i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
* i386-tbl.h: Regenerated.
2008-12-20 17:40:51 +00:00
f1f8f695c0
gas/
...
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE, EPT and MOVBE.
* config/tc-i386.c (cpu_arch): Add .movbe and .ept.
(md_show_usage): Add .movbe and .ept.
* doc/c-i386.texi: Add movbe and ept to -march=. Document
.movbe and .ept.
gas/testsuite/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
x86-64-inval-ept.
* gas/i386/arch-10.s: Add movbe and invept.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/ept.d: New file
* gas/i386/ept-intel.d: Likewise.
* gas/i386/ept.s: Likewise.
* gas/i386/inval-ept.l: Likewise.
* gas/i386/inval-ept.s: Likewise.
* gas/i386/inval-movbe.l: Likewise.
* gas/i386/inval-movbe.s: Likewise.
* gas/i386/movbe.d: Likewise.
* gas/i386/movbe-intel.d: Likewise.
* gas/i386/movbe.s: Likewise.
* gas/i386/x86-64-inval-ept.l: Likewise.
* gas/i386/x86-64-inval-ept.s: Likewise.
* gas/i386/x86-64-inval-movbe.l: Likewise.
* gas/i386/x86-64-inval-movbe.s: Likewise.
* gas/i386/x86-64-ept.d: Likewise.
* gas/i386/x86-64-ept-intel.d: Likewise.
* gas/i386/x86-64-ept.s: Likewise.
* gas/i386/x86-64-movbe.d: Likewise.
* gas/i386/x86-64-movbe-intel.d: Likewise.
* gas/i386/x86-64-movbe.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOVBE_Fixup): New.
(Mo): Likewise.
(PREFIX_0F3880): Likewise.
(PREFIX_0F3881): Likewise.
(PREFIX_0F38F0): Updated.
(prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
(three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
* i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
CPU_EPT_FLAGS.
(cpu_flags): Add CpuMovbe and CpuEPT.
* i386-opc.h (CpuMovbe): New.
(CpuEPT): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Add cpumovbe and cpuept.
* i386-opc.tbl: Add entries for movbe and EPT instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-05-02 16:53:40 +00:00
81f8a9131a
gas/
...
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Don't check SSE instructions
if noavx is 0.
opcodes/
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add NoAVX.
* i386-opc.h (NoAVX): New.
(OldGcc): Updated.
(i386_opcode_modifier): Add noavx.
* i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
instructions which don't have AVX equivalent.
* i386-tbl.h: Regenerated.
2008-04-22 22:27:13 +00:00
594ab6a333
gas/
...
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
2008-04-04 16:34:23 +00:00
c0f3af977b
binutils/
...
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:21 +00:00
b7240065b3
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (parse_real_register): Don't return 'FLAT'
if not in Intel mode.
(i386_intel_operand): Ignore segment overrides in immediate and
offset operands.
(intel_e11): Range-check i.mem_operands before use as array
index. Filter out FLAT for uses other than as segment override.
(intel_get_token): Remove broken promotion of "FLAT:" to mean
"offset FLAT:".
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.s: Replace invalid offset expression with
valid ones.
* gas/i386/x86_64.s: Likewise.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-opc.h (RegFlat): New.
* i386-reg.tbl (flat): Add.
* i386-tbl.h: Re-generate.
2008-02-13 13:41:26 +00:00
a60de03c61
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (allow_pseudo_reg): New.
(parse_real_register): Check for NULL just once. Allow all
register table entries when allow_pseudo_reg is non-zero.
Don't allow any registers without type when allow_pseudo_reg
is zero.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
(tc_x86_frame_initial_instructions): Adjust for above change.
* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
(tc_parse_to_dw2regnum): New.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
error handling.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/cfi/cfi-i386.s: Add code testing use of all registers.
Fix a few comments.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-gen.c (process_i386_registers): Process new fields.
* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
unsigned char. Add dw2_regnum and Dw2Inval.
* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
register names.
* i386-tbl.h: Re-generate.
2008-02-13 10:14:40 +00:00
475a2301db
gas/testsuite/
...
2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
and x86-64-xsave-intel.
* gas/i386/x86-64-xsave-intel.d: New file.
* gas/i386/x86-64-xsave.d: Likewise.
* gas/i386/x86-64-xsave.s: Likewise.
* gas/i386/xsave-intel.d: Likewise.
* gas/i386/xsave.d: Likewise.
* gas/i386/xsave.s: Likewise.
opcodes/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flags): Add CpuXsave.
* i386-opc.h (CpuXsave): New.
(Cpu64): Updated.
(i386_cpu_flags): Add cpuxsave.
* i386-dis.c (MOD_0FAE_REG_4): New.
(RM_0F01_REG_2): Likewise.
(MOD_0FAE_REG_5): Updated.
(RM_0F01_REG_3): Likewise.
(reg_table): Use MOD_0FAE_REG_4.
(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
for xrstor.
(rm_table): Add RM_0F01_REG_2.
* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-02-12 00:04:45 +00:00
115c7c25fe
gas/
...
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_target_format): Remove cpummx2.
gas/testsuite/
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: New.
* gas/i386/arch-11.s: Likewise.
* gas/i386/arch-12.d: Likewise.
* gas/i386/arch-12.s: Likewise.
* gas/i386/i386.exp: Run arch-11 and arch-12.
opcodes/
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
(cpu_flags): Likewise.
* i386-opc.h (CpuMMX2): Removed.
(CpuSSE): Updated.
* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-22 19:57:30 +00:00
5c07affcae
gas/
...
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_reg_size): New.
(match_mem_size): Likewise.
(operand_size_match): Likewise.
(operand_type_match): Also clear all size fields.
(match_template): Skip Intel syntax when in AT&T syntax.
Call operand_size_match to check operand size.
(i386_att_operand): Set the mem field to 1 for memory
operand.
(i386_intel_operand): Likewise.
gas/testsuite/
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add tests for movsx, movzx and movnti.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/x86-64-inval.s: Likewise.
* gas/i386/i386.d: Updated.
* gas/i386/inval.l: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IntelSyntax.
(operand_types): Add Mem.
* i386-opc.h (IntelSyntax): New.
* i386-opc.h (Mem): New.
(Byte): Updated.
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Add intelsyntax.
(i386_operand_type): Add mem.
* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
instructions.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-15 01:37:56 +00:00
0d6a2f58b8
2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.h (Byte): Fix a typo.
2008-01-14 05:15:06 +00:00
7d5e4556a3
gas/testsuite/
...
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/i386.s: Add tests for fnstsw and fstsw.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/intel.s: Use word instead of dword on ss.
* gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
and out.
* gas/i386/prefix.s: Remove invalid fstsw.
* gas/i386/inval.l: Updated.
* gas/i386/intelbad.l: Likewise.
* gas/i386/i386.d: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/prefix.d: Updated.
gas/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (_i386_insn): Update comment.
(operand_type_match): Also clear unspecified.
(operand_type_register_match): Likewise.
(parse_operands): Initialize unspecified.
(i386_intel_operand): Likewise.
(match_template): Check memory and accumulator operand size.
(i386_att_operand): Clear unspecified on register operand.
(intel_e11): Likewise.
(intel_e09): Set operand size and clean unspecified for
"XXX PTR".
opcodes/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (operand_type_init): Add Dword to
OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
Qword and Xmmword.
(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
Xmmword, Unspecified and Anysize.
(set_bitfield): Make Mmword an alias of Qword. Make Oword
an alias of Xmmword.
* i386-opc.h (CheckSize): Removed.
(Byte): Updated.
(Word): Likewise.
(Dword): Likewise.
(Qword): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(OTMax): Likewise.
(i386_opcode_modifier): Remove checksize, byte, word, dword,
qword and xmmword.
(Fword): New.
(TBYTE): Likewise.
(Unspecified): Likewise.
(Anysize): Likewise.
(i386_operand_type): Add byte, word, dword, fword, qword,
tbyte xmmword, unspecified and anysize.
* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
Tbyte, Xmmword, Unspecified and Anysize.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-12 16:05:42 +00:00
e1d4d8936f
gas/
...
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.
* config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
only.
(md_assemble): Remove Intel mode workaround.
(match_template): Check support for old gcc, AT&T mnemonic
and Intel Syntax.
(md_parse_option): Don't set intel_mnemonic to 0 for
OPTION_MOLD_GCC.
gas/testsuite/
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp,
fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp.
* gas/i386/intel.d: Updated.
* gas/i386/intel.e: Likewise.
opcodes/
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
ATTSyntax.
* i386-opc.h (IntelMnemonic): Renamed to ..
(ATTSyntax): This
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
and intelsyntax.
* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
* i386-tbl.h: Regenerated.
2008-01-05 17:07:25 +00:00
6f143e4d77
2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-gen.c: Update copyright to 2008.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-04 18:10:08 +00:00
3629bb00a8
gas/
...
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
(cpu_flags_not): Likewise.
(cpu_flags_match): Updated to check 64bit and arch.
(set_code_flag): Remove cpu_arch_flags_not.
(set_16bit_gcc_code_flag): Likewise.
(set_cpu_arch): Likewise.
(md_begin): Likewise.
(parse_insn): Call cpu_flags_match to check 64bit and arch.
(match_template): Likewise.
gas/testsuite/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-9.d: New file.
* gas/i386/arch-9.s: Likewise.
* gas/i386/i386.exp: Run arch-9.
opcodes/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
CpuSSE4_2_Or_ABM.
(cpu_flags): Likewise.
* i386-opc.h (CpuSSE4_1_Or_5): Removed.
(CpuSSE4_2_Or_ABM): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
and CpuPadLock, respectively.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-04 01:05:45 +00:00
24995bd6e3
gas/
...
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Use the xmmword field
instead of no_xsuf.
opcodes/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove No_xSuf.
* i386-opc.h (No_xSuf): Removed.
(CheckSize): Updated.
* i386-tbl.h: Regenerated.
2008-01-03 20:09:38 +00:00
e0329a2266
gas/testsuite/
...
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-5.d: New file.
* gas/i386/arch-5.s: Likewise.
* gas/i386/arch-6.d: Likewise.
* gas/i386/arch-6.s: Likewise.
* gas/i386/arch-7.d: Likewise.
* gas/i386/arch-7.s: Likewise.
* gas/i386/arch-8.d: Likewise.
* gas/i386/arch-8.s: Likewise.
* gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.
opcodes/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
CPU_SSE5_FLAGS.
(cpu_flags): Add CpuSSE4_2_Or_ABM.
* i386-opc.h (CpuSSE4_2_Or_ABM): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpusse4_2_or_abm.
* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
CpuABM|CpuSSE4_2 on popcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-03 05:29:53 +00:00
f2a9c676b7
gas/testsuite/
...
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add tests for movq.
* gas/i386/x86_64.s: Likewise.
* gas/i386/i386.d Updated.
* gas/i386/x86_64.d: Likewise.
opcodes/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h: Update comments.
2008-01-03 03:28:35 +00:00
d978b5be20
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
2008-01-02 23:54:47 +00:00
582d5eddfe
gas/
...
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
Check memory size in Intel mode.
(process_suffix): Handle XMMWORD_MNEM_SUFFIX.
(intel_e09): Likewise.
* config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
gas/testsuite/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/intel.s: Use QWORD on movq instead of DWORD.
* gas/i386/inval.s: Add tests for movq.
* gas/i386/x86-64-inval.s: Likewise.
* gas/i386/inval.l: Updated.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
Byte, Word, Dword, QWord and Xmmword.
* i386-opc.h (No_xSuf): New.
(CheckSize): Likewise.
(Byte): Likewise.
(Word): Likewise.
(Dword): Likewise.
(QWord): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
Dword, QWord and Xmmword.
* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
used.
* i386-tbl.h: Regenerated.
2008-01-02 21:43:34 +00:00
8d79a8c8d5
gas/testsuite/
...
2007-12-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-1.d: New file.
* gas/i386/arch-1.s: Likewise.
* gas/i386/arch-2.d: Likewise.
* gas/i386/arch-2.s: Likewise.
* gas/i386/arch-3.d: Likewise.
* gas/i386/arch-3.s: Likewise.
* gas/i386/arch-4.d: Likewise.
* gas/i386/arch-4.s: Likewise.
* gas/i386/i386.exp: Run arch-1, arch-2, arch-3 and arch-4.
opcodes/
2007-12-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuSSE4_1_Or_5 to
CPU_SSE4_1_FLAGS, CPU_SSE4_2_FLAGS and CPU_SSE5_FLAGS.
(cpu_flags): Add CpuSSE4_1_Or_5.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
* i386-opc.h (CpuSSE4_1_Or_5): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpusse4_1_or_5.
* i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1|CpuSSE5
on ptest roundpd, roundps, roundsd and roundss.
2007-12-28 16:04:41 +00:00
1efbbeb461
gas/
...
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (set_intel_mnemonic): New.
(intel_mnemonic): Likewise.
(old_gcc): Likewise.
(OPTION_MMNEMONIC): Likewise.
(OPTION_MSYNTAX): Likewise.
(OPTION_MINDEX_REG): Likewise.
(OPTION_MNAKED_REG): Likewise.
(OPTION_MOLD_GCC): Likewise.
(md_pseudo_table): Add .intel_mnemonic and .att_mnemonic.
(match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T
mnemonic is specified. Don't allow old gcc support if old_gcc
is 0.
(md_longopts): Add -mmnemonic, -msyntax, -mindex-reg,
-mmnaked-reg and -mold-gcc.
(md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX,
OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC.
* doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg
and AT&T mnemonic vs. Intel mnemonic.
gas/testsuite/
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler.
* gas/i386/compat.d: Likewise.
* gas/i386/i386.exp: Pass -mmnemonic=att to assembler for
"float". Pass -mold-gcc to assembler for "general".
opcodes/
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and
IntelMnemonic.
* i386-opc.h (OldGcc): New.
(ATTMnemonic): Likewise.
(IntelMnemonic): Likewise.
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Add oldgcc, attmnemonic and
intelmnemonic.
* i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul,
fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and
IntelMnemonic.
* i386-tbl.h: Regeneratd.
2007-12-24 05:27:39 +00:00
7ce189b305
gas/
...
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Replace no_xsuf with
no_ldsuf.
(match_template): Likewise.
opcodes/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Replace No_xSuf with
No_ldSuf.
* i386-opc.tbl: Likewise.
* i386-opc.h (No_xSuf): Renamed to ...
(No_ldSuf): This.
(FWait): Updated.
2007-11-01 19:06:54 +00:00
ca61edf2ff
gas/
...
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Check addrprefixop0 to
see if the address size override prefix changes the size of the
first operand.
(check_byte_reg): Don't warn if byteokintel is set.
(check_long_reg): Set i.suffix to QWORD_MNEM_SUFFIX if toqword
is set.
(check_qword_reg): Set i.suffix to LONG_MNEM_SUFFIX if todword
is set.
gas/testsuite/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.d: New.
* gas/i386/i386.s: Likewise.
* gas/i386/i386.exp: Run i386.
* gas/i386/x86_64.s: Add tests for movsx, movsbl, movsbq,
movsbw, movswl, movswq, movzx, movzb, movzbl, movzbq,
movzbw, movzwl and movzwq.
* gas/i386/x86_64.d: Updated.
opcodes/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword,
ToQword and AddrPrefixOp0.
* i386-opc.h (ByteOkIntel): New.
(ToDword): Likewise.
(ToQword): Likewise.
(AddrPrefixOp0): Likewise.
(IsPrefix): Updated.
(i386_opcode_modifier): Add byteokintel, todword, toqword
and addrprefixop0.
* i386-opc.tbl (cvtss2si): Add ToQword.
(cvttss2si): Likewise.
(cvtsd2si): Add ToDword.
(cvttsd2si): Likewise.
(monitor): Add AddrPrefixOp0.
(invlpga): Likewise.
(vmload): Likewise.
(vmrun): Likewise.
(vmsave): Likewise.
(pextrb): Add ByteOkIntel.
(pinsrb): Likewise.
* i386-tbl.h: Regenerated.
2007-11-01 16:27:08 +00:00
e2ec9d29b7
gas/
...
2007-10-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check the firstxmm0
field in opcode_modifier for instruction with a implicit
xmm0 as the first operand.
opcodes/
2007-10-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add FirstXmm0.
* i386-opc.h (FirstXmm0): New.
(IsPrefix): Updated.
(i386_opcode_modifier): Add firstxmm0.
* i386-opc.tbl (blendvpd): Replace RegKludge with FirstXmm0.
(blendvps): Likewise.
(pblendvb): Likewise.
* i386-tbl.h: Regenerated.
2007-10-12 21:40:38 +00:00
47dd174cba
gas/testsuite/
...
2007-10-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run smx.
* gas/i386/smx.d: New.
* gas/i386/smx.s: Likewise.
opcodes/
2007-10-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Add getsec.
* i386-gen.c (cpu_flags): Add CpuSMX.
* i386-opc.h (CpuSMX): New.
(CpuSSSE3): Updated.
(i386_cpu_flags): Add cpusmx.
* i386-opc.tbl: Add getsec.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2007-10-05 19:04:06 +00:00
9a04903eea
gas/
...
2007-09-26 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (build_modrm_byte): Also check for RegEip
when considering IP-relative addressing.
gas/testsuite/
2007-09-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/reloc64.s: Adjust for %eip-relative addressing no
longer generating errors.
* gas/i386/reloc64.d, gas/i386/reloc64.l: Update.
* gas/i386/x86-64-addr32.s: Remove explicit addr32 prefix
for %eip-realtive addressing case.
opcodes/
2007-09-26 Jan Beulich <jbeulich@novell.com>
* i386-opc.h (RegEip): Define.
(RegEiz): Adjust.
* i386-reg.tbl: Add eip. Mark rip and eip with RegRex64.
* i386-tbl.h: Re-generate.
2007-09-26 13:40:59 +00:00
4dffcebc10
gas/
...
2007-09-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (output_insn): Use i.tm.opcode_length to
check opcode length.
opcodes/
2007-09-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (process_i386_opcodes): Process opcode_length.
* i386-opc.h (template): Add opcode_length.
* 386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
2007-09-26 04:42:47 +00:00
a967d2b76a
2007-09-21 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.h: Adjust whitespaces.
2007-09-21 20:51:33 +00:00
db51cc60e2
gas/
...
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Removed.
(set_allow_index_reg): New.
(allow_index_reg): Likewise.
(md_pseudo_table): Add "allow_index_reg" and
"disallow_index_reg".
(build_modrm_byte): Set i.sib.index to NO_INDEX_REGISTER for
fake index registers.
(i386_scale): Updated.
(i386_index_check): Support fake index registers.
(parse_real_register): Return NULL on eiz/riz if fake index
registers aren't allowed.
gas/testsuite/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* gas/i386/i386.exp: Run sib-intel, x86-64-sib and
x86-64-sib-intel.
* gas/i386/nops-1-i386-i686.d: Updated.
* gas/i386/nops-1-i386.d: Likewise.
* gas/i386/nops-1.d: Likewise.
* gas/i386/nops-2-i386.d: Likewise.
* gas/i386/nops-2-merom.d: Likewise.
* gas/i386/nops-2.d: Likewise.
* gas/i386/nops-3-i386.d: Likewise.
* gas/i386/nops-3.d : Likewise.
* gas/i386/sib.d: Likewise.
* gas/i386/sib.s: Use %eiz in testcases.
* gas/i386/sib-intel.d: New.
* gas/i386/x86-64-sib-intel.d: Likewise.
* gas/i386/x86-64-sib.d: Likewise.
* gas/i386/x86-64-sib.s: Likewise.
ld/testsuite/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* ld-i386/tlsbin.dd: Updated.
* ld-i386/tlsld1.dd: Likewise.
opcodes/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* 386-dis.c (index64): New.
(index32): Likewise.
(intel_index64): Likewise.
(intel_index32): Likewise.
(att_index64): Likewise.
(att_index32): Likewise.
(print_insn): Set index64 and index32.
(OP_E_extended): Use index64/index32 for index register for
SIB with INDEX == 4.
* i386-opc.h (RegEiz): New.
(RegRiz): Likewise.
* i386-reg.tbl: Add eiz and riz.
* i386-tbl.h: Regenerated.
2007-09-20 17:38:38 +00:00
20e192ab8d
gas/
...
2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (baseindex): Removed.
(build_modrm_byte): Check reg_num for RIP register instead of
reg_type.
(i386_index_check): Likewise.
opcodes/
2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (RegRip): New.
* i386-reg.tbl (rip): Use RegRip for reg_num.
* i386-tbl.h: Regenerated.
2007-09-18 00:56:54 +00:00
85f10a010c
Add AMD SSE5 support
2007-09-14 18:21:09 +00:00
8c6c980951
2007-09-12 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.h (CpuUnused): Defined with CpuMax.
(OTUnused): Defined with OTMax.
2007-09-12 18:55:31 +00:00
40fb982012
gas/
...
2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.in (AC_CHECK_HEADERS): Add limits.h.
* configure: Regenerated.
* config.in: Likewise.
* config/tc-i386.c: Include "opcodes/i386-init.h".
(_i386_insn): Use i386_operand_type for types.
(cpu_arch_flags): Updated to new types with bitfield.
(cpu_arch_tune_flags): Likewise.
(cpu_arch_isa_flags): Likewise.
(cpu_arch): Likewise.
(i386_align_code): Likewise.
(set_code_flag): Likewise.
(set_16bit_gcc_code_flag): Likewise.
(set_cpu_arch): Likewise.
(md_assemble): Likewise.
(parse_insn): Likewise.
(process_operands): Likewise.
(output_branch): Likewise.
(output_jump): Likewise.
(parse_real_register): Likewise.
(mode_from_disp_size): Likewise.
(smallest_imm_type): Likewise.
(pi): Likewise.
(type_names): Likewise.
(pt): Likewise.
(pte): Likewise.
(swap_2_operands): Likewise.
(optimize_imm): Likewise.
(optimize_disp): Likewise.
(match_template): Likewise.
(check_string): Likewise.
(process_suffix): Likewise.
(check_byte_reg): Likewise.
(check_long_reg): Likewise.
(check_qword_reg): Likewise.
(check_word_reg): Likewise.
(finalize_imm): Likewise.
(build_modrm_byte): Likewise.
(output_insn): Likewise.
(disp_size): Likewise.
(imm_size): Likewise.
(output_disp): Likewise.
(output_imm): Likewise.
(gotrel): Likewise.
(i386_immediate): Likewise.
(i386_displacement): Likewise.
(i386_index_check): Likewise.
(i386_operand): Likewise.
(parse_real_register): Likewise.
(i386_intel_operand): Likewise.
(intel_e09): Likewise.
(intel_bracket_expr): Likewise.
(intel_e11): Likewise.
(cpu_arch_flags_not): New.
(cpu_flags_check_x64): Likewise.
(cpu_flags_all_zero): Likewise.
(cpu_flags_not): Likewise.
(i386_cpu_flags_biop): Likewise.
(cpu_flags_biop): Likewise.
(cpu_flags_match); Likewise.
(acc32): New.
(acc64): Likewise.
(control): Likewise.
(reg16_inoutportreg): Likewise.
(disp16): Likewise.
(disp32): Likewise.
(disp32s): Likewise.
(disp16_32): Likewise.
(anydisp): Likewise.
(baseindex): Likewise.
(regxmm): Likewise.
(imm8): Likewise.
(imm8s): Likewise.
(imm16): Likewise.
(imm32): Likewise.
(imm32s): Likewise.
(imm64): Likewise.
(imm16_32): Likewise.
(imm16_32s): Likewise.
(imm16_32_32s): Likewise.
(operand_type): Likewise.
(operand_type_check): Likewise.
(operand_type_match): Likewise.
(operand_type_register_match): Likewise.
(update_imm): Likewise.
(set_code_flag): Also update cpu_arch_flags_not.
(set_16bit_gcc_code_flag): Likewise.
(md_begin): Likewise.
(parse_insn): Use cpu_flags_check_x64 to check 64bit support.
Use cpu_flags_match to match instructions.
(i386_target_format): Update cpu_arch_isa_flags and
cpu_arch_tune_flags to i386_cpu_flags type with bitfield.
(smallest_imm_type): Check cpu_arch_tune to tune for i486.
(match_template): Don't initialize overlap0, overlap1,
overlap2, overlap3 and operand_types.
(process_suffix): Handle crc32 with 64bit register.
(MATCH): Removed.
(CONSISTENT_REGISTER_MATCH): Likewise.
* config/tc-i386.h (arch_entry): Updated to i386_cpu_flags
type.
opcodes/
2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.in (AC_CHECK_HEADERS): Add limits.h.
* configure: Regenerated.
* config.in: Likewise.
* i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and
<string.h>. Use xstrerror instead of strerror.
(initializer): New.
(cpu_flag_init): Likewise.
(bitfield): Likewise.
(BITFIELD): New.
(cpu_flags): Likewise.
(opcode_modifiers): Likewise.
(operand_types): Likewise.
(compare): Likewise.
(set_cpu_flags): Likewise.
(output_cpu_flags): Likewise.
(process_i386_cpu_flags): Likewise.
(output_opcode_modifier): Likewise.
(process_i386_opcode_modifier): Likewise.
(output_operand_type): Likewise.
(process_i386_operand_type): Likewise.
(set_bitfield): Likewise.
(operand_type_init): Likewise.
(process_i386_initializers): Likewise.
(process_i386_opcodes): Call process_i386_opcode_modifier to
process opcode_modifier. Call process_i386_operand_type to
process operand_types.
(process_i386_registers): Call process_i386_operand_type to
process reg_type.
(main): Check unused bits in i386_cpu_flags and i386_operand_type.
Sort cpu_flags, opcode_modifiers and operand_types. Call
process_i386_initializers.
* i386-init.h: New.
* i386-tbl.h: Regenerated.
* i386-opc.h: Include <limits.h>.
(CHAR_BIT): Define as 8 if not defined.
(Cpu186): Changed to position of bitfiled.
(Cpu286): Likewise.
(Cpu386): Likewise.
(Cpu486): Likewise.
(Cpu586): Likewise.
(Cpu686): Likewise.
(CpuP4): Likewise.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuMMX): Likewise.
(CpuMMX2): Likewise.
(CpuSSE): Likewise.
(CpuSSE2): Likewise.
(Cpu3dnow): Likewise.
(Cpu3dnowA): Likewise.
(CpuSSE3): Likewise.
(CpuPadLock): Likewise.
(CpuSVME): Likewise.
(CpuVMX): Likewise.
(CpuSSSE3): Likewise.
(CpuSSE4a): Likewise.
(CpuABM): Likewise.
(CpuSSE4_1): Likewise.
(CpuSSE4_2): Likewise.
(Cpu64): Likewise.
(CpuNo64): Likewise.
(D): Likewise.
(W): Likewise.
(Modrm): Likewise.
(ShortForm): Likewise.
(Jump): Likewise.
(JumpDword): Likewise.
(JumpByte): Likewise.
(JumpInterSegment): Likewise.
(FloatMF): Likewise.
(FloatR): Likewise.
(FloatD): Likewise.
(Size16): Likewise.
(Size32): Likewise.
(Size64): Likewise.
(IgnoreSize): Likewise.
(DefaultSize): Likewise.
(No_bSuf): Likewise.
(No_wSuf): Likewise.
(No_lSuf): Likewise.
(No_sSuf): Likewise.
(No_qSuf): Likewise.
(No_xSuf): Likewise.
(FWait): Likewise.
(IsString): Likewise.
(RegKludge): Likewise.
(IsPrefix): Likewise.
(ImmExt): Likewise.
(NoRex64): Likewise.
(Rex64): Likewise.
(Ugh): Likewise.
(Reg8): Likewise.
(Reg16): Likewise.
(Reg32): Likewise.
(Reg64): Likewise.
(FloatReg): Likewise.
(RegMMX): Likewise.
(RegXMM): Likewise.
(Imm8): Likewise.
(Imm8S): Likewise.
(Imm16): Likewise.
(Imm32): Likewise.
(Imm32S): Likewise.
(Imm64): Likewise.
(Imm1): Likewise.
(BaseIndex): Likewise.
(Disp8): Likewise.
(Disp16): Likewise.
(Disp32): Likewise.
(Disp32S): Likewise.
(Disp64): Likewise.
(InOutPortReg): Likewise.
(ShiftCount): Likewise.
(Control): Likewise.
(Debug): Likewise.
(Test): Likewise.
(SReg2): Likewise.
(SReg3): Likewise.
(Acc): Likewise.
(FloatAcc): Likewise.
(JumpAbsolute): Likewise.
(EsSeg): Likewise.
(RegMem): Likewise.
(OTMax): Likewise.
(Reg): Commented out.
(WordReg): Likewise.
(ImplicitRegister): Likewise.
(Imm): Likewise.
(EncImm): Likewise.
(Disp): Likewise.
(AnyMem): Likewise.
(LLongMem): Likewise.
(LongMem): Likewise.
(ShortMem): Likewise.
(WordMem): Likewise.
(ByteMem): Likewise.
(CpuMax): New
(CpuLM): Likewise.
(CpuNumOfUints): Likewise.
(CpuNumOfBits): Likewise.
(CpuUnused): Likewise.
(OTNumOfUints): Likewise.
(OTNumOfBits): Likewise.
(OTUnused): Likewise.
(i386_cpu_flags): New type.
(i386_operand_type): Likewise.
(i386_opcode_modifier): Likewise.
(CpuSledgehammer): Removed.
(CpuSSE4): Likewise.
(CpuUnknownFlags): Likewise.
(Reg): Likewise.
(WordReg): Likewise.
(ImplicitRegister): Likewise.
(Imm): Likewise.
(EncImm): Likewise.
(Disp): Likewise.
(AnyMem): Likewise.
(LLongMem): Likewise.
(LongMem): Likewise.
(ShortMem): Likewise.
(WordMem): Likewise.
(ByteMem): Likewise.
(template): Use i386_cpu_flags for cpu_flags, use
i386_opcode_modifier for opcode_modifier, use
i386_operand_type for operand_types.
(reg_entry): Use i386_operand_type for reg_type.
* Makefile.am (HFILES): Add i386-init.h.
($(srcdir)/i386-init.h): New rule.
($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h
instead.
* Makefile.in: Regenerated.
2007-09-09 01:22:57 +00:00
9b201bb5e5
Change source files over to GPLv3.
2007-07-05 09:49:03 +00:00
5f15756d11
gas/
...
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Replace regKludge
with RegKludge.
opcodes/
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (regKludge): Renamed to ...
(RegKludge): This.
* i386-opc.c (i386_optab): Replace regKludge with RegKludge.
2007-06-25 21:20:20 +00:00
4d67a4d303
2007-05-10 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.h (ShortForm): Redefined.
(Jump): Likewise.
(JumpDword): Likewise.
(JumpByte): Likewise.
(JumpInterSegment): Likewise.
(FloatMF): Likewise.
(FloatR): Likewise.
(FloatD): Likewise.
(Size16): Likewise.
(Size32): Likewise.
(Size64): Likewise.
(IgnoreSize): Likewise.
(DefaultSize): Likewise.
(No_bSuf): Likewise.
(No_wSuf): Likewise.
(No_lSuf): Likewise.
(No_sSuf): Likewise.
(No_qSuf): Likewise.
(No_xSuf): Likewise.
(FWait): Likewise.
(IsString): Likewise.
(regKludge): Likewise.
(IsPrefix): Likewise.
(ImmExt): Likewise.
(NoRex64): Likewise.
(Rex64): Likewise.
(Ugh): Likewise.
2007-05-10 18:21:13 +00:00
db55703487
gas/
...
* expr.c (expr): Assert on rankarg, not rank which can be unsigned.
* read.c (read_a_source_file): Remove buffer_limit[-1] assertion.
Don't skip over NUL char.
(pseudo_set): Set X_op for registers to O_register.
* symbols.c (symbol_clone): Remove assertion that sym is defined.
(resolve_symbol_value): Resolve O_register symbols.
* config/tc-i386.c (parse_real_register): Don't use i386_float_regtab.
Instead find st(0) by hash lookup.
* config/tc-ppc.c (ppc_macro): Warning fix.
opcodes/
* i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete.
Move contents to..
(i386_regtab): ..here.
* i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
2007-04-21 06:54:57 +00:00
381d071fc5
gas/
...
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
(match_template): Handle operand size for crc32 in SSE4.2.
(process_suffix): Handle operand type for crc32 in SSE4.2.
(output_insn): Support SSE4.2.
gas/testsuite/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2.
* gas/i386/sse4_2.d: New file.
* gas/i386/sse4_2.s: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
* gas/i386/x86-64-sse4_2.s: Likewise.
opcodes/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CRC32_Fixup): New.
(PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
PREGRP91): New.
(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
(three_byte_table): Likewise.
* i386-opc.c (i386_optab): Add SSE4.2 opcodes.
* gas/config/tc-i386.h (CpuSSE4_2): New.
(CpuSSE4): Likewise.
(CpuUnknownFlags): Add CpuSSE4_2.
2007-04-18 16:15:55 +00:00
42903f7f59
gas/
...
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4.1.
(process_operands): Adjust implicit operand for blendvpd,
blendvps and pblendvb in SSE4.1.
(output_insn): Support SSE4.1.
gas/testsuite/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.
* gas/i386/sse4_1.d: New file.
* gas/i386/sse4_1.s: Likewise.
* gas/i386/x86-64-sse4_1.d: Likewise.
* gas/i386/x86-64-sse4_1.s: Likewise.
opcodes/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (XMM_Fixup): New.
(Edqb): New.
(Edqd): New.
(XMM0): New.
(dqb_mode): New.
(dqd_mode): New.
(PREGRP39 ... PREGRP85): New.
(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(prefix_user_table): Add PREGRP39 ... PREGRP85.
(three_byte_table): Likewise.
(putop): Handle 'K'.
(intel_operand_size): Handle dqb_mode, dqd_mode):
(OP_E): Likewise.
(OP_G): Likewise.
* i386-opc.c (i386_optab): Add SSE4.1 opcodes.
* i386-opc.h (CpuSSE4_1): New.
(CpuUnknownFlags): Add CpuSSE4_1.
(regKludge): Update comment.
2007-04-18 16:13:15 +00:00
6e26e51a85
Remove trailing white spaces.
2007-04-13 21:59:35 +00:00
e72cf3ec8e
gas/
...
2007-03-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): For instructions with 2
register operands, encode destination in i.rm.regmem if its
RegMem bit is set.
opcodes/
2007-03-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
movq. Remove InvMem from sldt, smsw and str.
* i386-opc.h (InvMem): Renamed to ...
(RegMem): Update comments.
(AnyMem): Remove InvMem.
2007-03-29 04:27:54 +00:00
c3fe08facb
gas/
...
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_begin): Use i386_regtab_size to scan
i386_regtab.
(parse_register): Use i386_regtab_size instead of ARRAY_SIZE
on i386_regtab.
opcodes/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.c: Include "libiberty.h".
(i386_regtab): Remove the last entry.
(i386_regtab_size): New.
(i386_float_regtab_size): Likewise.
* i386-opc.h (i386_regtab_size): New.
(i386_float_regtab_size): Likewise.
2007-03-15 17:30:31 +00:00
0b1cf022c8
gas/
...
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerated.
* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
"opcode/i386.h".
(md_begin): Check reg_name != NULL for the last entry in
i386_regtab.
* config/tc-i386.h: Move many entries to opcode/i386.h and
opcodes/i386-opc.h.
* configure.in (need_opcodes): Set true for i386.
* configure: Regenerated.
include/opcode/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* i386.h: Add entries from config/tc-i386.h and move tables
to opcodes/i386-opc.h.
opcodes/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (CFILES): Add i386-opc.c.
(ALL_MACHINES): Add i386-opc.lo.
Run "make dep-am".
* Makefile.in: Regenerated.
* configure.in: Add i386-opc.lo for bfd_i386_arch.
* configure: Regenerated.
* i386-dis.c: Include "opcode/i386.h".
(MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
(FWAIT_OPCODE): Remove definition.
(UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
(MAX_OPERANDS): Remove definition.
* i386-opc.c: New file.
* i386-opc.h: Likewise.
2007-03-15 14:31:24 +00:00
Ilya Tocar
H.J. Lu
Roland McGrath
Quentin Neill
Sebastian Pop
Nick Clifton
Jan Beulich
Dwarakanath Rajagopal
Michael Meissner
Alan Modra