5c111e3769
Implement Intel SMAP instructions
...
gas/
PR gas/15159
* config/tc-i386.c (cpu_arch): Add ".smap".
* doc/c-i386.texi: Document smap.
gas/testsuite/
PR gas/15159
* gas/i386/i386.exp: Run smap and x86-64-smap.
* gas/i386/smap.d: New file.
* gas/i386/smap.s: likewise.
* gas/i386/x86-64-smap.d: likewise.
opcodes/
PR gas/15159
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
(cpu_flags): Add CpuSMAP.
* i386-opc.h (CpuSMAP): New.
(i386_cpu_flags): Add cpusmap.
* i386-opc.tbl: Add clac and stac.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2013-02-19 19:10:31 +00:00
9b30cccca9
Fix opcode for 64-bit jecxz
...
gas/testsuite/
PR gas/14859
* gas/i386/x86-64-opcode.s: Add jecxz.
* gas/i386/x86-64-opcode.d: Updated.
opcodes/
PR gas/14859
* i386-opc.tbl: Fix opcode for 64-bit jecxz.
* i386-tbl.h: Regenerated.
2012-11-20 14:21:33 +00:00
60aa667ec4
Replace CpuSSE3 with CpuCX16 for cmpxchg16b
...
gas/
* config/tc-i386.c (cpu_arch): Add .cx16.
* doc/c-i386.texi: Document .cx16.
gas/testsuite/
* gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b.
* gas/i386/x86-64-arch-2.d: Update correspondingly.
* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
* gas/i386/x86-64-arch-2-btver1.d: Likewise.
* gas/i386/x86-64-arch-2-btver2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
(cpu_flags): Add CpuCX16.
* i386-opc.h (CpuCX16): New.
(i386_cpu_flags): Add cpucx16.
* i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-09-20 11:53:33 +00:00
7b458c12dc
Add AMD btver1 and btver2 support
...
gas/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
(i386_align_code): Add case for PROCESSOR_BT.
* config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
* doc/c-i386.texi: Add -march={btver1, btver2} options.
gas/testsuite/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* gas/i386/i386.exp: Run btver1 and btver2 test cases.
* gas/i386/nops-1-btver1.d: New.
* gas/i386/nops-1-btver2.d: New.
* gas/i386/arch-10-btver1.d: New.
* gas/i386/arch-10-btver2.d: New.
* gas/i386/x86-64-nops-1-btver1.d: New.
* gas/i386/x86-64-nops-1-btver2.d: New.
* gas/i386/x86-64-arch-2-btver1.d: New.
* gas/i386/x86-64-arch-2-btver2.d: New.
opcodes/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
* i386-opc.h: Update CpuPRFCHW comment.
* i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-08-17 17:12:36 +00:00
4c692bc7aa
There were several cases where the registers in the REX encoded range
...
got treated identically to the ones in the base range, due to not
paying attention to the fact that reg_entry's reg_num field doesn't
fully specify the register number (reg_flags also needs to be checked
for RegRex). This patch introduces and uses a new (inline) function to
obtain the full register number, and uses it to fix all those cases.
It additionally adds the missing operand checks for SVME instructions
(which match the monitor/mwait ones).
gas/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (register_number): New function.
(build_vex_prefix, process_immext, process_operands,
build_modrm_byte, i386_index_check): Use it.
gas/testsuite/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* gas/i386/x86-64-specific-reg.{s,l}: New.
* gas/i386/i386.exp: Run new test.
opcodes/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
2012-08-07 16:51:34 +00:00
94948e646e
VMOVNTDQA was both misplaced and improperly tagged as being an AVX
...
instruction (instead of AVX2).
2012-07-31 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
instruction group. Mark as requiring AVX2.
* i386-tbl.h: Re-generate.
2012-07-31 07:38:42 +00:00
e2e1fcde62
Implement RDRSEED, ADX and PRFCHW instructions
...
gas/
* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
* doc/c-i386.texi: Document the new directives.
gas/testsuite/
* gas/i386/i386.exp: Run adx, rdseed and prefetchw tests.
* gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10-1.l: Changed correspondingly.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
* gas/i386/arch-10-prefetchw.d: New file.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/rdseed.s: Likewise.
* gas/i386/rdseed.d: Likewise.
* gas/i386/rdseed-intel.d: Likewise.
* gas/i386/adx.s: Likewise.
* gas/i386/adx.d: Likewise.
* gas/i386/adx-intel.d: Likewise.
* gas/i386/x86-64-rdseed.s: Likewise.
* gas/i386/x86-64-rdseed.d: Likewise.
* gas/i386/x86-64-rdseed-intel.d: Likewise.
* gas/i386/x86-64-adx.s: Likewise.
* gas/i386/x86-64-adx.d: Likewise.
* gas/i386/x86-64-adx-intel.d: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F38F6): New.
(prefix_table): Add adcx, adox instructions.
(three_byte_table): Use PREFIX_0F38F6.
(mod_table): Add rdseed instruction.
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
(cpu_flags): Likewise.
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
prefetchw.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-07-16 12:58:29 +00:00
9fa0f14a97
gas/testsuite/
...
* gas/i386/rep-suffix.s: Add 'rep nop' case.
* gas/i386/x86-64-rep-suffix.s: Likewise.
* gas/i386/rep-suffix.d: Updated.
* gas/i386/x86-64-rep-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-rep-suffix.d: Likewise.
opcodes/
* i386-opc.tbl: Add RepPrefixOk to nop.
* i386-tbl.h: Regenerate.
2012-07-02 18:12:28 +00:00
fe13e45b9a
gas/
...
* NEWS: Mention 'rep ret' too.
gas/testsuite/
* gas/i386/rep-ret.d: New file.
* gas/i386/rep-ret.s: New file.
* gas/i386/i386.exp: Add the new test.
opcodes/
* i386-opc.tbl: Add RepPrefixOk to ret.
* i386-tbl.h: Regenerate.
2012-06-22 21:54:06 +00:00
29c048b696
gas/
...
* config/tc-i386.c (parse_insn): Don't complain about REP prefix
when the template has opcode_modifier.repprefixok set.
* NEWS: Mention the change.
gas/testsuite/
* gas/i386/rep-bsf.d: New file.
* gas/i386/rep-bsf.s: New file.
* gas/i386/i386.exp: Add the new test.
opcodes/
* i386-opc.h (RepPrefixOk): New enum constant.
(i386_opcode_modifier): New bitfield 'repprefixok'.
* i386-gen.c (opcode_modifiers): Add RepPrefixOk.
* i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
instructions that have IsString.
* i386-tbl.h: Regenerate.
2012-06-22 16:42:08 +00:00
42164a7195
Implement Intel Transactional Synchronization Extensions
...
gas/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (HLE_PREFIX): New.
(check_hle): Likewise.
(_i386_insn): Add have_hle.
(cpu_arch): Add .hle and .rtm.
(md_assemble): Call check_hle if i.have_hle isn't zero.
(parse_insn): Set i.have_hle to 1 for HLE prefix.
(output_jump): Support up to 2 byte opcode.
* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.
gas/testsuite/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/hle-intel.d: New.
* gas/i386/hle.d: Likewise.
* gas/i386/hle.s: Likewise.
* gas/i386/hlebad.l: Likewise.
* gas/i386/hlebad.s: Likewise.
* gas/i386/rtm-intel.d: Likewise.
* gas/i386/rtm.d: Likewise.
* gas/i386/rtm.s: Likewise.
* gas/i386/x86-64-hle-intel.d: Likewise.
* gas/i386/x86-64-hle.d: Likewise.
* gas/i386/x86-64-hle.s: Likewise.
* gas/i386/x86-64-hlebad.l: Likewise.
* gas/i386/x86-64-hlebad.s: Likewise.
* gas/i386/x86-64-rtm-intel.d: Likewise.
* gas/i386/x86-64-rtm.d: Likewise.
* gas/i386/x86-64-rtm.s: Likewise.
* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
x86-64-rtm-intel.
include/opcode/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (XACQUIRE_PREFIX_OPCODE): New.
(XRELEASE_PREFIX_OPCODE): Likewise.
opcodes/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (HLE_Fixup1): New.
(HLE_Fixup2): Likewise.
(HLE_Fixup3): Likewise.
(Ebh1): Likewise.
(Evh1): Likewise.
(Ebh2): Likewise.
(Evh2): Likewise.
(Ebh3): Likewise.
(Evh3): Likewise.
(MOD_C6_REG_7): Likewise.
(MOD_C7_REG_7): Likewise.
(RM_C6_REG_7): Likewise.
(RM_C7_REG_7): Likewise.
(XACQUIRE_PREFIX): Likewise.
(XRELEASE_PREFIX): Likewise.
(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
MOD_C6_REG_7 and MOD_C7_REG_7.
(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
xtest.
(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
CPU_RTM_FLAGS.
(cpu_flags): Add CpuHLE and CpuRTM.
(opcode_modifiers): Add HLEPrefixOk.
* i386-opc.h (CpuHLE): New.
(CpuRTM): Likewise.
(HLEPrefixOk): Likewise.
(i386_cpu_flags): Add cpuhle and cpurtm.
(i386_opcode_modifier): Add hleprefixok.
* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
operand. Add xacquire, xrelease, xabort, xbegin, xend and
xtest.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-02-08 18:20:41 +00:00
8729a6f6a5
Add vmfunc
...
gas/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add ".vmfunc".
* doc/c-i386.texi: Document vmfunc.
gas/testsuite/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc.
* gas/i386/vmfunc.d: New.
* gas/i386/vmfunc.s: Likewise.
* gas/i386/x86-64-vmfunc.d: Likewise.
opcodes/
2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (mod_table): Add vmfunc.
* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
(cpu_flags): CpuVMFUNC.
* i386-opc.h (CpuVMFUNC): New.
(i386_cpu_flags): Add cpuvmfunc.
* i386-opc.tbl: Add vmfunc.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-01-13 22:19:32 +00:00
00f51a41a8
Add Disp32S to 64bit call.
...
gas/testsuite/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* gas/i386/x86-64-branch.s: Add tests for direct branch.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
opcodes/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* i386-opc.tbl: Add Disp32S to 64bit call.
* i386-tbl.h: Regenerated.
2011-08-01 19:25:48 +00:00
4cb0953da2
Fix rorx in BMI2.
...
gas/testsuite/
2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/bmi2.s: Correct rorx tests.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/bmi2-intel.d: Updated.
* gas/i386/bmi2.d: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
opcodes/
2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (vex_len_table): Correct rorxS.
* i386-opc.tbl: Correct rorx.
* i386-tbl.h: Regenerated.
2011-06-30 15:44:55 +00:00
6c30d220f1
Support AVX Programming Reference (June, 2011).
...
gas/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* config/tc-i386.c (i386_error): Add invalid_vsib_address and
unsupported_vector_index_register.
(cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid.
(check_VecOperands): New.
(match_template): Call check_VecOperands. Handle
invalid_vsib_address and unsupported_vector_index_register.
(build_modrm_byte): Support VecSIB. Check register-only source
operand when two source operands are swapped.
(i386_index_check): Allow Xmm/Ymm index registers.
* doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt
and invpcid./invpcid.
gas/testsuite/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/arch-10-1.l: Updated.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Add LZCNT to comments.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10-lzcnt.d: New.
* gas/i386/avx-gather-intel.d: Likewise.
* gas/i386/avx-gather.d: Likewise.
* gas/i386/avx-gather.s: Likewise.
* gas/i386/avx2-intel.d: Likewise.
* gas/i386/avx2.d: Likewise.
* gas/i386/avx2.s: Likewise
* gas/i386/avx256int-intel.d: Likewise.
* gas/i386/avx256int.d: Likewise.
* gas/i386/avx256int.s: Likewise.
* gas/i386/bmi2-intel.d: Likewise.
* gas/i386/bmi2.d: Likewise.
* gas/i386/bmi2.s: Likewise.
* gas/i386/inval-invpcid.l:Likewise.
* gas/i386/inval-invpcid.s: Likewise.
* gas/i386/invpcid-intel.d: Likewise.
* gas/i386/invpcid.d: Likewise.
* gas/i386/invpcid.s: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-avx-gather-intel.d: Likewise.
* gas/i386/x86-64-avx-gather.d: Likewise.
* gas/i386/x86-64-avx-gather.s: Likewise.
* gas/i386/x86-64-avx2-intel.d: Likewise.
* gas/i386/x86-64-avx2.d: Likewise.
* gas/i386/x86-64-avx2.s: Likewise.
* gas/i386/x86-64-avx256int-intel.d: Likewise.
* gas/i386/x86-64-avx256int.d: Likewise.
* gas/i386/x86-64-avx256int.s: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/x86-64-inval-invpcid.l: Likewise.
* gas/i386/x86-64-inval-invpcid.s: Likewise.
* gas/i386/x86-64-invpcid-intel.d: Likewise.
* gas/i386/x86-64-invpcid.d: Likewise.
* gas/i386/x86-64-invpcid.s: Likewise.
opcodes/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (XMGatherQ): New.
* i386-dis.c (EXxmm_mb): New.
(EXxmm_mb): Likewise.
(EXxmm_mw): Likewise.
(EXxmm_md): Likewise.
(EXxmm_mq): Likewise.
(EXxmmdw): Likewise.
(EXxmmqd): Likewise.
(VexGatherQ): Likewise.
(MVexVSIBDWpX): Likewise.
(MVexVSIBQWpX): Likewise.
(xmm_mb_mode): Likewise.
(xmm_mw_mode): Likewise.
(xmm_md_mode): Likewise.
(xmm_mq_mode): Likewise.
(xmmdw_mode): Likewise.
(xmmqd_mode): Likewise.
(ymmxmm_mode): Likewise.
(vex_vsib_d_w_dq_mode): Likewise.
(vex_vsib_q_w_dq_mode): Likewise.
(MOD_VEX_0F385A_PREFIX_2): Likewise.
(MOD_VEX_0F388C_PREFIX_2): Likewise.
(MOD_VEX_0F388E_PREFIX_2): Likewise.
(PREFIX_0F3882): Likewise.
(PREFIX_VEX_0F3816): Likewise.
(PREFIX_VEX_0F3836): Likewise.
(PREFIX_VEX_0F3845): Likewise.
(PREFIX_VEX_0F3846): Likewise.
(PREFIX_VEX_0F3847): Likewise.
(PREFIX_VEX_0F3858): Likewise.
(PREFIX_VEX_0F3859): Likewise.
(PREFIX_VEX_0F385A): Likewise.
(PREFIX_VEX_0F3878): Likewise.
(PREFIX_VEX_0F3879): Likewise.
(PREFIX_VEX_0F388C): Likewise.
(PREFIX_VEX_0F388E): Likewise.
(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
(PREFIX_VEX_0F38F5): Likewise.
(PREFIX_VEX_0F38F6): Likewise.
(PREFIX_VEX_0F3A00): Likewise.
(PREFIX_VEX_0F3A01): Likewise.
(PREFIX_VEX_0F3A02): Likewise.
(PREFIX_VEX_0F3A38): Likewise.
(PREFIX_VEX_0F3A39): Likewise.
(PREFIX_VEX_0F3A46): Likewise.
(PREFIX_VEX_0F3AF0): Likewise.
(VEX_LEN_0F3816_P_2): Likewise.
(VEX_LEN_0F3819_P_2): Likewise.
(VEX_LEN_0F3836_P_2): Likewise.
(VEX_LEN_0F385A_P_2_M_0): Likewise.
(VEX_LEN_0F38F5_P_0): Likewise.
(VEX_LEN_0F38F5_P_1): Likewise.
(VEX_LEN_0F38F5_P_3): Likewise.
(VEX_LEN_0F38F6_P_3): Likewise.
(VEX_LEN_0F38F7_P_1): Likewise.
(VEX_LEN_0F38F7_P_2): Likewise.
(VEX_LEN_0F38F7_P_3): Likewise.
(VEX_LEN_0F3A00_P_2): Likewise.
(VEX_LEN_0F3A01_P_2): Likewise.
(VEX_LEN_0F3A38_P_2): Likewise.
(VEX_LEN_0F3A39_P_2): Likewise.
(VEX_LEN_0F3A46_P_2): Likewise.
(VEX_LEN_0F3AF0_P_3): Likewise.
(VEX_W_0F3816_P_2): Likewise.
(VEX_W_0F3818_P_2): Likewise.
(VEX_W_0F3819_P_2): Likewise.
(VEX_W_0F3836_P_2): Likewise.
(VEX_W_0F3846_P_2): Likewise.
(VEX_W_0F3858_P_2): Likewise.
(VEX_W_0F3859_P_2): Likewise.
(VEX_W_0F385A_P_2_M_0): Likewise.
(VEX_W_0F3878_P_2): Likewise.
(VEX_W_0F3879_P_2): Likewise.
(VEX_W_0F3A00_P_2): Likewise.
(VEX_W_0F3A01_P_2): Likewise.
(VEX_W_0F3A02_P_2): Likewise.
(VEX_W_0F3A38_P_2): Likewise.
(VEX_W_0F3A39_P_2): Likewise.
(VEX_W_0F3A46_P_2): Likewise.
(MOD_VEX_0F3818_PREFIX_2): Removed.
(MOD_VEX_0F3819_PREFIX_2): Likewise.
(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
(VEX_LEN_0F3A0E_P_2): Likewise.
(VEX_LEN_0F3A0F_P_2): Likewise.
(VEX_LEN_0F3A42_P_2): Likewise.
(VEX_LEN_0F3A4C_P_2): Likewise.
(VEX_W_0F3818_P_2_M_0): Likewise.
(VEX_W_0F3819_P_2_M_0): Likewise.
(prefix_table): Updated.
(three_byte_table): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(vex_w_table): Likewise.
(mod_table): Likewise.
(putop): Handle "LW".
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
(OP_EX): Likewise.
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
vex_vsib_q_w_dq_mode.
(OP_XMM): Handle vex_vsib_q_w_dq_mode.
(OP_VEX): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
(opcode_modifiers): Add VecSIB.
* i386-opc.h (CpuAVX2): New.
(CpuBMI2): Likewise.
(CpuLZCNT): Likewise.
(CpuINVPCID): Likewise.
(VecSIB128): Likewise.
(VecSIB256): Likewise.
(VecSIB): Likewise.
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
(i386_opcode_modifier): Add vecsib.
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-06-10 21:27:40 +00:00
2a2a0f38e7
Add support for TBM instructions.
...
gas/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
* doc/c-i386.texi (i386-TBM): New section.
opcodes/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
gas/testsuite
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* gas/i386/tbm.s: New.
* gas/i386/tbm.d: New.
* gas/i386/tbm-intel.d: New.
* gas/i386/x86-64-tbm.s: New.
* gas/i386/x86-64-tbm.d: New.
* gas/i386/x86-64-tbm-intel.d: New.
* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
* gas/i386/arch-10.s: Add a TBM instruction.
* gas/i386/arch-10-1.l: Add TBM instruction pattern.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
2011-01-17 18:40:36 +00:00
f12dc42220
Implement BMI instructions.
2011-01-05 00:16:57 +00:00
553d0a7447
Remove CheckRegSize from movq.
...
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Remove CheckRegSize from movq.
* i386-tbl.h: Regenerated.
2010-10-14 23:16:19 +00:00
cfc08d490e
Remove CheckRegSize from instructions with 0, 1 or fixed operands.
...
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Remove CheckRegSize from instructions with
0, 1 or fixed operands.
* i386-tbl.h: Regenerated.
2010-10-14 21:37:30 +00:00
56ffb74112
Add CheckRegSize to instructions which require register size check.
...
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check checkregsize
instead of w for register size check.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run inval-reg.
* gas/i386/inval-reg.l: New.
* gas/i386/inval-reg.s: Likewise.
opcodes/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add CheckRegSize.
* i386-opc.h (CheckRegSize): New.
(i386_opcode_modifier): Add checkregsize.
* i386-opc.tbl: Add CheckRegSize to instructions which
require register size check.
* i386-tbl.h: Regenerated.
2010-10-14 18:45:10 +00:00
2210942396
Don't generate multi-byte NOPs for i686.
...
gas/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (arch_entry): Add negated bit to
disambiguate flag names starting with "no".
(cpu_arch): Add negated bit definitions. Add
".nop" CPU extension.
(i386_align_code): Use new .cpunop bit to decide
when to generate alignment using nops.
(set_cpu_arch): Use negated bit instead to decide
when to use cpu_flags or vs. cpu_flags_and_not.
(md_parse_option): Likewise.
gas/testsuite/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* gas/i386/arch-10-1.l: Add nopl instruction.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10.d: Add nopl instruction, and +nopl extension
flag to as flags.
* gas/i386/nops-5-i686.d: Change alignment code generated for
-mtune=i686.
* gas/i386/nops-5.d: Change alignment code generated for
.arch i686.
* gas/i386/x86-64-nops-5-k8.d: Likewise.
* gas/i386/x86-64-nops-5.d: Likewise.
opcodes/
2010-08-06 Quentin Neill <quentin.neill@amd.com>
* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
to processor flags for PENTIUMPRO processors and later.
* i386-opc.h (enum): Add CpuNop.
(i386_cpu_flags): Add cpunop bit.
* i386-opc.tbl: Change nop cpu_flags.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2010-08-06 18:22:50 +00:00
92d4d42efb
Add Cpu186 to ud1/ud2/ud2a/ud2b.
...
2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
* i386-tbl.h: Regenerated.
2010-08-06 01:03:17 +00:00
b414985b9e
Add ud1 to x86.
...
gas/testsuite/
2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run arch-4.
* gas/i386/arch-4.d: New.
* gas/i386/arch-4.s: Likewise.
* gas/i386/intel.d: Replace ud2a/ud2b with ud2/ud1.
* gas/i386/opcode-intel.d: Likewise.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
opcodes/
2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
* i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
* i386-tbl.h: Regenerated.
2010-08-06 00:52:57 +00:00
d7d9a9f820
Replace rdrnd with rdrand.
...
gas/testsuite/
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/rdrnd.s: Replace rdrnd with rdrand.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
opcodes/
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (mod_table): Replace rdrnd with rdrand.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
2010-07-05 17:14:22 +00:00
c7b8aa3a72
Support AVX Programming Reference (June, 2010)
...
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-01 21:55:02 +00:00
ce7d077ec0
2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
opcodes/
* i386-dis.c (OP_LWP_I): Removed.
(reg_table): Do not use OP_LWP_I, use Iq.
(OP_LWPCB_E): Remove use of names16.
(OP_LWP_E): Same.
* i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
should not set the Vex.length bit.
* i386-tbl.h: Regenerated.
gas/
* testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns.
* testsuite/gas/i386/lwp.s: Same.
* testsuite/gas/i386/x86-64-lwp.d: Updated.
* testsuite/gas/i386/lwp.d: Updated.
2010-03-23 02:56:24 +00:00
c75ef631bd
Update copyright.
...
gas/
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c: Update copyright.
opcodes/
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c: Update copyright.
* i386-gen.c: Likewise.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
2010-02-11 13:41:19 +00:00
a683cc34e4
2010-02-10 Quentin Neill <quentin.neill@amd.com>
...
Sebastian Pop <sebastian.pop@amd.com>
gas:
* config/tc-i386.c (vec_imm4) New operand type.
(fits_in_imm4): New.
(VEX_check_operands): New.
(check_reverse): Call VEX_check_operands.
(build_modrm_byte): Reintroduce code for 5
operand insns. Fix whitespace.
gas/testsuite:
* gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
* gas/i386/x86-64-xop.s: Likewise.
* gas/i386/xop.d: Likewise.
* gas/i386/xop.s: Likewise.
opcodes:
* i386-dis.c (OP_EX_VexImmW): Reintroduced
function to handle 5th imm8 operand.
(PREFIX_VEX_3A48): Added.
(PREFIX_VEX_3A49): Added.
(VEX_W_3A48_P_2): Added.
(VEX_W_3A49_P_2): Added.
(prefix table): Added entries for PREFIX_VEX_3A48
and PREFIX_VEX_3A49.
(vex table): Added entries for VEX_W_3A48_P_2 and
and VEX_W_3A49_P_2.
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
for Vec_Imm4 operands.
* i386-opc.h (enum): Added Vec_Imm4.
(i386_operand_type): Added vec_imm4.
* i386-opc.tbl: Add entries for vpermilp[ds].
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2010-02-11 05:06:14 +00:00
712366da0a
Replace "Vex" with "Vex=3" on AVX scalar instructions.
...
2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEXScalar): New.
* i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
instructions.
* i386-tbl.h: Regenerated.
2010-01-24 00:59:13 +00:00
73bb672904
Add xsave64 and xrstor64.
...
gas/testsuite/
2010-02-21 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-xsave.s: Add tests for xsave64 and xrstor64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-02-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
* i386-opc.tbl: Add xsave64 and xrstor64.
* i386-tbl.h: Regenerated.
2010-01-21 17:30:14 +00:00
a6461c0251
2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
...
gas/
* config/tc-i386.c (md_assemble): Before accessing the IMM field
check that it's not an XOP insn.
gas/testsuite/
* gas/i386/x86-64-xop.d: Add missing patterns.
* gas/i386/x86-64-xop.s: Same.
* gas/i386/xop.d: Same.
* gas/i386/xop.s: Same.
opcodes/
* i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
* i386-tbl.h: Regenerated.
2010-01-15 21:24:13 +00:00
2426c15ff8
Replace VexNDS, VexNDD and VexLWP with VexVVVV.
...
gas/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexvvvv instead
of vexnds and vexndd.
(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
and vexlwp.
opcodes/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
VexLWP. Add VexVVVV.
* i386-opc.h (VexNDS): Removed.
(VexNDD): Likewise.
(VexLWP): Likewise.
(VEXXDS): New.
(VEXNDD): Likewise.
(VEXLWP): Likewise.
(VexVVVV): Likewise.
(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
Add vexvvvv.
* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
VexVVVV=2 and VexLWP with VexVVVV=3.
* i386-tbl.h: Regenerated.
2009-12-19 18:36:27 +00:00
2eb952a4d9
Remove ByteOkIntel.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
Intel syntax if size is ignored and b/l/w suffixes are
illegal.
(check_byte_reg): Remove byteokintel check.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove ByteOkIntel.
* i386-opc.h (ByteOkIntel): Removed.
(i386_opcode_modifier): Remove byteokintel.
* i386-opc.tbl: Remove ByteOkIntel.
* i386-tbl.h: Regenerated.
2009-12-16 20:08:32 +00:00
7f399153c6
Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38,
vex0f3a, xop08, xop09 and xop0a with vexopcode.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38,
Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode.
* i386-opc.h (Vex0F): Removed.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(VexOpcode): New.
(VEX0F): Likewise.
(VEX0F38): Likewise.
(VEX0F3A): Likewise.
(XOP08): Defined as a macro.
(XOP09): Likewise.
(XOP0A): Likewise.
(i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08,
xop09 and xop0a. Add vexopcode.
* i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3,
XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5.
* i386-tbl.h: Regenerated.
2009-12-16 15:43:16 +00:00
8cd7925b45
Replace Vex2Sources and Vex3Sources with VexSources.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexsources
instead of vex3sources.
(build_modrm_byte): Check vexsources instead of vex2sources
and vex3sources.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex3Sources and
Vex2Sources. Add VexSources.
* i386-opc.h ()Vex2Sources: Removed.
(Vex3Sources): Likewise.
(VEX2SOURCES): New.
(VEX3SOURCES): Likewise.
(VexSources): Likewise.
(i386_opcode_modifier): Remove vex2sources and vex3sources.
Add vexsources.
* i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
Vex3Sourceswith VexSources=2.
* i386-tbl.h: Regenerated.
2009-12-16 04:00:35 +00:00
1ef99a7be9
Remove VexW0 and VexW1. Add VexW.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1
with vexw.
(build_modrm_byte): Likewise.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add
VexW.
* i386-opc.h (VexW0): Removed.
(VexW1): Likewise.
(VEXW0): New.
(VEXW1): Likewise.
(VexW): Likewise.
(i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw.
* i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with
Vex=2.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-12-16 02:10:45 +00:00
9e30b8e093
Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (USE_VEX_W_TABLE): New.
(VEX_W_TABLE): Likewise.
(VEX_W_XXX): Likewise.
(vex_w_table): Likewise.
(prefix_table): Use VEX_W_XXX.
(vex_table): Likewise.
(vex_len_table): Likewise.
(mod_table): Likewise.
(get_valid_dis386): Handle USE_VEX_W_TABLE.
* i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit
isn't used.
* i386-tbl.h: Regenerated.
2009-12-15 18:56:09 +00:00
eacc9c891d
Support fxsave64 and fxrstor64.
...
gas/testsuite/
2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel.
* gas/i386/rex.d: Updated for fxsave64.
* gas/i386/x86-64-fxsave-intel.d: New.
* gas/i386/x86-64-fxsave.d: Likewise.
* gas/i386/x86-64-fxsave.s: Likewise.
opcodes/
2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (FXSAVE_Fixup): New.
(FXSAVE): Likewise.
(mod_table): Use FXSAVE on fxsave and fxrstor.
* i386-opc.tbl: Add fxsave64 and fxrstor64.
* i386-tbl.h: Regenerated.
2009-12-04 07:51:41 +00:00
18d0c96eb9
Allow lock on cmpxch16b.
...
gas/testsuite/
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/lock-1.s: Add cmpxchg16b test.
* gas/i386/lock-1-intel.d: Updated.
* gas/i386/lock-1.d: Likewise.
opcodes/
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add IsLockable to cmpxch16b.
* i386-tbl.h: Regenerated.
2009-11-19 15:26:42 +00:00
f0ae4a24b0
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
...
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 20:28:59 +00:00
5dd85c9970
2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
(build_vex_prefix): Handle xop08.
(md_assemble): Don't special case the constant 3 for insns using MODRM.
(build_modrm_byte): Handle vex2sources.
(md_show_usage): Add xop and cvt16.
* doc/c-i386.texi: Document fma4, xop, and cvt16.
gas/testsuite/
* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
* gas/i386/lwp.d: Update name of the testcase.
* gas/i386/x86-64-xop.d: New.
* gas/i386/x86-64-xop.s: New.
* gas/i386/xop.d: New.
* gas/i386/xop.s: New.
* gas/i386/cvt16.d: New.
* gas/i386/cvt16.s: New.
opcodes/
* i386-dis.c (OP_Vex_2src_1): New.
(OP_Vex_2src_2): New.
(Vex_2src_1): New.
(Vex_2src_2): New.
(XOP_08): Added.
(VEX_LEN_XOP_08_A0): Added.
(VEX_LEN_XOP_08_A1): Added.
(VEX_LEN_XOP_09_80): Added.
(VEX_LEN_XOP_09_81): Added.
(xop_table): Added an entry for XOP_08. Handle xop instructions.
(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
(get_valid_dis386): Handle XOP_08.
(OP_Vex_2src): New.
* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
(cpu_flags): Add CpuXOP and CpuCVT16.
(opcode_modifiers): Add XOP08, Vex2Sources.
* i386-opc.h (CpuXOP): Added.
(CpuCVT16): Added.
(i386_cpu_flags): Add cpuxop and cpucvt16.
(XOP08): Added.
(Vex2Sources): Added.
(i386_opcode_modifier): Add xop08, vex2sources.
* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 04:04:17 +00:00
20efc68957
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc,
or, sbb, sub, xor and xchg with register only operands.
* i386-tbl.h: Regenerated.
2009-11-12 19:15:18 +00:00
c32fa91d70
gas/
...
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (LOCKREP_PREFIX): Removed.
(REP_PREFIX): New.
(LOCK_PREFIX): Likewise.
(PREFIX_GROUP): Likewise.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(add_prefix): Updated. Return enum PREFIX_GROUP.
(md_assemble): Check for lock without a lockable instruction.
(parse_insn): Updated.
(output_insn): Likewise.
gas/testsuite/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.
* gas/i386/lock-1-intel.d: New.
* gas/i386/lock-1.d: Likewise.
* gas/i386/lock-1.s: Likewise.
* gas/i386/lockbad-1.l: Likewise.
* gas/i386/lockbad-1.s: Likewise.
* gas/i386/x86-64-lock-1-intel.d: Likewise.
* gas/i386/x86-64-lock-1.d: Likewise.
* gas/i386/x86-64-lock-1.s: Likewise.
* gas/i386/x86-64-lockbad-1.l: Likewise.
* gas/i386/x86-64-lockbad-1.s: Likewise.
opcodes/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IsLockable.
* i386-opc.h (IsLockable): New.
(i386_opcode_modifier): Add islockable.
* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
xor, xadd and xchg.
* i386-tbl.h: Regenerated.
2009-11-12 18:57:14 +00:00
f88c9eb030
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
2009-11-05 23:40:05 +00:00
f98fa53424
2009-10-02 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.tbl: Drop Disp64 on jump and loop instructions.
* i386-tbl.h: Regenerated.
2009-10-02 19:03:40 +00:00
2bf05e5730
gas/
...
2009-09-24 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Check vex == 2 instead
of vex256.
opcodes/
2009-09-24 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex256.
(set_bitfield): Handle XXX=V.
* i386-opc.h (Vex): Update comments.
(Vex256): Removed.
(VexNDS): Updated.
(i386_opcode_modifier): Change vex to 2 bits. Remove vex256.
* i386-opc.tbl: Replace "Vex|Vex256" with Vex=2.
* i386-tbl.h: Regenerated.
2009-09-24 16:37:09 +00:00
309d33736f
gas/
...
2009-07-24 Jan Beulich <jbeulich@novell.com>
* tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx,
.nosse, and .noavx.
(cpu_flags_and_not): New.
(set_cpu_arch): Check whether sub-architecture specified is a
feature disable.
(md_parse_option): Likewise.
(parse_real_register): Don't return floating point register
when x87 functionality is disabled.
(md_show_usage): Add new sub-options.
* doc/c-i386.texi: Update with new command line sub-options.
gas/testsuite/
2009-07-24 Jan Beulich <jbeulich@novell.com>
* gas/i386/8087.[ds]: New.
* gas/i386/287.[ds]: New.
* gas/i386/387.[ds]: New.
* gas/i386/no87.[ls]: New.
* gas/i386/no87-2.[ls]: New.
* gas/i386/i386.exp: Run new tests.
* gas/i386/att-regs.s: Also check FPU register access.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Adjust expectations.
* gas/i386/intel-regs.d: Likewise.
opcodes/
2009-07-24 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add
frstpm.
* i386-gen.c (cpu_flag_init): Add FP enabling flags where needed.
(cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP.
(set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387.
* i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP):
Define.
(union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687,
and cpufisttp.
* i386-opc.tbl: Qualify floating point instructions by their
respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos,
and fsincos to be avilable only on 387. Fix fstsw ax to be
available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm,
and frstpm.
* i386-init.h, i386-tbl.h: Regenerate.
2009-07-24 15:41:20 +00:00
922d8de8c1
<gas changes>
...
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
(build_modrm_byte): Add support to handle FMA4 instructions.
(md_show_usage): Add fma4.
<gas/testsuite changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Add FMA4 tests.
* gas/i386/x86-64-fma4.d: Ditto.
* gas/i386/fma4.d: Ditto.
* gas/i386/x86-64-fma4.s: Ditto.
* gas/i386/fma4.s: Ditto.
<opcodes changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (CpuFMA4): Add CpuFMA4.
(i386_cpu_flags): New.
* i386-gen.c: Add CPU_FMA4_FLAGS.
* i386-opc.tbl: Add FMA4 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
(OP_XMM_VexW): Ditto.
(OP_EX_VexW): Ditto.
(VEXI4_Fixup): Ditto.
(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
(get_vex_imm8): New. handle FMA4.
(OP_EX_VexReg): Ditto.
2009-07-06 19:34:30 +00:00
c1e679ec0a
<gas changes>
...
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/tc-i386.c (process_drex): Delete. Remove SSE5 support.
(build_modrm_byte): Remove DREX handling support.
(DREX_*): Delete.
(drex_byte): Delete.
(md_assemble): Remove DREX handling support.
(process_operands): Remove DREX, SSE5 support.
(i386_insn): Remove DREX.
<gas/testsuite changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* gas/i386/i386.exp: Remove SSE5 tests.
* gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests.
* gas/i386/x86-64-sse5.d: Ditto.
* gas/i386/arch-10-1.l: Remove SSE5 tests.
* gas/i386/arch-10-2.l: Ditto.
* gas/i386/arch-10-3.l: Ditto.
* gas/i386/arch-10-4.l: Ditto.
* gas/i386/arch-10.d: Ditto.
* gas/i386/arch-10.s: Ditto.
* gas/i386/arch-4.s: Delete. Remove SSE5 tests.
* gas/i386/arch-4.d: Ditto.
* gas/i386/arch-8.s: Ditto.
* gas/i386/arch-8.d: Ditto.
* gas/i386/arch-2.s: Remove SSE5 tests.
* gas/i386/arch-2.d: Remove SSE5 tests.
* gas/i386/x86-64-arch-2.s: Ditto.
<opcodes changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-opc.h (Cpusse5): Delete.
(i386_cpu_flags): Delete.
* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
* i386-opc.tbl: Remove SSE5 instructions.
* i386-tbl.h: Regenerate.
* i386-init.h: Regenerate.
* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
(print_drex_arg): Delete.
(OP_DREX4): Delete.
(OP_DREX3): Delete.
(OP_DREX_ICMP): Delete.
(OP_DREX_FCMP): Delete.
(DREX_*): Delete.
(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
2009-05-22 15:57:25 +00:00
ac5c19e6ba
gas/testsuite/
...
2009-04-15 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-sse5.s: Add test of protd.
* gas/i386/x86-64-sse5.d: Adjust expectations to match input.
opcodes/
2009-04-15 Jan Beulich <jbeulich@novell.com>
* i386-opc.tbl (protb, protw, protd, protq): Set opcode
extension to None.
(pshab, pshaw, pshad, pshaq): Likewise.
* i386-tbl.h: Re-generate.
2009-04-15 13:31:28 +00:00
4c664d7bf7
gas/
...
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (vex_imm4): Removed.
(VEX_check_operands): Likewise.
(match_template): Updated.
opcodes/
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
(operand_types): Remove Vex_Imm4.
* i386-opc.h (Vex_Imm4): Removed.
(OTMax): Updated.
(i386_operand_type): Remove vex_imm4.
* i386-opc.tbl: Remove Vex_Imm4 comments.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-02-23 20:41:46 +00:00
ce2f5b3ce7
gas/
...
2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (January, 2009)
* config/tc-i386.c (CPU_FLAGS_PCLMUL_MATCH): New.
(CPU_FLAGS_AVX_MATCH): Updated.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(cpu_flags_match): Likewise.
gas/testsuite/
2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (January, 2009)
* gas/i386/arch-avx-1-3.l: New.
* gas/i386/arch-avx-1-3.s: Likewise.
* gas/i386/arch-avx-1-4.l: Likewise.
* gas/i386/arch-avx-1-4.s: Likewise.
* gas/i386/arch-avx-1-5.l: Likewise.
* gas/i386/arch-avx-1-5.s: Likewise.
* gas/i386/arch-avx-1-6.l: Likewise.
* gas/i386/arch-avx-1-6.s: Likewise.
* gas/i386/arch-10.s: Add vpclmul instructions.
* gas/i386/arch-avx-1.s: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/sse2avx.s: Add pclmul instructions.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-avx-1.d: Likewise.
* gas/i386/arch-avx-1-1.l: Likewise.
* gas/i386/arch-avx-1-2.l: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/i386.exp: Run arch-avx-1-3, arch-avx-1-4,
arch-avx-1-5 and arch-avx-1-6.
opcodes/
2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (January, 2009)
* i386-dis.c (PREFIX_VEX_3A44): New.
(VEX_LEN_3A44_P_2): Likewise.
(PREFIX_VEX_3A48): Updated.
(VEX_LEN_3A4C_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_3A44.
(vex_table): Likewise.
(vex_len_table): Add VEX_LEN_3A44_P_2.
* i386-opc.tbl: Add PCLMUL + AVX instructions.
* i386-tbl.h: Regenerated.
2009-02-04 16:03:31 +00:00
c1ec187589
gas/testsuite/
...
2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse-noavx.s: Add tests for lfence, mfence and movnti.
* gas/i386/x86-64-sse-noavx.s: Likewise.
* gas/i386/sse-noavx.d: Updated.
* gas/i386/x86-64-sse-noavx.d: Likewise.
opcodes/
2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoAVX to movnti, lfence and mfence.
* i386-tbl.h: Regenerated.
2009-01-13 00:00:35 +00:00
bd5295b282
gas/
...
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-10 17:25:52 +00:00
1b7f3fb0dd
gas/
...
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .rdtscp.
(md_show_usage): Display rdtscp.
* doc/c-i386.texi: Document rdtscp.
gas/testsuite/
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add rdtscp.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS.
(cpu_flags): Add CpuRdtscp.
(set_bitfield): Remove CpuSledgehammer check.
* i386-opc.h (CpuRdtscp): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpurdtscp.
* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-09 20:32:32 +00:00
168e309712
gas/testsuite/
...
2009-01-06 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* gas/i386/avx.s: Add tests for 256bit vmovntdq, vmovntpd and
vmovntps.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/avx.d: Updated.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
opcodes/
2009-01-06 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* i386-dis.c (VEX_LEN_2B_M_0): Removed.
(VEX_LEN_E7_P_2_M_0): Likewise.
(VEX_LEN_2C_P_1): Updated.
(VEX_LEN_E8_P_2): Likewise.
(vex_len_table): Remove VEX_LEN_2B_M_0 and VEX_LEN_E7_P_2_M_0.
(mod_table): Likewise.
* i386-opc.tbl: Add 256bit vmovntdq, vmovntpd and vmovntps.
* i386-tbl.h: Regenerated.
2009-01-06 17:15:28 +00:00
0bfee64967
gas/
...
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* config/tc-i386.c (build_modrm_byte): Remove 5 operand instruction
support. Don't swap REG and NDS for FMA.
gas/testsuite/
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* gas/i386/arch-10.s: Replace vfmaddpd with vfmadd132pd.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/avx.s: Remove vpermil2ps/vpermil2pd and FMA
instructions. Update tests.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/fma.d: New.
* gas/i386/fma.s: Likewise.
* gas/i386/fma-intel.d: Likewise.
* gas/i386/x86-64-fma.d: Likewise.
* gas/i386/x86-64-fma.s: Likewise.
* gas/i386/x86-64-fma-intel.d: Likewise.
* gas/i386/i386.exp: Run fma, fma-intel, x86-64-fma and
x86-64-fma-intel.
opcodes/
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (December, 2008)
* i386-dis.c (OP_VEX_FMA): Removed.
(OP_EX_VexW): Likewise.
(OP_EX_VexImmW): Likewise.
(OP_XMM_VexW): Likewise.
(VEXI4_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(VexI4): Likewise.
(VexFMA): Likewise.
(Vex128FMA): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(EXVexImmW): Likewise.
(XMVexW): Likewise.
(VPERMIL2): Likewise.
(PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise.
(PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise.
(PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise.
(PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise.
(VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise.
(VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise.
(get_vex_imm8): Likewise.
(OP_EX_VexReg): Likewise.
vpermil2_op): Likewise.
(EXVexWdq): New.
(vex_w_dq_mode): Likewise.
(PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise.
(PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise.
(PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise.
(es_reg): Updated.
(PREFIX_VEX_38DB): Likewise.
(PREFIX_VEX_3A4A): Likewise.
(PREFIX_VEX_3A60): Likewise.
(PREFIX_VEX_3ADF): Likewise.
(VEX_LEN_3ADF_P_2): Likewise.
(prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A,
PREFIX_VEX_3A5C...PREFIX_VEX_3A5F,
PREFIX_VEX_3A68...PREFIX_VEX_3A6F and
PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add
PREFIX_VEX_3896...PREFIX_VEX_389F,
PREFIX_VEX_38A6...PREFIX_VEX_38AF and
PREFIX_VEX_38B6...PREFIX_VEX_38BF.
(vex_table): Likewise.
(vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2
and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2.
(putop): Support "%XW".
(intel_operand_size): Handle vex_w_dq_mode.
* i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS.
* i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA
instructions. Add new FMA instructions.
* i386-tbl.h: Regenerated.
2009-01-06 01:03:27 +00:00
fa99fab222
gas/
...
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Changed to return
const template *. Handle i.swap_operand for 3 operands.
(build_vex_prefix): Take const template *. Swap operand for
2-byte VEX prefix if possible.
(md_assemble): Updated.
(build_modrm_byte): Handle RegMem bit for SSE2AVX.
gas/testsuite/
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.
* gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
vmovss.
* gas/i386/x86-64-opts.s: Likewise.
* gas/i386/opts.d: Updated.
* gas/i386/opts-intel.d: Likewise.
* gas/i386/sse2avx-opts.d: Likewise.
* gas/i386/sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.d: Likewise.
* gas/i386/x86-64-opts-intel.d: Likewise.
* gas/i386/x86-64-sse2avx-opts.d: Likewise.
* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-avx-swap.d: New.
* gas/i386/x86-64-avx-swap.s: Likewise.
* gas/i386/x86-64-avx-swap-intel.d: Likewise.
opcodes/
2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EXdS): New.
(EXdVexS): Likewise.
(EXqVexS): Likewise.
(d_swap_mode): Likewise.
(q_mode): Updated.
(prefix_table): Use EXdS on movss and EXqS on movsd.
(vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
(intel_operand_size): Handle d_swap_mode.
(OP_EX): Likewise.
* i386-opc.h (S): Update comments.
* i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
* i386-tbl.h: Regenerated.
2008-12-23 15:14:15 +00:00
b6169b206a
gas/
...
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add swap_operand.
(parse_insn): Handle ".s".
(match_template): Handle swap_operand.
* doc/c-i386.texi: Document .s suffix.
gas/testsuite/
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.
* gas/i386/opts.d: New.
* gas/i386/opts-intel.d: Likewise.
* gas/i386/opts.s: Likewise.
* gas/i386/sse2avx-opts.d: Likewise.
* gas/i386/sse2avx-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.d: Likewise.
* gas/i386/x86-64-opts-intel.d: Likewise.
* gas/i386/x86-64-opts.s: Likewise.
* gas/i386/x86-64-sse2avx-opts.d: Likewise.
* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
opcodes/
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EbS): New.
(EvS): Likewise.
(EMS): Likewise.
(EXqS): Likewise.
(EXxS): Likewise.
(b_swap_mode): Likewise.
(v_swap_mode): Likewise.
(q_swap_mode): Likewise.
(x_swap_mode): Likewise.
(v_mode): Updated.
(w_mode): Likewise.
(t_mode): Likewise.
(xmm_mode): Likewise.
(swap_operand): Likewise.
(dis386): Use EbS on movB. Use EvS on moveS.
(dis386_twobyte): Use EXxS on movapX.
(prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
(vex_table): Use EXxS on vmovapX.
(vex_len_table): Use EXqS on vmovq.
(intel_operand_size): Handle b_swap_mode, v_swap_mode,
q_swap_mode and x_swap_mode.
(OP_E_register): Handle b_swap_mode and v_swap_mode.
(OP_EM): Handle v_swap_mode.
(OP_EX): x_swap_mode and q_swap_mode.
* i386-gen.c (opcode_modifiers): Add S.
* i386-opc.h (S): New.
(Modrm): Updated.
(i386_opcode_modifier): Add s.
* i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
* i386-tbl.h: Regenerated.
2008-12-20 17:40:51 +00:00
a7bea99dc6
gas/testsuite/
...
2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for cmovpe and cmovpo.
* gas/i386/opcode.s: Likewise.
* gas/i386/intel.d: Updated.
* gas/i386/opcode.d: Likewise.
* gas/i386/opcode-intel.d: Likewise.
* gas/i386/opcode-suffix.d: Likewise.
opcodes/
2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add cmovpe and cmovpo.
* i386-tbl.h: Regenerated.
2008-11-03 19:38:09 +00:00
3e12678445
gas/testsuite/
...
2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse2avx.s: Remove pclmulXXX tests. Add tests for
Intel syntax.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/sse2avx.d: Updated.
* gas/i386/x86-64-sse2avx.d: Likewise.
opcodes/
2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
* i386-tbl.h: Regenerated.
2008-09-11 23:15:59 +00:00
ddab3d5917
gas/testsuite/
...
2008-08-28 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.s: Add retf.
* gas/i386/intel.{d,e}: Adjust.
* gas/i386/opcode-intel.d: Replace lret with retf.
opcodes/
2008-08-28 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (dis386): Adjust far return mnemonics.
* i386-opc.tbl: Add retf.
* i386-tbl.h: Re-generate.
2008-08-28 15:59:32 +00:00
515c56e780
gas/testsuite/
...
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for fidivr.
* gas/i386/intel.d: Updated.
opcodes/
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Correct fidivr operand size.
* i386-tbl.h: Regenerated.
2008-08-27 17:53:42 +00:00
a5ff0eb22b
gas/
...
2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (August, 2008)
* config/tc-i386.c (CPU_FLAGS_AES_MATCH): New.
(CPU_FLAGS_AVX_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Updated.
(cpu_flags_match): Likewise.
gas/testsuite/
2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (August, 2008)
* gas/i386/avx.s: Add AES + AVX tests.
* gas/i386/arch-10.s: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and
arch-avx-1-2.
* gas/i386/arch-avx-1.d: New.
* gas/i386/arch-avx-1.s: Likewise.
* gas/i386/arch-avx-1-1.l: Likewise.
* gas/i386/arch-avx-1-1.s: Likewise.
* gas/i386/arch-avx-1-2.l: Likewise.
* gas/i386/arch-avx-1-2.s: Likewise.
opcodes/
2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (August, 2008)
* i386-dis.c (PREFIX_VEX_38DB): New.
(PREFIX_VEX_38DC): Likewise.
(PREFIX_VEX_38DD): Likewise.
(PREFIX_VEX_38DE): Likewise.
(PREFIX_VEX_38DF): Likewise.
(PREFIX_VEX_3ADF): Likewise.
(VEX_LEN_38DB_P_2): Likewise.
(VEX_LEN_38DC_P_2): Likewise.
(VEX_LEN_38DD_P_2): Likewise.
(VEX_LEN_38DE_P_2): Likewise.
(VEX_LEN_38DF_P_2): Likewise.
(VEX_LEN_3ADF_P_2): Likewise.
(PREFIX_VEX_3A04): Updated.
(VEX_LEN_3A06_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
(x86_64_table): Likewise.
(vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
VEX_LEN_3ADF_P_2.
* i386-opc.tbl: Add AES + AVX instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-08-20 18:38:40 +00:00
dfb0759252
gas/testsuite/
...
2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/amd.s: Add syscall and sysret. Remove padding.
* gas/i386/amd.d: Updated.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/i386.exp: Run x86-64-intel64.
* gas/i386/x86-64-intel64.d: New.
* gas/i386/x86-64-intel64.s: Likewise.
* gas/i386/x86-64-opcode.s: Add syscall and sysret.
opcodes/
2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add syscall and sysret for Cpu64.
* i386-tbl.h: Regenerated.
2008-08-12 21:44:56 +00:00
a5dabbb023
gas/testsuite/
...
2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands.
* gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit
operands.
* gas/testsuite/gas/i386/x86-64-avx.d: Updated.
* gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
* gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
opcodes/
2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add vmovd with 64bit operand.
* i386-tbl.h: Regenerated.
2008-05-30 19:49:18 +00:00
cbc80391d0
gas/testsuite/
...
2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and
cvttpd2pi.
* gas/i386/x86-64-sse-noavx.s: Likewise.
* gas/i386/sse-noavx.d: Updated.
* gas/i386/x86-64-sse-noavx.d: Likewise.
opcodes/
2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
* i386-tbl.h: Regenerated.
2008-05-23 00:18:52 +00:00
116615c5f7
gas/testsuite/
...
2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
PR gas/6517
* gas/i386/avx.s: Add tests for unspecified memory operand
size in Intel syntax.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with
unspecified memory operand size in Intel syntax.
* gas/i386/avx.d: Updated.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/simd.d: Likewise.
* gas/i386/simd-intel.d: Likewise.
* gas/i386/simd-suffix.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
opcodes/
2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
PR gas/6517
* i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
into 32bit and 64bit. Remove Reg64|Qword and add
IgnoreSize|No_qSuf on 32bit version.
* i386-tbl.h: Regenerated.
2008-05-22 20:52:54 +00:00
d9479f2d8d
gas/testsuite/
...
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
* gas/i386/x86-64-sse-noavx.s: Likewise.
* gas/i386/sse-noavx.d: Updated.
* gas/i386/x86-64-sse-noavx.d: Likewise.
opcodes/
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
* i386-tbl.h: Regenerated.
2008-05-21 21:40:57 +00:00
f1f8f695c0
gas/
...
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE, EPT and MOVBE.
* config/tc-i386.c (cpu_arch): Add .movbe and .ept.
(md_show_usage): Add .movbe and .ept.
* doc/c-i386.texi: Add movbe and ept to -march=. Document
.movbe and .ept.
gas/testsuite/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
x86-64-inval-ept.
* gas/i386/arch-10.s: Add movbe and invept.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/ept.d: New file
* gas/i386/ept-intel.d: Likewise.
* gas/i386/ept.s: Likewise.
* gas/i386/inval-ept.l: Likewise.
* gas/i386/inval-ept.s: Likewise.
* gas/i386/inval-movbe.l: Likewise.
* gas/i386/inval-movbe.s: Likewise.
* gas/i386/movbe.d: Likewise.
* gas/i386/movbe-intel.d: Likewise.
* gas/i386/movbe.s: Likewise.
* gas/i386/x86-64-inval-ept.l: Likewise.
* gas/i386/x86-64-inval-ept.s: Likewise.
* gas/i386/x86-64-inval-movbe.l: Likewise.
* gas/i386/x86-64-inval-movbe.s: Likewise.
* gas/i386/x86-64-ept.d: Likewise.
* gas/i386/x86-64-ept-intel.d: Likewise.
* gas/i386/x86-64-ept.s: Likewise.
* gas/i386/x86-64-movbe.d: Likewise.
* gas/i386/x86-64-movbe-intel.d: Likewise.
* gas/i386/x86-64-movbe.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOVBE_Fixup): New.
(Mo): Likewise.
(PREFIX_0F3880): Likewise.
(PREFIX_0F3881): Likewise.
(PREFIX_0F38F0): Updated.
(prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
(three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
* i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
CPU_EPT_FLAGS.
(cpu_flags): Add CpuMovbe and CpuEPT.
* i386-opc.h (CpuMovbe): New.
(CpuEPT): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Add cpumovbe and cpuept.
* i386-opc.tbl: Add entries for movbe and EPT instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-05-02 16:53:40 +00:00
81f8a9131a
gas/
...
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Don't check SSE instructions
if noavx is 0.
opcodes/
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add NoAVX.
* i386-opc.h (NoAVX): New.
(OldGcc): Updated.
(i386_opcode_modifier): Add noavx.
* i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
instructions which don't have AVX equivalent.
* i386-tbl.h: Regenerated.
2008-04-22 22:27:13 +00:00
ce886ab1f8
<opcode changes>
...
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>
* i386-opc.tbl: Fix protX to allow memory in the middle operand.
* i386-tbl.h: Regenerate from i386-opc.tbl.
<gas/testsuite changes>
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>
* gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle
operand.
* gas/i386/x86-64-sse5.d: Likewise.
2008-04-16 15:31:33 +00:00
b122c2853a
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.tbl: Remove 4 extra blank lines.
2008-04-07 17:35:12 +00:00
594ab6a333
gas/
...
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
2008-04-04 16:34:23 +00:00
c0f3af977b
binutils/
...
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:21 +00:00
28dbc07952
gas/testsuite/
...
2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect
branches.
* gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect
branches.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
* i386-tbl.h: Regenerated.
2008-03-01 23:30:51 +00:00
849830bdfb
gas/testsuite/
...
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/jump.s: Add tests for far branches.
* gas/i386/jump16.s: Likewise.
* gas/i386/jump.d: Updated.
* gas/i386/jump16.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect
branches.
opcodes/
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Disallow 16-bit near indirect branches for
x86-64.
* i386-tbl.h: Regenerated.
2008-02-23 17:29:17 +00:00
743ddb6b3d
opcodes/
...
2008-02-21 Jan Beulich <jbeulich@novell.com>
* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
and Fword for far indirect jmp. Allow Reg16 and Word for near
indirect jmp on x86-64. Disallow Fword for lcall.
* i386-tbl.h: Re-generate.
2008-02-21 16:18:04 +00:00
34b772a651
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Also special-case 'bound'.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
* gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
gas/i386/opcode-intel.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (a_mode): New.
(cond_jump_mode): Adjust.
(Ma): Change to a_mode.
(intel_operand_size): Handle a_mode.
* i386-opc.tbl: Allow Dword and Qword for bound.
* i386-tbl.h: Re-generate.
2008-02-13 13:29:31 +00:00
475a2301db
gas/testsuite/
...
2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
and x86-64-xsave-intel.
* gas/i386/x86-64-xsave-intel.d: New file.
* gas/i386/x86-64-xsave.d: Likewise.
* gas/i386/x86-64-xsave.s: Likewise.
* gas/i386/xsave-intel.d: Likewise.
* gas/i386/xsave.d: Likewise.
* gas/i386/xsave.s: Likewise.
opcodes/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flags): Add CpuXsave.
* i386-opc.h (CpuXsave): New.
(Cpu64): Updated.
(i386_cpu_flags): Add cpuxsave.
* i386-dis.c (MOD_0FAE_REG_4): New.
(RM_0F01_REG_2): Likewise.
(MOD_0FAE_REG_5): Updated.
(RM_0F01_REG_3): Likewise.
(reg_table): Use MOD_0FAE_REG_4.
(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
for xrstor.
(rm_table): Add RM_0F01_REG_2.
* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-02-12 00:04:45 +00:00
595785c698
opcodes/
...
2008-02-11 Jan Beulich <jbeulich@novell.com>
* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
* i386-tbl.h: Re-generate.
2008-02-11 15:11:06 +00:00
115c7c25fe
gas/
...
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_target_format): Remove cpummx2.
gas/testsuite/
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: New.
* gas/i386/arch-11.s: Likewise.
* gas/i386/arch-12.d: Likewise.
* gas/i386/arch-12.s: Likewise.
* gas/i386/i386.exp: Run arch-11 and arch-12.
opcodes/
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
(cpu_flags): Likewise.
* i386-opc.h (CpuMMX2): Removed.
(CpuSSE): Updated.
* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-22 19:57:30 +00:00
fd07a1c880
gas/testsuite/
...
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/prescott.s: Add tests for movddup in Intel syntax.
* gas/i386/x86-64-prescott.s: Likewise.
* gas/i386/prescott.d: Updated.
* gas/i386/x86-64-prescott.d: Likewise.
opcodes/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Use Qword on movddup.
* i386-tbl.h: Regenerated.
2008-01-16 00:05:56 +00:00
321fd21e2f
gas/
...
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Also zap movzx and movsx
suffix for AT&T syntax.
gas/testsuite/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add more tests for movsx and movzx.
* gas/i386/x86_64.s: Likewise.
* gas/i386/inval.s: Remove tests for movsxw and movzxw.
* gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
movsxl, movzxb and movzxw.
* gas/i386/i386.d: Updated.
* gas/i386/inval.l: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
* i386-tbl.h: Regenerated.
2008-01-15 18:50:44 +00:00
5c07affcae
gas/
...
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_reg_size): New.
(match_mem_size): Likewise.
(operand_size_match): Likewise.
(operand_type_match): Also clear all size fields.
(match_template): Skip Intel syntax when in AT&T syntax.
Call operand_size_match to check operand size.
(i386_att_operand): Set the mem field to 1 for memory
operand.
(i386_intel_operand): Likewise.
gas/testsuite/
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add tests for movsx, movzx and movnti.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/x86-64-inval.s: Likewise.
* gas/i386/i386.d: Updated.
* gas/i386/inval.l: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IntelSyntax.
(operand_types): Add Mem.
* i386-opc.h (IntelSyntax): New.
* i386-opc.h (Mem): New.
(Byte): Updated.
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Add intelsyntax.
(i386_operand_type): Add mem.
* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
instructions.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-15 01:37:56 +00:00
7d5e4556a3
gas/testsuite/
...
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/i386.s: Add tests for fnstsw and fstsw.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/intel.s: Use word instead of dword on ss.
* gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
and out.
* gas/i386/prefix.s: Remove invalid fstsw.
* gas/i386/inval.l: Updated.
* gas/i386/intelbad.l: Likewise.
* gas/i386/i386.d: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/prefix.d: Updated.
gas/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (_i386_insn): Update comment.
(operand_type_match): Also clear unspecified.
(operand_type_register_match): Likewise.
(parse_operands): Initialize unspecified.
(i386_intel_operand): Likewise.
(match_template): Check memory and accumulator operand size.
(i386_att_operand): Clear unspecified on register operand.
(intel_e11): Likewise.
(intel_e09): Set operand size and clean unspecified for
"XXX PTR".
opcodes/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (operand_type_init): Add Dword to
OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
Qword and Xmmword.
(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
Xmmword, Unspecified and Anysize.
(set_bitfield): Make Mmword an alias of Qword. Make Oword
an alias of Xmmword.
* i386-opc.h (CheckSize): Removed.
(Byte): Updated.
(Word): Likewise.
(Dword): Likewise.
(Qword): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(OTMax): Likewise.
(i386_opcode_modifier): Remove checksize, byte, word, dword,
qword and xmmword.
(Fword): New.
(TBYTE): Likewise.
(Unspecified): Likewise.
(Anysize): Likewise.
(i386_operand_type): Add byte, word, dword, fword, qword,
tbyte xmmword, unspecified and anysize.
* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
Tbyte, Xmmword, Unspecified and Anysize.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-12 16:05:42 +00:00
e1d4d8936f
gas/
...
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.
* config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
only.
(md_assemble): Remove Intel mode workaround.
(match_template): Check support for old gcc, AT&T mnemonic
and Intel Syntax.
(md_parse_option): Don't set intel_mnemonic to 0 for
OPTION_MOLD_GCC.
gas/testsuite/
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp,
fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp.
* gas/i386/intel.d: Updated.
* gas/i386/intel.e: Likewise.
opcodes/
2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
ATTSyntax.
* i386-opc.h (IntelMnemonic): Renamed to ..
(ATTSyntax): This
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
and intelsyntax.
* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
* i386-tbl.h: Regenerated.
2008-01-05 17:07:25 +00:00
6f143e4d77
2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-gen.c: Update copyright to 2008.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-04 18:10:08 +00:00
c6add5371c
gas/testsuite/
...
2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/rexw.d: New.
* gas/i386/rexw.s: Likewise.
* gas/i386/x86-64-sse4_1-intel.d: Updated.
* gas/i386/x86-64-sse4_1.d: Likewise.
opcodes/
2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
* i386-tbl.h: Regenerated.
2008-01-04 18:03:02 +00:00
3629bb00a8
gas/
...
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
(cpu_flags_not): Likewise.
(cpu_flags_match): Updated to check 64bit and arch.
(set_code_flag): Remove cpu_arch_flags_not.
(set_16bit_gcc_code_flag): Likewise.
(set_cpu_arch): Likewise.
(md_begin): Likewise.
(parse_insn): Call cpu_flags_match to check 64bit and arch.
(match_template): Likewise.
gas/testsuite/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-9.d: New file.
* gas/i386/arch-9.s: Likewise.
* gas/i386/i386.exp: Run arch-9.
opcodes/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
CpuSSE4_2_Or_ABM.
(cpu_flags): Likewise.
* i386-opc.h (CpuSSE4_1_Or_5): Removed.
(CpuSSE4_2_Or_ABM): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
and CpuPadLock, respectively.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-04 01:05:45 +00:00
e0329a2266
gas/testsuite/
...
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-5.d: New file.
* gas/i386/arch-5.s: Likewise.
* gas/i386/arch-6.d: Likewise.
* gas/i386/arch-6.s: Likewise.
* gas/i386/arch-7.d: Likewise.
* gas/i386/arch-7.s: Likewise.
* gas/i386/arch-8.d: Likewise.
* gas/i386/arch-8.s: Likewise.
* gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.
opcodes/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
CPU_SSE5_FLAGS.
(cpu_flags): Add CpuSSE4_2_Or_ABM.
* i386-opc.h (CpuSSE4_2_Or_ABM): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpusse4_2_or_abm.
* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
CpuABM|CpuSSE4_2 on popcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-03 05:29:53 +00:00
615888ae9f
Fix a typo.
2008-01-03 00:02:26 +00:00
d978b5be20
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
* i386-opc.h: Likewise.
* i386-opc.tbl: Likewise.
2008-01-02 23:54:47 +00:00
582d5eddfe
gas/
...
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
Check memory size in Intel mode.
(process_suffix): Handle XMMWORD_MNEM_SUFFIX.
(intel_e09): Likewise.
* config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
gas/testsuite/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/intel.s: Use QWORD on movq instead of DWORD.
* gas/i386/inval.s: Add tests for movq.
* gas/i386/x86-64-inval.s: Likewise.
* gas/i386/inval.l: Updated.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
Byte, Word, Dword, QWord and Xmmword.
* i386-opc.h (No_xSuf): New.
(CheckSize): Likewise.
(Byte): Likewise.
(Word): Likewise.
(Dword): Likewise.
(QWord): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
Dword, QWord and Xmmword.
* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
used.
* i386-tbl.h: Regenerated.
2008-01-02 21:43:34 +00:00
98b528ac84
gas/testsuite/
...
2007-12-31 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/inval.s: Add test for cvtsi2ss/cvtsi2sd.
* gas/i386/simd.s: Likewise.
* gas/i386/x86-64-simd.s: Likewise.
* gas/i386/inval.l: Updated.
* gas/i386/simd-intel.d: Likewise.
* gas/i386/simd-suffix.d: Likewise.
* gas/i386/simd.d: Likewise.
* gas/i386/sse2.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/x86-64-simd-intel.d: Likewise.
* gas/i386/x86-64-simd-suffix.d: Likewise.
* gas/i386/x86-64-simd.d: Likewise.
opcodes/
2007-12-31 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (prefix_table): Use "%LQ" on cvtpi2ps/cvtsi2sd.
(putop): Handle '%' and "LQ".
* i386-opc.tbl: Remove IgnoreSize from cvtpi2ps/cvtsi2sd.
* i386-tbl.h: Regenerated.
2007-12-31 15:42:22 +00:00
8d79a8c8d5
gas/testsuite/
...
2007-12-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-1.d: New file.
* gas/i386/arch-1.s: Likewise.
* gas/i386/arch-2.d: Likewise.
* gas/i386/arch-2.s: Likewise.
* gas/i386/arch-3.d: Likewise.
* gas/i386/arch-3.s: Likewise.
* gas/i386/arch-4.d: Likewise.
* gas/i386/arch-4.s: Likewise.
* gas/i386/i386.exp: Run arch-1, arch-2, arch-3 and arch-4.
opcodes/
2007-12-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuSSE4_1_Or_5 to
CPU_SSE4_1_FLAGS, CPU_SSE4_2_FLAGS and CPU_SSE5_FLAGS.
(cpu_flags): Add CpuSSE4_1_Or_5.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
* i386-opc.h (CpuSSE4_1_Or_5): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpusse4_1_or_5.
* i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1|CpuSSE5
on ptest roundpd, roundps, roundsd and roundss.
2007-12-28 16:04:41 +00:00
1efbbeb461
gas/
...
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (set_intel_mnemonic): New.
(intel_mnemonic): Likewise.
(old_gcc): Likewise.
(OPTION_MMNEMONIC): Likewise.
(OPTION_MSYNTAX): Likewise.
(OPTION_MINDEX_REG): Likewise.
(OPTION_MNAKED_REG): Likewise.
(OPTION_MOLD_GCC): Likewise.
(md_pseudo_table): Add .intel_mnemonic and .att_mnemonic.
(match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T
mnemonic is specified. Don't allow old gcc support if old_gcc
is 0.
(md_longopts): Add -mmnemonic, -msyntax, -mindex-reg,
-mmnaked-reg and -mold-gcc.
(md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX,
OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC.
* doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg
and AT&T mnemonic vs. Intel mnemonic.
gas/testsuite/
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler.
* gas/i386/compat.d: Likewise.
* gas/i386/i386.exp: Pass -mmnemonic=att to assembler for
"float". Pass -mold-gcc to assembler for "general".
opcodes/
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and
IntelMnemonic.
* i386-opc.h (OldGcc): New.
(ATTMnemonic): Likewise.
(IntelMnemonic): Likewise.
(Opcode_Modifier_Max): Updated.
(i386_opcode_modifier): Add oldgcc, attmnemonic and
intelmnemonic.
* i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul,
fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and
IntelMnemonic.
* i386-tbl.h: Regeneratd.
2007-12-24 05:27:39 +00:00
7ce189b305
gas/
...
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Replace no_xsuf with
no_ldsuf.
(match_template): Likewise.
opcodes/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Replace No_xSuf with
No_ldSuf.
* i386-opc.tbl: Likewise.
* i386-opc.h (No_xSuf): Renamed to ...
(No_ldSuf): This.
(FWait): Updated.
2007-11-01 19:06:54 +00:00
ca61edf2ff
gas/
...
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Check addrprefixop0 to
see if the address size override prefix changes the size of the
first operand.
(check_byte_reg): Don't warn if byteokintel is set.
(check_long_reg): Set i.suffix to QWORD_MNEM_SUFFIX if toqword
is set.
(check_qword_reg): Set i.suffix to LONG_MNEM_SUFFIX if todword
is set.
gas/testsuite/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.d: New.
* gas/i386/i386.s: Likewise.
* gas/i386/i386.exp: Run i386.
* gas/i386/x86_64.s: Add tests for movsx, movsbl, movsbq,
movsbw, movswl, movswq, movzx, movzb, movzbl, movzbq,
movzbw, movzwl and movzwq.
* gas/i386/x86_64.d: Updated.
opcodes/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword,
ToQword and AddrPrefixOp0.
* i386-opc.h (ByteOkIntel): New.
(ToDword): Likewise.
(ToQword): Likewise.
(AddrPrefixOp0): Likewise.
(IsPrefix): Updated.
(i386_opcode_modifier): Add byteokintel, todword, toqword
and addrprefixop0.
* i386-opc.tbl (cvtss2si): Add ToQword.
(cvttss2si): Likewise.
(cvtsd2si): Add ToDword.
(cvttsd2si): Likewise.
(monitor): Add AddrPrefixOp0.
(invlpga): Likewise.
(vmload): Likewise.
(vmrun): Likewise.
(vmsave): Likewise.
(pextrb): Add ByteOkIntel.
(pinsrb): Likewise.
* i386-tbl.h: Regenerated.
2007-11-01 16:27:08 +00:00
e2ec9d29b7
gas/
...
2007-10-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check the firstxmm0
field in opcode_modifier for instruction with a implicit
xmm0 as the first operand.
opcodes/
2007-10-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add FirstXmm0.
* i386-opc.h (FirstXmm0): New.
(IsPrefix): Updated.
(i386_opcode_modifier): Add firstxmm0.
* i386-opc.tbl (blendvpd): Replace RegKludge with FirstXmm0.
(blendvps): Likewise.
(pblendvb): Likewise.
* i386-tbl.h: Regenerated.
2007-10-12 21:40:38 +00:00
H.J. Lu