The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.
gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
The PRU GAS port I originally submitted does not build on 32bit hosts.
This patch fixes it by aligning md_number_to_chars's definition with
the global declaration in tc.h.
Here is the original bug report I got:
https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175
* config/tc-pru.c (md_number_to_chars): Fix parameter to be
valueT, as declared in tc.h.
(md_apply_fix): Fix to work on 32-bit hosts.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify extended operand handling and only specially process immediates
which require bit shuffling, using the generic operand insertion and
extraction handlers for the '<' (5-bit shift amount) operand code in
particular. Require the least significant bit of all extended operand
forms to be (artificially) set to 0 for their special processing to
trigger.
gas/
* config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend'
use to operands whose LSB position is zero.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Simplify processing of
extended operands.
* mips16-opc.c (decode_mips16_operand): Switch the extended
form of the `<' operand type to LSB position 22.
Bail out right away when an unextended instruction encoding is required
either with the use of a `.t' suffix or by means of `.set noautoextend',
however an operand supplied requires the extended instruction form to be
used.
This is to avoid messing up with the internal state of the assembler,
even though no actual failures are known to happen as a result. Add
test cases for the situation concerned.
gas/
* config/tc-mips.c (match_mips16_insn): Don't update
`forced_insn_length' or the instruction opcode if an operand
requires an extended instruction form, but an unextended one
has been requested.
* testsuite/gas/mips/mips16-relax-unextended-1.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-2.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-relax-unextended-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range. No functional change.
gas/
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
include/
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
opcodes/
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Remove special casing for the `6' operand code used for the embedded
trap code of the BREAK and the SDBBP instructions to support supposedly
extended forms of these instructions.
According to all versions of the MIPS16 ASE specifications these
instructions are not extensible [1][2][3][4][5][7][8][10][11], and as
from revision 2.50 of the MIPS16e ASE specifications it has been further
clarified what was previously implied, that non-extesiable instructions
when preceded with an EXTEND prefix must cause a Reserved Instruction
exception [5][6][9][10].
Therefore supposedly extended BREAK and SDBBP instructions do not serve
their purpose anymore as they do not cause a Bp and a Debug exception
respectively and supporting these forms in disassembly only causes
confusion.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] same, Table 18. "Extendable MIPS16 Instructions", p. 24
[4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38
[5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41
[6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41
[7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49
[8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39
[9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42
[10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43
[11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50
gas/
* config/tc-mips.c (match_mips16_insn): Remove the `6' operand
code special case and its associated comment.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
encoding support.
Correct the handling of `.e' and `.t' instruction size suffixes with
instruction mnemonics which are not followed by any text on the same
line, such as arguments or white space, e.g.:
$ cat test.s
.set mips16
foo:
entry.t # comment
entry.t
exit.t # comment
exit.t
nop.t # comment
nop.t
$ as -32 -o test.o test.s
test.s: Assembler messages:
test.s:4: Error: unrecognized opcode `entry.t'
test.s:6: Error: unrecognized opcode `exit.t'
test.s:8: Error: unrecognized opcode `nop.t'
$
gas/
* config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
suffixes followed by a null character rather than a space too.
* testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
* testsuite/gas/mips/mips16-insn-length-noargs.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new test.
Do not allow any explicitly coded EXTEND instruction to be automatically
scheduled into a jump delay slot, as an EXTEND prefix is coupled with
the next regular MIPS16 instruction and therefore swapping it with a
jump would change program's semantics; EXTEND is not architecturally
allowed to be present in a jump delay slot anyway.
opcodes/
* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
"extend".
gas/
* testsuite/gas/mips/mips16-extend-swap.d: New test.
* testsuite/gas/mips/mips16-extend-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
This patch syncs the generated data structure in tc-msp430.c with the
latest version of devices.csv released by TI.
My understanding is that the devices being removed were "invalid spins",
so can't be being used by anyone, and never will be. Current web
searches related to these devices return no relevant results.
Built and tested (no regressions) as follows:
Configured with: --target=msp430-elf --disable-gdb
Test variations:
msp430-sim/-mcpu=msp430
msp430-sim/-mcpu=msp430x
msp430-sim/-mcpu=msp430x/-mlarge/-mdata-region=either/-mcode-region=either
msp430-sim/-mhwmult=none
msp430-sim/-mhwmult=f5series
gas/
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
devices.csv file as of September 2016.
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd). Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.
Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205
* config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
(riscv_frag_align_code): Correct frag_align_code arg.
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Limit MIPS16 instruction disassembly according to the ISA level and ASE
set selected, as with the regular MIPS and microMIPS instruction sets.
Retain the property of `objdump -m mips:16' disassembling all MIPS16
instructions however, regardless of any ISA level recorded in the binary
examined.
To validate the disassembler use the GAS test suite for its convenience
of running tests across multiple ISAs, even though placing the tests in
the binutils test suite would be more appropriate. Adjust the single
binutils test which depends on 64-bit instruction disassembly to have
the ISA level required actually recorded in the binary examined.
opcodes/
* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
(print_insn_mips16): Check opcode entries for validity against
the ISA level and ASE set selected.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module'
rather than `.set' to set the ISA level.
gas/
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add a RESTORE instruction smoke test to the `mips16e' GAS test.
gas/
* testsuite/gas/mips/mips16e.s: Add a RESTORE instruction.
* testsuite/gas/mips/mips16e.d: Adjust accordingly.
Run the `mips16', `mips16-64', `mips16e-64', `mips16-macro',
`mips16-macro-e' and `mips16-macro-t' GAS tests over multiple MIPS16
ISAs.
gas/
* testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16
ISA testing.
* testsuite/gas/mips/mips16-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16-macro.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation.
* testsuite/gas/mips/mips16e-64.l: Rename to...
* testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this.
* testsuite/gas/mips/mips16-64@mips16.d: New test.
* testsuite/gas/mips/mips16-64@mips16-64.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-macro.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64',
`mips16-macro', `mips16-macro-t', `mips16-macro-e' and
`mips16e-64' testing across multiple MIPS16 ISAs. Fold
`mips16-macro' and `mips16e-64' list test invocations into
corresponding dump tests.
Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit
variants of the base MIPS16 and the MIPS16e ISA each.
gas/
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e' and `mips16' prefixes.
(run_list_test_arch): Likewise.
Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
`mips16e-32' and `mips16e-64' architectures. Update `rol64',
`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
accordingly.
* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
* testsuite/gas/mips/mips16e@loc-swap.d: New test.
Pad alignment with zeros rather than NOP instructions, for sensible
multi-ISA MIPS16 testing.
gas/
* testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for
trailing alignment padding.
* testsuite/gas/mips/loc-swap.d: Adjust accordingly.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.
In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.
In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.
include/
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
gas/
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
`insn' together, with `extend' as the high-order 16 bits.
(match_kind): New enum.
(print_insn_mips16): Rework for 32-bit instruction matching.
Do not dump EXTEND prefixes here.
* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
Recode `match' and `mask' fields as 32-bit in absolute "jal" and
"jalx" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
test for separate EXTEND prefix disassembly.
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III
rather than MIPS I ISA. These macros expand to machine code sequences
including 64-bit instructions which require a 64-bit ISA. Entries for
those instructions are already correctly marked, however the marking is
ignored if entries are used in the process of macro expansion rather
than directly, making it possible to indirectly produce 64-bit machine
code even when output requested has been limited to a 32-bit ISA.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
INSN_MACRO entries.
gas/
* testsuite/gas/mips/mips16-macro.l: New list test.
* testsuite/gas/mips/mips.exp: Run the new test.
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor
opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit
instruction requiring a 64-bit ISA. This bug has been there since
forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
opcode).
gas/
* testsuite/gas/mips/mips16-sdrasp.d: New test.
* testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
* testsuite/gas/mips/mips16-sdrasp.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Make sure all tests that require NewABI support are only run with
`has_newabi' targets, removing numerous `mips-sgi-irix5' failures.
gas/
* testsuite/gas/mips/mips.exp: Limit remaining tests that
require NewABI support to `has_newabi' targets.
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI. We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.
Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive. Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.
This patch implements these two new flags and removes the old flags that
could conflict with these. There wasn't a RISC-V release before, so we
want to just support a clean flag set.
include/
* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
* readelf.c (get_machine_flags): Use
EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
* config/tc-riscv.h (xlen): Delete.
* config/tc-riscv.c (xlen): Make static.
(abi_xlen): New variable.
(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
with OPTION_MABI.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(riscv_elf_final_processing): Likewise.
* doc/as.texinfo (Target RISC-V options): Likewise.
* doc/c-riscv.texi (OPTIONS): Likewise.
* config/tc-riscv.c (float_mode): Removed.
(float_abi): New type, specifies the floating-point ABI.
(riscv_set_abi): New function.
(riscv_add_subset): Only allow lower-case ISA names and require
them to start with "rv".
(riscv_after_parse_args): Likewise.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
XLEN when none is provided.
Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them. This patch
significantly reworks how we handle linker relaxations:
* DWARF is now properly supported
* There is a ".option norelax" to disable relaxations, for when users
write assembly that can't be relaxed (if it's to be later patched up,
for example).
* There is an additional _RELAX relocation that specifies when previous
relocations can be relaxed.
We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).
Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!
include/
* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
(BFD_RELOC_RISCV_TPREL_S): Likewise.
(BFD_RELOC_RISCV_RELAX): Likewise.
(BFD_RELOC_RISCV_CFA): Likewise.
(BFD_RELOC_RISCV_SUB6): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET16): Likewise.
(BFD_RELOC_RISCV_SET32): Likewise.
* elfnn-riscv.c (perform_relocation): Handle the new
relocations.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Likewise.
(howto_table): Likewise.
(riscv_reloc_map): Likewise.
(relax_func_t): New type.
(_bfd_riscv_relax_call): Add reserve_size argument, which
controls the maximal offset pessimism. Correct type of max_alignment.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Compute the required reserve size
when relocating and use it to when calling relax_func.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
gas/
* config/tc-riscv.c (riscv_set_options): Add relax.
(riscv_opts): Likewise.
(s_riscv_option): Add relax and norelax.
(riscv_apply_const_reloc): New function.
(append_insn): Move constant relocation handling to
riscv_apply_const_reloc.
(md_pcrel_from): Likewise.
(parse_relocation): Skip BFD_RELOC_UNUSED.
(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
(md_apply_fix): Likewise.
(riscv_pre_output_hook): New function.
* config/tc-riscv.h (md_pre_output_hook): Define.
(riscv_pre_output_hook): Declare.
(DWARF_CIE_DATA_ALIGNMENT): Always -4.
This is a mixed bag of format changes:
* Replacing constants with macros (0xffffffff with MINUS_ONE, for
example). There's one technically functional change in here (some
MINUS_ONEs are changed to 0), but it only changes the behavior of an
otherwise-unused field.
* Using 0 instead of 0x0 in the relocation table.
* There were some missing spaces before parens, the spaces have been
added.
* A handful of comments are now more descriptive.
* A bunch of whitespace-only changes, mostly alignment and brace
newlines.
bfd/
* elfnn-riscv.c: Formatting and comment fixes throughout.
* elfxx-riscv.c: Likewise.
(howto_table): Change the src_mask field from MINUS_ONE to 0 for
R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
* riscv-opc.c: Formatting fixes.
gas/
* config/tc-riscv.c: Formatting and comment fixes throughout.
Complement commit c9775dde32 ("MIPS16: Add R_MIPS16_PC16_S1 branch
relocation support)" and report an assembly error when a relocation is
required for an instruction, currently a branch only, that has been
forced to use its unextended encoding, either with the use of an
explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being
active, fixing an assertion failure currently caused instead.
gas/
* config/tc-mips.c (md_convert_frag): Report an error instead of
asserting on `ext'.
* testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
* testsuite/gas/mips/mips16-branch-unextended.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run the new tests.
Fix the annotation of SP-relative SD instructions incorrectly marked as
reading from the PC rather than SP, which in turn prevented their 16-bit
forms from being scheduled into jump delay slots. This bug has been
there since forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
`pinfo2' with SP-relative "sd" entries.
gas/
* testsuite/gas/mips/mips16-sprel-swap.d: New test.
* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.
After the change, those fields are represented as immediate. Related checks are
added as well.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
qualifier.
(operand_general_constraint_met_p): Remove case for CP_REG.
(aarch64_print_operand): Print CRn, CRm operand using imm field.
* aarch64-tbl.h (QL_SYS): Use CR qualifier.
(QL_SYSL): Likewise.
(aarch64_opcode_table): Change CRn, CRm operand class and type.
* aarch64-opc-2.c : Regenerate.
* aarch64-asm-2.c : Likewise.
* aarch64-dis-2.c : Likewise.
include/
* opcode/aarch64.h (aarch64_operand_class): Remove
AARCH64_OPND_CLASS_CP_REG.
(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
AARCH64_OPND_Cm to AARCH64_OPND_CRm.
(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
gas/
* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
(get_reg_expected_msg): Remove CN register case.
(parse_operands): rewrite parser for CRn, CRm operand.
(reg_names): Remove CN register.
* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.
gas/
* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
include/
* opcode/mips.h: Remove references to `>' operand code.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
Make the `e' operand code used with raw EXTEND instructions use the
hexadecimal rather than decimal format, for consistency with what is
actually produced by code in `print_insn_mips16' dedicated to EXTEND
disassembly. Due to that special handling the operand code is only
interpreted for assembly however, which accepts either format either
way, so there is no functional change here.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
than UINT.
gas/
* testsuite/gas/mips/mips16-extend.d: New test.
* testsuite/gas/mips/mips16-extend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Fix a commit a9752fdf83 ("[ARC] Sync cpu names with the ones accepted
by GCC.") build regression:
cc1: warnings being treated as errors
.../gas/config/tc-arc.c: In function 'arc_show_cpu_list':
.../gas/config/tc-arc.c:3452: error: declaration of 'spaces' shadows a global declaration
.../gas/../include/libiberty.h:248: error: shadowed declaration is here
make[4]: *** [tc-arc.o] Error 1
in a way following commit 91d6fa6a03 ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
gas/
* config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local
variable to `space_buf'.
Fix a commit 008a97eff0 ("[GAS][ARM]Generate unpredictable warning for
pc used in data processing instructions with register-shifted register
operand.") build regression:
cc1: warnings being treated as errors
.../gas/config/tc-arm.c: In function 'encode_arm_shift':
.../gas/config/tc-arm.c:7439: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [tc-arm.o] Error 1
in a way following commit 91d6fa6a03 ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
gas/
* config/tc-arm.c (encode_arm_shift): Rename `index' local
variable to `op_index'.
Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use
a local copy just made in `isa'. No functional change.
gas/
* config/tc-mips.c (is_opcode_valid): Use local `isa'
consistently.
Add support for VCMLA and VCADD advanced SIMD complex number instructions.
The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.
In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.
gas/
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
ARMv8.3 is an architectural extension of ARMv8. Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
include/
* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
(ARM_ARCH_V8_3A): New.
* configure.ac: Add fuchsia to targets that use ELF.
* configure: Regenerated.
bfd * configure.tgt: Add support for fuchsia (OS).
gas * configure.tgt: Add support for fuchsia (OS).
ld * Makefile.am: Add dependency information for earmelf_fuchsia.c.
* Makefile.in: Regenerate.
* configure.tgt: Add support for aarch64-*-fuchsia, arm*-*-fuchsia*, and
x86_64-*-fuchsia* targets.
* emulparams/armelf_fuchsia.sh: New file.
* emulparams/armelfb_fuchsia.sh: New file.
While decoding 32-bit XOP instructions, 64 bit registers names are printed.
This patch fixes this by ignoring REX_B bit in 32-bit mode.
opcodes/
PR binutils/20637
* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
instructions.
gas/
PR binutils/20637
* testsuite/gas/i386/xop32reg.d: New file.
* testsuite/gas/i386/xop32reg.s: New file.
* testsuite/gas/i386/i386.exp: Run new test.
This patch fixes two problems in the SPARC assembler:
- The diagnostic message
Error: Illegal operands: Immediate value in cbcond is out of range.
is incorrectly issued for non-CBCOND instructions that feature a
simm5 immediate field, such as MPMUL, MONTMUL, etc.
- When an invalid immediate operand is used in a CBCOND
instruction, two redundant error messages are issued to the
user, the second due to a stale fixup (this happens since
commit 85024cd8bc).
Some diagnostic tests for the CBCOND instructions are also
included in the patch.
Tested in both sparc64-linux-gnu and sparcv9-linux-gnu targets.
gas/ChangeLog:
2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error
messages for non-cbcond instructions.
* testsuite/gas/sparc/cbcond-diag.s: New file.
* testsuite/gas/sparc/cbcond-diag.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
gas/ChangeLog:
2016-11-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Make sure the
hwcaps-bump test is run with 64-bit objects.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
gas/
2016-11-18 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cl-warn.s: New file.
* testsuite/gas/arc/cpu-pseudop-1.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.s: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.s: Likewise.
* testsuite/gas/arc/cpu-warn2.s: Likewise.
* config/tc-arc.c (selected_cpu): Initialize.
(feature_type): New struct.
(feature_list): New variable.
(arc_check_feature): New function.
(arc_select_cpu): Check for .cpu duplicates. Don't overwrite the
current cpu features. Check if a feature is available for a given
cpu.
(md_parse_option): Test if features are available for a given cpu.
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
PR gas/20732
* expr.c (integer_constant): If tc_allow_L_suffix is defined and
non-zero then accept a L or LL suffix.
* testsuite/gas/sparc/pr20732.d: New test source file.
* testsuite/gas/sparc/pr20732.d: New test output file.
* testsuite/gas/sparc/sparc.exp: Run new test.
Add support for system registers introduced in ARMv8.3
for pointer authentication.
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
(aarch64_sys_reg_supported_p): Add feature test for new registers.
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/sysreg-3.s: New.
* testsuite/gas/aarch64/sysreg-3.d: New.
* testsuite/gas/aarch64/illegal-sysreg-3.l: New.
* testsuite/gas/aarch64/illegal-sysreg-3.d: New.
This patch adds support for a subset of the ARMv8.3 pointer authentication
instructions: XPACLRI, PACIA1716, PACIB1716, AUTIA1716, AUTIA1716, PACIAZ,
PACIASP, PACIBZ, PACISP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP.
These are aliases to HINT #0x7, HINT #0x8, HINT #0xa, HINT #0xc, HINT #0xe,
HINT #0x18, HINT #0x19, ..., HINT #0x1f respectively.
For more details about pointer authentication in ARMv8.3 see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
autibsp.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/system-3.s: New.
* testsuite/gas/aarch64/system-3.d: New.
* testsuite/gas/aarch64/system.d: Update expected output.
ARMv8.3 can be selected with -march=armv8.3-a command line option.
An overview of the ARMv8.3 architecture extension is at
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
* doc/c-aarch64.texi (-march): Likewise.
include/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
(AARCH64_ARCH_V8_3): Define.
(AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all
Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This
patch adds an entry for Bad_Opcode in fgrps to avoid treating it
as FGRPd9_2.
gas/
PR binutils/20775
* testsuite/gas/i386/i386.exp: Run fpu-bad.
* testsuite/gas/i386/fpu-bad.d: New file.
* testsuite/gas/i386/fpu-bad.s: Likewise.
opcodes/
PR binutils/20775
* i386-dis.c (FGRPd9_2): Replace 0 with 1.
(FGRPd9_4): Replace 1 with 2.
(FGRPd9_5): Replace 2 with 3.
(FGRPd9_6): Replace 3 with 4.
(FGRPd9_7): Replace 4 with 5.
(FGRPda_5): Replace 5 with 6.
(FGRPdb_4): Replace 6 with 7.
(FGRPde_3): Replace 7 with 8.
(FGRPdf_4): Replace 8 with 9.
(fgrps): Add an entry for Bad_Opcode.
When we match against an address type operand within an instruction it
is important that we match exactly the right address type operand early
on, during the opcode selection phase. If we wait until the operand
insertion phase to check that we have the correct address operand, then
it is too late to select an alternative opcode. This becomes important
only when we have multiple opcodes with the same mnemonic, and operand
lists that differ only in the type of the address operands.
This commit fixes this issue, and adds some example instructions that
require this issue to be fixed (the instructions are identical except
for the address type operand).
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_operands): Add F_DI14.
(arc_flag_classes): Add C_DI14.
* arc-nps400-tbl.h: Add new exc instructions.
Since the bpp instruction has been added the 16 bit wide pc relative
relocs might occur at offset 2 as well at offset 4 in an instruction.
With this patch the different adjustment is passed from
md_gather_operand to md_apply_fix via fx_pcrel_adjust field in the fix
data structure.
No regressions on s390x.
gas/ChangeLog:
2016-11-04 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Set fx_pcrel_adjust.
(md_apply_fix): Use/Set fx_pcrel_adjust.
* testsuite/gas/s390/zarch-zEC12.d: Add bpp reloc test pattern.
* testsuite/gas/s390/zarch-zEC12.s: Add bpp reloc test.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m33): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M33 processor.
* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m23): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M23 processor.
* NEWS: Mention ARM Cortex-M23 support.
The long immediate operand chosen for one of the ldbit tests is
equivalent to a small negative value that would fit inside an s9
operand, leading to the assembler to choose an unexpected (but
legitimate) encoding of the instruction on 32-bit systems, and
therefore causing the test to fail. This commit fixes the test by
changing the offending limm value so that it can no longer be
interpreted as an s9 operand.
gas/ChangeLog:
* testsuite/gas/arc/nps400-6.s: Change ldbit tests so that
limm operands are out of the range of an s9, in order to fix
the test.
* testsuite/gas/arc/nps400-6.d: Updated to match new expected
output.
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
When assembling an instruction replace the short_insn boolean flag with
an integer field for holding the instruction length. This is in
preparation for moving to a world where instructions can be 2, 4, 6, or
8 bytes in length.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Replace short_insn flag with
len field.
(apply_fixups): Update to use len field.
(emit_insn0): Simplify code, making use of len field.
(md_convert_frag): Update to use len field.
(assemble_insn): Update to use len field.
This adds an option for the Qualcomm falkor core, the corresponding
gcc patch is here:
https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html
This was tested with aarch64 and armhf builds and make check and also
by building and running SPEC2006.
* config/tc-aarch64.c (aarch64_cpus): Add falkor.
* config/tc-arm.c (arm_cpus): Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-arm.texi: Likewise.
In the ARC assembler, when a cpu type is specified using the .cpu
directive, we rely on the bfd list of arc machine types in order to
validate the cpu name passed in.
This validation is only used in order to check that the cpu type passed
to the .cpu directive matches any machine type selected earlier on the
command line. Once that initial check has passed a full check is
performed using the assemblers internal list of know cpu types.
The problem is that the assembler knows about more cpu types than bfd,
some cpu types known by the assembler are actually aliases for a base
cpu type plus a specific set of assembler extensions. One such example
is NPS400, though more could be added later.
This commit removes the need for the assembler to use the bfd list of
machine types for validation. Instead the error checking, to ensure
that any value passed to a '.cpu' directive matches any earlier command
line selection, is moved into the function arc_select_cpu.
I have taken the opportunity to bundle the 4 separate static globals
that describe the currently selected machine type into a single
structure (called selected_cpu).
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delete.
(arc_target_name): Delete.
(arc_features): Delete.
(arc_mach_type): Delete.
(mach_type_specified_p): Delete.
(enum mach_selection_type): New enum.
(mach_selection_mode): New static global.
(selected_cpu): New static global.
(arc_eflag): Rename to ...
(arc_initial_eflag): ...this, and make const.
(arc_select_cpu): Update comment, new parameter, check how
previous machine type selection was made, and record this
selection. Use selected_cpu instead of old globals.
(arc_option): Remove use of arc_get_mach, instead use
arc_select_cpu to validate machine type selection. Use
selected_cpu over old globals.
(allocate_tok): Use selected_cpu over old globals.
(find_opcode_match): Likewise.
(assemble_tokens): Likewise.
(arc_cons_fix_new): Likewise.
(arc_extinsn): Likewise.
(arc_extcorereg): Likewise.
(md_begin): Update default machine type selection, use
selected_cpu over old globals.
(md_parse_option): Update machine type selection option handling,
use selected_cpu over old globals.
* testsuite/gas/arc/nps400-0.s: Add .cpu directive.
bfd/ChangeLog:
* cpu-arc.c (arc_get_mach): Delete.
This reverts commit 95e61695c1. People
still want to use older versions of bison, apparently.
Revert 2016-10-06 Alan Modra <amodra@gmail.com>
* config/rl78-parse.y: Do use old %name-prefix syntax.
* config/rx-parse.y: Likewise.
In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the
the highest bit in VEX.vvvv is either 1 or ignored. In 64-bit, we
need to check invalid mask registers.
gas/
PR binutis/20705
* testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
* testsuite/gas/i386/x86-64-opcode-bad.d: New file.
* testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.
opcodes/
PR binutis/20705
* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
the highest bit in VEX.vvvv for the 3-byte VEX prefix in
32-bit mode. Don't check vex.register_specifier in 32-bit
mode.
(OP_E_register): Check invalid mask registers.
(OP_G): Likewise.
(OP_VEX): Likewise.
The disassember was generating invXXX instructions for cases when in reality we
had llockd or scondd instrutions.
opcodes/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
arc-tbl.h: Removed any "inv.+" instructions from the table.
gas/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
testsuite/arc/dis-inv.s: Test to validate patch.
testsuite/arc/dis-inv.d: Likewise.
The ARC (short) instructions are using a special register number to
indicate is the instruction uses a long immediate (LIMM). In the case
of short instruction, this LIMM indicator depends on the ISA version
used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same
value used in "long" instructions. However, for the ARCv2 processors,
this LIMM indicator is 0x1E.
This patch fixes the LIMM detection for ARCv1 ISA and adds two tests.
gas/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/shortlimm_a7.d: New file.
* testsuite/gas/arc/shortlimm_a7.s: Likewise.
* testsuite/gas/arc/shortlimm_hs.d: Likewise.
* testsuite/gas/arc/shortlimm_hs.s: Likewise.
include/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_OPCODE_ARCV2): New define.
opcodes/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format_from_table): Discriminate LIMM indicator
usage on ISA basis.
The CFI* testcases fail on MIPS64 because the augmentation string does
not match the regexp. This is because MIPS64 doesn't use the default of
4 for DWARF2_FDE_RELOC_SIZE which ends up as "b" in the augmentation
string. MIPS64 uses the address size which is 8 resulting in "c".
Adding c to the regexp fixes a couple of them. Others also need
adjustments in the FDE header lines due to different
sizes/offsets.
gas/ChangeLog:
2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.
* testsuite/gas/cfi/cfi-common-2.d: Likewise.
* testsuite/gas/cfi/cfi-common-3.d: Likewise.
* testsuite/gas/cfi/cfi-common-4.d: Likewise.
* testsuite/gas/cfi/cfi-common-5.d: Likewise.
* testsuite/gas/cfi/cfi-common-7.d: Likewise.
* testsuite/gas/cfi/cfi-common-8.d: Likewise.
* testsuite/gas/cfi/cfi-common-9.d: Likewise.
* testsuite/gas/cfi/cfi-mips-1.d: Likewise.
I noticed a while ago that the rx-elf gas gprel test regressed for no
apparent reason. It turns out that the problem was rx-parse.y using
BFD_RELOC_RX_* values, which may change when other targets add new
relocs. If rx-parse.o doesn't depend on bfd.h, it won't be recompiled.
* Makefile.am (EXTRA_as_new_SOURCES): Add config/rl78-parse.y and
config/rx-parse.y. Move config/bfin-parse.y.
(bfin-parse.@OBJEXT@, rl78-parse.@OBJEXT@, rx-parse.@OBJEXT@): Delete.
($(srcdir)/config/rl78-defs.h): New rule.
* Makefile.in: Regenerate.
The comment logically belongs inside the preprocessor conditional,
but gcc's -Wimplicit-fallthrough loses track of it. Revert when/if
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77817 is fixed.
* app.c (do_scrub_chars): Move fall through comment.
* expr.c (operand): Likewise.
The .cfi_sections directive can be safely used multiple times
with different sections named at any time unless the compact form
of exception handling is requested after CFI information has
been emitted. Only the compact form of CFI information changes
the way in which CFI is generated and therefore cannot be
retrospectively requested after generating CFI information.
gas/
PR gas/20648
* dw2gencfi.c (dot_cfi_sections): Refine the check for
inconsistent .cfi_sections to only consider compact vs non
compact forms.
* testsuite/gas/cfi/cfi-common-9.d: New file.
* testsuite/gas/cfi/cfi-common-9.s: New file.
* testsuite/gas/cfi/cfi.exp: Run new test.
opcode/
PR target/20553
* aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
gas/
* testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
testcases for H and S variants. New low index testcases for D variant.
* testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
This patch adds support for .cfi_val_offset GAS pseudo command which
maps to DW_CFA_val_offset and DW_CFA_val_offset_sf.
gas/ChangeLog:
2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* doc/as.texinfo: Add docu for .cfi_val_offset.
* dw2gencfi.c (cfi_add_CFA_val_offset): New function.
(dot_cfi): Add case for DW_CFA_val_offset.
(output_cfi_insn): Likewise.
(cfi_pseudo_table): Add entry for cfi_val_offset.
* dw2gencfi.h: Add prototype for cfi_add_CFA_val_offset.
* testsuite/gas/cfi/cfi-common-8.d: New test.
* testsuite/gas/cfi/cfi-common-8.s: New test.
* testsuite/gas/cfi/cfi.exp: Run cfi-common-8 testcase.
binutils/ChangeLog:
2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* dwarf.c (display_debug_frames): Adjust output line.
cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.
L field of dcbf and wclr is 2 bits.
PR 20641
include/
* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
* ppc-opc.c (L): Make compulsory.
(LOPT): New, optional form of L.
(HTM_R): Define as LOPT.
(L0, L1): Delete.
(L32OPT): New, optional for 32-bit L.
(L2OPT): New, 2-bit L for dcbf.
(SVC_LEC): Update.
(L2): Define.
(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
<dcbf>: Use L2OPT.
<tlbiel, tlbie>: Use LOPT.
<wclr, wclrall>: Use L2.
gas/
* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker. I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings. This is
consistent with the fact that an older linker won't warn on an
entirely new tag.
include/
* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
(ppc_elf_merge_obj_attributes): Use it. Don't copy first file
attributes, merge them. Don't warn about undefined tag bits,
or copy unknown values to output.
* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
_bfd_elf_ppc_merge_fp_attributes.
binutils/
* readelf.c (display_power_gnu_attribute): Catch truncated section
for all powerpc attributes. Display long double ABI. Don't
capitalize words, except for names. Show known bits of tag values
when some unknown bits are present. Whitespace fixes.
gas/
* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
One of the review comments from the SVE series was that it would
be better to use "must" rather than "should" in error messages.
I think this patch fixes all cases in the AArch64 code.
It also uses "must be" instead of "expected to be".
opcodes/
* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
rather than "should be" or "expected to be" in error messages.
gas/
* config/tc-aarch64.c (output_operand_error_record): Use "must be"
rather than "should be" or "expected to be" in error messages.
(parse_operands): Likewise.
* testsuite/gas/aarch64/diagnostic.l: Likewise.
* testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Likewise.
* testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
This patch adds new tests for SVE. It also extends diagnostic.[sl] with
checks for some inappropriate uses of MUL and MUL VL in base AArch64
instructions.
gas/testsuite/
* gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for
invalid uses of MUL VL and MUL in base AArch64 instructions.
* gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s,
gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s,
gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l,
gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d,
gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s,
gas/aarch64/sve.d: New tests.
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
This patch adds support for the new SVE floating-point immediate
operands. One operand uses the same 8-bit encoding as base AArch64,
but in a different position. The others use a single bit to select
between two values.
One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding. I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.
As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error. This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:
fcpy z0, #2.5
In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision. Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
immediate operands.
* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
* aarch64-opc.c (fields): Add corresponding entry.
(operand_general_constraint_met_p): Handle the new SVE FP immediate
operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
(ins_sve_float_zero_one): New inserters.
* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
(aarch64_ins_sve_float_half_two): Likewise.
(aarch64_ins_sve_float_zero_one): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
(ext_sve_float_zero_one): New extractors.
* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
(aarch64_ext_sve_float_half_two): Likewise.
(aarch64_ext_sve_float_zero_one): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (double_precision_operand_p): New function.
(parse_operands): Use it to calculate the dp_p input to
parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
The SVE instructions have two enumerated operands: one to select a
vector pattern and another to select a prefetch operation. The latter
is a cut-down version of the base AArch64 prefetch operation.
Both types of operand can also be specified as raw enum values such as #31.
Reserved values can only be specified this way.
If it hadn't been for the pattern operand, I would have been tempted
to use the existing parsing for prefetch operations and add extra
checks for SVE. However, since the patterns needed new enum parsing
code anyway, it seeemed cleaner to reuse it for the prefetches too.
Because of the small number of enum values, I don't think we'd gain
anything by using hash tables.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
(AARCH64_OPND_SVE_PRFOP): Likewise.
(aarch64_sve_pattern_array): Declare.
(aarch64_sve_prfop_array): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
* aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
(FLD_SVE_prfop): Likewise.
* aarch64-opc.c: Include libiberty.h.
(aarch64_sve_pattern_array): New variable.
(aarch64_sve_prfop_array): Likewise.
(fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_enum_string): New function.
(po_enum_or_fail): New macro.
(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.
include/
* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
(AARCH64_OPND_QLF_P_M): Likewise.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
AARCH64_OPND_QLF_P_[ZM].
(aarch64_print_operand): Print /z and /m where appropriate.
gas/
* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
(parse_vector_type_for_operand): Assert that the skipped character
is a '.'.
(parse_predication_for_operand): New function.
(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
(vectype_to_qualifier): Handle NT_zero and NT_merge.
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
SVE predicate operands can appear in three forms:
1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"
No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped. Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing". This means that some Pg operands have
suffixes and others don't.
It would be possible to use context-sensitive parsing to handle
this difference. The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.
However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier. The normal qualifier matching code can then report cases
where the wrong kind of suffix is used. This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.
The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here. It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.
This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions. The behaviour
for other instructions doesn't change.
include/
* opcode/aarch64.h (F_STRICT): New flag.
opcodes/
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
gas/
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main. I think we
can just get rid of them and leave the callers to check the addressing
modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).
The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks. This again creates a corner case where:
.equ x2, 1
ldr w0, [x1], x2
was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.
Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.
ADDR_SIMM9_2 appers to be unused. I'll send a separate patch
to remove it.
This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.
gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things. It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.
SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough. It's more convenient to pass the type of register around as
a qualifier instead.
As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.
Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted. We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants. This is easier to do if the function returns the
reg_entry rather than just the register number.
This does create a corner case where:
.equ sp, 1
ldr w0, [x0, sp]
was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:
.equ sp, 1
add x0, x1, sp
To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE. The next patch also relies on this.
Finally, aarcch64_check_reg_type was written in a pretty
conservative way. It should always be equivalent to a single
bit test.
gas/
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number. Return the type as a qualifier rather than an
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise. Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.
Since some SVE constants are no longer explicitly tied to the 8-bit
FP immediate format, it seems better to move the range checks out of
parse_aarch64_imm_float and into the callers.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
(parse_operands): Check the range of 8-bit FP immediates here instead.
Previously:
fmov d0, #2
would give an error:
Operand 2 should be an integer register
whereas the user probably just forgot to add the ".0" to make:
fmov d0, #2.0
This patch reports an invalid floating point constant unless the
operand is obviously a register.
The FPIMM8 handling is only relevant for SVE. Without it:
fmov z0, z1
would try to parse z1 as an integer immediate zero (the res2 path),
whereas it's more likely that the user forgot the predicate. This is
tested by the final patch.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
low-severity error for registers.
(parse_operands): Report an invalid floating point constant for
if parsing an FPIMM8 fails, and if no better error has been
recorded.
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
to FMOV.
SVE has single-bit floating-point constants that don't really
have any relation to the AArch64 8-bit floating-point encoding.
(E.g. one of the constants selects between 0 and 1.) The easiest
way of representing them in the aarch64_opnd_info seemed to be
to use the IEEE float representation directly, rather than invent
some new scheme.
This patch paves the way for that by making the code that converts IEEE
doubles to IEEE floats accept any value in the range of an IEEE float,
not just zero and 8-bit floats. It leaves the range checking to the
caller (which already handles it).
gas/
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
to...
(can_convert_double_to_float): ...this. Accept any double-precision
value that converts to single precision without loss of precision.
(parse_aarch64_imm_float): Update accordingly.
To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:
.equ x0, 0
add v0.4s, v0.4s, x0
An explicit '#' must be used instead:
.equ x0, 0
add v0.4s, v0.4s, #x0
Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time. For backwards
compatibility, we should continue to allow things like:
.equ p0, 0
add v0.4s, v0.4s, p0
even though p0 is now an SVE register.
However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable. Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.
As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject. This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.
gas/
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.
Rename parse_neon_reg_list to parse_vector_reg_list and take
in the required register type as an argument. Later patches
will reuse the function for SVE registers.
gas/
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.
Generalise the name of parse_neon_type_for_operand to
parse_vector_type_for_operand. Later patches will add SVEisms to it.
gas/
* config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
(parse_vector_type_for_operand): ...this.
(parse_typed_reg): Update accordingly.
Similar to the previous patch, but this time for the neon_type_el
structure.
gas/
* config/tc-aarch64.c (neon_type_el): Rename to...
(vector_type_el): ...this.
(parse_neon_type_for_operand): Update accordingly.
(parse_typed_reg): Likewise.
(aarch64_reg_parse): Likewise.
(vectype_to_qualifier): Likewise.
(parse_operands): Likewise.
(eq_neon_type_el): Likewise. Rename to...
(eq_vector_type_el): ...this.
(parse_neon_reg_list): Update accordingly.
Later patches will add SVEisms to neon_el_type, so this patch renames
it to something more generic.
gas/
* config/tc-aarch64.c (neon_el_type: Rename to...
(vector_el_type): ...this.
(neon_type_el): Update accordingly.
(parse_neon_type_for_operand): Likewise.
(vectype_to_qualifier): Likewise.
A false return from parse_neon_operand_type had an overloaded
meaning: either the parsing failed, or there was nothing to parse
(which isn't necessarily an error). The only caller, parse_typed_reg,
would therefore not consume the suffix if it was invalid but instead
(successfully) parse the register without a suffix. It would still
leave inst.parsing_error with an error about the invalid suffix.
It seems wrong for a successful parse to leave an error message,
so this patch makes parse_typed_reg return PARSE_FAIL instead.
The patch doesn't seem to make much difference in practice.
Most possible follow-on errors use set_first_error and so the
error about the suffix tended to win despite the successful parse.
gas/
* config/tc-aarch64.c (parse_neon_operand_type): Delete.
(parse_typed_reg): Call parse_neon_type_for_operand directly.
For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or
2-operand, or a single operand instruction format, depending on the
values present in i-field, and a-field.
The disassembler is reading the section containing the extension
instruction format and stores them in a table. Each table element
represents a linked list with encodings for a particular MAJOR-MINOR
tuple.
The current implementation checks only against the first element of
the list, hence, the issue.
This patch is walking the linked list until empty or finds an opcode
match. It also adds a test outlining the found problem.
opcodes/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
gas/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
gas/ChangeLog:
2016-09-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v9 only in ELF targets to avoid spurious failures in
sparc-aout and sparc-coff targets.
Merely dumping the mnemonic name in "architecture mismatch" errors may
not provide enough information to determine what went wrong, as the same
mnemonic can be used for different variants of an instruction pertaining
to different architecture levels.
This little patch makes the assembler to include the instruction
arguments in the error message.
gas/ChangeLog:
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Print the instruction arguments
in "architecture mismatch" error messages.
Before SPARC V9 the effect of having a delayed branch instruction in the
delay slot of a conditional delayed branch was undefined.
In SPARC V9 DCTI couples are well defined.
However, starting with the UltraSPARC Architecture 2005, DCTI
couples (of all kind) are deprecated and should not be used, as they may
be slow or behave differently to what the programmer expects.
This patch adds a new command line option --dcti-couples-detect to `as',
disabled by default, that makes the assembler to warn the user if an
unpredictable DCTI couple is found. Tests and documentation are
included.
gas/ChangeLog:
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (md_assemble): Detect and warning on
unpredictable DCTI couples in certain arches.
(dcti_couples_detect): New global.
(md_longopts): Add command line option -dcti-couples-detect.
(md_show_usage): Document -dcti-couples-detect.
(md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests.
* testsuite/gas/sparc/dcti-couples.s: New file.
* testsuite/gas/sparc/dcti-couples-v9c.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9c.l: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.l: Likewise.
* doc/as.texinfo (Overview): Document --dcti-couples-detect.
* doc/c-sparc.texi (Sparc-Opts): Likewise.
The assembler accepts dtpoff complex relocation expression like
identifier@dtpoff + const. However, it doesn't accept an expression such
as identifier@dtpoff@base + const. This patch solves this issue, and adds
a number of tests.
ld/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/tls-dtpoff.dd: New file.
* testsuite/ld-arc/tls-dtpoff.rd: Likewise.
* testsuite/ld-arc/tls-dtpoff.s: Likewise.
* testsuite/ld-arc/tls-relocs.ld: Likewise.
* testsuite/ld-arc/arc.exp: Add new tdpoff test.
gas/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/tls-relocs2.d: New file.
* testsuite/gas/arc/tls-relocs2.s: Likewise.
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
is used.
This patch adds alternate CPU names which adhere to the number of the
architecture document. So instead of having z196, zEC12, and z13 you
can use arch9, arch10, and arch11. The old cpu names stay valid and
should primarily be used.
The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.
opcodes/ChangeLog:
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Support alternate arch strings.
gas/ChangeLog:
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Support alternate arch
strings.
* doc/as.texinfo: Document new arch strings.
* doc/c-s390.texi: Likewise.
Originally only Pentium integer instructions are allowed for IAMCU.
This patch removes such a restriction. For example, 387 and SSE2
instructions can be enabled by passing "-march=iamcu+sse2+387" to
assembler.
gas/
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
(set_cpu_arch): Updated.
(md_parse_option): Likewise.
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
iamcu-inval-2 and iamcu-inval-3.
* testsuite/gas/i386/iamcu-4.d: New file.
* testsuite/gas/i386/iamcu-4.s: Likewise.
* testsuite/gas/i386/iamcu-5.d: Likewise.
* testsuite/gas/i386/iamcu-5.s: Likewise.
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
* i386-init.h: Regenerated.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
ARMv8-A CPUs except xgene1.
ELF section sh_flags SHF_PPC_VLE was being set based on arch/mach,
which meant all code sections in an object file has the flag or all
lacked it. We can do better than that. Only those code sections
where VLE is enabled ought to have the flag, allowing an object file
to contain both VLE and non-VLE code.
Also, ELF header p_flags PF_PPC_VLE wasn't being set, and segments
were being split unnecessarily.
bfd/
* elf32-ppc.c (ppc_elf_section_processing): Delete.
(elf_backend_section_processing): Don't define.
(ppc_elf_modify_segment_map): Set p_flags and mark valid. Don't
split on non-exec sections differing in SHF_PPC_VLE. When
splitting segments, mark size invalid.
gas/
* config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
ppc_cpu rather than calling ppc_mach to determine VLE mode.
(ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
This patch fixes a typo in the mnemonic of the camellia_fl
instruction, which was implemented before as camellia_fi.
gas/ChangeLog:
2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/crypto.d: Rename invalid opcode camellia_fi
to camellia_fl.
* testsuite/gas/sparc/crypto.s: Likewise.
opcodes/ChangeLog:
2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
camellia_fl.
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
parse_aarch64_imm_float was accepting -0.0 even though that's not
a valid immediate for any instruction. The FPIMM0 caller rejected
it, but the FPIMM one would silently treat it as -2.0.
This patch rejects -0.0 and adds testcases to illegal.[sd].
Before the patch, the final error emitted for illegal.s was:
Error: cannot do 16-byte relocation
which was matched by:
[^:]*:569: Error: .*
The error was reported against the last line of the file rather than
the instruction that required the reloc. Adding more instructions
meant that the line number also changed.
Reporting against the wrong line isn't good from a QoI perspective
but isn't what I'm trying to fix here. Until it's fixed, I thought
it would be better to adjust the match to be against an end-of-file
comment rather than against whatever the last instruction happens to be.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0.
* testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l:
Add tests for -0.0. Add an end-of-file comment.
PR gas/20429
* config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16
registers are pushed.
(do_vfp_nsyn_pop): Check that no more than 16 registers are
popped.
* testsuite/gas/arm/pr20429.s: New test.
* testsuite/gas/arm/pr20429.d: New test driver.
* testsuite/gas/arm/pr20429.1: Expected error output.
PR gas/20364
* config/tc-aarch64.c (s_ltorg): Change the mapping state after
aligning the frag.
(aarch64_init): Treat rs_align frags in code sections as
containing code, not data.
* testsuite/gas/aarch64/pr20364.s: New test.
* testsuite/gas/aarch64/pr20364.d: New test driver.
Many of the existing sparc tests fail in non-ELF targets (coff and
a.out) due to spurious differences in the expected results:
- Unlike ELF, a.out text sections are aligned to 2**3 and padded
accordingly. The padding instruction is a `nop' (01 00 00 00).
- Likewise, coff text sections are also aligned to 2**3 and padded
accordingly. However, the padding instruction in these targets is an
`illtrap 0' (00 00 00 00).
- Unlike ELF, a.out and coff binaries don't contain hardware
capabilities bits that could be used by BFD to determine the opcodes
architecture corresponding to the instructions encoded in the
objects (v9, v9a, v9b, v9c, etc). Consequently, in both a.out and
coff tests we would need to pass proper `-m sparc:vXXX' options when
invoking objdump before comparing results.
In order to fix these issues, the most obvious solution would be to have
three variants of .d files per impacted test. For example, for save.d
we would have: save-elf.d, save-aout.d and save-coff.d. Using the
`#source' directive, a single save.s file would provide the input for
all of them. However, this approach has the following problems:
- The #target and #notarget .d directives are very limited: they use
globs instead of regular expressions, and thus it is not possible (or
too messy) to use them to discriminate between elf, coff and a.out
sparc targets.
- It adds little or no value to have variants of all these tests for all
the target types, and it would be a burden to maintain them. Actually
the features tested in the spuriously failing tests (relatively modern
sparc instructions, registers and asis) are not really found in
running coff or a.out sparc systems.
This patch changes sparc.exp so it will run these tests only in
ELF-targets, using the more standard `is_elf_format' from
binutils-common.exp instead of the ad-hoc (and less convenient, as it
must be called before _every_ single elf-only test) sparc_elf_setup.
Incidentally, the patch also fixes the #name entry for save-args.d.
Tested in sparc*-*-linux-gnu, sparc-aout and sparc-coff targets.
gas/ChangeLog:
2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
ELF targets.
Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
targets.
(sparc_elf_setup): Delete.
* testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
test's #name entry.
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.
Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous. This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has. Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.
Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form. For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction. A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.
Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well. We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded. Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.
For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.
gas/
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
Remove R_MIPS_PC26_S2 and R_MIPS_PC21_S2 relocation references that went
into `mips_force_relocation' with commit 9d862524f6 ("MIPS: Verify the
ISA mode and alignment of branch and jump targets") by mistake. Their
BFD_RELOC_MIPS_26_PCREL_S2 and BFD_RELOC_MIPS_21_PCREL_S2 equivalents
are already handled there.
gas/
* config/tc-mips.c (mips_force_relocation): Remove
R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX,
similarly to how JAL instructions are converted.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode
BAL to JALX.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a
corresponding error message.
gas/
* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
Adjust comments for BAL to JALX linker conversion.
(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
expected.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
* testsuite/gas/mips/branch-local-4.d: New test.
* testsuite/gas/mips/branch-local-n32-4.d: New test.
* testsuite/gas/mips/branch-local-n64-4.d: New test.
* testsuite/gas/mips/branch-addend.d: New test.
* testsuite/gas/mips/branch-addend-n32.d: New test.
* testsuite/gas/mips/branch-addend-n64.d: New test.
* testsuite/gas/mips/branch-local-4.s: New test source.
* testsuite/gas/mips/branch-addend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-branch-2.d: Update error
messages expected.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise.
* testsuite/ld-mips-elf/bal-jalx-addend.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test
source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code. Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.
Also make jump target's alignment verification consistent with that for
branches.
This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only. These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).
Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes. It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
Compatibility", p. 533
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
Compatibility", p. 623
bfd/
* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
(branch_reloc_p): New function.
(mips_elf_calculate_relocation): Handle ISA mode determination
for relocations against section symbols, against absolute
symbols and absolute relocations. Also set `*cross_mode_jump_p'
for branches.
<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
checks for weak undefined symbols. Also check target alignment
within the same ISA mode.
<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
in the alignment check.
<R_MICROMIPS_PC7_S1>: Add an alignment check.
<R_MICROMIPS_PC10_S1>: Likewise.
<R_MICROMIPS_PC16_S1>: Likewise.
(mips_elf_perform_relocation): Report a failure for unsupported
same-mode JALX instructions and cross-mode branches.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
error messages for jumps to misaligned addresses.
gas/
* config/tc-mips.c (mips_force_relocation): Also retain branch
relocations against MIPS16 and microMIPS symbols.
(fix_bad_cross_mode_jump_p): New function.
(fix_bad_same_mode_jalx_p): Likewise.
(fix_bad_misaligned_jump_p): Likewise.
(fix_bad_cross_mode_branch_p): Likewise.
(fix_bad_misaligned_branch_p): Likewise.
(fix_validate_branch): Likewise.
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
etc. Verify the ISA mode and alignment of the jump target.
<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
with a call to `fix_validate_branch'.
<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
<BFD_RELOC_16_PCREL_S2>: Likewise.
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
Verify the ISA mode and alignment of the branch target.
(md_convert_frag): Verify the ISA mode and alignment of resolved
MIPS16 branch targets.
* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
branch targets with `.insn'.
* testsuite/gas/mips/branch-misc-5.s: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
accordingly.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Annotate
non-instruction branch target with `.insn'.
* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
with external symbols.
* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
targets with `.insn'.
* testsuite/gas/mips/mips16.d: Update accordingly.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
branch target with `.insn'.
* testsuite/gas/mips/relax-swap3.s: Likewise.
* testsuite/gas/mips/branch-local-2.l: New list test.
* testsuite/gas/mips/branch-local-3.l: New list test.
* testsuite/gas/mips/branch-local-n32-2.l: New list test.
* testsuite/gas/mips/branch-local-n32-3.l: New list test.
* testsuite/gas/mips/branch-local-n64-2.l: New list test.
* testsuite/gas/mips/branch-local-n64-3.l: New list test.
* testsuite/gas/mips/unaligned-jump-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-3.d: New test.
* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
* testsuite/gas/mips/unaligned-branch-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-3.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
* testsuite/gas/mips/branch-local-2.s: New test source.
* testsuite/gas/mips/branch-local-3.s: New test source.
* testsuite/gas/mips/branch-local-n32-2.s: New test source.
* testsuite/gas/mips/branch-local-n32-3.s: New test source.
* testsuite/gas/mips/branch-local-n64-2.s: New test source.
* testsuite/gas/mips/branch-local-n64-3.s: New test source.
* testsuite/gas/mips/unaligned-jump-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
expected.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
microMIPS BAL and MIPS16 instructions.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update
accordingly.
* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
It can be initialized with values greater than 0x80000000, which don't fit in a
signed int. Further it appears to be used as a set of bit flags where unsigned
int is more typical.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (struct nds32_pseudo_opcode): Make pseudo_val
unsigned int.
(do_pseudo_b): Adjust.
(do_pseudo_bal): Likewise.
(do_pseudo_bge): Likewise.
(do_pseudo_bges): Likewise.
(do_pseudo_bgt): Likewise.
(do_pseudo_bgts): Likewise.
(do_pseudo_ble): Likewise.
(do_pseudo_bles): Likewise.
(do_pseudo_blt): Likewise.
(do_pseudo_blts): Likewise.
(do_pseudo_br): Likewise.
(do_pseudo_bral): Likewise.
(do_pseudo_la): Likewise.
(do_pseudo_li): Likewise.
(do_pseudo_ls_bhw): Likewise.
(do_pseudo_ls_bhwp): Likewise.
(do_pseudo_ls_bhwpc): Likewise.
(do_pseudo_ls_bhwi): Likewise.
(do_pseudo_move): Likewise.
(do_pseudo_neg): Likewise.
(do_pseudo_not): Likewise.
(do_pseudo_pushpopm): Likewise.
(do_pseudo_pushpop): Likewise.
(do_pseudo_v3push): Likewise.
(do_pseudo_v3pop): Likewise.
(do_pseudo_pushpop_stack): Likewise.
(do_pseudo_push_bhwd): Likewise.
(do_pseudo_pop_bhwd): Likewise.
(do_pseudo_pusha): Likewise.
(do_pseudo_pushi): Likewise.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (struct pop_entry): Make the type of reloc
bfd_reloc_code_real_type.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-z8k.c (newfix): Make type of type argument
bfd_reloc_code_real_type.
(apply_fix): Likewise.
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend. This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.
As an example assembling this program:
$ cat test.s
.text
foo:
b bar
b baz
.set bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s
produces this binary code:
$ objdump -dr test-o32.o test-n32.o
test-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
test-n32.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*+0x1230
4: 00000000 nop
8: 10000000 b c <foo+0xc>
8: R_MIPS_PC16 baz-0x4
c: 00000000 nop
$
where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word. In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.
Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise. This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.
Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function. The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.
With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:
$ objdump -dr fixed-o32.o
fixed-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000048c b 1234 <bar>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
$
Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used. Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
bfd/
* reloc.c (bfd_perform_relocation): Try the `howto' handler
first with relocations against absolute symbols.
(bfd_install_relocation): Likewise.
gas/
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/branch-absolute.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `branch-absolute-addend' and
`micromips-branch-absolute-addend', referred indirectly only.
Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c95 ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e ("Add in a JALRC
alias and fix the NAL instruction."). As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.
The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':
$ cat test.s
.text
foo:
nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o
nal.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo> 04100000 0x4100000
...
$
This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.
Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code. Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people. This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code. Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.
Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.
Add a suitable test case to the GAS test suite. While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
annotation from the "nal" entry and reorder it beyond "bltzal".
gas/
* testsuite/gas/mips/nal-1.d: New test.
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
* testsuite/gas/mips/nal-2.d: New test.
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
* testsuite/gas/mips/nal.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch adds support for the LDTXA instructions, along with the
corresponding ASIs. Tests for GAS are included.
opcodes/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (ldtxa): New macro.
(sparc_opcodes): Use the macro defined above to add entries for
the LDTXA instructions.
(asi_table): Add the ASI_TWINX_* asis used in the LDTXA
instruction.
gas/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/ldtxa.s: New file.
* testsuite/gas/sparc/ldtxa.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
gas/ChangeLog:
2016-07-05 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is
no longer needed.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Complement:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), and remove a call to
`install_insn' from `append_insn', which as from that change has become
redundant. This is because such a call, to place an instruction's bit
pattern in output, is already made from `move_insn', called from
`add_relaxed_insn' or `add_fixed_insn' as appropriate, either of which
now always is and has to be made from `append_insn' before the repeated
call to `install_insn' is made. Previously the place where this second
invocation is made was the only one where the output stream was updated,
although the update was made inline rather than with a function call.
Remove the repeated call then, to reclaim some performance.
gas/
* config/tc-mips.c (append_insn): Remove extraneous
`install_insn' call.
A missing 'r' (or wrong 'e') register prefix needs to be complained
about if the template allows for a 64-bit register, not a 32-bit one.
I assume this was a copy-and-paste type of mistake
(from check_long_reg()).
Move `branch-misc-2' tests for non locally-defined-global symbols into
separate files. These tests have been introduced with:
commit 6f171daac9
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Thu Dec 12 04:40:22 2002 +0000
<https://sourceware.org/ml/binutils/2002-11/msg00631.html>, ("mips:
branches to external labels are broken"), and:
commit d17b874b6c
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Wed Mar 12 23:07:22 2003 +0000
<https://sourceware.org/ml/binutils/2003-03/msg00136.html>, ("On
resolving the MIPS gas branch reloc issue"), while the test case served
a different purpose. With the original intent of the test case brought
back with:
commit bad36eacda
Author: Daniel Jacobowitz <drow@false.org>
Date: Wed Nov 23 14:04:18 2005 +0000
<https://sourceware.org/ml/binutils/2005-11/msg00324.html>,
("R_MIPS_PC16, again"), these stand in the way for linker testing.
gas/
* testsuite/gas/mips/branch-misc-2.s: Move non
locally-defined-global symbol tests...
* testsuite/gas/mips/branch-misc-5.s: ... to this new test.
* testsuite/gas/mips/branch-misc-2.d: Update accordingly.
* testsuite/gas/mips/branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/branch-misc-5.d: New test.
* testsuite/gas/mips/branch-misc-5pic.d: New test.
* testsuite/gas/mips/branch-misc-5-64.d: New test.
* testsuite/gas/mips/branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
Feature flag handling was not perfect, +nofp16 disabled fp
instructions too.
New feature flag macros were added to check features with multiple
bits set (matters for FP_F16 and SIMD_F16 opcode feature tests).
The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should
use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE
now checks all feature bits.
The aarch64_features table now contains the dependencies as
a separate field (so when the feature is enabled all dependencies
are enabled and when it is disabled everything that depends on it
is disabled).
Note that armv8-a+foo+nofoo is not equivalent to armv8-a if
+foo turns on dependent features that nofoo does not turn off.
gas/
* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
require field.
(aarch64_features): Initialize require fields.
(aarch64_parse_features): Handle dependencies.
(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
* testsuite/gas/aarch64/illegal-nofp16.s: New.
* testsuite/gas/aarch64/illegal-nofp16.l: New.
* testsuite/gas/aarch64/illegal-nofp16.d: New.
include/
* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
(AARCH64_CPU_HAS_ANY_FEATURES): New.
(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
(AARCH64_OPCODE_HAS_FEATURE): Remove.
binutuils* prdbg.c (pr_enum_type): Use a buffer big enough to hold an
extremely large decimal value.
(pr_range_type): Likewise.
(pr_array_type): Likewise.
(pr_struct_field): Likewise.
(pr_class_baseclass): Likewise.
(pr_class_method_variant): Likewise.
(pr_tag_type): Likewise.
(pr_int_constant): Likewise.
(pr_typed_constant): Likewise.
(pr_variable): Likewise.
(pr_function_parameter): Likewise.
(pr_start_block): Likewise.
(pr_lineno): Likewise.
(pr_end_block): Likewise.
(tg_enum_type): Likewise.
(tg_int_constant): Likewise.
(tg_typed_constant): Likewise.
(tg_start_block): Likewise.
gas * macro.c (macro_expand_body): Use a buffer big enough to hold an
extremely large integer.
While address overrides are ignored in 64-bit mode (and hence shouldn't
really result in an error, but upon v1 converting this to a warning I
was told otherwise), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt. (The
added test case at once also checks that bndc{l,n,u} won't accept
16-bit register operands.)
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
Fix an assertion failure like:
test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.
triggered by assembling MIPS16 code like:
hello:
addiu $4, $4, 4
jr $31
with the generation of a listing file enabled, e.g.:
$ as -mips16 -O2 -aln=test.lst
The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag. It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.
This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.
This effectively complements:
commit 464ab0e55a
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Mon Aug 6 20:33:00 2012 +0000
<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.
The assertion itself was introduced with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.
gas/
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
case MIPS16 handling.
* testsuite/gas/mips/branch-swap-3.d: New test.
* testsuite/gas/mips/branch-swap-4.d: New test.
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
* testsuite/gas/mips/branch-swap-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify non-MIPS16 branch swapping by copying the MIPS16 variant, which
sets the new position for the current instruction first and reduces the
calculation of the new position of the previous instruction. Also refer
to previous instruction's frag and position via `delay' for consistency.
Reintroduce an explanatory comment, updated, previously removed with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]").
gas/
* config/tc-mips.c (append_insn): Simplify non-MIPS16 branch
swapping sequence.
Correct a regression from commit 85024cd8bc ("Run write_object_file
after errors") causing unsuccessful assembly, which may be due to any
reason, such as supplying a valid source like this:
.text
.byte 0
.err
to terminate with an assertion failure like:
test.s: Assembler messages:
test.s:3: Error: .err encountered
../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg
../as-new: Please report this bug.
on targets whose default text section alignment is above 0, typically
RISC machines.
This is due to an attempt to set last text section's frag alignment to
0, requested from `subsegs_finish_section' where `frag_align_code
(alignment, 0)' is called with `alignment' set to 0 rather than the
section alignment if `had_errors' has returned true. The call to
`subsegs_finish_section' is made from `subsegs_finish' from
`write_object_file' at unsuccessful completion, which previously wasn't
made.
Always set last section's frag alignment from the section alignment
then, forcing no section padding instead if completing unsuccessfully,
so that in that case alignment padding is still suppressed from any
listing generated, fixing assertion failures for these targets:
alpha-linuxecoff -FAIL: all pr20312
arm-aout -FAIL: all pr20312
mips-freebsd -FAIL: all pr20312
mips-img-linux -FAIL: all pr20312
mips-linux -FAIL: all pr20312
mips-mti-linux -FAIL: all pr20312
mips-netbsd -FAIL: all pr20312
mips-sgi-irix5 -FAIL: all pr20312
mips-sgi-irix6 -FAIL: all pr20312
mips-vxworks -FAIL: all pr20312
mips64-freebsd -FAIL: all pr20312
mips64-img-linux -FAIL: all pr20312
mips64-linux -FAIL: all pr20312
mips64-mti-linux -FAIL: all pr20312
mips64-openbsd -FAIL: all pr20312
mips64el-freebsd -FAIL: all pr20312
mips64el-img-linux -FAIL: all pr20312
mips64el-linux -FAIL: all pr20312
mips64el-mti-linux -FAIL: all pr20312
mips64el-openbsd -FAIL: all pr20312
mipsel-freebsd -FAIL: all pr20312
mipsel-img-linux -FAIL: all pr20312
mipsel-linux -FAIL: all pr20312
mipsel-mti-linux -FAIL: all pr20312
mipsel-netbsd -FAIL: all pr20312
mipsel-vxworks -FAIL: all pr20312
mipsisa32-linux -FAIL: all pr20312
mipsisa32el-linux -FAIL: all pr20312
mipsisa64-linux -FAIL: all pr20312
mipsisa64el-linux -FAIL: all pr20312
sh-pe -FAIL: all pr20312
sparc-aout -FAIL: all pr20312
gas/
PR gas/20312
* write.c (subsegs_finish_section): Force no section padding to
alignment on failed assembly, always set last frag's alignment
from section.
* testsuite/gas/all/pr20312.l: New list test.
* testsuite/gas/all/pr20312.s: New test source.
* testsuite/gas/all/gas.exp: Run the new test
GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a
when assembling NEON instructions. The patch corrects this, making
-march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions
introduced with ARMv8.1-A.
include/
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
of enabled FPU features.
gas/
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/arm/armv8_2+rdma.d: New.
--enable-compressed-debug-sections=gas added to binutils 2.26. Make it
default for Linux/x86 targets in 2.27.
* NEWS: Mention --enable-compressed-debug-sections=gas is the
default for Linux/x86 targets.
* configure.tgt (ac_default_compressed_debug_sections): Default
to yes for Linux/x86 targets.
Remove an internal diagnostic regression introduced with the inclusion of
"libbfd.h" from write.c, added with:
commit e7ff5c732e
Author: Alan Modra <amodra@gmail.com>
Date: Fri Feb 16 03:40:17 2007 +0000
That change made "libbfd.h" override the `abort' definition provided by
"as.h" earlier on, making the message produced by any calls reached from
write.c, which is a part of the GAS proper, look like they came from
BFD, e.g.:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg
../as-new: Please report this bug.
vs:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
.../gas/testsuite/gas/elf/type.s: Internal error, aborting at .../gas/write.c:602 in size_seg
Please report this bug.
With the removal of "libbfd.h" restore the latter message format.
gas/
* write.c: Remove "libbfd.h" inclusion.
Complement commit a43942db49 ("LD/ELF: Unify STB_GNU_UNIQUE handling")
and use `supports_gnu_unique' with the `unique_symbol' and `type' tests,
fixing failures like:
.../binutils/testsuite/binutils-all/unique.s: Assembler messages:
.../binutils/testsuite/binutils-all/unique.s:2: Error: symbol type "gnu_unique_object" is supported only by GNU targets
ERROR: .../binutils/testsuite/binutils-all/unique.s: assembly failed
UNRESOLVED: ar unique symbol in archive
.../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o
Executing on host: .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o (timeout = 300)
.../binutils/ar: tmpdir/unique.o: No such file or directory
FAIL: ar unique symbol in archive
and:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg
../as-new: Please report this bug.
.../gas/testsuite/../../binutils/readelf -s dump.o | grep "1 *\[FIONTCU\]" > dump.out
Executing on host: sh -c {.../gas/testsuite/../../binutils/readelf -s dump.o >readelf.out 2>gas.stderr} /dev/null (timeout = 300)
readelf: Error: dump.o: Failed to read file's magic number
FAIL: elf type list
on MIPS/FreeBSD targets:
mips-freebsd -FAIL: ar unique symbol in archive
mips-freebsd -FAIL: elf type list
mips64-freebsd -FAIL: ar unique symbol in archive
mips64-freebsd -FAIL: elf type list
mips64el-freebsd -FAIL: ar unique symbol in archive
mips64el-freebsd -FAIL: elf type list
mipsel-freebsd -FAIL: ar unique symbol in archive
mipsel-freebsd -FAIL: elf type list
binutils/
* testsuite/binutils-all/ar.exp: Use `supports_gnu_unique' with
the `unique_symbol' test.
gas/
* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
`type' test.
aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked. This meant large invalid indices could be silently
truncated to smaller valid indices.
The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index. I went for the latter for two
reasons:
- Doing the range checking in operand_general_constraint_met_p
seems structurally cleaner than doing it while parsing.
- The bitfields didn't really buy us anything. The imm field
of the union is already 128 bits, so we can use a full int64_t
index without growing the structure.
The patch also adds missing range checks for the elements in a register
list index.
include/
* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
opcodes/
* aarch64-opc.c (operand_general_constraint_met_p): Check the
range of ldst_elemlist operands.
(print_register_list): Use PRIi64 to print the index.
(aarch64_print_operand): Likewise.
gas/
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
cfi_add_CFA_def_cfa to generate default CFA with offset
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
PR gas/20247
* as.h (do_not_pad_sections_to_alignment): New global variable.
* as.c (show_usage): Add --no-pad-sections.
(parse_args): Likewise.
* write.c (size_seg): Skip padding the end of the section if
requested from the command line.
(SUB_SEGMENT_ALIGN): Likewise.
* doc/as.texinfo: Document the new option.
* NEWS: Mention the new feature.
* testsuite/gas/elf/section11.s: New test.
* testsuite/gas/elf/section11.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
gas/ChangeLog:
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal
element in relax_table.
its only called with an argument of 0, so we might as well remove the code
supporting other values.
gas/ChangeLog:
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_set_default_include): remove argument
and simplify accordingly.
(tic54x_include): Adjust.
(tic54x_mlib): Likewise.
Correct a MIPS16 relocation handling regression in GAS introduced with:
commit 177b4a6ad0
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Mon Mar 18 18:56:18 2002 +0000
discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>,
which removed a preparatory call to `mips16_extended_frag' previously
made from `md_estimate_size_before_relax'. As a result the function is
never called with its `sec' parameter non-NULL and consequently all the
unsupported relocation checks within are dead and never trigger, causing
any unhandled relocations to silently resolve to 0. Unfortunately there
was no sufficient test suite coverage back then to catch this.
Remove all dead code then, and all the associated comments. Update the
remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass
the relocation section as the `sec' parameter and use it to mark frags
which require an external relocation, as extended. Finally handle any
outstanding MIPS16 relocations in `md_convert_frag' and report an error
since we don't support any except with percent operators.
gas/
* config/tc-mips.c (append_insn): Use any `O_symbol' expression
unchanged with relaxed MIPS16 instructions.
(mips16_extended_frag): Adjust accordingly. Return 1 right
away if a relocation will be required for the symbol requested.
Remove dead first relaxation pass code.
(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
(md_convert_frag): Adjust symbol value calculation. Raise an
error if a relocation is required for the symbol requested.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
add error output.
* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
* testsuite/gas/mips/mips16-branch-absolute.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Keep original microMIPS symbols in references from branch relocations so
that the ISA bit is retained and can be verified for validity in static
link. No need to update WRT MIPS16 symbols because we keep them all
anyway for other reasons.
gas/
* config/tc-mips.c (b_reloc_p): New function.
(mips_fix_adjustable): Also keep the original microMIPS symbol
referred from branch relocations.
* testsuite/gas/mips/branch-local-1.d: New test.
* testsuite/gas/mips/branch-local-n32-1.d: New test.
* testsuite/gas/mips/branch-local-n64-1.d: New test.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
relocations.
* testsuite/gas/mips/branch-local-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new cases.
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
There's no reason to define these macros twice.
gas/ChangeLog:
2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c: Include elf/xtensa.h.
Complement commit 7361da2c95 ("Add support for MIPS R6.") and fix
internal errors like:
foo.s: Assembler messages:
foo.s: Internal error!
Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028.
Please report this bug.
triggered by resolved R6 PC-relative relocations in sources containing
R6 code fragments wrapped into ISA override blocks embedded within code
otherwise assembled for an older ISA.
gas/
* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
<BFD_RELOC_LO16_PCREL>: New switch cases.
(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
Move switch cases along `BFD_RELOC_MIPS_JMP'.
<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
the resolved case.
* testsuite/gas/mips/pcrel-reloc-4.d: New test.
* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-5.d: New test.
* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Avoid segmentation faults in alignment checks made in `md_apply_fix' for
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2 relocations
caused by dereferencing `fixP->fx_addsy' which will be null if the
relocation processed has been fully resolved.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3>
<BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences
via `fixP->fx_addsy'.
The PC-relative R_MIPS_PC18_S3 relocation and consequently its BFD
internal BFD_RELOC_MIPS_18_PCREL_S3 representation is calculated from
the address of the aligned doubleword containing the location being
relocated: (sign_extend(A) + S - (P & ~0x7)) >> 3 rather than the
address of the location itself. Reflect this in calculations made by
GAS so that the relocated field is set correctly if resolved by GAS,
such as with local symbols in the same section which do not require
relocations to be propagated to the link stage.
gas/
* config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>:
Calculate relocation from the containing aligned doubleword.
(tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the
addend from the containing aligned doubleword.
Use the module level ISA setting rather than the last ISA selected with
a `.set' directive in the source file in determination as to whether to
keep PC-relative relocations and then with the original symbol referred,
for the purpose of R6 linker relaxation.
This is so that with e.g. code like this:
b foo
.set mips32r2
...
it's the command line options or any `.module' directive that decides
how to encode any relocation for `foo' rather than the presence of `.set
mips32r2'.
gas/
* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
rather than `mips_opts' for the R6 ISA check.
(mips_fix_adjustable): Likewise.
* testsuite/gas/mips/pcrel-reloc-1.d: New test.
* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-2.d: New test.
* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-3.d: New test.
* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Complement commit 44d3da2338 ("MIPS/GAS: Treat local jump relocs the
same no matter if REL or RELA") and update and clarify the comment on
jump reloc conversion.
gas/
* config/tc-mips.c (mips_fix_adjustable): Update comment on jump
reloc conversion.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
The current sparc assembler breaks when the name of an ancillary-state
register, privileged register or hyperprivileged register has a
%-pseudo-operation name as a prefix. For example, %hmcdper and %hm(),
or %hintp and %hi().
This patch fixes it by introducing a new table `perc_table' (for
%-table) that contains an entry for every %name supported by the
assembler, other than the general registers. This table is used to
detect name collisions when the assembler tries to detect a %-pseudo-op.
This patch also fixes a related bug, making sure that v9a_asr_table and
hpriv_reg_table are sorted in reverse lexicographic order, as otherwise
the search code may fail.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (priv_reg_table): Use NULL instead of the
empty string to mark the end of the array.
(hpriv_reg_table): Likewise.
(v9a_asr_table): Likewise.
(cmp_reg_entry): Handle entries with NULL names.
(F_POP_V9): Define.
(F_POP_PCREL): Likewise.
(F_POP_TLS_CALL): Likewise.
(F_POP_POSTFIX): Likewise.
(struct pop_entry): New type.
(pop_table): New variable.
(enum pop_entry_type): New type.
(struct perc_entry): Likewise.
(NUM_PERC_ENTRIES): Define.
(perc_table): New variable.
(cmp_perc_entry): New function.
(md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize
perc_table.
(sparc_ip): Handle entries with NULL names in priv_reg_table,
hpriv_reg_table and v9a_asr_table. Use perc_table to handle
%-pseudo-ops.
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20
reloc.
gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
instruction size.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mn10200.c (md_assemble): Likewise.
* config/tc-moxie.c (md_assemble): Likewise.
* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
exception targets. Add alpha, hppa, microblaze and rl78 to list
of exceptions.
(forward): Add microblaze to list of exceptions.
(fwdexp): Add alpha to list of exceptions.
(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
(do_930509a): Alpha sort list of exception targets. Add h8300 and
mn10200 to list of exceptions.
(align2): Expect to fail for nds32.
(cond): Add alpha and rl78 to list of exceptions.
* testsuite/gas/all/none.d: Skip for ft32 and hppa.
* testsuite/gas/all/string.d: Skip for tic4x.
* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
target does not support ELF.
* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH
tests for sh-pe and sh-rtemscoff targets.
* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
list of exceptions.
(type): Run the noifunc version for alpha-freebsd and visium.
* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
mn10200 or moxie targets.
* testsuite/gas/ft32/insn.d: Update expected disassembly.
* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
targets.
* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
mcore and rx targets.
* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
rl78 and vax.
(purge): Expect to fail on the ns32k and vax.
* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
* testsuite/gas/nds32/ls.d: Likewise.
* testsuite/gas/nds32/sys-reg.d: Likewise.
* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
* testsuite/gas/pe/section-align-3.d: Likewise.
* testsuite/gas/pe/section-exclude.d: Likewise.
* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
data has been seen.
* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
for variations in whitespace.
* testsuite/gas/tilepro/t_constants.d: Pass once all the required
data has been seen.
* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
Installs a 32-bit value without generating warnings on 64-bit
hosts.
Use the new macro to replace the .word directives.
opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
constants to match expected behaviour.
(nds32_parse_opcode): Likewise. Also for whitespace.
The extract function used for some arc_s instructions was not
implemented, and instead always returned 0. Fixed in this commit.
opcodes/ChangeLog:
* arc-opc.c (extract_rhv1): Extract value from insn.
gas/ChangeLog:
* testsuite/gas/arc/add_s.d: New file.
* testsuite/gas/arc/add_s.s: New file.
This commit adds the ldbit instruction for the NPS-400. The ldbit
instruction uses the same encoding as the ld instruction, but sets
the ZZ field to 11 (which is a reserved setting), and sets the AA
field to 1 or 2 for the x2 and x4 flags respectively.
With the exception of ldbit, this commit adds implementations of
all DPI instructions for the NPS-400. These instructions are:
- hash / hash.p[0-3]
- tr
- utf8
- e4by
- addf
Revert an inadvertent change to make RELA JALR relocations
section-relative on MIPS R6 targets made with commit 7361da2c95 ("Add
support for MIPS R6."). There is no need to make this a special case
and the comment introduced with the said change clearly indicates this
was not intended.
gas/
* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
JALR relocations on R6.
* testsuite/gas/mips/jal-svr4pic-local.d: New test.
* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
etc * texi2pod.pl: Escape curly braces, whilst searching for keyword
strong.
gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets
that are not supported.
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
constant.
* config/tc-cr16.c (check_range): Likewise.
* config/tc-nios2.c (nios2_check_overflow): Likewise.
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.
gas/
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
(arm_ext_ras): Renamed from arm_ext_v8_2.
(insns): Update for arm_ext_v8_2 renaming.
(arm_extensions): Add "ras".
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
* testsuite/gas/arm/armv8-a+ras.d: New.
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
options.
include/
* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
entries.
(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
opcodes/
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
ARM_EXT_RAS in relevant entries.
The values are always members of the enum, except the two places -1 is assigned
only to playcate -Wuninitialized because gcc isn't or at least didn't used to
be smart enough to figure out its only used if it was set.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sh.c (parse_reg): Change type of mode argument to
sh_arg_type.
(get_operand): Adjust.
(insert): Change type of how to bfd_reloc_code_real_type.
(insert4): Likewise.
* config/tc-sh64.c (shmedia_get_operand): Adjust.
(shmedia_parse_reg): Change type of mode to shmedia_arg_type.
it points to the result of strchr on a const char *, so it aliases
something that is const. Further its only passed to a function that expects a
const char *, so there's no reason for it to not be const.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg
const char *.
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.
gas/
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
This seems a little easier to understand than using a sentinal, and will
hopefully let the compiler optimize the loop better. It also has the effect
that we stop initializing a field of the sentinal that is an enum with zero.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (avr_parse_cons_expression): Replace iteration to
sentinal with iteration to array size.
I think this is the more typical way to do this. Its also slightly shorter and
less repeditive.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/xtensa-relax.h: Move typedefs of enums to the enums
definition.
Szabolcs Nagy
Norm Jacobs
Kito Cheng
Dimitar Dimitrov
Alan Modra
Maciej W. Rozycki
Joe Seymour
Tristan Gingold
Andrew Waterman
Tim Newsome
Renlin Li
Jiong Wang
Nick Clifton
Claudiu Zissulescu
Josh Conner
Amit Pawar
Ambrogino Modigliani
Jose E. Marchesi
Kuan-Lin Chen
Anthony Green
H.J. Lu
Nathan Sidwell
Andrew Burgess
Andreas Krebbel
Thomas Preud'homme
Palmer Dabbelt
Graham Markall
Siddhesh Poyarekar
Igor Tsimbalist
Cupertino Miranda
Matthew Fortune
Trevor Saunders
Vlad Zakharov
Richard Sandiford
Peter Bergner
Patrick Steuer
Richard Earnshaw
Tamar Christina
Stefan Trleman
Jan Beulich
Matthew Wahab
Vineet Gupta
Virendra Pathak
Kyrylo Tkachov
Vineet Gupta