2016-12-19 07:53:53 +01:00
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
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INSN_ALIAS.
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2016-12-19 07:53:52 +01:00
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
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format.
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Re-work RISC-V gas flags: now we just support -mabi and -march
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI. We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.
Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive. Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.
This patch implements these two new flags and removes the old flags that
could conflict with these. There wasn't a RISC-V release before, so we
want to just support a clean flag set.
include/
* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
* readelf.c (get_machine_flags): Use
EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
* config/tc-riscv.h (xlen): Delete.
* config/tc-riscv.c (xlen): Make static.
(abi_xlen): New variable.
(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
with OPTION_MABI.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(riscv_elf_final_processing): Likewise.
* doc/as.texinfo (Target RISC-V options): Likewise.
* doc/c-riscv.texi (OPTIONS): Likewise.
* config/tc-riscv.c (float_mode): Removed.
(float_abi): New type, specifies the floating-point ABI.
(riscv_set_abi): New function.
(riscv_add_subset): Only allow lower-case ISA names and require
them to start with "rv".
(riscv_after_parse_args): Likewise.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
XLEN when none is provided.
2016-12-19 07:53:50 +01:00
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
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XLEN when none is provided.
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2016-12-19 07:53:47 +01:00
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c: Formatting fixes.
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2016-12-20 02:18:21 +01:00
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2016-12-20 Alan Modra <amodra@gmail.com>
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
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* Makefile.in: Regenerate.
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* po/POTFILES.in: Regenerate.
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2016-12-19 12:35:14 +01:00
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2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
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Only examine ELF file structures here.
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2016-12-19 12:32:05 +01:00
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2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
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`bfd_mips_elf_get_abiflags' here.
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2016-12-16 11:59:36 +01:00
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2016-12-16 Nick Clifton <nickc@redhat.com>
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* arm-dis.c (print_insn_thumb32): Fix compile time warning
|
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computing value_in_comment.
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2016-12-14 22:49:56 +01:00
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2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (mips_convert_abiflags_ases): New function.
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(set_default_mips_dis_options): Also infer ASE flags from ELF
|
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file structures.
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2016-12-14 22:27:00 +01:00
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2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (set_default_mips_dis_options): Reorder ELF file
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header flag interpretation code.
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2016-12-14 22:18:16 +01:00
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2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
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`pinfo2' with SP-relative "sd" entries.
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2016-12-14 22:14:33 +01:00
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2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
|
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compact jumps.
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2016-12-13 13:37:18 +01:00
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2016-12-13 Renlin Li <renlin.li@arm.com>
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* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
|
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qualifier.
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(operand_general_constraint_met_p): Remove case for CP_REG.
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(aarch64_print_operand): Print CRn, CRm operand using imm field.
|
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* aarch64-tbl.h (QL_SYS): Use CR qualifier.
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(QL_SYSL): Likewise.
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(aarch64_opcode_table): Change CRn, CRm operand class and type.
|
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* aarch64-opc-2.c : Regenerate.
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* aarch64-asm-2.c : Likewise.
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* aarch64-dis-2.c : Likewise.
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2016-12-12 10:03:34 +01:00
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2016-12-12 Yao Qi <yao.qi@linaro.org>
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* rx-dis.c: Include <setjmp.h>
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(struct private): New.
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(rx_get_byte): Check return value of read_memory_func, and
|
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call memory_error_func and OPCODES_SIGLONGJMP on error.
|
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(print_insn_rx): Call OPCODES_SIGSETJMP.
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2016-12-12 10:03:34 +01:00
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2016-12-12 Yao Qi <yao.qi@linaro.org>
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* rl78-dis.c: Include <setjmp.h>.
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(struct private): New.
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(rl78_get_byte): Check return value of read_memory_func, and
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call memory_error_func and OPCODES_SIGLONGJMP on error.
|
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(print_insn_rl78_common): Call OPCODES_SIGJMP.
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2016-12-10 00:11:40 +01:00
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2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
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2016-12-09 23:50:07 +01:00
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2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
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than UINT.
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2016-12-09 23:27:00 +01:00
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2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_mips16): Use a tab rather than a space
|
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to separate `extend' and its uninterpreted argument output.
|
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Separate hexadecimal halves of undecoded extended instructions
|
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output.
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2016-12-09 00:29:37 +01:00
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2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_mips16_insn_arg): Remove extraneous
|
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indentation space across.
|
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2016-12-09 00:29:01 +01:00
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2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
|
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adjustment for PC-relative operations following MIPS16e compact
|
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jumps or undefined RR/J(AL)R(C) encodings.
|
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2016-12-08 23:51:44 +01:00
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2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
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* aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
|
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variable to `reglane_index'.
|
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2016-12-08 14:25:09 +01:00
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|
2016-12-08 Luis Machado <lgustavo@codesourcery.com>
|
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* ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
|
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|
2016-12-07 03:55:27 +01:00
|
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2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips-dis.c (print_mips16_insn_arg): Fix comment typo.
|
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2016-12-07 03:53:03 +01:00
|
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2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips16-opc.c (mips16_opcodes): Update comment naming structure
|
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members.
|
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2016-12-07 03:35:33 +01:00
|
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2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips-dis.c (print_mips_disassembler_options): Reformat output.
|
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2016-12-05 15:24:17 +01:00
|
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|
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
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* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
|
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(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
|
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2016-12-05 15:13:27 +01:00
|
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|
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
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* arm-dis.c (coprocessor_opcodes): Add vjcvt.
|
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2016-12-01 11:26:32 +01:00
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|
2016-12-01 Nick Clifton <nickc@redhat.com>
|
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|
|
PR binutils/20893
|
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* i386-dis.c (OP_VEX): Replace call to abort with a append of bad
|
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|
opcode designator.
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[ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
2016-11-15 15:11:47 +01:00
|
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|
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-opc.c (insert_ra_chk): New function.
|
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|
(insert_rb_chk): Likewise.
|
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|
|
(insert_rad): Update text error message.
|
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|
|
(insert_rcd): Likewise.
|
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|
|
(insert_rhv2): Likewise.
|
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|
(insert_r0): Likewise.
|
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|
(insert_r1): Likewise.
|
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|
(insert_r2): Likewise.
|
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|
(insert_r3): Likewise.
|
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|
(insert_sp): Likewise.
|
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|
(insert_gp): Likewise.
|
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|
(insert_pcl): Likewise.
|
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|
(insert_blink): Likewise.
|
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|
(insert_ilink1): Likewise.
|
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|
(insert_ilink2): Likewise.
|
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|
(insert_ras): Likewise.
|
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|
(insert_rbs): Likewise.
|
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|
(insert_rcs): Likewise.
|
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(insert_simm3s): Likewise.
|
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(insert_rrange): Likewise.
|
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|
(insert_fpel): Likewise.
|
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(insert_blinkel): Likewise.
|
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(insert_pcel): Likewise.
|
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(insert_nps_3bit_dst): Likewise.
|
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|
(insert_nps_3bit_dst_short): Likewise.
|
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|
|
(insert_nps_3bit_src2_short): Likewise.
|
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|
|
(insert_nps_bitop_size_2b): Likewise.
|
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|
|
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
|
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|
|
(RA_CHK): Define.
|
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|
(RB): Adjust.
|
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|
(RB_CHK): Define.
|
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|
(RC): Adjust.
|
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|
|
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
|
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|
|
* arc-tbl.h (div, divu): All instructions are DIVREM class.
|
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|
|
Change first insn argument to check for LP_COUNT usage.
|
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|
|
(rem): Likewise.
|
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|
|
(ld, ldd): All instructions are LOAD class. Change first insn
|
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|
|
|
argument to check for LP_COUNT usage.
|
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|
|
(st, std): All instructions are STORE class.
|
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|
|
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
|
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|
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|
|
Change first insn argument to check for LP_COUNT usage.
|
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|
|
(mov): All instructions are MOVE class. Change first insn
|
|
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|
|
argument to check for LP_COUNT usage.
|
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|
|
2016-10-06 12:05:27 +02:00
|
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|
|
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
|
* arc-dis.c (is_compatible_p): Remove function.
|
|
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|
|
|
(skip_this_opcode): Don't add any decoding class to decode list.
|
|
|
|
|
|
Remove warning.
|
|
|
|
|
|
(find_format_from_table): Go through all opcodes, and warn if we
|
|
|
|
|
|
use a guessed mnemonic.
|
|
|
|
|
|
|
2016-11-28 18:21:05 +01:00
|
|
|
|
2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
|
|
|
|
|
|
Amit Pawar <amit.pawar@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20637
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2016-11-22 16:43:03 +01:00
|
|
|
|
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
|
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|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 13:40:37 +01:00
|
|
|
|
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (HWS_V8): Definition moved from
|
|
|
|
|
|
gas/config/tc-sparc.c.
|
|
|
|
|
|
(HWS_V9): Likewise.
|
|
|
|
|
|
(HWS_VA): Likewise.
|
|
|
|
|
|
(HWS_VB): Likewise.
|
|
|
|
|
|
(HWS_VC): Likewise.
|
|
|
|
|
|
(HWS_VD): Likewise.
|
|
|
|
|
|
(HWS_VE): Likewise.
|
|
|
|
|
|
(HWS_VV): Likewise.
|
|
|
|
|
|
(HWS_VM): Likewise.
|
|
|
|
|
|
(HWS2_VM): Likewise.
|
|
|
|
|
|
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
|
|
|
|
|
|
existing entries.
|
|
|
|
|
|
|
2016-11-09 15:30:35 +01:00
|
|
|
|
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 11:02:16 +01:00
|
|
|
|
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
|
|
|
|
|
|
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
|
|
|
|
|
|
(aarch64_opcode_table): Add fcmla and fcadd.
|
|
|
|
|
|
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
|
|
|
|
|
|
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
|
|
|
|
|
|
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
|
|
|
|
|
|
(operand_general_constraint_met_p): Rotate and index range check.
|
|
|
|
|
|
(aarch64_print_operand): Handle rotate operand.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
2016-11-18 10:58:38 +01:00
|
|
|
|
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2016-11-18 10:53:45 +01:00
|
|
|
|
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
|
|
|
|
|
|
(QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2016-11-18 10:49:06 +01:00
|
|
|
|
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_X1NIL): New.
|
|
|
|
|
|
(arch64_opcode_table): Add ldraa, ldrab.
|
|
|
|
|
|
(AARCH64_OPERANDS): Add "ADDR_SIMM10".
|
|
|
|
|
|
* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
|
|
|
|
|
|
* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add data for FLD_S_simm10.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64] Add ARMv8.3 combined pointer authentication branch instructions
Add support for ARMv8.3 pointer authentication instructions
that are encoded as unconditional branch instructions.
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/pac.s: Add ARMv8.3 branch instruction tests.
* testsuite/gas/aarch64/pac.d: Likewise.
2016-11-11 11:43:15 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
|
|
|
|
|
|
brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2016-11-11 11:39:46 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (arch64_opcode_table): Add pacga.
|
|
|
|
|
|
(AARCH64_OPERANDS): Add Rm_SP.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64] Add ARMv8.3 single source PAC instructions
Add support for ARMv8.3 pointer authentication instructions
that are encoded as single source data processing instructions.
opcodes/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
autdzb, xpaci, xpacd.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/testsuite/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/pac.s: New.
* testsuite/gas/aarch64/pac.d: New.
2016-11-11 11:36:32 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
|
|
|
|
|
|
autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
|
|
|
|
|
|
autdzb, xpaci, xpacd.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2016-11-11 11:33:30 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
|
|
|
|
|
|
apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
|
|
|
|
|
|
apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
|
|
|
|
|
|
(aarch64_sys_reg_supported_p): Add feature test for new registers.
|
|
|
|
|
|
|
[AArch64] Add ARMv8.3 instructions which are in the NOP space
This patch adds support for a subset of the ARMv8.3 pointer authentication
instructions: XPACLRI, PACIA1716, PACIB1716, AUTIA1716, AUTIA1716, PACIAZ,
PACIASP, PACIBZ, PACISP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP.
These are aliases to HINT #0x7, HINT #0x8, HINT #0xa, HINT #0xc, HINT #0xe,
HINT #0x18, HINT #0x19, ..., HINT #0x1f respectively.
For more details about pointer authentication in ARMv8.3 see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
autibsp.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/system-3.s: New.
* testsuite/gas/aarch64/system-3.d: New.
* testsuite/gas/aarch64/system.d: Update expected output.
2016-11-11 11:29:07 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
|
|
|
|
|
|
(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
|
|
|
|
|
|
autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
|
|
|
|
|
|
autibsp.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
2016-11-11 11:22:56 +01:00
|
|
|
|
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
|
|
|
|
|
|
|
2016-11-09 23:00:18 +01:00
|
|
|
|
2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20799
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
|
|
|
|
|
|
* i386-dis.c (EdqwS): Removed.
|
|
|
|
|
|
(dqw_swap_mode): Likewise.
|
|
|
|
|
|
(intel_operand_size): Don't check dqw_swap_mode.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_E_memory): Likewise.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
(OP_EX): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Remove "S" from EVEX vpextrw.
|
|
|
|
|
|
* i386-tbl.h: Regerated.
|
|
|
|
|
|
|
2016-11-09 19:20:13 +01:00
|
|
|
|
2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Merge AVX512F vmovq.
|
2016-11-09 22:44:42 +01:00
|
|
|
|
* i386-tbl.h: Regerated.
|
2016-11-09 19:20:13 +01:00
|
|
|
|
|
2016-11-08 20:03:06 +01:00
|
|
|
|
2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20701
|
|
|
|
|
|
* i386-dis.c (THREE_BYTE_0F7A): Removed.
|
|
|
|
|
|
(dis386_twobyte): Don't use THREE_BYTE_0F7A.
|
|
|
|
|
|
(three_byte_table): Remove THREE_BYTE_0F7A.
|
|
|
|
|
|
|
2016-11-07 23:58:38 +01:00
|
|
|
|
2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20775
|
|
|
|
|
|
* i386-dis.c (FGRPd9_2): Replace 0 with 1.
|
|
|
|
|
|
(FGRPd9_4): Replace 1 with 2.
|
|
|
|
|
|
(FGRPd9_5): Replace 2 with 3.
|
|
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|
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|
(FGRPd9_6): Replace 3 with 4.
|
|
|
|
|
|
(FGRPd9_7): Replace 4 with 5.
|
|
|
|
|
|
(FGRPda_5): Replace 5 with 6.
|
|
|
|
|
|
(FGRPdb_4): Replace 6 with 7.
|
|
|
|
|
|
(FGRPde_3): Replace 7 with 8.
|
|
|
|
|
|
(FGRPdf_4): Replace 8 with 9.
|
|
|
|
|
|
(fgrps): Add an entry for Bad_Opcode.
|
|
|
|
|
|
|
2016-09-27 13:06:01 +02:00
|
|
|
|
2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (arc_flag_operands): Add F_DI14.
|
|
|
|
|
|
(arc_flag_classes): Add C_DI14.
|
|
|
|
|
|
* arc-nps400-tbl.h: Add new exc instructions.
|
|
|
|
|
|
|
2016-10-18 21:10:25 +02:00
|
|
|
|
2016-11-03 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (arc_insn_length): Return length 8 for instructions with
|
|
|
|
|
|
major opcode 0xa.
|
|
|
|
|
|
* arc-nps-400-tbl.h: Add dcmac instruction.
|
|
|
|
|
|
* arc-opc.c (arc_operands): Added operands for dcmac instruction.
|
|
|
|
|
|
(insert_nps_rbdouble_64): Added.
|
|
|
|
|
|
(extract_nps_rbdouble_64): Added.
|
|
|
|
|
|
(insert_nps_proto_size): Added.
|
|
|
|
|
|
(extract_nps_proto_size): Added.
|
|
|
|
|
|
|
arc: Change max instruction length to 64-bits
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
2016-07-06 20:39:55 +02:00
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|
|
2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
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|
|
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|
|
* arc-dis.c (struct arc_operand_iterator): Remove all fields
|
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|
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|
relating to long instruction processing, add new limm field.
|
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|
(OPCODE): Rename to...
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|
(OPCODE_32BIT_INSN): ...this.
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|
(OPCODE_AC): Delete.
|
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|
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|
(skip_this_opcode): Handle different instruction lengths, update
|
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|
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|
|
macro name.
|
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|
|
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|
(special_flag_p): Update parameter type.
|
|
|
|
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|
(find_format_from_table): Update for more instruction lengths.
|
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|
(find_format_long_instructions): Delete.
|
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|
(find_format): Update for more instruction lengths.
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|
(arc_insn_length): Likewise.
|
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|
(extract_operand_value): Update for more instruction lengths.
|
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|
(operand_iterator_next): Remove code relating to long
|
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|
instructions.
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|
(arc_opcode_to_insn_type): New function.
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|
(print_insn_arc):Update for more instructions lengths.
|
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|
* arc-ext.c (extInstruction_t): Change argument type.
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|
* arc-ext.h (extInstruction_t): Change argument type.
|
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* arc-fxi.h: Change type unsigned to unsigned long long
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|
extensively throughout.
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|
* arc-nps400-tbl.h: Add long instructions taken from
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|
arc_long_opcodes table in arc-opc.c.
|
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|
* arc-opc.c: Update parameter types on insert/extract handlers.
|
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|
(arc_long_opcodes): Delete.
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|
(arc_num_long_opcodes): Delete.
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|
(arc_opcode_len): Update for more instruction lengths.
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|
2016-10-13 10:34:16 +02:00
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|
2016-11-03 Graham Markall <graham.markall@embecosm.com>
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|
* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
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|
2016-09-29 20:25:25 +02:00
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|
2016-11-03 Graham Markall <graham.markall@embecosm.com>
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|
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
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|
with arc_opcode_len.
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|
(find_format_long_instructions): Likewise.
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|
* arc-opc.c (arc_opcode_len): New function.
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|
2016-09-29 18:51:16 +02:00
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2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Fix some instruction masks.
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2016-11-03 17:55:01 +01:00
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2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (REG_82): Removed.
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(X86_64_82_REG_0): Likewise.
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(X86_64_82_REG_1): Likewise.
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(X86_64_82_REG_2): Likewise.
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(X86_64_82_REG_3): Likewise.
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|
(X86_64_82_REG_4): Likewise.
|
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|
(X86_64_82_REG_5): Likewise.
|
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(X86_64_82_REG_6): Likewise.
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(X86_64_82_REG_7): Likewise.
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(X86_64_82): New.
|
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(dis386): Use X86_64_82 instead of REG_82.
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(reg_table): Remove REG_82.
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(x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
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X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
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X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
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X86_64_82_REG_7.
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2016-11-03 17:13:01 +01:00
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|
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
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|
PR binutils/20754
|
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|
* i386-dis.c (REG_82): New.
|
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|
(X86_64_82_REG_0): Likewise.
|
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|
(X86_64_82_REG_1): Likewise.
|
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|
(X86_64_82_REG_2): Likewise.
|
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|
(X86_64_82_REG_3): Likewise.
|
|
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|
(X86_64_82_REG_4): Likewise.
|
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|
(X86_64_82_REG_5): Likewise.
|
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|
(X86_64_82_REG_6): Likewise.
|
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(X86_64_82_REG_7): Likewise.
|
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|
(dis386): Use REG_82.
|
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(reg_table): Add REG_82.
|
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(x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
|
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|
X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
|
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X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
|
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|
2016-11-03 16:38:13 +01:00
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|
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
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|
* i386-dis.c (REG_82): Renamed to ...
|
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|
(REG_83): This.
|
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|
(dis386): Updated.
|
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(reg_table): Likewise.
|
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|
2016-11-02 20:31:25 +01:00
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|
2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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|
* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
|
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|
* i386-dis-evex.h (evex_table): Updated.
|
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|
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|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
|
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|
|
|
|
CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
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|
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|
|
(cpu_flags): Add CpuAVX512_4VNNIW.
|
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|
|
|
* i386-opc.h (enum): (AVX512_4VNNIW): New.
|
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|
|
|
|
(i386_cpu_flags): Add cpuavx512_4vnniw.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Ditto.
|
|
|
|
|
|
|
2016-11-02 20:24:39 +01:00
|
|
|
|
2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
|
|
|
|
|
|
PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Updated.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuAVX512_4FMAPS.
|
|
|
|
|
|
(opcode_modifiers): Add ImplicitQuadGroup modifier.
|
|
|
|
|
|
* i386-opc.h (AVX512_4FMAP): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx512_4fmaps.
|
|
|
|
|
|
(ImplicitQuadGroup): New.
|
|
|
|
|
|
(i386_opcode_modifier): Add implicitquadgroup.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Ditto.
|
|
|
|
|
|
|
2016-11-01 17:45:57 +01:00
|
|
|
|
2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
|
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|
|
|
|
Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
Add support for RISC-V architecture.
|
|
|
|
|
|
* configure.ac: Add entry for bfd_riscv_arch.
|
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|
|
|
|
* configure: Regenerate.
|
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|
|
|
|
* disassemble.c (disassembler): Add support for riscv.
|
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|
|
|
|
(disassembler_usage): Likewise.
|
|
|
|
|
|
* riscv-dis.c: New file.
|
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|
|
* riscv-opc.c: New file.
|
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|
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|
2016-10-21 21:16:32 +02:00
|
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|
|
2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
|
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|
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|
|
(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
|
|
|
|
|
|
(rm_table): Update the RM_0FAE_REG_7 entry.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
|
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|
|
|
|
(cpu_flags): Remove CpuPCOMMIT.
|
|
|
|
|
|
* i386-opc.h (CpuPCOMMIT): Removed.
|
|
|
|
|
|
(i386_cpu_flags): Remove cpupcommit.
|
|
|
|
|
|
* i386-opc.tbl: Remove pcommit.
|
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|
|
|
|
* i386-init.h: Regenerated.
|
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|
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|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2016-10-21 00:07:42 +02:00
|
|
|
|
2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
|
|
|
|
PR binutis/20705
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
|
|
|
|
|
|
the highest bit in VEX.vvvv for the 3-byte VEX prefix in
|
|
|
|
|
|
32-bit mode. Don't check vex.register_specifier in 32-bit
|
|
|
|
|
|
mode.
|
|
|
|
|
|
(OP_VEX): Check for invalid mask registers.
|
|
|
|
|
|
|
2016-10-18 18:06:27 +02:00
|
|
|
|
2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
|
|
|
|
PR binutis/20699
|
|
|
|
|
|
* i386-dis.c (OP_E_memory): Check addr32flag in stead of
|
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|
|
|
|
sizeflag.
|
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|
|
|
|
|
2016-10-18 17:14:10 +02:00
|
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|
|
2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
|
|
|
|
PR binutis/20704
|
|
|
|
|
|
* i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
|
|
|
|
|
|
|
2016-10-18 05:36:01 +02:00
|
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|
|
2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
|
|
|
|
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|
|
* aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
|
|
|
|
|
|
local variable to `index_regno'.
|
|
|
|
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|
|
2016-09-21 13:07:46 +02:00
|
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|
|
2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
|
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|
|
|
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|
|
* arc-tbl.h: Removed any "inv.+" instructions from the table.
|
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|
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|
|
2016-10-13 15:01:19 +02:00
|
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|
|
2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
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|
|
|
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|
|
* arc-dis.c (find_format_from_table): Discriminate LIMM indicator
|
|
|
|
|
|
usage on ISA basis.
|
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|
|
2016-10-11 12:24:44 +02:00
|
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|
|
2016-10-11 Jiong Wang <jiong.wang@arm.com>
|
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|
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PR target/20666
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* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
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2016-10-07 11:55:56 +02:00
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2016-10-07 Jiong Wang <jiong.wang@arm.com>
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PR target/20667
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* aarch64-opc.c (aarch64_print_operand): Always print operand if it's
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available.
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2016-10-07 02:28:35 +02:00
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2016-10-07 Alan Modra <amodra@gmail.com>
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* sh-opc.h (sh_merge_bfd_arch): Delete prototype.
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2016-10-05 09:47:02 +02:00
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2016-10-06 Alan Modra <amodra@gmail.com>
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* aarch64-opc.c: Spell fall through comments consistently.
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* i386-dis.c: Likewise.
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* aarch64-dis.c: Add missing fall through comments.
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* aarch64-opc.c: Likewise.
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* arc-dis.c: Likewise.
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* arm-dis.c: Likewise.
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* i386-dis.c: Likewise.
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* m68k-dis.c: Likewise.
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* mep-asm.c: Likewise.
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* ns32k-dis.c: Likewise.
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* sh-dis.c: Likewise.
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* tic4x-dis.c: Likewise.
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* tic6x-dis.c: Likewise.
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* vax-dis.c: Likewise.
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2016-10-05 08:22:24 +02:00
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2016-10-06 Alan Modra <amodra@gmail.com>
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* arc-ext.c (create_map): Add missing break.
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* msp430-decode.opc (encode_as): Likewise.
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* msp430-decode.c: Regenerate.
|
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2016-10-05 23:38:25 +02:00
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2016-10-06 Alan Modra <amodra@gmail.com>
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* cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
|
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* crx-dis.c (print_insn_crx): Likewise.
|
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|
2016-09-30 17:54:43 +02:00
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|
2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/20657
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* i386-dis.c (putop): Don't assign alt twice.
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2016-09-30 15:16:54 +02:00
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2016-09-29 Jiong Wang <jiong.wang@arm.com>
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PR target/20553
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* aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
|
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|
Disallow 3-operand cmp[l][i] for ppc64
cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.
L field of dcbf and wclr is 2 bits.
PR 20641
include/
* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
* ppc-opc.c (L): Make compulsory.
(LOPT): New, optional form of L.
(HTM_R): Define as LOPT.
(L0, L1): Delete.
(L32OPT): New, optional for 32-bit L.
(L2OPT): New, 2-bit L for dcbf.
(SVC_LEC): Update.
(L2): Define.
(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
<dcbf>: Use L2OPT.
<tlbiel, tlbie>: Use LOPT.
<wclr, wclrall>: Use L2.
gas/
* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
2016-09-29 07:42:47 +02:00
|
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|
2016-09-29 Alan Modra <amodra@gmail.com>
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|
* ppc-opc.c (L): Make compulsory.
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(LOPT): New, optional form of L.
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(HTM_R): Define as LOPT.
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(L0, L1): Delete.
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(L32OPT): New, optional for 32-bit L.
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(L2OPT): New, 2-bit L for dcbf.
|
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(SVC_LEC): Update.
|
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|
(L2): Define.
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|
|
(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
|
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|
(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
|
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|
<dcbf>: Use L2OPT.
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<tlbiel, tlbie>: Use LOPT.
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<wclr, wclrall>: Use L2.
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2016-09-26 17:36:08 +02:00
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|
2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
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* Makefile.in: Regenerate.
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|
* configure: Likewise.
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|
2016-09-14 13:40:38 +02:00
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|
2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
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|
* arc-ext-tbl.h (EXTINSN2OPF): Define.
|
|
|
|
|
|
(EXTINSN2OP): Use EXTINSN2OPF.
|
|
|
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|
|
(bspeekm, bspop, modapp): New extension instructions.
|
|
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|
|
* arc-opc.c (F_DNZ_ND): Define.
|
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|
|
(F_DNZ_D): Likewise.
|
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|
|
(F_SIZEB1): Changed.
|
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|
(C_DNZ_D): Define.
|
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|
(C_HARD): Changed.
|
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|
|
* arc-tbl.h (dbnz): New instruction.
|
|
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|
|
(prealloc): Allow it for ARC EM.
|
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|
|
(xbfu): Likewise.
|
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|
2016-09-21 18:11:52 +02:00
|
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|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-opc.c (print_immediate_offset_address): Print spaces
|
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|
|
after commas in addresses.
|
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|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
|
2016-09-21 18:11:04 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
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|
|
* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
|
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|
|
|
rather than "should be" or "expected to be" in error messages.
|
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|
|
[AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21 18:09:59 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
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|
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|
|
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|
|
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
|
|
|
|
|
|
(print_mnemonic_name): ...here.
|
|
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|
|
(print_comment): New function.
|
|
|
|
|
|
(print_aarch64_insn): Call it.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_conds): Add SVE names.
|
|
|
|
|
|
(aarch64_print_operand): Print alternative condition names in
|
|
|
|
|
|
a comment.
|
|
|
|
|
|
|
[AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.
include/
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
opcodes/
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
2016-09-21 17:58:48 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
|
|
|
|
|
|
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
|
|
|
|
|
|
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
|
|
|
|
|
|
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
|
|
|
|
|
|
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
|
|
|
|
|
|
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
|
|
|
|
|
|
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
|
|
|
|
|
|
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
|
|
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|
|
|
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
|
|
|
|
|
|
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
|
|
|
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|
|
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
|
|
|
|
|
|
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
|
|
|
|
|
|
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
|
|
|
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|
|
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
|
|
|
|
|
|
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
|
|
|
|
|
|
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
|
|
|
|
|
|
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
|
|
|
|
|
|
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
|
|
|
|
|
|
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
|
|
|
|
|
|
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
|
|
|
|
|
|
(OP_SVE_XWU, OP_SVE_XXU): New macros.
|
|
|
|
|
|
(aarch64_feature_sve): New variable.
|
|
|
|
|
|
(SVE): New macro.
|
|
|
|
|
|
(_SVE_INSN): Likewise.
|
|
|
|
|
|
(aarch64_opcode_table): Add SVE instructions.
|
|
|
|
|
|
* aarch64-opc.h (extract_fields): Declare.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.c (extract_fields): Make global.
|
|
|
|
|
|
(do_misc_decoding): Handle the new SVE aarch64_ops.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.
include/
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
aarch64_insn_classes.
opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.
2016-09-21 17:58:22 +02:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
|
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(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
|
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|
|
aarch64_field_kinds.
|
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* aarch64-opc.c (fields): Add corresponding entries.
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|
* aarch64-asm.c (aarch64_get_variant): New function.
|
|
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(aarch64_encode_variant_using_iclass): Likewise.
|
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(aarch64_opcode_encode): Call it.
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* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
|
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|
(aarch64_opcode_decode): Call it.
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|
2016-09-21 17:57:43 +02:00
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|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
|
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|
|
and FP register operands.
|
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* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
|
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|
|
(FLD_SVE_Vn): New aarch64_field_kinds.
|
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* aarch64-opc.c (fields): Add corresponding entries.
|
|
|
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|
|
(aarch64_print_operand): Handle the new SVE core and FP register
|
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|
operands.
|
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* aarch64-opc-2.c: Regenerate.
|
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* aarch64-asm-2.c: Likewise.
|
|
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|
* aarch64-dis-2.c: Likewise.
|
|
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|
|
2016-09-21 17:57:22 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
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|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
|
|
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|
|
|
immediate operands.
|
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|
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|
|
* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
|
|
|
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|
|
* aarch64-opc.c (fields): Add corresponding entry.
|
|
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|
|
|
(operand_general_constraint_met_p): Handle the new SVE FP immediate
|
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|
|
operands.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
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|
|
* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
|
|
|
|
|
|
(ins_sve_float_zero_one): New inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
|
|
|
|
|
|
(aarch64_ins_sve_float_half_two): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_float_zero_one): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
|
|
|
|
|
|
(ext_sve_float_zero_one): New extractors.
|
|
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|
|
|
* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
|
|
|
|
|
|
(aarch64_ext_sve_float_half_two): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_float_zero_one): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 17:56:57 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
|
|
|
|
|
|
integer immediate operands.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
|
|
|
|
|
|
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
|
|
|
|
|
|
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add corresponding entries.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle the new SVE integer
|
|
|
|
|
|
immediate operands.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
(aarch64_sve_dupm_mov_immediate_p): New function.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
|
|
|
|
|
|
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
|
|
|
|
|
|
(aarch64_ins_limm): ...here.
|
|
|
|
|
|
(aarch64_ins_inv_limm): New function.
|
|
|
|
|
|
(aarch64_ins_sve_aimm): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_asimm): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_limm_mov): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_shlimm): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_shrimm): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
|
|
|
|
|
|
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
|
|
|
|
|
|
* aarch64-dis.c (decode_limm): New function, split out from...
|
|
|
|
|
|
(aarch64_ext_limm): ...here.
|
|
|
|
|
|
(aarch64_ext_inv_limm): New function.
|
|
|
|
|
|
(decode_sve_aimm): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_aimm): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_asimm): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_limm_mov): Likewise.
|
|
|
|
|
|
(aarch64_top_bit): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_shlimm): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_shrimm): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
2016-09-21 17:56:15 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
|
|
|
|
|
|
operands.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
|
|
|
|
|
|
the AARCH64_MOD_MUL_VL entry.
|
|
|
|
|
|
(value_aligned_p): Cope with non-power-of-two alignments.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
|
|
|
|
|
|
(print_immediate_offset_address): Likewise.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
|
|
|
|
|
|
(ins_sve_addr_ri_s9xvl): New inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
|
|
|
|
|
|
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
|
|
|
|
|
|
(ext_sve_addr_ri_s9xvl): New extractors.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
|
|
|
|
|
|
address operands.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
|
|
|
|
|
|
(FLD_SVE_xs_22): New aarch64_field_kinds.
|
|
|
|
|
|
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
|
|
|
|
|
|
(get_operand_specific_data): New function.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
|
|
|
|
|
|
FLD_SVE_xs_14 and FLD_SVE_xs_22.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle the new SVE address
|
|
|
|
|
|
operands.
|
|
|
|
|
|
(sve_reg): New array.
|
|
|
|
|
|
(get_addr_sve_reg_name): New function.
|
|
|
|
|
|
(aarch64_print_operand): Handle the new SVE address operands.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
|
|
|
|
|
|
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
|
|
|
|
|
|
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
|
|
|
|
|
|
(aarch64_ins_sve_addr_rr_lsl): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_rz_xtw): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_zi_u5): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_zz): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_zz_lsl): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
|
|
|
|
|
|
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
|
|
|
|
|
|
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
|
|
|
|
|
|
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_u6): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_rr_lsl): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_rz_xtw): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_zi_u5): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_zz): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_zz_lsl): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 17:55:22 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
|
|
|
|
|
|
AARCH64_OPND_SVE_PATTERN_SCALED.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add a corresponding entry.
|
|
|
|
|
|
(set_multiplier_out_of_range_error): New function.
|
|
|
|
|
|
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle
|
|
|
|
|
|
AARCH64_OPND_SVE_PATTERN_SCALED.
|
|
|
|
|
|
(print_register_offset_address): Use PRIi64 to print the
|
|
|
|
|
|
shift amount.
|
|
|
|
|
|
(aarch64_print_operand): Likewise. Handle
|
|
|
|
|
|
AARCH64_OPND_SVE_PATTERN_SCALED.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_scale): New inserter.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_scale): New inserter.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
2016-09-21 17:54:53 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
|
|
|
|
|
|
AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
|
|
|
|
|
|
(FLD_SVE_prfop): Likewise.
|
|
|
|
|
|
* aarch64-opc.c: Include libiberty.h.
|
|
|
|
|
|
(aarch64_sve_pattern_array): New variable.
|
|
|
|
|
|
(aarch64_sve_prfop_array): Likewise.
|
|
|
|
|
|
(fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
|
|
|
|
|
|
(aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
|
|
|
|
|
|
AARCH64_OPND_SVE_PRFOP.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
2016-09-21 17:54:30 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
|
|
|
|
|
|
AARCH64_OPND_QLF_P_[ZM].
|
|
|
|
|
|
(aarch64_print_operand): Print /z and /m where appropriate.
|
|
|
|
|
|
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 17:53:54 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
|
|
|
|
|
|
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
|
|
|
|
|
|
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
|
|
|
|
|
|
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add corresponding entries here.
|
|
|
|
|
|
(operand_general_constraint_met_p): Check that SVE register lists
|
|
|
|
|
|
have the correct length. Check the ranges of SVE index registers.
|
|
|
|
|
|
Check for cases where p8-p15 are used in 3-bit predicate fields.
|
|
|
|
|
|
(aarch64_print_operand): Handle the new SVE operands.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_index): New function.
|
|
|
|
|
|
(aarch64_ins_sve_reglist): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_sve_index): New function.
|
|
|
|
|
|
(aarch64_ext_sve_reglist): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 17:52:30 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
|
|
|
|
|
|
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
|
|
|
|
|
|
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
|
|
|
|
|
|
tied operands.
|
|
|
|
|
|
|
2016-09-21 17:51:43 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (get_offset_int_reg_name): New function.
|
|
|
|
|
|
(print_immediate_offset_address): Likewise.
|
|
|
|
|
|
(print_register_offset_address): Take the base and offset
|
|
|
|
|
|
registers as parameters.
|
|
|
|
|
|
(aarch64_print_operand): Update caller accordingly. Use
|
|
|
|
|
|
print_immediate_offset_address.
|
|
|
|
|
|
|
2016-09-21 17:51:37 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (BANK): New macro.
|
|
|
|
|
|
(R32, R64): Take a register number as argument
|
|
|
|
|
|
(int_reg): Use BANK.
|
|
|
|
|
|
|
2016-09-21 17:51:30 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (print_register_list): Add a prefix parameter.
|
|
|
|
|
|
(aarch64_print_operand): Update accordingly.
|
|
|
|
|
|
|
2016-09-21 17:51:24 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
|
|
|
|
|
|
for FPIMM.
|
|
|
|
|
|
* aarch64-asm.h (ins_fpimm): New inserter.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_fpimm): New function.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_fpimm): New extractor.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
|
|
|
|
|
|
(aarch64_ext_fpimm): New function.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
2016-09-21 17:51:16 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c: Include libiberty.h.
|
|
|
|
|
|
(insert_fields): New function.
|
|
|
|
|
|
(aarch64_ins_imm): Use it.
|
|
|
|
|
|
* aarch64-dis.c (extract_fields): New function.
|
|
|
|
|
|
(aarch64_ext_imm): Use it.
|
|
|
|
|
|
|
2016-09-21 17:51:09 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
|
|
|
|
|
|
with an esize parameter.
|
|
|
|
|
|
(operand_general_constraint_met_p): Update accordingly.
|
|
|
|
|
|
Fix misindented code.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_limm): Update call to
|
|
|
|
|
|
aarch64_logical_immediate_p.
|
|
|
|
|
|
|
2016-09-21 17:51:00 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
|
|
|
|
|
|
|
2016-09-21 17:48:06 +02:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
|
|
|
|
|
|
|
2016-09-15 12:24:24 +02:00
|
|
|
|
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
|
|
|
|
|
|
|
Modify POWER9 support to match final ISA 3.0 documentation.
opcodes/
* ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3>: Delete mnemonics.
<cp_abort>: Rename mnemonic from ...
<cpabort>: ...to this.
<setb>: Change to a X form instruction.
<sync>: Change to 1 operand form.
<copy>: Delete mnemonic.
<copy_first>: Rename mnemonic from ...
<copy>: ...to this.
<paste, paste.>: Delete mnemonics.
<paste_last>: Rename mnemonic from ...
<paste.>: ...to this.
gas/
* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
<copy, paste.>: Update tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-09-15 05:10:51 +02:00
|
|
|
|
2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
|
|
|
|
|
|
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
|
|
|
|
|
|
xor3>: Delete mnemonics.
|
|
|
|
|
|
<cp_abort>: Rename mnemonic from ...
|
|
|
|
|
|
<cpabort>: ...to this.
|
|
|
|
|
|
<setb>: Change to a X form instruction.
|
|
|
|
|
|
<sync>: Change to 1 operand form.
|
|
|
|
|
|
<copy>: Delete mnemonic.
|
|
|
|
|
|
<copy_first>: Rename mnemonic from ...
|
|
|
|
|
|
<copy>: ...to this.
|
|
|
|
|
|
<paste, paste.>: Delete mnemonics.
|
|
|
|
|
|
<paste_last>: Rename mnemonic from ...
|
|
|
|
|
|
<paste.>: ...to this.
|
|
|
|
|
|
|
2016-09-14 13:20:13 +02:00
|
|
|
|
2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
|
|
|
|
|
|
|
2016-09-12 16:32:02 +02:00
|
|
|
|
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (main): Support alternate arch strings.
|
|
|
|
|
|
|
2016-09-12 16:32:02 +02:00
|
|
|
|
2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.txt: Fix kmctr instruction type.
|
|
|
|
|
|
|
2016-09-07 18:16:25 +02:00
|
|
|
|
2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2016-08-26 22:15:23 +02:00
|
|
|
|
2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/arc-dis.c (print_insn_arc): Changed.
|
|
|
|
|
|
|
2016-08-26 16:31:31 +02:00
|
|
|
|
2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
|
|
|
|
|
|
camellia_fl.
|
|
|
|
|
|
|
Add missing ARMv8-M special registers
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-26 12:53:30 +02:00
|
|
|
|
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
|
|
|
|
|
|
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
|
|
|
|
|
|
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
|
|
|
|
|
|
|
2016-08-25 00:27:11 +02:00
|
|
|
|
2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
|
|
|
|
|
|
(PREFIX_MOD_3_0FAE_REG_4): Likewise.
|
|
|
|
|
|
(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
|
|
|
|
|
|
PREFIX_MOD_3_0FAE_REG_4.
|
|
|
|
|
|
(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
|
|
|
|
|
|
PREFIX_MOD_3_0FAE_REG_4.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuPTWRITE.
|
|
|
|
|
|
* i386-opc.h (CpuPTWRITE): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuptwrite.
|
|
|
|
|
|
* i386-opc.tbl: Add ptwrite instruction.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2016-05-31 17:40:09 +02:00
|
|
|
|
2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.h: Wrap around in extern "C".
|
|
|
|
|
|
|
2016-08-23 10:03:19 +02:00
|
|
|
|
2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (V8_2_INSN): New macro.
|
|
|
|
|
|
(aarch64_opcode_table): Use it.
|
|
|
|
|
|
|
2016-08-23 10:02:38 +02:00
|
|
|
|
2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Make more use of
|
|
|
|
|
|
CORE_INSN, __FP_INSN and SIMD_INSN.
|
|
|
|
|
|
|
2016-08-23 10:01:54 +02:00
|
|
|
|
2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
|
|
|
|
|
|
(aarch64_opcode_table): Update uses accordingly.
|
|
|
|
|
|
|
2016-08-01 18:42:31 +02:00
|
|
|
|
2016-07-25 Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
Kwok Cheung Yeung <kcy@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
opcodes/
|
|
|
|
|
|
* ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
|
|
|
|
|
|
'e_cmplwi' to 'e_cmpli' instead.
|
|
|
|
|
|
(OPVUPRT, OPVUPRT_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add E200Z4 insns.
|
|
|
|
|
|
(vle_opcodes): Add context save/restore insns.
|
|
|
|
|
|
|
MIPS/GAS: Implement microMIPS branch/jump compaction
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.
Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous. This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has. Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.
Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form. For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction. A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.
Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well. We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded. Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.
For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.
gas/
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
2016-07-27 18:27:55 +02:00
|
|
|
|
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
|
|
|
|
|
|
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
|
|
|
|
|
|
"j".
|
|
|
|
|
|
|
2016-07-27 16:57:18 +02:00
|
|
|
|
2016-07-27 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Change block comments to GNU format.
|
|
|
|
|
|
* arc-dis.c: Add new globals addrtypenames,
|
|
|
|
|
|
addrtypenames_max, and addtypeunknown.
|
|
|
|
|
|
(get_addrtype): New function.
|
|
|
|
|
|
(print_insn_arc): Print colons and address types when
|
|
|
|
|
|
required.
|
|
|
|
|
|
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
|
|
|
|
|
|
define insert and extract functions for all address types.
|
|
|
|
|
|
(arc_operands): Add operands for colon and all address
|
|
|
|
|
|
types.
|
|
|
|
|
|
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
|
|
|
|
|
|
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
|
|
|
|
|
|
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
|
|
|
|
|
|
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
|
|
|
|
|
|
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
|
|
|
|
|
|
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
|
|
|
|
|
|
|
2016-07-22 00:22:13 +02:00
|
|
|
|
2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
|
2016-07-20 18:08:07 +02:00
|
|
|
|
2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (skipclass): New structure.
|
|
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|
|
(decodelist): New variable.
|
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|
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|
|
(is_compatible_p): New function.
|
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|
(new_element): Likewise.
|
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|
|
(skip_class_p): Likewise.
|
|
|
|
|
|
(find_format_from_table): Use skip_class_p function.
|
|
|
|
|
|
(find_format): Decode first the extension instructions.
|
|
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|
|
(print_insn_arc): Select either ARCEM or ARCHS based on elf
|
|
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|
|
e_flags.
|
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|
|
(parse_option): New function.
|
|
|
|
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|
(parse_disassembler_options): Likewise.
|
|
|
|
|
|
(print_arc_disassembler_options): Likewise.
|
|
|
|
|
|
(print_insn_arc): Use parse_disassembler_options function. Proper
|
|
|
|
|
|
select ARCv2 cpu variant.
|
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|
|
* disassemble.c (disassembler_usage): Add ARC disassembler
|
|
|
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|
|
options.
|
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|
|
MIPS/opcodes: Address issues with NAL disassembly
Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c952e ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e2e ("Add in a JALRC
alias and fix the NAL instruction."). As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.
The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':
$ cat test.s
.text
foo:
nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o
nal.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo> 04100000 0x4100000
...
$
This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.
Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code. Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people. This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code. Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.
Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.
Add a suitable test case to the GAS test suite. While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
annotation from the "nal" entry and reorder it beyond "bltzal".
gas/
* testsuite/gas/mips/nal-1.d: New test.
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
* testsuite/gas/mips/nal-2.d: New test.
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
* testsuite/gas/mips/nal.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-08 17:07:39 +02:00
|
|
|
|
2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
|
|
|
|
|
|
annotation from the "nal" entry and reorder it beyond "bltzal".
|
|
|
|
|
|
|
2016-07-13 10:42:28 +02:00
|
|
|
|
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
|
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|
|
|
|
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|
|
* sparc-opc.c (ldtxa): New macro.
|
|
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|
|
(sparc_opcodes): Use the macro defined above to add entries for
|
|
|
|
|
|
the LDTXA instructions.
|
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|
|
(asi_table): Add the ASI_TWINX_* asis used in the LDTXA
|
|
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|
|
instruction.
|
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|
2016-07-08 20:38:35 +02:00
|
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|
2016-07-07 James Bowman <james.bowman@ftdichip.com>
|
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|
|
* ft32-opc.c (ft32_opc_info): Correct mask for "callc"
|
|
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|
|
|
and "jmpc".
|
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|
2016-07-01 09:01:41 +02:00
|
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|
2016-07-01 Jan Beulich <jbeulich@suse.com>
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|
|
* i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
|
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|
(movzb): Adjust to cover all permitted suffixes.
|
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|
(movzw): New.
|
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|
|
* i386-tbl.h: Re-generate.
|
|
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|
|
2016-07-01 08:57:21 +02:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
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|
|
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|
|
|
|
|
* i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
|
|
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|
|
(lgdt): Remove Tbyte from non-64-bit variant.
|
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|
|
(fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
|
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|
|
|
xsaves64, xsavec64): Remove Disp16.
|
|
|
|
|
|
(cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
|
|
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|
Remove Disp32S from non-64-bit variants. Remove Disp16 from
|
|
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|
|
|
64-bit variants.
|
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|
(vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
|
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|
|
vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
|
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|
|
|
|
vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
|
|
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|
|
|
64-bit variants.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
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|
|
2016-07-01 08:56:13 +02:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
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|
|
|
|
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|
|
* i386-opc.tbl (xlat): Remove RepPrefixOk.
|
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|
|
* i386-tbl.h: Re-generate.
|
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|
|
|
|
2016-06-30 17:03:07 +02:00
|
|
|
|
2016-06-30 Yao Qi <yao.qi@linaro.org>
|
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|
|
|
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|
|
* arm-dis.c (print_insn): Fix typo in comment.
|
|
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|
|
2016-06-28 10:21:04 +02:00
|
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|
2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
|
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* aarch64-opc.c (operand_general_constraint_met_p): Check the
|
|
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|
|
range of ldst_elemlist operands.
|
|
|
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|
|
(print_register_list): Use PRIi64 to print the index.
|
|
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|
|
(aarch64_print_operand): Likewise.
|
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|
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|
|
2016-04-21 15:56:50 +02:00
|
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|
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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|
|
* mcore-opc.h: Remove sentinal.
|
|
|
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|
|
* mcore-dis.c (print_insn_mcore): Adjust.
|
|
|
|
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|
|
[ARC] Misc minor edits/fixes
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
2016-06-21 21:25:29 +02:00
|
|
|
|
2016-06-23 Graham Markall <graham.markall@embecosm.com>
|
|
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|
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|
|
|
|
|
|
|
* arc-opc.c: Correct description of availability of NPS400
|
|
|
|
|
|
features.
|
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|
|
|
|
|
Add support for yet some more new ISA 3.0 instructions.
opcodes/
* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
xor3>: New mnemonics.
<setb>: Change to a VX form instruction.
(insert_sh6): Add support for rldixor.
(extract_sh6): Likewise.
gas/
* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
setbool, xor3>: New tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-06-23 00:55:17 +02:00
|
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|
2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
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|
|
* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
|
|
|
|
|
|
(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
|
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|
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|
|
mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
|
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|
|
|
xor3>: New mnemonics.
|
|
|
|
|
|
<setb>: Change to a VX form instruction.
|
|
|
|
|
|
(insert_sh6): Add support for rldixor.
|
|
|
|
|
|
(extract_sh6): Likewise.
|
|
|
|
|
|
|
2016-06-04 05:11:46 +02:00
|
|
|
|
2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-ext.h: Wrap in extern C.
|
|
|
|
|
|
|
2016-06-21 15:03:08 +02:00
|
|
|
|
2016-06-21 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (arc_insn_length): Add comment on instruction length.
|
|
|
|
|
|
Use same method for determining instruction length on ARC700 and
|
|
|
|
|
|
NPS-400.
|
|
|
|
|
|
(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
|
|
|
|
|
|
* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
|
|
|
|
|
|
with the NPS400 subclass.
|
|
|
|
|
|
* arc-opc.c: Likewise.
|
|
|
|
|
|
|
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 11:15:43 +02:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (rdasr): New macro.
|
|
|
|
|
|
(wrasr): Likewise.
|
|
|
|
|
|
(rdpr): Likewise.
|
|
|
|
|
|
(wrpr): Likewise.
|
|
|
|
|
|
(rdhpr): Likewise.
|
|
|
|
|
|
(wrhpr): Likewise.
|
|
|
|
|
|
(sparc_opcodes): Use the macros above to fix and expand the
|
|
|
|
|
|
definition of read/write instructions from/to
|
|
|
|
|
|
asr/privileged/hyperprivileged instructions.
|
|
|
|
|
|
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
|
|
|
|
|
|
%hva_mask_nz. Prefer softint_set and softint_clear over
|
|
|
|
|
|
set_softint and clear_softint.
|
|
|
|
|
|
(print_insn_sparc): Support %ver in Rd.
|
|
|
|
|
|
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 11:14:18 +02:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
|
|
|
|
|
|
architecture according to the hardware capabilities they require.
|
|
|
|
|
|
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 11:12:48 +02:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
|
|
|
|
|
|
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
|
|
|
|
|
|
bfd_mach_sparc_v9{c,d,e,v,m}.
|
|
|
|
|
|
* sparc-opc.c (MASK_V9C): Define.
|
|
|
|
|
|
(MASK_V9D): Likewise.
|
|
|
|
|
|
(MASK_V9E): Likewise.
|
|
|
|
|
|
(MASK_V9V): Likewise.
|
|
|
|
|
|
(MASK_V9M): Likewise.
|
|
|
|
|
|
(v6): Add MASK_V9{C,D,E,V,M}.
|
|
|
|
|
|
(v6notlet): Likewise.
|
|
|
|
|
|
(v7): Likewise.
|
|
|
|
|
|
(v8): Likewise.
|
|
|
|
|
|
(v9): Likewise.
|
|
|
|
|
|
(v9andleon): Likewise.
|
|
|
|
|
|
(v9a): Likewise.
|
|
|
|
|
|
(v9b): Likewise.
|
|
|
|
|
|
(v9c): Define.
|
|
|
|
|
|
(v9d): Likewise.
|
|
|
|
|
|
(v9e): Likewise.
|
|
|
|
|
|
(v9v): Likewise.
|
|
|
|
|
|
(v9m): Likewise.
|
|
|
|
|
|
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
|
|
|
|
|
|
|
2016-06-15 17:25:34 +02:00
|
|
|
|
2016-06-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
|
|
|
|
|
|
constants to match expected behaviour.
|
|
|
|
|
|
(nds32_parse_opcode): Likewise. Also for whitespace.
|
|
|
|
|
|
|
2016-06-14 22:48:11 +02:00
|
|
|
|
2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (extract_rhv1): Extract value from insn.
|
|
|
|
|
|
|
2016-06-14 22:53:04 +02:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-13 10:03:05 +02:00
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add ldbit instruction.
|
|
|
|
|
|
* arc-opc.c: Add flag classes required for ldbit.
|
|
|
|
|
|
|
2016-06-14 22:53:04 +02:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-09 09:38:34 +02:00
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
|
|
|
|
|
|
* arc-opc.c: Add flag classes, insert/extract functions, and operands to
|
|
|
|
|
|
support the above instructions.
|
|
|
|
|
|
|
2016-06-14 22:53:04 +02:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-03 11:48:49 +02:00
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
|
|
|
|
|
|
imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
|
|
|
|
|
|
csma, cbba, zncv, and hofs.
|
|
|
|
|
|
* arc-opc.c: Add flag classes, insert/extract functions, and operands to
|
|
|
|
|
|
support the above instructions.
|
|
|
|
|
|
|
|
|
|
|
|
2016-06-06 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add andab and orab instructions.
|
|
|
|
|
|
|
|
|
|
|
|
2016-06-06 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add addl-like instructions.
|
|
|
|
|
|
|
|
|
|
|
|
2016-06-06 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add mxb and imxb instructions.
|
|
|
|
|
|
|
|
|
|
|
|
2016-06-06 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2016-06-10 13:40:48 +02:00
|
|
|
|
2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-dis.c (option_use_insn_len_bits_p): New file scope
|
|
|
|
|
|
variable.
|
|
|
|
|
|
(init_disasm): Handle new command line option "insnlength".
|
|
|
|
|
|
(print_s390_disassembler_options): Mention new option in help
|
|
|
|
|
|
output.
|
|
|
|
|
|
(print_insn_s390): Use the encoded insn length when dumping
|
|
|
|
|
|
unknown instructions.
|
|
|
|
|
|
|
2016-06-09 18:00:57 +02:00
|
|
|
|
2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* avr-dis.c (avr_operand): Add default data address space origin (0x800000)
|
|
|
|
|
|
to the address and set as symbol address for LDS/ STS immediate operands.
|
|
|
|
|
|
|
PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 14:34:38 +02:00
|
|
|
|
2016-06-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
|
|
|
|
|
|
cpu for "vle" to e500.
|
|
|
|
|
|
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
|
|
|
|
|
|
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
|
|
|
|
|
|
(PPCNONE): Delete, substitute throughout.
|
|
|
|
|
|
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
|
|
|
|
|
|
except for major opcode 4 and 31.
|
|
|
|
|
|
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
|
|
|
|
|
|
|
2016-06-07 10:56:42 +02:00
|
|
|
|
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
|
|
|
|
|
|
ARM_EXT_RAS in relevant entries.
|
|
|
|
|
|
|
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
gas/
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-04 01:38:02 +02:00
|
|
|
|
2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20196
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
|
|
|
|
|
|
opcodes for E6500.
|
|
|
|
|
|
|
2016-06-04 00:55:29 +02:00
|
|
|
|
2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutis/18386
|
|
|
|
|
|
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
|
|
|
|
|
|
(indir_v_mode): New.
|
|
|
|
|
|
Add comments for '&'.
|
|
|
|
|
|
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
|
|
|
|
|
|
(putop): Handle '&'.
|
|
|
|
|
|
(intel_operand_size): Handle indir_v_mode.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
|
|
|
|
|
|
64-bit indirect call/jmp for AMD64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated
|
|
|
|
|
|
|
2016-06-02 15:03:23 +02:00
|
|
|
|
2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (struct arc_operand_iterator): New structure.
|
|
|
|
|
|
(find_format_from_table): All the old content from find_format,
|
|
|
|
|
|
with some minor adjustments, and parameter renaming.
|
|
|
|
|
|
(find_format_long_instructions): New function.
|
|
|
|
|
|
(find_format): Rewritten.
|
|
|
|
|
|
(arc_insn_length): Add LSB parameter.
|
|
|
|
|
|
(extract_operand_value): New function.
|
|
|
|
|
|
(operand_iterator_next): New function.
|
|
|
|
|
|
(print_insn_arc): Use new functions to find opcode, and iterator
|
|
|
|
|
|
over operands.
|
|
|
|
|
|
* arc-opc.c (insert_nps_3bit_dst_short): New function.
|
|
|
|
|
|
(extract_nps_3bit_dst_short): New function.
|
|
|
|
|
|
(insert_nps_3bit_src2_short): New function.
|
|
|
|
|
|
(extract_nps_3bit_src2_short): New function.
|
|
|
|
|
|
(insert_nps_bitop1_size): New function.
|
|
|
|
|
|
(extract_nps_bitop1_size): New function.
|
|
|
|
|
|
(insert_nps_bitop2_size): New function.
|
|
|
|
|
|
(extract_nps_bitop2_size): New function.
|
|
|
|
|
|
(insert_nps_bitop_mod4_msb): New function.
|
|
|
|
|
|
(extract_nps_bitop_mod4_msb): New function.
|
|
|
|
|
|
(insert_nps_bitop_mod4_lsb): New function.
|
|
|
|
|
|
(extract_nps_bitop_mod4_lsb): New function.
|
|
|
|
|
|
(insert_nps_bitop_dst_pos3_pos4): New function.
|
|
|
|
|
|
(extract_nps_bitop_dst_pos3_pos4): New function.
|
|
|
|
|
|
(insert_nps_bitop_ins_ext): New function.
|
|
|
|
|
|
(extract_nps_bitop_ins_ext): New function.
|
|
|
|
|
|
(arc_operands): Add new operands.
|
|
|
|
|
|
(arc_long_opcodes): New global array.
|
|
|
|
|
|
(arc_num_long_opcodes): New global.
|
|
|
|
|
|
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
|
|
|
|
|
|
|
2016-05-29 10:29:22 +02:00
|
|
|
|
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* nds32-asm.h: Add extern "C".
|
|
|
|
|
|
* sh-opc.h: Likewise.
|
|
|
|
|
|
|
Add support for some variants of the ARC nps400 rflt instruction.
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
0,b,limm to the rflt instruction.
2016-06-01 17:29:27 +02:00
|
|
|
|
2016-06-01 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
|
|
|
|
|
|
0,b,limm to the rflt instruction.
|
|
|
|
|
|
|
2016-05-29 02:29:54 +02:00
|
|
|
|
2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
|
|
|
|
|
|
constant.
|
|
|
|
|
|
|
2016-05-29 17:26:43 +02:00
|
|
|
|
2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20145
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-27 19:05:39 +02:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20145
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
|
|
|
|
|
|
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
|
|
|
|
|
|
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
|
|
|
|
|
|
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
|
|
|
|
|
|
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
|
|
|
|
|
|
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
|
|
|
|
|
|
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
|
|
|
|
|
|
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
|
|
|
|
|
|
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
|
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|
|
|
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
|
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|
|
|
|
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
|
|
|
|
|
|
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
|
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|
|
|
|
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
|
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|
|
CpuRegMask for AVX512.
|
|
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|
|
|
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
|
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|
|
|
|
and CpuRegMask.
|
|
|
|
|
|
(set_bitfield_from_cpu_flag_init): New function.
|
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|
|
|
|
(set_bitfield): Remove const on f. Call
|
|
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|
|
|
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
|
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|
|
|
* i386-opc.h (CpuRegMMX): New.
|
|
|
|
|
|
(CpuRegXMM): Likewise.
|
|
|
|
|
|
(CpuRegYMM): Likewise.
|
|
|
|
|
|
(CpuRegZMM): Likewise.
|
|
|
|
|
|
(CpuRegMask): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
|
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|
|
|
|
and cpuregmask.
|
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|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2016-05-27 17:02:56 +02:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20154
|
|
|
|
|
|
* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
|
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|
|
|
|
(opcode_modifiers): Add AMD64 and Intel64.
|
|
|
|
|
|
(main): Properly verify CpuMax.
|
|
|
|
|
|
* i386-opc.h (CpuAMD64): Removed.
|
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|
|
|
(CpuIntel64): Likewise.
|
|
|
|
|
|
(CpuMax): Set to CpuNo64.
|
|
|
|
|
|
(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
|
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|
|
|
(AMD64): New.
|
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|
|
|
|
(Intel64): Likewise.
|
|
|
|
|
|
(i386_opcode_modifier): Add amd64 and intel64.
|
|
|
|
|
|
(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
|
|
|
|
|
|
on call and jmp.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2016-05-27 15:55:42 +02:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20154
|
|
|
|
|
|
* i386-gen.c (main): Fail if CpuMax is incorrect.
|
|
|
|
|
|
* i386-opc.h (CpuMax): Set to CpuIntel64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2016-05-27 14:49:58 +02:00
|
|
|
|
2016-05-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/20150
|
|
|
|
|
|
* msp430-dis.c (msp430dis_read_two_bytes): New function.
|
|
|
|
|
|
(msp430dis_opcode_unsigned): New function.
|
|
|
|
|
|
(msp430dis_opcode_signed): New function.
|
|
|
|
|
|
(msp430_singleoperand): Use the new opcode reading functions.
|
|
|
|
|
|
Only disassenmble bytes if they were successfully read.
|
|
|
|
|
|
(msp430_doubleoperand): Likewise.
|
|
|
|
|
|
(msp430_branchinstr): Likewise.
|
|
|
|
|
|
(msp430x_callx_instr): Likewise.
|
|
|
|
|
|
(print_insn_msp430): Check that it is safe to read bytes before
|
|
|
|
|
|
attempting disassembly. Use the new opcode reading functions.
|
|
|
|
|
|
|
2016-05-27 02:06:51 +02:00
|
|
|
|
2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (CY): New define. Document it.
|
|
|
|
|
|
(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
|
|
|
|
|
|
|
2016-05-25 20:23:40 +02:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
|
|
|
|
|
|
CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
|
|
|
|
|
|
and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
|
|
|
|
|
|
CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
|
|
|
|
|
|
CPU_ANY_AVX_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2016-05-25 19:49:25 +02:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20141
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
|
|
|
|
|
|
CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2016-05-25 19:25:50 +02:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
|
|
|
|
|
|
CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
[ARC] Update instruction type and delay slot info.
This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
2016-05-19 12:19:32 +02:00
|
|
|
|
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
|
|
|
|
|
|
information.
|
|
|
|
|
|
(print_insn_arc): Set insn_type information.
|
|
|
|
|
|
* arc-opc.c (C_CC): Add F_CLASS_COND.
|
|
|
|
|
|
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
|
|
|
|
|
|
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
|
|
|
|
|
|
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
|
|
|
|
|
|
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
|
|
|
|
|
|
(brne, brne_s, jeq_s, jne_s): Likewise.
|
|
|
|
|
|
|
2016-05-19 12:33:17 +02:00
|
|
|
|
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h (neg): New instruction variant.
|
|
|
|
|
|
|
2016-05-23 17:25:46 +02:00
|
|
|
|
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (find_format, find_format, get_auxreg)
|
|
|
|
|
|
(print_insn_arc): Changed.
|
|
|
|
|
|
* arc-ext.h (INSERT_XOP): Likewise.
|
|
|
|
|
|
|
2016-05-19 05:48:48 +02:00
|
|
|
|
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* tic54x-dis.c (sprint_mmr): Adjust.
|
|
|
|
|
|
* tic54x-opc.c: Likewise.
|
|
|
|
|
|
|
2016-05-19 09:24:54 +02:00
|
|
|
|
2016-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
|
|
|
|
|
|
|
2016-05-18 16:40:35 +02:00
|
|
|
|
2016-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c: Formatting.
|
|
|
|
|
|
(NSISIGNOPT): Define.
|
|
|
|
|
|
(powerpc_opcodes <subis>): Use NSISIGNOPT.
|
|
|
|
|
|
|
2016-05-18 12:22:30 +02:00
|
|
|
|
2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
|
|
|
|
|
|
replacing references to `micromips_ase' throughout.
|
|
|
|
|
|
(_print_insn_mips): Don't use file-level microMIPS annotation to
|
|
|
|
|
|
determine the disassembly mode with the symbol table.
|
|
|
|
|
|
|
2016-05-13 22:15:00 +02:00
|
|
|
|
2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
|
|
|
|
|
|
|
2014-11-26 12:15:01 +01:00
|
|
|
|
2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
|
|
|
|
|
|
mips64r6.
|
|
|
|
|
|
* mips-opc.c (D34): New macro.
|
|
|
|
|
|
(mips_builtin_opcodes): Define bposge32c for DSPr3.
|
|
|
|
|
|
|
2016-05-10 20:35:52 +02:00
|
|
|
|
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Add RDPID instruction.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add RDPID flag.
|
|
|
|
|
|
(cpu_flags): Add RDPID bitfield.
|
|
|
|
|
|
* i386-opc.h (enum): Add RDPID element.
|
|
|
|
|
|
(i386_cpu_flags): Add RDPID field.
|
|
|
|
|
|
* i386-opc.tbl: Add RDPID instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2016-05-10 17:14:23 +02:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
|
|
|
|
|
|
branch type of a symbol.
|
|
|
|
|
|
(print_insn): Likewise.
|
|
|
|
|
|
|
2016-05-10 16:01:53 +02:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
|
|
|
|
|
|
Mainline Security Extensions instructions.
|
|
|
|
|
|
(thumb_opcodes): Add entries for narrow ARMv8-M Security
|
|
|
|
|
|
Extensions instructions.
|
|
|
|
|
|
(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
|
|
|
|
|
|
special registers.
|
|
|
|
|
|
|
2016-05-09 13:09:53 +02:00
|
|
|
|
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
|
|
|
|
|
|
|
2016-05-03 13:44:13 +02:00
|
|
|
|
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
|
|
|
|
|
|
(arcExtMap_genOpcode): Likewise.
|
|
|
|
|
|
* arc-opc.c (arg_32bit_rc): Define new variable.
|
|
|
|
|
|
(arg_32bit_u6): Likewise.
|
|
|
|
|
|
(arg_32bit_limm): Likewise.
|
|
|
|
|
|
|
2016-05-03 12:48:56 +02:00
|
|
|
|
2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-gen.c (VERIFIER): Define.
|
|
|
|
|
|
* aarch64-opc.c (VERIFIER): Define.
|
|
|
|
|
|
(verify_ldpsw): Use static linkage.
|
|
|
|
|
|
* aarch64-opc.h (verify_ldpsw): Remove.
|
|
|
|
|
|
* aarch64-tbl.h: Use VERIFIER for verifiers.
|
|
|
|
|
|
|
2016-04-28 10:11:03 +02:00
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2016-04-28 Nick Clifton <nickc@redhat.com>
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PR target/19722
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* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
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* aarch64-opc.c (verify_ldpsw): New function.
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* aarch64-opc.h (verify_ldpsw): New prototype.
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* aarch64-tbl.h: Add initialiser for verifier field.
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(LDPSW): Set verifier to verify_ldpsw.
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2016-04-23 18:32:59 +02:00
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2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/19983
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PR binutils/19984
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* i386-dis.c (print_insn): Return -1 if size of bfd_vma is
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smaller than address size.
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2016-04-14 00:30:46 +02:00
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2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* alpha-dis.c: Regenerate.
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* crx-dis.c: Likewise.
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* disassemble.c: Likewise.
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* epiphany-opc.c: Likewise.
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* fr30-opc.c: Likewise.
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* frv-opc.c: Likewise.
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* ip2k-opc.c: Likewise.
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* iq2000-opc.c: Likewise.
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* lm32-opc.c: Likewise.
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* lm32-opinst.c: Likewise.
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* m32c-opc.c: Likewise.
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* m32r-opc.c: Likewise.
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* m32r-opinst.c: Likewise.
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* mep-opc.c: Likewise.
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* mt-opc.c: Likewise.
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* or1k-opc.c: Likewise.
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* or1k-opinst.c: Likewise.
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* tic80-opc.c: Likewise.
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* xc16x-opc.c: Likewise.
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* xstormy16-opc.c: Likewise.
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opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands.
There's also a test added into the assembler.
gas/ChangeLog:
* testsuite/gas/arc/nps400-6.d: New file.
* testsuite/gas/arc/nps400-6.s: New file.
include/ChangeLog:
* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp
instructions.
* arc-opc.c (insert_nps_bitop_size): Delete.
(extract_nps_bitop_size): Delete.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
(extract_nps_qcmp_m3): Define.
(extract_nps_qcmp_m2): Define.
(extract_nps_qcmp_m1): Define.
(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
NPS_QCMP_M3.
2016-04-01 20:51:50 +02:00
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
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fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
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calcsd, and calcxd instructions.
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* arc-opc.c (insert_nps_bitop_size): Delete.
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(extract_nps_bitop_size): Delete.
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(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
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(extract_nps_qcmp_m3): Define.
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(extract_nps_qcmp_m2): Define.
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(extract_nps_qcmp_m1): Define.
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(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
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(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
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(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
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NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
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NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
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NPS_QCMP_M3.
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2016-03-31 20:51:14 +02:00
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
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2016-04-16 01:20:02 +02:00
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2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.in: Regenerated with automake 1.11.6.
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* aclocal.m4: Likewise.
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arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-30 01:02:19 +02:00
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2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
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instructions.
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* arc-opc.c (insert_nps_cmem_uimm16): New function.
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(extract_nps_cmem_uimm16): New function.
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(arc_operands): Add NPS_XLDST_UIMM16 operand.
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2016-03-24 17:54:37 +01:00
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2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-dis.c (arc_insn_length): New function.
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(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
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(find_format): Change insnLen parameter to unsigned.
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2016-04-13 16:09:25 +02:00
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2016-04-13 Nick Clifton <nickc@redhat.com>
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PR target/19937
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* v850-opc.c (v850_opcodes): Correct masks for long versions of
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the LD.B and LD.BU instructions.
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2016-04-06 16:08:04 +02:00
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (find_format): Check for extension flags.
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(print_flags): New function.
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(print_insn_arc): Update for .extCondCode, .extCoreRegister and
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.extAuxRegister.
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* arc-ext.c (arcExtMap_coreRegName): Use
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LAST_EXTENSION_CORE_REGISTER.
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(arcExtMap_coreReadWrite): Likewise.
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(dump_ARC_extmap): Update printing.
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* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
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(arc_aux_regs): Add cpu field.
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* arc-regs.h: Add cpu field, lower case name aux registers.
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2016-04-06 16:47:56 +02:00
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-tbl.h: Add rtsc, sleep with no arguments.
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Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
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Initialize.
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(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
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(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
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(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
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(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
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(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
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(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
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(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
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(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
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(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
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(arc_opcode arc_opcodes): Null terminate the array.
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(arc_num_opcodes): Remove.
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* arc-ext.h (INSERT_XOP): Define.
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(extInstruction_t): Likewise.
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(arcExtMap_instName): Delete.
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(arcExtMap_insn): New function.
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(arcExtMap_genOpcode): Likewise.
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* arc-ext.c (ExtInstruction): Remove.
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(create_map): Zero initialize instruction fields.
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(arcExtMap_instName): Remove.
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(arcExtMap_insn): New function.
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(dump_ARC_extmap): More info while debuging.
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(arcExtMap_genOpcode): New function.
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* arc-dis.c (find_format): New function.
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(print_insn_arc): Use find_format.
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(arc_get_disassembler): Enable dump_ARC_extmap only when
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debugging.
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2016-04-11 18:56:01 +02:00
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2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_mips16_insn_arg): Mask unused extended
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instruction bits out.
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2016-03-29 00:05:09 +02:00
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2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
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* arc-opc.c (arc_flag_operands): Add new flags.
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(arc_flag_classes): Add new classes.
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2016-03-28 18:08:29 +02:00
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2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
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arc/nps400: Add additional instructions
Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16,
and crc32 instructions for the nps400 arc machine type.
gas/ChangeLog:
* testsuite/gas/arc/nps400-1.d: Update expected results.
* testsuite/gas/arc/nps400-1.s: Additional test cases.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
encode1, rflt, crc16, and crc32 instructions.
* arc-opc.c (arc_flag_operands): Add F_NPS_R.
(arc_flag_classes): Add C_NPS_R.
(insert_nps_bitop_size_2b): New function.
(extract_nps_bitop_size_2b): Likewise.
(insert_nps_bitop_uimm8): Likewise.
(extract_nps_bitop_uimm8): Likewise.
(arc_operands): Add new operand entries.
2016-03-21 19:49:34 +01:00
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2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
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encode1, rflt, crc16, and crc32 instructions.
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* arc-opc.c (arc_flag_operands): Add F_NPS_R.
|
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(arc_flag_classes): Add C_NPS_R.
|
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(insert_nps_bitop_size_2b): New function.
|
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(extract_nps_bitop_size_2b): Likewise.
|
|
|
|
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(insert_nps_bitop_uimm8): Likewise.
|
|
|
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|
(extract_nps_bitop_uimm8): Likewise.
|
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(arc_operands): Add new operand entries.
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2016-04-05 17:37:29 +02:00
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2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
|
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Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
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|
* arc-regs.h: Add a new subclass field. Add double assist
|
|
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|
|
|
accumulator register values.
|
|
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|
|
* arc-tbl.h: Use DPA subclass to mark the double assist
|
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instructions. Use DPX/SPX subclas to mark the FPX instructions.
|
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* arc-opc.c (RSP): Define instead of SP.
|
|
|
|
|
|
(arc_aux_regs): Add the subclass field.
|
2016-04-05 17:37:29 +02:00
|
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|
2016-04-05 16:54:00 +02:00
|
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|
2016-04-05 Jiong Wang <jiong.wang@arm.com>
|
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* arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
|
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|
|
2016-03-31 15:16:10 +02:00
|
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2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
|
2016-03-24 18:18:41 +01:00
|
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* arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
|
|
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|
|
NPS_R_SRC1.
|
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|
2016-03-30 19:13:31 +02:00
|
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|
2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
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|
|
|
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|
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* arc-nps400-tbl.h: Add a header comment, and fix some whitespace
|
|
|
|
|
|
issues. No functional changes.
|
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|
|
[ARC] Cleanup AUX register names.
opcodes/
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
(RTT): Remove duplicate.
(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
(PCT_CONFIG*): Remove.
(D1L, D1H, D2H, D2L): Define.
2016-03-30 16:06:54 +02:00
|
|
|
|
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
|
* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
|
|
|
|
|
|
(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
|
|
|
|
|
|
(RTT): Remove duplicate.
|
|
|
|
|
|
(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
|
|
|
|
|
|
(PCT_CONFIG*): Remove.
|
|
|
|
|
|
(D1L, D1H, D2H, D2L): Define.
|
[ARC] Cleanup AUX register names.
opcodes/
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
(RTT): Remove duplicate.
(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
(PCT_CONFIG*): Remove.
(D1L, D1H, D2H, D2L): Define.
2016-03-30 16:06:54 +02:00
|
|
|
|
|
2016-03-29 19:05:31 +02:00
|
|
|
|
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
|
* arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
|
2016-03-29 19:05:31 +02:00
|
|
|
|
|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
|
|
|
|
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
|
* arc-tbl.h (invld07): Remove.
|
|
|
|
|
|
* arc-ext-tbl.h: New file.
|
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|
|
|
|
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
|
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|
|
* arc-opc.c (arc_opcodes): Add ext-tbl include.
|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
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2016-03-24 22:42:09 +01:00
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|
2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
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|
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|
|
Fix -Wstack-usage warnings.
|
|
|
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|
|
* aarch64-dis.c (print_operands): Substitute size.
|
|
|
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|
|
* aarch64-opc.c (print_register_offset_address): Substitute tblen.
|
|
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|
2016-03-24 18:20:45 +01:00
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|
|
2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
|
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|
* sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
|
|
|
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|
|
to get a proper diagnostic when an invalid ASR register is used.
|
|
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|
2016-03-22 10:41:16 +01:00
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|
2016-03-22 Nick Clifton <nickc@redhat.com>
|
|
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* configure: Regenerate.
|
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2016-03-15 23:01:34 +01:00
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
* arc-nps400-tbl.h: New file.
|
|
|
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|
* arc-opc.c: Add top level comment.
|
|
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|
(insert_nps_3bit_dst): New function.
|
|
|
|
|
|
(extract_nps_3bit_dst): New function.
|
|
|
|
|
|
(insert_nps_3bit_src2): New function.
|
|
|
|
|
|
(extract_nps_3bit_src2): New function.
|
|
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|
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|
(insert_nps_bitop_size): New function.
|
|
|
|
|
|
(extract_nps_bitop_size): New function.
|
|
|
|
|
|
(arc_flag_operands): Add nps400 entries.
|
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|
(arc_flag_classes): Add nps400 entries.
|
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(arc_operands): Add nps400 entries.
|
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|
(arc_opcodes): Add nps400 include.
|
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|
arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
2016-03-14 23:17:47 +01:00
|
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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* arc-opc.c (arc_flag_classes): Convert all flag classes to use
|
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|
|
the new class enum values.
|
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|
2016-03-15 22:51:50 +01:00
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
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* arc-dis.c (print_insn_arc): Handle nps400.
|
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|
2016-03-01 12:41:12 +01:00
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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* arc-opc.c (BASE): Delete.
|
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2016-03-18 18:02:20 +01:00
|
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|
2016-03-18 Nick Clifton <nickc@redhat.com>
|
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PR target/19721
|
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* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
|
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|
|
of MOV insn that aliases an ORR insn.
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2016-03-16 17:11:59 +01:00
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|
|
2016-03-16 Jiong Wang <jiong.wang@arm.com>
|
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* arm-dis.c (neon_opcodes): Support new FP16 instructions.
|
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2016-03-07 16:16:28 +01:00
|
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|
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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* mcore-opc.h: Add const qualifiers.
|
|
|
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|
|
* microblaze-opc.h (struct op_code_struct): Likewise.
|
|
|
|
|
|
* sh-opc.h: Likewise.
|
|
|
|
|
|
* tic4x-dis.c (tic4x_print_indirect): Likewise.
|
|
|
|
|
|
(tic4x_print_op): Likewise.
|
|
|
|
|
|
|
2016-03-01 23:28:07 +01:00
|
|
|
|
2016-03-02 Alan Modra <amodra@gmail.com>
|
|
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|
|
2016-03-02 14:50:27 +01:00
|
|
|
|
* or1k-desc.h: Regenerate.
|
2016-03-01 23:28:07 +01:00
|
|
|
|
* fr30-ibld.c: Regenerate.
|
2016-03-02 03:11:01 +01:00
|
|
|
|
* rl78-decode.c: Regenerate.
|
2016-03-01 23:28:07 +01:00
|
|
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|
|
2016-03-01 11:52:24 +01:00
|
|
|
|
2016-03-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19747
|
|
|
|
|
|
* rl78-dis.c (print_insn_rl78_common): Fix typo.
|
|
|
|
|
|
|
2016-02-24 15:08:39 +01:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
|
|
|
|
|
|
(print_insn_coprocessor): Support fp16 instructions.
|
|
|
|
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|
|
2016-02-24 14:55:30 +01:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
|
|
|
|
|
|
vminnm, vrint(mpna).
|
|
|
|
|
|
|
2016-02-24 14:48:59 +01:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Check co-processor number for
|
|
|
|
|
|
cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
|
|
|
|
|
|
|
2016-02-16 00:58:42 +01:00
|
|
|
|
2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Parenthesize expression to prevent
|
|
|
|
|
|
truncated addresses.
|
|
|
|
|
|
(OP_J): Likewise.
|
|
|
|
|
|
|
Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 13:09:01 +01:00
|
|
|
|
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
Janek van Oirschot <jvanoirs@synopsys.com>
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
|
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
|
|
|
|
|
|
variable.
|
Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 13:09:01 +01:00
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2016-02-04 10:55:10 +01:00
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* msp430-dis.c (print_insn_msp430): Add a special case for
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decoding an RRC instruction with the ZC bit set in the extension
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word.
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opcodes/cgen: Rework calculation of shift when inserting fields
The calculation of the shift amount, used to insert fields into the
instruction buffer, is not correct when the following conditions are all
true:
- CGEN_INT_INSN_P is defined, and true.
- CGEN_INSN_LSB0_P is true
- Total instruction length is greater than the length of a single
instruction word (the instruction is made of multiple words)
- The word offset is non-zero (the field is outside the first word)
When the above conditions are all true, the calculated shift fails to
take account of the total instruction length.
After this commit the calculation of the shift amount is split into two
parts, first we calculate the shift required to get to BIT0 of the word
in which the field lives, then we calculate the shift required to place
the field within the instruction word.
The change in this commit only effects the CGEN_INT_INSN_P defined true
case, but changes the code for both CGEN_INSN_LSB0_P true, and false.
In the case of CGEN_INSN_LSB0_P being false, the code used to say:
shift = total_length - (word_offset + start + length);
Now it says:
shift_to_word = total_length - (word_offset + word_length);
shift_within_word = word_length - start - length;
shift = shift_to_word + shift_within_word;
From which we can see that in all cases the computed shift value should
be unchanged.
In the case of CGEN_INSN_LSB0_P being true, the code used to say:
shift = (word_offset + start + 1) - length;
Now it says:
shift_to_word = total_length - (word_offset + word_length);
shift_within_word = start + 1 - length;
shift = shift_to_word + shift_within_word;
In the case where 'total_length == word_length' AND 'word_offset ==
0' (which indicates an instruction of a single word), we see that the
computed shift value will be unchanged. However, when the total_length
and word_length are different, and the word_offset is non-zero then the
computed shift value will be different (and correct).
opcodes/ChangeLog:
* cgen-ibld.in (insert_normal): Rework calculation of shift.
* epiphany-ibld.c: Regenerate.
* fr30-ibld.c: Regenerate.
* frv-ibld.c: Regenerate.
* ip2k-ibld.c: Regenerate.
* iq2000-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32r-ibld.c: Regenerate.
* mep-ibld.c: Regenerate.
* mt-ibld.c: Regenerate.
* or1k-ibld.c: Regenerate.
* xc16x-ibld.c: Regenerate.
* xstormy16-ibld.c: Regenerate.
2016-01-31 01:41:12 +01:00
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* cgen-ibld.in (insert_normal): Rework calculation of shift.
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* epiphany-ibld.c: Regenerate.
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* fr30-ibld.c: Regenerate.
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* frv-ibld.c: Regenerate.
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* ip2k-ibld.c: Regenerate.
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* iq2000-ibld.c: Regenerate.
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* lm32-ibld.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32r-ibld.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mt-ibld.c: Regenerate.
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* or1k-ibld.c: Regenerate.
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* xc16x-ibld.c: Regenerate.
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* xstormy16-ibld.c: Regenerate.
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2016-02-01 19:21:37 +01:00
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* epiphany-dis.c: Regenerated from latest cpu files.
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2016-02-01 11:41:32 +01:00
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2016-02-01 Michael McConville <mmcco@mykolab.com>
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* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
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test bit.
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2016-01-25 16:06:54 +01:00
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2016-01-25 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (mapping_symbol_for_insn): New function.
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(find_ifthen_state): Call mapping_symbol_for_insn().
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2016-01-20 15:25:46 +01:00
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2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (operand_general_constraint_met_p): Check validity
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of MSR UAO immediate operand.
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MIPS: Remove remnants of 48-bit microMIPS instruction support
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.
This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
Major Opcode Field", p. 578
gas/
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
gdb/
* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
instruction support.
(micromips_next_pc): Likewise.
(micromips_scan_prologue): Likewise.
(micromips_deal_with_atomic_sequence): Likewise.
(micromips_stack_frame_destroyed_p): Likewise.
(mips_breakpoint_from_pc): Likewise.
opcodes/
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
instruction support.
2016-01-18 22:29:37 +01:00
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2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
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instruction support.
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2016-01-17 02:50:55 +01:00
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2016-01-17 Alan Modra <amodra@gmail.com>
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* configure: Regenerate.
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2016-01-14 17:23:35 +01:00
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2016-01-14 Nick Clifton <nickc@redhat.com>
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* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
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instructions that can support stack pointer operations.
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* rl78-decode.c: Regenerate.
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* rl78-dis.c: Fix display of stack pointer in MOVW based
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instructions.
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2016-01-14 11:55:11 +01:00
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2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
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testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
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erxtatus_el1 and erxaddr_el1.
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2016-01-12 17:35:30 +01:00
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2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
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* arm-dis.c (arm_opcodes): Add "esb".
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(thumb_opcodes): Likewise.
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2016-01-11 18:54:58 +01:00
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2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c <xscmpnedp>: Delete.
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<xvcmpnedp>: Likewise.
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<xvcmpnedp.>: Likewise.
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<xvcmpnesp>: Likewise.
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<xvcmpnesp.>: Likewise.
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2016-01-08 11:38:00 +01:00
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2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
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PR gas/13050
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* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
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addition to ISA_A.
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2016-01-01 12:25:12 +01:00
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2016-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2016-01-01 11:44:31 +01:00
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For older changes see ChangeLog-2015
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Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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