2017-07-07 04:44:53 +02:00
|
|
|
|
2017-07-07 Alan Modra <amodra@gmail.com>
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|
|
* cgen-dis.in: Include disassemble.h, not dis-asm.h.
|
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|
|
* m32c-dis.c: Regenerate.
|
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|
* mep-dis.c: Regenerate.
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2017-07-05 11:27:49 +02:00
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|
2017-07-05 Borislav Petkov <bp@suse.de>
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* i386-dis.c: Enable ModRM.reg /6 aliases.
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2017-07-05 11:21:07 +02:00
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|
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
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* opcodes/arm-dis.c: Support MVFR2 in disassembly
|
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|
|
with vmrs and vmsr.
|
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|
2017-07-04 11:15:33 +02:00
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2017-07-04 Tristan Gingold <gingold@adacore.com>
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* configure: Regenerate.
|
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|
2017-07-03 17:02:01 +02:00
|
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|
|
2017-07-03 Tristan Gingold <gingold@adacore.com>
|
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* po/opcodes.pot: Regenerate.
|
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|
2017-06-30 16:27:18 +02:00
|
|
|
|
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
* mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
|
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|
entries to the MSA ASE instruction block.
|
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MIPS: Add microMIPS XPA support
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
2017-06-30 08:21:56 +02:00
|
|
|
|
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
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|
Maciej W. Rozycki <macro@imgtec.com>
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|
* micromips-opc.c (XPA, XPAVZ): New macros.
|
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|
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
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|
"mthgc0".
|
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|
MIPS: Add microMIPS R5 support
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30 08:21:56 +02:00
|
|
|
|
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
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|
|
Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
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|
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|
|
* micromips-opc.c (I36): New macro.
|
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|
|
(micromips_opcodes): Add "eretnc".
|
|
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|
|
2017-06-30 08:21:55 +02:00
|
|
|
|
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
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|
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|
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|
|
|
|
* mips-dis.c (mips_calculate_combination_ases): Handle the
|
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|
|
ASE_XPA_VIRT flag.
|
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|
|
(parse_mips_ase_option): New function.
|
|
|
|
|
|
(parse_mips_dis_option): Factor out ASE option handling to the
|
|
|
|
|
|
new function. Call `mips_calculate_combination_ases'.
|
|
|
|
|
|
* mips-opc.c (XPAVZ): New macro.
|
|
|
|
|
|
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
|
|
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|
|
"mfhgc0", "mthc0" and "mthgc0".
|
|
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|
|
2017-06-30 01:55:07 +02:00
|
|
|
|
2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
|
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|
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|
|
* mips-dis.c (mips_calculate_combination_ases): New function.
|
|
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|
|
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
|
|
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|
|
calculation to the new function.
|
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|
|
(set_default_mips_dis_options): Call the new function.
|
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|
2017-06-19 12:27:52 +02:00
|
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|
2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
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|
|
|
|
|
* arc-dis.c (parse_disassembler_options): Use
|
|
|
|
|
|
FOR_EACH_DISASSEMBLER_OPTION.
|
|
|
|
|
|
|
[ARC] Fix handling of cpu=... disassembler option value
There is a bug in handling of cpu=... disassembler option in case there are
other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is
treated as an option value, and strcasecmp reports is as non-equal to "EM".
This is fixed by using disassembler_options_cmp function, which compares string
treating `,' the same way as `\0'.
This function also solves a problem with option order in parse_option.
Previously, if several option had same prefix (e.g. fpud, fpuda), then the
longer one should have been compared first, otherwise when longer option is
passed it would be treated as a short one, because
CONST_STRNEQ ("fpud", "fpuda")
would be true. The order of options was correct for ARC, so there were no
bugs per se, but with disassembler_option_cmp there is no risk of such a bug
being introduced in the future.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
disassembler option strings.
(parse_cpu_option): Likewise.
binutils/ChangeLog
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* testsuite/binutils-all/arc/double_store.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Tests for disassembler
options.
(do_objfile): New function.
(check_assembly): Likewise.
2017-06-15 14:58:32 +02:00
|
|
|
|
2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
|
|
|
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|
|
|
|
|
|
|
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
|
|
|
|
|
|
disassembler option strings.
|
|
|
|
|
|
(parse_cpu_option): Likewise.
|
|
|
|
|
|
|
2017-06-28 12:09:01 +02:00
|
|
|
|
2017-06-28 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
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|
|
* aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_reglane): Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
|
|
|
|
|
|
(aarch64_feature_dotprod, DOT_INSN): New.
|
|
|
|
|
|
(udot, sdot): New.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
|
2017-06-28 12:00:55 +02:00
|
|
|
|
2017-06-28 Jiong Wang <jiong.wang@arm.com>
|
|
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|
|
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|
|
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
|
|
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|
|
|
|
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
2017-06-28 03:07:36 +02:00
|
|
|
|
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Matthew Fortune <matthew.fortune@imgtec.com>
|
2017-06-30 08:21:56 +02:00
|
|
|
|
Andrew Bennett <andrew.bennett@imgtec.com>
|
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
2017-06-28 03:07:36 +02:00
|
|
|
|
|
|
|
|
|
|
* mips-formats.h (INT_BIAS): New macro.
|
|
|
|
|
|
(INT_ADJ): Redefine in INT_BIAS terms.
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
|
|
|
|
|
|
(mips_print_save_restore): New function.
|
|
|
|
|
|
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
|
|
|
|
|
|
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
|
|
|
|
|
|
call.
|
|
|
|
|
|
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
|
|
|
|
|
|
(print_mips16_insn_arg): Call `mips_print_save_restore' for
|
|
|
|
|
|
OP_SAVE_RESTORE_LIST handling, factored out from here.
|
|
|
|
|
|
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
|
|
|
|
|
|
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
|
|
|
|
|
|
(mips_builtin_opcodes): Add "restore" and "save" entries.
|
|
|
|
|
|
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
|
|
|
|
|
|
(IAMR2): New macro.
|
|
|
|
|
|
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
|
|
|
|
|
|
|
2017-05-15 17:50:57 +02:00
|
|
|
|
2017-06-23 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
|
|
|
|
|
|
alias; do not mark SLTI instruction as an alias.
|
|
|
|
|
|
|
2017-06-21 17:32:38 +02:00
|
|
|
|
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (RM_0FAE_REG_5): Removed.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
|
|
|
|
|
|
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
|
|
|
|
|
|
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
|
|
|
|
|
|
PREFIX_MOD_3_0F01_REG_5_RM_0.
|
|
|
|
|
|
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
|
|
|
|
|
|
PREFIX_MOD_3_0FAE_REG_5.
|
|
|
|
|
|
(mod_table): Update MOD_0FAE_REG_5.
|
|
|
|
|
|
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
|
|
|
|
|
|
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2017-06-21 17:30:01 +02:00
|
|
|
|
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
|
|
|
|
|
|
* i386-opc.tbl: Likewise.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2017-06-21 17:28:30 +02:00
|
|
|
|
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
|
|
|
|
|
|
and "jmp{&|}".
|
|
|
|
|
|
(NOTRACK_Fixup): Support memory indirect branch with NOTRACK
|
|
|
|
|
|
prefix.
|
|
|
|
|
|
|
2017-06-19 15:15:57 +02:00
|
|
|
|
2017-06-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21614
|
|
|
|
|
|
* score-dis.c (score_opcodes): Add sentinel.
|
|
|
|
|
|
|
2017-06-16 14:20:43 +02:00
|
|
|
|
2017-06-16 Alan Modra <amodra@gmail.com>
|
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|
|
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|
|
* rx-decode.c: Regenerate.
|
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|
|
|
2017-06-15 15:40:17 +02:00
|
|
|
|
2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21594
|
|
|
|
|
|
* i386-dis.c (OP_E_register): Check valid bnd register.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
|
2017-06-15 14:26:54 +02:00
|
|
|
|
2017-06-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21595
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
|
|
|
|
|
|
range value.
|
|
|
|
|
|
|
2017-06-15 13:37:01 +02:00
|
|
|
|
2017-06-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21588
|
|
|
|
|
|
* rl78-decode.opc (OP_BUF_LEN): Define.
|
|
|
|
|
|
(GETBYTE): Check for the index exceeding OP_BUF_LEN.
|
|
|
|
|
|
(rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
|
|
|
|
|
|
array.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2017-06-15 12:52:02 +02:00
|
|
|
|
2017-06-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21586
|
|
|
|
|
|
* bfin-dis.c (gregs): Clip index to prevent overflow.
|
|
|
|
|
|
(regs): Likewise.
|
|
|
|
|
|
(regs_lo): Likewise.
|
|
|
|
|
|
(regs_hi): Likewise.
|
|
|
|
|
|
|
2017-06-14 18:10:28 +02:00
|
|
|
|
2017-06-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21576
|
|
|
|
|
|
* score7-dis.c (score_opcodes): Add sentinel.
|
|
|
|
|
|
|
Don't use print_insn_XXX in GDB
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14 17:28:30 +02:00
|
|
|
|
2017-06-14 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
|
|
|
|
|
|
* arm-dis.c: Likewise.
|
|
|
|
|
|
* ia64-dis.c: Likewise.
|
|
|
|
|
|
* mips-dis.c: Likewise.
|
|
|
|
|
|
* spu-dis.c: Likewise.
|
|
|
|
|
|
* disassemble.h (print_insn_aarch64): New declaration, moved from
|
|
|
|
|
|
include/dis-asm.h.
|
|
|
|
|
|
(print_insn_big_arm, print_insn_big_mips): Likewise.
|
|
|
|
|
|
(print_insn_i386, print_insn_ia64): Likewise.
|
|
|
|
|
|
(print_insn_little_arm, print_insn_little_mips): Likewise.
|
|
|
|
|
|
|
2017-06-14 14:35:06 +02:00
|
|
|
|
2017-06-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21587
|
|
|
|
|
|
* rx-decode.opc: Include libiberty.h
|
|
|
|
|
|
(GET_SCALE): New macro - validates access to SCALE array.
|
|
|
|
|
|
(GET_PSCALE): New macro - validates access to PSCALE array.
|
|
|
|
|
|
(DIs, SIs, S2Is, rx_disp): Use new macros.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
2017-06-14 11:52:40 +02:00
|
|
|
|
2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Remove bogus entry for bx.
|
|
|
|
|
|
|
[ARC] Allow CPU to be enforced via disassemble_info options
Currently print_insn_arc relies on BFD mach and ELF private headers to
distinguish between various ARC architectures. Sometimes those values are not
correct or available, mainly in the case of debugging targets without and ELF
file available. Changing a BFD mach is not a problem for the debugger, because
this is a generic BFD field, and GDB, for example, already sets it according to
information provided in XML target description or specified via GDB 'set arch'
command. However, things are more complicated for ELF private headers, since
it requires existing of an actual ELF file. To workaround this problem this
patch allows CPU model to be specified via disassemble info options. If CPU is
specified in options, then it will take a higher precedence than whatever might
be specified in ELF file.
This is mostly needed for ARC EM and ARC HS, because they have the same
"architecture" (mach) ARCv2 and differ in their private ELF headers. Other ARC
architectures can be distinguished between each other purely via "mach" field.
Proposed disassemble option format is "cpu=<CPU>", where CPU can be any valid
ARC CPU name as supported by GAS. Note that this creates a seeming redundancy
with objdump -m/--architecture option, however -mEM and -mHS still result in
"ARCv2" architecture internally, while -Mcpu={HS,EM} would have an actual
effect on disassembler.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (enforced_isa_mask): Declare.
(cpu_types): Likewise.
(parse_cpu_option): New function.
(parse_disassembler_options): Use it.
(print_insn_arc): Use enforced_isa_mask.
(print_arc_disassembler_options): Document new options.
binutils/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* doc/binutils.texi: Document new cpu=... disassembler options for ARC.
2017-03-16 13:21:31 +01:00
|
|
|
|
2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (enforced_isa_mask): Declare.
|
|
|
|
|
|
(cpu_types): Likewise.
|
|
|
|
|
|
(parse_cpu_option): New function.
|
|
|
|
|
|
(parse_disassembler_options): Use it.
|
|
|
|
|
|
(print_insn_arc): Use enforced_isa_mask.
|
|
|
|
|
|
(print_arc_disassembler_options): Document new options.
|
|
|
|
|
|
|
Move print_insn_XXX to an opcodes internal header
With the changes done in previous patches, print_insn_XXX functions
don't have to be external visible out of opcodes, because both gdb
and objdump select disassemblers through a single interface.
This patch moves these print_insn_XXX declarations from
include/dis-asm.h to opcodes/disassemble.h, which is a new header
added by this patch.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h: Move some function declarations to
opcodes/disassemble.h.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-dis.c: Include disassemble.h, don't include
dis-asm.h.
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
* moxie-dis.c, msp430-dis.c, mt-dis.c:
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
* z80-dis.c, z8k-dis.c: Likewise.
* disassemble.h: New file.
2017-05-24 18:23:52 +02:00
|
|
|
|
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* alpha-dis.c: Include disassemble.h, don't include
|
|
|
|
|
|
dis-asm.h.
|
|
|
|
|
|
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
|
|
|
|
|
|
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
|
|
|
|
|
|
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
|
|
|
|
|
|
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
|
|
|
|
|
|
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
|
|
|
|
|
|
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
|
|
|
|
|
|
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
|
|
|
|
|
|
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
|
|
|
|
|
|
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
|
|
|
|
|
|
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
|
|
|
|
|
|
* moxie-dis.c, msp430-dis.c, mt-dis.c:
|
|
|
|
|
|
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
|
|
|
|
|
|
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
|
|
|
|
|
|
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
|
|
|
|
|
|
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
|
|
|
|
|
|
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
|
|
|
|
|
|
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
|
|
|
|
|
|
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
|
|
|
|
|
|
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
|
|
|
|
|
|
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
|
|
|
|
|
|
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
|
|
|
|
|
|
* z80-dis.c, z8k-dis.c: Likewise.
|
|
|
|
|
|
* disassemble.h: New file.
|
|
|
|
|
|
|
2017-05-24 18:23:52 +02:00
|
|
|
|
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-dis.c (rl78_get_disassembler): If parameter abfd
|
|
|
|
|
|
is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
|
|
|
|
|
|
|
2017-05-24 18:23:52 +02:00
|
|
|
|
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassembler): Add arguments a, big and mach.
|
|
|
|
|
|
Use them.
|
|
|
|
|
|
|
2017-05-22 20:02:46 +02:00
|
|
|
|
2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (NOTRACK_Fixup): New.
|
|
|
|
|
|
(NOTRACK): Likewise.
|
|
|
|
|
|
(NOTRACK_PREFIX): Likewise.
|
|
|
|
|
|
(last_active_prefix): Likewise.
|
|
|
|
|
|
(reg_table): Use NOTRACK on indirect call and jmp.
|
|
|
|
|
|
(ckprefix): Set last_active_prefix.
|
|
|
|
|
|
(prefix_name): Return "notrack" for NOTRACK_PREFIX.
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
|
|
|
|
|
|
* i386-opc.h (NoTrackPrefixOk): New.
|
|
|
|
|
|
(i386_opcode_modifier): Add notrackprefixok.
|
|
|
|
|
|
* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
|
|
|
|
|
|
Add notrack.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19 18:27:08 +02:00
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2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
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(X_IMM2): Define.
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(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
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bfd_mach_sparc_v9m8.
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(print_insn_sparc): Handle new operand types.
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* sparc-opc.c (MASK_M8): Define.
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(v6): Add MASK_M8.
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(v6notlet): Likewise.
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(v7): Likewise.
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(v8): Likewise.
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(v9): Likewise.
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(v9a): Likewise.
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(v9b): Likewise.
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(v9c): Likewise.
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(v9d): Likewise.
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(v9e): Likewise.
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(v9v): Likewise.
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(v9m): Likewise.
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(v9andleon): Likewise.
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(m8): Define.
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(HWS_VM8): Define.
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(HWS2_VM8): Likewise.
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(sparc_opcode_archs): Add entry for "m8".
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(sparc_opcodes): Add OSA2017 and M8 instructions
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dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
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fpx{ll,ra,rl}64x,
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ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
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ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
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revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
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stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
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(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
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ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
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ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
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ASI_CORE_SELECT_COMMIT_NHT.
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2017-05-18 07:17:40 +02:00
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2017-05-18 Alan Modra <amodra@gmail.com>
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* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
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* aarch64-dis.c: Likewise.
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* aarch64-gen.c: Likewise.
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* aarch64-opc.c: Likewise.
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MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
2017-05-15 14:26:01 +02:00
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2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
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ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
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(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
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(print_insn_arg) <OP_REG28>: Add handler.
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(validate_insn_args) <OP_REG28>: Handle.
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(print_mips16_insn_arg): Handle MIPS16 instructions that require
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32-bit encoding and 9-bit immediates.
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(print_insn_mips16): Handle MIPS16 instructions that require
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32-bit encoding and MFC0/MTC0 operand decoding.
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* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
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<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
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(RD_C0, WR_C0, E2, E2MT): New macros.
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(mips16_opcodes): Add entries for MIPS16e2 instructions:
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GP-relative "addiu" and its "addu" spelling, "andi", "cache",
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"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
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"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
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"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
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"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
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instructions, "swl", "swr", "sync" and its "sync_acquire",
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"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
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"xori", "dmt", "dvpe", "emt" and "evpe". Add split
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regular/extended entries for original MIPS16 ISA revision
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instructions whose extended forms are subdecoded in the MIPS16e2
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ISA revision: "li", "sll" and "srl".
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2017-05-15 14:04:19 +02:00
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2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
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reference in CP0 move operand decoding.
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2017-05-12 02:09:36 +02:00
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2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
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type to hexadecimal.
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(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
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MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.
References:
[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 305
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 481
opcodes/
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
"sync_rmb" and "sync_wmb" as aliases.
* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
gas/
* testsuite/gas/mips/mips32r2-sync-1.d: New test.
* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-05-12 01:46:45 +02:00
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2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
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* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
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"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
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"sync_rmb" and "sync_wmb" as aliases.
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* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
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"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
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[ARC] Object attributes.
gas/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/attr-arc600.d: New file.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.s: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-name.s: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.s
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
* testsuite/gas/arc/blank.s: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/nps400-0.d: Likewise.
* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
* config/tc-arc.c (opcode/arc-attrs.h): Include.
(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
(arc_attribute): Declare new function.
(md_pseudo_table): Add arc_attribute.
(cpu_types): Rename default cpu features.
(selected_cpu): Set the default OSABI flag.
(mpy_option): New variable.
(pic_option): Likewise.
(sda_option): Likewise.
(tls_option): Likewise.
(feature_type, feature_list): Remove.
(arc_initial_eflag): Likewise.
(attributes_set_explicitly): New variable.
(arc_check_feature): Check also for the conflicting features.
(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
(arc_option): Remove setting of private flags and architecture.
(check_cpu_feature): Refactor feature names.
(autodetect_attributes): New function.
(assemble_tokens): Use above function.
(md_parse_option): Refactor feature names.
(arc_attribute): New function.
(arc_set_attribute_int): Likewise.
(arc_set_attribute_string): Likewise.
(arc_stralloc): Likewise.
(arc_set_public_attributes): Likewise.
(arc_md_end): Likewise.
(arc_copy_symbol_attributes): Likewise.
(rc_convert_symbolic_attribute): Likewise.
* config/tc-arc.h (md_end): Define.
(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
* doc/c-arc.texi: Document ARC object attributes.
binutils/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
(get_arc_section_type_name): New function.
(get_section_type_name): Use the above function.
(display_arc_attribute): New function.
(process_arc_specific): Likewise.
(process_arch_specific): Handle ARC specific information.
* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
section.
include/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
(Tag_ARC_*): Define.
(E_ARC_OSABI_V4): Define.
(E_ARC_OSABI_CURRENT): Reassign it.
(TAG_CPU_*): Define.
* opcode/arc-attrs.h: New file.
* opcode/arc.h (insn_subclass_t): Assign enum values.
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
(ARC_CRC): Delete.
bfd/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf32-arc.c (FEATURE_LIST_NAME): Define.
(CONFLICT_LIST): Likewise.
(opcode/arc-attrs.h): Include.
(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
(arc_extract_features): New file.
(arc_stralloc): Likewise.
(arc_elf_merge_attributes): Likewise.
(arc_elf_merge_private_bfd_data): Use object attributes.
(bfd_arc_get_mach_from_attributes): New function.
(arc_elf_object_p): Use object attributes.
(arc_elf_final_write_processing): Likewise.
(elf32_arc_obj_attrs_arg_type): New function.
(elf32_arc_obj_attrs_handle_unknown): Likewise.
(elf32_arc_section_from_shdr): Likewise.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Likewise.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_handle_unknown): Likewise.
(elf_backend_section_from_shdr): Likewise.
ld/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/attr-merge-0.d: New file.
* testsuite/ld-arc/attr-merge-0.s: Likewise.
* testsuite/ld-arc/attr-merge-0e.s: Likewise.
* testsuite/ld-arc/attr-merge-1.d: Likewise.
* testsuite/ld-arc/attr-merge-1.s: Likewise.
* testsuite/ld-arc/attr-merge-1e.s: Likewise.
* testsuite/ld-arc/attr-merge-2.d: Likewise.
* testsuite/ld-arc/attr-merge-2.s: Likewise.
* testsuite/ld-arc/attr-merge-3.d: Likewise.
* testsuite/ld-arc/attr-merge-3.s: Likewise.
* testsuite/ld-arc/attr-merge-3e.s: Likewise.
* testsuite/ld-arc/attr-merge-4.s: Likewise.
* testsuite/ld-arc/attr-merge-5.d: Likewise.
* testsuite/ld-arc/attr-merge-5a.s: Likewise.
* testsuite/ld-arc/attr-merge-5b.s: Likewise.
* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
* testsuite/ld-arc/got-01.d: Update test.
* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
* testsuite/ld-arc/attr-quarkse.s: Likewise.
* testsuite/ld-arc/attr-quarkse2.s: Likewise.
opcodes/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (parse_option): Update quarkse_em option..
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
QUARKSE1.
(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
|
|
|
|
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
|
* arc-dis.c (parse_option): Update quarkse_em option..
|
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|
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
|
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|
QUARKSE1.
|
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(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
|
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2017-04-05 14:58:28 +02:00
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2017-05-03 Kito Cheng <kito.cheng@gmail.com>
|
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* riscv-dis.c (print_insn_args): Handle 'Co' operands.
|
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2017-04-27 06:08:46 +02:00
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2017-05-01 Michael Clark <michaeljclark@mac.com>
|
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* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
|
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register.
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2017-05-02 12:53:30 +02:00
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2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
|
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and branches and not synthetic data instructions.
|
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2017-05-02 11:28:09 +02:00
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2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
|
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* arm-dis.c (print_insn_thumb32): Fix value_in_comment.
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2017-04-25 17:07:00 +02:00
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
|
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* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
|
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* arc-opc.c (insert_r13el): New function.
|
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(R13_EL): Define.
|
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* arc-tbl.h: Add new enter/leave variants.
|
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2017-04-25 17:07:00 +02:00
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
|
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* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
|
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2017-04-25 12:49:37 +02:00
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2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips-dis.c (print_mips_disassembler_options): Add
|
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`no-aliases'.
|
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MIPS16/opcodes: Annotate instruction aliases
Complement commit 986e18a5a9fd ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases. These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.
binutils/
* testsuite/binutils-all/mips/mips16-alias.d: New test.
* testsuite/binutils-all/mips/mips16-noalias.d: New test.
* testsuite/binutils-all/mips/mips16-alias.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
opcodes/
* mips16-opc.c (AL): New macro.
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
of "ld" and "lw" as aliases.
2017-04-25 12:44:29 +02:00
|
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2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
|
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* mips16-opc.c (AL): New macro.
|
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(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
|
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of "ld" and "lw" as aliases.
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2017-04-24 12:55:44 +02:00
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2017-04-24 Tamar Christina <tamar.christina@arm.com>
|
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* aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
|
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arguments.
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2017-04-22 06:39:21 +02:00
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2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
|
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|
Alan Modra <amodra@gmail.com>
|
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* ppc-opc.c (ELEV): Define.
|
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(vle_opcodes): Add se_rfgi and e_sc.
|
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(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
|
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for E200Z4.
|
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2017-04-21 14:19:06 +02:00
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2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
|
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* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
|
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2017-04-21 13:18:06 +02:00
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2017-04-21 Nick Clifton <nickc@redhat.com>
|
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PR binutils/21380
|
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* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
|
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LD3R and LD4R.
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2017-04-13 03:03:53 +02:00
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2017-04-13 Alan Modra <amodra@gmail.com>
|
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* epiphany-desc.c: Regenerate.
|
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* fr30-desc.c: Regenerate.
|
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* frv-desc.c: Regenerate.
|
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* ip2k-desc.c: Regenerate.
|
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* iq2000-desc.c: Regenerate.
|
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* lm32-desc.c: Regenerate.
|
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* m32c-desc.c: Regenerate.
|
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* m32r-desc.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mt-desc.c: Regenerate.
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* or1k-desc.c: Regenerate.
|
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* xc16x-desc.c: Regenerate.
|
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* xstormy16-desc.c: Regenerate.
|
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2017-04-11 00:03:50 +02:00
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2017-04-11 Alan Modra <amodra@gmail.com>
|
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2017-04-11 00:10:24 +02:00
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* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
|
2017-04-11 00:13:21 +02:00
|
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|
PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
|
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PPC_OPCODE_TMR for e6500.
|
2017-04-11 00:03:50 +02:00
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* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
|
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(PPCVEC3): Define as PPC_OPCODE_POWER9.
|
2017-04-11 00:06:43 +02:00
|
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(PPCVSX2): Define as PPC_OPCODE_POWER8.
|
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(PPCVSX3): Define as PPC_OPCODE_POWER9.
|
2017-04-11 00:10:24 +02:00
|
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(PPCHTM): Define as PPC_OPCODE_POWER8.
|
2017-04-11 00:13:21 +02:00
|
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(powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
|
2017-04-11 00:03:50 +02:00
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2017-04-10 08:05:11 +02:00
|
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|
2017-04-10 Alan Modra <amodra@gmail.com>
|
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|
|
* ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
|
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|
|
* ppc-opc.c (MULHW): Add PPC_OPCODE_476.
|
|
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|
|
(powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
|
|
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|
|
|
removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
|
|
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|
2017-04-10 02:10:28 +02:00
|
|
|
|
2017-04-09 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
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|
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|
|
* wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
|
|
|
|
|
|
appropriate floating-point precision directly.
|
|
|
|
|
|
|
Remove E6500 insns from PPC_OPCODE_ALTIVEC2
This isn't losing anything from the testsuite. All of these insns
appear in testsuite/gas/ppc/e6500.s
opcodes/
* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
vector instructions with E6500 not PPCVEC2.
gas/
* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
* testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07 10:33:46 +02:00
|
|
|
|
2017-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
|
|
|
|
|
|
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
|
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|
|
|
lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
|
|
|
|
|
|
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
|
|
|
|
|
|
vector instructions with E6500 not PPCVEC2.
|
|
|
|
|
|
|
2017-04-06 18:17:15 +02:00
|
|
|
|
2017-04-06 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add wasm32-dis.c.
|
|
|
|
|
|
* configure.ac: Add wasm32-dis.c to wasm32 target.
|
|
|
|
|
|
* disassemble.c: Add wasm32 disassembler code.
|
|
|
|
|
|
* wasm32-dis.c: New file.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2017-04-05 20:21:33 +02:00
|
|
|
|
2017-04-05 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (parse_option, parse_disassembler_options): Constify.
|
|
|
|
|
|
* arm-dis.c (parse_arm_disassembler_options): Constify.
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Constify local.
|
|
|
|
|
|
* vax-dis.c (parse_disassembler_options): Constify.
|
|
|
|
|
|
|
2017-04-03 19:08:29 +02:00
|
|
|
|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
|
|
|
|
|
|
RISCV_GP_SYMBOL.
|
|
|
|
|
|
|
2017-03-30 11:57:21 +02:00
|
|
|
|
2017-03-30 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Add (empty) bfd_wasm32_arch target.
|
|
|
|
|
|
* configure: Regenerate
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2017-03-29 21:20:23 +02:00
|
|
|
|
2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
|
|
|
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Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
|
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|
|
OSA2015.
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|
|
* opcodes/sparc-opc.c (asi_table): New ASIs.
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|
|
2017-03-29 05:13:06 +02:00
|
|
|
|
2017-03-29 Alan Modra <amodra@gmail.com>
|
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|
|
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
|
|
|
|
|
|
"raw" option.
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|
(lookup_powerpc): Don't special case -1 dialect. Handle
|
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|
PPC_OPCODE_RAW.
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|
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
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|
|
lookup_powerpc call, pass it on second.
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|
2017-03-26 23:49:48 +02:00
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|
2017-03-27 Alan Modra <amodra@gmail.com>
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|
|
PR 21303
|
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|
|
|
* ppc-dis.c (struct ppc_mopt): Comment.
|
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|
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
|
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|
|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 12:14:30 +02:00
|
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|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
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* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
|
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|
|
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
|
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|
|
F_NPS_M, F_NPS_CORE, F_NPS_ALL.
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|
(insert_nps_misc_imm_offset): New function.
|
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|
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|
(extract_nps_misc imm_offset): New function.
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|
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
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|
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
|
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2017-03-21 14:21:02 +01:00
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|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
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|
* s390-mkopc.c (main): Remove vx2 check.
|
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* s390-opc.txt: Remove vx2 instruction flags.
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|
2017-03-21 12:37:33 +01:00
|
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|
|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
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|
* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
|
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|
|
* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
|
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|
|
(insert_nps_imm_offset): New function.
|
|
|
|
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|
(extract_nps_imm_offset): New function.
|
|
|
|
|
|
(insert_nps_imm_entry): New function.
|
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|
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|
(extract_nps_imm_entry): New function.
|
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|
2017-03-17 09:36:12 +01:00
|
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|
|
2017-03-17 Alan Modra <amodra@gmail.com>
|
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|
|
PR 21248
|
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|
|
* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
|
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|
|
mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
|
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|
|
those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
|
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|
2017-03-07 11:15:02 +01:00
|
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|
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
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|
|
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
|
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|
<c.andi>: Likewise.
|
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|
<c.addiw> Likewise.
|
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|
2017-03-07 12:56:40 +01:00
|
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|
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
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|
|
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
|
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|
2017-03-13 20:46:33 +01:00
|
|
|
|
2017-03-13 Andrew Waterman <andrew@sifive.com>
|
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|
|
* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
|
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|
<srl> Likewise.
|
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|
<srai> Likewise.
|
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|
|
<sra> Likewise.
|
|
|
|
|
|
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
|
|
|
|
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
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|
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|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace S with Load.
|
|
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|
|
* i386-opc.h (S): Removed.
|
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|
|
(Load): New.
|
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|
|
|
|
(i386_opcode_modifier): Replace s with load.
|
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|
|
|
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
|
|
|
|
|
|
and {evex}. Replace S with Load.
|
|
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|
|
|
* i386-tbl.h: Regenerated.
|
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|
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|
|
2017-03-09 16:43:48 +01:00
|
|
|
|
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
* i386-opc.tbl: Use CpuCET on rdsspq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
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|
|
2017-03-09 03:49:03 +01:00
|
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|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
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|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
|
|
|
|
|
|
<vsx>: Do not use PPC_OPCODE_VSX3;
|
|
|
|
|
|
|
2017-03-08 21:00:42 +01:00
|
|
|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
|
|
|
|
|
|
|
2017-03-07 00:26:37 +01:00
|
|
|
|
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (REG_0F1E_MOD_3): New enum.
|
|
|
|
|
|
(MOD_0F1E_PREFIX_1): Likewise.
|
|
|
|
|
|
(MOD_0F38F5_PREFIX_2): Likewise.
|
|
|
|
|
|
(MOD_0F38F6_PREFIX_0): Likewise.
|
|
|
|
|
|
(RM_0F1E_MOD_3_REG_7): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_0_0F01_REG_5): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
|
|
|
|
|
|
(PREFIX_0F1E): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
|
|
|
|
|
|
(PREFIX_0F38F5): Likewise.
|
|
|
|
|
|
(dis386_twobyte): Use PREFIX_0F1E.
|
|
|
|
|
|
(reg_table): Add REG_0F1E_MOD_3.
|
|
|
|
|
|
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
|
|
|
|
|
|
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
|
|
|
|
|
|
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
|
|
|
|
|
|
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
|
|
|
|
|
|
(three_byte_table): Use PREFIX_0F38F5.
|
|
|
|
|
|
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
|
|
|
|
|
|
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
|
|
|
|
|
|
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
|
|
|
|
|
|
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
|
|
|
|
|
|
PREFIX_MOD_3_0F01_REG_5_RM_2.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuCET.
|
|
|
|
|
|
* i386-opc.h (CpuCET): New enum.
|
|
|
|
|
|
(CpuUnused): Commented out.
|
|
|
|
|
|
(i386_cpu_flags): Add cpucet.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel CET instructions.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2017-03-06 10:09:34 +01:00
|
|
|
|
2017-03-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21124
|
|
|
|
|
|
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
|
|
|
|
|
|
(extract_raq, extract_ras, extract_rbx): New functions.
|
|
|
|
|
|
(powerpc_operands): Use opposite corresponding insert function.
|
|
|
|
|
|
(Q_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
|
|
|
|
|
|
register restriction.
|
|
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c Include "safe-ctype.h".
|
|
|
|
|
|
(disassemble_init_for_target): Handle s390 init.
|
|
|
|
|
|
(remove_whitespace_and_extra_commas): New function.
|
|
|
|
|
|
(disassembler_options_cmp): Likewise.
|
|
|
|
|
|
* arm-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(NUM_ELEM): Delete.
|
|
|
|
|
|
(regnames): Use long disassembler style names.
|
|
|
|
|
|
Add force-thumb and no-force-thumb options.
|
|
|
|
|
|
(NUM_ARM_REGNAMES): Rename from this...
|
|
|
|
|
|
(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
|
|
|
|
|
|
(get_arm_regname_num_options): Delete.
|
|
|
|
|
|
(set_arm_regname_option): Likewise.
|
|
|
|
|
|
(get_arm_regnames): Likewise.
|
|
|
|
|
|
(parse_disassembler_options): Likewise.
|
|
|
|
|
|
(parse_arm_disassembler_option): Rename from this...
|
|
|
|
|
|
(parse_arm_disassembler_options): ...to this. Make static.
|
|
|
|
|
|
Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
|
|
|
|
|
|
(print_insn): Use parse_arm_disassembler_options.
|
|
|
|
|
|
(disassembler_options_arm): New function.
|
|
|
|
|
|
(print_arm_disassembler_options): Handle updated regnames.
|
|
|
|
|
|
* ppc-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(ppc_opts): Add "32" and "64" entries.
|
|
|
|
|
|
(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
|
|
|
|
|
|
(powerpc_init_dialect): Add break to switch statement.
|
|
|
|
|
|
Use new FOR_EACH_DISASSEMBLER_OPTION macro.
|
|
|
|
|
|
(disassembler_options_powerpc): New function.
|
|
|
|
|
|
(print_ppc_disassembler_options): Use ARRAY_SIZE.
|
|
|
|
|
|
Remove printing of "32" and "64".
|
|
|
|
|
|
* s390-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(init_flag): Remove unneeded variable.
|
|
|
|
|
|
(struct s390_options_t): New structure type.
|
|
|
|
|
|
(options): New structure.
|
|
|
|
|
|
(init_disasm): Rename from this...
|
|
|
|
|
|
(disassemble_init_s390): ...to this. Add initializations for
|
|
|
|
|
|
current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
|
|
|
|
|
|
(print_insn_s390): Delete call to init_disasm.
|
|
|
|
|
|
(disassembler_options_s390): New function.
|
|
|
|
|
|
(print_s390_disassembler_options): Print using information from
|
|
|
|
|
|
struct 'options'.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2017-02-28 10:53:35 +01:00
|
|
|
|
2017-02-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PCMPESTR_Fixup): New.
|
|
|
|
|
|
(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
|
|
|
|
|
|
(prefix_table): Use PCMPESTR_Fixup.
|
|
|
|
|
|
(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
|
|
|
|
|
|
PCMPESTR_Fixup.
|
|
|
|
|
|
(vex_w_table): Delete VPCMPESTR{I,M} entries.
|
|
|
|
|
|
* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
|
|
|
|
|
|
Split 64-bit and non-64-bit variants.
|
|
|
|
|
|
* opcodes/i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
|
|
|
|
|
|
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
|
|
|
|
|
|
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
|
|
|
|
|
|
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
|
|
|
|
|
|
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
|
|
|
|
|
|
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
|
|
|
|
|
|
(OP_SVE_V_HSD): New macros.
|
|
|
|
|
|
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
|
|
|
|
|
|
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
|
|
|
|
|
|
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
|
|
|
|
|
|
(aarch64_opcode_table): Add new SVE instructions.
|
|
|
|
|
|
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
|
|
|
|
|
|
for rotation operands. Add new SVE operands.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
|
|
|
|
|
|
(ins_sve_quad_index): Likewise.
|
|
|
|
|
|
(ins_imm_rotate): Split into...
|
|
|
|
|
|
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
|
|
|
|
|
|
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
|
|
|
|
|
|
functions.
|
|
|
|
|
|
(aarch64_ins_sve_addr_ri_s4): New function.
|
|
|
|
|
|
(aarch64_ins_sve_quad_index): Likewise.
|
|
|
|
|
|
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
|
|
|
|
|
|
(ext_sve_quad_index): Likewise.
|
|
|
|
|
|
(ext_imm_rotate): Split into...
|
|
|
|
|
|
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
|
|
|
|
|
|
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
|
|
|
|
|
|
functions.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_s4): New function.
|
|
|
|
|
|
(aarch64_ext_sve_quad_index): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_index): Allow quad indices.
|
|
|
|
|
|
(do_misc_decoding): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
|
|
|
|
|
|
aarch64_field_kinds.
|
|
|
|
|
|
(OPD_F_OD_MASK): Widen by one bit.
|
|
|
|
|
|
(OPD_F_NO_ZR): Bump accordingly.
|
|
|
|
|
|
(get_operand_field_width): New function.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add new SVE fields.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle new SVE operands.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2017-02-24 19:27:26 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
|
|
|
|
|
|
(aarch64_feature_compnum): ...this.
|
|
|
|
|
|
(SIMD_V8_3): Replace with...
|
|
|
|
|
|
(COMPNUM): ...this.
|
|
|
|
|
|
(CNUM_INSN): New macro.
|
|
|
|
|
|
(aarch64_opcode_table): Use it for the complex number instructions.
|
|
|
|
|
|
|
2017-02-24 10:04:26 +01:00
|
|
|
|
2017-02-24 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
|
|
|
|
|
|
|
2017-02-23 16:49:37 +01:00
|
|
|
|
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
Add support for associating SPARC ASIs with an architecture level.
|
|
|
|
|
|
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
|
|
|
|
|
|
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
|
|
|
|
|
|
decoding of SPARC ASIs.
|
|
|
|
|
|
|
2017-02-23 11:03:55 +01:00
|
|
|
|
2017-02-23 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
|
|
|
|
|
|
82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
|
|
|
|
|
|
|
2017-02-22 10:36:05 +01:00
|
|
|
|
2017-02-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
|
|
|
|
|
|
1 (instead of to itself). Correct typo.
|
|
|
|
|
|
|
2017-02-15 00:37:04 +01:00
|
|
|
|
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
|
|
|
|
|
|
pseudoinstructions.
|
|
|
|
|
|
|
2017-02-15 17:54:21 +01:00
|
|
|
|
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
|
|
|
|
|
|
(aarch64_sys_reg_supported_p): Handle them.
|
|
|
|
|
|
|
2017-02-15 11:57:51 +01:00
|
|
|
|
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (UIMM6_20R): Define.
|
|
|
|
|
|
(SIMM12_20): Use above.
|
|
|
|
|
|
(SIMM12_20R): Define.
|
|
|
|
|
|
(SIMM3_5_S): Use above.
|
|
|
|
|
|
(UIMM7_A32_11R_S): Define.
|
|
|
|
|
|
(UIMM7_9_S): Use above.
|
|
|
|
|
|
(UIMM3_13R_S): Define.
|
|
|
|
|
|
(SIMM11_A32_7_S): Use above.
|
|
|
|
|
|
(SIMM9_8R): Define.
|
|
|
|
|
|
(UIMM10_A32_8_S): Use above.
|
|
|
|
|
|
(UIMM8_8R_S): Define.
|
|
|
|
|
|
(W6): Use above.
|
|
|
|
|
|
(arc_relax_opcodes): Use all above defines.
|
|
|
|
|
|
|
2017-02-15 09:52:53 +01:00
|
|
|
|
2017-02-15 Vineet Gupta <vgupta@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h: Distinguish some of the registers different on
|
|
|
|
|
|
ARC700 and HS38 cpus.
|
|
|
|
|
|
|
2017-02-14 11:08:21 +01:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
|
|
|
|
|
|
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
|
|
|
|
|
|
|
2017-02-11 07:47:59 +01:00
|
|
|
|
2017-02-11 Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
|
|
|
|
|
|
Use insn_bytes_value and insn_int_value directly instead. Don't
|
|
|
|
|
|
free allocated memory until function exit.
|
|
|
|
|
|
|
2017-02-10 05:18:23 +01:00
|
|
|
|
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
|
|
|
|
|
|
|
2017-02-03 10:04:21 +01:00
|
|
|
|
2017-02-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21096
|
|
|
|
|
|
* aarch64-opc.c (print_register_list): Ensure that the register
|
|
|
|
|
|
list index will fir into the tb buffer.
|
|
|
|
|
|
(print_register_offset_address): Likewise.
|
|
|
|
|
|
* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
|
|
|
|
|
|
|
2017-01-27 13:00:55 +01:00
|
|
|
|
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21056
|
|
|
|
|
|
* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
|
|
|
|
|
|
instructions when the previous fetch packet ends with a 32-bit
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
|
2017-01-25 13:19:27 +01:00
|
|
|
|
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
|
|
|
|
|
|
|
|
|
|
|
* pru-opc.c: Remove vague reference to a future GDB port.
|
|
|
|
|
|
|
2017-01-20 13:25:07 +01:00
|
|
|
|
2017-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/ga.po: Updated Irish translation.
|
|
|
|
|
|
|
2017-01-18 18:08:34 +01:00
|
|
|
|
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
|
|
|
|
|
|
|
2017-01-13 13:27:39 +01:00
|
|
|
|
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
|
|
|
|
|
|
if FETCH_DATA returns 0.
|
|
|
|
|
|
(m68k_scan_mask): Likewise.
|
|
|
|
|
|
(print_insn_m68k): Update code to handle -1 return value.
|
|
|
|
|
|
|
2017-01-13 13:21:22 +01:00
|
|
|
|
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c (enum print_insn_arg_error): New.
|
|
|
|
|
|
(NEXTBYTE): Replace -3 with
|
|
|
|
|
|
PRINT_INSN_ARG_MEMORY_ERROR.
|
|
|
|
|
|
(NEXTULONG): Likewise.
|
|
|
|
|
|
(NEXTSINGLE): Likewise.
|
|
|
|
|
|
(NEXTDOUBLE): Likewise.
|
|
|
|
|
|
(NEXTDOUBLE): Likewise.
|
|
|
|
|
|
(NEXTPACKED): Likewise.
|
|
|
|
|
|
(FETCH_ARG): Likewise.
|
|
|
|
|
|
(FETCH_DATA): Update comments.
|
|
|
|
|
|
(print_insn_arg): Update comments. Replace magic numbers with
|
|
|
|
|
|
enum.
|
|
|
|
|
|
(match_insn_m68k): Likewise.
|
|
|
|
|
|
|
2017-01-12 17:42:17 +01:00
|
|
|
|
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Updated.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
|
|
|
|
|
|
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Ditto.
|
|
|
|
|
|
|
2017-01-12 10:40:41 +01:00
|
|
|
|
2017-01-12 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430-dis.c (msp430_singleoperand): Return -1 if
|
|
|
|
|
|
msp430dis_opcode_signed returns false.
|
|
|
|
|
|
(msp430_doubleoperand): Likewise.
|
|
|
|
|
|
(msp430_branchinstr): Return -1 if
|
|
|
|
|
|
msp430dis_opcode_unsigned returns false.
|
|
|
|
|
|
(msp430x_calla_instr): Likewise.
|
|
|
|
|
|
(print_insn_msp430): Likewise.
|
|
|
|
|
|
|
2017-01-05 10:11:47 +01:00
|
|
|
|
2017-01-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 20946
|
|
|
|
|
|
* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
|
|
|
|
|
|
could not be matched.
|
|
|
|
|
|
(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
|
|
|
|
|
|
NULL.
|
|
|
|
|
|
|
2017-01-04 13:27:10 +01:00
|
|
|
|
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
|
|
|
|
|
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(aarch64_opcode_table): Use RCPC_INSN.
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2017-01-03 18:42:01 +01:00
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
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extension.
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* riscv-opcodes/all-opcodes: Likewise.
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2017-01-03 17:02:36 +01:00
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2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
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* riscv-dis.c (print_insn_args): Add fall through comment.
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2017-01-03 16:51:11 +01:00
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2017-01-03 Nick Clifton <nickc@redhat.com>
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* po/sr.po: New Serbian translation.
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* configure.ac (ALL_LINGUAS): Add sr.
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* configure: Regenerate.
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2017-01-02 14:27:58 +01:00
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2017-01-02 Alan Modra <amodra@gmail.com>
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* epiphany-desc.h: Regenerate.
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* epiphany-opc.h: Regenerate.
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* fr30-desc.h: Regenerate.
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* fr30-opc.h: Regenerate.
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|
* frv-desc.h: Regenerate.
|
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|
* frv-opc.h: Regenerate.
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* ip2k-desc.h: Regenerate.
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|
* ip2k-opc.h: Regenerate.
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|
* iq2000-desc.h: Regenerate.
|
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* iq2000-opc.h: Regenerate.
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|
* lm32-desc.h: Regenerate.
|
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|
* lm32-opc.h: Regenerate.
|
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|
* m32c-desc.h: Regenerate.
|
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|
|
* m32c-opc.h: Regenerate.
|
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|
* m32r-desc.h: Regenerate.
|
|
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|
|
* m32r-opc.h: Regenerate.
|
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|
|
* mep-desc.h: Regenerate.
|
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|
|
* mep-opc.h: Regenerate.
|
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|
|
* mt-desc.h: Regenerate.
|
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|
|
* mt-opc.h: Regenerate.
|
|
|
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|
|
* or1k-desc.h: Regenerate.
|
|
|
|
|
|
* or1k-opc.h: Regenerate.
|
|
|
|
|
|
* xc16x-desc.h: Regenerate.
|
|
|
|
|
|
* xc16x-opc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-desc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-opc.h: Regenerate.
|
|
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|
|
2017-01-02 04:36:43 +01:00
|
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|
|
2017-01-02 Alan Modra <amodra@gmail.com>
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|
|
Update year range in copyright notice of all files.
|
|
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|
|
2017-01-02 04:25:05 +01:00
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|
|
For older changes see ChangeLog-2016
|
2016-01-01 11:44:31 +01:00
|
|
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|
2017-01-02 04:25:05 +01:00
|
|
|
|
Copyright (C) 2017 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
|
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|
|
Copying and distribution of this file, with or without modification,
|
|
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|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
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|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
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|
|
fill-column: 74
|
|
|
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|
|
version-control: never
|
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End:
|
