Use operand->extract to provide defaults for optional PowerPC operands
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
2018-08-16 08:44:12 +02:00
|
|
|
|
2018-08-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (operand_value_powerpc): Init "invalid".
|
|
|
|
|
|
(skip_optional_operands): Count optional operands, and update
|
|
|
|
|
|
ppc_optional_operand_value call.
|
|
|
|
|
|
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
|
|
|
|
|
|
(extract_vlensi): Likewise.
|
|
|
|
|
|
(extract_fxm): Return default value for missing optional operand.
|
|
|
|
|
|
(extract_ls, extract_raq, extract_tbr): Likewise.
|
|
|
|
|
|
(insert_sxl, extract_sxl): New functions.
|
|
|
|
|
|
(insert_esync, extract_esync): Remove Power9 handling and simplify.
|
|
|
|
|
|
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
|
|
|
|
|
|
flag and extra entry.
|
|
|
|
|
|
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
|
|
|
|
|
|
extract_sxl.
|
|
|
|
|
|
|
2018-08-20 01:52:28 +02:00
|
|
|
|
2018-08-20 Alan Modra <amodra@gmail.com>
|
2018-07-24 13:40:21 +02:00
|
|
|
|
|
2018-08-20 01:52:28 +02:00
|
|
|
|
* sh-opc.h (MASK): Simplify.
|
2018-07-24 13:40:21 +02:00
|
|
|
|
|
2018-08-20 10:46:34 +02:00
|
|
|
|
2018-08-18 John Darrington <john@darrington.wattle.id.au>
|
2018-07-11 10:42:01 +02:00
|
|
|
|
|
2018-08-20 01:52:28 +02:00
|
|
|
|
* s12z-dis.c (bm_decode): Deal with cases where the mode is
|
|
|
|
|
|
BM_RESERVED0 or BM_RESERVED1
|
2018-08-20 10:46:34 +02:00
|
|
|
|
(bm_rel_decode, bm_n_bytes): Ditto.
|
2018-08-20 01:52:28 +02:00
|
|
|
|
|
2018-08-20 10:46:34 +02:00
|
|
|
|
2018-08-18 John Darrington <john@darrington.wattle.id.au>
|
2018-08-20 01:52:28 +02:00
|
|
|
|
|
|
|
|
|
|
* s12z.h: Delete.
|
2018-07-11 10:42:01 +02:00
|
|
|
|
|
2018-08-14 18:55:43 +02:00
|
|
|
|
2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
|
|
|
|
|
|
address with the addr32 prefix and without base nor index
|
|
|
|
|
|
registers.
|
|
|
|
|
|
|
2018-08-11 23:37:14 +02:00
|
|
|
|
2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
|
|
|
|
|
|
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
|
|
|
|
|
|
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuCMOV and CpuFXSR.
|
|
|
|
|
|
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
|
|
|
|
|
|
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-08-06 15:41:32 +02:00
|
|
|
|
2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h: Update auxiliary registers.
|
|
|
|
|
|
|
2018-08-06 08:34:36 +02:00
|
|
|
|
2018-08-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
|
|
|
|
|
|
(RegIP, RegIZ): Define.
|
|
|
|
|
|
* i386-reg.tbl: Adjust comments.
|
|
|
|
|
|
(rip): Use Qword instead of BaseIndex. Use RegIP.
|
|
|
|
|
|
(eip): Use Dword instead of BaseIndex. Use RegIP.
|
|
|
|
|
|
(riz): Add Qword. Use RegIZ.
|
|
|
|
|
|
(eiz): Add Dword. Use RegIZ.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-03 09:30:58 +02:00
|
|
|
|
2018-08-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
|
|
|
|
|
|
pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
|
|
|
|
|
|
vpmovzxdq, vpmovzxwd): Remove NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-03 09:30:02 +02:00
|
|
|
|
2018-08-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_types): Remove Mem field.
|
|
|
|
|
|
* i386-opc.h (union i386_operand_type): Remove mem field.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-01 03:02:56 +02:00
|
|
|
|
2018-08-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-07-31 18:49:53 +02:00
|
|
|
|
2018-07-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2018-07-31 10:58:05 +02:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-31 10:57:09 +02:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (ZEROING_MASKING) Rename to ...
|
|
|
|
|
|
(DYNAMIC_MASKING): ... this. Adjust comment.
|
|
|
|
|
|
* i386-opc.tbl (MaskingMorZ): Define.
|
|
|
|
|
|
(vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
|
|
|
|
|
|
vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
|
|
|
|
|
|
vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
|
|
|
|
|
|
vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
|
|
|
|
|
|
vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
|
|
|
|
|
|
vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
|
|
|
|
|
|
vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
|
|
|
|
|
|
vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
|
|
|
|
|
|
|
2018-07-31 10:55:17 +02:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Use element rather than vector size for AVX512*
|
|
|
|
|
|
scatter/gather insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-31 10:52:37 +02:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
|
|
|
|
|
|
(cpu_flags): Drop CpuVREX.
|
|
|
|
|
|
* i386-opc.h (CpuVREX): Delete.
|
|
|
|
|
|
(union i386_cpu_flags): Remove cpuvrex.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-30 22:55:41 +02:00
|
|
|
|
2018-07-30 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
|
|
|
|
|
|
fields.
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
|
|
|
|
|
|
|
Add support for the C_SKY series of processors.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
2018-07-30 13:24:14 +02:00
|
|
|
|
2018-07-30 Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.ac: Add C-SKY.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* csky-dis.c: New file.
|
|
|
|
|
|
* csky-opc.h: New file.
|
|
|
|
|
|
* disassemble.c (ARCH_csky): Define.
|
|
|
|
|
|
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
|
|
|
|
|
|
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
|
|
|
|
|
|
|
2018-07-27 00:49:45 +02:00
|
|
|
|
2018-07-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_sprbat): Correct function parameter and
|
|
|
|
|
|
return type.
|
|
|
|
|
|
(extract_sprbat): Likewise, variable too.
|
|
|
|
|
|
|
2018-07-24 01:51:44 +02:00
|
|
|
|
2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
|
|
|
|
|
|
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
|
|
|
|
|
|
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
|
|
|
|
|
|
support disjointed BAT.
|
|
|
|
|
|
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
|
|
|
|
|
|
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
|
|
|
|
|
|
|
2018-07-26 00:28:07 +02:00
|
|
|
|
2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (adjust_broadcast_modifier): New function.
|
|
|
|
|
|
(process_i386_opcode_modifier): Add an argument for operands.
|
|
|
|
|
|
Adjust the Broadcast value based on operands.
|
|
|
|
|
|
(output_i386_opcode): Pass operand_types to
|
|
|
|
|
|
process_i386_opcode_modifier.
|
|
|
|
|
|
(process_i386_opcodes): Pass NULL as operands to
|
|
|
|
|
|
process_i386_opcode_modifier.
|
|
|
|
|
|
* i386-opc.h (BYTE_BROADCAST): New.
|
|
|
|
|
|
(WORD_BROADCAST): Likewise.
|
|
|
|
|
|
(DWORD_BROADCAST): Likewise.
|
|
|
|
|
|
(QWORD_BROADCAST): Likewise.
|
|
|
|
|
|
(i386_opcode_modifier): Expand broadcast to 3 bits.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-07-24 09:05:52 +02:00
|
|
|
|
2018-07-24 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 23430
|
|
|
|
|
|
* or1k-desc.h: Regenerate.
|
|
|
|
|
|
|
2018-07-24 09:46:27 +02:00
|
|
|
|
2018-07-24 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
|
|
|
|
|
|
vcvtusi2ss, and vcvtusi2sd.
|
|
|
|
|
|
* i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
|
|
|
|
|
|
Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-23 11:09:43 +02:00
|
|
|
|
2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (extract_w6): Fix extending the sign.
|
|
|
|
|
|
|
2018-07-23 11:09:43 +02:00
|
|
|
|
2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h (vewt): Allow it for ARC EM family.
|
|
|
|
|
|
|
2018-07-23 05:29:23 +02:00
|
|
|
|
2018-07-23 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 23419
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
|
|
|
|
|
|
opcode variants for mtspr/mfspr encodings.
|
|
|
|
|
|
|
2018-07-20 14:21:33 +02:00
|
|
|
|
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
|
|
|
|
|
|
loongson3a descriptors.
|
|
|
|
|
|
(parse_mips_ase_option): Handle -M loongson-mmi option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -M loongson-mmi.
|
|
|
|
|
|
* mips-opc.c (LMMI): New macro.
|
|
|
|
|
|
(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2018-07-19 08:36:19 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
|
|
|
|
|
|
vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
|
|
|
|
|
|
IgnoreSize and [XYZ]MMword where applicable.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:35:38 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
|
|
|
|
|
|
(vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
|
|
|
|
|
|
(vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
|
|
|
|
|
|
(vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:34:45 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
|
|
|
|
|
|
AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
|
|
|
|
|
|
VPCLMULQDQ templates into their respective AVX512VL counterparts
|
|
|
|
|
|
where possible, using Disp8ShiftVL and CheckRegSize instead of
|
|
|
|
|
|
Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:34:01 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512DQ templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:32:17 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512BW templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:31:24 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512CD templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:29:35 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (DISP8_SHIFT_VL): New.
|
|
|
|
|
|
* i386-opc.tbl (Disp8ShiftVL): Define.
|
|
|
|
|
|
(various): Fold AVX512VL templates into their respective
|
|
|
|
|
|
AVX512F counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 08:28:29 +02:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Change dependencies and rule for
|
|
|
|
|
|
$(srcdir)/i386-init.h.
|
|
|
|
|
|
* Makefile.in: Re-generate.
|
|
|
|
|
|
* i386-gen.c (process_i386_opcodes): New local variable
|
|
|
|
|
|
"marker". Drop opening of input file. Recognize marker and line
|
|
|
|
|
|
number directives.
|
|
|
|
|
|
* i386-opc.tbl (OPCODE_I386_H): Define.
|
|
|
|
|
|
(i386-opc.h): Include it.
|
|
|
|
|
|
(None): Undefine.
|
|
|
|
|
|
|
x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
After
commit 1b54b8d7e4fc8055f9220a5287e8a94d8a65a88d
Author: Jan Beulich <jbeulich@novell.com>
Date: Mon Dec 18 09:36:14 2017 +0100
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these
RegXMM|...|Xmmword|...
and
RegXMM|...
The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.
gas/
PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.
opcodes/
PR gas/23418
* i386-opc.h (Byte): Update comments.
(Word): Likewise.
(Dword): Likewise.
(Fword): Likewise.
(Qword): Likewise.
(Tbyte): Likewise.
(Xmmword): Likewise.
(Ymmword): Likewise.
(Zmmword): Likewise.
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
vcvttps2uqq.
* i386-tbl.h: Regenerated.
2018-07-18 14:33:36 +02:00
|
|
|
|
2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/23418
|
|
|
|
|
|
* i386-opc.h (Byte): Update comments.
|
|
|
|
|
|
(Word): Likewise.
|
|
|
|
|
|
(Dword): Likewise.
|
|
|
|
|
|
(Fword): Likewise.
|
|
|
|
|
|
(Qword): Likewise.
|
|
|
|
|
|
(Tbyte): Likewise.
|
|
|
|
|
|
(Xmmword): Likewise.
|
|
|
|
|
|
(Ymmword): Likewise.
|
|
|
|
|
|
(Zmmword): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
|
|
|
|
|
|
vcvttps2uqq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-07-12 16:46:17 +02:00
|
|
|
|
2018-07-12 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add entry for
|
|
|
|
|
|
ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
Add remainder of Em16 restrictions for AArch64 gas.
This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.
The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.
The list has been cross checked (by hand) through the Arm ARM version Ca.
opcodes/
PR binutils/23192
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
sqdmulh, sqrdmulh): Use Em16.
gas/
PR binutils/23192
* testsuite/gas/aarch64/illegal-by-element.s: New.
* testsuite/gas/aarch64/illegal-by-element.d: New.
* testsuite/gas/aarch64/illegal-by-element.l: New.
2018-07-12 11:28:46 +02:00
|
|
|
|
2018-07-12 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23192
|
|
|
|
|
|
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
|
|
|
|
|
|
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
|
|
|
|
|
|
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
|
|
|
|
|
|
sqdmulh, sqrdmulh): Use Em16.
|
|
|
|
|
|
|
2018-07-11 19:05:34 +02:00
|
|
|
|
2018-07-11 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
|
|
|
|
|
|
csdb together with them.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2018-07-11 10:30:00 +02:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (monitor, monitorx): Add 64-bit template
|
|
|
|
|
|
requiring 32-bit registers as operands 2 and 3. Improve
|
|
|
|
|
|
comments.
|
|
|
|
|
|
(mwait, mwaitx): Fold templates. Improve comments.
|
|
|
|
|
|
OPERAND_TYPE_INOUTPORTREG.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-11 10:28:56 +02:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Remove
|
|
|
|
|
|
OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
|
|
|
|
|
|
OPERAND_TYPE_INOUTPORTREG.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-07-11 10:25:40 +02:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (wrssd, wrussd): Add Dword.
|
|
|
|
|
|
(wrssq, wrussq): Add Qword.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-11 10:24:44 +02:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h: Rename OTMax to OTNum.
|
|
|
|
|
|
(OTNumOfUints): Adjust calculation.
|
|
|
|
|
|
(OTUnused): Directly alias to OTNum.
|
|
|
|
|
|
|
2018-07-09 16:50:57 +02:00
|
|
|
|
2018-07-09 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
|
|
|
|
|
|
`reg_xys'.
|
|
|
|
|
|
(lea_reg_xys): Likewise.
|
|
|
|
|
|
(print_insn_loop_primitive): Rename `reg' local variable to
|
|
|
|
|
|
`reg_dxy'.
|
|
|
|
|
|
|
2018-07-06 17:18:19 +02:00
|
|
|
|
2018-07-06 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23242
|
|
|
|
|
|
* aarch64-tbl.h (ldarh): Fix disassembly mask.
|
|
|
|
|
|
|
2018-07-06 17:15:41 +02:00
|
|
|
|
2018-07-06 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23369
|
|
|
|
|
|
* aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
|
|
|
|
|
|
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
|
|
|
|
|
|
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
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2018-07-02 Maciej W. Rozycki <macro@mips.com>
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PR tdep/8282
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* mips-dis.c (mips_option_arg_t): New enumeration.
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(mips_options): New variable.
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(disassembler_options_mips): New function.
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(print_mips_disassembler_options): Reimplement in terms of
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`disassembler_options_mips'.
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* arm-dis.c (disassembler_options_arm): Adapt to using the
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`disasm_options_and_args_t' structure.
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* ppc-dis.c (disassembler_options_powerpc): Likewise.
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* s390-dis.c (disassembler_options_s390): Likewise.
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[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
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2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
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expected result.
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* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
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* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
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* testsuite/ld-arm/tls-longplt.d: Likewise.
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Fix AArch64 encodings for by element instructions.
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.
e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.
Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.
This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
Also the patch updates all instructions that should be affected by this.
opcodes/
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
gas/
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
include/
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-29 13:12:27 +02:00
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2018-06-29 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23192
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
|
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* aarch64-opc.c (operand_general_constraint_met_p,
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aarch64_print_operand): Likewise.
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* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
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smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
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fmlal2, fmlsl2.
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(AARCH64_OPERANDS): Add Em2.
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2018-06-26 15:03:16 +02:00
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2018-06-26 Nick Clifton <nickc@redhat.com>
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* po/uk.po: Updated Ukranian translation.
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* po/de.po: Updated German translation.
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* po/pt_BR.po: Updated Brazilian Portuguese translation.
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2018-06-26 13:56:23 +02:00
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2018-06-26 Nick Clifton <nickc@redhat.com>
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* nfp-dis.c: Fix spelling mistake.
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2018-06-24 20:13:01 +02:00
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2018-06-24 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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* po/opcodes.pot: Regenerate.
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2018-06-24 19:36:15 +02:00
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2018-06-24 Nick Clifton <nickc@redhat.com>
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2.31 branch created.
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2018-06-22 13:27:53 +02:00
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2018-06-19 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Likewise.
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2018-06-21 23:45:47 +02:00
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2018-06-21 Maciej W. Rozycki <macro@mips.com>
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* mips-dis.c (print_mips_disassembler_options): Fix a typo in
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`-M ginv' option description.
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2018-06-19 07:12:48 +02:00
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2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
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PR gas/23305
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* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
|
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la and lla.
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Bump to autoconf 2.69 and automake 1.15.1
When trying to run the update-gnulib.sh script in gdb, I get this:
Error: Wrong automake version (Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\${ <-- HERE ([^ =:+{}]+)}/ at /opt/automake/1.11.1/bin/automake line 4113.), we need 1.11.1.
Aborting.
Apparently, it's an issue with a regex in automake that triggers a
warning starting with Perl 5.22. It has been fixed in automake 1.15.1.
So I think it's a good excuse to bump the versions of autoconf and
automake used in the gnulib import. And to avoid requiring multiple
builds of autoconf/automake, it was suggested that we bump the required
version of those tools for all binutils-gdb.
For autoconf, the 2.69 version is universally available, so it's an easy
choice. For automake, different distros and distro versions have
different automake versions. But 1.15.1 seems to be the most readily
available as a package. In any case, it's easy to build it from source.
I removed the version checks from AUTOMAKE_OPTIONS and AC_PREREQ,
because I don't think they are useful in our case. They only specify a
lower bound for the acceptable version of automake/autoconf. That's
useful if you let the user choose the version of the tool they want to
use, but want to set a minimum version (because you use a feature that
was introduced in that version). In our case, we force people to use a
specific version anyway. For the autoconf version, we have the check in
config/override.m4 that enforces the version we want. It will be one
less thing to update next time we change autotools version.
I hit a few categories of problems that required some changes. They are
described below along with the chosen solutions.
Problem 1:
configure.ac:17: warning: AM_INIT_AUTOMAKE: two- and three-arguments forms are deprecated. For more info, see:
configure.ac:17: http://www.gnu.org/software/automake/manual/automake.html#Modernize-AM_005fINIT_005fAUTOMAKE-invocation
Solution 1:
Adjust the code based on the example at that URL.
Problem 2 (in zlib/):
Makefile.am: error: required file './INSTALL' not found
Makefile.am: 'automake --add-missing' can install 'INSTALL'
Makefile.am: error: required file './NEWS' not found
Makefile.am: error: required file './AUTHORS' not found
Makefile.am: error: required file './COPYING' not found
Makefile.am: 'automake --add-missing' can install 'COPYING'
Solution 2:
Add the foreign option to AUTOMAKE_OPTIONS.
Problem 3:
doc/Makefile.am:20: error: support for Cygnus-style trees has been removed
Solution 3:
Remove the cygnus options.
Problem 4:
Makefile.am:656: warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Solution 4:
Rename "INCLUDES = " to "AM_CPPFLAGS += " (because AM_CPPFLAGS is
already defined earlier).
Problem 5:
doc/Makefile.am:71: warning: suffix '.texinfo' for Texinfo files is discouraged; use '.texi' instead
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 5:
Rename .texinfo files to .texi.
Problem 6:
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 6:
Remove the hack at the bottom of doc/Makefile.am and use
the info-in-builddir automake option.
Problem 7:
doc/Makefile.am:35: error: required file '../texinfo.tex' not found
doc/Makefile.am:35: 'automake --add-missing' can install 'texinfo.tex'
Solution 7:
Use the no-texinfo.tex automake option. We also have one in
texinfo/texinfo.tex, not sure if we should point to that, or move it
(or a newer version of it added with automake --add-missing) to
top-level.
Problem 8:
Makefile.am:131: warning: source file 'config/tc-aarch64.c' is in a subdirectory,
Makefile.am:131: but option 'subdir-objects' is disabled
automake: warning: possible forward-incompatibility.
automake: At least a source file is in a subdirectory, but the 'subdir-objects'
automake: automake option hasn't been enabled. For now, the corresponding output
automake: object file(s) will be placed in the top-level directory. However,
automake: this behaviour will change in future Automake versions: they will
automake: unconditionally cause object files to be placed in the same subdirectory
automake: of the corresponding sources.
automake: You are advised to start using 'subdir-objects' option throughout your
automake: project, to avoid future incompatibilities.
Solution 8:
Use subdir-objects, that means adjusting references to some .o that will now
be in config/.
Problem 9:
configure.ac:375: warning: AC_LANG_CONFTEST: no AC_LANG_SOURCE call detected in body
../../lib/autoconf/lang.m4:193: AC_LANG_CONFTEST is expanded from...
../../lib/autoconf/general.m4:2601: _AC_COMPILE_IFELSE is expanded from...
../../lib/autoconf/general.m4:2617: AC_COMPILE_IFELSE is expanded from...
../../lib/m4sugar/m4sh.m4:639: AS_IF is expanded from...
../../lib/autoconf/general.m4:2042: AC_CACHE_VAL is expanded from...
../../lib/autoconf/general.m4:2063: AC_CACHE_CHECK is expanded from...
configure.ac:375: the top level
Solution 9:
Use AC_LANG_SOURCE, or use proper quoting.
Problem 10 (in intl/):
configure.ac:7: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS
/usr/share/aclocal/threadlib.m4:36: gl_THREADLIB_EARLY_BODY is expanded from...
/usr/share/aclocal/threadlib.m4:29: gl_THREADLIB_EARLY is expanded from...
/usr/share/aclocal/threadlib.m4:318: gl_THREADLIB is expanded from...
/usr/share/aclocal/lock.m4:9: gl_LOCK is expanded from...
/usr/share/aclocal/intl.m4:211: gt_INTL_SUBDIR_CORE is expanded from...
/usr/share/aclocal/intl.m4:25: AM_INTL_SUBDIR is expanded from...
/usr/share/aclocal/gettext.m4:57: AM_GNU_GETTEXT is expanded from...
configure.ac:7: the top level
Solution 10:
Add AC_USE_SYSTEM_EXTENSIONS in configure.ac.
ChangeLog:
* libtool.m4: Use AC_LANG_SOURCE.
* configure.ac: Remove AC_PREREQ, use AC_LANG_SOURCE.
* README-maintainer-mode: Update version requirements.
* ar-lib: New file.
* test-driver: New file.
* configure: Re-generate.
bfd/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
(INCLUDES): Rename to ...
(AM_CPPFLAGS): ... this.
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9, cygnus, add
info-in-builddir no-texinfo.tex.
(info_TEXINFOS): Rename bfd.texinfo to bfd.texi.
* doc/bfd.texinfo: Rename to ...
* doc/bfd.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove cygnus, add
info-in-builddir no-texinfo.tex.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
config/ChangeLog:
* override.m4 (_GCC_AUTOCONF_VERSION): Bump from 2.64 to 2.69.
etc/ChangeLog:
* configure.in: Remove AC_PREREQ.
* configure: Re-generate.
gas/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
(TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix.
* configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles,
extra_objects): Add config/ prefix.
* doc/as.texinfo: Rename to...
* doc/as.texi: ... this.
* doc/Makefile.am: Rename as.texinfo to as.texi throughout.
Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and
info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gdb/ChangeLog:
* common/common-defs.h (PACKAGE_NAME, PACKAGE_VERSION,
PACKAGE_STRING, PACKAGE_TARNAME): Undefine.
* configure.ac: Remove AC_PREREQ, add missing quoting.
* gnulib/configure.ac: Modernize usage of
AC_INIT/AM_INIT_AUTOMAKE. Remove AC_PREREQ.
* gnulib/update-gnulib.sh (AUTOCONF_VERSION): Bump to 2.69.
(AUTOMAKE_VERSION): Bump to 1.15.1.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
* gnulib/aclocal.m4: Re-generate.
* gnulib/config.in: Re-generate.
* gnulib/configure: Re-generate.
* gnulib/import/Makefile.in: Re-generate.
gdb/gdbserver/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
gdb/testsuite/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
gold/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting and usage
of AC_LANG_SOURCE.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.11, add info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* gconfig.in: Re-generate.
intl/ChangeLog:
* configure.ac: Add AC_USE_SYSTEM_EXTENSIONS, remove AC_PREREQ.
* configure: Re-generate.
* config.h.in: Re-generate.
* aclocal.m4: Re-generate.
ld/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack, rename ld.texinfo to
ld.texi, ldint.texinfo to ldint.texi throughout.
(AUTOMAKE_OPTIONS): Add info-in-builddir.
* README: Rename ld.texinfo to ld.texi, ldint.texinfo to
ldint.texi throughout.
* gen-doc.texi: Likewise.
* h8-doc.texi: Likewise.
* ld.texinfo: Rename to ...
* ld.texi: ... this.
* ldint.texinfo: Rename to ...
* ldint.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
libdecnumber/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* aclocal.m4.
libiberty/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* config.in: Re-generate.
opcodes/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
* configure.ac: Remove AC_PREREQ.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
readline/ChangeLog.gdb:
* configure: Re-generate.
* examples/rlfe/configure: Re-generate.
sim/ChangeLog:
* All configure.ac: Remove AC_PREREQ.
* All configure: Re-generate.
zlib/ChangeLog.bin-gdb:
* configure.ac: Modernize AC_INIT call, remove AC_PREREQ.
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add
foreign.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
2018-06-19 22:54:48 +02:00
|
|
|
|
2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
|
|
|
|
|
|
* configure.ac: Remove AC_PREREQ.
|
|
|
|
|
|
* Makefile.in: Re-generate.
|
|
|
|
|
|
* aclocal.m4: Re-generate.
|
|
|
|
|
|
* configure: Re-generate.
|
|
|
|
|
|
|
MIPS: Add Global INValidate ASE support
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
2018-06-14 22:34:49 +02:00
|
|
|
|
2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
|
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|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
|
|
|
|
|
|
mips64r6 descriptors.
|
|
|
|
|
|
(parse_mips_ase_option): Handle -Mginv option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -Mginv.
|
|
|
|
|
|
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
|
|
|
|
|
|
(GINV): New macro.
|
|
|
|
|
|
(mips_opcodes): Define ginvi and ginvt.
|
|
|
|
|
|
|
MIPS: Add CRC ASE support
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
2018-06-13 16:39:05 +02:00
|
|
|
|
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
|
|
|
|
|
|
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
|
|
|
|
|
|
* mips-opc.c (CRC, CRC64): New macros.
|
|
|
|
|
|
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
|
|
|
|
|
|
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
|
|
|
|
|
|
crc32cd for CRC64.
|
|
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|
|
|
|
2018-06-08 15:02:52 +02:00
|
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|
|
2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
|
|
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|
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|
|
|
|
PR 20319
|
|
|
|
|
|
* aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
|
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|
|
(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
|
|
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|
|
2018-06-06 08:00:35 +02:00
|
|
|
|
2018-06-06 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
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|
|
* xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
|
|
|
|
|
|
setjmp. Move init for some other vars later too.
|
|
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|
|
2018-05-24 20:22:14 +02:00
|
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|
|
2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
|
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|
|
|
|
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|
|
* xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
|
|
|
|
|
|
(dis_private): Add new fields for property section tracking.
|
|
|
|
|
|
(xtensa_coalesce_insn_tables, xtensa_find_table_entry)
|
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|
|
|
|
(xtensa_instruction_fits): New functions.
|
|
|
|
|
|
(fetch_data): Bump minimal fetch size to 4.
|
|
|
|
|
|
(print_insn_xtensa): Make struct dis_private static.
|
|
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|
|
Load and prepare property table on section change.
|
|
|
|
|
|
Don't disassemble literals. Don't disassemble instructions that
|
|
|
|
|
|
cross property table boundaries.
|
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|
|
|
|
2018-06-01 18:34:04 +02:00
|
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|
|
2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
|
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|
* configure: Regenerated.
|
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|
2018-06-01 08:41:16 +02:00
|
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|
|
2018-06-01 Jan Beulich <jbeulich@suse.com>
|
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|
|
|
|
|
|
|
|
|
* i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
|
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|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-06-01 08:40:38 +02:00
|
|
|
|
2018-06-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (sldt, str): Add NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-06-01 08:37:24 +02:00
|
|
|
|
2018-06-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (invpcid): Add Oword.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-06-01 03:30:46 +02:00
|
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|
|
2018-06-01 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
* sysdep.h (_bfd_error_handler): Don't declare.
|
|
|
|
|
|
* msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
|
|
|
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|
|
* rl78-decode.opc: Likewise.
|
|
|
|
|
|
* msp430-decode.c: Regenerate.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
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|
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|
|
2018-05-30 08:57:35 +02:00
|
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|
|
2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
|
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|
|
|
|
|
|
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|
|
* i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
|
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|
|
|
|
* i386-init.h : Regenerated.
|
|
|
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|
|
|
2018-05-25 08:35:30 +02:00
|
|
|
|
2018-05-25 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
Remove fake operand handling for extended mnemonics.
opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-22 00:31:07 +02:00
|
|
|
|
2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
|
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|
|
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|
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|
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|
|
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
|
|
|
|
|
|
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
|
|
|
|
|
|
(insert_bab, extract_bab, insert_btab, extract_btab,
|
|
|
|
|
|
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
|
|
|
|
|
|
(BAT, BBA VBA RBS XB6S): Delete macros.
|
|
|
|
|
|
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
|
|
|
|
|
|
(BB, BD, RBX, XC6): Update for new macros.
|
|
|
|
|
|
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
|
|
|
|
|
|
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
|
|
|
|
|
|
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
|
|
|
|
|
|
|
2018-05-18 16:26:18 +02:00
|
|
|
|
2018-05-18 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add support for s12z architecture.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* s12z-dis.c: New file.
|
|
|
|
|
|
* s12z.h: New file.
|
|
|
|
|
|
|
2018-05-18 01:01:13 +02:00
|
|
|
|
2018-05-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nfp-dis.c: Don't #include libbfd.h.
|
|
|
|
|
|
(init_nfp3200_priv): Use bfd_get_section_contents.
|
|
|
|
|
|
(nit_nfp6000_mecsr_sec): Likewise.
|
|
|
|
|
|
|
2018-05-17 17:24:42 +02:00
|
|
|
|
2018-05-17 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/zh_CN.po: Updated simplified Chinese translation.
|
|
|
|
|
|
|
2018-05-16 13:13:42 +02:00
|
|
|
|
2018-05-16 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23109
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
|
Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 17:37:20 +02:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
|
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|
|
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|
* aarch64-asm.c (opintl.h): Include.
|
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|
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|
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(aarch64_ins_sysreg): Enforce read/write constraints.
|
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|
|
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* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
|
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|
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
|
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(F_REG_READ, F_REG_WRITE): New.
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* aarch64-opc.c (aarch64_print_operand): Generate notes for
|
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AARCH64_OPND_SYSREG.
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(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
|
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(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
|
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mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
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id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
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id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
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id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
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mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
|
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id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
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id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
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id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
|
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csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
|
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rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
|
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mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
|
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mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
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pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
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* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
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msr (F_SYS_WRITE), mrs (F_SYS_READ).
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2018-05-15 17:34:54 +02:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* aarch64-dis.c (no_notes: New.
|
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(parse_aarch64_dis_option): Support notes.
|
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(aarch64_decode_insn, print_operands): Likewise.
|
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|
(print_aarch64_disassembler_options): Document notes.
|
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|
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|
* aarch64-opc.c (aarch64_print_operand): Support notes.
|
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|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
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|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
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|
|
|
|
|
|
|
|
|
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PR binutils/21446
|
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|
|
|
|
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
|
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|
|
|
and take error struct.
|
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|
|
|
|
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
|
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|
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|
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
|
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|
|
|
|
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
|
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|
|
|
|
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
|
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|
|
|
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
|
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|
|
|
|
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
|
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|
|
|
|
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
|
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aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
|
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aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
|
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aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
|
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|
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
|
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|
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|
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
|
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|
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
|
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aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
|
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aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
|
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aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
|
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aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
|
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aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
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aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
|
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|
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
|
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|
|
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aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
|
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|
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|
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
|
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|
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|
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
|
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|
|
|
|
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
|
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|
|
|
|
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
|
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|
|
|
|
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
|
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|
|
|
|
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
|
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|
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|
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
|
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|
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
|
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|
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
|
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|
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
|
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aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
|
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|
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
|
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aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
|
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aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
|
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aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
|
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|
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
|
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|
|
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
|
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|
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aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
|
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aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
|
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|
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
|
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aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
|
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aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
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aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
|
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|
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
|
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aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
|
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|
|
|
|
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
|
|
|
|
|
|
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
|
|
|
|
|
|
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
|
|
|
|
|
|
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
|
|
|
|
|
|
(determine_disassembling_preference, aarch64_decode_insn,
|
|
|
|
|
|
print_insn_aarch64_word, print_insn_data): Take errors struct.
|
|
|
|
|
|
(print_insn_aarch64): Use errors.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
|
|
|
|
|
|
boolean in aarch64_insert_operan.
|
|
|
|
|
|
(print_operand_extractor): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
|
|
|
|
|
|
|
2018-05-15 14:28:06 +02:00
|
|
|
|
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
|
|
|
|
|
|
|
2018-05-09 20:17:26 +02:00
|
|
|
|
2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
|
|
|
|
|
|
|
2018-05-09 08:20:29 +02:00
|
|
|
|
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-opc.c (cr16_instruction): Comment typo fix.
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Likewise.
|
|
|
|
|
|
|
RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-09 00:46:19 +02:00
|
|
|
|
2018-05-08 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
|
|
|
|
|
|
(match_c_slli64, match_srxi_as_c_srxi): New.
|
|
|
|
|
|
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
|
|
|
|
|
|
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
|
|
|
|
|
|
<c.slli, c.srli, c.srai>: Use match_s_slli.
|
|
|
|
|
|
<c.slli64, c.srli64, c.srai64>: New.
|
|
|
|
|
|
|
2018-05-07 04:05:22 +02:00
|
|
|
|
2018-05-08 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
|
|
|
|
|
|
(VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
|
|
|
|
|
|
partition opcode space for index lookup.
|
|
|
|
|
|
|
2018-05-08 03:47:54 +02:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
|
|
|
|
|
|
<insn_length>: ...with this. Update usage.
|
|
|
|
|
|
Remove duplicate call to *info->memory_error_func.
|
|
|
|
|
|
|
Enable Intel MOVDIRI, MOVDIR64B instructions
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-07 18:30:02 +02:00
|
|
|
|
2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Gva): New.
|
|
|
|
|
|
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
|
|
|
|
|
|
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
|
|
|
|
|
|
(prefix_table): New instructions (see prefix above).
|
|
|
|
|
|
(mod_table): New instructions (see prefix above).
|
|
|
|
|
|
(OP_G): Handle va_mode.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
|
|
|
|
|
|
CPU_MOVDIR64B_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
|
|
|
|
|
|
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
|
|
|
|
|
|
* i386-opc.tbl: Add movidir{i,64b}.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-05-07 18:57:06 +02:00
|
|
|
|
2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
|
|
|
|
|
|
AddrPrefixOpReg.
|
|
|
|
|
|
* i386-opc.h (AddrPrefixOp0): Renamed to ...
|
|
|
|
|
|
(AddrPrefixOpReg): This.
|
|
|
|
|
|
(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
|
|
|
|
|
|
* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
|
|
|
|
|
|
|
2018-05-07 16:40:59 +02:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
|
|
|
|
|
|
(vle_num_opcodes): Likewise.
|
|
|
|
|
|
(spe2_num_opcodes): Likewise.
|
|
|
|
|
|
* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
|
|
|
|
|
|
initialization loop.
|
|
|
|
|
|
(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
|
|
|
|
|
|
(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
|
|
|
|
|
|
only once.
|
|
|
|
|
|
|
2018-05-01 18:11:11 +02:00
|
|
|
|
2018-05-01 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
|
|
|
|
|
|
|
2018-04-30 18:02:59 +02:00
|
|
|
|
2018-04-30 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
Makefile.am: Added nfp-dis.c.
|
|
|
|
|
|
configure.ac: Added bfd_nfp_arch.
|
|
|
|
|
|
disassemble.h: Added print_insn_nfp prototype.
|
|
|
|
|
|
disassemble.c: Added ARCH_nfp and call to print_insn_nfp
|
|
|
|
|
|
nfp-dis.c: New, for NFP support.
|
|
|
|
|
|
po/POTFILES.in: Added nfp-dis.c to the list.
|
|
|
|
|
|
Makefile.in: Regenerate.
|
|
|
|
|
|
configure: Regenerate.
|
|
|
|
|
|
|
2018-04-26 08:55:02 +02:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold various non-memory operand AVX512VL
|
|
|
|
|
|
templates into their base ones.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 08:48:56 +02:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
|
|
|
|
|
|
CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
|
|
|
|
|
|
CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
|
|
|
|
|
|
CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 08:48:01 +02:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
|
|
|
|
|
|
CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
|
|
|
|
|
|
CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
|
|
|
|
|
|
Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
|
|
|
|
|
|
comment.
|
|
|
|
|
|
(cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
and CpuRegMask.
|
|
|
|
|
|
* i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
CpuRegMask: Delete.
|
|
|
|
|
|
(union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
|
|
|
|
|
|
cpuregzmm, and cpuregmask.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 08:45:35 +02:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
|
|
|
|
|
|
CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 08:30:06 +02:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (VexImmExt): Delete.
|
|
|
|
|
|
* i386-opc.h (VexImmExt, veximmext): Delete.
|
|
|
|
|
|
* i386-opc.tbl: Drop all VexImmExt uses.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-25 16:26:10 +02:00
|
|
|
|
2018-04-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
|
|
|
|
|
|
register-only forms.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-25 14:37:30 +02:00
|
|
|
|
2018-04-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
|
|
|
|
|
|
|
2018-04-16 23:09:01 +02:00
|
|
|
|
2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
|
|
|
|
|
|
PREFIX_0F1C.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
|
|
|
|
|
|
(cpu_flags): Add CpuCLDEMOTE.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuCLDEMOTE,
|
|
|
|
|
|
(i386_cpu_flags): Add cpucldemote.
|
|
|
|
|
|
* i386-opc.tbl: Add cldemote.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:59:39 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove sh5 and sh64 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* sh-dis.c: Likewise.
|
|
|
|
|
|
* sh64-dis.c: Delete.
|
|
|
|
|
|
* sh64-opc.c: Delete.
|
|
|
|
|
|
* sh64-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:56:05 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove w65 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* w65-dis.c: Delete.
|
|
|
|
|
|
* w65-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:54:43 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Remove we32k support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:53:38 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove m88k support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* m88k-dis.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:51:56 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove i370 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* i370-dis.c: Delete.
|
|
|
|
|
|
* i370-opc.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:49:41 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove h8500 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* h8500-dis.c: Delete.
|
|
|
|
|
|
* h8500-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 07:38:40 +02:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Remove tahoe support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-04-15 17:38:23 +02:00
|
|
|
|
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
|
|
|
|
|
|
umwait.
|
|
|
|
|
|
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
|
|
|
|
|
|
64-bit mode.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-04-09 12:58:50 +02:00
|
|
|
|
2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
|
|
|
|
|
|
PREFIX_MOD_1_0FAE_REG_6.
|
|
|
|
|
|
(va_mode): New.
|
|
|
|
|
|
(OP_E_register): Use va_mode.
|
|
|
|
|
|
* i386-dis-evex.h (prefix_table):
|
|
|
|
|
|
New instructions (see prefixes above).
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add WAITPKG.
|
|
|
|
|
|
(cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.h (enum): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Add umonitor, umwait, tpause.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
Remove i860, i960, bout and aout-adobe targets
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 11:16:05 +02:00
|
|
|
|
2018-04-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/i860-dis.c: Delete.
|
|
|
|
|
|
* opcodes/i960-dis.c: Delete.
|
|
|
|
|
|
* Makefile.am: Remove i860 and i960 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-04 13:36:44 +02:00
|
|
|
|
2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23025
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
|
|
|
|
|
|
to 0.
|
|
|
|
|
|
(print_insn): Clear vex instead of vex.evex.
|
|
|
|
|
|
|
2018-04-04 10:00:18 +02:00
|
|
|
|
2018-04-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
|
2018-03-28 14:25:07 +02:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete VecESize.
|
|
|
|
|
|
* i386-opc.h (VecESize): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete vecesize.
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 14:24:05 +02:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
|
|
|
|
|
|
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
|
|
|
|
|
|
* i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 14:22:56 +02:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
|
|
|
|
|
|
Fold AVX512 forms
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 14:22:00 +02:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Drop Y for cvt*2si.
|
|
|
|
|
|
(vex_len_table): Drop Y for vcvt*2si.
|
|
|
|
|
|
(putop): Replace plain 'Y' handling by abort().
|
|
|
|
|
|
|
2018-03-28 10:44:45 +02:00
|
|
|
|
2018-03-28 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22988
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
|
|
|
|
|
|
instructions with only a base address register.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
|
|
|
|
|
|
handle AARHC64_OPND_SVE_ADDR_R.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64_dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2018-03-22 08:46:25 +01:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize from register only insn forms and
|
|
|
|
|
|
memory forms not allowing broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 08:34:24 +01:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
|
|
|
|
|
|
vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
|
|
|
|
|
|
sha256*): Drop Disp<N>.
|
|
|
|
|
|
|
2018-03-22 08:32:50 +01:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EbndS, bnd_swap_mode): New.
|
|
|
|
|
|
(prefix_table): Use EbndS.
|
|
|
|
|
|
(OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
|
|
|
|
|
|
* i386-opc.tbl (bndmov): Move misplaced Load.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 08:31:43 +01:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
|
|
|
|
|
|
templates allowing memory operands and folded ones for register
|
|
|
|
|
|
only flavors.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 08:29:45 +01:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
|
|
|
|
|
|
256-bit templates. Drop redundant leftover Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-15 00:04:03 +01:00
|
|
|
|
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
|
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|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_insn_types): New.
|
|
|
|
|
|
|
2018-03-13 17:57:29 +01:00
|
|
|
|
2018-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
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|
|
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|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-03-08 15:41:34 +01:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add Optimize to clr.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 15:31:32 +01:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove OldGcc.
|
|
|
|
|
|
* i386-opc.h (OldGcc): Removed.
|
|
|
|
|
|
(i386_opcode_modifier): Remove oldgcc.
|
|
|
|
|
|
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
|
|
|
|
|
|
instructions for old (<= 2.8.1) versions of gcc.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 08:58:55 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
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|
|
|
|
|
|
|
|
|
|
* i386-opc.h (EVEXDYN): New.
|
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|
|
|
|
* i386-opc.tbl: Fold various AVX512VL templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
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|
|
|
|
2018-03-08 08:58:05 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
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|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
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|
|
|
|
vpexpandd, vpexpandq): Fold AFX512VF templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:57:19 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
|
|
|
|
|
|
Fold 128- and 256-bit VEX-encoded templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:56:47 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
|
|
|
|
|
vpexpandd, vpexpandq): Fold AVX512F templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:56:08 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
|
|
|
|
|
|
64-bit templates. Drop Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:55:37 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
|
|
|
|
|
|
and 256-bit templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:52:27 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg8b): Add NoRex64.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:36:41 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
|
|
|
|
|
|
Drop NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:35:48 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:34:09 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete FloatD.
|
|
|
|
|
|
* i386-opc.h (FloatD): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete floatd.
|
|
|
|
|
|
* i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
|
|
|
|
|
|
FloatD by D.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:33:06 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
|
|
|
|
|
|
|
2018-03-08 08:26:35 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 08:25:31 +01:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
|
|
|
|
|
|
forms.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-07 01:36:15 +01:00
|
|
|
|
2018-03-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
|
|
|
|
|
|
bfd_arch_rs6000.
|
|
|
|
|
|
* disassemble.h (print_insn_rs6000): Delete.
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
|
|
|
|
|
|
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
|
|
|
|
|
|
(print_insn_rs6000): Delete.
|
|
|
|
|
|
|
opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-01 22:53:50 +01:00
|
|
|
|
2018-03-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sysdep.h (opcodes_error_handler): Define.
|
|
|
|
|
|
(_bfd_error_handler): Declare.
|
|
|
|
|
|
* Makefile.am: Remove stray #.
|
|
|
|
|
|
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
|
|
|
|
|
|
EDIT" comment.
|
|
|
|
|
|
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
|
|
|
|
|
|
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
|
|
|
|
|
|
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
|
|
|
|
|
|
opcodes_error_handler to print errors. Standardize error messages.
|
|
|
|
|
|
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
|
|
|
|
|
|
and include opintl.h.
|
|
|
|
|
|
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
|
|
|
|
|
|
* i386-gen.c: Standardize error messages.
|
|
|
|
|
|
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
|
|
|
|
|
|
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
|
|
|
|
|
|
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
|
|
|
|
|
|
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
|
|
|
|
|
|
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
|
|
|
|
|
|
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
|
|
|
|
|
|
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
|
|
|
|
|
|
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
|
|
|
|
|
|
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
|
|
|
|
|
|
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
|
|
|
|
|
|
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
|
|
|
|
|
|
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2018-03-01 15:08:04 +01:00
|
|
|
|
2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
|
|
|
|
|
|
vpsub[bwdq] instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-02-28 22:56:51 +01:00
|
|
|
|
2018-03-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac (ALL_LINGUAS): Sort.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-02-27 17:40:45 +01:00
|
|
|
|
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
|
|
|
|
|
|
macro by assignements.
|
|
|
|
|
|
|
x86: Add -O[2|s] assembler command-line options
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
2018-02-27 16:36:33 +01:00
|
|
|
|
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/22871
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add Optimize.
|
|
|
|
|
|
* i386-opc.h (Optimize): New enum.
|
|
|
|
|
|
(i386_opcode_modifier): Add optimize.
|
|
|
|
|
|
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
|
|
|
|
|
|
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
|
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|
|
|
|
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
|
|
|
|
|
|
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
|
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|
|
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
|
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|
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|
|
vpxord and vpxorq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
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|
|
2018-02-24 01:03:33 +01:00
|
|
|
|
2018-02-26 Alan Modra <amodra@gmail.com>
|
|
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|
|
|
|
|
|
|
|
|
* crx-dis.c (getregliststring): Allocate a large enough buffer
|
|
|
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|
|
to silence false positive gcc8 warning.
|
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|
|
2018-02-22 20:28:51 +01:00
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|
|
2018-02-22 Shea Levy <shea@shealevy.com>
|
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|
|
|
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|
|
* disassemble.c (ARCH_riscv): Define if ARCH_all.
|
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|
|
2018-02-22 15:18:27 +01:00
|
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|
|
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
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|
|
|
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|
|
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|
|
* i386-opc.tbl: Add {rex},
|
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|
|
* i386-tbl.h: Regenerated.
|
|
|
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|
|
2018-02-20 21:51:36 +01:00
|
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|
|
2018-02-20 Maciej W. Rozycki <macro@mips.com>
|
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|
|
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|
|
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
|
|
|
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|
|
(mips16_opcodes): Replace `M' with `m' for "restore".
|
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|
2018-02-19 13:05:18 +01:00
|
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|
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
|
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
|
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|
|
2018-02-13 13:56:29 +01:00
|
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|
|
2018-02-13 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
|
|
|
|
|
|
variable to `function_index'.
|
|
|
|
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|
|
2018-02-13 14:14:47 +01:00
|
|
|
|
2018-02-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22823
|
|
|
|
|
|
* metag-dis.c (print_fmmov): Double buffer size to avoid warning
|
|
|
|
|
|
about truncation of printing.
|
|
|
|
|
|
|
MIPS: Fix encoding for MIPSr6 sigrie instruction.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12 15:50:42 +01:00
|
|
|
|
2018-02-12 Henry Wong <henry@stuffedcow.net>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
|
|
|
|
|
|
|
2018-02-05 14:09:15 +01:00
|
|
|
|
2018-02-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-01-23 17:56:30 +01:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add pconfig.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuPCONFIG.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuPCONFIG.
|
|
|
|
|
|
(i386_cpu_flags): Add cpupconfig.
|
|
|
|
|
|
* i386-opc.tbl: Add PCONFIG instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-23 17:39:05 +01:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_0F09.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuWBNOINVD.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuWBNOINVD.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuwbnoinvd.
|
|
|
|
|
|
* i386-opc.tbl: Add WBNOINVD instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-17 23:04:16 +01:00
|
|
|
|
2018-01-17 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
|
|
|
|
|
|
|
Replace CET bit with IBT and SHSTK bits.
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-17 17:45:52 +01:00
|
|
|
|
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
|
|
|
|
|
|
Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
|
|
|
|
|
|
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(cpu_flags): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuibt, cpushstk.
|
|
|
|
|
|
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-16 13:45:44 +01:00
|
|
|
|
2018-01-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portugese translation.
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
|
2018-01-15 23:53:44 +01:00
|
|
|
|
2018-01-15 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_nop): New.
|
|
|
|
|
|
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
|
|
|
|
|
|
|
2018-01-15 13:09:11 +01:00
|
|
|
|
2018-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2018-01-13 14:56:48 +01:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Regenerated.
|
|
|
|
|
|
|
2018-01-13 14:31:12 +01:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-01-13 14:26:38 +01:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.30 branch created.
|
|
|
|
|
|
|
2018-01-11 00:56:45 +01:00
|
|
|
|
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2018-01-10 14:53:43 +01:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 14:53:05 +01:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
|
|
|
|
|
|
vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
|
|
|
|
|
|
vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
|
|
|
|
|
|
vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
|
|
|
|
|
|
vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
|
|
|
|
|
|
Disp8MemShift of AVX512VL forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 01:40:06 +01:00
|
|
|
|
2018-01-09 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (maybe_print_address): If base_reg is zero,
|
|
|
|
|
|
then the hi_addr value is zero.
|
|
|
|
|
|
|
2018-01-09 15:15:00 +01:00
|
|
|
|
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add csdb.
|
|
|
|
|
|
(thumb32_opcodes): Add csdb.
|
|
|
|
|
|
|
2018-01-09 12:28:04 +01:00
|
|
|
|
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2018-01-08 13:36:59 +01:00
|
|
|
|
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/22681
|
|
|
|
|
|
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
|
|
|
|
|
|
Remove AVX512 vmovd with 64-bit operands.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-01-06 02:51:23 +01:00
|
|
|
|
2018-01-05 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
|
|
|
|
|
|
jalr.
|
|
|
|
|
|
|
2018-01-03 06:17:27 +01:00
|
|
|
|
2018-01-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2018-01-02 11:44:04 +01:00
|
|
|
|
2018-01-02 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
|
|
|
|
|
|
and OPERAND_TYPE_REGZMM entries.
|
|
|
|
|
|
|
2018-01-03 06:15:17 +01:00
|
|
|
|
For older changes see ChangeLog-2017
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
2018-01-03 06:15:17 +01:00
|
|
|
|
Copyright (C) 2018 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
