Add the relocation numbers defined in ABI release 1.0 but missing
from the current header. This will allow tools like objdump to dump
objects that use these relocations.
include/elf/ChangeLog:
2014-10-08 Will Newton <will.newton@linaro.org>
* aarch64.h: Sync up relocations with ABI release 1.0.
Refactor each relaxation pattern to raise the maintainability.
In origin, all patterns is analysed in nds32_elf_relax_section,
so it is hard to debug and maintain. Therefore, we classify all
patterns into different functions in this patch.
Moreover, we adjust all optimizations into nds32_elf_relax_section
to take these optimizations in turn. This can promise all relaxation
being done after calling gld${EMULATION_NAME}_after_allocation.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elfn32-mips.c: Likewise.
* elfxx-mips.c (MIPSR6_P): New define.
(mipsr6_exec_plt_entry): New array.
(hi16_reloc_p): Add support for R_MIPS_PCHI16.
(lo16_reloc_p): Add support for R_MIPS_PCLO16.
(aligned_pcrel_reloc_p): New function.
(mips_elf_relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(mips_elf_calculate_relocation): Add support for relocs:
R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
R_MIPS_PCHI16 and R_MIPS_PCLO16.
(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(_bfd_mips_elf_relocate_section): Add a check for unaligned
pc relative relocs.
(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
plt entry.
(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
(mips_32bit_flags_p): Add support for mips32r6.
* libbfd.h (bfd_reloc_code_real_names): Add entries for
BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
binutils/
* readelf.c (get_machine_flags): Add support for mips32r6 and
mips64r6.
elfcpp/
* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
gas/
* config/tc-mips.c (mips_nan2008): New static global.
(mips_flag_nan2008): Removed.
(LL_SC_FMT): New define.
(COP12_FMT): Updated.
(ISA_IS_R6): New define.
(ISA_HAS_64BIT_REGS): Add mips64r6.
(ISA_HAS_DROR): Likewise.
(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_LEGACY_NAN): New define.
(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
(mips_ase): Add field rem_rev.
(mips_ases): Updated to add which ISA an ASE was removed in.
(mips_isa_rev): Add support for mips32r6 and mips64r6.
(mips_check_isa_supports_ase): Add support to check if an ASE
has been removed in the specified MIPS ISA revision.
(validate_mips_insn): Skip '-' character.
(macro_build): Likewise.
(mips_check_options): Prevent R6 working with fp32, mips16,
micromips, or branch relaxation.
(file_mips_check_options): Set R6 floating point registers to
64 bit. Also deal with the nan2008 option.
(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(match_check_prev_operand): New static function.
(match_same_rs_rt_operand): New static function.
(match_non_zero_reg_operand): New static function.
(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(insns_between): Added case to deal with forbidden slots.
(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
and BFD_RELOC_MIPS_26_PCREL_S2.
(match_insn): Add support for operands -A, -B, +' and +". Also
skip '-' character.
(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
(md_parse_option): Add support for mips32r6 and mips64r6. Also
update the nan option handling.
(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2.
(mips_force_relocation): Prevent forced relaxation for MIPS r6.
(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(s_mipsset): Add support for mips32r6 and mips64r6.
(s_nan): Update to support the new nan2008 framework.
(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(mips_elf_final_processing): Updated to use the mips_nan2008.
(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
macros for R6.
(mips_fix_adjustable): Make PC relative R6 relocations relative
to the symbol and not the section.
* configure.ac: Add support for mips32r6 and mips64r6.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
non-supported instructions from being tested.
* gas/mips/24k-triple-stores-2.s: Likewise.
* gas/mips/24k-triple-stores-3.s: Likewise.
* gas/mips/24k-triple-stores-6.s: Likewise.
* gas/mips/beq.s: Likewise.
* gas/mips/eva.s: Likewise.
* gas/mips/ld-zero-3.s: Likewise.
* gas/mips/mips32-cp2.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/add.s: Don't test the add instructions if r6, and
add padding.
* gas/mips/add.d: Check for a triple dot not a nop at the end of the
disassembly output.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
* gas/mips/mipsr6@add.d: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
* gas/mips/mipsr6@beq.d: New file.
* gas/mips/mipsr6@bge.d: New file.
* gas/mips/mipsr6@bgeu.d: New file.
* gas/mips/mipsr6@blt.d: New file.
* gas/mips/mipsr6@bltu.d: New file.
* gas/mips/mipsr6@branch-misc-1.d: New file.
* gas/mips/mipsr6@branch-misc-2-64.d: New file.
* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
* gas/mips/mipsr6@branch-misc-4-64.d: New file.
* gas/mips/mipsr6@cache.d: New file.
* gas/mips/mipsr6@eva.d: New file.
* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
* gas/mips/mipsr6@jal-svr4pic.d: New file.
* gas/mips/mipsr6@ld-zero-2.d: New file.
* gas/mips/mipsr6@ld-zero-3.d: New file.
* gas/mips/mipsr6@loc-swap-dis.d: New file.
* gas/mips/mipsr6@mips32-cp2.d: New file.
* gas/mips/mipsr6@mips32-imm.d: New file.
* gas/mips/mipsr6@mips32.d: New file.
* gas/mips/mipsr6@mips32r2.d: New file.
* gas/mips/mipsr6@mips4-fp.d: New file.
* gas/mips/mipsr6@mips4-fp.l: New file.
* gas/mips/mipsr6@mips4-fp.s: New file.
* gas/mips/mipsr6@mips4.d: New file.
* gas/mips/mipsr6@mips5-fp.d: New file.
* gas/mips/mipsr6@mips5-fp.l: New file.
* gas/mips/mipsr6@mips5-fp.s: New file.
* gas/mips/mipsr6@mips64.d: New file.
* gas/mips/mipsr6@msa-branch.d: New file.
* gas/mips/mipsr6@msa.d: New file.
* gas/mips/mipsr6@pref.d: New file.
* gas/mips/mipsr6@relax-swap3.d: New file.
* gas/mips/r6-64-n32.d: New file.
* gas/mips/r6-64-n64.d: New file.
* gas/mips/r6-64-removed.l: New file.
* gas/mips/r6-64-removed.s: New file.
* gas/mips/r6-64.s: New file.
* gas/mips/r6-attr-none-double.d: New file.
* gas/mips/r6-n32.d: New file.
* gas/mips/r6-n64.d: New file.
* gas/mips/r6-removed.l: New file.
* gas/mips/r6-removed.s: New file.
* gas/mips/r6.d: New file.
* gas/mips/r6.s: New file.
* gas/mips/mipsr6@mips32-dsp.d: New file.
* gas/mips/mipsr6@mips32-dspr2.d: New file.
* gas/mips/mipsr6@mips32r2-ill.l: New file.
* gas/mips/mipsr6@mips32r2-ill.s: New file.
* gas/mips/cache.s: Add r6 instruction varients.
* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
architectures. Also prevent non r6 supported tests from running.
Finally, add in support for running the new r6 tests.
(run_dump_test_arch): Add support for mipsr6 tests.
(run_list_test_arch): Add support for using files of the
form arch@testname.l .
include/elf/
* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(E_MIPS_ARCH_32R6): New define.
(E_MIPS_ARCH_64R6): New define.
include/opcode/
* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+I, +O, +R, +:, +\, +", +;
(mips_check_prev_operand): New struct.
(INSN2_FORBIDDEN_SLOT): New define.
(INSN_ISA32R6): New define.
(INSN_ISA64R6): New define.
(INSN_UPTO32R6): New define.
(INSN_UPTO64R6): New define.
(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
(ISA_MIPS32R6): New define.
(ISA_MIPS64R6): New define.
(CPU_MIPS32R6): New define.
(CPU_MIPS64R6): New define.
(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
ld/
* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
opcodes/
* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
mips64r6.
(parse_mips_dis_option): Allow MSA and virtualization support for
mips64r6.
(mips_print_arg_state): Add fields dest_regno and seen_dest.
(mips_seen_register): New function.
(print_insn_arg): Refactored code to use mips_seen_register
function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
the register rather than aborting.
(print_insn_args): Add length argument. Add code to correctly
calculate the instruction address for pc relative instructions.
(validate_insn_args): New static function.
(print_insn_mips): Prevent jalx disassembling for r6. Use
validate_insn_args.
(print_insn_micromips): Use validate_insn_args.
all the arguments are valid.
* mips-formats.h (PREV_CHECK): New define.
* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
(RD_pc): New define.
(FS): New define.
(I37): New define.
(I69): New define.
(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
MIPS R6 instructions from MIPS R2 instructions.
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.
opcodes/
* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
"sdbbp", "syscall" and "wait".
include/opcode/
* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
over to `+J'.
addresses outside of the 32-bit range before memory exhaustion. This
results in a higher entropy implementation of ASLR when used with the
DYNAMIC_BASE flag.
* include/coff/pe.h: Add HIGH_ENTROPY_VA flag
* ld/emultempl/pep.em: Add --high-entropy-va switch
* ld/ld.texinfo: Document the --high-entropy-va switch
The main aim of this change was to have non_ir_ref set correctly on
new indirect symbols. I could have added a "copy" param to the "notice"
function, so that indirect symbols could be created in plugin_notice,
but it seemed cleaner to create indirect syms earlier and pass them
rather than "string" to "notice".
include/
* bfdlink.h (struct bfd_link_callbacks <notice>): Remove "string"
param, add "inh".
bfd/
* coff-aux.c (coff_m68k_aux_link_add_one_symbol): Only call "notice"
here when not calling the generic add_symbol function. Formatting.
Correct handling of indirect symbols. Update notice call.
* elflink.c (_bfd_elf_notice_as_needed): Update notice call.
* linker.c (_bfd_generic_link_add_one_symbol): Create indirect
symbols early. Update notice call. Add comments regarding weak
symbols vs. indirect.
ld/
* ldmain.c (notice): Update args.
* plugin.c (plugin_notice): Likewise. Follow warning sym link.
Handle new indirect symbol.
gas/
* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
include/opcode/
* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
(INSN_LOAD_COPROC): New define.
(INSN_COPROC_MOVE_DELAY): Rename to...
(INSN_COPROC_MOVE): New define.
opcodes/
* micromips-opc.c (COD): Rename throughout to...
(CM): New define, update to use INSN_COPROC_MOVE.
(LCD): Rename throughout to...
(LC): New define, update to use INSN_LOAD_COPROC.
* mips-opc.c: Likewise.
* elf32-avr.c: Handle R_AVR_PORT5 and R_AVR_PORT6.
* reloc.c: Add BFD_RELOC_AVR_PORT5 and BFD_RELOC_AVR_PORT6.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* avr.h: Add R_AVR_PORT5 and R_AVR_PORT6.
* config/tc-avr.c (avr_operand): Permit referring to r26-r31 by
name as [xyz][hl]. Permit using a symbol whoes name begins with
`r' to refer to a register.
Allow arbitrary expressions for the P and p operators.
(md_apply_fix): Check the BFD_RELOC_AVR_PORT5 and
BFD_RELOC_AVR_PORT6 relocations.
* archures.c: add avrtiny architecture for avr target.
* bfd-in2.h: Regenerate.
* cpu-avr.c (arch_info_struct): add avrtiny arch info.
* elf32-avr.c (elf_avr_howto_table): new relocation R_AVR_LDS_STS_16
added for 16 bit LDS/STS instruction of avrtiny arch.
(avr_reloc_map): reloc R_AVR_LDS_STS_16 is mapped to
BFD_RELOC_AVR_LDS_STS_16.
(bfd_elf_avr_final_write_processing): select machine number avrtiny arch.
(elf32_avr_object_p): set machine number for avrtiny arch.
* libbfd.h: Regenerate.
* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.
* config/tc-avr.c (mcu_types): Add avrtiny arch.
Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
and attiny40.
(md_show_usage): Add avrtiny arch in usage message.
(avr_operand): validate and issue error for invalid register for avrtiny.
add new reloc exp for 16 bit lds/sts instruction.
(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
(md_assemble): check ISA for arch and issue diagnostic.
* include/elf/avr.h (E_AVR_MACH_AVRTINY): define avrtiny machine number.
(R_AVR_LDS_STS_16): define 16 bit lds/sts reloc number.
* include/opcode/avr.h (AVR_ISA_TINY): define avrtiny specific ISA.
(AVR_ISA_2xxxa): define ISA without LPM.
(AVR_ISA_AVRTINY): define avrtiny arch ISA.
Add doc for contraint used in 16 bit lds/sts.
Adjust ISA group for icall, ijmp, pop and push.
Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
* opcodes/avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
(print_insn_avr): do not select opcode if insn ISA is avrtiny and machine
is not avrtiny.
* Makefile.am (ALL_EMULATION_SOURCES): add avrtiny emulation source.
(eavrtiny.c): add rules for avrtiny emulation source.
* Makefile.in: Regenerate.
* configure.tgt: Add avrtiny to avr target emulations.
* scripttempl/avrtiny.sc: New file.
linker script template for avrtiny arch.
* emulparams/avrtiny.sh: New file.
emulation parameters for avrtiny arch.
Fixes issues with dwz multi-file (-m) and ld's -wrap option.
Symbols referenced from DWARF debug info in a separate file, eg. to
specify low and high pc, must use the real symbol. The DWARF info
is specifying attributes of the real function, not one interposed
with --wrap.
include/
* bfdlink.h (unwrap_hash_lookup): Declare.
bfd/
* linker.c (unwrap_hash_lookup): New function.
* elf-bfd (RELOC_FOR_GLOBAL_SYMBOL): Call unwrap_hash_lookup.
* elf32-i370.c (i370_elf_relocate_section): Likewise.
* elf32-m32c.c (m32c_elf_relocate_section): Likewise.
* elf32-m32r.c (m32r_elf_relocate_section): Likewise.
* elf32-score.c (s3_bfd_score_elf_relocate_section): Likewise.
* elf32-score7.c (s7_bfd_score_elf_relocate_section): Likewise.
* elf32-spu.c (spu_elf_relocate_section): Likewise.
* elf64-hppa.c (elf64_hppa_relocate_section): Likewise.
* config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter.
Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1.
(msp430_srcoperand): Store vshift value in operand.
* msp430.h (struct msp430_operand_s): Add vshift field.
* gas/elf/struct.d: Expect extra output from some toolchains.
* gas/symver/symver0.d: Likewise.
* gas/symver/symver1.d: Likewise.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
bfd/
* peicode.h (pe_ILF_object_p): Adjust, as the version number
has been read.
(pe_bfd_object_p): Also read version number to detect ILF.
* pe-x86_64.c (COFF_WITH_PE_BIGOBJ): Define.
(x86_64pe_bigobj_vec): Define
* coffcode.h (bfd_coff_backend_data): Add _bfd_coff_max_nscns field.
(bfd_coff_max_nscns): New macro.
(coff_compute_section_file_positions): Use unsigned int for
target_index. Compare with bfd_coff_max_nscns.
(bfd_coff_std_swap_table, ticoff0_swap_table, ticoff1_swap_table):
Set a value for _bfd_coff_max_nscns.
(header_bigobj_classid): New constant.
(coff_bigobj_swap_filehdr_in, coff_bigobj_swap_filehdr_out)
(coff_bigobj_swap_sym_in, coff_bigobj_swap_sym_out)
(coff_bigobj_swap_aux_in, coff_bigobj_swap_aux_out): New
functions.
(bigobj_swap_table): New table.
* libcoff.h: Regenerate.
* coff-sh.c (bfd_coff_small_swap_table): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Add value for
_bfd_coff_max_nscns.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coff-rs6000.c (bfd_xcoff_backend_data)
(bfd_pmac_xcoff_backend_data): Likewise.
* coff64-rs6000.c (bfd_xcoff_backend_data)
(bfd_xcoff_aix5_backend_data): Likewise.
* targets.c (x86_64pe_bigobj_vec): Declare.
* configure.in (x86_64pe_bigobj_vec): New vector.
* configure: Regenerate.
* config.bfd: Add bigobj object format for Windows targets.
gas/
* config/tc-i386.c (use_big_obj): Declare.
(OPTION_MBIG_OBJ): Define.
(md_longopts): Add -mbig-obj option.
(md_parse_option): Handle it.
(md_show_usage): Display help for this option.
(i386_target_format): Use bigobj for x86-64 if -mbig-obj.
* doc/c-i386.texi: Document the option.
gas/testsuite/
* gas/pe/big-obj.d, gas/pe/big-obj.s: Add test.
* gas/pe/pe.exp: Add test.
include/coff/
* pe.h (struct external_ANON_OBJECT_HEADER_BIGOBJ): Declare.
(FILHSZ_BIGOBJ): Define.
(struct external_SYMBOL_EX): Declare.
(SYMENT_BIGOBJ, SYMESZ_BIGOBJ): Define.
(union external_AUX_SYMBOL_EX): Declare.
(AUXENT_BIGOBJ, AUXESZ_BIGOBJ): Define.
* internal.h (struct internal_filehdr): Change type
of f_nscns.
It is rare for people to want to modify the cmd arg. In general, they
really shouldn't be, but a few still do. For those who misbehave, dupe
the string locally so they can bang on it.
This adds support for "func@localentry", an expression that returns the
ELFv2 local entry point address of function "func". I've excluded
dynamic relocation support because that obviously would require glibc
changes.
include/elf/
* ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
bfd/
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* Add BFD_RELOC_PPC64_ADDR64_LOCAL.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @localentry.
(md_apply_fix): Support R_PPC64_ADDR64_LOCAL.
ld/testsuite/
* ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files.
* ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files.
* ld-powerpc/powerpc.exp: Run new test.
elfcpp/
* powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::local, global): Support
R_PPC64_ADDR64_LOCAL.
(Target_powerpc::Relocate::relocate): Likewise.
Recent ppc64 Linux kernels provide a new auxv entry AT_HWCAP2,
which is currently not recognized by GDB, causing every use of
"info auxv" to show an error.
This commit adds the AT_HWCAP2 define to include/elf/common.h
and handles it in GDB.
include/elf/ChangeLog:
* common.h (AT_HWCAP2): Define.
gdb/ChangeLog:
* auxv.c (fprint_target_auxv): Handle AT_HWCAP2.
This removes the remaining uses of PARAMS from include/cgen.
Tested by rebuilding; a file in opcodes includes this header.
2014-01-06 Tom Tromey <tromey@redhat.com>
* bitset.h: Remove uses of PARAMS.
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
bfd/
2013-11-27 Tristan Gingold <gingold@adacore.com>
* pei-x86_64.c (pex_regs): Make it const. Add comments.
(pex64_get_runtime_function): Do not split UnwindData.
(pex64_get_unwind_info): Extract the chain and the handler.
(pex64_xdata_print_uwd_codes): Rewritten: do not reverse print
the opcode, handle version 2, add consistency check, make the
code host neutral.
(pex64_dump_xdata): Change arguments to pass the section and its
content. Handle version 2, change output.
(pex64_bfd_print_pdata): Add comments, load section for xdata.
Avoid duplicate outputs.
include/coff
2013-11-27 Tristan Gingold <gingold@adacore.com>
* pe.h (struct pex64_runtime_function): Remove isChained.
(UWOP_SAVE_XMM): Add comment.
(struct pex64_unwind_info): Remove extra fields.
gas/
* config/tc-arm.c (arm_archs): New armv7ve architecture option.
(arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with
ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Document armv7ve.
gas/testsuite/
* gas/arm/attr-march-armv7ve.d: New test case for armv7ve.
include/opcode/
* arm.h (ARM_AEXT_V7VE): New define.
(ARM_ARCH_V7VE): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Use
R_AARCH64_TLS_DTPMOD64 instead of R_AARCH64_TLS_DTPMOD;
likewise for R_AARCH64_TLS_DTPREL and R_AARCH64_TLS_TPREL.
include/elf/
* aarch64.h: Define R_AARCH64_TLS_DTPMOD64,
R_AARCH64_TLS_DTPREL64 and R_AARCH64_TLS_TPREL64; guard
R_AARCH64_TLS_DTPMOD, R_AARCH64_TLS_DTPREL and
R_AARCH64_TLS_TPREL with RELOC_MACROS_GEN_FUNC.
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
This removes the DT_PPC_TLSOPT/DT_PPC64_TLSOPT dynamic tag and replaces
it with DT_PPC_OPT/DT_PPC64_OPT tag to provide the same functionality
and more. This isn't backwards compatible, but the TLSOPT tag hasn't
been used since the tls optimisation support was never submitted to
glibc.
/include/elf/
* ppc.h (DT_PPC_TLSOPT): Delete.
(DT_PPC_OPT, PPC_OPT_TLS): Define.
* ppc64.h (DT_PPC64_TLSOPT): Delete.
(DT_PPC64_OPT, PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC): Define.
bfd/
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Use new DT_PPC_OPT
tag to specify tls optimisation.
* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_finish_dynamic_sections): Specify whether multiple
toc pointers are used via DT_PPC64_OPT.
binutils/
* readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT.
(get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT.
This defines the ELF symbol st_other field used to encode the number
of instructions between a function "global entry" and its "local entry",
and adds support related to the local entry offset.
include/elf/
* ppc64.h (STO_PPC64_LOCAL_BIT, STO_PPC64_LOCAL_MASK): Define.
(ppc64_decode_local_entry, ppc64_encode_local_entry): New functions.
(PPC64_LOCAL_ENTRY_OFFSET, PPC64_SET_LOCAL_ENTRY_OFFSET): Define.
bfd/
* elf64-ppc.c (struct ppc_stub_hash_entry): Add "other".
(stub_hash_newfunc): Init new ppc_stub_hash_entry field, and one
we forgot, "plt_ent".
(ppc64_elf_add_symbol_hook): Check ELFv1 objects don't have
st_other bits only valid in ELFv2.
(ppc64_elf_merge_symbol_attribute): New function.
(ppc_type_of_stub): Add local_off param to test branch range.
(ppc_build_one_stub): Adjust destinations for ELFv2 locals.
(ppc_size_one_stub, toc_adjusting_stub_needed): Similarly.
(ppc64_elf_size_stubs): Pass local_off to ppc_type_of_stub.
Set "other" field.
(ppc64_elf_relocate_section): Adjust destination for ELFv2 local
calls.
gas/
* config/tc-ppc.c (md_pseudo_table): Add .localentry.
(ppc_elf_localentry): New function.
(ppc_force_relocation): Force relocs on all branches to localenty
symbols.
(ppc_fix_adjustable): Don't reduce such symbols to section+offset.
binutils/
* readelf.c (get_ppc64_symbol_other): New function.
(get_symbol_other): Use it for EM_PPC64.
Defines bits in ELF e_flags to differentiate ELFv2 objects from ELFv2,
adds .abiversion directive to explicitly choose the ABI, and code to
check and automatically select ABI.
include/elf/
* ppc64.h (EF_PPC64_ABI): Define.
bfd/
* elf64-ppc.c (abiversion, set_abiversion): New functions.
(ppc64_elf_get_synthetic_symtab): Handle ELFv2 objects without .opd.
(struct ppc_link_hash_table): Add opd_abi.
(ppc64_elf_check_relocs): Check no .opd with ELFv2.
(ppc64_elf_merge_private_bfd_data): New function.
(ppc64_elf_print_private_bfd_data): New function.
(ppc64_elf_tls_setup): Set htab->opd_abi.
(ppc64_elf_size_dynamic_sections): Don't emit OPD related dynamic
tags for ELFv2.
(ppc_build_one_stub): Use R_PPC64_IRELATIVE for ELFv2 ifunc.
(ppc64_elf_finish_dynamic_symbol): Likewise
binutils/
* readelf.c (get_machine_flags): Display ABI version for EM_PPC64.
gas/
* config/tc-ppc.c: Include elf/ppc64.h.
(ppc_abiversion): New variable.
(md_pseudo_table): Add .abiversion.
(ppc_elf_abiversion, ppc_elf_end): New functions.
* config/tc-ppc.h (md_end): Define.
This changes the behaviour of @h and @ha on PowerPC64 to report errors
on 32-bit overflow. The motivation for this change is that on
PowerPC64, most uses of @h and @ha modifiers and their corresponding
relocations are to build up 32-bit offsets. We'd like to know when
such offsets overflow. Only rarely do people use @h or @ha with the
high 32-bit modifiers to build a 64-bit constant. Those uses will now
need to use two new modifiers, @high and @higha, if the constant isn't
known at assembly time. For now, we won't report overflow at assembly
time..
This also fixes an error when applying some of the HIGHER and HIGHEST
relocations.
include/elf/
* ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
(IS_PPC64_TLS_RELOC): Match new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
Make all _HA and _HI relocs report signed overflow.
(ppc64_elf_reloc_type_lookup): Handle new relocs.
(must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
(dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
(ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (SEX16): Don't mask.
(REPORT_OVERFLOW_HI): Define as zero.
(ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
@tprel@high, and @tprel@higha modifiers.
(md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
Handle new relocs.
(md_apply_fix): Similarly.
elfcpp/
* powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
(Target_powerpc::Scan::global, local): Likewise.
(Target_powerpc::Relocate::relocate): Likewise. Check for overflow
on all ppc64 @h and @ha relocs.
- The Mach exception/signals escaped the TARGET_ -> GDB_ prefix change
done a while ago, but there's no real reason for that. I grepped
for TARGET_EXC and fixed all found, which unsurprisingly, means
darwin-nat.c needed fixing. I think the change there is as obvious
and trivial as it can get, so I'd be quite surprised if this broke
anything there somehow.
- GDB_SIGNAL_LAST's description string was unnecessarily inconsistent
with the enum name.
Built on x86_64 Fedora 17.
gdb/
2013-10-22 Pedro Alves <palves@redhat.com>
* include/gdb/signals.def (TARGET_EXC_BAD_ACCESS): Rename to
GDB_EXC_BAD_ACCESS.
(TARGET_EXC_BAD_INSTRUCTION): Rename to GDB_EXC_BAD_INSTRUCTION.
(TARGET_EXC_ARITHMETIC): Rename to GDB_EXC_ARITHMETIC.
(TARGET_EXC_EMULATION): Rename to GDB_EXC_EMULATION.
(TARGET_EXC_SOFTWARE): Rename to GDB_EXC_SOFTWARE.
(TARGET_EXC_BREAKPOINT): Rename to GDB_EXC_BREAKPOINT.
(GDB_SIGNAL_LAST): Change description string.
* common/signals.c (gdb_signal_from_host, do_gdb_signal_to_host):
Adjust to signal renaming.
* darwin-nat.c (darwin_decode_message): Likewise.
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
(mips_int_operand_min, mips_int_operand_max): New functions.
(mips_decode_pcrel_operand): Use mips_decode_int_operand.
opcodes/
* mips-formats.h (PCREL): Reorder parameters and update the definition
to match new mips_pcrel_operand layout.
(JUMP, JALX, BRANCH): Update accordingly.
* mips16-opc.c (decode_mips16_operand): Likewise.
gas/
* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
and mips_int_operand_max.
(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
Delete.
(mips16_immed_operand, mips16_immed_in_range_p): New functions.
(mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
instead of mips16_immed_operand.
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
(MIPS16_INSN_COND_BRANCH): Delete.
opcodes/
* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
(WR_SP): Replace with...
(MOD_SP): ...this.
(mips16_opcodes): Update accordingly.
* mips-dis.c (print_insn_mips16): Likewise.
gas/
* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
flags for MIPS16 and non-MIPS16 instructions.
(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
and non-MIPS16 instructions. Fix formatting.
* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
(mips_operand, mips_int_operand, mips_mapped_int_operand)
(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
(mips_pcrel_operand): New structures.
(mips_insert_operand, mips_extract_operand, mips_signed_operand)
(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
(decode_mips_operand, decode_micromips_operand): Declare.
opcodes/
* mips-formats.h: New file.
* mips-opc.c: Include mips-formats.h.
(reg_0_map): New static array.
(decode_mips_operand): New function.
* micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
(int_c_map): New static arrays.
(decode_micromips_operand): New function.
* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(print_reg): New function.
(mips_print_arg_state): New structure.
(init_print_arg_state, print_insn_arg): New functions.
(print_insn_args): Change interface and use mips_operand structures.
Delete GET_OP_S. Move GET_OP definition to...
(print_insn_mips): ...here. Update the call to print_insn_args.
(print_insn_micromips): Use print_insn_args.
gas/
* config/tc-mips.c (validate_mips_insn): Move further up file.
Add insn_bits and decode_operand arguments. Use the mips_operand
fields to work out which bits an operand occupies. Detect double
definitions.
(validate_micromips_insn): Move further up file. Call into
validate_mips_insn.
* mips.h (EF_MIPS_NAN2008): New macro.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle
EF_MIPS_NAN2008.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
binutils/
* readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008.
gas/
* config/tc-mips.c (mips_flag_nan2008): New variable.
(options): Add OPTION_NAN enum value.
(md_longopts): Handle it.
(md_parse_option): Likewise.
(s_nan): New function.
(mips_elf_final_processing): Handle EF_MIPS_NAN2008.
(md_show_usage): Add -mnan.
* doc/as.texinfo (Overview): Add -mnan.
* doc/c-mips.texi (MIPS Opts): Document -mnan.
(MIPS NaN Encodings): New node. Document .nan directive.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/nan-2008-1.d: New test.
* gas/mips/nan-2008-2.d: New test.
* gas/mips/nan-2008-3.d: New test.
* gas/mips/nan-2008-4.d: New test.
* gas/mips/nan-legacy-1.d: New test.
* gas/mips/nan-legacy-2.d: New test.
* gas/mips/nan-legacy-3.d: New test.
* gas/mips/nan-legacy-4.d: New test.
* gas/mips/nan-legacy-5.d: New test.
* gas/mips/nan-error-1.l: New list test.
* gas/mips/nan-error-2.l: New list test.
* gas/mips/nan-2008-override.s: New test source.
* gas/mips/nan-2008.s: New test source.
* gas/mips/nan-legacy-override.s: New test source.
* gas/mips/nan-legacy.s: New test source.
* gas/mips/nan-error-1.s: New test source.
* gas/mips/nan-error-2.s: New test source.
* gas/mips/mips.exp: Run the new tests.
ld/testsuite/
* ld-mips-elf/nan-2008.d: New test.
* ld-mips-elf/nan-legacy.d: New test.
* ld-mips-elf/nan-mixed-1.d: New test.
* ld-mips-elf/nan-mixed-2.d: New test.
* ld-mips-elf/nan-2008.s: New test source.
* ld-mips-elf/nan-legacy.s: New test source.
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
* mips.h: Update documentation of "+s" and "+S".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
"+S" for "cins".
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
Combine cases.
gas/
* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
Require the msb to be <= 31 for "+s". Check that the size is <= 31
for both "+s" and "+S".
* mips.h: Document "+i".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
(mips_ip, mips16_ip): Handle "+i".
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
opcodes/
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
include/elf/
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
R_390_PC24DBL, and R_390_PLT24DBL.
gas/testsuite/
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
variants requiring relocations.
* gas/s390/zarch-zEC12.d: Likewise.
gas/
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
relocs.
bfd/
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
relocations.
* elf64-s390.c: See elf32-s390.c
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
* libbfd.h: Add new reloc strings.
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
Use "source" rather than "destination" for microMIPS "G".
gas/
* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
* elfxx-mips.h (_bfd_mips_elf_get_synthetic_symtab): New
prototype.
* elf32-mips.c (elf_backend_plt_sym_val): Remove macro.
(bfd_elf32_get_synthetic_symtab): New macro.
* elfxx-mips.c (plt_entry): New structure.
(mips_elf_link_hash_entry): Add use_plt_entry member.
(mips_elf_link_hash_table): Rename plt_entry_size member to
plt_mips_entry_size. Add plt_comp_entry_size, plt_mips_offset,
plt_comp_offset, plt_got_index entries and plt_header_is_comp
members.
(STUB_LW_MICROMIPS, STUB_MOVE_MICROMIPS): New macros.
(STUB_LUI_MICROMIPS, STUB_JALR_MICROMIPS): Likewise.
(STUB_ORI_MICROMIPS, STUB_LI16U_MICROMIPS): Likewise.
(STUB_LI16S_MICROMIPS): Likewise.
(MICROMIPS_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_o32_exec_plt0_entry): New variable.
(mips16_o32_exec_plt_entry): Likewise.
(micromips_o32_exec_plt_entry): Likewise.
(mips_elf_link_hash_newfunc): Initialize use_plt_entry.
(mips_elf_output_extsym): Update to use gotplt_union's plist
member rather than offset.
(mips_elf_gotplt_index): Likewise. Remove the VxWorks
restriction. Use MIPS_ELF_GOT_SIZE to calculate GOT address.
(mips_elf_count_got_symbols): Update to use gotplt_union's plist
member rather than offset.
(mips_elf_calculate_relocation): Handle MIPS16/microMIPS PLT
entries.
(_bfd_mips_elf_create_dynamic_sections): Don't set PLT sizes
here.
(mips_elf_make_plt_record): New function.
(_bfd_mips_elf_check_relocs): Update comment. Record occurences
of JAL relocations that might need a PLT entry.
(_bfd_mips_elf_adjust_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Set individual
PLT entry sizes here. Handle MIPS16/microMIPS PLT entries.
Don't set the symbol's value in the symbol table for PLT
references here. Don't set the PLT or PLT GOT section sizes
here.
(mips_elf_estimate_stub_size): Handle microMIPS stubs.
(mips_elf_allocate_lazy_stub): Likewise.
(mips_elf_lay_out_lazy_stubs): Likewise. Define a _MIPS_STUBS_
magic symbol.
(mips_elf_set_plt_sym_value): New function.
(_bfd_mips_elf_size_dynamic_sections): Set PLT header size and
PLT and PLT GOT section sizes here. Set the symbol values in
the symbol table for PLT references here. Handle microMIPS
annotation of the _PROCEDURE_LINKAGE_TABLE_ magic symbol.
(_bfd_mips_elf_finish_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Handle
MIPS16/microMIPS PLT entries. Handle microMIPS stubs.
(_bfd_mips_vxworks_finish_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Use
MIPS_ELF_GOT_SIZE to calculate GOT address.
(mips_finish_exec_plt): Handle microMIPS PLT. Return status.
(_bfd_mips_elf_finish_dynamic_sections): Handle result from
mips_finish_exec_plt.
(_bfd_mips_elf_link_hash_table_create): Update to use
gotplt_union's plist member rather than offset.
(_bfd_mips_elf_get_synthetic_symtab): New function.
include/elf/
* mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting.
(ELF_ST_SET_MIPS_PLT): Likewise.
gdb/
* mips-tdep.c (mips_elf_make_msymbol_special): Handle MIPS16 and
microMIPS synthetic symbols.
ld/
* emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed
as close to .plt as possible.
* scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and
$PLT_NEXT_DATA variables.
ld/testsuite/
* ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support.
* ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_
magic symbol.
* ld-mips-elf/pic-and-nonpic-3b.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise.
* ld-mips-elf/stub-dynsym-1-10000.d: Likewise.
* ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise.
* ld-mips-elf/stub-dynsym-1-7fff.d: Likewise.
* ld-mips-elf/stub-dynsym-1-8000.d: Likewise.
* ld-mips-elf/stub-dynsym-1-fff0.d: Likewise.
* ld-mips-elf/tlslib-o32.d: Likewise.
opcodes/
* mips-dis.c (is_mips16_plt_tail): New function.
(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
word.
(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
* config.bfd (msp430): Define targ_selvecs.
* configure.in: Add bfd_elf32_msp430_ti_vec.
* cpu-msp430.c: Add some more MSP430 machine numbers.
* elf32-msp430.c Add support for MSP430X relocations.
Add support for TI compiler generated relocations.
Add support for sym_diff relocations.
Add support for relaxing out of range short branches into long
branches.
Add support for MSP430 attribute section.
* reloc.c: Add MSP430X relocations.
* targets.c: Add bfd_elf32_msp430_ti_vec.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* readelf.c: Add support for MSP430X architecture.
* readelf.exp: Expect -wi test to fail for the MSP430.
* config/tc-msp430.c: Add support for the MSP430X architecture.
Add code to insert a NOP instruction after any instruction that
might change the interrupt state.
Add support for the LARGE memory model.
Add code to initialise the .MSP430.attributes section.
* config/tc-msp430.h: Add support for the MSP430X architecture.
* doc/c-msp430.texi: Document the new -mL and -mN command line
options.
* NEWS: Mention support for the MSP430X architecture.
* gas/all/gas.exp: Skip the DIFF1 test for the MSP430.
Expect the FORWARD test to pass for the MSP430.
Skip the REDEF tests for the MSP430.
Expect the 930509A test to fail for the MSP430.
* gas/all/sleb128-4.d: Skip for the MSP430.
* gas/elf/elf.exp: Set target_machine to msp430 for the MSP430.
Skip the EHOPT0 test for the MSP430.
Skip the REDEF and EQU-RELOC tests for the MSP430.
* gas/elf/section2.e-msp430: New file.
* gas/lns/lns-big-delta.d: Remove expectation of 20-bit
addresses.
* gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430.
* gas/msp430/msp430x.s: New test.
* gas/msp430/msp430x.d: Expected disassembly.
* gas/msp430/msp430.exp: Run new test.
* gas/msp430/opcode.d: Update expected disassembly.
* msp430.h: Add MSP430X relocs.
Add some more MSP430 machine numbers.
Add values used by .MSP430.attributes section.
* msp430.h: Add patterns for MSP430X instructions.
* Makefile.am: Add emsp430X.c
* Makefine.in: Regenerate.
* configure.tgt (msp430): Add msp430X emulation.
* ldmain.c (multiple_definition): Only disable relaxation if it
was enabled by the user.
* ldmain.h (RELAXATION_ENABLED_BY_USER): New macro.
* emulparams/msp430all.sh: Add support for MSP430X.
* emultempl/generic.em: (before_parse): Enable relaxation for the
MSP430.
* scripttempl/msp430.sc: Reorganize sections. Add .rodata
section.
* scripttempl/msp430_3.sc: Likewise.
* NEWS: Mention support for MSP430X.
* ld-elf/flags1.d: Expect this test to pass on the MSP430.
* ld-elf/init-fini-arrays.d: Expect this test to fail on the
MSP430.
* ld-elf/merge.d: Expect this test to pass on the MSP430.
* ld-elf/sec64k.exp: Skip these tests for the MSP430.
* ld-gc/pr13683.d: Expect this test to fail on the MSP430.
* ld-srec/srec.exp: Expect these tests to fail on the MSP430.
* ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to
fail on the MSP430.
* msp430-dis.c: Add support for MSP430X instructions.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* v850.h (V850_INVERSE_PCREL): Define.
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
destination address by subtracting the operand from the current
address.
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
a positive value in the insn.
(extract_u16_loop): Do not negate the returned value.
(D16_LOOP): Add V850_INVERSE_PCREL flag.
(ceilf.sw): Remove duplicate entry.
(cvtf.hs): New entry.
(cvtf.sh): Likewise.
(fmaf.s): Likewise.
(fmsf.s): Likewise.
(fnmaf.s): Likewise.
(fnmsf.s): Likewise.
(maddf.s): Restrict to E3V5 architectures.
(msubf.s): Likewise.
(nmaddf.s): Likewise.
(nmsubf.s): Likewise.
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
* elf.c (elfcore_write_s390_tdb): New function.
(elfcore_write_register_note): Call it.
(elfcore_grok_s390_tdb): New function.
(elfcore_grok_note): Call it.
* readelf.c (get_note_type): Add NT_S390_TDB.
to the plugin API. This patch helps preventing problems while
cherry-picking plugin-api.h changes from trunk gold to local branches.
For instance, a linker plugin compiled with a cherry-picked
plugin-api.h header with some enum values missing will behave
strangely when used with a linker built with the up to date header.
* plugin-api.h (enum ld_plugin_level): Assign integers
explicitly for all values.
* tic6x-opcode-table.h: Fix encoding of BNOP instruction.
* gas/tic6x/insns-c674x-pcrel.s: Add test of BNOP instruction
within header based fetch packet.
* gas/tic6x/insns-c674x-pcrel.d: Update expected disassembly.
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
opcodes/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
AARCH64_MOD_LSL, move the range check on the shift amount before the
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
gas/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Change to output
the out-of-range error message as value-expected message if there is
only one single value in the expected range.
(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
LSL #0 as a programmer-friendly feature.
gas/testsuite/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/movi.s: Add tests.
* gas/aarch64/movi.d: Update.
* gas/aarch64/programmer-friendly.s: Add comment.
* metag.h: New file.
* dis-asm.h (print_insn_metag): New declaration.
* metag.h: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.in: Add Meta.
* disassemble.c: Add Meta support.
* metag-dis.c: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* archures.c (bfd_mach_metag): New.
* bfd-in2.h: Regenerate.
* config.bfd: Add Meta.
* configure: Regenerate.
* configure.in: Add Meta.
* cpu-metag.c: New file.
* elf-bfd.h: Add Meta.
* elf32-metag.c: New file.
* elf32-metag.h: New file.
* libbfd.h: Regenerate.
* reloc.c: Add Meta relocations.
* targets.c: Add Meta.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* config/tc-metag.c: New file.
* config/tc-metag.h: New file.
* configure.tgt: Add Meta.
* doc/Makefile.am: Add Meta.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add Meta.
* doc/as.texiinfo: Document Meta options.
* doc/c-metag.texi: New file.
* gas/metag/labelarithmetic.d: New file.
* gas/metag/labelarithmetic.s: New file.
* gas/metag/metacore12.d: New file.
* gas/metag/metacore12.s: New file.
* gas/metag/metacore21-invalid.l: New file.
* gas/metag/metacore21-invalid.s: New file.
* gas/metag/metacore21.d: New file.
* gas/metag/metacore21.s: New file.
* gas/metag/metacore21ext.d: New file.
* gas/metag/metacore21ext.s: New file.
* gas/metag/metadsp21-invalid.l: New file.
* gas/metag/metadsp21-invalid.s: New file.
* gas/metag/metadsp21.d: New file.
* gas/metag/metadsp21.s: New file.
* gas/metag/metadsp21ext.d: New file.
* gas/metag/metadsp21ext.s: New file.
* gas/metag/metafpu21.d: New file.
* gas/metag/metafpu21.s: New file.
* gas/metag/metafpu21ext.d: New file.
* gas/metag/metafpu21ext.s: New file.
* gas/metag/metag.exp: New file.
* gas/metag/tls.d: New file.
* gas/metag/tls.s: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure.tgt: Add Meta.
* emulparams/elf32metag.sh: New file.
* emultempl/metagelf.em: New file.
* ld-elf/merge.d: Mark Meta as xfail.
* ld-gc/start.d: Skip this test on Meta.
* ld-gc/personality.d: Skip this test on Meta.
* ld-metag/external.s: New file.
* ld-metag/metag.exp: New file.
* ld-metag/pcrel.d: New file.
* ld-metag/pcrel.s: New file.
* ld-metag/shared.d: New file.
* ld-metag/shared.r: New file.
* ld-metag/shared.s: New file.
* ld-metag/stub.d: New file.
* ld-metag/stub.s: New file.
* ld-metag/stub_pic_app.d: New file.
* ld-metag/stub_pic_app.r: New file.
* ld-metag/stub_pic_app.s: New file.
* ld-metag/stub_pic_shared.d: New file.
* ld-metag/stub_pic_shared.s: New file.
* ld-metag/stub_shared.d: New file.
* ld-metag/stub_shared.r: New file.
* ld-metag/stub_shared.s: New file.
* binutils/readelf.c: (guess_is_rela): Add EM_METAG.
(dump_relocations): Add EM_METAG.
(get_machine_name): Correct case for Meta.
(is_32bit_abs_reloc): Add support for Meta ADDR32 reloc.
(is_none_reloc): Add support for Meta NONE reloc.
* bfd-in2.h: Add support for MIPS r5900
* config.bfd: Add support for Sony Playstation 2
* cpu-mips.c: Add support for MIPS r5900
* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000)
* config/tc-mips.c: Add support for MIPS r5900
Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq.
* config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot.
* config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900.
* config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
* config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900.
* configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu).
* config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900.
* elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software.
* opcode/mips.h: Add support for r5900 instructions including lq and sq.
* configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk).
* emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32.
* emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32.
* Makefile.am: Add linker scripts for Sony Playstation 2 ELF files.
* opcodes/mips-dis.c: Add names for CP0 registers of r5900.
* opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq.
* opcodes/mips-opc.c: Add support for MIPS r5900 CPU.
Add support for 128 bit MMI (Multimedia Instructions).
Add support for EE instructions (Emotion Engine).
Disable unsupported floating point instructions (64 bit and undefined compare operations).
Enable instructions of MIPS ISA IV which are supported by r5900.
Disable 64 bit co processor instructions.
Disable 64 bit multiplication and division instructions.
Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)).
Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900.
Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
* elf32-rx.c (describe_flags): New function. Returns a buffer
containing a description of the E_FLAG_RX_... values set.
(rx_elf_merge_private_bfd_data): Use it.
(rx_elf_print_private_bfd_data): Likewise.
(elf32_rx_machine): Skip EF_RX_CPU_RX check.
(elf32_rx_special_sections): Define.
(elf_backend_special_sections): Define.
2012-11-09 Nick Clifton <nickc@redhat.com>
* readelf.c (get_machine_flags): Add support for E_FLAG_RX_ABI.
2012-11-09 Nick Clifton <nickc@redhat.com>
* config/obj-elf.c (obj_elf_change_section): Allow init array
sections to have the SHF_EXECINSTR attribute for the RX target.
* config/tc-rx.c (elf_flags): Initialise with E_FLAG_RX_ABI.
(enum options): Add OPTION_USES_GCC_ABI and OPTION_USES_RX_ABI.
(md_longopts): Add -mgcc-abi and -mrx-abi.
(md_parse_option): Add support for OPTION_USES_GCC_ABI and
OPTION_USES_RX_ABI.
* doc/as.texinfo (RX Options): Add mention of remaining RX
options.
* doc/c-rx.texi: Document -mgcc-abi and -mrx-abi.
2012-11-09 Nick Clifton <nickc@redhat.com>
* rx.h (EF_RX_CPU_RX): Add comment.
(E_FLAG_RX_ABI): Define.
2012-11-09 Nick Clifton <nickc@redhat.com>
* emultempl/rxelf.em (no_flag_mismatch_warnings): Initialise to
true.
(PARSE_AND_LIST_LONGOPTS): Add flag-mismatch-warnings.
(PARSE_AND_LIST_ARG_CASES): Add support for
--flag-mismatch-warnings.
* elf32-arm.c (elf32_arm_print_private_bfd_data): Recognise and
display the new ARM hard-float/soft-float ABI flags for EABI_VER5
(elf32_arm_post_process_headers): Add the hard-float/soft-float
ABI flag as appropriate for ET_DYN/ET_EXEC in EABI_VER5.
binutils:
* readelf.c (decode_ARM_machine_flags): Recognise and display the
new ARM hard-float/soft-float ABI flags for EABI_VER5. Split out
the code for EABI_VER4 and EABI_VER5 to allow this.
elfcpp:
* arm.h: New enum for EABI soft- and hard-float flags.
gold:
* gold.cc (Target_arm::do_adjust_elf_header): Add the
hard-float/soft-float ABI flag as appropriate for ET_DYN/ET_EXEC
in EABI_VER5.
include:
* elf/arm.h (EF_ARM_ABI_FLOAT_SOFT): New define.
(EF_ARM_ABI_FLOAT_HARD): Likewise.
ld/testsuite:
* ld-arm/eabi-hard-float.s: New test source.
* ld-arm/eabi-soft-float.s: New test source.
* ld-arm/eabi-hard-float.d: New test.
* ld-arm/eabi-soft-float.d: New test.
* ld-arm/eabi-soft-float-ABI4.d: New test.
* ld-arm/eabi-soft-float-r.d: New test.
* ld-arm/arm-elf.xp: Use the new tests.
binutils:
PR binutils/14779
* configure.in: Add checks for wchar.h and mbstate_t.
* config.in: Regenerate.
* configure: Regenerate.
* readelf.c: Conditionally include wchar.h.
(print_symbol): Conditionally use mbstate_t.
* config/tc-s390.c (s390_parse_cpu): Add new option zEC12.
* doc/as.texinfo: Document new option zEC12.
* doc/c-s390.texi: Likewise.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/s390.exp: Run zEC12 tests.
* gas/s390/zarch-zEC12.d: New file.
* gas/s390/zarch-zEC12.s: New file.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-mkopc.c: Support new option zEC12.
* s390-opc.c: Add new instruction formats.
* s390-opc.txt: Add new instructions for zEC12.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
bfd/
* bfd-in2.h: Regenerated.
* elf64-aarch64.c
(elf64_aarch64_howto_table): Add R_AARCH64_GOT_LD_PREL19 reloc to HOWTO.
(elf64_aarch64_reloc_map): Add reloc entry.
(aarch64_resolve_relocation): Likewise.
(bfd_elf_aarch64_put_addend): Likewise.
(aarch64_reloc_got_type): Likewise.
(elf64_aarch64_final_link_relocate): Likewise.
(lf64_aarch64_check_relocs): Likewise.
(elf64_aarch64_check_relocs): New case for R_AARCH64_ADR_PREL_LO21
reloc.
* libbfd.h: Regenerated.
* reloc.c (R_AARCH64_GOT_LD_PREL19): New reloc.
gas/
* config/tc-aarch64.c
(reloc_table): Add reloc to table entry.
(parse_address_main): Add support for #:<reloc_op>:<symbol>.
(parse_operands): Check for unused reloc.
(md_apply_fix): New case for reloc.
(aarch64_force_relocation): Likewise.
gas/testsuite
* gas/aarch64/reloc-insn.d
(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add expected asm for new reloc test.
* gas/aarch64/reloc-insn.s
(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add test for reloc.
include/
* elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc.
ld/testsuite
* ld-aarch64/aarch64-elf.exp: New reloc tests.
* ld-aarch64/emit-relocs-309-low-bad.d: New file. Expected asm for test
failure (lower bound overflow).
* ld-aarch64/emit-relocs-309-low.d: New file. Expected asm for test
success (lower bound).
* ld-aarch64/emit-relocs-309-up-bad.d: New file. Expected asm for test
failure (upper bound overflow).
* ld-aarch64/emit-relocs-309-up.d: New file. Expected asm for test
success (upper bound).
* ld-aarch64/emit-relocs-309.s: New file. Asm for new reloc tests.
bfd/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
(ext_cnt6a): Ditto.
(ins_strd5b): Ditto.
(ext_strd5b): Ditto.
(elf64_ia64_operands): Add new operand types.
gas/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* config/tc-ia64.c (reg_symbol): Add a new register.
(indirect_reg): Ditto.
(pseudo_func): Add new symbolic constants.
(operand_match): Add new operand types recognition.
(operand_insn): Add new register recognition.
(md_begin): Add new register definition.
(specify_resource): Add new register recognition.
gas/testsuite/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* gas/testsuite/gas/ia64/psn.d: New file.
* gas/testsuite/gas/ia64/psn.s: New file.
* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
* gas/testsuite/gas/ia64/opc-m.d: Ditto.
include/opcode/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
opcodes/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
* ia64-gen.c: Promote completer index type to longlong.
(irf_operand): Add new register recognition.
(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
(lookup_specifier): Add new resource recognition.
(insert_bit_table_ent): Relax abort condition according to the
changed completer index type.
(print_dis_table): Fix printf format for completer index.
* ia64-ic.tbl: Add a new instruction class.
* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
* ia64-opc.h: Define short names for new operand types.
* ia64-raw.tbl: Add new RAW resource for DAHR register.
* ia64-waw.tbl: Add new WAW resource for DAHR register.
* ia64-asmtab.c: Regenerate.
segments.
2012-08-24 Sriraman Tallam <tmsriram@google.com>
* gold.cc (queue_middle_tasks): Call layout again when unique
segments for sections is desired.
* layout.cc (Layout::Layout): Initialize new members.
(Layout::get_output_section_flags): New function.
(Layout::choose_output_section): Call get_output_section_flags.
(Layout::layout): Make output section for mapping to a unique segment.
(Layout::insert_section_segment_map): New function.
(Layout::attach_allocated_section_to_segment): Make unique segment for
output sections marked so.
(Layout::segment_precedes): Check for unique segments when sorting.
* layout.h (Layout::Unique_segment_info): New struct.
(Layout::Section_segment_map): New typedef.
(Layout::insert_section_segment_map): New function.
(Layout::get_output_section_flags): New function.
(Layout::is_unique_segment_for_sections_specified): New function.
(Layout::set_unique_segment_for_sections_specified): New function.
(Layout::unique_segment_for_sections_specified_): New member.
(Layout::section_segment_map_): New member.
* object.cc (Sized_relobj_file<size, big_endian>::do_layout):
Rename is_gc_pass_one to is_pass_one.
Rename is_gc_pass_two to is_pass_two.
Rename is_gc_or_icf to is_two_pass.
Check for which pass based on whether symbols data is present.
Make it two pass when unique segments for sections is desired.
* output.cc (Output_section::Output_section): Initialize new
members.
* output.h (Output_section::is_unique_segment): New function.
(Output_section::set_is_unique_segment): New function.
(Output_section::is_unique_segment_): New member.
(Output_section::extra_segment_flags): New function.
(Output_section::set_extra_segment_flags): New function.
(Output_section::extra_segment_flags_): New member.
(Output_section::segment_alignment): New function.
(Output_section::set_segment_alignment): New function.
(Output_section::segment_alignment_): New member.
(Output_segment::Output_segment): Initialize is_unique_segment_.
(Output_segment::is_unique_segment): New function.
(Output_segment::set_is_unique_segment): New function.
(Output_segment::is_unique_segment_): New member.
* plugin.cc (allow_unique_segment_for_sections): New function.
(unique_segment_for_sections): New function.
(Plugin::load): Add new functions to transfer vector.
* Makefile.am (plugin_final_layout.readelf.stdout): Add readelf output.
* Makefile.in: Regenerate.
* testsuite/plugin_final_layout.sh: Check if unique segment
functionality works.
* testsuite/plugin_section_order.c (onload): Check if new interfaces
are available.
(allow_unique_segment_for_sections): New global.
(unique_segment_for_sections): New global.
(claim_file_hook): Call allow_unique_segment_for_sections.
(all_symbols_read_hook): Call unique_segment_for_sections.
2012-08-24 Sriraman Tallam <tmsriram@google.com>
* plugin-api.h (ld_plugin_allow_unique_segment_for_sections):
New interface.
(ld_plugin_unique_segment_for_sections): New interface.
(LDPT_ALLOW_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val.
(LDPT_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val.
(tv_allow_unique_segment_for_sections): New member.
(tv_unique_segment_for_sections): New member.
* elf64-s390.c: Include elf-s390-common.c.
(R_390_IRELATIVE): New reloc.
(elf_s390_reloc_type_lookup): Support R_390_IRELATIVE.
(RELA_ENTRY_SIZE): New macro.
(elf_s390_link_hash_entry): New fields ifunc_resolver_address and
*ifunc_resolver_section.
(struct plt_entry): New struct.
(struct elf_s390_obj_tdata): New field local_plt.
(elf_s390_local_plt): New macro.
(struct elf_s390_link_hash_table): New field irelifunc.
(ELF64): New macro.
(link_hash_newfunc): Initialize new fields.
(elf_s390_check_relocs): Handle IFUNC symbols.
(elf_s390_adjust_dynamic_symbol): Don't do anything for IFUNC
symbols.
(allocate_dynrelocs): Call s390_elf_allocate_ifunc_dyn_relocs for
IFUNC symbols.
(elf_s390_size_dynamic_sections): Handle IFUNC symbols.
(elf_s390_relocate_section): Likewise.
(elf_s390_finish_dynamic_symbol): Likewise.
(elf_s390_finish_dynamic_sections): Handle local IFUNC symbols.
(elf_s390_finish_ifunc_symbol): New function.
(elf_s390_gc_sweep_hook): Handle local plt entries.
(elf_backend_add_symbol_hook): Define.
* elf32-s390.c: See elf64-s390.c changes.
* elf-s390-common.c: New file.
* bfd-in2.h (BFD_RELOC_390_IRELATIVE): New enum field.
* libbfd.h (BFD_RELOC_390_IRELATIVE): New entry for
BFD_RELOC_390_IRELATIVE.
* reloc.c (BFD_RELOC_390_IRELATIVE): Document new relocation.
2012-07-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* elf/s390.h (START_RELOC_NUMBERS): Define R_390_IRELATIVE reloc.
2012-07-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* emulparams/elf_s390.sh (IREL_IN_PLT): Define.
* emulparams/elf64_s390.sh (IREL_IN_PLT): Define.
* tc-xgate.c: Revised assembler so that operands
are collected before the addressing mode is
determined.
include/opcode/
* xgate.h: Changed the format string for mode
XGATE_OP_DYA_MON.
opcodes/
* xgate-dis.c: Removed an IF statement that will
always be false due to overlapping operand masks.
* xgate-opc.c: Corrected 'com' opcode entry and
fixed spacing.
* NEWS: Document additions to .gdb_index.
* dwarf2read.c: #include "gdb/gdb-index.h".
(DW2_GDB_INDEX_SYMBOL_STATIC_SET_VALUE): New macro.
(DW2_GDB_INDEX_SYMBOL_KIND_SET_VALUE): New macro.
(DW2_GDB_INDEX_CU_SET_VALUE): New macro.
(dwarf2_read_index): Recognize version 7.
(dw2_do_expand_symtabs_matching): New args want_specific_block,
block_kind, domain): All callers updated.
(dw2_find_symbol_file): Handle new index CU values.
(dw2_expand_symtabs_matching): Match symbol kind if requested.
(add_index_entry): New args is_static, kind. All callers updated.
(offset_type_compare, uniquify_cu_indices): New functions
(symbol_kind): New function.
(write_psymtabs_to_index): Remove duplicate CU values.
(write_psymtabs_to_index): Write .gdb_index version 7.
doc/
* gdb.texinfo (Index Section Format): Document version 7 format.
include/gdb/
* gdb-index.h: New file.
(read_uleb128_to_uint64): Renamed from read_uleb128_to_ull.
Change to take a uint64_t * argument instead of unsigned long long.
(read_sleb128_to_uint64): Renamed from read_sleb128_to_ll.
Change to take an int64_t * argument instead of long long.
* reloc.c: Add new ENUM for BFD_RELOC_AVR_8_LO,
BFD_RELOC_AVR_8_HI, BFD_RELOC_AVR_8_HHI.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenrate.
* elf32-avr.c (elf_avr_howto_table): Add entries for
R_AVR_8_LO8, R_AVR_8_HI8, R_AVR_8_HHI8.
(avr_reloc_map): Add RELOC mappings for R_AVR_8_LO8, R_AVR_8_HI8,
R_AVR_8_HHI8.
* config/tc-avr.c (exp_mod_pm): Remove variable.
(exp_mod_data_t): New typedef.
(pexp_mod_data, exp_mod_data): New variables.
(avr_parse_cons_expression): Scan through exp_mod_data[] to find
data expression modifiers "pm", "gs", "lo8", hi8", "hhi8", "hh8"
and set pexp_mod_data accordingly to be used in avr_cons_fix_new.
(avr_cons_fix_new): Handle new data expression modifiers shipped
in pexp_mod_data.
(md_apply_fix): Handle BFD_RELOC_AVR_8_LO, BFD_RELOC_AVR_8_HI,
BFD_RELOC_AVR_8_HHI.
* elf/avr.h (RELOC_NUMBERS): Add values for R_AVR_8_LO8,
R_AVR_8_HI8, R_AVR_8_HHI8.
The common sim code has slightly unfinished support for these already,
but even arch ports are unable to handle these if the common header does
not define them. This is because the generated callback header includes
simple common gdb/sim headers only which causes it to skip the new ARGV
syscalls. Plus, it isn't like providing these in the common header will
break any sim targets which don't want them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* elf.c (_bfd_elf_map_sections_to_segments): Set INFO->user_phdrs.
* elf-nacl.c (nacl_modify_segment_map): Do nothing if INFO->user_phdrs.
(nacl_modify_program_headers): Likewise.
include/
* bfdlink.h (struct bfd_link_info): Add new member user_phdrs.
* config/tc-crx.c: Include bfd_stdint.h.
(getconstant): Remove irrelevant comment. Don't fail due to
sign-extension of int mask.
(check_range): Rewrite using unsigned arithmetic throughout.
opcodes/
* crx-dis.c (print_arg): Mask constant to 32 bits.
* crx-opc.c (cst4_map): Use int array.
include/opcode/
* crx.h (cst4_map): Update declaration.
BFD:
* mach-o.c (bfd_mach_o_swap_in_non_scattered_reloc): New.
(bfd_mach_o_canonicalize_one_reloc): Swap non-scattered reloc
bit-fields when target and host differ in endian-ness. When
PAIRs are non-scattered find the 'symbol' from the preceding
reloc. Add FIXME re. reloc symbols on section boundaries.
(bfd_mach_o_swap_out_non_scattered_reloc): New.
(bfd_mach_o_write_relocs): Use bfd_mach_o_encode_non_scattered_reloc.
include/mach-o:
* external.h: Add comments about relocations fields. Add macros
for non-scattered relocations. Move scattered relocation macros to here.
* reloc.h: Remove macros related to external representation of reloc fields.
* elf32-rl78.c (rl78_elf_howto_table): Add R_RL78_RH_RELAX.
(rl78_reloc_map): Add BFD_RELOC_RL78_RELAX.
(rl78_elf_relocate_section): Add R_RL78_RH_RELAX, R_RL78_RH_SFR,
and R_RL78_RH_SADDR.
(rl78_elf_finish_dynamic_sections): Only validate PLT section if
we didn't relax anything, as relaxing might remove a PLT reference
after we've set up the table.
(elf32_rl78_relax_delete_bytes): New.
(reloc_bubblesort): New.
(rl78_offset_for_reloc): New.
(relax_addr16): New.
(rl78_elf_relax_section): Add support for relaxing long
instructions into short ones.
[gas]
* config/rl78-defs.h (rl78_linkrelax_addr16): Add.
(rl78_linkrelax_dsp, rl78_linkrelax_imm): Remove.
* config/rl78-parse.y: Tag all addr16 and branch patterns with
relaxation markers.
* config/tc-rl78.c (rl78_linkrelax_addr16): New.
(rl78_linkrelax_branch): New.
(OPTION_RELAX): New.
(md_longopts): Add relax option.
(md_parse_option): Add OPTION_RELAX.
(rl78_frag_init): Support relaxation.
(rl78_handle_align): New.
(md_assemble): Support relaxation.
(md_apply_fix): Likewise.
(md_convert_frag): Likewise.
* config/tc-rl78.h (MAX_MEM_FOR_RS_ALIGN_CODE): New.
(HANDLE_ALIGN): New.
(rl78_handle_align): Declare.
* config/rl78-parse.y (rl78_bit_insn): New. Set it for all bit
insn patterns.
(find_bit_index): New. Strip .BIT suffix off relevent
expressions for bit insns.
(rl78_lex): Exclude bit suffixes from expression parsing.
[include/elf]
* rl78.h (R_RL78_RH_RELAX, R_RL78_RH_SFR, R_RL78_RH_SADDR): New.
(RL78_RELAXA_BRA, RL78_RELAXA_ADDR16: New.
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* archures.c (bfd_mach_mips_octeon2): New macro
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsocteon2): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeon2.
* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
(mips_mach_extensions): Add bfd_mach_mips_octeon2.
gas:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
(mips_cpu_info_table): Add Octeon2.
* doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.
gas/testsuite:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips.exp: Add Octeon2 for an architecture.
Run octeon2 test.
* gas/mips/octeon2.d: New file.
* gas/mips/octeon2.s: New file.
include/opcode:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
(CPU_OCTEON2): New macro.
(OPCODE_IS_MEMBER): Add Octeon2.
opcodes:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add Octeon2.
For "octeon+", just include OcteonP for the insn.
* mips-opc.c (IOCT): Include Octeon2.
(IOCTP): Include Octeon2.
(IOCT2): New macro.
(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
loads are, and add IOCT2 to them.
Add "lbx" and "lhux".
Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
Add "zcb" and "zcbt".
The common sim code provides a useful "get_string" function which reads
a C string out of the target's memory space. So rename and export it
for other people to use.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (INSN_TRAP): Rename to...
(INSN_NO_DELAY_SLOT): ... this.
(INSN_SYNC): Remove macro.
gas/
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
INSN_TRAP to INSN_NO_DELAY_SLOT. Remove the check for INSN_SYNC
as well as explicit checks for ERET and DERET when scheduling
branch delay slots.
opcodes/
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(DSP_VOLA): Likewise.
(mips_builtin_opcodes): Add NODS annotation to "deret" and
"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
place of TRAP for "wait", "waiti" and "yield".
* mips16-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
"restore" and "save".
* plugin-api.h
(ld_plugin_section): New struct.
(ld_plugin_get_section_count): New typedef.
(ld_plugin_get_section_type): New typedef.
(ld_plugin_get_section_name): New typedef.
(ld_plugin_get_section_contents): New typedef.
(ld_plugin_update_section_order): New typedef.
(ld_plugin_allow_section_ordering): New typedef.
(LDPT_GET_SECTION_COUNT): New enum value.
(LDPT_GET_SECTION_TYPE): New enum value.
(LDPT_GET_SECTION_NAME): New enum value.
(LDPT_GET_SECTION_CONTENTS): New enum value.
(LDPT_UPDATE_SECTION_ORDER): New enum value.
(LDPT_ALLOW_SECTION_ORDERING): New enum value.
(tv_get_section_count): New struct members.
(tv_get_section_type): New struct members.
(tv_get_section_name): New struct members.
(tv_get_section_contents): New struct members.
(tv_update_section_order): New struct members.
(tv_allow_section_ordering): New struct members.
* archive.cc (Archive::get_elf_object_for_member): Add extra parameter
to claim_file call.
* layout.cc (Layout::Layout): Initialize section_ordering_specified_,
input_section_position_, and input_section_glob_.
(read_layout_from_file): Call function section_ordering_specified.
* layout.h (is_section_ordering_specified): New function.
(section_ordering_specified): New function.
(section_ordering_specified_): New boolean member.
* main.cc(main): Call load_plugins after layout object is defined.
* output.cc (Output_section::add_input_section): Use
function section_ordering_specified to check if section ordering is
needed.
* output.cc (Output_section::add_relaxed_input_section): Use
function section_ordering_specified to check if section ordering is
needed.
(Output_section::update_section_layout): New function.
(Output_section::sort_attached_input_sections): Check if input section
must be reordered.
* output.h (Output_section::update_section_layout): New function.
* plugin.cc (get_section_count): New function.
(get_section_type): New function.
(get_section_name): New function.
(get_section_contents): New function.
(update_section_order): New function.
(allow_section_ordering): New function.
(Plugin::load): Add the new interfaces to the transfer vector.
(Plugin_manager::load_plugins): New parameter.
(Plugin_manager::all_symbols_read): New parameter.
(Plugin_manager::claim_file): New parameter. Save the elf object for
unclaimed objects.
(Plugin_manager::get_elf_object): New function.
(Plugin_manager::get_view): Change to directly use the bool to check
if get_view is called from claim_file_hook.
* plugin.h (input_objects): New function
(Plugin__manager::load_plugins): New parameter.
(Plugin_manager::claim_file): New parameter.
(Plugin_manager::get_elf_object): New function.
(Plugin_manager::in_claim_file_handler): New function.
(Plugin_manager::in_claim_file_handler_): New member.
(layout): New function.
* readsyms.cc (Read_symbols::do_read_symbols): Call the claim_file
handler with an extra parameter. Make the elf object before calling
claim_file handler.
* testsuite/plugin_test.c (get_section_count): New function pointer.
(get_section_type): New function pointer.
(get_section_name): New function pointer.
(get_section_contents): New function pointer.
(update_section_order): New function pointer.
(allow_section_ordering): New function pointer.
(onload): Check if the new interfaces exist.
2011-07-06 Tristan Gingold <gingold@adacore.com>
* mach-o.h: Move loader related definitions to
include/mach-o/loader.h. Include it.
include/mach-o/
2011-07-06 Tristan Gingold <gingold@adacore.com>
* loader.h: New file.
include/ChangeLog:
* filenames.h (HAVE_CASE_INSENSITIVE_FILE_SYSTEM): Define
on Darwin, as well as on the systems that use a DOS-like
filesystem.
libiberty/ChangeLog:
* filename_cmp.c (filename_cmp, filename_ncmp): Add handling of
HAVE_CASE_INSENSITIVE_FILE_SYSTEM.
* dwarf.c (decode_location_expression): For DW_OP_GNU_convert and
DW_OP_GNU_reinterpret, if uvalue is 0, don't add cu_offset.
Handle DW_OP_GNU_parameter_ref.
After testing the hardware with all the different dsp flags, the MM flag
triggers sign extension in all modes. So drop the limited use of it, and
the local custom helper that was also extending unsigned values. We also
can see that the flag checks in the mult/mac insns have the same behavior
with sign extending, so add a helper func to keep the logic the same in
both places.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
bfd/
* elf32-arm.c (elf32_arm_final_link_relocate): Only do bl conversion
for known functions.
(elf32_arm_swap_symbol_in): Only set ST_BRANCH_TO_ARM for function
symbols.
include/elf/
* arm.h (arm_st_branch_type): Add ST_BRANCH_UNKNOWN.
ld/testsuite/
* ld-arm/cortex-a8-far.d: Adjust expected output.
* ld-arm/arm-call1.s: Give function symbol correct type.
* ld-arm/arm-call2.s: Ditto.
* ld-arm/farcall-group4.s: Ditto.
* ld-arm/arm-elf.exp (cortex-a8-far): Define far symbols with correct
type via assembly file.
* ld-arm/cortex-a8-far-3.s: New file.
* ld-arm/abs-call-1.s: Add Thumb tests
PR ld/12696
include/
* bfdlink.h (ENUM_BITFIELD): Define.
(struct bfd_link_hash_entry): Make "type" a bitfield. Add "non_ir_ref".
(struct bfd_link_callbacks <notice>): Pass bfd_link_hash_entry pointer
rather than "name".
bfd/
* coff-aux.c (coff_m68k_aux_link_add_one_symbol): Update "notice" call.
* linker.c (_bfd_link_hash_newfunc): Clear bitfields.
(_bfd_generic_link_add_one_symbol): Update "notice" call.
* elflink.c (_bfd_elf_merge_symbol): Don't skip weak redefs when
it is a redef of an IR symbol in a real BFD.
ld/
* ldmain.c (notice): Delete "name" param, add "h".
* plugin.c (plugin_notice): Likewise. Set non_ir_ref. Handle
redefinitions of IR symbols in real BFDs.
(plugin_multiple_definition, plugin_multiple_common): Delete.
(non_ironly_hash, init_non_ironly_hash): Delete.
(is_visible_from_outside): Traverse entry_symbol chain.
(get_symbols): Use non_ir_ref flag rather than hash lookup.
For now, only the sub-command name is completed. No support yet for
completing options to that command. But even this is a huge step as
currently, nothing is completed, and the basic "help sim" is fairly
obtuse as to what exactly the "sim" command accepts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* tic6x.h (R_C6000_JUMP_SPLOT, R_C6000_EHTYPE,
R_C6000_PCR_H16, R_C6000_PCR_L16): New relocs.
(SHN_TIC6X_SCOMMON): Define.
bfd/
* elf32-tic6x.h (struct elf32_tic6x_params): New.
(elf32_tic6x_setup): Declare.
* elf32-tic6x.c: Include <limits.h>.
(ELF_DYNAMIC_LINKER, DEFAULT_STACK_SIZE, PLT_ENTRY_SIZE): Define.
(struct elf32_tic6x_link_hash_table, struct elf32_link_hash_entry):
New structures.
(elf32_tic6x_link_hash_table, is_tic6x_elf): New macros.
(tic6x_elf_scom_section, tic6x_elf_scom_symbol,
tic6x_elf_scom_symbol_ptr): New static variables.
(elf32_tic6x_howto_table, elf32_tic6x_howto_table_rel,
elf32_tic6x_reloc_map): Add R_C6000_JUMP_SLOT, R_C6000_EHTYPE,
R_C6000_PCR_H16 and R_C6000_PCR_L16.
(elf32_tic6x_link_hash_newfunc, elf32_tic6x_link_hash_table_create,
elf32_tic6x_link_hash_table_free, elf32_tic6x_setup,
elf32_tic6x_using_dsbt, elf32_tic6x_install_rela,
elf32_tic6x_create_dynamic_sections, elf32_tic6x_make_got_dynreloc,
elf32_tic6x_finish_dynamic_symbol, elf32_tic6x_gc_sweep_hook,
elf32_tic6x_adjust_dynamic_symbol): New static functions.
(elf32_tic6x_relocate_section): For R_C6000_PCR_S21, convert branches
to weak symbols as required by the ABI.
Handle GOT and DSBT_INDEX relocs, and copy relocs to the output file
as needed when generating DSBT output.
(elf32_tic6x_check_relocs, elf32_tic6x_add_symbol_hook,
elf32_tic6x_symbol_processing, elf32_tic6x_section_from_bfd_section,
elf32_tic6x_allocate_dynrelocs, elf32_tic6x_size_dynamic_sections,
elf32_tic6x_always_size_sections, elf32_tic6x_modify_program_headers,
elf32_tic6x_finish_dynamic_sections, elf32_tic6x_plt_sym_val,
elf32_tic6x_copy_private_data, elf32_tic6x_link_omit_section_dynsym):
New static functions.
(ELF_MAXPAGESIZE): Define to 0x1000.
(bfd_elf32_bfd_copy_private_bfd_data,
bfd_elf32_bfd_link_hash_table_create,
bfd_elf32_bfd_link_hash_table_free, elf_backend_can_refcount,
elf_backend_want_got_plt, elf_backend_want_dynbss,
elf_backend_plt_readonly, elf_backend_got_header_size,
elf_backend_gc_sweep_hook, elf_backend_modify_program_headers,
elf_backend_create_dynamic_sections, elf_backend_adjust_dynamic_symbol,
elf_backend_check_relocs, elf_backend_add_symbol_hook,
elf_backend_symbol_processing, elf_backend_link_output_symbol_hook,
elf_backend_section_from_bfd_section,
elf_backend_finish_dynamic_symbol, elf_backend_always_size_sections,
elf32_tic6x_size_dynamic_sections, elf_backend_finish_dynamic_sections,
elf_backend_omit_section_dynsym, elf_backend_plt_sym_val): Define.
* bfd/reloc.c (BFD_RELOC_C6000_JUMP_SLOT, BFD_RELOC_C6000_EHTYPE,
BFD_RELOC_C6000_PCR_H16, BFD_RELOC_C6000_PCR_S16): Add.
* bfd/bfd-in2.h: Regenerate.
* bfd/libbfd.h: Regenerate.
* config.bfd: Accept tic6x-*-* instead of tic6x-*-elf.
gas/
* config/tc-tic6x.c (sbss_section, scom_section, scom_symbol): New
static variables.
(md_begin): Initialize them.
(s_tic6x_scomm): New static function.
(md_pseudo_table): Add "scomm".
(tc_gen_reloc): Really undo all adjustments made by
bfd_install_relocation.
* doc/c-tic6x.texi: Document the .scomm directive.
gas/testsuite/
* gas/tic6x/scomm-directive-1.s: New test.
* gas/tic6x/scomm-directive-1.d: New test.
* gas/tic6x/scomm-directive-2.s: New test.
* gas/tic6x/scomm-directive-2.d: New test.
* gas/tic6x/scomm-directive-3.s: New test.
* gas/tic6x/scomm-directive-3.d: New test.
* gas/tic6x/scomm-directive-4.s: New test.
* gas/tic6x/scomm-directive-4.d: New test.
* gas/tic6x/scomm-directive-5.s: New test.
* gas/tic6x/scomm-directive-5.d: New test.
* gas/tic6x/scomm-directive-6.s: New test.
* gas/tic6x/scomm-directive-6.d: New test.
* gas/tic6x/scomm-directive-7.s: New test.
* gas/tic6x/scomm-directive-7.d: New test.
* gas/tic6x/scomm-directive-8.s: New test.
* gas/tic6x/scomm-directive-8.d: New test.
ld/
* emulparams/elf32_tic6x_le.sh (BIG_OUTPUT_FORMAT, EXTRA_EM_FILE,
GENERATE_SHLIB_SCRIPT): New defines.
(TEXT_START_ADDR): Define differently depending on target.
(.got): Redefine to include "*(.dsbt)".
(SDATA_START_SYMBOLS): Remove, replace with
(OTHER_GOT_SYMBOLS): New.
(OTHER_BSS_SECTIONS): Define only for ELF targets.
* emultempl/tic6xdsbt.em: New file.
* gen-doc.texi: Set C6X.
* ld.texinfo: Likewise.
(Options specific to C6X uClinux targets): New section.
binutils/
* readelf.c (get_symbol_index_type): Handle SCOM for TIC6X.
(dump_relocations): Likewise.
binutils/testsuite/
* lib/binutils-common.exp (is_elf_format): Accept tic6x*-*-uclinux*.
ld/testsuite/
* ld-scripts/crossref.exp: Add CFLAGS for tic6x*-*-*.
* ld-elf/sec-to-seg.exp: Remove tic6x from list of targets defining
pagesize to 1.
* ld-tic6x/tic6x.exp: Add support for DSBT shared library/executable
linking tests.
* ld-tic6x/dsbt.ld: New linker script.
* ld-tic6x/dsbt-be.ld: New linker script.
* ld-tic6x/dsbt-overflow.ld: New linker script.
* ld-tic6x/dsbt-inrange.ld: New linker script.
* ld-tic6x/shlib-1.s: New test.
* ld-tic6x/shlib-2.s: New test.
* ld-tic6x/shlib-app-1r.s: New test.
* ld-tic6x/shlib-app-1.s: New test.
* ld-tic6x/shlib-1.sd: New test.
* ld-tic6x/shlib-1.dd: New test.
* ld-tic6x/shlib-app-1.rd: New test.
* ld-tic6x/shlib-app-1rb.rd: New test.
* ld-tic6x/shlib-app-1.sd: New test.
* ld-tic6x/static-app-1rb.od: New test.
* ld-tic6x/shlib-app-1.dd: New test.
* ld-tic6x/shlib-app-1rb.sd: New test.
* ld-tic6x/static-app-1b.od: New test.
* ld-tic6x/static-app-1r.od: New test.
* ld-tic6x/shlib-1rb.rd: New test.
* ld-tic6x/shlib-app-1rb.dd: New test.
* ld-tic6x/shlib-1rb.sd: New test.
* ld-tic6x/shlib-1rb.dd: New test.
* ld-tic6x/shlib-app-1b.od: New test.
* ld-tic6x/tic6x.exp: New test.
* ld-tic6x/static-app-1rb.rd: New test.
* ld-tic6x/shlib-app-1r.od: New test.
* ld-tic6x/static-app-1.od: New test.
* ld-tic6x/static-app-1b.rd: New test.
* ld-tic6x/static-app-1r.rd: New test.
* ld-tic6x/static-app-1rb.sd: New test.
* ld-tic6x/static-app-1b.sd: New test.
* ld-tic6x/static-app-1rb.dd: New test.
* ld-tic6x/static-app-1r.sd: New test.
* ld-tic6x/static-app-1b.dd: New test.
* ld-tic6x/shlib-1b.rd: New test.
* ld-tic6x/static-app-1r.dd: New test.
* ld-tic6x/shlib-app-1b.rd: New test.
* ld-tic6x/shlib-1r.rd: New test.
* ld-tic6x/shlib-app-1r.rd: New test.
* ld-tic6x/shlib-1b.sd: New test.
* ld-tic6x/static-app-1.rd: New test.
* ld-tic6x/shlib-app-1b.sd: New test.
* ld-tic6x/shlib-1r.sd: New test.
* ld-tic6x/shlib-1b.dd: New test.
* ld-tic6x/shlib-app-1r.sd: New test.
* ld-tic6x/shlib-app-1b.dd: New test.
* ld-tic6x/shlib-1r.dd: New test.
* ld-tic6x/static-app-1.sd: New test.
* ld-tic6x/shlib-app-1r.dd: New test.
* ld-tic6x/static-app-1.dd: New test.
* ld-tic6x/shlib-noindex.rd: New test.
* ld-tic6x/shlib-noindex.dd: New test.
* ld-tic6x/shlib-noindex.sd: New test.
* ld-tic6x/got-reloc-local-1.s: New test.
* ld-tic6x/got-reloc-local-2.s: New test.
* ld-tic6x/got-reloc-local-r.d: New test.
* ld-tic6x/got-reloc-global.s: New test.
* ld-tic6x/got-reloc-global-addend-1.d: New test.
* ld-tic6x/got-reloc-global-addend-1.s: New test.
* ld-tic6x/got-reloc-global-addend-2.d: New test.
* ld-tic6x/got-reloc-inrange.d: New test.
* ld-tic6x/got-reloc-overflow.d: New test.
* ld-tic6x/got-reloc-global-addend-2.s: New test.
* ld-tic6x/dsbt-index-error.d: New test.
* ld-tic6x/dsbt-index.d: New test.
* ld-tic6x/dsbt-index.s: New test.
* ld-tic6x/shlib-app-1.od: New test.
* ld-tic6x/shlib-app-1rb.od: New test.
* ld-tic6x/shlib-1.rd: New test.
* ld-tic6x/weak.d: New test.
* ld-tic6x/weak-be.d: New test.
* ld-tic6x/weak.s: New test.
* ld-tic6x/weak-data.d: New test.
* ld-tic6x/common.d: New test.
* ld-tic6x/common.ld: New test.
* ld-tic6x/common.s: New test.
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* archures.c: Add AVR XMEGA architecture information.
* cpu-avr.c (arch_info_struct): Likewise.
* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
(elf32_avr_object_p): Likewise.
/gas:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
(AVR_INSN): Change definition to match.
(avr_opcodes): Likewise, change to match.
(mcu_types): Add XMEGA architecture names and new XMEGA device names.
(md_show_usage): Add XMEGA architecture names.
(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
Add support for SPM Z+ instruction.
* doc/c-avr.texi: Add documentation for XMEGA architectures and
devices.
/include/opcode:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
New instruction set flags.
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
/ld:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
(eavrxmega?.c): Likewise.
* configure.tgt (targ_extra_emuls): Likewise.
* emulparams/avrxmega1.sh: New file.
* emulparams/avrxmega2.sh: Likewise.
* emulparams/avrxmega3.sh: Likewise.
* emulparams/avrxmega4.sh: Likewise.
* emulparams/avrxmega5.sh: Likewise.
* emulparams/avrxmega6.sh: Likewise.
* emulparams/avrxmega7.sh: Likewise.
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
/opcodes:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
post-increment to support LPM Z+ instruction. Add support for 'E'
constraint for DES instruction.
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
* internal.h (elf_internal_sym): Add st_target_internal.
* arm.h (arm_st_branch_type): New enum.
(ARM_SYM_BRANCH_TYPE): New macro.
bfd/
* elf-bfd.h (elf_link_hash_entry): Add target_internal.
* elf.c (swap_out_syms): Set st_target_internal for each
Elf_Internal_Sym.
* elfcode.h (elf_swap_symbol_in): Likewise.
* elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise.
* elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise.
* elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
* elflink.c (elf_link_output_extsym): Likewise.
(bfd_elf_final_link): Likewise.
(elf_link_add_object_symbols): Copy st_target_internal
to the hash table if we see a definition.
(_bfd_elf_copy_link_hash_symbol_type): Copy target_internal.
* elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with
a branch_type field.
(a8_erratum_fix, a8_erratum_reloc): Likewise.
(arm_type_of_stub): Replace actual_st_type with an
actual_branch_type parameter.
(arm_build_one_stub): Use branch types rather than st_types to
determine the type of branch.
(cortex_a8_erratum_scan): Likewise.
(elf32_arm_size_stubs): Likewise.
(bfd_elf32_arm_process_before_allocation): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_final_link_relocate): Replace sym_flags parameter with
a branch_type parameter.
(elf32_arm_relocate_section): Update call accordingly.
(elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC.
(elf32_arm_output_map_sym): Initialize st_target_internal.
(elf32_arm_output_stub_sym): Likewise.
(elf32_arm_symbol_processing): Delete.
(elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs.
Use st_target_internal to record the branch type.
(elf32_arm_swap_symbol_out): Use st_target_internal to test for
Thumb functions.
(elf32_arm_is_function_type): Delete.
(elf_backend_symbol_processing): Likewise.
(elf_backend_is_function_type): Likewise.
gas/
* config/tc-arm.c (arm_adjust_symtab): Set the branch type
for Thumb symbols.
ld/
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check
eh->target_internal.
opcodes/
* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
Use branch types instead.
(print_insn): Likewise.
This can boot Das U-Boot and a Linux kernel. It also supports Linux
userspace FLAT and FDPIC (dynamic and static) ELFs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The mmod field is decoded in a few places (gas/opcodes/sim), so move it to
a common place to avoid duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gdb/ChangeLog
* remote-sim.c (gdbsim_store_register): Update API to
sim_store_register to check more error conditions.
include/gdb/ChangeLog
* remote-sim.h (sim_store_register): Update the API
documentation for this function.
sim/erc32/ChangeLog
sim/h8300/ChangeLog
sim/m32c/ChangeLog
sim/mn10300/ChangeLog
sim/ppc/ChangeLog
sim/rx/ChangeLog
sim/v850/ChangeLog
* ???.c (sim_store_register): Update return value to
match new API.
* config/tc-hppa.c (pa_ip): Revert last change. Add variable need_cond
to determine whether a 64-bit condition is needed for 'A' and 'S'
conditions. Default to 32-bit never condition for logical and unit
instructions. Add error message for missing branch on bit condition.
* hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
"bb" entries.
* hppa-dis.c (compare_cond_64_names): Change never condition to ",*".
(add_cond_64_names): Likewise.
(logical_cond_64_names): Likewise.
(unit_cond_64_names): Likewise.
* config/tc-hppa.c (pa_ip): Set doubleword carry/borrow bit when a
doubleword completer or doubleword condition is found in an add/sub
instruction. Reject match for 'A'/'S' only if there is no condition
and d bit is not set.
* gas/hppa/basic/add2.s: Add test for a simple doubleword carry
instruction.
* gas/hppa/basic/sub2.s: Add tests for simple word and doubleword
borrow instructions.
* gas/hppa/basic/basic.exp: Update regexps for above.
* opcode/hppa.h: Clear "d" bit in "add" and "sub" patterns.
* config/tc-s390.c (current_cpu): Initialize with latest CPU.
(init_default_arch): Default to z/Architecture mode if CPU provides it.
Remove the check setting the CPU default.
2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
Add new linker options for marking programs to load into L1 memory
at runtime. This needs new EF flag bits, so declare them.
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/config/tc-arm.c (arm_arch_v6m_only): New variable.
(aeabi_set_public_attributes): Ensure we only set the Operating System
Extension when we are on an M-profile core.
* gas/testsuite/gas/arm/pr12198-1.d: New test.
* gas/testsuite/gas/arm/pr12918-1.s: Likewise.
* gas/testsuite/gas/arm/pr12198-2.d: Likewise.
* gas/testsuite/gas/arm/pr12918-2.s: Likewise.
* include/opcode/arm.h (ARM_AEXT_V6M_ONLY): New define.
(ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
(ARM_ARCH_V6M_ONLY): New define.
[PATCH] Add infrastructure for plugin API; functionality to follow.
include/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 1/6).
* plugin-api.h (LDPT_GNU_LD_VERSION): New ld_plugin_tag enum member.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 1/6).
* configure.in: Add AC_CHECKs for file io and dlfcn headers and
functions and AC_SEARCH for -ldl.
(enable_plugins): New shell variable set if above tests find dlopen
functionality.
(ENABLE_PLUGINS): Add related automake conditional.
* configure: Regenerate.
* config.in: Likewise.
* Makefile.am (PLUGIN_C): Declare plugin C source file, conditional
on ENABLE_PLUGINS being defined.
(PLUGIN_H): Likewise for header file.
(PLUGIN_OBJECT): Likewise for object file.
(PLUGIN_CFLAGS): Likewise -D flag required to compile plugin support.
(AM_CPPFLAGS): Use PLUGIN_CFLAGS.
(CFILES): Use PLUGIN_C.
(HFILES): Use PLUGIN_H.
(OFILES): Use PLUGIN_OBJECT.
(ld_new_SOURCES): Use PLUGIN_C.
(noinst_LTLIBRARIES)[ENABLE_PLUGINS]: Declare test plugin.
(libldtestplug_la_SOURCES)[ENABLE_PLUGINS]: Add automake definition
for test plugin.
(libldtestplug_la_CFLAGS)[ENABLE_PLUGINS]: Likewise.
(libldtestplug_la_LDFLAGS)[ENABLE_PLUGINS]: Likewise.
* Makefile.in: Regenerate.
* sysdep.h: Include stdarg.h, unistd.h and one of fcntl.h or
sys/file.h where available. Include dlfcn.h when ENABLE_PLUGINS.
(O_RDONLY): Supply default definition likewise to bfd's sysdep.h
(O_WRONLY): Likewise.
(O_RDWR): Likewise.
(O_ACCMODE): Likewise.
(O_BINARY): Likewise.
(SEEK_SET): Likewise.
(SEEK_CUR): Likewise.
(SEEK_END): Likewise.
* ldmisc.c (vfinfo): Make non-static. Add %p format char.
* ldmisc.h (vfinfo): Declare extern prototype.
* lexsup.c (enum option_values)[ENABLE_PLUGINS]: Add new entries for
OPTION_PLUGIN and OPTION_PLUGIN_OPT.
(ld_options[])[ENABLE_PLUGINS]: Add option data for the above two.
(parse_args)[ENABLE_PLUGINS]: Handle them, and load all plugins once
option parsing is complete.
* ldmain.c (main)[ENABLE_PLUGINS]: Call plugin cleanup hooks just
after lang_finish.
* plugin.c: New source file.
* plugin.h: Likewise new header.
* testplug.c: New source file.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 1/6).
* ld-bootstrap/bootstrap.exp: Skip static tests also if LD plugins
are enabled.
* lib/ld-lib.exp (proc regexp_diff): Extend verbose debug output.
(proc set_file_contents): Write a file with the supplied content.
(run_ld_link_tests): Add new 'ld' action to test linker output.
(proc check_plugin_api_available): Return true if linker under test
supports the plugin API.
* ld-plugin/func.c: New test source file.
* ld-plugin/main.c: Likewise.
* ld-plugin/text.c: Likewise.
* ld-plugin/plugin-1.d: New dump test output pattern script.
* ld-plugin/plugin-2.d: Likewise.
* ld-plugin/plugin-3.d: Likewise.
* ld-plugin/plugin-4.d: Likewise.
* ld-plugin/plugin-5.d: Likewise.
* ld-plugin/plugin.exp: New test control script.
---
[PATCH] Implement claim file and all symbols read hooks and add symbols callback.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 2/6).
* ldfile.c (ldfile_try_open_bfd)[ENABLE_PLUGINS]: Don't return early
during compat checks if they pass, instead offer any successfully
opened and accepted file to the plugin claim file hooks chain. Create
a dummy bfd to accept symbols added by the plugin, if the plugin
claims the file.
* ldlang.c (lang_process)[ENABLE_PLUGINS]: Call plugin all symbols
read hook chain before ldemul_after_open.
* ldlang.h (struct lang_input_statement_struct): Add new single-bit
'claimed' flag.
* plugin.c (IRONLY_SUFFIX): New macro for dummy bfd file suffix.
(IRONLY_SUFFIX_LEN): Length of the above string.
(plugin_get_ir_dummy_bfd): New function to create the dummy bfd used
to store symbols for ir-only files.
(is_ir_dummy_bfd): New function to check if a bfd is ir-only.
(asymbol_from_plugin_symbol): New function converts symbol formats.
(add_symbols): Call it to convert plugin syms to bfd syms and add
them to the dummy bfd.
* plugin.h: Add missing include guards.
(plugin_get_ir_dummy_bfd): Add prototype.
(is_ir_dummy_bfd): Likewise.
* testplug.c (TV_MESSAGE): New helper macro.
(struct claim_file): New struct.
(claim_file_t): New typedef.
(tag_names[]): Make static and const.
(claimfiles_list): New variable.
(claimfiles_tail_chain_ptr): Likewise.
(last_claimfile): Likewise.
(record_claim_file): Record a file to claim on a singly-linked list.
(parse_symdefstr): Parse an ASCII representation of a symbol from a
plugin option into the fields of a struct ld_plugin_symbol.
(record_claimed_file_symbol): Use it to parse plugin option for
adding a symbol.
(parse_option): Parse claim file and add symbol options.
(dump_tv_tag): Use TV_MESSAGE.
(onload): Likewise.
(onclaim_file): Make static. Use TV_MESSAGE. Scan list of files to
claim and claim this file if required, adding any symbols specified.
(onall_symbols_read): Make static and use TV_MESSAGE.
(oncleanup): Likewise.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 2/6).
* ld-plugin/plugin-3.d: Enable regexes for new functionality.
* ld-plugin/plugin-5.d: Likewise.
* ld-plugin/plugin-6.d: New testcase.
* ld-plugin/plugin-7.d: Likewise.
* ld-plugin/plugin.exp: Use 'nm' on compiled test objects to determine
whether symbols in plugin arguments need an underscore prefix. Add
new plugin-6.d and plugin-7.d testcases.
---
[PATCH] Implement get symbols callback.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 3/6).
* ldmain.c (notice)[ENABLE_PLUGINS]: Call plugin_notice.
* plugin.c (non_ironly_hash): Add new bfd hash table.
(plugin_load_plugins): Exit early if no plugins to load. If plugins
do load successfully, set notice_all flag in link info.
(get_symbols): Implement.
(plugin_load_plugins): Exit early if no plugins to load, else after
loading plugins successfully enable notice_all mode.
(init_non_ironly_hash): Lazily init non_ironly_hash table.
(plugin_notice): Record symbols referenced from non-IR files in the
non_ironly_hash. Suppress tracing, cref generation and nocrossrefs
tracking for symbols from dummy IR bfds.
* plugin.h: Fix formatting.
(plugin_notice): Add prototype.
* testplug.c (dumpresolutions): New global var.
(parse_options): Accept "dumpresolutions".
(onall_symbols_read): Get syms and dump resolutions if it was given.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 3/6).
* ld-plugin/plugin-8.d: New testcase.
* ld-plugin/plugin.exp: Invoke it.
---
[PATCH] Implement add input file, add input lib and set extra lib path callbacks.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 4/6).
* ldlang.c (lang_process)[ENABLE_PLUGINS]: Move invocation of
plugin_call_all_symbols_read to before setting of gc_sym_list, and
open any new input files that may have been added during it.
* ldmain.c (multiple_definition)[ENABLE_PLUGINS]: Call out to
plugin_multiple_definition and let it have first say over what to do
with the clashing definitions.
* plugin.c (no_more_claiming): New boolean variable.
(plugin_cached_allow_multiple_defs): Likewise.
(add_input_file): Implement.
(add_input_library): Likewise.
(set_extra_library_path): Likewise.
(plugin_call_claim_file): Don't do anything when no_more_claiming set.
(plugin_call_all_symbols_read): Set it. Disable link info
"allow_multiple_definition" flag, but cache its value.
(plugin_multiple_definition): New function.
* plugin.h (plugin_multiple_definition): Add prototype.
* testplug.c (addfile_enum_t): New enumerated typedef.
(add_file_t): New struct typedef.
(addfiles_list): New variable.
(addfiles_tail_chain_ptr): Likewise.
(record_add_file): New function.
(parse_option): Parse "add:", "lib:" and "dir:" options and call it.
(onall_symbols_read): Iterate the list of new files, libs and dirs,
adding them.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 4/6).
* ld-plugin/plugin-9.d: New testcase.
* ld-plugin/plugin.exp: Invoke it.
---
[PATCH] Add ELF symbol visibility support to plugin interface.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 5/6).
* plugin.c (asymbol_from_plugin_symbol): If the bfd is an ELF bfd,
find the elf symbol data and set the visibility in the st_other field.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 5/6).
* ld-plugin/plugin-ignore.d: New dump test control script.
* ld-plugin/plugin-vis-1.d: Likewise.
* ld-plugin/plugin.exp: Add list of ELF-only tests and run them if
testing on an ELF target.
---
[PATCH] Add archive support to plugin interface.
bfd/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 6/6).
* aoutx.h (aout_link_check_ar_symbols): Take new "subsbfd" reference
parameter and pass it when invoking add_archive_element callback.
(aout_link_check_archive_element): Handle substitute bfd if it
was set during add_archive_element callback in the above.
* cofflink.c (coff_link_check_ar_symbols): Take new "subsbfd" reference
parameter and pass it when invoking add_archive_element callback.
(coff_link_check_archive_element): Handle substitute bfd if it
was set during add_archive_element callback in the above.
* ecoff.c (read_ext_syms_and_strs): New function holds symbol-reading
code factored-out from ecoff_link_check_archive_element.
(reread_ext_syms_and_strs): Clear old symbols and call it.
(ecoff_link_check_archive_element): Use the above. Handle substitute
BFD if one is set by add_archive_element callback.
(ecoff_link_add_archive_symbols): Likewise allow bfd substitution.
* elflink.c (elf_link_add_archive_symbols): Likewise.
* linker.c (generic_link_check_archive_element): Likewise.
* pdp11.c (aout_link_check_ar_symbols): Take new "subsbfd" reference
parameter and pass it when invoking add_archive_element callback.
(aout_link_check_archive_element): Handle substitute bfd if it was
set during add_archive_element callback in the above.
* vms-alpha.c (alpha_vms_link_add_archive_symbols): Handle substitute
BFD if one is set by add_archive_element callback.
* xcofflink.c (xcoff_link_check_dynamic_ar_symbols): Take new "subsbfd"
reference parameter and pass it when invoking add_archive_element
callback.
(xcoff_link_check_ar_symbols): Likewise.
(xcoff_link_check_archive_element): Handle bfd substitution if it was
set by callback in the above.
include/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 6/6).
* bfdlink.h (struct_bfd_link_callbacks): Document new argument
to add_archive_element callback used to return a replacement bfd which
is to be added to the hash table in place of the original element.
ld/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 6/6).
* ldlang.c (load_symbols): Handle bfd subsitution when calling the
add_archive_element callback.
* ldmain.c (add_archive_element)[ENABLE_PLUGINS]: Offer the archive
member to the plugins and if claimed set "subsbfd" output parameter to
point to the dummy IR-only BFD.
ld/testsuite/ChangeLog:
2010-10-14 Dave Korn <dave.korn.cygwin@gmail.com>
Apply LD plugin patch series (part 6/6).
* ld-plugin/plugin-10.d: New dump test control script.
* ld-plugin/plugin-11.d: Likewise.
* ld-plugin/plugin.exp: Run them.
---
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* dwarf.c (decode_location_expression): Add offset_size and
dwarf_version arguments. Prefix DIE offset with 0x for
DW_OP_call{2,4,_ref}. Fix up DW_OP_call_ref operand size,
complain if in frame info section. Handle
DW_OP_GNU_implicit_pointer.
(read_and_display_attr_value, display_debug_loc,
display_debug_frames): Adjust decode_location_expression callers.
(process_debug_info): Save offset_size and dwarf_version values
into debug_information array.
* dwarf2.h (DW_OP_GNU_implicit_pointer): New.
* common/signals.c (ANY): Remove.
(SET): No longer use ANY.
include/gdb/
* signals.def: Replace all ANY uses by SET with specific numbers.
* signals.h (ANY): Remove.
* common/signals.c (signals): Move the content to signals.def.
Include it. Remove the INDENT comments.
gdb/gdbserver/
* Makefile.in (signals_def): New.
(server_h): Append include/gdb/signals.h and signals_def.
(server.o): Append signals_def.
include/gdb/
* signals.h (enum target_signal): Move the content to signals.def.
Include it.
* signals.def: New file.
* rx.h (RX_Operand_Type): Add TwoReg.
(RX_Opcode_ID): Remove ediv and ediv2.
[opcodes]
* rx-decode.opc (SRR): New.
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.
[sim/rx]
* rx.c (decode_cache_base): New.
(id_names): Remove ediv and edivu.
(optype_names): Add TwoReg.
(maybe_get_mem_page): New.
(rx_get_byte): Call it.
(get_op): Add TwoReg support.
(put_op): Likewise.
(PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode"
is a pointer now.
(DO_RETURN): New. We use longjmp to return an exception result.
(decode_opcode): Make opcode a pointer to the decode cache. Save
decoded opcode information and re-use. Call DO_RETURN instead of
return throughout. Remove ediv and edivu.
* mem.c (ptdc): New. Adds decode cache.
(rx_mem_ptr): Support it.
(rx_mem_decode_cache): New.
* mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE.
(rx_mem_decode_cache): Declare.
* gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here...
* main.c (main): ...and here. Use a fast loop if neither trace
nor disassemble is given.
* cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED,
RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a
valid code for anything.
* internal.h (ELF_TBSS_SPECIAL): New macro, extracted from..
(ELF_SECTION_SIZE): ..here.
(ELF_SECTION_IN_SEGMENT_1): Add "strict" arg.
(ELF_SECTION_IN_SEGMENT_STRICT): New macro.
bfd/
* elf.c (assign_file_positions_for_load_sections): Check that
zero size sections are allocated in segments too.
(assign_file_positions_for_non_load_sections): Warn if zero
size alloc sections are found here.
(copy_elf_program_header): Don't drop zero size sections from
segment map.
(copy_private_bfd_data): Check for changes in zero size sections.
binutils/
* readelf.c (process_program_headers): Don't ignore all zero size
sections.
ld/testsuite/
* ld-powerpc/tlsexe.r: Update.
* ld-powerpc/tlsexetoc.r: Update.
* ld-powerpc/tlsso.r: Update.
* ld-powerpc/tlstocso.r: Update.
2010-07-06 Ken Werner <ken.werner@de.ibm.com>
* floatformat.h (floatformat_ieee_half_big): Add declaration.
(floatformat_ieee_half_little): Likewise.
libiberty/ChangeLog:
2010-07-06 Ken Werner <ken.werner@de.ibm.com>
* floatformat.c (floatformat_ieee_half_big): New variable.
(floatformat_ieee_half_little): Likewise.
gdb/ChangeLog:
2010-07-06 Ken Werner <ken.werner@de.ibm.com>
* gdbtypes.h (floatformats_ieee_half): Add declaration.
* gdbtypes.c (floatformats_ieee_half): New variable.
* doublest.c (floatformat_from_length): Set format to
gdbarch_half_format if length matches.
* gdbarch.sh (half_bit): New architecture method.
(half_format): Likewise.
* gdbarch.h: Regenerate.
* gdbarch.c: Likewise.
* fileread.cc (Input_file::find_fie): New
(Input_file::open): Use Input_file::find_fie.
* fileread.h (Input_file::find_fie): New
* plugin.cc (set_extra_library_path): New.
(Plugin::load): Add set_extra_library_path to the transfer vector.
(Plugin_manager::set_extra_library_path): New.
(Plugin_manager::add_input_file): Use the extra search path if set.
(set_extra_library_path(): New.
* plugin.h (Plugin_manager): Add set_extra_library_path and
extra_search_path_.
2010-06-21 Rafael Espindola <espindola@google.com>
* plugin-api.h (ld_plugin_set_extra_library_path): New.
(ld_plugin_tag): Add LDPT_SET_EXTRA_LIBRARY_PATH.
(ld_plugin_tv): Add tv_set_extra_library_path.
* config/tc-ppc.c (md_assemble): Emit APUinfo section for
PPC_OPCODE_E500.
gas/testsuite/
* gas/ppc/e500.s: Add eieio, mbar and lwsync
* gas/ppc/e500.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_E500): Define.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
touch floating point regs and are enabled by COM, PPC or PPCCOM.
Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
Treat lwsync as msync on e500.
* plugin-api.h (ld_plugin_tag): Add LDPT_OUTPUT_NAME.
2010-06-01 Rafael Espindola <espindola@google.com>
* plugin.cc (Plugin::load): Pass the output name to the plugin.
Joseph Myers <joseph@codesourcery.com>
Andrew Stubbs <ams@codesourcery.com>
bfd/
* config.bfd (sh-*-uclinux* | sh[12]-*-uclinux*): Add
bfd_elf32_shl_vec, and FDPIC vectors to targ_selvecs.
* configure.in: Handle FDPIC vectors.
* elf32-sh-relocs.h: Add FDPIC and movi20 relocations.
* elf32-sh.c (DEFAULT_STACK_SIZE): Define.
(SYMBOL_FUNCDESC_LOCAL): Define. Use it instead of
SYMBOL_REFERENCES_LOCAL for function descriptors.
(fdpic_object_p): New.
(sh_reloc_map): Add FDPIC and movi20 relocations.
(sh_elf_info_to_howto, sh_elf_relocate_section): Handle new invalid
range.
(struct elf_sh_plt_info): Add got20 and short_plt. Update all
definitions.
(FDPIC_PLT_ENTRY_SIZE, FDPIC_PLT_LAZY_OFFSET): Define.
(fdpic_sh_plt_entry_be, fdpic_sh_plt_entry_le, fdpic_sh_plts): New.
(FDPIC_SH2A_PLT_ENTRY_SIZE, FDPIC_SH2A_PLT_LAZY_OFFSET): Define.
(fdpic_sh2a_plt_entry_be, fdpic_sh2a_plt_entry_le)
(fdpic_sh2a_short_plt_be, fdpic_sh2a_short_plt_le, fdpic_sh2a_plts):
New.
(get_plt_info): Handle FDPIC.
(MAX_SHORT_PLT): Define.
(get_plt_index, get_plt_offset): Handle short_plt.
(union gotref): New.
(struct elf_sh_link_hash_entry): Add funcdesc, rename tls_type to
got_type and adjust all uses. Add GOT_FUNCDESC.
(struct sh_elf_obj_tdata): Add local_funcdesc. Rename
local_got_tls_type to local_got_type.
(sh_elf_local_got_type): Renamed from sh_elf_local_got_tls_type. All
users changed.
(sh_elf_local_funcdesc): Define.
(struct elf_sh_link_hash_table): Add sfuncdesc, srelfuncdesc, fdpic_p,
and srofixup.
(sh_elf_link_hash_newfunc): Initialize new fields.
(sh_elf_link_hash_table_create): Set fdpic_p.
(sh_elf_omit_section_dynsym): New.
(create_got_section): Create .got.funcdesc, .rela.got.funcdesc
and .rofixup.
(allocate_dynrelocs): Allocate local function descriptors and space
for R_SH_FUNCDESC-related relocations, and for rofixups.
Handle GOT_FUNCDESC. Create fixups. Handle GOT entries which
require function descriptors.
(sh_elf_always_size_sections): Handle PT_GNU_STACK and __stacksize.
(sh_elf_modify_program_headers): New.
(sh_elf_size_dynamic_sections): Allocate function descriptors for
local symbols. Allocate .got.funcdesc contents. Allocate rofixups.
Handle local GOT entries of type GOT_FUNCDESC. Create fixups for
local GOT entries. Ensure that FDPIC libraries always have a PLTGOT
entry in the .dynamic section.
(sh_elf_add_dyn_reloc, sh_elf_got_offset, sh_elf_initialize_funcdesc)
(sh_elf_add_rofixup, sh_elf_osec_to_segment)
(sh_elf_osec_readonly_p, install_movi20_field): New functions.
(sh_elf_relocate_section): Handle new relocations, R_SH_FUNCDESC,
R_SH_GOTFUNCDESC and R_SH_GOTOFFFUNCDESC. Use sh_elf_got_offset
and .got.plt throughout to find _GLOBAL_OFFSET_TABLE_. Add rofixup
read-only section warnings. Handle undefined weak symbols. Generate
fixups for R_SH_DIR32 and GOT entries. Check for cross-segment
relocations and clear EF_SH_PIC. Handle 20-bit relocations.
Always generate R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_gc_sweep_hook): Handle R_SH_FUNCDESC, R_SH_GOTOFF20,
R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20, and R_SH_GOTOFFFUNCDESC.
Handle 20-bit relocations.
(sh_elf_copy_indirect_symbol): Copy function descriptor reference
counts.
(sh_elf_check_relocs): Handle new relocations. Make symbols
dynamic for FDPIC relocs. Account for rofixups. Error for FDPIC
symbol mismatches. Allocate a GOT for R_SH_DIR32. Allocate fixups
for R_SH_DIR32.
(sh_elf_copy_private_data): Copy PT_GNU_STACK size.
(sh_elf_merge_private_data): Copy initial flags. Do not clobber
non-mach flags. Set EF_SH_PIC for FDPIC. Reject FDPIC mismatches.
(sh_elf_finish_dynamic_symbol): Do not handle got_funcdesc entries
here. Rename sgot to sgotplt and srel to srelplt. Handle short_plt,
FDPIC descriptors, and got20. Create R_SH_FUNCDESC_VALUE for FDPIC.
Use install_movi20_field. Rename srel to srelgot. Always generate
R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_finish_dynamic_sections): Fill in the GOT pointer in rofixup.
Do not fill in reserved GOT entries for FDPIC. Correct DT_PLTGOT.
Rename sgot to sgotplt. Assert that the right number of rofixups
and dynamic relocations were allocated.
(sh_elf_use_relative_eh_frame, sh_elf_encode_eh_address): New.
(elf_backend_omit_section_dynsym): Use sh_elf_omit_section_dynsym.
(elf_backend_can_make_relative_eh_frame)
(elf_backend_can_make_lsda_relative_eh_frame)
(elf_backend_encode_eh_address): Define.
(TARGET_BIG_SYM, TARGET_BIG_NAME, TARGET_LITTLE_SYM)
(TARGET_LITTLE_NAME, elf_backend_modify_program_headers, elf32_bed):
Redefine for FDPIC vector.
* reloc.c: Add SH FDPIC and movi20 relocations.
* targets.c (_bfd_target_vector): Add FDPIC vectors.
* configure, bfd-in2.h, libbfd.h: Regenerated.
binutils/
* readelf.c (get_machine_flags): Handle EF_SH_PIC and EF_SH_FDPIC.
gas/
* config/tc-sh.c (sh_fdpic): New.
(sh_check_fixup): Handle relocations on movi20.
(parse_exp): Do not reject PIC operators here.
(build_Mytes): Check for unhandled PIC operators here. Use
sh_check_fixup for movi20.
(enum options): Add OPTION_FDPIC.
(md_longopts, md_parse_option, md_show_usage): Add --fdpic.
(sh_fix_adjustable, md_apply_fix): Handle FDPIC and movi20 relocations.
(sh_elf_final_processing): Handle --fdpic.
(sh_uclinux_target_format): New.
(sh_parse_name): Handle FDPIC relocation operators.
* config/tc-sh.h (TARGET_FORMAT): Define specially for TE_UCLINUX.
(sh_uclinux_target_format): Declare for TE_UCLINUX.
* configure.tgt (sh-*-uclinux* | sh[12]-*-uclinux*): Set
em=uclinux.
* doc/c-sh.texi (SH Options): Document --fdpic.
gas/testsuite/
* gas/sh/basic.exp: Run new tests. Handle uClinux like Linux.
* gas/sh/fdpic.d: New file.
* gas/sh/fdpic.s: New file.
* gas/sh/reg-prefix.d: Force big-endian.
* gas/sh/sh2a-pic.d: New file.
* gas/sh/sh2a-pic.s: New file.
* lib/gas-defs.exp (is_elf_format): Include sh*-*-uclinux*.
include/elf/
* sh.h (EF_SH_PIC, EF_SH_FDPIC): Define.
(R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New. Adjust
other invalid ranges.
(R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20)
(R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC)
(R_SH_FUNCDESC_VALUE): New.
ld/
* Makefile.am (ALL_EMULATIONS): Add eshelf_fd.o and eshlelf_fd.o.
(eshelf_fd.c, eshlelf_fd.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh-*-uclinux*): Add shelf_fd and shlelf_fd
emulations.
* emulparams/shelf_fd.sh: New file.
* emulparams/shlelf_fd.sh: New file.
* emulparams/shlelf_linux.sh: Update comment.
ld/testsuite/
* ld-sh/sh.exp: Handle uClinux like Linux.
* lib/ld-lib.exp (is_elf_format): Include sh*-*-uclinux*.
* ld-sh/fdpic-funcdesc-shared.d: New file.
* ld-sh/fdpic-funcdesc-shared.s: New file.
* ld-sh/fdpic-funcdesc-static.d: New file.
* ld-sh/fdpic-funcdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesc-shared.d: New file.
* ld-sh/fdpic-gotfuncdesc-shared.s: New file.
* ld-sh/fdpic-gotfuncdesc-static.d: New file.
* ld-sh/fdpic-gotfuncdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotfuncdesci20-static.d: New file.
* ld-sh/fdpic-gotfuncdesci20-static.s: New file.
* ld-sh/fdpic-goti20-shared.d: New file.
* ld-sh/fdpic-goti20-shared.s: New file.
* ld-sh/fdpic-goti20-static.d: New file.
* ld-sh/fdpic-goti20-static.s: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesc-static.d: New file.
* ld-sh/fdpic-gotofffuncdesc-static.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.s: New file.
* ld-sh/fdpic-gotoffi20-shared.d: New file.
* ld-sh/fdpic-gotoffi20-shared.s: New file.
* ld-sh/fdpic-gotoffi20-static.d: New file.
* ld-sh/fdpic-gotoffi20-static.s: New file.
* ld-sh/fdpic-plt-be.d: New file.
* ld-sh/fdpic-plt-le.d: New file.
* ld-sh/fdpic-plt.s: New file.
* ld-sh/fdpic-plti20-be.d: New file.
* ld-sh/fdpic-plti20-le.d: New file.
* ld-sh/fdpic-stack-default.d: New file.
* ld-sh/fdpic-stack-size.d: New file.
* ld-sh/fdpic-stack.s: New file.
2010-05-03 Tristan Gingold <gingold@adacore.com>
* vms-alpha.c: Add comments.
(struct vms_private_data_struct): Remove image_autoextend field.
(dst_check_allocation): Removed.
(image_write): Remove call to dst_check_allocation.
(vms_slurp_debug): Do not set image_autoextend. Adjust section
size.
(_bfd_vms_slurp_object_records): Remove useless new_type variable.
(alpha_vms_write_exec): Use dst_section to get the dst section.
Write the dmt section.
(evax_bfd_print_image): Also print the dst size in hexa. Fix typo.
(alpha_vms_read_sections_content): Do not set image_autoextend.
include/vms/
2010-05-03 Tristan Gingold <gingold@adacore.com>
* dmt.h: Improve comments.
* internal.h (ELF_SECTION_SIZE): Protect macro args with parentheses.
Invert logic to clarify test for .tbss.
(ELF_IS_SECTION_IN_SEGMENT): Rename to..
(ELF_SECTION_IN_SEGMENT_1): ..this. Add check_vma param. Protect
macro args with parentheses.
(ELF_SECTION_IN_SEGMENT): Define.
(ELF_IS_SECTION_IN_SEGMENT_FILE): Delete.
(ELF_IS_SECTION_IN_SEGMENT_MEMORY): Delete.
bfd/
* elf.c: Replace use of ELF_IS_SECTION_IN_SEGMENT and
ELF_IS_SECTION_IN_SEGMENT_FILE with ELF_SECTION_IN_SEGMENT
throughout file.
(assign_file_positions_for_load_sections): Modify section in
segment warning to ignore overlay vmas.
* elf32-spu.c (spu_elf_object_p): Replace use of
ELF_IS_SECTION_IN_SEGMENT_MEMORY with ELF_SECTION_IN_SEGMENT.
binutils/
* readelf.c (process_program_headers): Replace use of
ELF_IS_SECTION_IN_SEGMENT_MEMORY with ELF_SECTION_IN_SEGMENT.
Most the sim write functions declare their source buffer const because
they only ever read from it. The global sim_write() function does not
follow this convention though which causes some warnings when trying to
pass it const strings or buffers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* dwarf2.h (DWARF2_Internal_LineInfo): Add li_max_ops_per_insn
field.
bfd/
* dwarf2.c (struct line_head): Add maximum_ops_per_insn field.
(struct line_info): Add op_index field, change end_sequence type to
unsigned char.
(new_line_sorts_after): For the same address compare op_index.
(add_line_info): Add op_index argument, store it into the structure.
(decode_line_info): Complain about unknown versions of .debug_line.
Initialize maximum_ops_per_insn. Add op_index state register and
track it.
binutils/
* dwarf.c (struct State_Machine_Registers): Add op_index field,
change end_sequence type to unsigned char.
(reset_state_machine): Clear op_index.
(process_extended_line_op): For DW_LNE_set_address clear op_index.
(display_debug_lines_raw): Initialize li_max_ops_per_insn.
Track op_index state machine register and print it if
li_max_ops_per_insn is != 1.
(display_debug_lines_decoded): Likewise.
mips_fix_loongson2f_jump): New variables.
(md_longopts): Add New options -mfix-loongson2f-nop/jump,
-mno-fix-loongson2f-nop/jump.
(md_parse_option): Initialize variables via above options.
(options): New enums for the above options.
(md_begin): Initialize nop_insn from LOONGSON2F_NOP_INSN.
(fix_loongson2f, fix_loongson2f_nop, fix_loongson2f_jump):
New functions.
(append_insn): call fix_loongson2f().
(mips_handle_align): Replace the implicit nops.
* config/tc-mips.h (MAX_MEM_FOR_RS_ALIGN_CODE): Modified
for the new mips_handle_align().
* doc/c-mips.texi: Document the new options.
* gas/mips/loongson-2f-2.s: New test of -mfix-loongson2f-nop.
* gas/mips/loongson-2f-2.d: Likewise.
* gas/mips/loongson-2f-3.s: New test of -mfix-loongson2f-jump.
* gas/mips/loongson-2f-3.d: Likewise.
* gas/mips/mips.exp: Run the new tests.
* opcode/mips.h (LOONGSON2F_NOP_INSN): New macro.
* elf/sparc.h (R_SPARC_JMP_IREL, R_SPARC_IRELATIVE): Define.
bfd/
* reloc.c (BFD_RELOC_SPARC_JMP_IREL): New.
(BFD_RELOC_SPARC_IRELATIVE): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfxx-sparc.h (_bfd_sparc_elf_link_hash_table): Add loc_hash_table
and loc_hash_memory.
(_bfd_sparc_elf_link_hash_table_free): Declare.
* elf32-sparc.c (elf32_sparc_add_symbol_hook): New.
(elf_backend_add_symbol_hook, elf_backend_post_process_headers,
bfd_elf32_bfd_link_hash_table_free): Define.
* elf64-sparc.c (elf64_sparc_add_symbol_hook): Set
has_ifunc_symbols if STT_GNU_IFUNC.
(bfd_elf64_bfd_link_hash_table_free): Define.
(elf_backend_post_process_headers): Define always.
* elfxx-sparc.c (sparc_jmp_irel_howto, sparc_irelative_howto): New.
(sparc_reloc_map): Add entries for new IFUNC relocs.
(_bfd_sparc_elf_reloc_type_lookup): Handle new IFUNC relocs.
(_bfd_sparc_elf_info_to_howto_ptr): Likewise.
(elf_sparc_local_htab_hash, elf_sparc_local_htab_eq,
elf_sparc_get_local_sym_hash): New.
(_bfd_sparc_elf_create_dynamic_sections): Move PLT ops initialization
from here...
(_bfd_sparc_elf_link_hash_table_create): ... to here. Allocate
local hash table.
(_bfd_sparc_elf_link_hash_table_free): New.
(create_ifunc_sections): New.
(_bfd_sparc_elf_check_relocs): Unconditionally assign htab->elf.dynobj
and call create_ifunc_sections(). For local STT_GNU_IFUNC symbols
cons up a fake local hash table entry for it. Unconditionally add
a PLT refcount for STT_GNU_IFUNC symbols when h->def_regular. Count
dyn relocs for ifunc.
(_bfd_sparc_elf_adjust_dynamic_symbol): Handle ifunc.
(allocate_dynrelocs): Unconditionally emit a PLT entry when STT_GNU_IFUNC
and h->def_regular. Count GOT dyn relocs for ifunc.
(allocate_local_dynrelocs): New function.
(_bfd_sparc_elf_size_dynamic_sections): Invoke it over the local hash table.
Emit dynamic relocs to irelplt when not shared. Treat iplt like splt.
(_bfd_sparc_elf_relocate_section): Handle ifunc relocations by hand.
(_bfd_sparc_elf_finish_dynamic_symbol): Adjust for non-dynamic ifunc plt
in iplt/irelplt.
ld/testsuite/
* ld-ifunc/ifunc.exp: Run for sparc.
Iain Buclaw
Jose E. Marchesi
Will Newton
Kuan-Lin Chen
Andrew Bennett
Jiong Wang
DJ Delorie
Maciej W. Rozycki
Nick Clifton
Alan Modra
Matthew Fortune
Barney Stratford
Richard Sandiford
Steve Ellcey
Christian Svensson
Tristan Gingold
Denis Chertykov
Jon TURNEY
Tristan Gingold
Mike Frysinger
Doug Evans
Andrew Pinski
Sandra Loosemore
Ulrich Weigand
tromey
Tom Tromey
Bill Maddox
Joel Brobecker
rsandifo
Yufeng Zhang
H.J. Lu
Catherine Moore
glisse
gerald
sterling
Pedro Alves
Chao-ying Fu
Sean Keys
Steve Ellcey
Eric Botcazou
Maciej W. Rozycki
Andreas Krebbel
Will Newton
Catherine Moore
Denis Chertykov
David S. Miller
Kyrylo Tkachov
Cary Coutant
Sriraman Tallam
Kai Tietz
Peter Bergner
Joel Brobecker
Michael Eager
Nathan Sidwell
Dave Anglin
Anthony Green
Richard Earnshaw
Walter Lee
Matthew Gretton-Dann
Doug Evans
Iain Sandoe
Rafael Ávila de Espíndola
James Lemke
Roland McGrath
Kevin Buettner
Jason Merrill
Chung-Lin Tang
Ulrich Weigand
Joern Rennecke
Jakub Jelinek
Thomas Schwinge
Eric B. Weddington
Paul Brook
Jan Kratochvil
Bernd Schmidt
Andrew Burgess
Joseph Myers
Dave Korn
Rainer Orth
Martin Schwidefsky