binutils-gdb/gas/ChangeLog

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2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Use a switch on the
microMIPS relaxation type rather than a chain of conditionals.
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Rewrite `fix_new_exp'
calls in terms of `fix_new'.
MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxation Use frag symbols with a non-zero offset directly in `fix_new_exp' calls made in PIC branch relaxation. There is no need here to make a helper symbol to hold the result of a `symbol+offset' calculation requested as only branches to local symbols are relaxed and in this case the LO16 part of the PIC address load sequence will have the offset accounted for in calculation against the local GOT entry retrieved as the GOT16 high part. Consequently actual code produed is identical whether a helper symbol is used or the original `symbol+offset' expression used directly. Verify that this is indeed the case with GAS and LD tests. gas/ * config/tc-mips.c (md_convert_frag): Don't make a helper expression symbol for `fix_new_exp' called with a non-zero offset. * testsuite/gas/mips/relax-offset.d: New test. * testsuite/gas/mips/mips1@relax-offset.d: New test. * testsuite/gas/mips/r3000@relax-offset.d: New test. * testsuite/gas/mips/r3900@relax-offset.d: New test. * testsuite/gas/mips/micromips@relax-offset.d: New test. * testsuite/gas/mips/relax-offset.l: New stderr output. * testsuite/gas/mips/relax-offset.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/relax-offset.dd: New test. * testsuite/ld-mips-elf/relax-offset.gd: New test. * testsuite/ld-mips-elf/relax-offset-umips.dd: New test. * testsuite/ld-mips-elf/relax-offset-umips.gd: New test. * testsuite/ld-mips-elf/relax-offset.ld: New test linker script. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. (prune_warnings): New temporary procedure.
2017-07-01 01:42:19 +02:00
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Don't make a helper
expression symbol for `fix_new_exp' called with a non-zero
offset.
* testsuite/gas/mips/relax-offset.d: New test.
* testsuite/gas/mips/mips1@relax-offset.d: New test.
* testsuite/gas/mips/r3000@relax-offset.d: New test.
* testsuite/gas/mips/r3900@relax-offset.d: New test.
* testsuite/gas/mips/micromips@relax-offset.d: New test.
* testsuite/gas/mips/relax-offset.l: New stderr output.
* testsuite/gas/mips/relax-offset.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add support for a __gcc_isr pseudo isntruction to the AVR assembler. PR gas/21683 include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr. gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it. (AVR Pseudo Instructions): New node. * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook. (md_undefined_symbol): Define to avr_undefined_symbol. (avr_pre_output_hook, avr_undefined_symbol): New protos. * config/tc-avr.c (struc-symbol.h): Include it. (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums. (avr_isr, avr_gccisr_opcode) (avr_no_sreg_hash, avr_no_sreg): New static variables. (avr_opt_s) <have_gccisr>: Add field. (avr_opt): Add initializer for have_gccisr. (enum options) <OPTION_HAVE_GCCISR>: Add enum. (md_longopts) <"mgcc-isr">: Add entry. (md_show_usage): Document -mgcc-isr. (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it. (md_undefined_symbol): Remove. (avr_undefined_symbol, avr_pre_output_hook): New fuctions. (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them. (avr_operand) <pregno>: Add argument and set *pregno if function is called for a register constraint. [N]: Handle constraint. (avr_operands) <avr_operand>: Pass 5th parameter to calls. [avr_opt.have_gccisr]: Call avr_update_gccisr. Call avr_gccisr_operands instead of avr_operands. (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag) (avr_gccisr_operands, avr_check_gccisr_done): New static functions. * testsuite/gas/avr/gccisr-01.d: New test. * testsuite/gas/avr/gccisr-01.s: New test. * testsuite/gas/avr/gccisr-02.d: New test. * testsuite/gas/avr/gccisr-02.s: New test. * testsuite/gas/avr/gccisr-03.d: New test. * testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30 17:37:39 +02:00
2017-06-30 Georg-Johann Lay <avr@gjlay.de>
PR gas/21683
* doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_float_constant): Update description.
(match_operand): Likewise.
2017-06-30 08:21:56 +02:00
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
MIPS: Fix XPA base and Virtualization ASE instruction handling Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30 08:21:55 +02:00
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
MIPS/GAS: Clear the ASE_MIPS16E2_MT flag for recalculation Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which is not correctly calculated as `.set nomips16e2' and `.set nomt' pseudo-ops are processed. This leads to code like: $ cat foo.s .set nomt evpe .align 4, 0 $ cat bar.s .set nomips16e2 dvpe .align 4, 0 $ to successfully assemble where it should not: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s $ objdump -m mips:16 -d foo.o foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f027 6700 evpe ... bar.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f026 6700 dvpe ... $ This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never cleared. Fix the problem by clearing it there before it is calculated based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as expected: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s foo.s: Assembler messages: foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe' $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s bar.s: Assembler messages: bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe' $ gas/ * config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT flag before recalculating. * testsuite/gas/mips/mips16e2-mt-err.d: New test. * testsuite/gas/mips/mips16e2-mt-err.l: New stderr output. * testsuite/gas/mips/mips16e2-mt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30 01:55:07 +02:00
2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT
flag before recalculating.
* testsuite/gas/mips/mips16e2-mt-err.d: New test.
* testsuite/gas/mips/mips16e2-mt-err.l: New stderr output.
* testsuite/gas/mips/mips16e2-mt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-06-28 Tamar Christina <tamar.christina@arm.com>
* config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B.
(aarch64_features): Added dotprod.
* doc/c-aarch64.texi: Added dotprod.
* testsuite/gas/aarch64/dotproduct.d: New.
* testsuite/gas/aarch64/dotproduct.s: New.
2017-06-28 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
MIPS: Add new Imagination interAptiv MR2 GAS and LD tests Add GAS tests to verify Imagination interAptiv MR2 instruction assembly, disassembly and ELF object file flags. Add LD tests to verify Imagination interAptiv MR2 ELF object file link-time compatibility and flag merging/propagation. Use the framework enhancement added with commit 7575e6a752ec ("MIPS/LD/testsuite: mips-elf-flags: Add MIPS ABI Flags handling"). gas/ * testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test. * testsuite/gas/mips/save-err.d: New test. * testsuite/gas/mips/save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save.d: New test. * testsuite/gas/mips/mips1@save-sub.d: New test. * testsuite/gas/mips/mips2@save-sub.d: New test. * testsuite/gas/mips/mips3@save-sub.d: New test. * testsuite/gas/mips/mips4@save-sub.d: New test. * testsuite/gas/mips/mips5@save-sub.d: New test. * testsuite/gas/mips/mips32@save-sub.d: New test. * testsuite/gas/mips/mips64@save-sub.d: New test. * testsuite/gas/mips/mips16@save-sub.d: New test. * testsuite/gas/mips/mips16e@save-sub.d: New test. * testsuite/gas/mips/r3000@save-sub.d: New test. * testsuite/gas/mips/r3900@save-sub.d: New test. * testsuite/gas/mips/r4000@save-sub.d: New test. * testsuite/gas/mips/vr5400@save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test. * testsuite/gas/mips/sb1@save-sub.d: New test. * testsuite/gas/mips/octeon2@save-sub.d: New test. * testsuite/gas/mips/octeon3@save-sub.d: New test. * testsuite/gas/mips/xlr@save-sub.d: New test. * testsuite/gas/mips/r5900@save-sub.d: New test. * testsuite/gas/mips/mips16e2-copy.d: New test. * testsuite/gas/mips/mips16e2-copy-err.d: New test. * testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name' option. Adjust for trailing padding change. * testsuite/gas/mips/mips16e2-copy-err.l: New stderr output. * testsuite/gas/mips/save-sub.s: New test source. * testsuite/gas/mips/mips16e2-copy.s: New test source. * testsuite/gas/mips/mips16e2-copy-err.s: New test source. * testsuite/gas/mips/save.s: Update description, change trailing padding and remove trailing white space. * testsuite/gas/mips/mips.exp: Expand `save' and `save-err' tests across the regular MIPS interAptiv MR2 architecture. Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2 tests.
2017-06-28 03:07:36 +02:00
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
* testsuite/gas/mips/save-err.d: New test.
* testsuite/gas/mips/save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
* testsuite/gas/mips/mips1@save-sub.d: New test.
* testsuite/gas/mips/mips2@save-sub.d: New test.
* testsuite/gas/mips/mips3@save-sub.d: New test.
* testsuite/gas/mips/mips4@save-sub.d: New test.
* testsuite/gas/mips/mips5@save-sub.d: New test.
* testsuite/gas/mips/mips32@save-sub.d: New test.
* testsuite/gas/mips/mips64@save-sub.d: New test.
* testsuite/gas/mips/mips16@save-sub.d: New test.
* testsuite/gas/mips/mips16e@save-sub.d: New test.
* testsuite/gas/mips/r3000@save-sub.d: New test.
* testsuite/gas/mips/r3900@save-sub.d: New test.
* testsuite/gas/mips/r4000@save-sub.d: New test.
* testsuite/gas/mips/vr5400@save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
* testsuite/gas/mips/sb1@save-sub.d: New test.
* testsuite/gas/mips/octeon2@save-sub.d: New test.
* testsuite/gas/mips/octeon3@save-sub.d: New test.
* testsuite/gas/mips/xlr@save-sub.d: New test.
* testsuite/gas/mips/r5900@save-sub.d: New test.
* testsuite/gas/mips/mips16e2-copy.d: New test.
* testsuite/gas/mips/mips16e2-copy-err.d: New test.
* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
option. Adjust for trailing padding change.
* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
* testsuite/gas/mips/save-sub.s: New test source.
* testsuite/gas/mips/mips16e2-copy.s: New test source.
* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
* testsuite/gas/mips/save.s: Update description, change trailing
padding and remove trailing white space.
* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
tests across the regular MIPS interAptiv MR2 architecture. Run
the new tests.
MIPS: Add Imagination interAptiv MR2 GAS test infrastructure Define a new regular MIPS and MIPS16 interAptiv MR2 test architecture and adjust existing tests now run against these architectures accordingly. This change causes new test failures: FAIL: MIPS jal-svr4pic (interaptiv-mr2) FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2) with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are consistent with the remaining architecture results for these cases, that do not take into account the lack of R_MIPS_JALR relocations produced by GAS for these targets. As a preexisting issue these failures are not addressed with this change. gas/ * testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture. (mips16e2-interaptiv-mr2): Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d: New test. * testsuite/gas/mips/interaptiv-mr2@mcu.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test. * testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE flag lines present rather than just one. * testsuite/gas/mips/attr-gnu-4-6.d: Likewise. * testsuite/gas/mips/attr-gnu-4-7.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64.d: Likewise. * testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr output.
2017-06-28 03:07:36 +02:00
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
(mips16e2-interaptiv-mr2): Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d:
New test.
* testsuite/gas/mips/interaptiv-mr2@mcu.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test.
* testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE
flag lines present rather than just one.
* testsuite/gas/mips/attr-gnu-4-6.d: Likewise.
* testsuite/gas/mips/attr-gnu-4-7.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l:
New stderr output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr
output.
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-28 03:07:36 +02:00
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e-save.d: Rename to...
* testsuite/gas/mips/save.d: ... this.
* testsuite/gas/mips/mips16e-save-err.d: Update the
`error-output' option and rename to...
* testsuite/gas/mips/save-err.d: ... this.
* testsuite/gas/mips/mips16e-save-err.l: Rename to...
* testsuite/gas/mips/save-err.l: ... this.
* testsuite/gas/mips/mips16e-save.s: Rename to...
* testsuite/gas/mips/save.s: ... this.
* testsuite/gas/mips/mips16e-save-err.s: Rename to...
* testsuite/gas/mips/save-err.s: ... this.
* testsuite/gas/mips/mips.exp: Rename `mips16e-save' and
`mips16e-save-err' invocations to `save' and `save-err'
respectively and reorder these tests away from MIPS16 tests.
2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e-save.d: Remove `-mmips:isa32
-mmips:16' from `objdump' flags and `-march=mips32 -mips16' from
`as' flags.
* testsuite/gas/mips/mips16e-save-err.d: Remove `-march=mips32'
from `as' flags.
* testsuite/gas/mips/mips16e-save.s: Remove the `.set mips16'
pseudo-op.
* testsuite/gas/mips/mips16e-save-err.s: Likewise.
* testsuite/gas/mips/mips.exp: Run SAVE/RESTORE tests across all
MIPS16e architectures.
2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e-save-err.d: New test.
* gas/testsuite/gas/mips/mips.exp: Fold `mips16e-save-err' list
test into the new test.
2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e-save.d: Capitalize the `name'
option.
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
2017-06-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/21661
* config/obj-elf.c (obj_elf_symver): Don't allow .symver with
common symbol.
(elf_frob_symbol): Likewise.
* testsuite/gas/elf/elf.exp: Run pr21661.
* testsuite/gas/elf/pr21661.d: New file.
* testsuite/gas/elf/pr21661.s: Likewise.
2017-06-26 Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (fpu_any): Only define for ELF based targets.
2017-06-26 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Mention support of ARM Cortex-R52 processor.
* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
* doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
[ARM] Add support for ARMv8-R in assembler and readelf === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro.
2017-06-24 11:37:47 +02:00
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
[ARM] Remove ARMv6S-M special casing === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to remove special casing for ARMv6S-M autodetection. === Motivation === Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor architectures with extra checks in the handler function (do_t_swi) to give an error message when ARMv6-M is targeted and some more special casing in aeabi_set_public_attributes. This was made to exclude these mnemonics for ARMv6-M unless the OS extension is in use. However this logic is superfluous: there is already code to check whether an instruction is available based on the feature bit it is part of and whether the targeted architecture has that feature bit. This patch aims at removing that unneeded complexity. === Patch description === The OS extension is already limited to the ARMv6-M architecture so all this patch does is redefined availability of the ARM_EXT_OS feature bit to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any change either because it already includes ARM_EXT_OS. The patch also make sure that the error message that was given by do_t_swi when SWI/SVC is unavailable is still the same by detecting the situation in md_assemble. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v6m): Delete. (arm_ext_v7m): Delete. (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M profile. (arm_arch_v6m_only): Delete. (do_t_swi): Remove special case for ARMv6S-M. (md_assemble): Display error message previously in do_t_swi when SVC is not available. (insns): Guard swi and svc by arm_ext_os for Thumb mode. (aeabi_set_public_attributes): Remove special case for ARMv6S-M. include/ * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set. (ARM_AEXT_V4T): Likewise. (ARM_AEXT_V5TxM): Likewise. (ARM_AEXT_V5T): Likewise. (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-24 11:26:41 +02:00
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_ext_v6m): Delete.
(arm_ext_v7m): Delete.
(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
profile.
(arm_arch_v6m_only): Delete.
(do_t_swi): Remove special case for ARMv6S-M.
(md_assemble): Display error message previously in do_t_swi when
SVC is not available.
(insns): Guard swi and svc by arm_ext_os for Thumb mode.
(aeabi_set_public_attributes): Remove special case for ARMv6S-M.
2017-05-11 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (riscv_ip): Changes as_warn to as_bad for improper
shift amounts.
2017-06-22 Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (arm_ext_v7m): Add ATTRIBUTE_UNUSED.
[ARM] Rework Tag_CPU_arch build attribute value selection === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to rework the Tag_CPU_arch build attribute value selection to (i) match architecture or CPU if specified by user without any need for hack and (ii) match an architecture with all the features used if in autodetection mode or return an error. === Motivation === Currently, Tag_CPU_arch build attribute value selection assumes that an architecture is always a superset of architectures released earlier. As such, the logic is to browse architectures in chronological order of release and selecting the Tag_CPU_arch value of the last one to contribute a feature used[1]/requested[2] not contributed by earlier architectures. [1] in case of autodetection mode [2] otherwise, ie. in case of -mcpu/-march or associated directives This logic fails the two objectives mentionned in the Context section. First, due to the assumption it does an architecture can be selected while not having all the features used/requested which fails the second objective. Second, not doing an exact match when an architecture or CPU is selected by the user means the wrong value is chosen when a later architecture provides a subset of the feature bits of an earlier architecture. This is the case for the implementation of ARMv8-R (see later patch). An added benefit of this patch is that it is possible to easily generate more consistent build attribute by setting the feature bits from the architecture matched in aeabi_set_public_attributes in autodetection mode. This is better done as a separate patch because lots of testcase' expected results must then be updated accordingly. === Patch description === The patch changes the main logic for Tag_CPU_arch and Tag_CPU_arch_profile values selection to: - look for an exact match in case an architecture or CPU was specified on the command line or in a directive - select the first released architecture that provides a superset of the feature used in the autodetection case - select the most featureful architecture in case of -march=all The array cpu_arch_ver is updated to include all architectures in order to make the first point work. Note that when looking for an exact match, the architecture with selected extension is tried first and then only the architecture. This is because some architectures are exactly equivalent to an earlier architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS extension) and ARMv6KZ (ARMv6K + security extension) are two such examples. Other adjustments are also necessary in aeabi_set_public_attributes to make this change work. 1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the absence of feature bit used/requested to decide whether to give the default value for empty files (see EABI attribute defaults test). It was previously checking that arch == 0 which would only happen if no feature bit could be matched by any architecture, ie there is no feature bit to match. 2) A fallback to a superset match must exist when no_cpu_selected () returns true. This is because aeabi_set_public_attributes is called again after relaxation and at this point selected_cpu is set from the previous execution of that function. There is therefore no way to check whether the user specified an architecture or CPU. 3) Tag_CPU_arch lines are removed from expected output when the detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch value for pre-ARMv4 architectures and default value for an absent entry is 0. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (fpu_any): Defined from FPU_ANY. (cpu_arch_ver): Add all architectures and sort by release date. (have_ext_for_needed_feat_p): New. (get_aeabi_cpu_arch_from_fset): New. (aeabi_set_public_attributes): Call above function to determine Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use and Tag_THUMB_ISA_use selection logic to check absence of feature bit accordingly. * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build attribute value. * testsuite/gas/arm/attr-march-armv2.d: Likewise. * testsuite/gas/arm/attr-march-armv2a.d: Likewise. * testsuite/gas/arm/attr-march-armv2s.d: Likewise. * testsuite/gas/arm/attr-march-armv3.d: Likewise. * testsuite/gas/arm/attr-march-armv3m.d: Likewise. * testsuite/gas/arm/pr12198-2.d: Likewise. include/ * opcode/arm.h (FPU_ANY): New macro.
2017-06-21 17:32:40 +02:00
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (fpu_any): Defined from FPU_ANY.
(cpu_arch_ver): Add all architectures and sort by release date.
(have_ext_for_needed_feat_p): New.
(get_aeabi_cpu_arch_from_fset): New.
(aeabi_set_public_attributes): Call above function to determine
Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use
and Tag_THUMB_ISA_use selection logic to check absence of feature bit
accordingly.
* testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
attribute value.
* testsuite/gas/arm/attr-march-armv2.d: Likewise.
* testsuite/gas/arm/attr-march-armv2a.d: Likewise.
* testsuite/gas/arm/attr-march-armv2s.d: Likewise.
* testsuite/gas/arm/attr-march-armv3.d: Likewise.
* testsuite/gas/arm/attr-march-armv3m.d: Likewise.
* testsuite/gas/arm/pr12198-2.d: Likewise.
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Update NOTRACK prefix check.
* testsuite/gas/i386/notrack-intel.d: Updated.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
* testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with
memory indirect branch.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.s: Remove memory indirect branch
with NOTRACK prefix.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
[ARM] Allow Thumb division as an extension for ARMv7 === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to allow ARMv7 to be selected in automatic architecture selection in presence of Thumb division instructions. === Motivation === any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect autodetection code to select ARMv7 in presence of Thumb integer division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do not contain these instructions and the idiv extension is only available for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic detection code proposed in the subsequent patch of the series ARMv7 is refused if a Thumb division instruction is present. === Patch description === This patch adds a new "idiv" extension after the existing one that is available to all ARMv7 targets. This new entry is ignored by all current code parsing arm_extensions such that it would be unavailable on the command-line and remain a purely internal hack, easily removed in favor of a better solution later. This is considered though by the subsequent patch reworking automatic detection of build attributes such that ARMv7 is allowed to match in present of Thumb division instructions. For good measure, comments are added in all instances of code browsing arm_extensions to mention the expected behavior in case of duplicate entries as well as a new testcase. 2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable Thumb division for ARMv7 architecture. (arm_parse_extension): Document expected behavior for duplicate entries. (s_arm_arch_extension): Likewise. * testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test. * testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for above test.
2017-06-21 16:06:51 +02:00
2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable
Thumb division for ARMv7 architecture.
(arm_parse_extension): Document expected behavior for duplicate
entries.
(s_arm_arch_extension): Likewise.
* testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test.
* testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for
above test.
[ARM] Rework selection of feature bits to base build attributes on === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to set the feature bits on which to decide what the build attributes should be according to the mode (autodetection, user specified architecture or CPU, or -march/-mcpu=all). === Motivation === Currently, the flags variable which is used to determine the build attribute is constructed from the instruction used (arm_arch_used and thumb_arch_used) as well as the user specified architecture or CPU (selected_cpu). This means when several .arch are specified the resulting feature bits can be such that no architecture provide them all and can thus result in incorrect Tag_CPU_arch. See for instance what having both .arch armv8-a and .arch armv8-m.base would result in. This is not caught by the testsuite because of further bugs in the Tag_CPU_arch build attribute value selection logic (see next patch in the series). === Patch description === As one would expect, this patch solves the problem by setting flags from feature bits used if in autodetection mode [1] and from selected_cpu otherwise. The logic to set arm_ext_v1, arm_ext_v4t and arm_ext_os feature bits is also moved to only run in autodetection mode since otherwise the architecture or CPU would have a consistent set of feature bits already. [1] No architecture or CPU was specified by the user 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Populate flags from feature bits used or selected_cpu depending on whether a CPU was selected by the user.
2017-06-21 15:57:53 +02:00
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Populate flags from
feature bits used or selected_cpu depending on whether a CPU was
selected by the user.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to
decide whether to set Tag_DSP_extension build attribute value. Remove
now useless arm_arch variable.
[ARM] Keep separation between extensions and architecture bits throughout execution === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to keep the distinction between architecture feature bits and extension ones after parsing has occured. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. The previous patch in the patch series makes the distinction possible when parsing -mcpu and .cpu directives but the distinction gets lost after. Similarly feature bits contributed by extensions in -march or .arch_extensions directive are mixed together with architecture extensions. === Patch description === The patch adds new feature bit pointer for extension feature bits. Information from the parsing regarding extensions can then be kept separate in those. This requires adapting arm_parse_extension to deal with two feature bits, allowing the architecture bits to be marked as const. It also requires extra care when setting cpu_variant and selected_cpu because the extension bits are optional since there might not be any extension in use. Note that contrary to cpu feature bits, the extension feature bits are made read/write and are always dynamically allocated. This allows to unconditionally free them in arm_md_post_relax added for this occasion, thereby fixing a longstanding memory leak when arm_parse_extension was invoked (XNEW of ext_fset without corresponding XDELETE). Introduction of arm_md_post_relax is necessary to only free the extension feature bits after aeabi_set_attribute_string has been called for the last time. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (dyn_mcpu_ext_opt): New static variable. (dyn_march_ext_opt): Likewise. (md_begin): Copy extension feature bits alongside architecture ones. Merge extensions feature bits in selected_cpu and cpu_variant if there is some. (arm_parse_extension): Pass architecture and extension feature bits in separate parameters, with architecture bits being read only. Update **opt_p directly rather than *ext_set and initialize it if needed. (arm_parse_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Adapt to change in parameters of arm_parse_extension. (arm_parse_arch): Adapt to change in parameters of arm_parse_extension. (aeabi_set_attribute_string): Make function static. (arm_md_post_relax): New function. (s_arm_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Merge extension feature bits in cpu_variant if there is any. (s_arm_arch): Reset extension feature bit. Set selected_cpu from *mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for consistency with s_arm_cpu. (s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than selected_cpu, allocating it before hand if needed. Set selected_cpu from it and then cpu_variant. (s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant. * config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax. (aeabi_set_public_attributes): Delete external declaration. (arm_md_post_relax): Declare externally.
2017-06-21 15:08:08 +02:00
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (dyn_mcpu_ext_opt): New static variable.
(dyn_march_ext_opt): Likewise.
(md_begin): Copy extension feature bits alongside architecture ones.
Merge extensions feature bits in selected_cpu and cpu_variant if there
is some.
(arm_parse_extension): Pass architecture and extension feature bits in
separate parameters, with architecture bits being read only. Update
**opt_p directly rather than *ext_set and initialize it if needed.
(arm_parse_cpu): Stop merging architecture and extension feature bits
and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
respectively. Adapt to change in parameters of arm_parse_extension.
(arm_parse_arch): Adapt to change in parameters of arm_parse_extension.
(aeabi_set_attribute_string): Make function static.
(arm_md_post_relax): New function.
(s_arm_cpu): Stop merging architecture and extension feature bits and
instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
respectively. Merge extension feature bits in cpu_variant
if there is any.
(s_arm_arch): Reset extension feature bit. Set selected_cpu from
*mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for
consistency with s_arm_cpu.
(s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than
selected_cpu, allocating it before hand if needed. Set selected_cpu
from it and then cpu_variant.
(s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant.
* config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax.
(aeabi_set_public_attributes): Delete external declaration.
(arm_md_post_relax): Declare externally.
[ARM] Separate extensions from architectures in arm_cpus === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to distinguish for a CPU the feature bits coming from its architecture from the feature bits coming from extension(s) available in this CPU. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. === Patch description === The patch creates a new field in the arm_cpus table to hold the feature set for the extensions available in each CPU. The existing architecture feature set is then updated to remove those feature bit. The patch also takes advantage of all the lines being changed to reindent the whole table. Note: This patch *adds* a memory leak due to mcpu_cpu_opt sometimes pointing to dynamically allocated feature bits which is never freeed. The subsequent patch in the series solves this issue as well as a preexisting identical issue in arm_parse_extension. The patches are kept separate for ease of review since they are both big enough already. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_cpu_option_table): New ext field. (ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical name field just after the name field. (arm_cpus): Move extension feature bit from value field to ext field, reorder parameter according to changes in ARM_CPU_OPT and reindent. (arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and ext field from the selected arm_cpus entry. (s_arm_cpu): Likewise.
2017-06-21 14:16:56 +02:00
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (struct arm_cpu_option_table): New ext field.
(ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical
name field just after the name field.
(arm_cpus): Move extension feature bit from value field to ext field,
reorder parameter according to changes in ARM_CPU_OPT and reindent.
(arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and
ext field from the selected arm_cpus entry.
(s_arm_cpu): Likewise.
2017-06-21 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75.
* doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75.
2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/21594
* testsuite/gas/i386/mpx.s: Add 2 tests with invalid bnd
register.
* testsuite/gas/i386/x86-64-mpx.s: Likewise.
* testsuite/gas/i386/mpx.d: Updated.
* testsuite/gas/i386/x86-64-mpx.d: Likewise.
2017-06-14 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (density_supported, xtensa_fetch_width,
absolute_literals_supported): Leave definitions uninitialized.
(directive_state): Leave entries for directive_density and
directive_absolute_literals initialized to false.
(xg_init_global_config, xtensa_init): New functions.
* config/tc-xtensa.h (TARGET_BYTES_BIG_ENDIAN): Define as 0.
(HOST_SPECIAL_INIT): New definition.
(xtensa_init): New declaration.
2017-06-07 Michael Collison <michael.collison@arm.com>
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
IP1, FP, and LR as register aliases of register 16, 17, 29
and 30 respectively.
* testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
prohibiting register 'lr' which is now an alias.
* testsuite/gas/aarch64/diagnostic.s: Remove instruction
utilizing register 'lr' which is now an alias.
[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-A For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through the "reject_bad_reg" macro and several scattered checks. This patch only rejects REG_SP in "reject_bad_reg" and several related places for legacy architectures before ARMv8-A. I have checked those affected instructions , all of them qualify such relaxations. Testcases adjusted accordingly. * ld-sp-warn.d was written without .arch and without -march options passed. By default it assumes all architectures, so I deleted the REG_SP warning on ldrsb as it's supported on ARMv8-A. There are actually quite a few seperate tests on other architectures, for example ld-sp-warn-v7.l etc., so there the test for ldrsb on legacy architectures are still covered. * sp-pc-validations-bad-t has been extended to armv8-a. * strex-bad-t.d restricted on armv7-a. * Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*. gas/ * config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A. (parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on ARMv8-A. (do_co_reg): Allow REG_SP for Rd on ARMv8-A. (do_t_add_sub): Likewise. (do_t_mov_cmp): Likewise. (do_t_tb): Likewise. * testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for ldrsb. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test. * testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a. * testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a". * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax.s: New test. * testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
2017-05-25 11:40:07 +02:00
2017-06-06 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
2017-06-05 Jim Wilson <jim.wilson@linaro.org>
* config/tc-arm.c (arm_cpus): Delete falkor and qdf24xx entries.
* doc/c-arm.texi (-mcpu): Likewise.
2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
* config/tc-arc.c (cpu_types): Include arc-cpu.def
2017-05-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/testsuite/gas/i386/notrackbad.l: Updated for non-ELF
targets.
* gas/testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_apply_fix): Use as_bad_where.
(assemble_insn): Use as_bad.
x86: Add NOTRACK prefix support For register indirect branches, NOTRACK prefix (0x3e), which is also the DS segment register prefix, can be used to ignore the CET indirect branch track. gas/ * config/tc-i386.c (REX_PREFIX): Changed to 7. (NOTRACK_PREFIX): New. (MAX_PREFIXES): Changed to 8. (_i386_insn): Add notrack_prefix. (PREFIX_GROUP): Add PREFIX_DS. (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE. (md_assemble): Check if NOTRACK prefix is supported. (parse_insn): Set notrack_prefix and issue an error for other prefixes after NOTRACK prefix. * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix. * testsuite/gas/i386/notrack-intel.d: New file. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrack.s: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/notrackbad.s: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. include/ * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New. opcodes/ * i386-dis.c (NOTRACK_Fixup): New. (NOTRACK): Likewise. (NOTRACK_PREFIX): Likewise. (last_active_prefix): Likewise. (reg_table): Use NOTRACK on indirect call and jmp. (ckprefix): Set last_active_prefix. (prefix_name): Return "notrack" for NOTRACK_PREFIX. * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. * i386-opc.h (NoTrackPrefixOk): New. (i386_opcode_modifier): Add notrackprefixok. * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. Add notrack. * i386-tbl.h: Regenerated.
2017-05-22 20:02:46 +02:00
2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (REX_PREFIX): Changed to 7.
(NOTRACK_PREFIX): New.
(MAX_PREFIXES): Changed to 8.
(_i386_insn): Add notrack_prefix.
(PREFIX_GROUP): Add PREFIX_DS.
(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
(md_assemble): Check if NOTRACK prefix is supported.
(parse_insn): Set notrack_prefix and issue an error for
other prefixes after NOTRACK prefix.
* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
* testsuite/gas/i386/notrack-intel.d: New file.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/notrackbad.s: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
2017-05-22 Jiong Wang <jiong.wang@arm.com>
* configure.tgt: Set "arch" to "aarch64" if ${cpu} equals "aarch64".
Recognize the new triplet name aarch64*-linux-gnu_ilp32.
* configure.ac: Output DEFAULT_ARCH macro for AArch64.
* configure: Regenerate.
* config/tc-aarch64.h (aarch64_after_parse_args): New declaration.
(md_after_parse_args): New define.
* config/tc-aarch64.c (aarch64_abi_type): New enumeration
AARCH64_ABI_NONE.
(DEFAULT_ARCH): New define.
(aarch64_abi): Set default value to AARCH64_ABI_NONE.
(aarch64_after_parse_args): New function.
binutils: support for the SPARC M8 processor This patch adds support for the new SPARC M8 processor (implementing OSA 2017) to binutils. New instructions: - Dictionary Unpack + dictunpack - Partitioned Compare with shifted result + Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl - Partitioned Dual-Equal compared, with shifted result + fpcmpde{8,16,32}shl - Partitioned Unsigned Range Compare, with shifted result + fpcmpur{8,16,32}shl - 64-bit shifts on Floating-Point registers + fps{ll,ra,rl}64x - Misaligned loads and stores + ldm{sh,uh,sw,uw,x,ux} + ldm{sh,uh,sw,uw,x,ux}a + ldmf{s,d} + ldmf{s,d}a + stm{h,w,x} + stm{h,w,x}a + stmf{s,d} + stmf{s,d}a - Oracle Numbers + on{add,sub,mul,div} - Reverse Bytes/Bits + revbitsb + revbytes{h,w,x} - Run-Length instructions + rle_burst + rle_length - New crypto instructions + sha3 - Instruction to read the new register %entropy + rd %entropy New Alternate Address Identifiers: - 0x24, #ASI_CORE_COMMIT_COUNT - 0x24, #ASI_CORE_SELECT_COUNT - 0x48, #ASI_ARF_ECC_REG - 0x53, #ASI_ITLB_PROBE - 0x58, #ASI_DSFAR - 0x5a, #ASI_DTLB_PROBE_PRIMARY - 0x5b, #ASI_DTLB_PROBE_REAL - 0x64, #ASI_CORE_SELECT_COMMIT_NHT The new assembler command-line options for selecting the M8 architecture are: -Av9m8 or -Asparc6 for 64-bit binaries. -Av8plusm8 for 32-bit (v8+) binaries. The corresponding disassembler command-line options are: -msparc:v9m8 for 64-bit binaries. -msparc:v8plusm8 for 32-bit (v8+) binaries. Tested for regressions in the following targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux bfd/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v9m8): Define. (bfd_mach_sparc_v8plusm8): Likewise. (bfd_mach_sparc_v9_p): Adjust to M8. (bfd_mach_sparc_64bit_p): Likewise. * aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and bfd_mach_sparc_v8plusm8. * bfd-in2.h: Regenerated. * cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and sparc:v8plusm8. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and SHA3. * elf32-sparc.c (elf32_sparc_final_write_processing): Handle bfd_mach_sparc_v8plusm8. binutils/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Mention the SPARC M8 support. gas/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6', `v9m8' and `v8plusm8'. (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8. (get_hwcap_name): Support the M8 hardware capabilities. (sparc_ip): Handle new operand types. * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and -Asparc6, and the corresponding -xarch aliases. * testsuite/gas/sparc/sparc6.s: New file. * testsuite/gas/sparc/sparc6.d: Likewise. * testsuite/gas/sparc/sparc6-diag.s: Likewise. * testsuite/gas/sparc/sparc6-diag.l: Likewise. * testsuite/gas/sparc/fpcmpshl.s: Likewise. * testsuite/gas/sparc/fpcmpshl.d: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise. * testsuite/gas/sparc/ldm-stm.s: Likewise. * testsuite/gas/sparc/ldm-stm.d: Likewise. * testsuite/gas/sparc/ldm-stm-diag.s: Likewise. * testsuite/gas/sparc/ldm-stm-diag.l: Likewise. * testsuite/gas/sparc/ldmf-stmf.s: Likewise. * testsuite/gas/sparc/ldmf-stmf.d: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise. * testsuite/gas/sparc/on.s: Likewise. * testsuite/gas/sparc/on.d: Likewise. * testsuite/gas/sparc/on-diag.s: Likewise. * testsuite/gas/sparc/on-diag.l: Likewise. * testsuite/gas/sparc/rle.s: Likewise. * testsuite/gas/sparc/rle.d: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests. * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY. * testsuite/gas/sparc/rdasr.d: Likewise. include/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define. (ELF_SPARC_HWCAP2_ONADDSUB): Likewise. (ELF_SPARC_HWCAP2_ONMUL): Likewise. (ELF_SPARC_HWCAP2_ONDIV): Likewise. (ELF_SPARC_HWCAP2_DICTUNP): Likewise. (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise. (ELF_SPARC_HWCAP2_RLE): Likewise. (ELF_SPARC_HWCAP2_SHA3): Likewise. * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8 and adjust SPARC_OPCODE_ARCH_MAX. (HWCAP2_SPARC6): Define. (HWCAP2_ONADDSUB): Likewise. (HWCAP2_ONMUL): Likewise. (HWCAP2_ONDIV): Likewise. (HWCAP2_DICTUNP): Likewise. (HWCAP2_FPCMPSHL): Likewise. (HWCAP2_RLE): Likewise. (HWCAP2_SHA3): Likewise. (OPM): Likewise. (OPMI): Likewise. (ONFCN): Likewise. (REVFCN): Likewise. (SIMM10): Likewise. opcodes/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. (X_IMM2): Define. (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8. (print_insn_sparc): Handle new operand types. * sparc-opc.c (MASK_M8): Define. (v6): Add MASK_M8. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Likewise. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (v9andleon): Likewise. (m8): Define. (HWS_VM8): Define. (HWS2_VM8): Likewise. (sparc_opcode_archs): Add entry for "m8". (sparc_opcodes): Add OSA2017 and M8 instructions dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, fpx{ll,ra,rl}64x, ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19 18:27:08 +02:00
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/call-relax.d: Support 32-bit targets.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Use -64 to
run asi-bump-warn.
2017-05-19 Georg-Johann Lay <avr@gjlay.de>
PR ld/21472
* config/tc-avr.c (mcu_types): Add entries for: attiny416,
attiny417, attiny816, attiny817.
2017-05-18 Alan Modra <amodra@gmail.com>
* config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE.
* config/tc-hppa.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-score7.c: Likewise.
2017-05-16 Alan Modra <amodra@gmail.com>
* write.c (GENERIC_FORCE_RELOCATION_LOCAL): Define.
(TC_FORCE_RELOCATION_LOCAL): Use it.
(GENERIC_FORCE_RELOCATION_SUB_SAME): Define.
(TC_FORCE_RELOCATION_SUB_SAME): Use it.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL,
TC_FORCE_RELOCATION_SUB_SAME): Use GENERIC defines.
* config/tc-aarch64.h: Similarly.
* config/tc-avr.h: Similarly.
* config/tc-cris.h: Similarly.
* config/tc-i386.h: Similarly.
* config/tc-i960.h: Similarly.
* config/tc-ia64.h: Similarly.
* config/tc-microblaze.h: Similarly.
* config/tc-mips.h: Similarly.
* config/tc-msp430.h: Similarly.
* config/tc-nds32.h: Similarly.
* config/tc-pru.h: Similarly.
* config/tc-riscv.h: Similarly.
* config/tc-rl78.h: Similarly.
* config/tc-s390.h: Similarly.
* config/tc-sh.h: Similarly.
* config/tc-sh64.h: Similarly.
* config/tc-sparc.h: Similarly.
* config/tc-xtensa.h: Similarly.
* config/tc-mn10300.h: Similarly.
(GENERIC_FORCE_RELOCATION_LOCAL): Define.
* config/tc-msp430.c (msp430_force_relocation_local): Modify to
be addition to rather than replacement of standard
TC_FORCE_RELOCATION_LOCAL.
2017-05-15 Nick Clifton <nickc@redhat.com>
PR gas/21458
* config/tc-arm.c (do_adr): If the ADR involves a thumb function
symbol, ensure that the T bit will be set.
(do_adrl): Likewise.
(do_t_adr): Likewise.
* testsuite/gas/arm/pr21458.s: New test.
* testsuite/gas/arm/pr21458.d: New test driver.
MIPS16e2: Add new MIPS16e2 relaxation GAS and LD tests Verify MIPS16 PC-relative instruction relaxation using the MIPS16e2 LUI instruction rather than an LI/SLL instruction pair. gas/ * testsuite/gas/mips/mips16-pcrel-1.d: Remove `-mips3' from `as' flags. * testsuite/gas/mips/mips16-pcrel-pic-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-5.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-5.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-2.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-3.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-5.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-1.l: Adjust line numbers. * testsuite/gas/mips/mips16-pcrel-1.s: Adjust for alignment preservation between MIPS16 and MIPS16e2 code. * testsuite/gas/mips/mips.exp: Run MIPS16 relaxation tests over all MIPS16 architectures. ld/ * testsuite/ld-mips-elf/mips16e2-pcrel-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-1.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-2.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-6.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-1.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-05-15 14:52:04 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-pcrel-1.d: Remove `-mips3' from `as'
flags.
* testsuite/gas/mips/mips16-pcrel-pic-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-4.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-5.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-7.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-9.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-2.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-3.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-7.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
Likewise.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-2.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-2.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-3.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-6.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-7.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-2.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-3.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-6.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-7.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-8.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-9.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-8.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-9.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-8.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-9.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute.d: New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-1.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-2.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-3.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-4.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-5.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-6.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-7.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-4.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-6.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-4.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-6.d: New
test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-4.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-6.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-4.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-6.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-4.d:
New test.
* testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-6.d:
New test.
* testsuite/gas/mips/mips16-pcrel-1.l: Adjust line numbers.
* testsuite/gas/mips/mips16-pcrel-1.s: Adjust for alignment
preservation between MIPS16 and MIPS16e2 code.
* testsuite/gas/mips/mips.exp: Run MIPS16 relaxation tests over
all MIPS16 architectures.
MIPS16e2: Add new MIPS16e2 ASE binutils and GAS tests Verify MIPS16e2 ASE instruction assembly, disassembly and object file flags. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Add `-mips3' to `as' flags. * testsuite/binutils-all/mips/mips16e2-undecoded.d: New test. * testsuite/binutils-all/mips/mips16e2-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-undecoded.s: Remove `.module mips3'. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/mips16e2.d: New test. * testsuite/gas/mips/mips16e2-mt.d: New test. * testsuite/gas/mips/mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-hilo.d: New test. * testsuite/gas/mips/mips16e2-hilo-n32.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.d: New test. * testsuite/gas/mips/mips16e2-imm-error.d: New test. * testsuite/gas/mips/elf_ase_mips16e2.d: New test. * testsuite/gas/mips/elf_ase_mips16e2-2.d: New test. * testsuite/gas/mips/elf-rel9-mips16e2.d: New test. * testsuite/gas/mips/mips16e2-lui.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test. * testsuite/gas/mips/mips16e2@lui-2.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output. * testsuite/gas/mips/mips16e2-imm-error.l: New stderr output. * testsuite/gas/mips/mips16e2@lui-2.l: New stderr output. * testsuite/gas/mips/mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-mt.s: New test source. * testsuite/gas/mips/mips16e2-sub.s: New test source. * testsuite/gas/mips/mips16e2-mt-sub.s: New test source. * testsuite/gas/mips/mips16e2-hilo.s: New test source. * testsuite/gas/mips/mips16e2-reloc-error.s: New test source. * testsuite/gas/mips/mips16e2-imm-error.s: New test source. * testsuite/gas/mips/elf-rel9-mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-lui.s: New test source. * testsuite/gas/mips/mips.exp: Expand `mips32r2-sync', `mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2 architectures. Run the new tests.
2017-05-15 14:45:42 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-mt.d: New test.
* testsuite/gas/mips/mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2-hilo.d: New test.
* testsuite/gas/mips/mips16e2-hilo-n32.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.d: New test.
* testsuite/gas/mips/mips16e2-imm-error.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2-2.d: New test.
* testsuite/gas/mips/elf-rel9-mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-lui.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips16e2@lui-2.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output.
* testsuite/gas/mips/mips16e2-imm-error.l: New stderr output.
* testsuite/gas/mips/mips16e2@lui-2.l: New stderr output.
* testsuite/gas/mips/mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-mt.s: New test source.
* testsuite/gas/mips/mips16e2-sub.s: New test source.
* testsuite/gas/mips/mips16e2-mt-sub.s: New test source.
* testsuite/gas/mips/mips16e2-hilo.s: New test source.
* testsuite/gas/mips/mips16e2-reloc-error.s: New test source.
* testsuite/gas/mips/mips16e2-imm-error.s: New test source.
* testsuite/gas/mips/elf-rel9-mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-lui.s: New test source.
* testsuite/gas/mips/mips.exp: Expand `mips32r2-sync',
`mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2
architectures. Run the new tests.
MIPS16e2: Add MIPS16e2 ASE GAS test infrastructure Define a new 32-bit and 64-bit MIPS16e2 test architecture and adjust existing tests now run against these architectures accordingly. gas/ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add `mips16e2@' prefix. (run_list_test_arch): Likewise. (mips16e2-32, mips16e2-64): New architectures. * testsuite/gas/mips/mips16e2-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e2-32@mips16e-64.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e2-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e2@relax-swap3.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: Remove `source' tag. Add `-I$srcdir/$subdir' to `as' flags. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: Likewise. * testsuite/gas/mips/mips16e2-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-sub.s: Add `.set nomips16e2'. * testsuite/gas/mips/mips16e-sub.s: Likewise. * testsuite/gas/mips/mips16e-64-sub.s: Likewise. * testsuite/gas/mips/mips16-asmacro.s: Remove `.set mips32'. * testsuite/gas/mips/mips16-32@mips16-asmacro.s: New test source. * testsuite/gas/mips/mips16-64@mips16-asmacro.s: New test source.
2017-05-15 14:40:50 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e2@' prefix.
(run_list_test_arch): Likewise.
(mips16e2-32, mips16e2-64): New architectures.
* testsuite/gas/mips/mips16e2-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16e-64.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e2@relax-swap3.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: Remove `source'
tag. Add `-I$srcdir/$subdir' to `as' flags.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: Likewise.
* testsuite/gas/mips/mips16e2-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-sub.s: Add `.set nomips16e2'.
* testsuite/gas/mips/mips16e-sub.s: Likewise.
* testsuite/gas/mips/mips16e-64-sub.s: Likewise.
* testsuite/gas/mips/mips16-asmacro.s: Remove `.set mips32'.
* testsuite/gas/mips/mips16-32@mips16-asmacro.s: New test
source.
* testsuite/gas/mips/mips16-64@mips16-asmacro.s: New test
source.
MIPS16e2: Add MIPS16e2 ASE support Add MIPS16e2 ASE support as per the architecture specification[1], including in particular: 1. A new ELF ASE flag to mark MIPS16e2 binaries. 2. MIPS16e2 instruction assembly support, including a relaxation update to use LUI rather than an LI/SLL instruction pair for loading the high part of 32-bit addresses. 3. MIPS16e2 instruction disassembly support, including updated rules for extended forms of instructions that are now subdecoded and therefore do not alias to the original MIPS16 ISA revision instructions even for encodings that are not valid in the MIPS16e2 instruction set. Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and `.module' pseudo-ops. Control the availability of the MT ASE subset of the MIPS16e2 instruction set with a combination of these controls and the preexisting MT ASE controls. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific Extension Technical Reference Manual", Imagination Technologies Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016 include/ * elf/mips.h (AFL_ASE_MIPS16E2): New macro. (AFL_ASE_MASK): Adjust accordingly. * opcode/mips.h: Document new operand codes defined. (mips_operand_type): Add OP_REG28 enum value. (INSN2_SHORT_ONLY): Update description. (ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros. bfd/ * elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. (print_insn_arg) <OP_REG28>: Add handler. (validate_insn_args) <OP_REG28>: Handle. (print_mips16_insn_arg): Handle MIPS16 instructions that require 32-bit encoding and 9-bit immediates. (print_insn_mips16): Handle MIPS16 instructions that require 32-bit encoding and MFC0/MTC0 operand decoding. * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. (RD_C0, WR_C0, E2, E2MT): New macros. (mips16_opcodes): Add entries for MIPS16e2 instructions: GP-relative "addiu" and its "addu" spelling, "andi", "cache", "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" instructions, "swl", "swr", "sync" and its "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, "xori", "dmt", "dvpe", "emt" and "evpe". Add split regular/extended entries for original MIPS16 ISA revision instructions whose extended forms are subdecoded in the MIPS16e2 ISA revision: "li", "sll" and "srl". binutils/ * readelf.c (print_mips_ases): Handle MIPS16e2 ASE. * NEWS: Mention MIPS16e2 ASE support. gas/ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag. (RELAX_MIPS16_E2): New macro. (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO) (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT) (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT) (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED) (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED) (RELAX_MIPS16_MARK_ALWAYS_EXTENDED) (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO) (RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits. (mips16_immed_extend): New prototype. (options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum values. (md_longopts): Add "mmips16e2" and "mno-mips16e2" options. (mips_ases): Add "mips16e2" entry. (mips_set_ase): Handle MIPS16e2 ASE. (insn_insert_operand): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (is_opcode_valid_16): Pass enabled ASE bitmask on to `opcode_is_member'. (validate_mips_insn): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (operand_reg_mask) <OP_REG28>: Add handler. (match_reg28_operand): New function. (match_operand) <OP_REG28>: Add handler. (append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE. (match_mips16_insn): Handle MIPS16 instructions that require 32-bit encoding and `V' and `u' operand codes. (mips16_ip): Allow any characters except from `.' in opcodes. (mips16_immed_extend): Handle 9-bit immediates. Do not shuffle immediates whose width is not one of these listed. (md_estimate_size_before_relax): Handle MIPS16e2 relaxation. (mips_relax_frag): Likewise. (md_convert_frag): Likewise. (mips_convert_ase_flags): Handle MIPS16e2 ASE. * doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and `-mno-mips16e2' options. (-mmips16e2, -mno-mips16e2): New options. * doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and `-mno-mips16e2' options. (MIPS ASE Instruction Generation Overrides): Add `.set mips16e2' and `.set nomips16e2'.
2017-05-15 14:26:01 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
MIPS16/GAS: Improve [32768,65535] out-of-range operand error diagnostics Improve out-of-range operand error diagnostics for invalid values in the [32768,65535] range used for a signed 16-bit immediate, making the message consistent with that used for other invalid values, e.g.: foo.s:1: Error: operand 2 must be an immediate expression `addiu $2,$gp,32768' foo.s:2: Error: invalid operands `lw $2,32768($gp)' vs: foo.s:3: Error: operand 3 out of range `addiu $2,$gp,-32769' foo.s:4: Error: operand 2 out of range `lw $2,-32769($gp)' This case does not currently trigger however, for two reasons. First, for regular MIPS and microMIPS assembly in the case of no match caused by `match_int_operand' here, the function is always called again from `mips_ip' via `match_insns', `match_insn' and then `match_operand' for the same opcode table's entry with `lax_match' set to TRUE, in which case the attempt to match succeeds and no error is issued. Second, in the case of MIPS16 assembly no call to `match_int_operand' is made at all for signed 16-bit immediates, because such immediates are currently only matched with extensible instructions, and these are handled in `match_mips16_insn' via `match_expression' directly rather than via `match_operand'. This will change for MIPS16 code with MIPS16e2 support introduced, where non-extensible instructions accepting signed 16-bit immediates will be added, so make the case work well right from the start: foo.s:1: Error: operand 3 out of range `addiu $2,$gp,32768' foo.s:2: Error: operand 2 out of range `lw $2,32768($gp)' gas/ * config/tc-mips.c (match_int_operand): Call `match_out_of_range' before returning failure for 0x8000-0xffff values conditionally allowed.
2017-05-15 14:21:01 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_int_operand): Call
`match_out_of_range' before returning failure for 0x8000-0xffff
values conditionally allowed.
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_int_operand): Call
`match_not_constant' before returning failure for a non-constant
16-bit immediate conditionally allowed.
MIPS/GAS: Improve bignum operand error diagnostics Improve bignum operand error diagnostics for cases where a constant would be accepted and report them as range errors, also indicating the offending operand and instruction, e.g.: $ cat bignum.s addiu $2, 0x10000000000000000 break 0x10000000000000000 $ as -o bignum.o bignum.s bignum.s:1: Error: bignum invalid bignum.s:2: Error: operand 1 must be constant `break 0x10000000000000000' $ now show as: $ as -o bignum.o bignum.s bignum.s:1: Error: operand 2 out of range `addiu $2,0x10000000000000000' bignum.s:2: Error: operand 1 out of range `break 0x10000000000000000' $ gas/ * config/tc-mips.c (match_const_int): Call `match_out_of_range' rather than `match_not_constant' for unrelocated operands retrieved as an `O_big' expression. (match_int_operand): Call `match_out_of_range' for relocatable operands retrieved as an `O_big' expression. (match_mips16_insn): Call `match_out_of_range' for relaxable operands retrieved as an `O_big' expression. * testsuite/gas/mips/addiu-error.d: New test. * testsuite/gas/mips/mips16@addiu-error.d: New test. * testsuite/gas/mips/micromips@addiu-error.d: New test. * testsuite/gas/mips/break-error.d: New test. * testsuite/gas/mips/lui-1.l: Adjust error message. * testsuite/gas/mips/addiu-error.l: New stderr output. * testsuite/gas/mips/mips16@addiu-error.l: New stderr output. * testsuite/gas/mips/micromips@addiu-error.l: New stderr output. * testsuite/gas/mips/break-error.l: New stderr output. * testsuite/gas/mips/addiu-error.s: New test source. * testsuite/gas/mips/break-error.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-05-15 14:17:18 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_const_int): Call `match_out_of_range'
rather than `match_not_constant' for unrelocated operands
retrieved as an `O_big' expression.
(match_int_operand): Call `match_out_of_range' for relocatable
operands retrieved as an `O_big' expression.
(match_mips16_insn): Call `match_out_of_range' for relaxable
operands retrieved as an `O_big' expression.
* testsuite/gas/mips/addiu-error.d: New test.
* testsuite/gas/mips/mips16@addiu-error.d: New test.
* testsuite/gas/mips/micromips@addiu-error.d: New test.
* testsuite/gas/mips/break-error.d: New test.
* testsuite/gas/mips/lui-1.l: Adjust error message.
* testsuite/gas/mips/addiu-error.l: New stderr output.
* testsuite/gas/mips/mips16@addiu-error.l: New stderr output.
* testsuite/gas/mips/micromips@addiu-error.l: New stderr output.
* testsuite/gas/mips/break-error.l: New stderr output.
* testsuite/gas/mips/addiu-error.s: New test source.
* testsuite/gas/mips/break-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS16/GAS: Improve non-immediate operand error diagnostics Improve non-immediate operand error diagnostics for extensible MIPS16 instructions and make it match corresponding regular MIPS and microMIPS handling, e.g: $ cat addiu.s addiu $4, $3, $2 $ as -o addiu.o addiu.s addiu.s: Assembler messages: addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2' $ as -mips16 -o addiu.o addiu.s addiu.s: Assembler messages: addiu.s:1: Error: invalid operands `addiu $4,$3,$2' $ To do so observe that for extensible MIPS16 instructions and a non-PC relative operand this case is handled by an explicit OT_INTEGER check in `match_mips16_insn' returning a failure right away and consequently preventing a call to `match_expression' from being made. As from commit d436c1c2e889 ("Improve error reporting for register expressions"), <https://sourceware.org/ml/binutils/2013-08/msg00134.html>, however the check has become redundant as `match_expression' now only ever returns success for OT_INTEGER argument tokens, and a special case of an OT_CHAR `(' token already handled by `match_mips16_insn' just ahead of the `match_expression' call. Previously it also returned success for OT_REG argument tokens. Let the call to `match_expression' always happen then, yielding the same failure for the affected cases, however with more accurate diagnostics provided by the call making reporting consistent: $ as -mips16 -o addiu.o addiu.s addiu.s: Assembler messages: addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2' $ gas/ * config/tc-mips.c (match_mips16_insn): Remove the explicit OT_INTEGER check before the `match_expression' call. * testsuite/gas/mips/mips16-insn-e.l: Adjust messages. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: Likewise. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: Likewise. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: Likewise. * testsuite/gas/mips/mips16-reg-error.d: New test. * testsuite/gas/mips/mips16-reg-error.l: New stderr output. * testsuite/gas/mips/mips16-reg-error.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2017-05-15 14:13:41 +02:00
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_mips16_insn): Remove the explicit
OT_INTEGER check before the `match_expression' call.
* testsuite/gas/mips/mips16-insn-e.l: Adjust messages.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16-reg-error.d: New test.
* testsuite/gas/mips/mips16-reg-error.l: New stderr output.
* testsuite/gas/mips/mips16-reg-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_mips16_insn): Call
`match_not_constant' for a disallowed relocation operation.
* testsuite/gas/mips/mips16-reloc-error.d: New test.
* testsuite/gas/mips/mips16-reloc-error.l: New stderr output.
* testsuite/gas/mips/mips16-reloc-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/lui-1.d: New test.
* testsuite/gas/mips/lui-2.d: New test.
* gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_const_int): Update description.
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* doc/as.texinfo (-mips16, -no-mips16): Refer to `.module
mips16' rather than `.set mips16'.
(-mmicromips, -mno-micromips): Refer to `.module micromips' and
`.module nomicromips' rather than `.set micromips' and `.set
nomicromips'.
(-msmartmips, -mno-smartmips): Refer to `.module smartmips'
rather than `.set smartmips'.
* doc/c-mips.texi (MIPS Options): Refer to `.module mips16',
`.module micromips', `.module nomicromips' and `.module
smartmips' rather than `.set mips16', `.set micromips', `.set
nomicromips' and `.set smartmips' respectively.
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (mips_percent_op): Add "%gprel".
(mips16_percent_op): Add "%gp_rel".
* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips32r2-sync-1.d: New test.
* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS/testsuite: Convert ISA override list tests to dump tests And remove the zillion duplicate sources. Also `mips1@isa-override-2.l' is the same as `r3000@isa-override-2.l', so remove the latter too, now that `r3000@isa-override-2.d' can name a file to match stderr output against. gas/ * testsuite/gas/mips/isa-override-2.d: New test. * testsuite/gas/mips/mips1@isa-override-2.d: New test. * testsuite/gas/mips/r3000@isa-override-2.d: New test. * testsuite/gas/mips/r3900@isa-override-2.d: New test. * testsuite/gas/mips/mips2@isa-override-2.d: New test. * testsuite/gas/mips/mips32@isa-override-2.d: New test. * testsuite/gas/mips/mips32r2@isa-override-2.d: New test. * testsuite/gas/mips/mips32r3@isa-override-2.d: New test. * testsuite/gas/mips/mips32r5@isa-override-2.d: New test. * testsuite/gas/mips/mips32r6@isa-override-2.d: New test. * testsuite/gas/mips/octeon3@isa-override-2.d: New test. * testsuite/gas/mips/r3000@isa-override-2.l: Remove list test. * testsuite/gas/mips/mips1@isa-override-2.s: Remove test source. * testsuite/gas/mips/r3000@isa-override-2.s: Remove test source. * testsuite/gas/mips/r3900@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips2@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: Remove test source. * testsuite/gas/mips/octeon3@isa-override-2.s: Remove test source. * gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests into the new tests.
2017-05-10 21:14:11 +02:00
2017-05-10 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/isa-override-2.d: New test.
* testsuite/gas/mips/mips1@isa-override-2.d: New test.
* testsuite/gas/mips/r3000@isa-override-2.d: New test.
* testsuite/gas/mips/r3900@isa-override-2.d: New test.
* testsuite/gas/mips/mips2@isa-override-2.d: New test.
* testsuite/gas/mips/mips32@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-2.d: New test.
* testsuite/gas/mips/octeon3@isa-override-2.d: New test.
* testsuite/gas/mips/r3000@isa-override-2.l: Remove list test.
* testsuite/gas/mips/mips1@isa-override-2.s: Remove test source.
* testsuite/gas/mips/r3000@isa-override-2.s: Remove test source.
* testsuite/gas/mips/r3900@isa-override-2.s: Remove test source.
* testsuite/gas/mips/mips2@isa-override-2.s: Remove test source.
* testsuite/gas/mips/mips32@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/octeon3@isa-override-2.s: Remove test
source.
* gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
2017-05-10 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e-sub.d: Correct test name.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: Likewise.
* testsuite/gas/mips/mips16e-64-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: Likewise.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: Likewise.
2017-05-10 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-macro.l: Remove list test.
2017-05-10 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/r3900@ecoff@ld.d: Remove test.
* testsuite/gas/mips/mips2@ecoff@ld.d: Remove test.
* testsuite/gas/mips/mips32@ecoff@ld.d: Remove test.
* testsuite/gas/mips/mips32r2@ecoff@ld.d: Remove test.
* testsuite/gas/mips/r3900@ecoff@ld-forward.d: Remove test.
* testsuite/gas/mips/mips2@ecoff@ld-forward.d: Remove test.
* testsuite/gas/mips/mips32@ecoff@ld-forward.d: Remove test.
* testsuite/gas/mips/mips32r2@ecoff@ld-forward.d: Remove test.
* testsuite/gas/mips/mips1@ecoff@sd.d: Remove test.
* testsuite/gas/mips/r3000@ecoff@sd.d: Remove test.
* testsuite/gas/mips/r3900@ecoff@sd.d: Remove test.
* testsuite/gas/mips/mips2@ecoff@sd.d: Remove test.
* testsuite/gas/mips/mips32@ecoff@sd.d: Remove test.
* testsuite/gas/mips/mips32r2@ecoff@sd.d: Remove test.
* testsuite/gas/mips/mips1@ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/r3000@ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/r3900@ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/mips2@ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/mips32@ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/mips32r2@ecoff@sd-forward.d: Remove test.
[ARC] Object attributes. gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/attr-arc600.d: New file.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.s: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-name.s: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.s
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
* testsuite/gas/arc/blank.s: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/nps400-0.d: Likewise.
* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
* config/tc-arc.c (opcode/arc-attrs.h): Include.
(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
(arc_attribute): Declare new function.
(md_pseudo_table): Add arc_attribute.
(cpu_types): Rename default cpu features.
(selected_cpu): Set the default OSABI flag.
(mpy_option): New variable.
(pic_option): Likewise.
(sda_option): Likewise.
(tls_option): Likewise.
(feature_type, feature_list): Remove.
(arc_initial_eflag): Likewise.
(attributes_set_explicitly): New variable.
(arc_check_feature): Check also for the conflicting features.
(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
(arc_option): Remove setting of private flags and architecture.
(check_cpu_feature): Refactor feature names.
(autodetect_attributes): New function.
(assemble_tokens): Use above function.
(md_parse_option): Refactor feature names.
(arc_attribute): New function.
(arc_set_attribute_int): Likewise.
(arc_set_attribute_string): Likewise.
(arc_stralloc): Likewise.
(arc_set_public_attributes): Likewise.
(arc_md_end): Likewise.
(arc_copy_symbol_attributes): Likewise.
(rc_convert_symbolic_attribute): Likewise.
* config/tc-arc.h (md_end): Define.
(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
* doc/c-arc.texi: Document ARC object attributes.
MIPS16/GAS: Relax 32-bit non-PIC PC-relative synthetic instructions Implement the relaxation of MIPS16 PC-relative synthetic LA, DLA, LW and LD instructions to an equivalent sequence of instructions produced where the address operand requested is out of range, absolute or requires linker relocation, for ABIs that use 32-bit addressing and non-PIC code. The sequence generated uses the register specified for the destination operand as a temporary and begins with LI to load the high 16-bit part of the address, then continues with SLL by 16 bits to move that part into place and finally completes with a suitable operation corresponding to the synthetic instruction used, one of: 2-argument ADDIU, 2-argument DADDIU, absolute LW, and absolute LD respectively, providing the low 16-bit part of the address. All instructions use the extended encoding. As a special exception accept absolute addresses for relaxation even in PIC code. For example: la $2, 0x12345678 produces code as: li $2, 0x1234 sll $2, $2, 16 addiu $2, 0x5678 would. Where linker relocation is required emit an R_MIPS16_HI16 relocation on the initial LI instruction and an R_MIPS16_LO16 relocation on the final operation. For example (where `foo' is not local): lw $3, foo produces code as: li $3, %hi(foo) sll $3, $3, 16 lw $3, %lo(foo)($3) would. Emit assembly warnings as appropriate where this new relaxation triggers in the `nomacro' mode or for an instruction manually placed in a branch delay slot in the `noreorder' mode. Refrain from relaxation where an explicit instruction size suffix has been used and in the `noautoextend' mode. gas/ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and `nomacro' flags. (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO): New macros. (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT) (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT) (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED) (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED) (RELAX_MIPS16_MARK_ALWAYS_EXTENDED) (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits. (RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO) (RELAX_MIPS16_CLEAR_MACRO): New macros. (append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and `mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE. (mips16_macro_frag): New function. (md_estimate_size_before_relax): Handle HI16/LO16 relaxation. (mips_relax_frag): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/mips16@relax-swap3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16e@relax-swap3.d: New test subarchitecture. * testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing NOP padding. * testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16@relax-swap3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file. * testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file. * testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file. * testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file. * testsuite/gas/mips/relax-swap3.s: Adjust trailing padding. * testsuite/gas/mips/mips16-pcrel-0.d: New test. * testsuite/gas/mips/mips16-pcrel-1.d: New test. * testsuite/gas/mips/mips16-pcrel-2.d: New test. * testsuite/gas/mips/mips16-pcrel-3.d: New test. * testsuite/gas/mips/mips16-pcrel-4.d: New test. * testsuite/gas/mips/mips16-pcrel-5.d: New test. * testsuite/gas/mips/mips16-pcrel-pic-0.d: New test. * testsuite/gas/mips/mips16-pcrel-pic-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n32-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n32-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-1.d: New test. * testsuite/gas/mips/mips16-pcrel-delay-0.d: New test. * testsuite/gas/mips/mips16-pcrel-delay-1.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-4.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-5.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-6.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-7.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-0.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-2.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-3.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-4.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-5.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source. * testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-pcrel-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-1.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-05-03 21:43:10 +02:00
2017-05-03 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and
`nomacro' flags.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO):
New macros.
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits.
(RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO)
(RELAX_MIPS16_CLEAR_MACRO): New macros.
(append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and
`mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE.
(mips16_macro_frag): New function.
(md_estimate_size_before_relax): Handle HI16/LO16 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove error output,
add dump patterns.
* testsuite/gas/mips/mips16e@relax-swap3.d: New test
subarchitecture.
* testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing
NOP padding.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16@relax-swap3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file.
* testsuite/gas/mips/relax-swap3.s: Adjust trailing padding.
* testsuite/gas/mips/mips16-pcrel-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-pic-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-pic-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-delay-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-delay-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
New test.
* testsuite/gas/mips/mips16-pcrel-0.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-1.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-2.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-3.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-4.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-5.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-05-03 Nick Clifton <nickc@redhat.com>
PR gas/20941
* symbols.c (snapshot_symbol): Handle the case where
resolve_expression returns a local symbol.
MIPS16/GAS: Fix absolute references with PC-relative synthetic instructions Complement commit 88a7ef168927 ("MIPS16/GAS: Restore unsupported relocation diagnostics") and also propagate constant expressions, either already reduced from absolute symbol references or created from literals in the first place, used as a PC-relative operand with the MIPS16 LA, LW, DLA and LD synthetic instructions to relaxation, matching the way forward absolute symbol references have been handled as from the commit referred and letting relaxation produce any necessary relocations, if possible, for the absolute value requested to be reproduced at the run time. Call `symbol_append' for any expression symbol created for the purpose of MIPS16 relaxation as with constant expressions now propagated from earlier on such symbols may make it through and have R_MIPS16_PC16_S1 relocations emitted against, and therefore need to appear in the symbol table produced. gas/ * config/tc-mips.c (append_insn): Call `symbol_append' for any expression symbol created for MIPS16 relaxation. (match_mips16_insn): Don't encode a constant value as an immediate with a PC-relative operand. * testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-1.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-2.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-absolute-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-05-03 01:05:15 +02:00
2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Call `symbol_append' for any
expression symbol created for MIPS16 relaxation.
(match_mips16_insn): Don't encode a constant value as an
immediate with a PC-relative operand.
* testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-1.s: New test
source.
* testsuite/gas/mips/mips16-branch-absolute-2.s: New test
source.
* testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-27 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips16_pcrel_val): New function, factored
out from...
(mips16_extended_frag): ... here.
(md_convert_frag): Use `mips16_pcrel_val' rather than repeated
code in MIPS16 relaxation, with `stretch' hardcoded to 0.
2017-04-27 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_MIPS16_LONG_BRANCH): Rename to...
(RELAX_MIPS16_ALWAYS_EXTENDED): ... this.
(RELAX_MIPS16_MARK_LONG_BRANCH): Rename to...
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED): ... this.
(RELAX_MIPS16_CLEAR_LONG_BRANCH): Rename to...
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): ... this.
(mips16_extended_frag): Adjust accordingly.
2017-04-27 Alan Modra <amodra@gmail.com>
* symbols.c (S_FORCE_RELOC): Separate section and symbol tests.
MIPS/GAS: Fix `.option picX' handling with relaxation Correct the handling of `.option pic0' and `.option pic2' GAS pseudo-ops in relaxation and use the setting of `mips_pic' (which these directives control) as at the time a relaxed frag has been created rather than the final `mips_pic' setting at the end of the source file processed. To do so record whether `mips_pic' is NO_PIC or not in the frag itself and use this information throughout relaxation instead of `mips_pic' to decide which of NO_PIC or SVR4_PIC to produce machine code for, fixing code generation and removing a possible fatal failure reproducible with: $ as -32 --relax-branch -o option-pic-relax-3.o option-pic-relax-3.s option-pic-relax-3.s: Assembler messages: option-pic-relax-3.s:7: Warning: relaxed out-of-range branch into a jump option-pic-relax-3.s: Internal error in cvt_frag_to_fill at .../gas/write.c:490. Please report this bug. $ using the test source included, due to a buffer overrun in filling the variable part of a frag. Likewise use the `fx_tcbit2' flag of a BFD_RELOC_16_PCREL_S2 fixup to handle the simple case of substituting an out of range unconditional branch with an equivalent absolute jump in NO_PIC code. Retain the current way of VXWORKS_PIC use, which commit 41a1578ed17c ("MIPS/GAS: Sanitize `.option picX' pseudo-op") has forbidden the use of `.option picX' with. gas/ * config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag. (RELAX_PIC): New macro. (RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO) (RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT) (RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND): Shift bits. (RELAX_BRANCH_ENCODE): Add `pic' flag. (RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK) (RELAX_BRANCH_TOOFAR): Shift bits. (RELAX_BRANCH_PIC): New macro. (RELAX_MICROMIPS_ENCODE): Add `pic' flag. (RELAX_MICROMIPS_PIC): New macro. (RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT) (RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS) (RELAX_MICROMIPS_RELAX32): Shift bits. (relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE. (append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the first fixup created. (md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the fixup processed rather than `mips_pic' in choosing to relax an out of range branch to a jump. (relaxed_branch_length): Use the `pic' flag of the relaxed frag rather than `mips_pic'. (relaxed_micromips_32bit_branch_length): Likewise. (md_estimate_size_before_relax): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/option-pic-relax-0.d: New test. * testsuite/gas/mips/option-pic-relax-1.d: New test. * testsuite/gas/mips/option-pic-relax-2.d: New test. * testsuite/gas/mips/option-pic-relax-3.d: New test. * testsuite/gas/mips/option-pic-relax-3a.d: New test. * testsuite/gas/mips/option-pic-relax-4.d: New test. * testsuite/gas/mips/option-pic-relax-5.d: New test. * testsuite/gas/mips/option-pic-relax-2.l: New stderr output. * testsuite/gas/mips/option-pic-relax-3.l: New stderr output. * testsuite/gas/mips/option-pic-relax-4.l: New stderr output. * testsuite/gas/mips/option-pic-relax-5.l: New stderr output. * testsuite/gas/mips/option-pic-relax-0.s: New test source. * testsuite/gas/mips/option-pic-relax-1.s: New test source. * testsuite/gas/mips/option-pic-relax-2.s: New test source. * testsuite/gas/mips/option-pic-relax-3.s: New test source. * testsuite/gas/mips/option-pic-relax-4.s: New test source. * testsuite/gas/mips/option-pic-relax-5.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-27 01:47:15 +02:00
2017-04-26 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag.
(RELAX_PIC): New macro.
(RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO)
(RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT)
(RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND):
Shift bits.
(RELAX_BRANCH_ENCODE): Add `pic' flag.
(RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK)
(RELAX_BRANCH_TOOFAR): Shift bits.
(RELAX_BRANCH_PIC): New macro.
(RELAX_MICROMIPS_ENCODE): Add `pic' flag.
(RELAX_MICROMIPS_PIC): New macro.
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS)
(RELAX_MICROMIPS_RELAX32): Shift bits.
(relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE.
(append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE
and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the
first fixup created.
(md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the
fixup processed rather than `mips_pic' in choosing to relax an
out of range branch to a jump.
(relaxed_branch_length): Use the `pic' flag of the relaxed frag
rather than `mips_pic'.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_estimate_size_before_relax): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/option-pic-relax-0.d: New test.
* testsuite/gas/mips/option-pic-relax-1.d: New test.
* testsuite/gas/mips/option-pic-relax-2.d: New test.
* testsuite/gas/mips/option-pic-relax-3.d: New test.
* testsuite/gas/mips/option-pic-relax-3a.d: New test.
* testsuite/gas/mips/option-pic-relax-4.d: New test.
* testsuite/gas/mips/option-pic-relax-5.d: New test.
* testsuite/gas/mips/option-pic-relax-2.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-3.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-4.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-5.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-0.s: New test source.
* testsuite/gas/mips/option-pic-relax-1.s: New test source.
* testsuite/gas/mips/option-pic-relax-2.s: New test source.
* testsuite/gas/mips/option-pic-relax-3.s: New test source.
* testsuite/gas/mips/option-pic-relax-4.s: New test source.
* testsuite/gas/mips/option-pic-relax-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: Update test.
* testsuite/gas/arc/leave_enter.s: Likewise.
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test.
* testsuite/gas/arc/noargs_hs.d: Likewise.
2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Correct
BFD_RELOC_MIPS16_16_PCREL_S1 fixup size.
* testsuite/gas/mips/mips16-branch-addend-4.d: New test.
* testsuite/gas/mips/mips16-branch-addend-5.d: New test.
* testsuite/gas/mips/mips16-branch-addend-5.l: New stderr
output.
* testsuite/gas/mips/mips16-branch-addend-4.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/21407
* config/tc-sparc.c (md_apply_fix): Do not transform `call'
instructions into branch instructions in fixups generating
additional relocations.
* testsuite/gas/sparc/call-relax.s: New file.
* testsuite/gas/sparc/call-relax.d: Likewise.
* testsuite/gas/sparc/call-relax-aout.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
Forbid MOV.W and MOVW if destination is SP or PC.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
expectation of LDR not generating a MOVS for low registers and small
constants. Add tests of MOVW generation.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
expected disassembly.
2017-04-22 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
* testsuite/gas/ppc/vle.d: Update.
2017-04-21 Nick Clifton <nickc@redhat.com>
PR binutils/21380
* testsuite/gas/aarch64/illegal-3.s: New file.
* testsuite/gas/aarch64/illegal-3.d: New file.
2017-04-11 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
* testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
2017-04-10 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag):
Initialize lps->frag_count with auto_litpool_limit.
(xg_promote_candidate_litpool): New function.
(xtensa_move_literals): Extract candidate litpool promotion code
into separate function. Call it for all possible found
candidates.
(xtensa_switch_to_literal_fragment): Drop 'recursive' flag and
call to xtensa_mark_literal_pool_location that it guards.
Replace it with call to xtensa_maybe_create_literal_pool_frag.
Initialize pool_location with created literal pool candidate.
* testsuite/gas/xtensa/all.exp: Add new tests.
* testsuite/gas/xtensa/auto-litpools-first1.d: New test results.
* testsuite/gas/xtensa/auto-litpools-first1.s: New test.
* testsuite/gas/xtensa/auto-litpools-first2.d: New test results.
* testsuite/gas/xtensa/auto-litpools-first2.s: New test.
* testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due
to additional jump instruction.
2017-04-07 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
* testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section12a.d: Don't expect alignment of 1
for .mbind.text.
2017-04-06 Pip Cet <pipcet@gmail.com>
* testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
changes.
* testsuite/gas/wasm32/disass.d: New test.
* testsuite/gas/wasm32/disass.s: New test.
* testsuite/gas/wasm32/disass-2.d: New test.
* testsuite/gas/wasm32/disass-2.s: New test.
* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
names.
* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
syntax.
* testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn
test to succeed.
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX Mark an ALLOC section, which should be placed in special memory area, with SHF_GNU_MBIND. Its sh_info field indicates the special memory type. GNU_MBIND section names start with ".mbind" so that they are placed as orphan sections by linker. All input GNU_MBIND sections with the same sh_type, sh_flags and sh_info are placed in one output GNU_MBIND section. In executable and shared object, create a GNU_MBIND segment for each GNU_MBIND section and its segment type is PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is aligned at page boundary. The assembler syntax: .section .mbind.foo,"adx",%progbits ^ 0: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.foo,"adx",%progbits,0x1 ^ 1: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2 ^ 2: Special memory type. | 'd' for SHF_GNU_MBIND. bfd/ * elf.c (get_program_header_size): Add a GNU_MBIND segment for each GNU_MBIND section and align GNU_MBIND section to page size. (_bfd_elf_map_sections_to_segments): Create a GNU_MBIND segment for each GNU_MBIND section. (_bfd_elf_init_private_section_data): Copy sh_info from input for GNU_MBIND section. binutils/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX. (get_elf_section_flags): Handle SHF_GNU_MBIND. (process_section_headers): Likewise. * testsuite/binutils-all/mbind1.s: New file. * testsuite/binutils-all/objcopy.exp: Run readelf test on mbind1.s. gas/ * NEWS: Mention support for ELF SHF_GNU_MBIND. * config/obj-elf.c (section_match): New. (get_section): Match both sh_info and group name. (obj_elf_change_section): Add argument for sh_info. Pass both sh_info and group name to get_section. Issue an error for SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info. (obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'. (obj_elf_section): Support SHF_GNU_MBIND section info. * config/obj-elf.h (obj_elf_change_section): Add argument for sh_info. * config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texinfo: Document 'd' for SHF_GNU_MBIND. * testsuite/gas/elf/elf.exp: Run section12a, section12b and section13. * testsuite/gas/elf/section10.d: Updated. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section12.s: New file. * testsuite/gas/elf/section12a.d: Likewise. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.l: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.s: Likewise. include/ * elf/common.h (PT_GNU_MBIND_NUM): New. (PT_GNU_MBIND_LO): Likewise. (PT_GNU_MBIND_HI): Likewise. (SHF_GNU_MBIND): Likewise. ld/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place input GNU_MBIND sections with the same type, attributes and sh_info field into a single output GNU_MBIND section. * testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b. * testsuite/ld-elf/mbind1.s: New file. * testsuite/ld-elf/mbind1a.d: Likewise. * testsuite/ld-elf/mbind1b.d: Likewise. * testsuite/ld-elf/mbind1c.d: Likewise. * testsuite/ld-elf/mbind2a.s: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 18:05:48 +02:00
2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to
avoid const warnings.
2017-03-30 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_clear_subsets): New function.
(riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
clear RVC when it's been previously set.
2017-03-31 Nick Clifton <nickc@redhat.com>
PR gas/21333
* config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative
fixups in mergeable sections to be adjusted.
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils. binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate.
2017-03-30 11:57:21 +02:00
2017-03-30 Pip Cet <pipcet@gmail.com>
* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
* Makefile.am: Add WebAssembly assembler target.
* configure.tgt: Add WebAssembly assembler target.
* doc/c-wasm32.texi: New file: Start documenting WebAssembly
assembler.
* doc/all.texi: Define WASM32.
* doc/as.texinfo: Add WebAssembly entries.
* NEWS: Mention the new support.
* Makefile.in: Regenerate.
* po/gas.pot: Regenerate.
* po/POTFILES.in: Regenerate.
* testsuite/gas/wasm32: New directory.
* testsuite/gas/wasm32/allinsn.d: New file.
* testsuite/gas/wasm32/allinsn.s: New file.
* testsuite/gas/wasm32/illegal.l: New file.
* testsuite/gas/wasm32/illegal.s: New file.
* testsuite/gas/wasm32/illegal-2.l: New file.
* testsuite/gas/wasm32/illegal-2.s: New file.
* testsuite/gas/wasm32/illegal-3.l: New file.
* testsuite/gas/wasm32/illegal-3.s: New file.
* testsuite/gas/wasm32/illegal-4.l: New file.
* testsuite/gas/wasm32/illegal-4.s: New file.
* testsuite/gas/wasm32/illegal-5.l: New file.
* testsuite/gas/wasm32/illegal-5.s: New file.
* testsuite/gas/wasm32/illegal-6.l: New file.
* testsuite/gas/wasm32/illegal-6.s: New file.
* testsuite/gas/wasm32/illegal-7.l: New file.
* testsuite/gas/wasm32/illegal-7.s: New file.
* testsuite/gas/wasm32/illegal-8.l: New file.
* testsuite/gas/wasm32/illegal-8.s: New file.
* testsuite/gas/wasm32/illegal-9.l: New file.
* testsuite/gas/wasm32/illegal-9.s: New file.
* testsuite/gas/wasm32/illegal-10.l: New file.
* testsuite/gas/wasm32/illegal-10.s: New file.
* testsuite/gas/wasm32/illegal-11.l: New file.
* testsuite/gas/wasm32/illegal-11.s: New file.
* testsuite/gas/wasm32/illegal-12.l: New file.
* testsuite/gas/wasm32/illegal-12.s: New file.
* testsuite/gas/wasm32/illegal-13.l: New file.
* testsuite/gas/wasm32/illegal-13.s: New file.
* testsuite/gas/wasm32/illegal-14.l: New file.
* testsuite/gas/wasm32/illegal-14.s: New file.
* testsuite/gas/wasm32/illegal-15.l: New file.
* testsuite/gas/wasm32/illegal-15.s: New file.
* testsuite/gas/wasm32/illegal-16.l: New file.
* testsuite/gas/wasm32/illegal-16.s: New file.
* testsuite/gas/wasm32/illegal-17.l: New file.
* testsuite/gas/wasm32/illegal-17.s: New file.
* testsuite/gas/wasm32/illegal-18.l: New file.
* testsuite/gas/wasm32/illegal-18.s: New file.
* testsuite/gas/wasm32/illegal-19.l: New file.
* testsuite/gas/wasm32/illegal-19.s: New file.
* testsuite/gas/wasm32/illegal-20.l: New file.
* testsuite/gas/wasm32/illegal-20.s: New file.
* testsuite/gas/wasm32/illegal-21.l: New file.
* testsuite/gas/wasm32/illegal-21.s: New file.
* testsuite/gas/wasm32/illegal-22.l: New file.
* testsuite/gas/wasm32/illegal-22.s: New file.
* testsuite/gas/wasm32/illegal-24.l: New file.
* testsuite/gas/wasm32/illegal-24.s: New file.
* testsuite/gas/wasm32/illegal-25.l: New file.
* testsuite/gas/wasm32/illegal-25.s: New file.
* testsuite/gas/wasm32/reloc.d: New file.
* testsuite/gas/wasm32/reloc.s: New file.
* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
architecture.
2017-03-29 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_parse_option): Reject -mraw.
2017-03-27 Alan Modra <amodra@gmail.com>
PR 21303
* testsuite/gas/ppc/pr21303.d,
* testsuite/gas/ppc/pr21303.s: New test
* testsuite/gas/ppc/ppc.exp: Run it.
2017-03-27 Rinat Zelig <rinat@mellanox.com>
* testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
CPU_DEFAULT is defined.
2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
* config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
print an invalid default ISA string.
* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
reassigned fixup to size of jump instruction (3) and fx_r_type
to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
(add_jump_to_trampoline): Search
origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
symbol and use that slot instead of slot 0.
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
from cpu_table. Remove vx2, and novx2 from cpu_flags.
2017-03-21 Rinat Zelig <rinat@mellanox.com>
* testsuite/gas/arc/nps400-11.s: New file.
* testsuite/gas/arc/nps400-11.d: New file.
2017-03-20 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (2byte): Note that if no expressions are present
the directive does nothing. Emphasize that the output is
unaligned, and that this can have an effect on the relocations
generated.
(4byte): Simplify description. Refer back to the 2byte
description.
(8byte): Likewise.
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c (arm_fpus): Note entires that should not be
documented.
* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
neon-fp16. Fix spelling error.
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-03-16 Rinat Zelig <rinat@mellanox.com>
* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
specially for ARCv2.
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
encoding format, which can accept 0-valued immediates.
(riscv_ip): Likewise.
2017-03-15 Nick Clifton <nickc@redhat.com>
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time
warning about discarding a const qualifier.
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Set fx_frag and
fx_next->fx_frag for CFA_advance_loc relocations.
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Compute the correct offsets
for CFA relocations.
2017-03-13 10:58:04 +01:00
2017-03-13 Nick Clifton <nickc@redhat.com>
PR binutils/21202
* config/tc-aarch64.c (reloc_table): Rename
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
(md_apply_fix): Likewise.
(aarch64_force_relocation): Likewise.
* testsuite/gas/aarch64/tls.d: Update regexp.
2017-03-10 Tobin C. Harding <me@tobin.cc>
Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (2byte): Tidy up wording. Add note that
overlarge values will produce a warning message and be trunacted.
(4byte): Likewise.
X86: Add pseudo prefixes to control encoding Many x86 instructions have more than one encodings. Assembler picks the default one, usually the shortest one. Although the ".s", ".d8" and ".d32" suffixes can be used to swap register operands or specify displacement size, they aren't very flexible. This patch adds pseudo prefixes, {xxx}, to control instruction encoding. The available pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and ".d32" suffixes, which are deprecated. gas/ * config/tc-i386.c (_i386_insn): Add dir_encoding and vec_encoding. Remove swap_operand and need_vrex. (extra_symbol_chars): Add '}'. (md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in mnemonic. (build_vex_prefix): Don't use 2-byte VEX encoding with {vex3}. Check dir_encoding and load. (parse_insn): Check pseudo prefixes. Set dir_encoding. (VEX_check_operands): Likewise. (match_template): Check dir_encoding and load. (parse_real_register): Set vec_encoding instead of need_vrex. (parse_register): Likewise. * doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32" * testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos. * testsuite/gas/i386/pseudos.d: New file. * testsuite/gas/i386/pseudos.s: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace S with Load. * i386-opc.h (S): Removed. (Load): New. (i386_opcode_modifier): Replace s with load. * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} and {evex}. Replace S with Load. * i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
(objdump): Use the -Mpower8 option.
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <lnia> New test.
* testsuite/gas/ppc/power9.s: Likewise.
2017-03-07 Alan Modra <amodra@gmail.com>
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
2017-03-07 Tobin C. Harding <me@tobin.cc>
Alan Modra <amodra@gmail.com>
* doc/as.texinfo (2byte, 4byte, 8byte): Document.
* doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
Add support for Intel CET instructions Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-03-07 00:26:37 +01:00
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
2017-03-06 Alan Modra <amodra@gmail.com>
* dw2gencfi.c (encoding_size): Return unsigned int.
(emit_expr_encoded): Assert size matches reloc bitsize.
(output_fde): Use unsigned for offset_size and addr_size. Set
addr_size earlier and use in place of constant 4 and uses of
DWARF2_FDE_RELOC_SIZE. Assert it matches reloc bitsize.
2017-03-06 Alan Modra <amodra@gmail.com>
* dw2gencfi.c: Wrap overlong lines. Add parens for emacs
auto reformat. Formatting and whitespace fixes.
2017-03-05 Mark Wielaard <mark@klomp.org>
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
(out_debug_info): Accept symbols to name, comp_dir and producer in
the .debug_str section and emit those offsets not full strings.
(out_debug_str): New function that outputs the strings for name,
comp_dir and producer in .debug_str and generates symbols to those
strings.
(out_debug_line): Create a .debug_str section if necessary and call
out_debug_str before calling out_debug_info.
* testsuite/gas/aarch64/dwarf.d: Add extra section symbol to expected
output.
GAS: Fix bogus "attempt to move .org backwards" relaxation errors Fix a commit 6afe8e98a664 ("internal error for backwards .org"), <https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>, GAS regression that caused legitimate code to fail assembly with an "attempt to move .org backwards" error. For example with the `mips-linux' target we get: $ cat org.s .set mips16 la $2, foo .org 0x1000 .align 2 foo: .half 0 $ as -o org.o org.s org.s: Assembler messages: org.s:3: Error: attempt to move .org backwards $ where the location pointer is obviously not moved backwards with `.org'. The cause is positive `stretch' in relaxation due to a PC-relative ADDIU instruction (produced from the LA macro used) getting expanded from 2 to 4 bytes as `foo' is noticed to be out of range for the short encoding. This in turn triggers logic in `relax_segment' which concludes in the processing of an `rs_org' frag produced that the location pointer is moved backwards while in fact only the amount to space forward to the location requested has shrunk, resulting in a negative growth of the frag. Correct the bad logic then and instead verify that the fixed part of an `rs_org' frag has not overrun the location requested, as per the comment already included with the error message: /* Growth may be negative, but variable part of frag cannot have fewer than 0 chars. That is, we can't .org backwards. */ which accurately describes the regression scenario. Move the comment ahead the conditional noted, for clarity. Add generic and MIPS test cases for the `.org' pseudo-op, including the test case discussed though not integrated with the offending commit in particular, adjusted to work across all targets. gas/ * write.c (relax_segment) <rs_org>: Only bail out if the fixed part of the frag has overrun the location requested. * testsuite/gas/all/org-1.d: New test. * testsuite/gas/all/org-2.d: New test. * testsuite/gas/all/org-3.d: New test. * testsuite/gas/all/org-4.d: New test. * testsuite/gas/all/org-5.d: New test. * testsuite/gas/all/org-6.d: New test. * testsuite/gas/all/org-1.l: New stderr output. * testsuite/gas/all/org-2.l: New stderr output. * testsuite/gas/all/org-3.l: New stderr output. * testsuite/gas/all/org-1.s: New test source. * testsuite/gas/all/org-2.s: New test source. * testsuite/gas/all/org-3.s: New test source. * testsuite/gas/all/org-4.s: New test source. * testsuite/gas/all/org-5.s: New test source. * testsuite/gas/all/org-6.s: New test source. * testsuite/gas/all/gas.exp: Run the new tests. * testsuite/gas/mips/org-1.d: New test. * testsuite/gas/mips/org-2.d: New test. * testsuite/gas/mips/org-3.d: New test. * testsuite/gas/mips/org-4.d: New test. * testsuite/gas/mips/org-5.d: New test. * testsuite/gas/mips/org-6.d: New test. * testsuite/gas/mips/org-7.d: New test. * testsuite/gas/mips/org-8.d: New test. * testsuite/gas/mips/org-9.d: New test. * testsuite/gas/mips/org-10.d: New test. * testsuite/gas/mips/org-11.d: New test. * testsuite/gas/mips/org-12.d: New test. * testsuite/gas/mips/org-1.l: New stderr output. * testsuite/gas/mips/org-4.l: New stderr output. * testsuite/gas/mips/org-5.l: New stderr output. * testsuite/gas/mips/org-6.l: New stderr output. * testsuite/gas/mips/org-10.l: New stderr output. * testsuite/gas/mips/org-1.s: New test source. * testsuite/gas/mips/org-2.s: New test source. * testsuite/gas/mips/org-3.s: New test source. * testsuite/gas/mips/org-4.s: New test source. * testsuite/gas/mips/org-5.s: New test source. * testsuite/gas/mips/org-6.s: New test source. * testsuite/gas/mips/org-7.s: New test source. * testsuite/gas/mips/org-8.s: New test source. * testsuite/gas/mips/org-9.s: New test source. * testsuite/gas/mips/org-10.s: New test source. * testsuite/gas/mips/org-11.s: New test source. * testsuite/gas/mips/org-12.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-03-02 02:24:15 +01:00
2017-03-02 Maciej W. Rozycki <macro@imgtec.com>
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
part of the frag has overrun the location requested.
* testsuite/gas/all/org-1.d: New test.
* testsuite/gas/all/org-2.d: New test.
* testsuite/gas/all/org-3.d: New test.
* testsuite/gas/all/org-4.d: New test.
* testsuite/gas/all/org-5.d: New test.
* testsuite/gas/all/org-6.d: New test.
* testsuite/gas/all/org-1.l: New stderr output.
* testsuite/gas/all/org-2.l: New stderr output.
* testsuite/gas/all/org-3.l: New stderr output.
* testsuite/gas/all/org-1.s: New test source.
* testsuite/gas/all/org-2.s: New test source.
* testsuite/gas/all/org-3.s: New test source.
* testsuite/gas/all/org-4.s: New test source.
* testsuite/gas/all/org-5.s: New test source.
* testsuite/gas/all/org-6.s: New test source.
* testsuite/gas/all/gas.exp: Run the new tests.
* testsuite/gas/mips/org-1.d: New test.
* testsuite/gas/mips/org-2.d: New test.
* testsuite/gas/mips/org-3.d: New test.
* testsuite/gas/mips/org-4.d: New test.
* testsuite/gas/mips/org-5.d: New test.
* testsuite/gas/mips/org-6.d: New test.
* testsuite/gas/mips/org-7.d: New test.
* testsuite/gas/mips/org-8.d: New test.
* testsuite/gas/mips/org-9.d: New test.
* testsuite/gas/mips/org-10.d: New test.
* testsuite/gas/mips/org-11.d: New test.
* testsuite/gas/mips/org-12.d: New test.
* testsuite/gas/mips/org-1.l: New stderr output.
* testsuite/gas/mips/org-4.l: New stderr output.
* testsuite/gas/mips/org-5.l: New stderr output.
* testsuite/gas/mips/org-6.l: New stderr output.
* testsuite/gas/mips/org-10.l: New stderr output.
* testsuite/gas/mips/org-1.s: New test source.
* testsuite/gas/mips/org-2.s: New test source.
* testsuite/gas/mips/org-3.s: New test source.
* testsuite/gas/mips/org-4.s: New test source.
* testsuite/gas/mips/org-5.s: New test source.
* testsuite/gas/mips/org-6.s: New test source.
* testsuite/gas/mips/org-7.s: New test source.
* testsuite/gas/mips/org-8.s: New test source.
* testsuite/gas/mips/org-9.s: New test source.
* testsuite/gas/mips/org-10.s: New test source.
* testsuite/gas/mips/org-11.s: New test source.
* testsuite/gas/mips/org-12.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-03-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
2017-02-28 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-avx.s: Add suffixed variants of
VPCMPESTR{I,M}.
* testsuite/gas/i386/x86-64-sse2avx.s: Likewise.
* testsuite/gas/i386/x86-64-sse4_2.s: Add suffixed variants
of PCMPESTR{I,M}.
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse4_2.d: Likewise.
* testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx.d: Likewise.
* testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
* testsuite/gas/i386/x86-64-sse4_2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-sse4_2.d: Likewise.
Nios2 dynobj handling fixes A number of places in elf32-nios.c created dynamic sections but didn't set the hash table dynobj. That meant we could have duplicate dynamic sections connected to a number of bfds, so size_dynamic_sections didn't properly discard or allocate contents. Also, the entire set of dynamic sections was created in check_relocs on seeing GOT relocs, when only .got related sections are needed, probably done to hide segfaults later in finish_dynamic_sections. The patch fixes these issues and makes the assembler emit errors when nios2 lacks the necessary pc-relative relocs for subtraction expressions, rather than silently generating bad code. eg. ld-elf/merge. I've also tidied uses of elf32_nios2_hash_table and elf_hash_table. bfd/ PR 20995 * elf32-nios2.c (nios2_elf32_relocate_section): Use htab rather than elf32_nios2_hash_table or elf_hash_table. (create_got_section): Likewise. (nios2_elf32_finish_dynamic_symbol): Likewise. (nios2_elf32_adjust_dynamic_symbol): Likewise. (nios2_elf32_size_dynamic_sections): Likewise. (nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot vars. Use htab equivalents directly instead. Don't create all dynamic sections on needing just the GOT. Use a goto rather than a fall-through with reloc test. Ensure htab->dynobj is set when making dynamic sreloc section. (nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab equivalent directly instead. Don't segfault on looking for .dynamic when dynamic sections have not been created. Don't segfault on .got.plt being discarded. (nios2_elf32_size_dynamic_sections): Delete plt and got vars. Don't set "relocs" on .rela.plt. Do handle .sbss. Delete fixme and another not so relevant comment. (nios2_elf_add_symbol_hook): Delete dynobj var. If not already set, set hash table dynobj on creating .sbss. gas/ * config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define. ld/ * testsuite/ld-elf/merge.d: xfail for nios.
2017-02-28 01:08:51 +01:00
2017-02-28 Alan Modra <amodra@gmail.com>
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
PowerPC addpcis fix This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range.
2017-02-27 23:02:36 +01:00
2017-02-28 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
2017-02-28 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
encoding patterns.
* testsuite/gas/mips/jalr4-n64.d: Likewise.
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
2017-02-25 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/strtab.s: Don't put directives on first
column or continuation with labels not in first column.
[AArch64] Additional SVE instructions This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
* testsuite/gas/i386/x86-64-opcode.s: Likewise.
* testsuite/gas/i386/opcode.d: Adjust accordingly.
* testsuite/gas/i386/opcode-intel.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
2017-02-24 Sheldon Lobo <sheldon.lobo@oracle.com>
Test cases for the architecture level aware SPARC ASI work.
* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
MIPS/BFD: Discard ineligible JALR relocations right away Discard R_MIPS_JALR and R_MICROMIPS_JALR relocations associated with jumps that cannot be converted to an equivalent branch right away in `mips_elf_calculate_relocation' rather than letting them through to `mips_elf_perform_relocation'. This includes cross-mode jumps which need to flip the ISA bit or jumps to a misaligned location that cannot be encoded with a branch, in addition to preemptible symbol references already handled. Cross-mode jumps are actually already rejected as the conversion is made in `mips_elf_perform_relocation', so in this case this change only saves some processing. Jumps to a misaligned location are however converted, with bits causing misalignment lost, making resulting code functionally different even if the lone effect is avoiding an address error exception with an instruction fetch at the jump destination requested. Add test cases suitable, also including GAS verification to confirm that the JALR relocations explicitly requested have indeed been output in the intermediate objects used. bfd/ * elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_JALR> <R_MICROMIPS_JALR>: Discard relocation if `cross_mode_jump_p' or misaligned. gas/ * testsuite/gas/mips/jalr4.d: New test. * testsuite/gas/mips/jalr4-n32.d: New test. * testsuite/gas/mips/jalr4-n64.d: New test. * testsuite/gas/mips/jalr4.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalr4.dd: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-02-23 20:26:53 +01:00
2017-02-23 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/jalr4.d: New test.
* testsuite/gas/mips/jalr4-n32.d: New test.
* testsuite/gas/mips/jalr4-n64.d: New test.
* testsuite/gas/mips/jalr4.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
Add support for associating SPARC ASIs with an architecture level.
* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.
2017-02-23 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/all/err-sizeof.s: Don't use sums or differences
of symbols as expression.
2017-02-23 Jan Beulich <jbeulich@suse.com>
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.d: Add 32- and 16-
bit GPR forms of BNDCL, BNDCU, and BNDCN. Add RSP-as-index
Intel syntax forms of BNDMK, BNDSTX, and BNDLDX.
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust.
GAS: Consistently fix labels at the `.end' pseudo-op Fix a functional regression with the `.end' pseudo-op, introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit dcd410fe1544 ("GNU as 2.14 on IRIX 6: crashes with shared libs"), <https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused symbol values for labels placed between the end of a function's contents and its terminating `.end' followed by one of the alignment pseudo-ops to be different depending on whether either `-mdebug', or `-mno-pdr', or neither of the command-line options is in effect, be it implied or specified. Given debug-label-end.s as follows and the `mips-linux' target we have: $ cat debug-label-end.s .text .globl foo .globl bar .align 4, 0 .ent foo foo: nop .aent bar bar: .insn .end foo .align 4, 0 .space 16 .globl baz .ent baz baz: nop .end baz .align 4, 0 .space 16 $ as -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar $ as -mdebug -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ as -mno-pdr -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ The reason is the call to `md_flush_pending_output', which in the case of `mips*-*-*' targets expands to `mips_emit_delays', which in turn calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which clears the list of outstanding labels. That list is in turn consulted in `mips_align', called in the interpretation of alignment directives, and the labels adjusted to the current location. A call to `md_flush_pending_output' is only made from `s_mips_end' and then only if `-mpdr' is in effect, which is the default for `*-*-linux*' and some other `mips*-*-*' targets. A call to `md_flush_pending_output' is never made from `ecoff_directive_end', which is used in place of `s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or `-mdebug' is in effect the list of outstanding labels makes it through to any alignment directive that follows and the labels are differently interpreted depending on the command-lines options used. And we want code produced to be always the same. Call `md_flush_pending_output' unconditionally then in `s_mips_end' and add such a call from `ecoff_directive_end' as well, as long as the macro is defined. While `ecoff_directive_end' is shared among targets, the only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it does not define `md_flush_pending_output'. So the semantics isn't going to change for it and neither it has to have its `s_alpha_end' updated or have code in `ecoff_directive_end' conditionalized. gas/ * ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call `md_flush_pending_output'. * config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call `md_flush_pending_output' unconditionally. * testsuite/gas/mips/debug-label-end-1.d: New test. * testsuite/gas/mips/debug-label-end-2.d: New test. * testsuite/gas/mips/debug-label-end-3.d: New test. * testsuite/gas/mips/debug-label-end.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-17 21:30:55 +01:00
2017-02-22 Maciej W. Rozycki <macro@imgtec.com>
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
`md_flush_pending_output'.
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
`md_flush_pending_output' unconditionally.
* testsuite/gas/mips/debug-label-end-1.d: New test.
* testsuite/gas/mips/debug-label-end-2.d: New test.
* testsuite/gas/mips/debug-label-end-3.d: New test.
* testsuite/gas/mips/debug-label-end.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-22 14:17:33 +01:00
2017-02-22 Hans-Peter Nilsson <hp@axis.com>
* testsuite/gas/all/err-sizeof.s: Include cris*-*-* in the list of
targets yielding an error message matching "too complex".
2017-02-22 Nick Clifton <nickc@redhat.com>
* testsuite/gas/arm/vcmp-noprefix-imm.d: Skip for non-ELF targets.
2017-02-21 Jan Beulich <jbeulich@suse.com>
* expr.c (operand): Handle missing operand to .startof.() and
.sizeof.().
* testsuite/gas/all/err-sizeof.s: New.
2017-02-20 Alan Modra <amodra@gmail.com>
PR 21118
* NEWS: Revise powerpc register check.
* config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid
register expression" a warning.
GAS: Add ECOFF `.aent' pseudo-op support Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section support with ELF objects and, for consistency, also with ECOFF objects. This is so that the same MIPS source can be assembled without and with `.mdebug' section generation enabled. Taking the `gas/testsuite/gas/mips/aent.s' test case source as an example and the `mips-linux' target we have: $ as -o aent.o aent.s $ as -mdebug -o aent.o aent.s aent.s: Assembler messages: aent.s:10: Error: unknown pseudo-op: `.aent' $ because for the !ECOFF_DEBUGGING case (which is the default) the pseudo-op is already handled by the MIPS backend with `s_mips_ent', however no handler is present for the opposite case. For the MIPS target this is a functional regression introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where support for the `.mdebug' section was added along with its associated `-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency between the assembly syntax supported for each of these options as far as the `.aent' pseudo-op is concerned. Assembly language documentation available describes the pseudo-op respectively as follows[1]: " .aent name, symno Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. It must appear inside an .ent/.end pair." and[2]: " .aent name [,symno] Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives. (The optional symno is for compiler use only. It refers to a dense number in a .T file (symbol table).)" Copy the approach from `s_mips_ent' then and add `.aent' support to the `.ent' pseudo-op handler shared between the ELF and ECOFF object file format backends, by setting BSF_FUNCTION for the symbol requested. References: [1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics, Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96 <http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf> [2] "Digital UNIX Assembly Language Programmer's Guide", Digital Equipment Corporation, Order Number: AA-PS31D-TE, March 1996, Chapter 5 "Assembler Directives", p. 5-2 <http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF> gas/ * ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'. * config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry. * config/obj-elf.c (ecoff_debug_pseudo_table): Likewise. * testsuite/gas/mips/aent-2.d: New test. * testsuite/gas/mips/aent-mdebug.d: New test. * testsuite/gas/mips/aent-mdebug-2.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-16 02:50:29 +01:00
2017-02-17 Maciej W. Rozycki <macro@imgtec.com>
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
* testsuite/gas/mips/aent-2.d: New test.
* testsuite/gas/mips/aent-mdebug.d: New test.
* testsuite/gas/mips/aent-mdebug-2.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-sysreg.s,
testsuite/gas/aarch64/sve-sysreg.d,
testsuite/gas/aarch64/sve-sysreg-invalid.d,
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Fix sve entry.
[ARC] Fix assembler relaxation. Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-15 11:57:51 +01:00
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
information from input expression.
(assemble_insn): Make sure pcrel is correctly set.
(arc_pcrel_adjust): Compensate for PCL rounding.
* testsuite/gas/arc/relax-add01.d: New file.
* testsuite/gas/arc/relax-add01.s: Likewise.
* testsuite/gas/arc/relax-add02.d: Likewise.
* testsuite/gas/arc/relax-add02.s: Likewise.
* testsuite/gas/arc/relax-add03.d: Likewise.
* testsuite/gas/arc/relax-add03.s: Likewise.
* testsuite/gas/arc/relax-add04.d: Likewise.
* testsuite/gas/arc/relax-add04.s: Likewise.
* testsuite/gas/arc/relax-ld01.d: Likewise.
* testsuite/gas/arc/relax-ld01.s: Likewise.
* testsuite/gas/arc/relax-ld02.d: Likewise.
* testsuite/gas/arc/relax-ld02.s: Likewise.
* testsuite/gas/arc/relax-mov01.d: Likewise.
* testsuite/gas/arc/relax-mov01.s: Likewise.
* testsuite/gas/arc/relax-mov02.d: Likewise.
* testsuite/gas/arc/relax-mov02.s: Likewise.
* testsuite/gas/arc/relax-mpy01.d: Likewise.
* testsuite/gas/arc/relax-mpy01.s: Likewise.
* testsuite/gas/arc/relax-sub01.d: Likewise.
* testsuite/gas/arc/relax-sub01.s: Likewise.
* testsuite/gas/arc/relax-sub02.d: Likewise.
* testsuite/gas/arc/relax-sub02.s: Likewise.
* testsuite/gas/arc/relax-sub03.d: Likewise.
* testsuite/gas/arc/relax-sub03.s: Likewise.
* testsuite/gas/arc/relax-sub04.d: Likewise.
* testsuite/gas/arc/relax-sub04.s: Likewise.
2017-02-09 Vineet Gupta <vgupta@synopsys.com>
* testsuite/gas/arc/st.d: Update for 0xe having a name now
2017-02-14 Alan Modra <amodra@gmail.com>
PR 21118
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
2017-02-14 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/cell.s: Correct invalid registers.
* testsuite/gas/ppc/vle-simple-1.s: Likewise.
* testsuite/gas/ppc/vle-simple-2.s: Likewise.
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
syntax.
* testsuite/gas/arm/vcmp-noprefix-imm.d: New file.
* testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-02 Maciej W. Rozycki <macro@imgtec.com>
* doc/as.texinfo (Overview): Select MIPS options for man page
inclusion.
MIPS: Add options to control branch ISA checks Complement commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") and add GAS and LD options to control the checks for invalid branches between ISA modes introduced there, to help with some handwritten code lacking `.insn' annotation for labels used as branch targets and code produced by older versions of GCC which suffers from the issue with branches to code that has been optimized away, addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with `.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>. bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to... (_bfd_mips_elf_linker_flags): ... this. Add another parameter. * elfxx-mips.c (mips_elf_link_hash_table): Add `ignore_branch_isa' member. (mips_elf_perform_relocation): Do not treat an ISA mode mismatch in branch relocation calculation as an error if `ignore_branch_isa' has been set. (_bfd_mips_elf_insn32): Rename to... (_bfd_mips_elf_linker_flags): ... this. Rename the `on' parameter to `insn32' and add an `ignore_branch_isa' parameter. Handle the new parameter. gas/ * config/tc-mips.c (mips_ignore_branch_isa): New variable. (options): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (md_longopts): Add "mignore-branch-isa" and "mno-ignore-branch-isa" options. (md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. (fix_bad_cross_mode_branch_p): Return FALSE if `mips_ignore_branch_isa' has been set. (md_show_usage): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa'. * doc/as.texinfo (Target MIPS options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. (-mignore-branch-isa, -mno-ignore-branch-isa): New options. * doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. * testsuite/gas/mips/branch-local-ignore-2.d: New test. * testsuite/gas/mips/branch-local-ignore-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * emultempl/mipself.em (ignore_branch_isa): New variable. (mips_create_output_section_statements): Rename `_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags', add `ignore_branch_isa' argument. (PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and "no-ignore-branch-isa" options. (PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and `--no-ignore-branch-isa'. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. * ld.texinfo (Options specific to MIPS targets): Add `--ignore-branch-isa' and `--no-ignore-branch-isa' options. (ld and the MIPS family): Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-01-30 18:11:22 +01:00
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
(options): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(md_longopts): Add "mignore-branch-isa" and
"mno-ignore-branch-isa" options.
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
(fix_bad_cross_mode_branch_p): Return FALSE if
`mips_ignore_branch_isa' has been set.
(md_show_usage): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa'.
* doc/as.texinfo (Target MIPS options): Add
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa' options.
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/branch-local-2.d: New test.
* testsuite/gas/mips/branch-local-3.d: New test.
* testsuite/gas/mips/branch-local-n32-2.d: New test.
* testsuite/gas/mips/branch-local-n32-3.d: New test.
* testsuite/gas/mips/branch-local-n64-2.d: New test.
* testsuite/gas/mips/branch-local-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
PR 21056
* testsuite/gas/tic6x/insns16-parallel.s: New test case.
* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (aarch64*-*-rtems*): Remove.
(bfin-*-rtems*): Likewise.
(h8300-*-rtems*): Likewise.
(i386-*-rtems*): Likewise.
(m32c-*-rtems*): Likewise.
(m32r-*-rtems*): Likewise.
(m68k-*-rtems*): Likewise.
(mips-*-rtems*): Likewise.
(nios2-*-rtems*): Likewise.
(ppc-*-rtems*): Likewise.
(sh-*-rtems*): Likewise.
(sparc64-*-rtems*): Likewise.
(sparc-*-rtems*): Likewise.
(*-*-rtems*) Use ELF format.
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (arm-*-rtems*): Move to (arm-*-eabi*).
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (sh-*-rtemscoff*): Remove.
2017-01-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (riscv*-*-*): Remove em=linux.
Fix spelling mistakes and typos in the GAS sources. PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-23 16:23:07 +01:00
2017-01-23 Sebastian Rasmussen <sebras@gmail.com>
PR gas/21072
* asintl.h: Fix spelling mistakes and typos.
* atof-generic.c: Likewise.
* bit_fix.h: Likewise.
* config/atof-ieee.c: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff-seh.h: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-evax.c: Likewise.
* config/obj-macho.c: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-epiphany.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mep.h: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-msp430.h: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-nios2.h: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-pru.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/te-vms.c: Likewise.
* config/xtensa-relax.c: Likewise.
* doc/as.texinfo: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-nds32.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-riscv.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-tilegx.texi: Likewise.
* doc/c-tilepro.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* itbl-ops.c: Likewise.
* listing.c: Likewise.
* macro.c: Likewise.
* po/gas.pot: Likewise.
* read.c: Likewise.
* struc-symbol.h: Likewise.
* symbols.h: Likewise.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* write.c: Likewise.
2017-01-23 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
2017-01-20 Nick Clifton <nickc@redhat.com>
* config/tc-i386.c (parse_operands): Check for operand overflow
before setting the unspecified bit.
PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sections Correct a regression from commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which caused symbols in linkonce or what is these days known as comdat sections to be treated as external for the purpose of PIC relocation generation even if their binding remains STB_LOCAL. This in turn disabled GOT16/LO16 relocation pairing with references to such symbols, as no complementing LO16 relocation is expected for external GOT16 references in the o32 ABI, which ultimately leads to link errors, e.g.: ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]' as with the LD test case included with this change. Revert the special case for symbols in comdat sections then, making code actually match `adjust_reloc_syms' as indicated in its explanatory comment, and adjust calling code accordingly. Also bring back the corresponding description of what now is `s_is_linkonce', lost with commit 5f0fe04bc550 ("Improved MIPS16/MIPS32 code intermixing for gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>. gas/ PR gas/20649 * config/tc-mips.c (pic_need_relax): Don't check for linkonce symbols, remove the `segtype' parameter. (mips_frob_file, md_estimate_size_before_relax): Adjust accordingly. (s_is_linkonce): Add an explanatory comment. * testsuite/gas/mips/comdat-reloc.d: New test. * testsuite/gas/mips/comdat-reloc.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. ld/ PR gas/20649 * testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16 relocation pairing link test.
2017-01-18 19:18:21 +01:00
2017-01-18 Maciej W. Rozycki <macro@imgtec.com>
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-18 Bernhard Rosenkranzer <bero@lindev.ch>
PR 21059
* config/bfin-lex.l: Support processing with flex 2.6.3.
* itbl-lex.l: Likewise.
2017-01-18 Nathan Sidwell <nathan@acm.org>
* as.h (gas_assert): Use abort.
(as_assert): Remove.
(signal_init): Declare.
* as.c (main): Call signal_init.
* messages.c: #include <signal.h>
(as_assert): Delete.
(as_abort): Allow NULL FILE.
(signal_crash): New.
(signal_init): Register fatal signal handlers.
* configure.ac: Check for strsignal.
* config.in: Rebuilt.
* configure: Rebuilt.
2017-01-18 12:35:29 +01:00
2017-01-17 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
(cpu_noarch): Add noavx512_vpopcntdq.
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
2017-01-12 Nick Clifton <nickc@redhat.com>
* read.c (temp_ilp): New function. Installs a temporary input
line pointer.
(restore_ilp): New function. Restores the original input line
pointer.
* read.h (temp_ilp): Prototype.
(restore_ilp): Prototype.
* stabs.c (dot_func_p): Use bfd_boolean type.
(generate_asm_file): Use temp_ilp and restore_ilp.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_endfunc): Likewise.
2017-01-11 Jeremy Soller <jackpot51@gmail.com>
* configure.tgt: Add entry for i386-redox.
2017-01-10 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
2017-01-10 Tristan Gingold <gingold@adacore.com>
* testsuite/gas/all/sleb128-8.d: Adjust test.
* testsuite/gas/all/gas.exp (test_cond): Likewise.
2017-01-10 Tristan Gingold <gingold@adacore.com>
* read.c (emit_leb128_expr): Extended unsigned big number for
sleb128.
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
* testsuite/gas/all/sleb128.d: New test.
* testsuite/gas/all/sleb128.s: New test source.
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
Kito Cheng <kito.cheng@gmail.com>
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
Removed.
(SDATA_START_SYMBOLS): Likewise.
2017-01-09 Nick Clifton <nickc@redhat.com>
* po/sv.po: New Swedish translation.
* configure.ac (ALL_LINGUAS): Add sv.
* configure: Regenerate.
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (relaxed_branch_length): Use the long
sequence when the target is a weak symbol.
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04 Norm Jacobs <norm.jacobs@oracle.com>
PR gas/20992
* configure.tgt: Treat sparcv9 as sparc64.
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
2017-01-03 Dimitar Dimitrov <dimitar@dinux.eu>
* config/tc-pru.c (md_number_to_chars): Fix parameter to be
valueT, as declared in tc.h.
(md_apply_fix): Fix to work on 32-bit hosts.
2017-01-02 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
2017-01-02 04:25:05 +01:00
For older changes see ChangeLog-2016
2017-01-02 04:25:05 +01:00
Copyright (C) 2017 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
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