binutils-gdb/gas/ChangeLog

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2016-12-21 15:09:02 +01:00
2016-12-21 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
(riscv_frag_align_code): Correct frag_align_code arg.
2016-12-21 15:09:02 +01:00
2016-12-21 Tim Newsome <tim@sifive.com>
* config/tc-riscv.c (riscv_pre_output_hook): Remove const from
loc4_frag.
2016-12-21 Alan Modra <amodra@gmail.com>
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
2016-12-21 Alan Modra <amodra@gmail.com>
PR gas/10946
* doc/as.texinfo (Chars): Document escape sequences.
MIPS16/opcodes: Respect ISA and ASE in disassembly Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20 12:38:53 +01:00
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16e.s: Add a RESTORE instruction.
* testsuite/gas/mips/mips16e.d: Adjust accordingly.
MIPS/GAS/testsuite: Extend MIPS16 testing over multiple ISAs Run the `mips16', `mips16-64', `mips16e-64', `mips16-macro', `mips16-macro-e' and `mips16-macro-t' GAS tests over multiple MIPS16 ISAs. gas/ * testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-macro.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation. * testsuite/gas/mips/mips16e-64.l: Rename to... * testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this. * testsuite/gas/mips/mips16-64@mips16.d: New test. * testsuite/gas/mips/mips16-64@mips16-64.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-64@mips16-macro.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64', `mips16-macro', `mips16-macro-t', `mips16-macro-e' and `mips16e-64' testing across multiple MIPS16 ISAs. Fold `mips16-macro' and `mips16e-64' list test invocations into corresponding dump tests.
2016-12-20 12:33:49 +01:00
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16
ISA testing.
* testsuite/gas/mips/mips16-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16-macro.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation.
* testsuite/gas/mips/mips16e-64.l: Rename to...
* testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this.
* testsuite/gas/mips/mips16-64@mips16.d: New test.
* testsuite/gas/mips/mips16-64@mips16-64.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-macro.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64',
`mips16-macro', `mips16-macro-t', `mips16-macro-e' and
`mips16e-64' testing across multiple MIPS16 ISAs. Fold
`mips16-macro' and `mips16e-64' list test invocations into
corresponding dump tests.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e' and `mips16' prefixes.
(run_list_test_arch): Likewise.
Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
`mips16e-32' and `mips16e-64' architectures. Update `rol64',
`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
accordingly.
* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
* testsuite/gas/mips/mips16e@loc-swap.d: New test.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for
trailing alignment padding.
* testsuite/gas/mips/loc-swap.d: Adjust accordingly.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
MIPS16: Switch to 32-bit opcode table interpretation Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20 03:03:40 +01:00
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-macro.l: New list test.
* testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-sdrasp.d: New test.
* testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
* testsuite/gas/mips/mips16-sdrasp.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp: Limit remaining tests that
require NewABI support to `has_newabi' targets.
2015-12-20 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (riscv_pseudo_table): Remove "align",
"p2align", and "balign".
(s_align): Remove.
(riscv_handle_align): New function.
(riscv_frag_align_code): Likewise.
(riscv_make_nops): Likewise.
* config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7.
(HANDLE_ALIGN): Define.
(md_do_align): Define.
(riscv_handle_align): Declare.
(riscv_frag_align_code): Likewise.
Re-work RISC-V gas flags: now we just support -mabi and -march We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-19 07:53:50 +01:00
2016-12-20 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.h (xlen): Delete.
* config/tc-riscv.c (xlen): Make static.
(abi_xlen): New variable.
(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
with OPTION_MABI.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(riscv_elf_final_processing): Likewise.
* doc/as.texinfo (Target RISC-V options): Likewise.
* doc/c-riscv.texi (OPTIONS): Likewise.
* config/tc-riscv.c (float_mode): Removed.
(float_abi): New type, specifies the floating-point ABI.
(riscv_set_abi): New function.
(riscv_add_subset): Only allow lower-case ISA names and require
them to start with "rv".
(riscv_after_parse_args): Likewise.
Rework RISC-V relocations Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-19 07:53:48 +01:00
2016-12-20 Andrew Waterman <andrew@sifive.com>
Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-riscv.c (riscv_set_options): Add relax.
(riscv_opts): Likewise.
(s_riscv_option): Add relax and norelax.
(riscv_apply_const_reloc): New function.
(append_insn): Move constant relocation handling to
riscv_apply_const_reloc.
(md_pcrel_from): Likewise.
(parse_relocation): Skip BFD_RELOC_UNUSED.
(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
(md_apply_fix): Likewise.
(riscv_pre_output_hook): New function.
* config/tc-riscv.h (md_pre_output_hook): Define.
(riscv_pre_output_hook): Declare.
(DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-20 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c: Formatting and comment fixes throughout.
2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Report an error instead of
asserting on `ext'.
* testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
* testsuite/gas/mips/mips16-branch-unextended.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-sprel-swap.d: New test.
* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2016-12-13 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
(get_reg_expected_msg): Remove CN register case.
(parse_operands): rewrite parser for CRn, CRm operand.
(reg_names): Remove CN register.
* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
[AArch64] Make GAS testcases support ILP32 mode gas/ * gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode. * gas/testsuite/gas/aarch64/advsimd-across.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise. * gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise. * gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise. * gas/testsuite/gas/aarch64/alias.d: Likewise. * gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise. * gas/testsuite/gas/aarch64/b_1.d: Likewise. * gas/testsuite/gas/aarch64/beq_1.d: Likewise. * gas/testsuite/gas/aarch64/bitfield-dump: Likewise. * gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/codealign.d: Likewise. * gas/testsuite/gas/aarch64/codealign_1.d: Likewise. * gas/testsuite/gas/aarch64/crc32-directive.d: Likewise. * gas/testsuite/gas/aarch64/crc32.d: Likewise. * gas/testsuite/gas/aarch64/crypto-directive.d: Likewise. * gas/testsuite/gas/aarch64/crypto.d: Likewise. * gas/testsuite/gas/aarch64/dwarf.d: Likewise. * gas/testsuite/gas/aarch64/float-fp16.d: Likewise. * gas/testsuite/gas/aarch64/floatdp2.d: Likewise. * gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise. * gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise. * gas/testsuite/gas/aarch64/fpmov.d: Likewise. * gas/testsuite/gas/aarch64/inst-directive.d: Likewise. * gas/testsuite/gas/aarch64/ldr_1.d: Likewise. * gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * gas/testsuite/gas/aarch64/lor-directive.d: Likewise. * gas/testsuite/gas/aarch64/lor.d: Likewise. * gas/testsuite/gas/aarch64/lse-atomic.d: Likewise. * gas/testsuite/gas/aarch64/mapmisc.d: Likewise. * gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/mov.d: Likewise. * gas/testsuite/gas/aarch64/movi.d: Likewise. * gas/testsuite/gas/aarch64/movw_label.d: Likewise. * gas/testsuite/gas/aarch64/msr.d: Likewise. * gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise. * gas/testsuite/gas/aarch64/neon-frint.d: Likewise. * gas/testsuite/gas/aarch64/neon-ins.d: Likewise. * gas/testsuite/gas/aarch64/neon-not.d: Likewise. * gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise. * gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise. * gas/testsuite/gas/aarch64/no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/optional.d: Likewise. * gas/testsuite/gas/aarch64/pac.d: Likewise. * gas/testsuite/gas/aarch64/pan-directive.d: Likewise. * gas/testsuite/gas/aarch64/pan.d: Likewise. * gas/testsuite/gas/aarch64/rdma-directive.d: Likewise. * gas/testsuite/gas/aarch64/rdma.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise. * gas/testsuite/gas/aarch64/shifted.d: Likewise. * gas/testsuite/gas/aarch64/sve.d: Likewise. * gas/testsuite/gas/aarch64/symbol.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-1.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-2.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-3.d: Likewise. * gas/testsuite/gas/aarch64/sysreg.d: Likewise. * gas/testsuite/gas/aarch64/system-2.d: Likewise. * gas/testsuite/gas/aarch64/system-3.d: Likewise. * gas/testsuite/gas/aarch64/system.d: Likewise. * gas/testsuite/gas/aarch64/tbz_1.d: Likewise. * gas/testsuite/gas/aarch64/tlbi_op.d: Likewise. * gas/testsuite/gas/aarch64/tls.d: Likewise. * gas/testsuite/gas/aarch64/uao-directive.d: Likewise. * gas/testsuite/gas/aarch64/uao.d: Likewise. * gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise. * gas/testsuite/gas/aarch64/virthostext.d: Likewise. * gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64. * gas/testsuite/gas/aarch64/int-insns.d: Likewise. * gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise. * gas/testsuite/gas/aarch64/reloc-data.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-insn.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise. * gas/testsuite/gas/aarch64/tail_padding.d: Likewise. * gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
2016-12-13 13:46:35 +01:00
2016-12-13 Jiong Wang <jiong.wang@arm.com>
* gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode.
* gas/testsuite/gas/aarch64/advsimd-across.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise.
* gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise.
* gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise.
* gas/testsuite/gas/aarch64/alias.d: Likewise.
* gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise.
* gas/testsuite/gas/aarch64/b_1.d: Likewise.
* gas/testsuite/gas/aarch64/beq_1.d: Likewise.
* gas/testsuite/gas/aarch64/bitfield-dump: Likewise.
* gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/codealign.d: Likewise.
* gas/testsuite/gas/aarch64/codealign_1.d: Likewise.
* gas/testsuite/gas/aarch64/crc32-directive.d: Likewise.
* gas/testsuite/gas/aarch64/crc32.d: Likewise.
* gas/testsuite/gas/aarch64/crypto-directive.d: Likewise.
* gas/testsuite/gas/aarch64/crypto.d: Likewise.
* gas/testsuite/gas/aarch64/dwarf.d: Likewise.
* gas/testsuite/gas/aarch64/float-fp16.d: Likewise.
* gas/testsuite/gas/aarch64/floatdp2.d: Likewise.
* gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise.
* gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise.
* gas/testsuite/gas/aarch64/fpmov.d: Likewise.
* gas/testsuite/gas/aarch64/inst-directive.d: Likewise.
* gas/testsuite/gas/aarch64/ldr_1.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
* gas/testsuite/gas/aarch64/lor-directive.d: Likewise.
* gas/testsuite/gas/aarch64/lor.d: Likewise.
* gas/testsuite/gas/aarch64/lse-atomic.d: Likewise.
* gas/testsuite/gas/aarch64/mapmisc.d: Likewise.
* gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/mov.d: Likewise.
* gas/testsuite/gas/aarch64/movi.d: Likewise.
* gas/testsuite/gas/aarch64/movw_label.d: Likewise.
* gas/testsuite/gas/aarch64/msr.d: Likewise.
* gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise.
* gas/testsuite/gas/aarch64/neon-frint.d: Likewise.
* gas/testsuite/gas/aarch64/neon-ins.d: Likewise.
* gas/testsuite/gas/aarch64/neon-not.d: Likewise.
* gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise.
* gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise.
* gas/testsuite/gas/aarch64/no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/optional.d: Likewise.
* gas/testsuite/gas/aarch64/pac.d: Likewise.
* gas/testsuite/gas/aarch64/pan-directive.d: Likewise.
* gas/testsuite/gas/aarch64/pan.d: Likewise.
* gas/testsuite/gas/aarch64/rdma-directive.d: Likewise.
* gas/testsuite/gas/aarch64/rdma.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
* gas/testsuite/gas/aarch64/shifted.d: Likewise.
* gas/testsuite/gas/aarch64/sve.d: Likewise.
* gas/testsuite/gas/aarch64/symbol.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-1.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-2.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-3.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg.d: Likewise.
* gas/testsuite/gas/aarch64/system-2.d: Likewise.
* gas/testsuite/gas/aarch64/system-3.d: Likewise.
* gas/testsuite/gas/aarch64/system.d: Likewise.
* gas/testsuite/gas/aarch64/tbz_1.d: Likewise.
* gas/testsuite/gas/aarch64/tlbi_op.d: Likewise.
* gas/testsuite/gas/aarch64/tls.d: Likewise.
* gas/testsuite/gas/aarch64/uao-directive.d: Likewise.
* gas/testsuite/gas/aarch64/uao.d: Likewise.
* gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise.
* gas/testsuite/gas/aarch64/virthostext.d: Likewise.
* gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64.
* gas/testsuite/gas/aarch64/int-insns.d: Likewise.
* gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-data.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-insn.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
* gas/testsuite/gas/aarch64/tail_padding.d: Likewise.
* gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-extend.d: New test.
* testsuite/gas/mips/mips16-extend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local
variable to `space_buf'.
2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-arm.c (encode_arm_shift): Rename `index' local
variable to `op_index'.
2016-12-08 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (is_opcode_valid): Use local `isa'
consistently.
2016-12-06 Nick Clifton <nickc@redhat.com>
PR gas/20901
* read.c (s_space): Place an upper limit on the number of spaces
generated.
PR gas/20896
* testsuite/gas/mmix/err-byte1.s: Adjust expected warning messages
to account for patch to next_char_of_string.
2016-12-05 Nick Clifton <nickc@redhat.com>
PR gas/20902
* read.c (next_char_of_string): Do end advance past the end of the
buffer.
PR gas/20904
* as.h (SKIP_ALL_WHITESPACE): New macro.
* expr.c (operand): Use it.
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
2016-12-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister-1.d: New file.
* testsuite/gas/arc/textauxregister-1.s: Likewise.
* testsuite/gas/arc/textcondcode-err.s: Likewise.
* testsuite/gas/arc/textcoreregister-err.s: Likewise.
* config/tc-arc.c (tokenize_extregister): Return bfd_boolean,
don't check second argument of extension auxiliary register for
signess.
(arc_extcorereg): Consider the return of tokenize_extregister
function call.
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
(insns): Add vjcvt.
* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
2016-12-02 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cpu-em-err.s: New file.
* testsuite/gas/arc/cpu-em4-err.s: Likewise.
* testsuite/gas/arc/cpu-fpuda-err.s: Likewise.
* testsuite/gas/arc/cpu-hs-err.s: Likewise.
* testsuite/gas/arc/cpu-quarkse-err.s: Likewise.
* testsuite/gas/arc/noargs_a7.s: Add .cpu.
* config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define.
(ARC_CPU_TYPE_A7xx): Likewise.
(ARC_CPU_TYPE_AV2EM): Likewise.
(ARC_CPU_TYPE_AV2HS): Likewise.
(cpu_types): Update list of known CPU names.
(arc_show_cpu_list): New function.
(md_show_usage): Print accepted CPU names.
(cl_features): New variable.
(arc_select_cpu): Use cl_features.
(arc_option): Allow various .cpu names.
(md_parse_option): Set cl_features.
* doc/c-arc.texi: Update -mcpu and .cpu documentation.
2016-12-02 Josh Conner <joshconner@google.com>
* configure.tgt: Add support for fuchsia (OS).
2016-12-01 Nick Clifton <nickc@redhat.com>
PR gas/20898
* app.c (do_scrub_chars): Do not attempt to unget EOF.
PR gas/20897
* subsegs.c (subsegs_print_statistics): Do nothing if no output
file was created.
PR gas/20895
* symbols.c (resolve_symbol_value): Gracefully handle erroneous
symbolic expressions.
[ARC] Add checking for LP_COUNT reg usage, improve error reporting. gas/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes.
2016-11-15 15:11:47 +01:00
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
Amit Pawar <amit.pawar@amd.com>
PR binutils/20637
* testsuite/gas/i386/xop32reg.d: New file.
* testsuite/gas/i386/xop32reg.s: New file.
* testsuite/gas/i386/i386.exp: Run new test.
2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* arparse.y: Fix spelling in comments.
2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* config/bfin-lex.l: Fix spelling in comments.
2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* testsuite/gas/all/gas.exp: Fix spelling in comments.
* testsuite/gas/cris/cris.exp: Fix spelling in comments.
* testsuite/gas/hppa/basic/basic.exp: Fix spelling in comments.
* testsuite/gas/hppa/parse/parse.exp: Fix spelling in comments.
* testsuite/gas/hppa/reloc/reloc.exp: Fix spelling in comments.
* testsuite/gas/sh/arch/arch.exp: Fix spelling in comments.
* testsuite/gas/tic4x/tic4x.exp: Fix spelling in comments.
2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* testsuite/gas/arm/local_function.d: Fix spelling in comments.
* testsuite/gas/arm/req.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1xD.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments.
* testsuite/gas/mcore/allinsn.s: Fix spelling in comments.
* testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments.
* testsuite/gas/mips/delay.d: Fix spelling in comments.
* testsuite/gas/mips/nodelay.d: Fix spelling in comments.
* testsuite/gas/mips/r5900-full.s: Fix spelling in comments.
* testsuite/gas/mips/r5900.s: Fix spelling in comments.
Fix spelling in comments in C source files (gas) * as.h: Fix spelling in comments. * config/obj-ecoff.c: Fix spelling in comments. * config/obj-macho.c: Fix spelling in comments. * config/tc-aarch64.c: Fix spelling in comments. * config/tc-arc.c: Fix spelling in comments. * config/tc-arm.c: Fix spelling in comments. * config/tc-avr.c: Fix spelling in comments. * config/tc-cr16.c: Fix spelling in comments. * config/tc-epiphany.c: Fix spelling in comments. * config/tc-frv.c: Fix spelling in comments. * config/tc-hppa.c: Fix spelling in comments. * config/tc-hppa.h: Fix spelling in comments. * config/tc-i370.c: Fix spelling in comments. * config/tc-m68hc11.c: Fix spelling in comments. * config/tc-m68k.c: Fix spelling in comments. * config/tc-mcore.c: Fix spelling in comments. * config/tc-mep.c: Fix spelling in comments. * config/tc-metag.c: Fix spelling in comments. * config/tc-mips.c: Fix spelling in comments. * config/tc-mn10200.c: Fix spelling in comments. * config/tc-mn10300.c: Fix spelling in comments. * config/tc-nds32.c: Fix spelling in comments. * config/tc-nios2.c: Fix spelling in comments. * config/tc-ns32k.c: Fix spelling in comments. * config/tc-pdp11.c: Fix spelling in comments. * config/tc-ppc.c: Fix spelling in comments. * config/tc-riscv.c: Fix spelling in comments. * config/tc-rx.c: Fix spelling in comments. * config/tc-score.c: Fix spelling in comments. * config/tc-score7.c: Fix spelling in comments. * config/tc-sparc.c: Fix spelling in comments. * config/tc-tic54x.c: Fix spelling in comments. * config/tc-vax.c: Fix spelling in comments. * config/tc-xgate.h: Fix spelling in comments. * config/tc-xtensa.c: Fix spelling in comments. * config/tc-z80.c: Fix spelling in comments. * dwarf2dbg.c: Fix spelling in comments. * input-file.h: Fix spelling in comments. * itbl-ops.c: Fix spelling in comments. * read.c: Fix spelling in comments. * stabs.c: Fix spelling in comments. * symbols.c: Fix spelling in comments. * write.c: Fix spelling in comments. * testsuite/gas/all/itbl-test.c: Fix spelling in comments. * testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
2016-11-25 21:01:41 +01:00
2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* as.h: Fix spelling in comments.
* config/obj-ecoff.c: Fix spelling in comments.
* config/obj-macho.c: Fix spelling in comments.
* config/tc-aarch64.c: Fix spelling in comments.
* config/tc-arc.c: Fix spelling in comments.
* config/tc-arm.c: Fix spelling in comments.
* config/tc-avr.c: Fix spelling in comments.
* config/tc-cr16.c: Fix spelling in comments.
* config/tc-epiphany.c: Fix spelling in comments.
* config/tc-frv.c: Fix spelling in comments.
* config/tc-hppa.c: Fix spelling in comments.
* config/tc-hppa.h: Fix spelling in comments.
* config/tc-i370.c: Fix spelling in comments.
* config/tc-m68hc11.c: Fix spelling in comments.
* config/tc-m68k.c: Fix spelling in comments.
* config/tc-mcore.c: Fix spelling in comments.
* config/tc-mep.c: Fix spelling in comments.
* config/tc-metag.c: Fix spelling in comments.
* config/tc-mips.c: Fix spelling in comments.
* config/tc-mn10200.c: Fix spelling in comments.
* config/tc-mn10300.c: Fix spelling in comments.
* config/tc-nds32.c: Fix spelling in comments.
* config/tc-nios2.c: Fix spelling in comments.
* config/tc-ns32k.c: Fix spelling in comments.
* config/tc-pdp11.c: Fix spelling in comments.
* config/tc-ppc.c: Fix spelling in comments.
* config/tc-riscv.c: Fix spelling in comments.
* config/tc-rx.c: Fix spelling in comments.
* config/tc-score.c: Fix spelling in comments.
* config/tc-score7.c: Fix spelling in comments.
* config/tc-sparc.c: Fix spelling in comments.
* config/tc-tic54x.c: Fix spelling in comments.
* config/tc-vax.c: Fix spelling in comments.
* config/tc-xgate.h: Fix spelling in comments.
* config/tc-xtensa.c: Fix spelling in comments.
* config/tc-z80.c: Fix spelling in comments.
* dwarf2dbg.c: Fix spelling in comments.
* input-file.h: Fix spelling in comments.
* itbl-ops.c: Fix spelling in comments.
* read.c: Fix spelling in comments.
* stabs.c: Fix spelling in comments.
* symbols.c: Fix spelling in comments.
* write.c: Fix spelling in comments.
* testsuite/gas/all/itbl-test.c: Fix spelling in comments.
* testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error
messages for non-cbcond instructions.
* testsuite/gas/sparc/cbcond-diag.s: New file.
* testsuite/gas/sparc/cbcond-diag.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
2016-11-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Make sure the
hwcaps-bump test is run with 64-bit objects.
2016-11-23 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-riscv.c: Add missing break.
2016-11-23 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
gas,opcodes: fix hardware capabilities bumping in the sparc assembler. When the assembler finds an instruction which is part of a higher opcode architecture it bumps the current opcode architecture. For example: $ echo "mwait" | as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" However, when two instructions pertaining to the same opcode architecture but associated to different SPARC hardware capabilities are found in the input stream, and no GAS architecture is specified in the command line, the assembler bangs: $ echo "mwait; wr %g0,%g1,%mcdper" | as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" {standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr". ... and it should'nt, as WRMCDPER pertains to the same architecture level than MWAIT. This patch fixes this by extending the definition of sparc opcode architectures to contain a set of hardware capabilities and making the assembler to take these capabilities into account when updating the set of allowed hwcaps when an architecture bump is triggered by some instruction. This way, hwcaps associated to architecture levels are maintained in opcodes, while the assembler keeps the flexibiity of defining GAS architectures including additional hwcaps (like -Asparcfmaf or the v8plus* variants). A test covering this failure case is included. gas/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c: Move HWS_* and HWS2_* definitions to opcodes/sparc-opc.c. (sparc_arch): Clarify the new role of the hwcap_allowed and hwcap2_allowed fields. (sparc_arch_table): Remove HWS_* and HWS2_* instances from hwcap_allowed and hwcap2_allowed respectively. (md_parse_option): Include the opcode arch hwcaps when processing -A. (sparc_ip): Use the current opcode arch hwcaps to update hwcap_allowed, as well of the hwcaps of the instruction triggering the bump. * testsuite/gas/sparc/hwcaps-bump.s: New file. * testsuite/gas/sparc/hwcaps-bump.l: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in hwcaps-bump. include/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and hwcaps2. opcodes/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (HWS_V8): Definition moved from gas/config/tc-sparc.c. (HWS_V9): Likewise. (HWS_VA): Likewise. (HWS_VB): Likewise. (HWS_VC): Likewise. (HWS_VD): Likewise. (HWS_VE): Likewise. (HWS_VV): Likewise. (HWS_VM): Likewise. (HWS2_VM): Likewise. (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of existing entries.
2016-11-22 13:40:37 +01:00
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well as the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test result.
2016-11-22 Alan Modra <amodra@gmail.com>
PR 20744
* config/tc-ppc.c: Delete VLE insn defines.
(md_assemble): Swap use_a_reloc and use_d_reloc.
* testsuite/gas/ppc/vle-reloc.d: Update.
2016-11-21 Renlin Li <renlin.li@arm.com>
PR gas/20827
* config/tc-arm.c (encode_arm_shift): Don't assert for operands not
presented.
* testsuite/gas/arm/add-shift-two.d: New.
* testsuite/gas/arm/add-shift-two.s: New.
2016-11-21 Alan Modra <amodra@gmail.com>
* configure.ac: Invoke ACX_PROG_CMP_IGNORE_INITIAL.
* Makefile.am (comparison): Rewrite using do_compare.
* configure: Regenerate.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
2016-11-18 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cl-warn.s: New file.
* testsuite/gas/arc/cpu-pseudop-1.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.s: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.s: Likewise.
* testsuite/gas/arc/cpu-warn2.s: Likewise.
* config/tc-arc.c (selected_cpu): Initialize.
(feature_type): New struct.
(feature_list): New variable.
(arc_check_feature): New function.
(arc_select_cpu): Check for .cpu duplicates. Don't overwrite the
current cpu features. Check if a feature is available for a given
cpu.
(md_parse_option): Test if features are available for a given cpu.
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions Add support for FCMLA and FCADD complex arithmetic SIMD instructions. FCMLA has an indexed element variant where the index range has to be treated specially because a complex number takes two elements and the indexed vector size depends on the other operands. These complex number SIMD instructions are part of ARMv8.3 https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. (enum aarch64_op): Add OP_FCMLA_ELEM. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. (aarch64_opcode_table): Add fcmla and fcadd. (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. * aarch64-asm.c (aarch64_ins_imm_rotate): Define. * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. * aarch64-dis.c (aarch64_ext_imm_rotate): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. (operand_general_constraint_met_p): Rotate and index range check. (aarch64_print_operand): Handle rotate operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*. * testsuite/gas/aarch64/advsimd-armv8_3.d: New. * testsuite/gas/aarch64/advsimd-armv8_3.s: New. * testsuite/gas/aarch64/illegal-fcmla.s: New. * testsuite/gas/aarch64/illegal-fcmla.l: New. * testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 11:02:16 +01:00
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.s: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.l: Likewise.
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test.
* testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.
[AArch64] Add ARMv8.3 combined pointer authentication load instructions Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and load instructions. These instructions authenticate the base register and load 8 byte from it plus a scaled 10-bit offset with optional writeback to update the base register. A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10) were introduced to handle the special addressing form. include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_X1NIL): New. (arch64_opcode_table): Add ldraa, ldrab. (AARCH64_OPERANDS): Add "ADDR_SIMM10". * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. * aarch64-asm.c (aarch64_ins_addr_simm10): Define. * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. * aarch64-dis.c (aarch64_ext_addr_simm10): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. * aarch64-opc.c (fields): Add data for FLD_S_simm10. (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10. (fix_insn): Likewise. (warn_unpredictable_ldst): Handle ldst_imm10. * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests. * testsuite/gas/aarch64/pac.d: Likewise. * testsuite/gas/aarch64/illegal-ldraa.s: New. * testsuite/gas/aarch64/illegal-ldraa.l: New. * testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-11-18 10:49:06 +01:00
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Handle ldst_imm10.
* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
* testsuite/gas/aarch64/pac.d: Likewise.
* testsuite/gas/aarch64/illegal-ldraa.s: New.
* testsuite/gas/aarch64/illegal-ldraa.l: New.
* testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-11-15 Nick Clifton <nickc@redhat.com>
PR gas/20803
* config/tc-sparc.c (cons_fix_new_sparc): Use unaligned relocs in
the .eh_frame section.
2016-11-13 14:11:44 +01:00
2016-11-13 Anthony Green <green@moxielogic.org>
* config/tc-moxie.c (md_assemble): Assemble 'bad' opcode.
2016-11-11 Nick Clifton <nickc@redhat.com>
PR gas/20732
* expr.c (integer_constant): If tc_allow_L_suffix is defined and
non-zero then accept a L or LL suffix.
* testsuite/gas/sparc/pr20732.d: New test source file.
* testsuite/gas/sparc/pr20732.d: New test output file.
* testsuite/gas/sparc/sparc.exp: Run new test.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/pac.s: Add ARMv8.3 branch instruction tests.
* testsuite/gas/aarch64/pac.d: Likewise.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/pac.s: Add pacga.
* testsuite/gas/aarch64/pac.d: Add pacga.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/pac.s: New.
* testsuite/gas/aarch64/pac.d: New.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/sysreg-3.s: New.
* testsuite/gas/aarch64/sysreg-3.d: New.
* testsuite/gas/aarch64/illegal-sysreg-3.l: New.
* testsuite/gas/aarch64/illegal-sysreg-3.d: New.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/system-3.s: New.
* testsuite/gas/aarch64/system-3.d: New.
* testsuite/gas/aarch64/system.d: Update expected output.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
* doc/c-aarch64.texi (-march): Likewise.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto".
* testsuite/gas/aarch64/illegal-crypto-nofp.d: New.
* testsuite/gas/aarch64/illegal-crypto-nofp.l: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.d: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.l: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20799
* testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode-suffix.d: Likewise.
* testsuite/gas/i386/opcode.d: Likewise.
* testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
tests.
* testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20754
* testsuite/gas/i386/opcode-suffix.d: Updated.
2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20775
* testsuite/gas/i386/i386.exp: Run fpu-bad.
* testsuite/gas/i386/fpu-bad.d: New file.
* testsuite/gas/i386/fpu-bad.s: Likewise.
2016-11-04 Nathan Sidwell <nathan@acm.org>
gas/
* input-scrub.c (partial_size): Make size_t.
(buffer_length): Likewise. Adjust meaning.
(struct input_save): Adjust partial_size type.
(input_scrub_reinit): New.
(input_scrub_push, input_scrub_begin): Use it.
(input_scrub_next_buffer): Fix buffer extension logic. Only scan
newly read buffer for newline.
2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cortex-m33): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M33 processor.
* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cortex-m23): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M23 processor.
* NEWS: Mention ARM Cortex-M23 support.
2016-11-04 Palmer Dabbelt <palmer@dabbelt.com>
Andrew Waterman <andrew@sifive.com>
* Makefile.am (CPU_DOCS): Add c-riscv.texi.
* Makefile.in: Regenerate.
* doc/all.texi: Set RISCV.
* doc/as.texinfo: Add RISCV options.
Add RISC-V-Dependent node.
Include c-riscv.texi.
* doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm
operands are out of the range of an s9, in order to fix the test.
* testsuite/gas/arc/nps400-6.d: Updated to match new expected output.
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps-400-9.d: Added.
* testsuite/gas/arc/nps-400-9.s: Added.
arc: Change max instruction length to 64-bits The current handling for arc instructions longer than 32-bits is all handled as a special case in both the assembler and disassembler. The problem with this approach is that it leads to code duplication, selecting a long instruction is exactly the same process as selecting a short instruction, except over more bits, in both cases we select based on bit comparison, and initial operand insertion and extraction. This commit unifies both the long and short instruction worlds, converting the core opcodes library from being largely 32-bit focused, to being largely 64-bit focused. The changes are, on the whole, not too much. There's obviously a lot of type changes but otherwise the bulk of the code just works. Most of the actual functional changes are to code that previously handled the longer 48 or 64 bit instructions. The insert/extract handlers for these have now been brought into line with the short instruction insert/extract handlers. All of the special case handling code that was previously added has now been removed again. Overall, this commit reduces the amount of code in the arc assembler and disassembler. gas/ChangeLog: * config/tc-arc.c (struct arc_insn): Change type of insn field. (md_number_to_chars_midend): Support 6- and 8-byte values. (emit_insn0): Update debug output. (find_opcode_match): Likewise. (build_fake_opcode_hash_entry): Delete. (find_special_case_long_opcode): Delete. (find_special_case): Remove long format special case handling. (insert_operand): Change instruction type and update debug print format. (assemble_insn): Change instruction type, update debug print formats, and remove unneeded assert. include/ChangeLog: * opcode/arc.h (struct arc_opcode): Change type of opcode and mask fields. (struct arc_long_opcode): Delete. (struct arc_operand): Change types for insert and extract handlers. opcodes/ChangeLog: * arc-dis.c (struct arc_operand_iterator): Remove all fields relating to long instruction processing, add new limm field. (OPCODE): Rename to... (OPCODE_32BIT_INSN): ...this. (OPCODE_AC): Delete. (skip_this_opcode): Handle different instruction lengths, update macro name. (special_flag_p): Update parameter type. (find_format_from_table): Update for more instruction lengths. (find_format_long_instructions): Delete. (find_format): Update for more instruction lengths. (arc_insn_length): Likewise. (extract_operand_value): Update for more instruction lengths. (operand_iterator_next): Remove code relating to long instructions. (arc_opcode_to_insn_type): New function. (print_insn_arc):Update for more instructions lengths. * arc-ext.c (extInstruction_t): Change argument type. * arc-ext.h (extInstruction_t): Change argument type. * arc-fxi.h: Change type unsigned to unsigned long long extensively throughout. * arc-nps400-tbl.h: Add long instructions taken from arc_long_opcodes table in arc-opc.c. * arc-opc.c: Update parameter types on insert/extract handlers. (arc_long_opcodes): Delete. (arc_num_long_opcodes): Delete. (arc_opcode_len): Update for more instruction lengths.
2016-07-06 20:39:55 +02:00
2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (struct arc_insn): Replace short_insn flag with
len field.
(apply_fixups): Update to use len field.
(emit_insn0): Simplify code, making use of len field.
(md_convert_frag): Update to use len field.
(assemble_insn): Update to use len field.
2016-11-03 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org>
* config/tc-aarch64.c (aarch64_cpus): Add falkor.
* config/tc-arm.c (arm_cpus): Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-arm.texi: Likewise.
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20754
* testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode.d: Likewise.
2016-11-02 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (SBIT_SHIFT): New.
(T2_SBIT_SHIFT): Likewise.
(t32_insn_ok): Return TRUE for MOV in ARMv8-M Baseline.
(md_apply_fix): Try UINT16 encoding when ARM/Thumb modified immediate
encoding failed.
* testsuite/gas/arm/archv6t2-bad.s: New error case.
* testsuite/gas/arm/archv6t2-bad.l: New error match.
* testsuite/gas/arm/archv6t2.s: New testcase.
* testsuite/gas/arm/archv6t2.d: New expected result.
* testsuite/gas/arm/archv8m.s: New testcase.
* testsuite/gas/arm/archv8m-base.d: New expected result.
* testsuite/gas/arm/archv8m-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
(cpu_noarch): Add noavx512_4vnniw.
* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.
Enable Intel AVX512_4FMAPS instructions gas/ * config/tc-i386.c (cpu_arch): Add .avx512_4fmaps. (cpu_noarch): Add noavx512_4fmaps. (process_operands): Handle implicit quad group. * doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps. * testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test. * testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto. * testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto. * testsuite/gas/i386/avx512_4fmaps.d: Ditto. * testsuite/gas/i386/avx512_4fmaps.s: Ditto. * testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto. * testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto. opcodes/ * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS, CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4FMAPS. (opcode_modifiers): Add ImplicitQuadGroup modifier. * i386-opc.h (AVX512_4FMAP): New. (i386_cpu_flags): Add cpuavx512_4fmaps. (ImplicitQuadGroup): New. (i386_opcode_modifier): Add implicitquadgroup. * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2016-11-02 20:24:39 +01:00
2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
(cpu_noarch): Add noavx512_4fmaps.
(process_operands): Handle implicit quad group.
* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-01 17:45:57 +01:00
2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
Andrew Waterman <andrew@sifive.com>
Add support for RISC-V architecture.
* Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.
gas/arc: Don't rely on bfd list of cpu type for cpu selection In the ARC assembler, when a cpu type is specified using the .cpu directive, we rely on the bfd list of arc machine types in order to validate the cpu name passed in. This validation is only used in order to check that the cpu type passed to the .cpu directive matches any machine type selected earlier on the command line. Once that initial check has passed a full check is performed using the assemblers internal list of know cpu types. The problem is that the assembler knows about more cpu types than bfd, some cpu types known by the assembler are actually aliases for a base cpu type plus a specific set of assembler extensions. One such example is NPS400, though more could be added later. This commit removes the need for the assembler to use the bfd list of machine types for validation. Instead the error checking, to ensure that any value passed to a '.cpu' directive matches any earlier command line selection, is moved into the function arc_select_cpu. I have taken the opportunity to bundle the 4 separate static globals that describe the currently selected machine type into a single structure (called selected_cpu). gas/ChangeLog: * config/tc-arc.c (arc_target): Delete. (arc_target_name): Delete. (arc_features): Delete. (arc_mach_type): Delete. (mach_type_specified_p): Delete. (enum mach_selection_type): New enum. (mach_selection_mode): New static global. (selected_cpu): New static global. (arc_eflag): Rename to ... (arc_initial_eflag): ...this, and make const. (arc_select_cpu): Update comment, new parameter, check how previous machine type selection was made, and record this selection. Use selected_cpu instead of old globals. (arc_option): Remove use of arc_get_mach, instead use arc_select_cpu to validate machine type selection. Use selected_cpu over old globals. (allocate_tok): Use selected_cpu over old globals. (find_opcode_match): Likewise. (assemble_tokens): Likewise. (arc_cons_fix_new): Likewise. (arc_extinsn): Likewise. (arc_extcorereg): Likewise. (md_begin): Update default machine type selection, use selected_cpu over old globals. (md_parse_option): Update machine type selection option handling, use selected_cpu over old globals. * testsuite/gas/arc/nps400-0.s: Add .cpu directive. bfd/ChangeLog: * cpu-arc.c (arc_get_mach): Delete.
2016-07-08 19:01:00 +02:00
2016-10-27 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_target): Delete.
(arc_target_name): Delete.
(arc_features): Delete.
(arc_mach_type): Delete.
(mach_type_specified_p): Delete.
(enum mach_selection_type): New enum.
(mach_selection_mode): New static global.
(selected_cpu): New static global.
(arc_eflag): Rename to ...
(arc_initial_eflag): ...this, and make const.
(arc_select_cpu): Update comment, new parameter, check how
previous machine type selection was made, and record this
selection. Use selected_cpu instead of old globals.
(arc_option): Remove use of arc_get_mach, instead use
arc_select_cpu to validate machine type selection. Use
selected_cpu over old globals.
(allocate_tok): Use selected_cpu over old globals.
(find_opcode_match): Likewise.
(assemble_tokens): Likewise.
(arc_cons_fix_new): Likewise.
(arc_extinsn): Likewise.
(arc_extcorereg): Likewise.
(md_begin): Update default machine type selection, use
selected_cpu over old globals.
(md_parse_option): Update machine type selection option handling,
use selected_cpu over old globals.
* testsuite/gas/arc/nps400-0.s: Add .cpu directive.
2016-10-26 Alan Modra <amodra@gmail.com>
Revert 2016-10-06 Alan Modra <amodra@gmail.com>
* config/rl78-parse.y: Do use old %name-prefix syntax.
* config/rx-parse.y: Likewise.
2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Remove .pcommit.
* doc/c-i386.texi: Likewise.
* testsuite/gas/i386/i386.exp: Remove pcommit tests.
* testsuite/gas/i386/pcommit-intel.d: Removed.
* testsuite/gas/i386/pcommit.d: Likewise.
* testsuite/gas/i386/pcommit.s: Likewise.
* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.s: Likewise.
2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/20705
* testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
* testsuite/gas/i386/x86-64-opcode-bad.d: New file.
* testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.
2016-10-19 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (encode_arm_shift): Generate unpredictable warning
for register-shifted register instructions.
* testsuite/gas/arm/shift-bad-pc.d: New.
* testsuite/gas/arm/shift-bad-pc.l: New.
* testsuite/gas/arm/shift-bad-pc.s: New.
2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/arc/dis-inv.d: Fixed matching.
2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/arc/dis-inv.s: Test to validate patch.
* testsuite/arc/dis-inv.d: Likewise.
2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/shortlimm_a7.d: New file.
* testsuite/gas/arc/shortlimm_a7.s: Likewise.
* testsuite/gas/arc/shortlimm_hs.d: Likewise.
* testsuite/gas/arc/shortlimm_hs.s: Likewise.
Enhance objdump so that it will use .got, .plt and .plt.got section symbols when disassembling, and it will use dynamic relocs to interpret entries in the PLT and GOT. binutils * objdump.c (is_significant_symbol_name): New function. (remove_useless_symbols): Do not remove significanr symbols. (find_symbol_for_address): If an exact match for the specified address has not been found, try scanning the dynamic relocs to see if one of these matches the address. If so, use the symbol associated with the reloc. (objdump_print_addr_with_symbol): Do not print offsets to symbols with no value. (disassemble_section): Only use dynamic relocs if the user requested this. (disassemble_data): Always load dynamic relocs if they are available. ld * ld-aarch64/emit-relocs-515-be.d: Adjust output to match change in objdump. * ld-aarch64/emit-relocs-515.d: Likewise. * ld-aarch64/emit-relocs-516-be.d: Likewise. * ld-aarch64/emit-relocs-516.d: Likewise. * ld-aarch64/farcall-b-plt.d: Likewise. * ld-aarch64/farcall-bl-plt.d: Likewise. * ld-aarch64/gc-plt-relocs.d: Likewise. * ld-aarch64/tls-desc-ie.d: Likewise. * ld-aarch64/tls-tiny-desc.d: Likewise. * ld-aarch64/tls-tiny-gd.d: Likewise. * ld-aarch64/tls-tiny-ie.d: Likewise. * ld-arm/arm-app-abs32.d: Likewise. * ld-arm/arm-app.d: Likewise. * ld-arm/arm-lib-plt32.d: Likewise. * ld-arm/arm-lib.d: Likewise. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/cortex-a8-fix-b-plt.d: Likewise. * ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. * ld-arm/cortex-a8-fix-blx-plt.d: Likewise. * ld-arm/farcall-mixed-app-v5.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-app2.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/ifunc-10.dd: Likewise. * ld-arm/ifunc-14.dd: Likewise. * ld-arm/ifunc-15.dd: Likewise. * ld-arm/ifunc-3.dd: Likewise. * ld-arm/ifunc-4.dd: Likewise. * ld-arm/ifunc-9.dd: Likewise. * ld-arm/long-plt-format.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. * ld-arm/tls-lib-loc.d: Likewise. * ld-cris/dso-pltdis1.d: Likewise. * ld-cris/dso-pltdis2.d: Likewise. * ld-cris/dso12-pltdis.d: Likewise. * ld-elf/symbolic-func.r: Likewise. * ld-frv/fdpic-pie-1.d: Likewise. * ld-frv/fdpic-pie-2.d: Likewise. * ld-frv/fdpic-pie-6.d: Likewise. * ld-frv/fdpic-pie-7.d: Likewise. * ld-frv/fdpic-pie-8.d: Likewise. * ld-frv/fdpic-shared-1.d: Likewise. * ld-frv/fdpic-shared-2.d: Likewise. * ld-frv/fdpic-shared-3.d: Likewise. * ld-frv/fdpic-shared-4.d: Likewise. * ld-frv/fdpic-shared-5.d: Likewise. * ld-frv/fdpic-shared-6.d: Likewise. * ld-frv/fdpic-shared-7.d: Likewise. * ld-frv/fdpic-shared-8.d: Likewise. * ld-frv/fdpic-shared-local-2.d: Likewise. * ld-frv/fdpic-shared-local-8.d: Likewise. * ld-frv/fdpic-static-1.d: Likewise. * ld-frv/fdpic-static-2.d: Likewise. * ld-frv/fdpic-static-6.d: Likewise. * ld-frv/fdpic-static-7.d: Likewise. * ld-frv/fdpic-static-8.d: Likewise. * ld-frv/tls-dynamic-2.d: Likewise. * ld-frv/tls-initial-shared-2.d: Likewise. * ld-frv/tls-relax-shared-2.d: Likewise. * ld-frv/tls-shared-2.d: Likewise. * ld-i386/plt-nacl.pd: Likewise. * ld-i386/plt-pic-nacl.pd: Likewise. * ld-i386/plt-pic.pd: Likewise. * ld-i386/plt.pd: Likewise. * ld-i386/pr19636-1d-nacl.d: Likewise. * ld-i386/pr19636-1d.d: Likewise. * ld-i386/pr19636-2c-nacl.d: Likewise. * ld-i386/pr19636-2c.d: Likewise. * ld-ifunc/ifunc-21-x86-64.d: Likewise. * ld-ifunc/ifunc-22-x86-64.d: Likewise. * ld-ifunc/pr17154-i386.d: Likewise. * ld-ifunc/pr17154-x86-64.d: Likewise. * ld-m68k/plt1-68020.d: Likewise. * ld-m68k/plt1-cpu32.d: Likewise. * ld-m68k/plt1-isab.d: Likewise. * ld-m68k/plt1-isac.d: Likewise. * ld-metag/shared.d: Likewise. * ld-metag/stub_pic_app.d: Likewise. * ld-metag/stub_pic_shared.d: Likewise. * ld-metag/stub_shared.d: Likewise. * ld-s390/tlsbin_64.dd: Likewise. * ld-s390/tlspic_64.dd: Likewise. * ld-tic6x/shlib-1.dd: Likewise. * ld-tic6x/shlib-1b.dd: Likewise. * ld-tic6x/shlib-1rb.dd: Likewise. * ld-tic6x/shlib-app-1.dd: Likewise. * ld-tic6x/shlib-app-1b.dd: Likewise. * ld-tic6x/shlib-app-1r.dd: Likewise. * ld-tic6x/shlib-app-1rb.dd: Likewise. * ld-tic6x/shlib-noindex.dd: Likewise. * ld-vax-elf/export-class-data.dd: Likewise. * ld-vax-elf/plt-local-lib.dd: Likewise. * ld-vax-elf/plt-local.dd: Likewise. * ld-x86-64/bnd-ifunc-2.d: Likewise. * ld-x86-64/bnd-plt-1.d: Likewise. * ld-x86-64/gotpcrel1.dd: Likewise. * ld-x86-64/libno-plt-1b.dd: Likewise. * ld-x86-64/load1c-nacl.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d-nacl.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/mov1a.d: Likewise. * ld-x86-64/mov1b.d: Likewise. * ld-x86-64/mov1c.d: Likewise. * ld-x86-64/mov1d.d: Likewise. * ld-x86-64/mov2a.d: Likewise. * ld-x86-64/mov2b.d: Likewise. * ld-x86-64/mov2c.d: Likewise. * ld-x86-64/mov2d.d: Likewise. * ld-x86-64/mpx3.dd: Likewise. * ld-x86-64/mpx4.dd: Likewise. * ld-x86-64/no-plt-1a.dd: Likewise. * ld-x86-64/no-plt-1b.dd: Likewise. * ld-x86-64/no-plt-1c.dd: Likewise. * ld-x86-64/no-plt-1e.dd: Likewise. * ld-x86-64/no-plt-1f.dd: Likewise. * ld-x86-64/no-plt-1g.dd: Likewise. * ld-x86-64/plt-main-bnd.dd: Likewise. * ld-x86-64/plt-nacl.pd: Likewise. * ld-x86-64/plt.pd: Likewise. * ld-x86-64/pr18591.d: Likewise. * ld-x86-64/pr19609-1c.d: Likewise. * ld-x86-64/pr19609-1e.d: Likewise. * ld-x86-64/pr19609-1j.d: Likewise. * ld-x86-64/pr19609-1l.d: Likewise. * ld-x86-64/pr19609-1m.d: Likewise. * ld-x86-64/pr19609-5b.d: Likewise. * ld-x86-64/pr19609-5c.d: Likewise. * ld-x86-64/pr19609-5e.d: Likewise. * ld-x86-64/pr19609-6b.d: Likewise. * ld-x86-64/pr19609-7b.d: Likewise. * ld-x86-64/pr19609-7d.d: Likewise. * ld-x86-64/pr19636-2d.d: Likewise. * ld-x86-64/pr20093-1.d: Likewise. * ld-x86-64/pr20093-2.d: Likewise. * ld-x86-64/pr20253-1b.d: Likewise. * ld-x86-64/pr20253-1d.d: Likewise. * ld-x86-64/pr20253-1f.d: Likewise. * ld-x86-64/pr20253-1h.d: Likewise. * ld-x86-64/pr20253-1j.d: Likewise. * ld-x86-64/pr20253-1l.d: Likewise. * ld-x86-64/protected3.d: Likewise. * ld-x86-64/tlsbin.dd: Likewise. * ld-x86-64/tlsbin2.dd: Likewise. * ld-x86-64/tlsbindesc.dd: Likewise. * ld-x86-64/tlsdesc-nacl.pd: Likewise. * ld-x86-64/tlsdesc.dd: Likewise. * ld-x86-64/tlsdesc.pd: Likewise. * ld-x86-64/tlsgd10.dd: Likewise. * ld-x86-64/tlsgd5.dd: Likewise. * ld-x86-64/tlsgd6.dd: Likewise. * ld-x86-64/tlsgd8.dd: Likewise. * ld-x86-64/tlsgdesc.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/tlspic2.dd: Likewise. 2016-10-11 Nick Clifton <nickc@redhat.com> PR ld/20535 * emultempl/elf32.em (_search_needed): Add support for pseudo environment variables supported by ld.so. Namely $ORIGIN, $LIB and $PLATFORM. * configure.ac: Add getauxval to list AC_CHECK_FUNCS list. * config.in: Regenerate. * configure: Regenerate. 2016-10-11 Alan Modra <amodra@gmail.com> * ldlang.c (lang_do_assignments_1): Descend into output section statements that do not yet have bfd sections. Set symbol section temporarily for symbols defined in such statements to the undefined section. Don't error on data or reloc statements until final phase. * ldexp.c (exp_fold_tree_1 <etree_assign>): Handle bfd_und_section in expld.section. * testsuite/ld-mmix/bpo-10.d: Adjust. * testsuite/ld-mmix/bpo-11.d: Adjust. 2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * emulparams/elf64_s390.sh: Move binary start to 16M. * testsuite/ld-s390/tlsbin_64.dd: Adjust testcases accordingly. * testsuite/ld-s390/tlsbin_64.rd: Likewise. 2016-10-07 Alan Modra <amodra@gmail.com> * ldexp.c (MAX): Define. (exp_unop, exp_binop, exp_trinop): Alloc at least enough for etree_type.value. 2016-10-07 Alan Modra <amodra@gmail.com> * testsuite/lib/ld-lib.exp (is_generic_elf): New, extracted from.. * testsuite/ld-elf/elf.exp: ..here. 2016-10-06 Ludovic Court?s <ludo@gnu.org> * emulparams/elf32bmipn32-defs.sh: Shift quote of "x$EMULATION_NAME" to the left to work around <http://ftp.gnu.org/gnu/bash/bash-4.2-patches/bash42-007>. 2016-10-06 Alan Modra <amodra@gmail.com> * lexsup.c: Spell fall through comments consistently and add missing fall through comments. 2016-10-06 Alan Modra <amodra@gmail.com> * plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning by adding return. 2016-10-04 Alan Modra <amodra@gmail.com> * ld.texinfo (Expression Section): Update result of arithmetic expressions. * ldexp.c (arith_result_section): New function. (fold_binary): Use it. 2016-10-04 Alan Modra <amodra@gmail.com> * ldexp.c (exp_value_fold): New function. (exp_unop, exp_binop, exp_trinop): Use it. 2016-09-30 Alan Modra <amodra@gmail.com> * scripttempl/v850.sc: Don't reference __ctbp, __ep, __gp when not relocating. * scripttempl/v850_rh850.sc: Likewise. 2016-09-30 Alan Modra <amodra@gmail.com> PR ld/20528 * testsuite/ld-elf/pr20528a.d: xfail generic elf targets. Allow multiple .text sections for hppa-linux. * testsuite/ld-elf/pr20528b.d: Likewise. 2016-09-30 Alan Modra <amodra@gmail.com> * ldmain.c (default_bfd_error_handler): New function pointer. (ld_bfd_error_handler): New function. (main): Arrange to call it on bfd errors/warnings. (ld_bfd_assert_handler): Enable tail call. 2016-09-30 Alan Modra <amodra@gmail.com> * ldlang.c (ignore_bfd_errors): Update params. 2016-09-29 H.J. Lu <hongjiu.lu@intel.com> PR ld/20528 * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Don't merge 2 sections with different SHF_EXCLUDE. * testsuite/ld-elf/pr20528a.d: New file. * testsuite/ld-elf/pr20528a.s: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr20528b.s: Likewise. 2016-09-28 Christophe Lyon <christophe.lyon@linaro.org> PR ld/20608 * testsuite/ld-arm/arm-elf.exp: Handle new testcase. * testsuite/ld-arm/farcall-mixed-app2.d: New file. * testsuite/ld-arm/farcall-mixed-app2.r: Likewise. * testsuite/ld-arm/farcall-mixed-app2.s: Likewise. * testsuite/ld-arm/farcall-mixed-app2.sym: Likewise. 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com> * Makefile.in: Regenerate. * configure: Likewise. 2016-09-26 Alan Modra <amodra@gmail.com> * testsuite/ld-powerpc/attr-gnu-4-4.s: Delete. * testsuite/ld-powerpc/attr-gnu-4-14.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-24.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-34.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-41.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning. * testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output. * testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise. * testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests. 2016-09-23 Akihiko Odaki <akihiko.odaki.4i@stu.hosei.ac.jp> PR ld/20595 * testsuite/ld-arm/unwind-4.d: Add -q option to linker command line and -r option to objdump command line. Match emitted relocs to make sure that superflous relocs are not generated. 2016-09-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * emulparams/elf64_s390.sh: Change TEXT_START_ADDR to 256MB. * testsuite/ld-s390/tlsbin_64.dd: Adjust testcase accordingly. * testsuite/ld-s390/tlsbin_64.rd: Likewise. 2016-09-22 Nick Clifton <nickc@redhat.com> * emultempl/elf32.em (_try_needed): In verbose mode, report failed attempts to find a needed library. 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> * testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after "," in addresses. * testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-301.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310.d: Likewise. * testsuite/ld-aarch64/emit-relocs-313.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516.d: Likewise. * testsuite/ld-aarch64/emit-relocs-531.d: Likewise. * testsuite/ld-aarch64/emit-relocs-532.d: Likewise. * testsuite/ld-aarch64/emit-relocs-533.d: Likewise. * testsuite/ld-aarch64/emit-relocs-534.d: Likewise. * testsuite/ld-aarch64/emit-relocs-535.d: Likewise. * testsuite/ld-aarch64/emit-relocs-536.d: Likewise. * testsuite/ld-aarch64/emit-relocs-537.d: Likewise. * testsuite/ld-aarch64/emit-relocs-538.d: Likewise. * testsuite/ld-aarch64/erratum835769.d: Likewise. * testsuite/ld-aarch64/erratum843419.d: Likewise. * testsuite/ld-aarch64/farcall-b-plt.d: Likewise. * testsuite/ld-aarch64/farcall-bl-plt.d: Likewise. * testsuite/ld-aarch64/gc-plt-relocs.d: Likewise. * testsuite/ld-aarch64/ifunc-21.d: Likewise. * testsuite/ld-aarch64/ifunc-7c.d: Likewise. * testsuite/ld-aarch64/tls-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-large-desc-be.d: Likewise. * testsuite/ld-aarch64/tls-large-desc.d: Likewise. * testsuite/ld-aarch64/tls-large-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-large-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-all.d: Likewise. * testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-tiny-desc.d: Likewise. * testsuite/ld-aarch64/tls-tiny-gd.d: Likewise. gas * gas/arm/tls.d: Adjust output to match change in objdump.
2016-10-11 14:50:10 +02:00
2016-10-11 Nick Clifton <nickc@redhat.com>
* gas/arm/tls.d: Adjust output to match change in objdump.
2016-10-11 Jiong Wang <jiong.wang@arm.com>
PR target/20666
* testsuite/gas/aarch64/alias-2.d: Update expected results.
2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.
* testsuite/gas/cfi/cfi-common-2.d: Likewise.
* testsuite/gas/cfi/cfi-common-3.d: Likewise.
* testsuite/gas/cfi/cfi-common-4.d: Likewise.
* testsuite/gas/cfi/cfi-common-5.d: Likewise.
* testsuite/gas/cfi/cfi-common-7.d: Likewise.
* testsuite/gas/cfi/cfi-common-8.d: Likewise.
* testsuite/gas/cfi/cfi-common-9.d: Likewise.
* testsuite/gas/cfi/cfi-mips-1.d: Likewise.
2016-10-08 Alan Modra <amodra@gmail.com>
* Makefile.am (EXTRA_as_new_SOURCES): Add config/rl78-parse.y and
config/rx-parse.y. Move config/bfin-parse.y.
(bfin-parse.@OBJEXT@, rl78-parse.@OBJEXT@, rx-parse.@OBJEXT@): Delete.
($(srcdir)/config/rl78-defs.h): New rule.
* Makefile.in: Regenerate.
2016-10-07 Jiong Wang <jiong.wang@arm.com>
PR target/20667
* testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions using
SYS_Rt reg.
* testsuite/gas/aarch64/sys-rt-reg.d: New testcase.
2016-10-06 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: New file.
* testsuite/gas/arc/leave_enter.s: Likewise.
* testsuite/gas/arc/regnames.d: Likewise.
* testsuite/gas/arc/regnames.s: Likewise.
* config/tc-arc.c (arc_parse_name): Don't match reg names against
confirmed symbol names.
2016-10-06 Alan Modra <amodra@gmail.com>
* app.c (do_scrub_chars): Move fall through comment.
* expr.c (operand): Likewise.
2016-10-06 Matthew Fortune <matthew.fortune@imgtec.com>
PR gas/20648
* dw2gencfi.c (dot_cfi_sections): Refine the check for
inconsistent .cfi_sections to only consider compact vs non
compact forms.
* testsuite/gas/cfi/cfi-common-9.d: New file.
* testsuite/gas/cfi/cfi-common-9.s: New file.
* testsuite/gas/cfi/cfi.exp: Run new test.
-Wimplicit-fallthrough warning fixes Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
2016-10-05 09:47:02 +02:00
2016-10-06 Alan Modra <amodra@gmail.com>
* app.c: Add missing fall through comments.
* dw2gencfi.c: Likewise.
* expr.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/obj-elf.c: Likewise.
* config/tc-i386.c: Likewise.
* depend.c: Spell fall through comments consistently.
* config/tc-arm.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z8k.c: Likewise.
2016-10-06 Alan Modra <amodra@gmail.com>
* as.h (as_assert): Add ATTRIBUTE_NORETURN.
2016-10-06 Alan Modra <amodra@gmail.com>
* config/tc-arc.c (find_opcode_match): Add missing break.
* config/tc-i960.c (get_cdisp): Likewise.
* config/tc-metag.c (parse_swap, md_apply_fix): Likewise.
* config/tc-mt.c (md_parse_option): Likewise.
* config/tc-nds32.c (nds32_apply_fix): Likewise.
* config/tc-hppa.c (pa_ip): Assert rather than testing last
condition of multiple if statements.
* config/tc-s390.c (s390_exp_compare): Return 0 on error.
* config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break
out of case rather than falling into next case. Formatting.
2016-10-06 Alan Modra <amodra@gmail.com>
* config/rl78-parse.y: Don't use deprecated %name-prefix.
* config/rx-parse.y: Likewise.
2016-09-29 Jiong Wang <jiong.wang@arm.com>
PR target/20553
* testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
testcases for H and S variants. New low index testcases for D variant.
* testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
2016-09-29 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
2016-09-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of
cnt_argp to concat.
2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
* Makefile.in: Regenerate.
* configure: Likewise.
* doc/Makefile.in: Likewise.
PowerPC .gnu.attributes This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs, makes the assembler warn about undefined tag values, and removes similar warnings from the linker. I think it is better to not warn in the linker about undefined tag values as future extensions to the tags then won't result in likely bogus warnings. This is consistent with the fact that an older linker won't warn on an entirely new tag. include/ * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment. bfd/ * elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare. * elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function. (ppc_elf_merge_obj_attributes): Use it. Don't copy first file attributes, merge them. Don't warn about undefined tag bits, or copy unknown values to output. * elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call _bfd_elf_ppc_merge_fp_attributes. binutils/ * readelf.c (display_power_gnu_attribute): Catch truncated section for all powerpc attributes. Display long double ABI. Don't capitalize words, except for names. Show known bits of tag values when some unknown bits are present. Whitespace fixes. gas/ * config/tc-ppc.c (ppc_elf_gnu_attribute): New function. (md_pseudo_table <ELF>): Handle "gnu_attribute". ld/ * testsuite/ld-powerpc/attr-gnu-4-4.s: Delete. * testsuite/ld-powerpc/attr-gnu-4-14.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-24.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-34.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-41.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning. * testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output. * testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise. * testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
2016-09-26 10:34:57 +02:00
2016-09-26 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
(md_pseudo_table <ELF>): Handle "gnu_attribute".
2016-09-22 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (v7m_psrs): Remove BASEPRI_MASK MRS/MSR special
register and redundant basepri_max.
[AArch64] Print spaces after commas in addresses I got an off-list request to make the AArch64 disassembler print spaces after commas in addresses. This patch does that. The same code is used to print operands in "did you mean" errors, so to keep things consistent, the patch also prints spaces between operands in those messages. opcodes/ * aarch64-opc.c (print_immediate_offset_address): Print spaces after commas in addresses. (aarch64_print_operand): Likewise. gas/ * config/tc-aarch64.c (print_operands): Print spaces between operands. * testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after "," in addresses. * testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise. * testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise. * testsuite/gas/aarch64/ldst-reg-pair.d: Likewise. * testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise. * testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise. * testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. * testsuite/gas/aarch64/symbol.d: Likewise. * testsuite/gas/aarch64/system.d: Likewise. * testsuite/gas/aarch64/tls-desc.d: Likewise. * testsuite/gas/aarch64/sve-invalid.l: Expect spaces after "," in suggested alternatives. * testsuite/gas/aarch64/verbose-error.l: Likewise. ld/ * testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after "," in addresses. * testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-301.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310.d: Likewise. * testsuite/ld-aarch64/emit-relocs-313.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516.d: Likewise. * testsuite/ld-aarch64/emit-relocs-531.d: Likewise. * testsuite/ld-aarch64/emit-relocs-532.d: Likewise. * testsuite/ld-aarch64/emit-relocs-533.d: Likewise. * testsuite/ld-aarch64/emit-relocs-534.d: Likewise. * testsuite/ld-aarch64/emit-relocs-535.d: Likewise. * testsuite/ld-aarch64/emit-relocs-536.d: Likewise. * testsuite/ld-aarch64/emit-relocs-537.d: Likewise. * testsuite/ld-aarch64/emit-relocs-538.d: Likewise. * testsuite/ld-aarch64/erratum835769.d: Likewise. * testsuite/ld-aarch64/erratum843419.d: Likewise. * testsuite/ld-aarch64/farcall-b-plt.d: Likewise. * testsuite/ld-aarch64/farcall-bl-plt.d: Likewise. * testsuite/ld-aarch64/gc-plt-relocs.d: Likewise. * testsuite/ld-aarch64/ifunc-21.d: Likewise. * testsuite/ld-aarch64/ifunc-7c.d: Likewise. * testsuite/ld-aarch64/tls-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-large-desc-be.d: Likewise. * testsuite/ld-aarch64/tls-large-desc.d: Likewise. * testsuite/ld-aarch64/tls-large-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-large-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-all.d: Likewise. * testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-tiny-desc.d: Likewise. * testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.
2016-09-21 18:11:52 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (print_operands): Print spaces between
operands.
* testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
in addresses.
* testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
* testsuite/gas/aarch64/symbol.d: Likewise.
* testsuite/gas/aarch64/system.d: Likewise.
* testsuite/gas/aarch64/tls-desc.d: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
in suggested alternatives.
* testsuite/gas/aarch64/verbose-error.l: Likewise.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Use "must be"
rather than "should be" or "expected to be" in error messages.
(parse_operands): Likewise.
* testsuite/gas/aarch64/diagnostic.l: Likewise.
* testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Likewise.
* testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
[AArch64] Add SVE condition codes SVE defines new names for existing NZCV conditions, to reflect the result of instructions like PTEST. This patch adds support for these names. The patch also adds comments to the disassembly output to show the alternative names of a condition code. For example: cinv x0, x1, cc becomes: cinv x0, x1, cc // cc = lo, ul, last and: b.cc f0 <...> becomes: b.cc f0 <...> // b.lo, b.ul, b.last Doing this for the SVE names follows the practice recommended by the SVE specification and is definitely useful when reading SVE code. If the feeling is that it's too distracting elsewhere, we could add an option to turn it off. include/ * opcode/aarch64.h (aarch64_cond): Bump array size to 4. opcodes/ * aarch64-dis.c (remove_dot_suffix): New function, split out from... (print_mnemonic_name): ...here. (print_comment): New function. (print_aarch64_insn): Call it. * aarch64-opc.c (aarch64_conds): Add SVE names. (aarch64_print_operand): Print alternative condition names in a comment. gas/ * config/tc-aarch64.c (opcode_lookup): Search for the end of a condition name, rather than assuming that it will have exactly 2 characters. (parse_operands): Likewise. * testsuite/gas/aarch64/alias.d: Add new condition-code comments to the expected output. * testsuite/gas/aarch64/beq_1.d: Likewise. * testsuite/gas/aarch64/float-fp16.d: Likewise. * testsuite/gas/aarch64/int-insns.d: Likewise. * testsuite/gas/aarch64/no-aliases.d: Likewise. * testsuite/gas/aarch64/programmer-friendly.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s: New test. ld/ * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. * testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21 18:09:59 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
2016-09-21 18:08:58 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for
invalid uses of MUL VL and MUL in base AArch64 instructions.
* testsuite/gas/aarch64/sve-add.s, testsuite/gas/aarch64/sve-add.d,
testsuite/gas/aarch64/sve-dup.s, testsuite/gas/aarch64/sve-dup.d,
testsuite/gas/aarch64/sve-invalid.s,
testsuite/gas/aarch64/sve-invalid.d,
testsuite/gas/aarch64/sve-invalid.l,
testsuite/gas/aarch64/sve-reg-diagnostic.s,
testsuite/gas/aarch64/sve-reg-diagnostic.d,
testsuite/gas/aarch64/sve-reg-diagnostic.l,
testsuite/gas/aarch64/sve.s, testsuite/gas/aarch64/sve.d: New tests.
[AArch64][SVE 31/32] Add SVE instructions This patch adds the SVE instruction definitions and associated OP_* enum values. include/ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE.
2016-09-21 17:58:48 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
[AArch64][SVE 28/32] Add SVE FP immediate operands This patch adds support for the new SVE floating-point immediate operands. One operand uses the same 8-bit encoding as base AArch64, but in a different position. The others use a single bit to select between two values. One of the single-bit operands is a choice between 0 and 1, where 0 is not a valid 8-bit encoding. I think the cleanest way of handling these single-bit immediates is therefore to use the IEEE float encoding itself as the immediate value and select between the two possible values when encoding and decoding. As described in the covering note for the patch that added F_STRICT, we get better error messages by accepting unsuffixed vector registers and leaving the qualifier matching code to report an error. This means that we carry on parsing the other operands, and so can try to parse FP immediates for invalid instructions like: fcpy z0, #2.5 In this case there is no suffix to tell us whether the immediate should be treated as single or double precision. Again, we get better error messages by picking one (arbitrary) immediate size and reporting an error for the missing suffix later. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP immediate operands. * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. * aarch64-opc.c (fields): Add corresponding entry. (operand_general_constraint_met_p): Handle the new SVE FP immediate operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) (ins_sve_float_zero_one): New inserters. * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. (aarch64_ins_sve_float_half_two): Likewise. (aarch64_ins_sve_float_zero_one): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) (ext_sve_float_zero_one): New extractors. * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. (aarch64_ext_sve_float_half_two): Likewise. (aarch64_ext_sve_float_zero_one): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (double_precision_operand_p): New function. (parse_operands): Use it to calculate the dp_p input to parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
2016-09-21 17:57:22 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (double_precision_operand_p): New function.
(parse_operands): Use it to calculate the dp_p input to
parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
[AArch64][SVE 27/32] Add SVE integer immediate operands This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical immediate <limm> is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands.
2016-09-21 17:56:57 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes This patch adds support for addresses of the form: [<base>, #<offset>, MUL VL] This involves adding a new AARCH64_MOD_MUL_VL modifier, which is why I split it out from the other addressing modes. For LD2, LD3 and LD4, the offset must be a multiple of the structure size, so for LD3 the possible values are 0, 3, 6, .... The patch therefore extends value_aligned_p to handle non-power-of-2 alignments. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL operands. * aarch64-opc.c (aarch64_operand_modifiers): Initialize the AARCH64_MOD_MUL_VL entry. (value_aligned_p): Cope with non-power-of-two alignments. (operand_general_constraint_met_p): Handle the new MUL VL addresses. (print_immediate_offset_address): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) (ins_sve_addr_ri_s9xvl): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. (aarch64_ins_sve_addr_ri_s6xvl): Likewise. (aarch64_ins_sve_addr_ri_s9xvl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) (ext_sve_addr_ri_s9xvl): New extractors. * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. (aarch64_ext_sve_addr_ri_s4xvl): Likewise. (aarch64_ext_sve_addr_ri_s6xvl): Likewise. (aarch64_ext_sve_addr_ri_s9xvl): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New parse_shift_modes. (parse_shift): Handle SHIFTED_MUL_VL. (parse_address_main): Add an imm_shift_mode parameter. (parse_address, parse_sve_address): Update accordingly. (parse_operands): Handle MUL VL addressing modes.
2016-09-21 17:56:15 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
[AArch64][SVE 25/32] Add support for SVE addressing modes This patch adds most of the new SVE addressing modes and associated operands. A follow-on patch adds MUL VL, since handling it separately makes the changes easier to read. The patch also introduces a new "operand-dependent data" field to the operand flags, based closely on the existing one for opcode flags. For SVE this new field needs only 2 bits, but it could be widened in future if necessary. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE address operands. * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) (FLD_SVE_xs_22): New aarch64_field_kinds. (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. (get_operand_specific_data): New function. * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14 and FLD_SVE_xs_22. (operand_general_constraint_met_p): Handle the new SVE address operands. (sve_reg): New array. (get_addr_sve_reg_name): New function. (aarch64_print_operand): Handle the new SVE address operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. (aarch64_ins_sve_addr_rr_lsl): Likewise. (aarch64_ins_sve_addr_rz_xtw): Likewise. (aarch64_ins_sve_addr_zi_u5): Likewise. (aarch64_ins_sve_addr_zz): Likewise. (aarch64_ins_sve_addr_zz_lsl): Likewise. (aarch64_ins_sve_addr_zz_sxtw): Likewise. (aarch64_ins_sve_addr_zz_uxtw): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. (aarch64_ext_sve_addr_ri_u6): Likewise. (aarch64_ext_sve_addr_rr_lsl): Likewise. (aarch64_ext_sve_addr_rz_xtw): Likewise. (aarch64_ext_sve_addr_zi_u5): Likewise. (aarch64_ext_sve_addr_zz): Likewise. (aarch64_ext_sve_addr_zz_lsl): Likewise. (aarch64_ext_sve_addr_zz_sxtw): Likewise. (aarch64_ext_sve_addr_zz_uxtw): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New register types. (get_reg_expected_msg): Handle them. (aarch64_addr_reg_parse): New function, split out from aarch64_reg_parse_32_64. Handle Z registers too. (aarch64_reg_parse_32_64): Call it. (parse_address_main): Add base_qualifier, offset_qualifier, base_type and offset_type parameters. Handle SVE base and offset registers. (parse_address): Update call to parse_address_main. (parse_sve_address): New function. (parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.
2016-09-21 17:55:22 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
[AArch64][SVE 23/32] Add SVE pattern and prfop operands The SVE instructions have two enumerated operands: one to select a vector pattern and another to select a prefetch operation. The latter is a cut-down version of the base AArch64 prefetch operation. Both types of operand can also be specified as raw enum values such as #31. Reserved values can only be specified this way. If it hadn't been for the pattern operand, I would have been tempted to use the existing parsing for prefetch operations and add extra checks for SVE. However, since the patterns needed new enum parsing code anyway, it seeemed cleaner to reuse it for the prefetches too. Because of the small number of enum values, I don't think we'd gain anything by using hash tables. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. (AARCH64_OPND_SVE_PRFOP): Likewise. (aarch64_sve_pattern_array): Declare. (aarch64_sve_prfop_array): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. (FLD_SVE_prfop): Likewise. * aarch64-opc.c: Include libiberty.h. (aarch64_sve_pattern_array): New variable. (aarch64_sve_prfop_array): Likewise. (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_enum_string): New function. (po_enum_or_fail): New macro. (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
2016-09-21 17:54:53 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_enum_string): New function.
(po_enum_or_fail): New macro.
(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
(parse_vector_type_for_operand): Assert that the skipped character
is a '.'.
(parse_predication_for_operand): New function.
(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
(vectype_to_qualifier): Handle NT_zero and NT_merge.
[AArch64][SVE 21/32] Add Zn and Pn registers This patch adds the Zn and Pn registers, and associated fields and operands. include/ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries.
2016-09-21 17:53:54 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
[AArch64][SVE 13/32] Add an F_STRICT flag SVE predicate operands can appear in three forms: 1. unsuffixed: "Pn" 2. with a predication type: "Pn/[ZM]" 3. with a size suffix: "Pn.[BHSD]" No variation is allowed: unsuffixed operands cannot have a (redundant) suffix, and the suffixes can never be dropped. Unsuffixed Pn are used in LDR and STR, but they are also used for Pg operands in cases where the result is scalar and where there is therefore no choice to be made between "merging" and "zeroing". This means that some Pg operands have suffixes and others don't. It would be possible to use context-sensitive parsing to handle this difference. The tc-aarch64.c code would then raise an error if the wrong kind of suffix is used for a particular instruction. However, we get much more user-friendly error messages if we parse all three forms for all SVE instructions and record the suffix as a qualifier. The normal qualifier matching code can then report cases where the wrong kind of suffix is used. This is a slight extension of existing usage, which really only checks for the wrong choice of suffix within a particular kind of suffix. The only catch is a that a "NIL" entry in the qualifier list specifically means "no suffix should be present" (case 1 above). NIL isn't a wildcard here. It also means that an instruction that requires all-NIL qualifiers can fail to match (because a suffix was supplied when it shouldn't have been); this requires a slight change to find_best_match. This patch adds an F_STRICT flag to select this behaviour. The flag will be set for all SVE instructions. The behaviour for other instructions doesn't change. include/ * opcode/aarch64.h (F_STRICT): New flag. opcodes/ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. gas/ * config/tc-aarch64.c (find_best_match): Simplify, allowing an instruction with all-NIL qualifiers to fail to match.
2016-09-21 17:51:00 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.
[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main In the review of the original version of this series, Richard didn't like the use of boolean parameters to parse_address_main. I think we can just get rid of them and leave the callers to check the addressing modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this for relocation operators (i.e. it used parse_address_reloc and then rejected relocations). The callers are already set up to reject invalid register post-indexed addressing, so we can simply remove the accept_reg_post_index parameter without adding any more checks. This again creates a corner case where: .equ x2, 1 ldr w0, [x1], x2 was previously an acceptable way of writing "ldr w0, [x1], #1" but is now rejected. Removing the "reloc" parameter means that two cases need to check explicitly for relocation operators. ADDR_SIMM9_2 appers to be unused. I'll send a separate patch to remove it. This patch makes parse_address temporarily equivalent to parse_address_main, but later patches in the series will need to keep the distinction. gas/ * config/tc-aarch64.c (parse_address_main): Remove reloc and accept_reg_post_index parameters. Parse relocations and register post indexes unconditionally. (parse_address): Remove accept_reg_post_index parameter. Update call to parse_address_main. (parse_address_reloc): Delete. (parse_operands): Call parse_address instead of parse_address_main. Update existing callers of parse_address and make them check inst.reloc.type where appropriate. * testsuite/gas/aarch64/diagnostic.s: Add tests for relocations in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses. Also test for invalid uses of post-index register addressing. * testsuite/gas/aarch64/diagnostic.l: Update accordingly.
2016-09-21 17:49:31 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface aarch64_reg_parse_32_64 is currently used to parse address registers, among other things. It returns two bits of information about the register: whether it's W rather than X, and whether it's a zero register. SVE adds addressing modes in which the base or offset can be a vector register instead of a scalar, so a choice between W and X is no longer enough. It's more convenient to pass the type of register around as a qualifier instead. As it happens, two callers of aarch64_reg_parse_32_64 already wanted the information in the form of a qualifier, so the change feels pretty natural even without SVE. Also, the function took two parameters to control whether {W}SP and (W|X)ZR should be accepted. We tend to get slightly better error messages by accepting them regardless and getting the caller to do the check, rather than potentially treating "xzr", "sp" etc. as constants. This is easier to do if the function returns the reg_entry rather than just the register number. This does create a corner case where: .equ sp, 1 ldr w0, [x0, sp] was previously an acceptable way of writing "ldr w0, [x0, #1]", but I don't think it's important to continue supporting that. We already rejected things like: .equ sp, 1 add x0, x1, sp To ensure these new error messages "win" when matching against several candidate instruction entries, we need to use the same address-parsing code for all addresses, including ADDR_SIMPLE and SIMD_ADDR_SIMPLE. The next patch also relies on this. Finally, aarcch64_check_reg_type was written in a pretty conservative way. It should always be equivalent to a single bit test. gas/ * config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register types. (get_reg_expected_msg): Handle them and REG_TYPE_R64_SP. (aarch64_check_reg_type): Simplify. (aarch64_reg_parse_32_64): Return the reg_entry instead of the register number. Return the type as a qualifier rather than an "isreg32" boolean. Remove reject_sp, reject_rz and isregzero parameters. (parse_shifter_operand): Update call to aarch64_parse_32_64_reg. Use get_reg_expected_msg. (parse_address_main): Likewise. Use aarch64_check_reg_type. (po_int_reg_or_fail): Replace reject_sp and reject_rz parameters with a reg_type parameter. Update call to aarch64_parse_32_64_reg. Use aarch64_check_reg_type to test the result. (parse_operands): Update after the above changes. Parse ADDR_SIMPLE addresses normally before enforcing the syntax restrictions. * testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index zero register and for a stack pointer index. * testsuite/gas/aarch64/diagnostic.l: Update accordingly. Also update existing diagnostic messages after the above changes. * testsuite/gas/aarch64/illegal-lse.l: Update the error message for 32-bit register bases.
2016-09-21 17:49:24 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number. Return the type as a qualifier rather than an
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise. Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
(parse_operands): Check the range of 8-bit FP immediates here instead.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
low-severity error for registers.
(parse_operands): Report an invalid floating point constant for
if parsing an FPIMM8 fails, and if no better error has been
recorded.
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
to FMOV.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
to...
(can_convert_double_to_float): ...this. Accept any double-precision
value that converts to single precision without loss of precision.
(parse_aarch64_imm_float): Update accordingly.
[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V To remove parsing ambiguities and to avoid register names being accidentally added to the symbol table, the immediate parsing routines reject things like: .equ x0, 0 add v0.4s, v0.4s, x0 An explicit '#' must be used instead: .equ x0, 0 add v0.4s, v0.4s, #x0 Of course, it wasn't possible to predict what other register names might be added in future, so this behaviour was restricted to the register names that were defined at the time. For backwards compatibility, we should continue to allow things like: .equ p0, 0 add v0.4s, v0.4s, p0 even though p0 is now an SVE register. However, it seems reasonable to extend the x0 behaviour above to SVE registers when parsing SVE instructions, especially since none of the SVE immediate formats are relocatable. Doing so removes the same parsing ambiguity for SVE instructions as the x0 behaviour removes for base AArch64 instructions. As a prerequisite, we then need to be able to tell the parsing routines which registers to reject. This patch changes the interface to make that possible, although the set of rejected registers doesn't change at this stage. gas/ * config/tc-aarch64.c (parse_immediate_expression): Add a reg_type parameter. (parse_constant_immediate): Likewise, and update calls. (parse_aarch64_imm_float): Likewise. (parse_big_immediate): Likewise. (po_imm_nc_or_fail): Update accordingly, passing down a new imm_reg_type variable. (po_imm_of_fail): Likewise. (parse_operands): Likewise.
2016-09-21 17:48:50 +02:00
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
(parse_vector_type_for_operand): ...this.
(parse_typed_reg): Update accordingly.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (neon_type_el): Rename to...
(vector_type_el): ...this.
(parse_neon_type_for_operand): Update accordingly.
(parse_typed_reg): Likewise.
(aarch64_reg_parse): Likewise.
(vectype_to_qualifier): Likewise.
(parse_operands): Likewise.
(eq_neon_type_el): Likewise. Rename to...
(eq_vector_type_el): ...this.
(parse_neon_reg_list): Update accordingly.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (neon_el_type: Rename to...
(vector_el_type): ...this.
(neon_type_el): Update accordingly.
(parse_neon_type_for_operand): Likewise.
(vectype_to_qualifier): Likewise.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_neon_operand_type): Delete.
(parse_typed_reg): Call parse_neon_type_for_operand directly.
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
2016-09-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v9 only in ELF targets to avoid spurious failures in
sparc-aout and sparc-coff targets.
2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
<copy, paste.>: Update tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Print the instruction arguments
in "architecture mismatch" error messages.
gas: detect DCTI couples in sparc Before SPARC V9 the effect of having a delayed branch instruction in the delay slot of a conditional delayed branch was undefined. In SPARC V9 DCTI couples are well defined. However, starting with the UltraSPARC Architecture 2005, DCTI couples (of all kind) are deprecated and should not be used, as they may be slow or behave differently to what the programmer expects. This patch adds a new command line option --dcti-couples-detect to `as', disabled by default, that makes the assembler to warn the user if an unpredictable DCTI couple is found. Tests and documentation are included. gas/ChangeLog: 2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (md_assemble): Detect and warning on unpredictable DCTI couples in certain arches. (dcti_couples_detect): New global. (md_longopts): Add command line option -dcti-couples-detect. (md_show_usage): Document -dcti-couples-detect. (md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests. * testsuite/gas/sparc/dcti-couples.s: New file. * testsuite/gas/sparc/dcti-couples-v9c.d: Likewise. * testsuite/gas/sparc/dcti-couples-v8.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9c.l: Likewise. * testsuite/gas/sparc/dcti-couples-v8.l: Likewise. * doc/as.texinfo (Overview): Document --dcti-couples-detect. * doc/c-sparc.texi (Sparc-Opts): Likewise.
2016-09-14 16:10:49 +02:00
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (md_assemble): Detect and warning on
unpredictable DCTI couples in certain arches.
(dcti_couples_detect): New global.
(md_longopts): Add command line option -dcti-couples-detect.
(md_show_usage): Document -dcti-couples-detect.
(md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests.
* testsuite/gas/sparc/dcti-couples.s: New file.
* testsuite/gas/sparc/dcti-couples-v9c.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9c.l: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.l: Likewise.
* doc/as.texinfo (Overview): Document --dcti-couples-detect.
* doc/c-sparc.texi (Sparc-Opts): Likewise.
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/tls-relocs2.d: New file.
* testsuite/gas/arc/tls-relocs2.s: Likewise.
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
is used.
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Support alternate arch
strings.
* doc/as.texinfo: Document new arch strings.
* doc/c-s390.texi: Likewise.
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c: Set all facitily bits by default
2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Adjust testcase.
2016-09-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_target_format): Allow PROCESSOR_IAMCU
for Intel MCU.
2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
(set_cpu_arch): Updated.
(md_parse_option): Likewise.
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
iamcu-inval-2 and iamcu-inval-3.
* testsuite/gas/i386/iamcu-4.d: New file.
* testsuite/gas/i386/iamcu-4.s: Likewise.
* testsuite/gas/i386/iamcu-5.d: Likewise.
* testsuite/gas/i386/iamcu-5.s: Likewise.
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
ARMv8-A CPUs except xgene1.
2016-08-31 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
ppc_cpu rather than calling ppc_mach to determine VLE mode.
(ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/crypto.d: Rename invalid opcode camellia_fi
to camellia_fl.
* testsuite/gas/sparc/crypto.s: Likewise.
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (v7m_psrs): Remove msp_s, MSP_S, psp_s and PSP_S
special registers.
* testsuite/gas/arm/archv8m-cmse-msr.s: Remove test for above special
registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .ptwrite.
* doc/c-i386.texi: Document ptwrite and .ptwrite.
* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
x86-64-ptwrite and x86-64-ptwrite-intel.
* testsuite/gas/i386/ptwrite-intel.d: New file.
* testsuite/gas/i386/ptwrite.d: Likewise.
* testsuite/gas/i386/ptwrite.s: Likewise.
* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
2016-08-19 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (do_co_reg2c): Added constraint.
* testsuite/gas/arm/dest-unpredictable.s: New.
* testsuite/gas/arm/dest-unpredictable.l: New.
* testsuite/gas/arm/dest-unpredictable.d: New.
Place .shstrtab section after .symtab and .strtab, thus restoring monotonically increasing section offsets. bfd * elf.c (assign_section_numbers): Assign number for the .shstrtab section after the symbol table and string table sections. binutils * testsuite/binutils-all/readelf.s: Adjust expected ordering of sections. * testsuite/binutils-all/readelf.s-64: Likewise. gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected ordering of sections. * testsuite/gas/i386/x86-64-unwind.d: Likewise. * testsuite/gas/ia64/alias-ilp32.d: Likewise. * testsuite/gas/ia64/alias.d: Likewise. * testsuite/gas/ia64/group-1.d: Likewise. * testsuite/gas/ia64/group-2.d: Likewise. * testsuite/gas/ia64/secname-ilp32.d: Likewise. * testsuite/gas/ia64/secname.d: Likewise. * testsuite/gas/ia64/unwind-ilp32.d: Likewise. * testsuite/gas/ia64/unwind.d: Likewise. * testsuite/gas/ia64/xdata-ilp32.d: Likewise. * testsuite/gas/ia64/xdata.d: Likewise. * testsuite/gas/mmix/bspec-1.d: Likewise. * testsuite/gas/mmix/bspec-2.d: Likewise. * testsuite/gas/mmix/byte-1.d: Likewise. * testsuite/gas/mmix/loc-1.d: Likewise. * testsuite/gas/mmix/loc-2.d: Likewise. * testsuite/gas/mmix/loc-3.d: Likewise. * testsuite/gas/mmix/loc-4.d: Likewise. * testsuite/gas/mmix/loc-5.d: Likewise. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. ld * testsuite/ld-alpha/tlsbin.rd: Adjust expected ordering of sections. * testsuite/ld-alpha/tlsbinr.rd: Likewise. * testsuite/ld-alpha/tlspic.rd: Likewise. * testsuite/ld-cris/libdso-2.d: Likewise. * testsuite/ld-i386/nogot1.d: Likewise. * testsuite/ld-i386/pr12718.d: Likewise. * testsuite/ld-i386/pr12921.d: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-ia64/tlsbin.rd: Likewise. * testsuite/ld-ia64/tlspic.rd: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-10.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-50.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-60.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-70.d: Likewise. * testsuite/ld-mmix/bspec1.d: Likewise. * testsuite/ld-mmix/bspec2.d: Likewise. * testsuite/ld-mmix/local1.d: Likewise. * testsuite/ld-mmix/local3.d: Likewise. * testsuite/ld-mmix/local5.d: Likewise. * testsuite/ld-mmix/local7.d: Likewise. * testsuite/ld-mmix/undef-3.d: Likewise. * testsuite/ld-powerpc/tlsexe.r: Likewise. * testsuite/ld-powerpc/tlsexe32.r: Likewise. * testsuite/ld-powerpc/tlsexetoc.r: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sh/sh64/crange1.rd: Likewise. * testsuite/ld-sh/sh64/crange2.rd: Likewise. * testsuite/ld-sh/sh64/crange3-cmpct.rd: Likewise. * testsuite/ld-sh/sh64/crange3-media.rd: Likewise. * testsuite/ld-sh/sh64/crange3.rd: Likewise. * testsuite/ld-sh/sh64/crangerel1.rd: Likewise. * testsuite/ld-sh/sh64/crangerel2.rd: Likewise. * testsuite/ld-sh/tlsbin-2.d: Likewise. * testsuite/ld-sh/tlspic-2.d: Likewise. * testsuite/ld-sparc/gotop32.rd: Likewise. * testsuite/ld-sparc/gotop64.rd: Likewise. * testsuite/ld-sparc/tlssunbin32.rd: Likewise. * testsuite/ld-sparc/tlssunbin64.rd: Likewise. * testsuite/ld-sparc/tlssunnopic32.rd: Likewise. * testsuite/ld-sparc/tlssunnopic64.rd: Likewise. * testsuite/ld-sparc/tlssunpic32.rd: Likewise. * testsuite/ld-sparc/tlssunpic64.rd: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/ilp32-4.d: Likewise. * testsuite/ld-x86-64/nogot1.d: Likewise. * testsuite/ld-x86-64/pr12718.d: Likewise. * testsuite/ld-x86-64/pr12921.d: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/split-by-file.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2.rd: Likewise. * testsuite/ld-xtensa/tlsbin.rd: Likewise. * testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-08-19 10:16:30 +02:00
2016-08-19 Nick Clifton <nickc@redhat.com>
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected
ordering of sections.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
* testsuite/gas/ia64/alias-ilp32.d: Likewise.
* testsuite/gas/ia64/alias.d: Likewise.
* testsuite/gas/ia64/group-1.d: Likewise.
* testsuite/gas/ia64/group-2.d: Likewise.
* testsuite/gas/ia64/secname-ilp32.d: Likewise.
* testsuite/gas/ia64/secname.d: Likewise.
* testsuite/gas/ia64/unwind-ilp32.d: Likewise.
* testsuite/gas/ia64/unwind.d: Likewise.
* testsuite/gas/ia64/xdata-ilp32.d: Likewise.
* testsuite/gas/ia64/xdata.d: Likewise.
* testsuite/gas/mmix/bspec-1.d: Likewise.
* testsuite/gas/mmix/bspec-2.d: Likewise.
* testsuite/gas/mmix/byte-1.d: Likewise.
* testsuite/gas/mmix/loc-1.d: Likewise.
* testsuite/gas/mmix/loc-2.d: Likewise.
* testsuite/gas/mmix/loc-3.d: Likewise.
* testsuite/gas/mmix/loc-4.d: Likewise.
* testsuite/gas/mmix/loc-5.d: Likewise.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
2016-08-11 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0.
* testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l:
Add tests for -0.0. Add an end-of-file comment.
2016-08-05 Nick Clifton <nickc@redhat.com>
PR gas/20429
* config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16
registers are pushed.
(do_vfp_nsyn_pop): Check that no more than 16 registers are
popped.
* testsuite/gas/arm/pr20429.s: New test.
* testsuite/gas/arm/pr20429.d: New test driver.
* testsuite/gas/arm/pr20429.1: Expected error output.
PR gas/20364
* config/tc-aarch64.c (s_ltorg): Change the mapping state after
aligning the frag.
(aarch64_init): Treat rs_align frags in code sections as
containing code, not data.
* testsuite/gas/aarch64/pr20364.s: New test.
* testsuite/gas/aarch64/pr20364.d: New test driver.
2016-08-04 Stefan Trleman <stefan.teleman@oracle.com>
PR gas/20427
* config/tc-sparc.c (cons_fix_new_sparc): Prevent the generation
of 64-bit relocation types when assembling for a 32-bit Solaris
target.
gas: avoid spurious failures in non-ELF targets in the SPARC testsuite. Many of the existing sparc tests fail in non-ELF targets (coff and a.out) due to spurious differences in the expected results: - Unlike ELF, a.out text sections are aligned to 2**3 and padded accordingly. The padding instruction is a `nop' (01 00 00 00). - Likewise, coff text sections are also aligned to 2**3 and padded accordingly. However, the padding instruction in these targets is an `illtrap 0' (00 00 00 00). - Unlike ELF, a.out and coff binaries don't contain hardware capabilities bits that could be used by BFD to determine the opcodes architecture corresponding to the instructions encoded in the objects (v9, v9a, v9b, v9c, etc). Consequently, in both a.out and coff tests we would need to pass proper `-m sparc:vXXX' options when invoking objdump before comparing results. In order to fix these issues, the most obvious solution would be to have three variants of .d files per impacted test. For example, for save.d we would have: save-elf.d, save-aout.d and save-coff.d. Using the `#source' directive, a single save.s file would provide the input for all of them. However, this approach has the following problems: - The #target and #notarget .d directives are very limited: they use globs instead of regular expressions, and thus it is not possible (or too messy) to use them to discriminate between elf, coff and a.out sparc targets. - It adds little or no value to have variants of all these tests for all the target types, and it would be a burden to maintain them. Actually the features tested in the spuriously failing tests (relatively modern sparc instructions, registers and asis) are not really found in running coff or a.out sparc systems. This patch changes sparc.exp so it will run these tests only in ELF-targets, using the more standard `is_elf_format' from binutils-common.exp instead of the ad-hoc (and less convenient, as it must be called before _every_ single elf-only test) sparc_elf_setup. Incidentally, the patch also fixes the #name entry for save-args.d. Tested in sparc*-*-linux-gnu, sparc-aout and sparc-coff targets. gas/ChangeLog: 2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate ELF targets. Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm, pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima, ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper, sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF targets. (sparc_elf_setup): Delete. * testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the test's #name entry.
2016-07-27 15:59:16 +02:00
2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
ELF targets.
Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
targets.
(sparc_elf_setup): Delete.
* testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
test's #name entry.
MIPS/GAS: Implement microMIPS branch/jump compaction Convert microMIPS branches and jumps whose delay slot would be filled by a generated NOP instruction to the corresponding compact form where one exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap. Do so even where the transformation switches from a 16-bit to a 32-bit branch encoding for no benefit in code size reduction, as this is still advantageous. This is because a branch/NOP pair takes 2 pipeline slots or a 2-cycle completion latency except in superscalar implementations. Whereas a compact branch may or may not stall on its target fetch, so it will at most have a 2-cycle completion latency and may have only 1 even in scalar implementations, and in superscalar implementations it is expected to have no worse latency as a branch/NOP pair has. Also it won't stall and therefore take the extra latency cycle in the not-taken case. Technically this is the same as MIPS16 compaction: for the qualifying instruction encodings the APPEND_ADD_COMPACT machine code generation method is selected where APPEND_ADD_WITH_NOP otherwise would and tells the code generator in `append_insn' to convert the regular form of an instruction to its corresponding compact form. For this the opcode is tweaked as necessary and the microMIPS opcode table is scanned for the matching updated instruction. A non-$0 `rt' operand to BEQ and BNE instructions is moved to the `rs' operand field of BEQZC and BNEZC encodings as required. Unlike with MIPS16 compaction however we need to handle out-of-distance branch relaxation as well. We do this by deferring the generation of any delay-slot NOP required to relaxation made in `md_convert_frag', by converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD where a relaxed instruction is recorded. Relaxation then, depending on actual code produced, chooses between either using a compact branch or jump encoding and emitting the NOP outstanding if no compact encoding is possible. For code simplicity's sake the relaxation pass is retained even if the principle of preferring a compact encoding to a 16-bit branch/NOP pair means, in the absence of out-of-range branch relaxation, that a single compact branch machine code instruction will eventually be produced from a given assembly source instruction. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16) (RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16) (RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32) (RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (get_append_method): Also return APPEND_ADD_COMPACT for microMIPS instructions. (find_altered_mips16_opcode): Exclude macros from matching. Factor code out... (find_altered_opcode): ... to this new function. (find_altered_micromips_opcode): New function. (frag_branch_delay_slot_size): Likewise. (append_insn): Handle microMIPS branch/jump compaction. (macro_start): Likewise. (relaxed_micromips_32bit_branch_length): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips.s: Add conditional explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-size-1.s: Likewise. * testsuite/gas/mips/micromips.l: Adjust line numbers. * testsuite/gas/mips/micromips-warn.l: Likewise. * testsuite/gas/mips/micromips-size-1.l: Likewise. * testsuite/gas/mips/micromips.d: Adjust padding. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips@beq.d: Update patterns for branch/jump compaction. * testsuite/gas/mips/micromips@bge.d: Likewise. * testsuite/gas/mips/micromips@bgeu.d: Likewise. * testsuite/gas/mips/micromips@blt.d: Likewise. * testsuite/gas/mips/micromips@bltu.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise. * testsuite/gas/mips/micromips@relax.d: Likewise. * testsuite/gas/mips/micromips@relax-at.d: Likewise. * testsuite/gas/mips/micromips@relax-swap3.d: Likewise. * testsuite/gas/mips/branch-extern-2.d: Likewise. * testsuite/gas/mips/branch-extern-4.d: Likewise. * testsuite/gas/mips/branch-section-2.d: Likewise. * testsuite/gas/mips/branch-section-4.d: Likewise. * testsuite/gas/mips/branch-weak-2.d: Likewise. * testsuite/gas/mips/branch-weak-5.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/micromips-compact.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. ld/ * testsuite/ld-mips-elf/micromips-branch-absolute.d: Update patterns for branch compaction. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to "j".
2016-07-27 18:27:55 +02:00
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Begin implementing ARC NPS-400 Accelerator instructions opcodes * arc-nps400-tbl.h: Change block comments to GNU format. * arc-dis.c: Add new globals addrtypenames, addrtypenames_max, and addtypeunknown. (get_addrtype): New function. (print_insn_arc): Print colons and address types when required. * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to define insert and extract functions for all address types. (arc_operands): Add operands for colon and all address types. * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, ARC_OPERAND_COLON. Add the arc_nps_address_type enum and ARC_NUM_ADDRTYPES. * opcode/arc.h: Add BMU to insn_class_t enum. * opcode/arc.h: Add PMU to insn_class_t enum. gas * config/tc-arc.c: Add new global arc_addrtype_hash. Define O_colon and O_addrtype. (debug_exp): Add O_colon and O_addrtype. (tokenize_arguments): Handle colon and address type tokens. (declare_addrtype): New function. (md_begin): Initialise arc_addrtype_hash. (arc_parse_name): Add lookup of address types. (assemble_insn): Handle colons and address types by ignoring them. * testsuite/gas/arc/nps400-8.s: New file. * testsuite/gas/arc/nps400-8.d: New file. * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests. * testsuite/gas/arc/nps400-8.d: Add expected PMU instruction output.
2016-07-27 16:57:18 +02:00
2016-07-27 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
MIPS/GAS: Respect the `insn32' mode in branch relaxation Complement: commit 833794fc12d98139fc33f6b0b85feb03471007b7 Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Tue Jun 25 18:02:34 2013 +0000 <https://sourceware.org/ml/binutils/2013-06/msg00104.html>, ("microMIPS insn32 mode support"), and fix an issue with microMIPS branch relaxation producing 16-bit instructions in the `insn32' mode. Use equivalent 32-bit instruction sequences. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag. (RELAX_MICROMIPS_INSN32): New macro. (RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT) (RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32) (RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16) (RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32) (RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (append_insn): Record `mips_opts.insn32' with relaxed microMIPS branches. (relaxed_micromips_32bit_branch_length): Handle the `insn32' mode. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips-branch-relax.s: Add `insn32' conditionals. * testsuite/gas/mips/micromips-branch-relax.l: Update line numbers accordingly. * testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise. * testsuite/gas/mips/micromips-branch-relax-insn32.d: New test. * testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New test. * testsuite/gas/mips/micromips-branch-relax-insn32.l: New stderr output. * testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New stderr output. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-26 18:50:55 +02:00
2016-07-26 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag.
(RELAX_MICROMIPS_INSN32): New macro.
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32)
(RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16)
(RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32)
(RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32):
Shift bits.
(append_insn): Record `mips_opts.insn32' with relaxed microMIPS
branches.
(relaxed_micromips_32bit_branch_length): Handle the `insn32'
mode.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Add `insn32'
conditionals.
* testsuite/gas/mips/micromips-branch-relax.l: Update line
numbers accordingly.
* testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise.
* testsuite/gas/mips/micromips-branch-relax-insn32.d: New test.
* testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New
test.
* testsuite/gas/mips/micromips-branch-relax-insn32.l: New
stderr output.
* testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New
stderr output.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/dsp.d: New file.
* testsuite/gas/arc/dsp.s: Likewise.
* testsuite/gas/arc/fpu.d: Likewise.
* testsuite/gas/arc/fpu.s: Likewise.
* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/tdpfp.d: Likewise.
* testsuite/gas/arc/tfpuda.d: Likewise.
2016-07-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_force_relocation): Remove
R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
MIPS: Convert cross-mode BAL to JALX Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX, similarly to how JAL instructions are converted. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode BAL to JALX. (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a corresponding error message. gas/ * config/tc-mips.c (mips_force_relocation, mips_fix_adjustable): Adjust comments for BAL to JALX linker conversion. (fix_bad_cross_mode_branch_p): Accept cross-mode BAL. * testsuite/gas/mips/unaligned-branch-1.l: Update error messages expected. * testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise. * testsuite/gas/mips/branch-local-4.d: New test. * testsuite/gas/mips/branch-local-n32-4.d: New test. * testsuite/gas/mips/branch-local-n64-4.d: New test. * testsuite/gas/mips/branch-addend.d: New test. * testsuite/gas/mips/branch-addend-n32.d: New test. * testsuite/gas/mips/branch-addend-n64.d: New test. * testsuite/gas/mips/branch-local-4.s: New test source. * testsuite/gas/mips/branch-addend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/unaligned-branch-2.d: Update error messages expected. * testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend.d: New test. * testsuite/ld-mips-elf/bal-jalx-local.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-3.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19 17:19:19 +02:00
2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
Adjust comments for BAL to JALX linker conversion.
(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
expected.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
* testsuite/gas/mips/branch-local-4.d: New test.
* testsuite/gas/mips/branch-local-n32-4.d: New test.
* testsuite/gas/mips/branch-local-n64-4.d: New test.
* testsuite/gas/mips/branch-addend.d: New test.
* testsuite/gas/mips/branch-addend-n32.d: New test.
* testsuite/gas/mips/branch-addend-n64.d: New test.
* testsuite/gas/mips/branch-local-4.s: New test source.
* testsuite/gas/mips/branch-addend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS: Verify the ISA mode and alignment of branch and jump targets Verify that the ISA mode of branch targets is the same as the referring relocation, so that an attempt to produce a branch between instructions encoded in different ISA modes each causes an error rather than silently producing non-functional code. Make sure that no symbol or addend bits are silently truncated: terminate with an error if the relocation value calculated cannot be encoded in the relocatable field of a branch; for REL targets also applying to any intermediate addend. Also make jump target's alignment verification consistent with that for branches. This change will require an update to some obscure handcoded assembly sources which make branches to labels placed at data objects, however for microMIPS code only. These labels will have to be updated with the `.insn' directive for containing code to assemble and link successfully. Such code is broken as any such labels have always been required by the microMIPS architecture specification[1][2] to be annotated this way for correct interpretation, and with our old code missing `.insn' directives caused labels to present different semantics depending on whether they were referred with branch (ISA bit ignored) or other relocations (ISA bit respected). Enforcing these checks however will ensure errors in building software, like mixed regular MIPS and microMIPS code links with branches between, will be diagnosed at the build time rather than causing odd run-time errors such as intermittent crashes. It will also let cross-mode BAL instructions be converted to JALX instructions, with a separate change. References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level Compatibility", p. 533 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level Compatibility", p. 623 bfd/ * elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1. (branch_reloc_p): New function. (mips_elf_calculate_relocation): Handle ISA mode determination for relocations against section symbols, against absolute symbols and absolute relocations. Also set `*cross_mode_jump_p' for branches. <R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment checks for weak undefined symbols. Also check target alignment within the same ISA mode. <R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches in the alignment check. <R_MICROMIPS_PC7_S1>: Add an alignment check. <R_MICROMIPS_PC10_S1>: Likewise. <R_MICROMIPS_PC16_S1>: Likewise. (mips_elf_perform_relocation): Report a failure for unsupported same-mode JALX instructions and cross-mode branches. (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add error messages for jumps to misaligned addresses. gas/ * config/tc-mips.c (mips_force_relocation): Also retain branch relocations against MIPS16 and microMIPS symbols. (fix_bad_cross_mode_jump_p): New function. (fix_bad_same_mode_jalx_p): Likewise. (fix_bad_misaligned_jump_p): Likewise. (fix_bad_cross_mode_branch_p): Likewise. (fix_bad_misaligned_branch_p): Likewise. (fix_validate_branch): Likewise. (md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP> <BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5, etc. Verify the ISA mode and alignment of the jump target. <BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check with a call to `fix_validate_branch'. <BFD_RELOC_MIPS_26_PCREL_S2>: Likewise. <BFD_RELOC_16_PCREL_S2>: Likewise. <BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1> <BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend. Verify the ISA mode and alignment of the branch target. (md_convert_frag): Verify the ISA mode and alignment of resolved MIPS16 branch targets. * testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction branch targets with `.insn'. * testsuite/gas/mips/branch-misc-5.s: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Update accordingly. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips-branch-relax.s: Annotate non-instruction branch target with `.insn'. * testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets with external symbols. * testsuite/gas/mips/micromips-insn32.d: Update accordingly. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips.d: Likewise. * testsuite/gas/mips/mips16.s: Annotate non-instruction branch targets with `.insn'. * testsuite/gas/mips/mips16.d: Update accordingly. * testsuite/gas/mips/mips16-64.d: Likewise. * testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction branch target with `.insn'. * testsuite/gas/mips/relax-swap3.s: Likewise. * testsuite/gas/mips/branch-local-2.l: New list test. * testsuite/gas/mips/branch-local-3.l: New list test. * testsuite/gas/mips/branch-local-n32-2.l: New list test. * testsuite/gas/mips/branch-local-n32-3.l: New list test. * testsuite/gas/mips/branch-local-n64-2.l: New list test. * testsuite/gas/mips/branch-local-n64-3.l: New list test. * testsuite/gas/mips/unaligned-jump-1.l: New list test. * testsuite/gas/mips/unaligned-jump-2.l: New list test. * testsuite/gas/mips/unaligned-jump-3.d: New test. * testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test. * testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test. * testsuite/gas/mips/unaligned-jump-mips16-3.d: New test. * testsuite/gas/mips/unaligned-jump-micromips-1.l: New list test. * testsuite/gas/mips/unaligned-jump-micromips-2.l: New list test. * testsuite/gas/mips/unaligned-jump-micromips-3.d: New test. * testsuite/gas/mips/unaligned-branch-1.l: New list test. * testsuite/gas/mips/unaligned-branch-2.l: New list test. * testsuite/gas/mips/unaligned-branch-3.d: New test. * testsuite/gas/mips/unaligned-branch-r6-1.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-2.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-3.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-4.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-5.d: New test. * testsuite/gas/mips/unaligned-branch-r6-6.d: New test. * testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test. * testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test. * testsuite/gas/mips/unaligned-branch-mips16-3.d: New test. * testsuite/gas/mips/unaligned-branch-micromips-1.l: New list test. * testsuite/gas/mips/unaligned-branch-micromips-2.l: New list test. * testsuite/gas/mips/unaligned-branch-micromips-3.d: New test. * testsuite/gas/mips/branch-local-2.s: New test source. * testsuite/gas/mips/branch-local-3.s: New test source. * testsuite/gas/mips/branch-local-n32-2.s: New test source. * testsuite/gas/mips/branch-local-n32-3.s: New test source. * testsuite/gas/mips/branch-local-n64-2.s: New test source. * testsuite/gas/mips/branch-local-n64-3.s: New test source. * testsuite/gas/mips/unaligned-jump-1.s: New test source. * testsuite/gas/mips/unaligned-jump-2.s: New test source. * testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source. * testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source. * testsuite/gas/mips/unaligned-jump-micromips-1.s: New test source. * testsuite/gas/mips/unaligned-jump-micromips-2.s: New test source. * testsuite/gas/mips/unaligned-branch-1.s: New test source. * testsuite/gas/mips/unaligned-branch-2.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-1.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-2.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-3.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-4.s: New test source. * testsuite/gas/mips/unaligned-branch-mips16-1.s: New test source. * testsuite/gas/mips/unaligned-branch-mips16-2.s: New test source. * testsuite/gas/mips/unaligned-branch-micromips-1.s: New test source. * testsuite/gas/mips/unaligned-branch-micromips-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message expected. * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise. * testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps, microMIPS BAL and MIPS16 instructions. * testsuite/ld-mips-elf/undefweak-overflow.d: Update accordingly. * testsuite/ld-mips-elf/unaligned-branch-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test. * testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test. * testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test. * testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test. * testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test. * testsuite/ld-mips-elf/unaligned-jump.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19 14:59:28 +02:00
2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_force_relocation): Also retain branch
relocations against MIPS16 and microMIPS symbols.
(fix_bad_cross_mode_jump_p): New function.
(fix_bad_same_mode_jalx_p): Likewise.
(fix_bad_misaligned_jump_p): Likewise.
(fix_bad_cross_mode_branch_p): Likewise.
(fix_bad_misaligned_branch_p): Likewise.
(fix_validate_branch): Likewise.
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
etc. Verify the ISA mode and alignment of the jump target.
<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
with a call to `fix_validate_branch'.
<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
<BFD_RELOC_16_PCREL_S2>: Likewise.
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
Verify the ISA mode and alignment of the branch target.
(md_convert_frag): Verify the ISA mode and alignment of resolved
MIPS16 branch targets.
* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
branch targets with `.insn'.
* testsuite/gas/mips/branch-misc-5.s: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
accordingly.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Annotate
non-instruction branch target with `.insn'.
* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
with external symbols.
* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
targets with `.insn'.
* testsuite/gas/mips/mips16.d: Update accordingly.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
branch target with `.insn'.
* testsuite/gas/mips/relax-swap3.s: Likewise.
* testsuite/gas/mips/branch-local-2.l: New list test.
* testsuite/gas/mips/branch-local-3.l: New list test.
* testsuite/gas/mips/branch-local-n32-2.l: New list test.
* testsuite/gas/mips/branch-local-n32-3.l: New list test.
* testsuite/gas/mips/branch-local-n64-2.l: New list test.
* testsuite/gas/mips/branch-local-n64-3.l: New list test.
* testsuite/gas/mips/unaligned-jump-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-3.d: New test.
* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
* testsuite/gas/mips/unaligned-branch-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-3.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
* testsuite/gas/mips/branch-local-2.s: New test source.
* testsuite/gas/mips/branch-local-3.s: New test source.
* testsuite/gas/mips/branch-local-n32-2.s: New test source.
* testsuite/gas/mips/branch-local-n32-3.s: New test source.
* testsuite/gas/mips/branch-local-n64-2.s: New test source.
* testsuite/gas/mips/branch-local-n64-3.s: New test source.
* testsuite/gas/mips/unaligned-jump-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (struct nds32_pseudo_opcode): Make pseudo_val
unsigned int.
(do_pseudo_b): Adjust.
(do_pseudo_bal): Likewise.
(do_pseudo_bge): Likewise.
(do_pseudo_bges): Likewise.
(do_pseudo_bgt): Likewise.
(do_pseudo_bgts): Likewise.
(do_pseudo_ble): Likewise.
(do_pseudo_bles): Likewise.
(do_pseudo_blt): Likewise.
(do_pseudo_blts): Likewise.
(do_pseudo_br): Likewise.
(do_pseudo_bral): Likewise.
(do_pseudo_la): Likewise.
(do_pseudo_li): Likewise.
(do_pseudo_ls_bhw): Likewise.
(do_pseudo_ls_bhwp): Likewise.
(do_pseudo_ls_bhwpc): Likewise.
(do_pseudo_ls_bhwi): Likewise.
(do_pseudo_move): Likewise.
(do_pseudo_neg): Likewise.
(do_pseudo_not): Likewise.
(do_pseudo_pushpopm): Likewise.
(do_pseudo_pushpop): Likewise.
(do_pseudo_v3push): Likewise.
(do_pseudo_v3pop): Likewise.
(do_pseudo_pushpop_stack): Likewise.
(do_pseudo_push_bhwd): Likewise.
(do_pseudo_pop_bhwd): Likewise.
(do_pseudo_pusha): Likewise.
(do_pseudo_pushi): Likewise.
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (struct pop_entry): Make the type of reloc
bfd_reloc_code_real_type.
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (pop_table): Remove sentinel.
(NUM_PERC_ENTRIES): Use ARRAY_SIZE on pop_table.
(md_begin): Adjust.
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-z8k.c (newfix): Make type of type argument
bfd_reloc_code_real_type.
(apply_fix): Likewise.
2016-07-16 Alan Modra <amodra@gmail.com>
* config/tc-epiphany.c: Don't include libbfd.h.
* config/tc-frv.c: Likewise.
* config/tc-ip2k.c: Likewise.
* config/tc-iq2000.c: Likewise.
* config/tc-m32c.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mt.c: Likewise.
* config/tc-nios2.c: Likewise.
2016-07-16 Alan Modra <amodra@gmail.com>
* config/bfin-parse.y: Don't include libbfd.h.
* config/tc-bfin.c: Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-metag.c: Likewise.
(create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT.
* Makefile.am: Update dependencies.
* Makefile.in: Regenerate.
MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbols Don't convert PC-relative REL relocations against absolute symbols to section-relative references and retain the original symbol reference instead. Offsets into the absolute section may overflow the limited range of their in-place addend field, causing an assembly error, e.g.: $ cat test.s .text .globl foo .ent foo foo: b bar .end foo .set bar, 0x12345678 $ as -EB -32 -o test.o test.s test.s: Assembler messages: test.s:3: Error: relocation overflow $ With the original reference retained the source can now be assembled and linked successfully: $ as -EB -32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 1000ffff b 0 <foo> 0: R_MIPS_PC16 bar 4: 00000000 nop ... $ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o $ objdump -dr test test: file format elf32-tradbigmips Disassembly of section .text: 12340000 <foo>: 12340000: 1000159d b 12345678 <bar> 12340004: 00000000 nop ... $ For simplicity always retain the original symbol reference, even if it would indeed fit. Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch relocations against absolute symbols to be converted on RELA targets to section-relative references. This is an intended effect of this change. Absolute symbols carry no ISA annotation in their `st_other' field and their value is not going to change with linker relaxation, so it is safe to discard the original reference and keep the calculated final symbol value only in the relocation's addend. Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring absolute symbols can be safely converted even on REL targets, as there the in-place addend of these relocations covers the entire 32-bit address space so it can hold the calculated final symbol value, and likewise the value referred won't be affected by any linker relaxation. Add a set of suitable test cases and enable REL linker tests which now work and were previously used as dump patterns for RELA tests only. gas/ * config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro. (mips_force_relocation_abs): New prototype. * config/tc-mips.c (mips_force_relocation_abs): New function. * testsuite/gas/mips/branch-absolute.d: Adjust dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/branch-absolute-addend.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf.exp: Run `branch-absolute-addend', `mips16-branch-absolute', `mips16-branch-absolute-addend' and `micromips-branch-absolute-addend'.
2016-07-12 02:31:29 +02:00
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Keep the ISA bit in the addend of branch relocations Correct a problem with the ISA bit being stripped from the addend of compressed branch relocations, affecting RELA targets. It has been there since microMIPS support has been added, with: commit df58fc944dbc6d5efd8d3826241b64b6af22f447 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Sun Jul 24 14:20:15 2011 +0000 <https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS: microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 relocations originally affected, and the R_MIPS16_PC16_S1 relocation recently added with commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually triggering a linker error, due to its heightened processing strictness level: $ cat test.s .text .set mips16 foo: b bar .set bar, 0x1235 .align 4, 0 $ as -EB -n32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1230 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o test.o: In function `foo': (.text+0x0): Branch to a non-instruction-aligned address $ This is because the ISA bit of the branch target does not match the ISA bit of the referring branch, hardwired to 1 of course. Retain the ISA bit then, so that the linker knows this is really MIPS16 code referred: $ objdump -dr fixed.o fixed.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1231 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o $ Add a set of MIPS16 tests to cover the relevant cases, excluding linker tests though which would overflow the in-place addend on REL targets and use them as dump patterns for RELA targets only. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1> <BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1> <BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the addend calculated. * testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit in `bar', export `foo'. * testsuite/gas/mips/mips16-branch-absolute.d: Adjust accordingly. * testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: Likewise. ld/ * testsuite/ld-mips-elf/mips16-branch-absolute.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except from `mips16-branch-absolute' and `mips16-branch-absolute-addend', referred indirectly only.
2016-07-12 02:30:48 +02:00
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
BFD: Let targets handle relocations against absolute symbols Fix a generic BFD issue with relocations against absolute symbols, which are installed without using any individual relocation handler provided by the backend. This causes any absolute section's addend to be lost on REL targets such as o32 MIPS, and also relocation-specific calculation adjustments are not made. As an example assembling this program: $ cat test.s .text foo: b bar b baz .set bar, 0x1234 $ as -EB -32 -o test-o32.o test.s $ as -EB -n32 -o test-n32.o test.s produces this binary code: $ objdump -dr test-o32.o test-n32.o test-o32.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 10000000 b 4 <foo+0x4> 0: R_MIPS_PC16 *ABS* 4: 00000000 nop 8: 1000ffff b 8 <foo+0x8> 8: R_MIPS_PC16 baz c: 00000000 nop test-n32.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: 10000000 b 4 <foo+0x4> 0: R_MIPS_PC16 *ABS*+0x1230 4: 00000000 nop 8: 10000000 b c <foo+0xc> 8: R_MIPS_PC16 baz-0x4 c: 00000000 nop $ where it is clearly visible in `test-o32.o', which uses REL relocations, that the absolute section's addend equivalent to the value of `bar' -- a reference to which cannot be fully resolved at the assembly time, because the reference is PC-relative -- has been lost, as has been the relocation-specific adjustment of -4, required to take into account the PC+4-relative calculation made by hardware with branches and seen in the external symbol reference to `baz' as the `ffff' addend encoded in the instruction word. In `test-n32.o', which uses RELA relocations, the absolute section's addend has been correctly retained. Give precedence then in `bfd_perform_relocation' and `bfd_install_relocation' to any individual relocation handler the backend selected may have provided, while still resorting to the generic calculation otherwise. This retains the semantics which we've had since forever or before the beginning of our repository history, and is at the very least compatible with `bfd_elf_generic_reloc' being used as the handler. Retain the `bfd_is_und_section' check unchanged at the beginning of `bfd_perform_relocation' since this does not affect the semantics of the function. The check returns the same `bfd_reloc_undefined' code the check for a null `howto' does, so swapping the two does not matter. Also the check is is mutually exclusive with the `bfd_is_abs_section' check, since a section cannot be absolute and undefined both at once, so swapping the two does not matter either. With this change applied the program quoted above now has the in-place addend correctly calculated and installed in the field being relocated: $ objdump -dr fixed-o32.o fixed-o32.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 1000048c b 1234 <bar> 0: R_MIPS_PC16 *ABS* 4: 00000000 nop 8: 1000ffff b 8 <foo+0x8> 8: R_MIPS_PC16 baz c: 00000000 nop $ Add a set of MIPS tests to cover the relevant cases, including absolute symbols with addends, and verifying that PC-relative relocations against symbols concerned resolve to the same value in the final link regardless of whether the REL or the RELA relocation form is used. Exclude linker tests though which would overflow the in-place addend on REL targets and use them as dump patterns for RELA targets only. bfd/ * reloc.c (bfd_perform_relocation): Try the `howto' handler first with relocations against absolute symbols. (bfd_install_relocation): Likewise. gas/ * testsuite/gas/mips/mips16-branch-absolute.d: Update patterns. * testsuite/gas/mips/branch-absolute.d: New test. * testsuite/gas/mips/branch-absolute-n32.d: New test. * testsuite/gas/mips/branch-absolute-n64.d: New test. * testsuite/gas/mips/branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/micromips-branch-absolute.d: New test. * testsuite/gas/mips/micromips-branch-absolute-n32.d: New test. * testsuite/gas/mips/micromips-branch-absolute-n64.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/branch-absolute.s: New test source. * testsuite/gas/mips/branch-absolute-addend.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-addend.s: New test source. * testsuite/gas/mips/micromips-branch-absolute.s: New test source. * testsuite/gas/mips/micromips-branch-absolute-addend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/branch-absolute.d: New test. * testsuite/ld-mips-elf/branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except from `branch-absolute-addend' and `micromips-branch-absolute-addend', referred indirectly only.
2016-07-12 02:30:01 +02:00
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/opcodes: Address issues with NAL disassembly Address issues with the disassembly of the NAL assembly idiom and R6 instruction introduced with commit 7361da2c952e ("Add support for MIPS R6.") and then further tweaked with commit b9121b573e2e ("Add in a JALRC alias and fix the NAL instruction."). As from R6 this instruction has replaced the encoding of `bltzal $0, . + 4' as the solely supported form of the former BLTZAL instruction for the regular MIPS ISA. The instruction is marked as an alias only in our regular MIPS opcode table, making it fail to disassemble in R6 code if the `no-aliases' machine option has been passed to `objdump': $ cat test.s .text foo: nal $ as -mips64r6 -o test.o test.s $ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o nal.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo> 04100000 0x4100000 ... $ This is because the `bltzal' entry has been marked as pre-R6 only in the opcode table and there is no other opcode pattern to match. Additionally the changes referred made NAL replace the equivalent `bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases' machine option has been used, in legacy code. Seeing NAL, especially in its updated form lacking the branch target argument, in the disassembly of such code may be confusing to people. This is because unlike with EHB only used in R2 and newer code -- the machine encoding of which we anyway always disassemble to its corresponding current architecture's mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has been indeed used in legacy code. Even though `bltzal $0, . + 8' and its machine code encoding (0x04100001) -- which is not equivalent to NAL and still disassembles as BLTZAL -- has been the predominant form as opposed to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep the old form in disassembly, while still accepting `nal' in assembly. Remove the alias marking then from the the `nal' instruction pattern, making it always match for R6 code, even with the `no-aliases' option. And move the entry beyond the `bltzal' entry, making the latter one take precedence for legacy binary code, while letting the former still match any `nal' mnemonic in source code assembled for a legacy target. Add a suitable test case to the GAS test suite. While the change affects the disassembler more than the assembler, so placing the test case in the binutils test suite might be more appropriate, the intent is also to verify that `nal' is still accepted by GAS for legacy targets, plus we have test infrastructure available in the GAS test suite for automatic multiple ISA level testing, which we lack from the binutils framework. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS annotation from the "nal" entry and reorder it beyond "bltzal". gas/ * testsuite/gas/mips/nal-1.d: New test. * testsuite/gas/mips/mipsr6@nal-1.d: New test. * testsuite/gas/mips/nal-2.d: New test. * testsuite/gas/mips/mipsr6@nal-2.d: New test. * testsuite/gas/mips/nal.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-08 17:07:39 +02:00
2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/nal-1.d: New test.
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
* testsuite/gas/mips/nal-2.d: New test.
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
* testsuite/gas/mips/nal.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/ldtxa.s: New file.
* testsuite/gas/sparc/ldtxa.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
2016-07-11 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum
as it is no longer needed.
2016-07-08 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Remove extraneous
`install_insn' call.
2016-07-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_qword_reg): Correct register kind
checked.
* testsuite/gas/i386/x86-64-suffix-bad.s: Add q-suffix with
16-bit register cases.
* testsuite/gas/i386/x86-64-suffix-bad.l: Adjust expectations.
MIPS/GAS/testsuite: Remove remnants of a.out/ECOFF support Complement: commit 16e5e222b6eae6f110ea72bf627585c095a453a8 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Sat Jun 22 16:57:42 2013 +0000 <https://sourceware.org/ml/binutils/2013-06/msg00195.html>, ("Make gas/mips/mips.exp ELF-only"), and remove the remaining stale ECOFF test dumps and pieces of a.out/ECOFF support in relocation match patterns. gas/ * testsuite/gas/mips/ecoff@ld.d: Remove test. * testsuite/gas/mips/ecoff@ld-forward.d: Remove test. * testsuite/gas/mips/ecoff@ld-zero-3.d: Remove test. * testsuite/gas/mips/ecoff@sd.d: Remove test. * testsuite/gas/mips/ecoff@sd-forward.d: Remove test. * testsuite/gas/mips/beq.d: Remove a.out and ECOFF support from reloc patterns. * testsuite/gas/mips/mipsr6@beq.d: Likewise. * testsuite/gas/mips/bge.d: Likewise. * testsuite/gas/mips/mipsr6@bge.d: Likewise. * testsuite/gas/mips/bgeu.d: Likewise. * testsuite/gas/mips/mipsr6@bgeu.d: Likewise. * testsuite/gas/mips/blt.d: Likewise. * testsuite/gas/mips/mipsr6@blt.d: Likewise. * testsuite/gas/mips/bltu.d: Likewise. * testsuite/gas/mips/mipsr6@bltu.d: Likewise. * testsuite/gas/mips/branch-likely.d: Likewise. * testsuite/gas/mips/la.d: Likewise. * testsuite/gas/mips/lb.d: Likewise. * testsuite/gas/mips/lifloat.d: Likewise. * testsuite/gas/mips/sb.d: Likewise. * testsuite/gas/mips/uld.d: Likewise. * testsuite/gas/mips/ulh.d: Likewise. * testsuite/gas/mips/ulw.d: Likewise. * testsuite/gas/mips/usd.d: Likewise. * testsuite/gas/mips/ush.d: Likewise. * testsuite/gas/mips/usw.d: Likewise.
2016-07-03 00:39:18 +02:00
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/ecoff@ld.d: Remove test.
* testsuite/gas/mips/ecoff@ld-forward.d: Remove test.
* testsuite/gas/mips/ecoff@ld-zero-3.d: Remove test.
* testsuite/gas/mips/ecoff@sd.d: Remove test.
* testsuite/gas/mips/ecoff@sd-forward.d: Remove test.
* testsuite/gas/mips/beq.d: Remove a.out and ECOFF support from
reloc patterns.
* testsuite/gas/mips/mipsr6@beq.d: Likewise.
* testsuite/gas/mips/bge.d: Likewise.
* testsuite/gas/mips/mipsr6@bge.d: Likewise.
* testsuite/gas/mips/bgeu.d: Likewise.
* testsuite/gas/mips/mipsr6@bgeu.d: Likewise.
* testsuite/gas/mips/blt.d: Likewise.
* testsuite/gas/mips/mipsr6@blt.d: Likewise.
* testsuite/gas/mips/bltu.d: Likewise.
* testsuite/gas/mips/mipsr6@bltu.d: Likewise.
* testsuite/gas/mips/branch-likely.d: Likewise.
* testsuite/gas/mips/la.d: Likewise.
* testsuite/gas/mips/lb.d: Likewise.
* testsuite/gas/mips/lifloat.d: Likewise.
* testsuite/gas/mips/sb.d: Likewise.
* testsuite/gas/mips/uld.d: Likewise.
* testsuite/gas/mips/ulh.d: Likewise.
* testsuite/gas/mips/ulw.d: Likewise.
* testsuite/gas/mips/usd.d: Likewise.
* testsuite/gas/mips/ush.d: Likewise.
* testsuite/gas/mips/usw.d: Likewise.
MIPS/GAS/testsuite: Split `branch-misc-2' tests into two Move `branch-misc-2' tests for non locally-defined-global symbols into separate files. These tests have been introduced with: commit 6f171daac941741e5fa904f6e462adb75a595495 Author: Alexandre Oliva <aoliva@redhat.com> Date: Thu Dec 12 04:40:22 2002 +0000 <https://sourceware.org/ml/binutils/2002-11/msg00631.html>, ("mips: branches to external labels are broken"), and: commit d17b874b6c14caa2f2ed1b5544a48de9f39a1a65 Author: Alexandre Oliva <aoliva@redhat.com> Date: Wed Mar 12 23:07:22 2003 +0000 <https://sourceware.org/ml/binutils/2003-03/msg00136.html>, ("On resolving the MIPS gas branch reloc issue"), while the test case served a different purpose. With the original intent of the test case brought back with: commit bad36eacdad37042c4efb1c5fbf48476b47de82b Author: Daniel Jacobowitz <drow@false.org> Date: Wed Nov 23 14:04:18 2005 +0000 <https://sourceware.org/ml/binutils/2005-11/msg00324.html>, ("R_MIPS_PC16, again"), these stand in the way for linker testing. gas/ * testsuite/gas/mips/branch-misc-2.s: Move non locally-defined-global symbol tests... * testsuite/gas/mips/branch-misc-5.s: ... to this new test. * testsuite/gas/mips/branch-misc-2.d: Update accordingly. * testsuite/gas/mips/branch-misc-2-64.d: Likewise. * testsuite/gas/mips/branch-misc-2pic.d: Likewise. * testsuite/gas/mips/branch-misc-2pic-64.d: Likewise. * testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise. * testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-2.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise. * testsuite/gas/mips/branch-misc-5.d: New test. * testsuite/gas/mips/branch-misc-5pic.d: New test. * testsuite/gas/mips/branch-misc-5-64.d: New test. * testsuite/gas/mips/branch-misc-5pic-64.d: New test. * testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test. * testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test. * testsuite/gas/mips/micromips@branch-misc-5.d: New test. * testsuite/gas/mips/micromips@branch-misc-5pic.d: New test. * testsuite/gas/mips/micromips@branch-misc-5-64.d: New test. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-03 00:09:06 +02:00
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/branch-misc-2.s: Move non
locally-defined-global symbol tests...
* testsuite/gas/mips/branch-misc-5.s: ... to this new test.
* testsuite/gas/mips/branch-misc-2.d: Update accordingly.
* testsuite/gas/mips/branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/branch-misc-5.d: New test.
* testsuite/gas/mips/branch-misc-5pic.d: New test.
* testsuite/gas/mips/branch-misc-5-64.d: New test.
* testsuite/gas/mips/branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/beq.s: Uncomment branches to undefined
symbols.
* testsuite/gas/mips/beq.d: Update accordingly.
* testsuite/gas/mips/mipsr6@beq.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Likewise.
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp: Restrict 64-bit `branch-mips'
tests to NewABI targets.
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips.exp: Group `branch-misc' tests
together.
2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
require field.
(aarch64_features): Initialize require fields.
(aarch64_parse_features): Handle dependencies.
(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
* testsuite/gas/aarch64/illegal-nofp16.s: New.
* testsuite/gas/aarch64/illegal-nofp16.l: New.
* testsuite/gas/aarch64/illegal-nofp16.d: New.
2016-07-01 Nick Clifton <nickc@redhat.com>
* macro.c (macro_expand_body): Use a buffer big enough to hold an
extremely large integer.
2016-07-01 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/mpx-inval-2.l: Relax for COFF targets.
2016-07-01 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.27.
2016-07-01 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (i386_index_check): Add special checks for bndmk,
bndldx, and bndstx.
* testsuite/gas/i386/mpx-inval-2.s: Add %rip and %eip relative
as well as scaling by other than 1 tests.
* testsuite/gas/i386/mpx-inval-2.l: Adjust accordingly.
2016-07-01 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (md_assemble): Alter address size checking for MPX
instructions.
* testsuite/gas/i386/mpx-inval-2.s: New.
* testsuite/gas/i386/mpx-inval-2.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
2016-07-01 Jan Beulich <jbeulich@suse.com>
PR gas/20318
* config/tc-i386.c (match_template): Add char parameter,
consumed in Intel mode for an extra suffix check.
(md_assemble): New local variable mnem_suffix.
* testsuite/gas/i386/suffix-bad.s: New.
* testsuite/gas/i386/suffix-bad.l: New.
* testsuite/gas/i386/i386.exp: Run new test (twice).
2016-07-01 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/movz.s: New.
* testsuite/gas/i386/movz32.d: New.
* testsuite/gas/i386/movz64.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
2016-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (struct _i386_insn): New field memop1_string.
(md_assemble): Free first memory operand string.
(i386_index_check): Use repprefixok to distingush xlat from
other (real) string ops.
(maybe_adjust_templates): New.
(i386_att_operand). Call it. Store first memory operand string.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
* testsuite/gas/i386/intel-movs.s: New.
* testsuite/gas/i386/intel-movs32.d: New.
* testsuite/gas/i386/intel-movs64.d: New.
* testsuite/gas/i386/i386.exp: Run new tests. Invoke as for
64-bits tests with "--defsym x86_64=1 --strip-local-absolute".
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (get_append_method): Fix a comment typo.
MIPS16/GAS: Fix delay slot filling across frags Fix an assertion failure like: test.s: Assembler messages: test.s:3: Internal error! Assertion failure in append_insn at .../gas/config/tc-mips.c:7523. Please report this bug. triggered by assembling MIPS16 code like: hello: addiu $4, $4, 4 jr $31 with the generation of a listing file enabled, e.g.: $ as -mips16 -O2 -aln=test.lst The cause of the problem is the lack of support for moving instructions across frags in MIPS16 jump swapping, which triggers more easily with listing enabled as in that case every instruction gets placed in its own frag. It would trigger even with listing disabled though if the instruction to swap a MIPS16 jump with was unfortunately enough placed as last in a frag that became full. This scenario is already handled correctly with branch swapping in regular MIPS and microMIPS code, so reuse it for MIPS16 code as well, and now that all MIPS16 handling has become the same as the regular MIPS and microMIPS cases remove MIPS16 special casing altogether. This effectively complements: commit 464ab0e55ade01d2bb0b4fa45c429af7a2f85a26 Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Mon Aug 6 20:33:00 2012 +0000 <https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS: Correct microMIPS branch swapping assertion") for the MIPS16 case. The assertion itself was introduced with: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction merely noted our existing lack of support for MIPS16 jump swapping across frags. gas/ * config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special case MIPS16 handling. * testsuite/gas/mips/branch-swap-3.d: New test. * testsuite/gas/mips/branch-swap-4.d: New test. * testsuite/gas/mips/mips16@branch-swap-3.d: New test. * testsuite/gas/mips/mips16@branch-swap-4.d: New test. * testsuite/gas/mips/micromips@branch-swap-3.d: New test. * testsuite/gas/mips/micromips@branch-swap-4.d: New test. * testsuite/gas/mips/branch-swap-3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30 16:02:20 +02:00
2016-06-30 Matthew Fortune <Matthew.Fortune@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
case MIPS16 handling.
* testsuite/gas/mips/branch-swap-3.d: New test.
* testsuite/gas/mips/branch-swap-4.d: New test.
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
* testsuite/gas/mips/branch-swap-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Simplify non-MIPS16 branch
swapping sequence.
PR gas/20312: Do not pad sections to alignment on failed assembly Correct a regression from commit 85024cd8bcb9 ("Run write_object_file after errors") causing unsuccessful assembly, which may be due to any reason, such as supplying a valid source like this: .text .byte 0 .err to terminate with an assertion failure like: test.s: Assembler messages: test.s:3: Error: .err encountered ../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg ../as-new: Please report this bug. on targets whose default text section alignment is above 0, typically RISC machines. This is due to an attempt to set last text section's frag alignment to 0, requested from `subsegs_finish_section' where `frag_align_code (alignment, 0)' is called with `alignment' set to 0 rather than the section alignment if `had_errors' has returned true. The call to `subsegs_finish_section' is made from `subsegs_finish' from `write_object_file' at unsuccessful completion, which previously wasn't made. Always set last section's frag alignment from the section alignment then, forcing no section padding instead if completing unsuccessfully, so that in that case alignment padding is still suppressed from any listing generated, fixing assertion failures for these targets: alpha-linuxecoff -FAIL: all pr20312 arm-aout -FAIL: all pr20312 mips-freebsd -FAIL: all pr20312 mips-img-linux -FAIL: all pr20312 mips-linux -FAIL: all pr20312 mips-mti-linux -FAIL: all pr20312 mips-netbsd -FAIL: all pr20312 mips-sgi-irix5 -FAIL: all pr20312 mips-sgi-irix6 -FAIL: all pr20312 mips-vxworks -FAIL: all pr20312 mips64-freebsd -FAIL: all pr20312 mips64-img-linux -FAIL: all pr20312 mips64-linux -FAIL: all pr20312 mips64-mti-linux -FAIL: all pr20312 mips64-openbsd -FAIL: all pr20312 mips64el-freebsd -FAIL: all pr20312 mips64el-img-linux -FAIL: all pr20312 mips64el-linux -FAIL: all pr20312 mips64el-mti-linux -FAIL: all pr20312 mips64el-openbsd -FAIL: all pr20312 mipsel-freebsd -FAIL: all pr20312 mipsel-img-linux -FAIL: all pr20312 mipsel-linux -FAIL: all pr20312 mipsel-mti-linux -FAIL: all pr20312 mipsel-netbsd -FAIL: all pr20312 mipsel-vxworks -FAIL: all pr20312 mipsisa32-linux -FAIL: all pr20312 mipsisa32el-linux -FAIL: all pr20312 mipsisa64-linux -FAIL: all pr20312 mipsisa64el-linux -FAIL: all pr20312 sh-pe -FAIL: all pr20312 sparc-aout -FAIL: all pr20312 gas/ PR gas/20312 * write.c (subsegs_finish_section): Force no section padding to alignment on failed assembly, always set last frag's alignment from section. * testsuite/gas/all/pr20312.l: New list test. * testsuite/gas/all/pr20312.s: New test source. * testsuite/gas/all/gas.exp: Run the new test
2016-06-29 02:38:50 +02:00
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
PR gas/20312
* write.c (subsegs_finish_section): Force no section padding to
alignment on failed assembly, always set last frag's alignment
from section.
* testsuite/gas/all/pr20312.l: New list test.
* testsuite/gas/all/pr20312.s: New test source.
* testsuite/gas/all/gas.exp: Run the new test
2016-06-30 Andrew Burgess <andrew.burgess@embecosm.com>
* config.in (TARGET_WITH_CPU): Undefine.
* configure.ac: Add --with-cpu support, and define in config.h.
* configure: Regenerate.
* config/tc-arc.c: Use TARGET_WITH_CPU to select default CPU.
* NEWS: Mention new configure option.
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/arm/armv8_2+rdma.d: New.
2016-06-29 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention --enable-compressed-debug-sections=gas is the
default for Linux/x86 targets.
* configure.tgt (ac_default_compressed_debug_sections): Default
to yes for Linux/x86 targets.
2016-06-29 Maciej W. Rozycki <macro@imgtec.com>
* write.c: Remove "libbfd.h" inclusion.
Use `supports_gnu_unique' with the `unique_symbol' and `type' tests Complement commit a43942db49b0 ("LD/ELF: Unify STB_GNU_UNIQUE handling") and use `supports_gnu_unique' with the `unique_symbol' and `type' tests, fixing failures like: .../binutils/testsuite/binutils-all/unique.s: Assembler messages: .../binutils/testsuite/binutils-all/unique.s:2: Error: symbol type "gnu_unique_object" is supported only by GNU targets ERROR: .../binutils/testsuite/binutils-all/unique.s: assembly failed UNRESOLVED: ar unique symbol in archive .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o Executing on host: .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o (timeout = 300) .../binutils/ar: tmpdir/unique.o: No such file or directory FAIL: ar unique symbol in archive and: .../gas/testsuite/gas/elf/type.s: Assembler messages: .../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets ../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg ../as-new: Please report this bug. .../gas/testsuite/../../binutils/readelf -s dump.o | grep "1 *\[FIONTCU\]" > dump.out Executing on host: sh -c {.../gas/testsuite/../../binutils/readelf -s dump.o >readelf.out 2>gas.stderr} /dev/null (timeout = 300) readelf: Error: dump.o: Failed to read file's magic number FAIL: elf type list on MIPS/FreeBSD targets: mips-freebsd -FAIL: ar unique symbol in archive mips-freebsd -FAIL: elf type list mips64-freebsd -FAIL: ar unique symbol in archive mips64-freebsd -FAIL: elf type list mips64el-freebsd -FAIL: ar unique symbol in archive mips64el-freebsd -FAIL: elf type list mipsel-freebsd -FAIL: ar unique symbol in archive mipsel-freebsd -FAIL: elf type list binutils/ * testsuite/binutils-all/ar.exp: Use `supports_gnu_unique' with the `unique_symbol' test. gas/ * testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the `type' test.
2016-06-28 14:21:36 +02:00
2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
`type' test.
2016-06-28 Alan Modra <amodra@gmail.com>
PR gas/20247
* testsuite/gas/elf/section11.s: Don't start directives in first column.
2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
MIPS16: Add R_MIPS16_PC16_S1 branch relocation support For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1' and the usual MIPS16 bit shuffling applies to relocated field handling, as per the encoding of the branch target in the extended form of the MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions. include/ * elf/mips.h (R_MIPS16_PC16_S1): New relocation. bfd/ * elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_PC16_S1. (mips16_reloc_map): Likewise. * elf64-mips.c (mips16_elf64_howto_table_rel): Likewise. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfn32-mips.c (elf_mips16_howto_table_rel): Likewise. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfxx-mips.c (mips16_branch_reloc_p): New function. (mips16_reloc_p): Handle R_MIPS16_PC16_S1. (b_reloc_p): Likewise. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_check_relocs): Likewise. * reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-mips.c (mips16_reloc_p): Handle BFD_RELOC_MIPS16_16_PCREL_S1. (b_reloc_p): Likewise. (limited_pcrel_reloc_p): Likewise. (md_pcrel_from): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. (md_convert_frag): Likewise. (mips_fix_adjustable): Update comment. * testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-3.l: Remove file. * testsuite/gas/mips/mips16-branch-absolute.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.s: Add padding. * testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid implicit instruction padding, avoid MIPS16 JR->JRC conversion. * testsuite/gas/mips/branch-weak-6.d: New test. * testsuite/gas/mips/branch-weak-7.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-3.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test. * testsuite/ld-mips-elf/mips16-branch.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 02:23:36 +02:00
2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips16_reloc_p): Handle
BFD_RELOC_MIPS16_16_PCREL_S1.
(b_reloc_p): Likewise.
(limited_pcrel_reloc_p): Likewise.
(md_pcrel_from): Likewise.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise.
(md_convert_frag): Likewise.
(mips_fix_adjustable): Update comment.
* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
implicit instruction padding, avoid MIPS16 JR->JRC conversion.
* testsuite/gas/mips/branch-weak-6.d: New test.
* testsuite/gas/mips/branch-weak-7.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-27 Vineet Gupta <vgupta@synopsys.com>
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
cfi_add_CFA_def_cfa to generate default CFA with offset
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
2016-06-27 14:52:20 +02:00
2016-06-27 Nick Clifton <nickc@redhat.com>
PR gas/20247
* as.h (do_not_pad_sections_to_alignment): New global variable.
* as.c (show_usage): Add --no-pad-sections.
(parse_args): Likewise.
* write.c (size_seg): Skip padding the end of the section if
requested from the command line.
(SUB_SEGMENT_ALIGN): Likewise.
* doc/as.texinfo: Document the new option.
* NEWS: Mention the new feature.
* testsuite/gas/elf/section11.s: New test.
* testsuite/gas/elf/section11.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
2016-06-27 12:01:34 +02:00
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-dlx.c: Include bfd/elf32-dlx.h.
* config/tc-dlx.h: Remove prototype of dlx_set_skip_hi16.
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (xtensa_elf_suffix): Use ARRAY_SIZE instead of a
sentinal element.
(map_suffix_reloc_to_operator): Likewise.
(map_operator_to_reloc): Likewise.
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal
element in relax_table.
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c: Make the type of reg_entry::type
aarch_reg_type.
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-bfin.c (bfin_cpus): Remove sentinal.
(md_parse_option): Adjust.
* config/tc-aarch64.c (aarch64_parse_abi): Replace use of a sentinal
with iteration from 0 to ARRAY_SIZE.
* config/tc-mcore.c (md_begin): Likewise.
* config/tc-visium.c (visium_parse_arch): Likewise.
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_set_default_include): remove argument
and simplify accordingly.
(tic54x_include): Adjust.
(tic54x_mlib): Likewise.
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (xtensa_make_property_section): Remove prototype.
MIPS16/GAS: Restore unsupported relocation diagnostics Correct a MIPS16 relocation handling regression in GAS introduced with: commit 177b4a6ad0047c8995fbc55016bc4f4b68d53b4a Author: Alexandre Oliva <aoliva@redhat.com> Date: Mon Mar 18 18:56:18 2002 +0000 discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>, which removed a preparatory call to `mips16_extended_frag' previously made from `md_estimate_size_before_relax'. As a result the function is never called with its `sec' parameter non-NULL and consequently all the unsupported relocation checks within are dead and never trigger, causing any unhandled relocations to silently resolve to 0. Unfortunately there was no sufficient test suite coverage back then to catch this. Remove all dead code then, and all the associated comments. Update the remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass the relocation section as the `sec' parameter and use it to mark frags which require an external relocation, as extended. Finally handle any outstanding MIPS16 relocations in `md_convert_frag' and report an error since we don't support any except with percent operators. gas/ * config/tc-mips.c (append_insn): Use any `O_symbol' expression unchanged with relaxed MIPS16 instructions. (mips16_extended_frag): Adjust accordingly. Return 1 right away if a relocation will be required for the symbol requested. Remove dead first relaxation pass code. (mips_relax_frag): Pass `sec' down to `mips16_extended_frag'. (md_convert_frag): Adjust symbol value calculation. Raise an error if a relocation is required for the symbol requested. * testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns, add error output. * testsuite/gas/mips/mips16@relax-swap3.l: New error output. * testsuite/gas/mips/mips16-pcrel-relax-0.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-1.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-2.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-0.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-1.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-2.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-3.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute.d: New test. * testsuite/gas/mips/mips16-branch-reloc-0.d: New test. * testsuite/gas/mips/mips16-branch-reloc-1.d: New test. * testsuite/gas/mips/mips16-branch-reloc-2.d: New test. * testsuite/gas/mips/mips16-branch-reloc-3.d: New test. * testsuite/gas/mips/mips16-branch-addend-0.d: New test. * testsuite/gas/mips/mips16-branch-addend-1.d: New test. * testsuite/gas/mips/mips16-branch-addend-2.d: New test. * testsuite/gas/mips/mips16-branch-addend-3.d: New test. * testsuite/gas/mips/mips16-branch-absolute.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-0.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-1.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-2.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output. * testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output. * testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-absolute.l: New error output. * testsuite/gas/mips/mips16-branch-reloc-2.l: New error output. * testsuite/gas/mips/mips16-branch-reloc-3.l: New error output. * testsuite/gas/mips/mips16-branch-addend-2.l: New error output. * testsuite/gas/mips/mips16-branch-addend-3.l: New error output. * testsuite/gas/mips/mips16-branch-absolute.l: New error output. * testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output. * testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-absolute.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-0.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-1.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-2.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-3.s: New test source. * testsuite/gas/mips/mips16-branch-addend-0.s: New test source. * testsuite/gas/mips/mips16-branch-addend-1.s: New test source. * testsuite/gas/mips/mips16-branch-addend-2.s: New test source. * testsuite/gas/mips/mips16-branch-addend-3.s: New test source. * testsuite/gas/mips/mips16-branch-absolute.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-25 01:49:10 +02:00
2016-06-24 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Use any `O_symbol' expression
unchanged with relaxed MIPS16 instructions.
(mips16_extended_frag): Adjust accordingly. Return 1 right
away if a relocation will be required for the symbol requested.
Remove dead first relaxation pass code.
(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
(md_convert_frag): Adjust symbol value calculation. Raise an
error if a relocation is required for the symbol requested.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
add error output.
* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
* testsuite/gas/mips/mips16-branch-absolute.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-24 Alan Modra <amodra@gmail.com>
* configure.tgt (alpha-*-openbsd*): Use em=nbsd.
2016-06-23 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (b_reloc_p): New function.
(mips_fix_adjustable): Also keep the original microMIPS symbol
referred from branch relocations.
* testsuite/gas/mips/branch-local-1.d: New test.
* testsuite/gas/mips/branch-local-n32-1.d: New test.
* testsuite/gas/mips/branch-local-n64-1.d: New test.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
relocations.
* testsuite/gas/mips/branch-local-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new cases.
2016-06-23 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (options, md_longopts, md_parse_option): Move
-mspfp, -mdpfp and -mfpuda out of the sections for dummy
options. Correct erroneous enabling of SPFP instructions when
using -mnps400.
2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
setbool, xor3>: New tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c: Include elf/xtensa.h.
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
<BFD_RELOC_LO16_PCREL>: New switch cases.
(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
Move switch cases along `BFD_RELOC_MIPS_JMP'.
<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
the resolved case.
* testsuite/gas/mips/pcrel-reloc-4.d: New test.
* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-5.d: New test.
* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3>
<BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences
via `fixP->fx_addsy'.
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>:
Calculate relocation from the containing aligned doubleword.
(tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the
addend from the containing aligned doubleword.
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
rather than `mips_opts' for the R6 ISA check.
(mips_fix_adjustable): Likewise.
* testsuite/gas/mips/pcrel-reloc-1.d: New test.
* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-2.d: New test.
* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-3.d: New test.
* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Arc assembler: Convert nps400 from a machine type to an extension. gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-21 15:03:08 +02:00
2016-06-21 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (check_cpu_feature, md_parse_option):
Add nps400 option and feature. Add check for nps400
feature. Refactor existing checks to check subclass before
feature enablement.
(md_show_usage): Document flags for NPS-400 and add some other
undocumented flags.
(cpu_type): Remove nps400 CPU type entry
(check_zol): Remove bfd_mach_arc_nps400 case.
(md_show_usage): Add help on -mcpu=nps400.
(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
set.
* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
-fpuda flags. Document -mcpu=nps400.
* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
expected flags to match ARC700 instead of NPS400.
* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
* testsuite/gas/arc/nps-400-2.d: Likewise.
* testsuite/gas/arc/nps-400-3.d: Likewise.
* testsuite/gas/arc/nps-400-4.d: Likewise.
* testsuite/gas/arc/nps-400-5.d: Likewise.
* testsuite/gas/arc/nps-400-6.d: Likewise.
* testsuite/gas/arc/nps-400-7.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
avoid clash with cbba instruction.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
2016-06-20 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
2016-06-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_fix_adjustable): Update comment on jump
reloc conversion.
2016-06-20 Virendra Pathak <virendra.pathak@broadcom.com>
* config/tc-aarch64.c (aarch64_cpus): Update vulcan feature set.
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns. This patch fixes and expands the definition of the read/write instructions for ancillary-state, privileged and hyperprivileged registers in opcodes. It also adds support for three new v9m hyperprivileged registers: %hmcdper, %hmcddfr and %hva_mask_nz. Finally, the patch expands existing tests (and adds several new ones) in order to cover all the read/write instructions in all its variants. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (rdasr): New macro. (wrasr): Likewise. (rdpr): Likewise. (wrpr): Likewise. (rdhpr): Likewise. (wrhpr): Likewise. (sparc_opcodes): Use the macros above to fix and expand the definition of read/write instructions from/to asr/privileged/hyperprivileged instructions. * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and %hva_mask_nz. Prefer softint_set and softint_clear over set_softint and clear_softint. (print_insn_sparc): Support %ver in Rd. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper, %hmcddfr and %hva_mask_nz. (sparc_ip): New handling of asr/privileged/hyperprivileged registers, adapted to the new form of the sparc opcodes table. * testsuite/gas/sparc/rdasr.s: New file. * testsuite/gas/sparc/rdasr.d: Likewise. * testsuite/gas/sparc/wrasr.s: Likewise. * testsuite/gas/sparc/wrasr.d: Likewise. * testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and wrasr tests. * testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged registers require it. * testsuite/gas/sparc/wrpr.s: Complete to cover all privileged registers and write instruction modalities. * testsuite/gas/sparc/wrpr.d: Likewise. * testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged registers. * testsuite/gas/sparc/rdhpr.d: Likewise. * testsuite/gas/sparc/wrhpr.s: Likewise. * testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 11:15:43 +02:00
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
gas: sparc: fix collision of registers and pseudo-ops. The current sparc assembler breaks when the name of an ancillary-state register, privileged register or hyperprivileged register has a %-pseudo-operation name as a prefix. For example, %hmcdper and %hm(), or %hintp and %hi(). This patch fixes it by introducing a new table `perc_table' (for %-table) that contains an entry for every %name supported by the assembler, other than the general registers. This table is used to detect name collisions when the assembler tries to detect a %-pseudo-op. This patch also fixes a related bug, making sure that v9a_asr_table and hpriv_reg_table are sorted in reverse lexicographic order, as otherwise the search code may fail. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (priv_reg_table): Use NULL instead of the empty string to mark the end of the array. (hpriv_reg_table): Likewise. (v9a_asr_table): Likewise. (cmp_reg_entry): Handle entries with NULL names. (F_POP_V9): Define. (F_POP_PCREL): Likewise. (F_POP_TLS_CALL): Likewise. (F_POP_POSTFIX): Likewise. (struct pop_entry): New type. (pop_table): New variable. (enum pop_entry_type): New type. (struct perc_entry): Likewise. (NUM_PERC_ENTRIES): Define. (perc_table): New variable. (cmp_perc_entry): New function. (md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize perc_table. (sparc_ip): Handle entries with NULL names in priv_reg_table, hpriv_reg_table and v9a_asr_table. Use perc_table to handle %-pseudo-ops.
2016-06-17 11:13:30 +02:00
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (priv_reg_table): Use NULL instead of the
empty string to mark the end of the array.
(hpriv_reg_table): Likewise.
(v9a_asr_table): Likewise.
(cmp_reg_entry): Handle entries with NULL names.
(F_POP_V9): Define.
(F_POP_PCREL): Likewise.
(F_POP_TLS_CALL): Likewise.
(F_POP_POSTFIX): Likewise.
(struct pop_entry): New type.
(pop_table): New variable.
(enum pop_entry_type): New type.
(struct perc_entry): Likewise.
(NUM_PERC_ENTRIES): Define.
(perc_table): New variable.
(cmp_perc_entry): New function.
(md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize
perc_table.
(sparc_ip): Handle entries with NULL names in priv_reg_table,
hpriv_reg_table and v9a_asr_table. Use perc_table to handle
%-pseudo-ops.
Fix simple gas testsuite failures. binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 reloc. gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the instruction size. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mn10200.c (md_assemble): Likewise. * config/tc-moxie.c (md_assemble): Likewise. * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of exception targets. Add alpha, hppa, microblaze and rl78 to list of exceptions. (forward): Add microblaze to list of exceptions. (fwdexp): Add alpha to list of exceptions. (redef2): Add arm-epoc-pe and rl78 to list of exceptions. (redef3): Add rl78 and x86_64 cygwin to list of exceptions. (do_930509a): Alpha sort list of exception targets. Add h8300 and mn10200 to list of exceptions. (align2): Expect to fail for nds32. (cond): Add alpha and rl78 to list of exceptions. * testsuite/gas/all/none.d: Skip for ft32 and hppa. * testsuite/gas/all/string.d: Skip for tic4x. * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff target does not support ELF. * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH tests for sh-pe and sh-rtemscoff targets. * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to list of exceptions. (type): Run the noifunc version for alpha-freebsd and visium. * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, mn10200 or moxie targets. * testsuite/gas/ft32/insn.d: Update expected disassembly. * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin targets. * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for mcore and rx targets. * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, rl78 and vax. (purge): Expect to fail on the ns32k and vax. * testsuite/gas/nds32/alu-2.d: Update expected disassembly. * testsuite/gas/nds32/ls.d: Likewise. * testsuite/gas/nds32/sys-reg.d: Likewise. * testsuite/gas/nds32/usr-spe-reg.d: Likewise. * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. * testsuite/gas/pe/section-align-3.d: Likewise. * testsuite/gas/pe/section-exclude.d: Likewise. * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required data has been seen. * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow for variations in whitespace. * testsuite/gas/tilepro/t_constants.d: Pass once all the required data has been seen. * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. Installs a 32-bit value without generating warnings on 64-bit hosts. Use the new macro to replace the .word directives. opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer constants to match expected behaviour. (nds32_parse_opcode): Likewise. Also for whitespace.
2016-06-15 17:25:34 +02:00
2016-06-15 Nick Clifton <nickc@redhat.com>
* config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
instruction size.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mn10200.c (md_assemble): Likewise.
* config/tc-moxie.c (md_assemble): Likewise.
* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
exception targets. Add alpha, hppa, microblaze and rl78 to list
of exceptions.
(forward): Add microblaze to list of exceptions.
(fwdexp): Add alpha to list of exceptions.
(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
(do_930509a): Alpha sort list of exception targets. Add h8300 and
mn10200 to list of exceptions.
(align2): Expect to fail for nds32.
(cond): Add alpha and rl78 to list of exceptions.
* testsuite/gas/all/none.d: Skip for ft32 and hppa.
* testsuite/gas/all/string.d: Skip for tic4x.
* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
target does not support ELF.
* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH
tests for sh-pe and sh-rtemscoff targets.
* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
list of exceptions.
(type): Run the noifunc version for alpha-freebsd and visium.
* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
mn10200 or moxie targets.
* testsuite/gas/ft32/insn.d: Update expected disassembly.
* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
targets.
* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
mcore and rx targets.
* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
rl78 and vax.
(purge): Expect to fail on the ns32k and vax.
* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
* testsuite/gas/nds32/ls.d: Likewise.
* testsuite/gas/nds32/sys-reg.d: Likewise.
* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
* testsuite/gas/pe/section-align-3.d: Likewise.
* testsuite/gas/pe/section-exclude.d: Likewise.
* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
data has been seen.
* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
for variations in whitespace.
* testsuite/gas/tilepro/t_constants.d: Pass once all the required
data has been seen.
* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
Installs a 32-bit value without generating warnings on 64-bit
hosts.
Use the new macro to replace the .word directives.
2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/add_s.d: New file.
* testsuite/gas/arc/add_s.s: New file.
2016-06-14 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps400-6.s: Add tests of ldbit.
* testsuite/gas/arc/nps400-6.d: Likewise.
2016-06-14 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps400-6.s: Add tests of hash, tr, utf8, e4by, and
addf.
* testsuite/gas/arc/nps400-6.d: Likewise.
2016-06-14 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps400-6.s: Add tests of calcbsd, calcbxd,
calckey, calcxkey, mxb, imxb, addl, subl, andl, orl, xorl, andab, orab,
lbdsize, bdlen, csms, csma, cbba, zncv, and hofs.
* testsuite/gas/arc/nps400-6.d: Likewise.
2016-06-14 Nick Clifton <nickc@redhat.com>
* config/tc-nds32.c (nds32_get_align): Avoid left shifting a
signed constant.
2016-06-13 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
JALR relocations on R6.
* testsuite/gas/mips/jal-svr4pic-local.d: New test.
* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-13 Virendra Pathak <virendra.pathak@broadcom.com>
* config/tc-aarch64.c (aarch64_cpus): Add Broadcom Vulcan.
* doc/c-aarch64.texi: Document that vulcan is a valid processor
name.
2016-06-13 Nick Clifton <nickc@redhat.com>
* config/tc-arm.c: For non-ELF based targets skip ARM feature sets
that are not supported.
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
constant.
* config/tc-cr16.c (check_range): Likewise.
* config/tc-nios2.c (nios2_check_overflow): Likewise.
2016-06-08 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (print_operands): Substitute size.
(output_operand_error_record): Likewise.
PowerPC VLE VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 14:34:38 +02:00
2016-06-07 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
(arm_ext_ras): Renamed from arm_ext_v8_2.
(insns): Update for arm_ext_v8_2 renaming.
(arm_extensions): Add "ras".
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
* testsuite/gas/arm/armv8-a+ras.d: New.
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
options.
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* itbl-parse.y (yyerror): Use modern argument declaration style.
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sh.c (parse_reg): Change type of mode argument to
sh_arg_type.
(get_operand): Adjust.
(insert): Change type of how to bfd_reloc_code_real_type.
(insert4): Likewise.
* config/tc-sh64.c (shmedia_get_operand): Adjust.
(shmedia_parse_reg): Change type of mode to shmedia_arg_type.
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg
const char *.
2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry.
* doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry.
* doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
2016-06-02 Vineet Gupta <Vineet.Gupta1@synopsys.com>
* configure.tgt: Replace -uclibc with *.
Add support for 48 and 64 bit ARC instructions. gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-02 15:03:23 +02:00
2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ns32k.c: Remove definition of input_line_pointer.
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (avr_parse_cons_expression): Replace iteration to
sentinal with iteration to array size.
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/xtensa-relax.h: Move typedefs of enums to the enums
definition.
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ns32k.c (bit_fix_new): Replace obstack-alloc with XOBNEW
macro.
2016-06-01 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
2016-05-29 17:26:43 +02:00
2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20145
* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
noavx512ifma and noavx512vbmi.
* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
and noavx512vbmi.
* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
* testsuite/gas/i386/noavx512-1.l: New file.
* testsuite/gas/i386/noavx512-1.s: Likewise.
* testsuite/gas/i386/noavx512-2.l: Likewise.
* testsuite/gas/i386/noavx512-2.s: Likewise.
Update x86 CPU_XXX_FLAGS handling Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C, FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives to x86 assembler. TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_arch): Add 687. (cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. (parse_real_register): Check cpuregmmx instead of cpummx for MMX register. Check cpuregxmm instead of cpusse for XMM register. Check cpuregymm instead of cpuavx for YMM register. Check cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register. * doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. * testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx. * testsuite/gas/i386/arch-10.d (as): Likewise. * testsuite/gas/i386/arch-11.s: Add ".arch .mmx". * testsuite/gas/i386/i386.exp: Pass mmx to assembler for arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3 and noavx-4. * testsuite/gas/i386/no87-3.l: New file. * testsuite/gas/i386/no87-3.s: Likewise. * testsuite/gas/i386/noavx-3.l: Likewise. * testsuite/gas/i386/noavx-3.s: Likewise. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-4.s: Likewise. * testsuite/gas/i386/nosse-4.l: Likewise. * testsuite/gas/i386/nosse-4.s: Likewise. * testsuite/gas/i386/nosse-5.d: Likewise. * testsuite/gas/i386/nosse-5.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and CpuRegMask for AVX512. (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM and CpuRegMask. (set_bitfield_from_cpu_flag_init): New function. (set_bitfield): Remove const on f. Call set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. * i386-opc.h (CpuRegMMX): New. (CpuRegXMM): Likewise. (CpuRegYMM): Likewise. (CpuRegZMM): Likewise. (CpuRegMask): Likewise. (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm and cpuregmask. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-27 19:05:39 +02:00
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20154
* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
cpuintel64.
(match_template): Check Intel64/AMD64 ISA.
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20154
* config/tc-i386.c (intel64): New.
(cpu_flags_match): Set cpuamd64 and cpuintel64.
(md_parse_option): Set intel64 instead of cpuamd64 and
cpuintel64.
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor
cpuno64.
2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
* testsuite/gas/ppc/altivec3.s: Likewise.
* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-05-26 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
* testsuite/gas/i386/noavx-1.l: Likewise.
* testsuite/gas/i386/nommx-1.l: Likewise.
* testsuite/gas/i386/nosse-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
* testsuite/gas/i386/noavx-1.s: Likewise.
* testsuite/gas/i386/nommx-1.s: Likewise.
* testsuite/gas/i386/nosse-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-metag.c (metag_handle_align): Make the type of noop
unsigned char.
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
bfd_reloc_code_real_type.
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20140
* config/tc-i386.c (cpu_flags_match): Require another match
for AVX512VL.
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
x86-64-avx512vl-1 and x86-64-avx512vl-2.
* testsuite/gas/i386/avx512vl-1.l: New file.
* testsuite/gas/i386/avx512vl-1.s: Likewise.
* testsuite/gas/i386/avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/20141
* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
* testsuite/gas/i386/x86-64-pr20141.d: New file.
* testsuite/gas/i386/x86-64-pr20141.s: Likewise.
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (arch_entry): Remove negated.
(noarch_entry): New struct.
(cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx.
(cpu_noarch): New.
(set_cpu_arch): Check cpu_noarch after cpu_arch.
(md_parse_option): Allow -march=+nosse. Check cpu_noarch after
cpu_arch.
(output_message): New function.
(show_arch): Use it. Handle cpu_noarch.
* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
* testsuite/gas/i386/noavx-1.l: New file.
* testsuite/gas/i386/noavx-1.s: Likewise.
* testsuite/gas/i386/noavx-2.s: Likewise.
* testsuite/gas/i386/noavx-2.l: Likewise.
* testsuite/gas/i386/nommx-1.s: Likewise.
* testsuite/gas/i386/nommx-1.l: Likewise.
* testsuite/gas/i386/nommx-2.s: Likewise.
* testsuite/gas/i386/nommx-2.l: Likewise.
* testsuite/gas/i386/nommx-3.s: Likewise.
* testsuite/gas/i386/nommx-3.l: Likewise.
* testsuite/gas/i386/nosse-1.s: Likewise.
* testsuite/gas/i386/nosse-1.l: Likewise.
* testsuite/gas/i386/nosse-2.s: Likewise.
* testsuite/gas/i386/nosse-2.l: Likewise.
* testsuite/gas/i386/nosse-3.s: Likewise.
* testsuite/gas/i386/nosse-3.l: Likewise.
2016-05-25 Chua Zheng Leong <chuazl@comp.nus.edu.sg>
2016-05-25 14:12:14 +02:00
PR target/20067
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
instruction if supported by the currently selected fpu variant.
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
jump relocations against MIPS16 or microMIPS symbols on RELA
targets.
* testsuite/gas/mips/jalx-local.d: New test.
* testsuite/gas/mips/jalx-local-n32.d: New test.
* testsuite/gas/mips/jalx-local-n64.d: New test.
* testsuite/gas/mips/jalx-local.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_apply_fix)
<BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust
code accordingly.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct suffix_reloc_map): Change type of field
operator to operatorT.
(map_suffix_reloc_to_operator): Change return type to operatorT.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-d30v.c (find_format): Change type of X_op to operatorT.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mmix.c (mmix_parse_predefined_name): Change type of
handler_charp to const char *.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove.
(ft32_target_format): Likewise.
(TARGET_FORMAT): Adjust.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (dot_rot): simplify allocations from obstacks.
(ia64_frob_label): Likewise.
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-cr16.c (check_range): Make type of retval op_err.
* config/tc-crx.c: Likewise.
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_begin): Add XY registers.
(cpu_types): Code density is default off for ARC EM.
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (attributes_t): Renamed attribute class to
attr_class.
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
2016-05-23 14:56:46 +02:00
2016-05-23 Kuba Sejdak <jakub.sejdak@phoesys.com>
* configuse.tgt: Add entry for arm-phoenix.
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_sect): simplify string creation.
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_mmregs): Adjust.
(md_begin): Likewise.
(encode_condition): Likewise.
(encode_cc3): Likewise.
(encode_cc2): Likewise.
(encode_operand): Likewise.
(tic54x_undefined_symbol): Likewise.
2016-05-20 Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (mips_cpu_info_table): Update comment. Add
p6600 entry.
* doc/c-mips.texi: Document p6600 -march option.
2016-05-20 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19600
* config/tc-i386.c (md_apply_fix): Preserve addend for
BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
* testsuite/gas/i386/addend.d: New file.
* testsuite/gas/i386/addend.s: Likewise.
* testsuite/gas/i386/x86-64-addend.d: Likewise.
* testsuite/gas/i386/x86-64-addend.s: Likewise.
* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
* testsuite/gas/i386/reloc32.d: Updated.
MIPS: Fix the encoding of immediates with microMIPS JALX The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation with microMIPS J/JAL/JALS instructions, however unlike the latters its encoded immediate argument is unusually shifted left by 2 rather than 1 in calculating the value used for the operation requested. We already handle this exception in `mips_elf_calculate_relocation' in LD, in a scenario where JALX is produced as a result of relaxing JAL for the purpose of making a cross-mode jump. We also get it right in the disassembler in `decode_micromips_operand'. What we don't correctly do however is processing microMIPS JALX produced by GAS from an assembly source, where a non-zero constant argument or a symbol reference with a non-zero in-place addend has been used. In this case the same calculation is made as for microMIPS J/JAL/JALS, causing the wrong encoding to be produced by GAS on making an object file, and then again by LD in the final link. The latter in particular causes the calculation, where the addend fits in the relocatable field, to produce different final addresses for the same source code depending on whether REL or RELA relocations are used. Correct these issues by special-casing microMIPS JALX in the places that have been previously missed. bfd/ * elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for microMIPS JALX. gas/ * config/tc-mips.c (append_insn): Correct the encoding of a constant argument for microMIPS JALX. (tc_gen_reloc): Correct the encoding of an in-place addend for microMIPS JALX. * testsuite/gas/mips/jalx-addend.d: New test. * testsuite/gas/mips/jalx-addend-n32.d: New test. * testsuite/gas/mips/jalx-addend-n64.d: New test. * testsuite/gas/mips/jalx-imm.d: New test. * testsuite/gas/mips/jalx-imm-n32.d: New test. * testsuite/gas/mips/jalx-imm-n64.d: New test. * testsuite/gas/mips/jalx-addend.s: New test source. * testsuite/gas/mips/jalx-imm.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-addend.d: New test. * testsuite/ld-mips-elf/jalx-addend-n32.d: New test. * testsuite/ld-mips-elf/jalx-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-20 14:32:19 +02:00
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (append_insn): Correct the encoding of a
constant argument for microMIPS JALX.
(tc_gen_reloc): Correct the encoding of an in-place addend for
microMIPS JALX.
* testsuite/gas/mips/jalx-addend.d: New test.
* testsuite/gas/mips/jalx-addend-n32.d: New test.
* testsuite/gas/mips/jalx-addend-n64.d: New test.
* testsuite/gas/mips/jalx-imm.d: New test.
* testsuite/gas/mips/jalx-imm-n32.d: New test.
* testsuite/gas/mips/jalx-imm-n64.d: New test.
* testsuite/gas/mips/jalx-addend.s: New test source.
* testsuite/gas/mips/jalx-imm.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c: Correct tab-after-space formatting mistakes
throughout.
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Remove casting away of
const.
* config/tc-arc.h (struct arc_flags): Make flgp field const.
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
appropriate.
(md_convert_frag): Likewise.
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
cached opcode to NULL when we reach a non-matching opcode.
* testsuite/gas/arc/asm-errors-2.d: New file.
* testsuite/gas/arc/asm-errors-2.err: New file.
* testsuite/gas/arc/asm-errors-2.s: New file.
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (struct cpu_type): Change the type of a field from
int to enum rx_cpu_types.
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-dlx.c (struct machine_it): change the type of a field from
int to bfd_reloc_code_real_type.
* config/tc-tic4x.c: Likewise.
2016-05-18 12:17:33 +02:00
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-v850.c (v850_target_arch): change type to enum
bfd_architecture.
* config/tc-v850.h (v850_target_arch): Likewise.
2016-05-18 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
allowed negative range.
* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
* testsuite/gas/ppc/power9.d: Update.
2016-05-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Force Thumb when
disassembling and stop skipping targets.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
* testsuite/gas/arm/archv8m-base.d: Also allow nops after the last
instruction for targets that have stronger alignment requirement.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main.d: Likewise.
* testsuite/gas/arm/archv8m.s: Add label.
* testsuite/gas/arm/archv8m-cmse.s: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise.
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32r.c (mach_table): Make static and const.
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-vax.c (flonum_gen2vax): Adjust prototype to match
definition.
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mn10300.c (md_begin): set linkrelax here instead of
defining it.
* config/tc-msp430.c (md_begin): Likewise.
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m68hc11.c (fixup8): Change variables type from int to
bfd_reloc_code_real_type where appropriate.
(fixup16): Likewise.
(fixup8_xg): Likewise.
2016-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-sh64.c (shmedia_check_limits): Constify `msg'.
2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <xxspltib>: Add additional operand tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-05-13 Alan Modra <amodra@gmail.com>
* config/obj-coff.c (weak_uniquify): Delete unused var.
use XNEW and related macros more Its a bit shorter and simpler than raw xmalloc. gas/ChangeLog: 2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * app.c (app_push): Use XNEW and related macros. * as.c (parse_args): Likewise. * cgen.c (make_right_shifted_expr): Likewise. (gas_cgen_tc_gen_reloc): Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff.c (stack_init): Likewise. (stack_push): Likewise. (coff_obj_symbol_new_hook): Likewise. (coff_obj_symbol_clone_hook): Likewise. (add_lineno): Likewise. (coff_frob_symbol): Likewise. * config/obj-elf.c (obj_elf_section_name): Likewise. (build_group_lists): Likewise. * config/obj-evax.c (evax_symbol_new_hook): Likewise. * config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise. * config/tc-aarch64.c (insert_reg_alias): Likewise. (find_or_make_literal_pool): Likewise. (add_to_lit_pool): Likewise. (fill_instruction_hash_table): Likewise. * config/tc-alpha.c (load_expression): Likewise. (emit_jsrjmp): Likewise. (s_alpha_ent): Likewise. (s_alpha_end): Likewise. (s_alpha_linkage): Likewise. (md_begin): Likewise. (tc_gen_reloc): Likewise. * config/tc-arc.c (arc_insert_opcode): Likewise. (arc_extcorereg): Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c (preprocess_reglist): Likewise. * config/tc-d10v.c: Likewise. * config/tc-frv.c (frv_insert_vliw_insn): Likewise. (frv_tomcat_shuffle): Likewise. * config/tc-h8300.c: Likewise. * config/tc-i370.c (i370_macro): Likewise. * config/tc-i386.c (lex_got): Likewise. (md_parse_option): Likewise. * config/tc-ia64.c (alloc_record): Likewise. (set_imask): Likewise. (save_prologue_count): Likewise. (dot_proc): Likewise. (dot_endp): Likewise. (ia64_frob_label): Likewise. (add_qp_imply): Likewise. (add_qp_mutex): Likewise. (mark_resource): Likewise. (dot_alias): Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. (s_save): Likewise. (mri_control_label): Likewise. (push_mri_control): Likewise. (build_mri_control_operand): Likewise. (s_mri_else): Likewise. (s_mri_break): Likewise. (s_mri_next): Likewise. (s_mri_for): Likewise. (s_mri_endw): Likewise. * config/tc-metag.c (create_mnemonic_htab): Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c (s_loc): Likewise. * config/tc-nds32.c (nds32_relax_hint): Likewise. * config/tc-nios2.c (nios2_insn_reloc_new): Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c (shmedia_frob_section_type): Likewise. * config/tc-sparc.c: Likewise. * config/tc-spu.c: Likewise. * config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise. (tic6x_start_unwind_section): Likewise. * config/tc-tilegx.c: Likewise. * config/tc-tilepro.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise. (new_resource_table): Likewise. (resize_resource_table): Likewise. (xtensa_create_trampoline_frag): Likewise. (xtensa_maybe_create_literal_pool_frag): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c (append_transition): Likewise. (append_condition): Likewise. (append_value_condition): Likewise. (append_constant_value_condition): Likewise. (append_literal_op): Likewise. (append_label_op): Likewise. (append_constant_op): Likewise. (append_field_op): Likewise. (append_user_fn_field_op): Likewise. (enter_opname_n): Likewise. (enter_opname): Likewise. (split_string): Likewise. (parse_insn_templ): Likewise. (clone_req_or_option_list): Likewise. (clone_req_option_list): Likewise. (parse_option_cond): Likewise. (parse_insn_pattern): Likewise. (parse_insn_repl): Likewise. (build_transition): Likewise. (build_transition_table): Likewise. * dw2gencfi.c (alloc_fde_entry): Likewise. (alloc_cfi_insn_data): Likewise. (cfi_add_CFA_remember_state): Likewise. (dot_cfi_escape): Likewise. (dot_cfi_fde_data): Likewise. (select_cie_for_fde): Likewise. * dwarf2dbg.c (dwarf2_directive_loc): Likewise. * ecoff.c (ecoff_add_bytes): Likewise. (ecoff_build_debug): Likewise. * input-scrub.c (input_scrub_push): Likewise. (input_scrub_begin): Likewise. (input_scrub_next_buffer): Likewise. * itbl-ops.c (append_insns_as_macros): Likewise. (alloc_entry): Likewise. (alloc_field): Likewise. * listing.c (listing_newline): Likewise. (listing_listing): Likewise. * macro.c (get_any_string): Likewise. (delete_macro): Likewise. * stabs.c (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * subsegs.c (subseg_change): Likewise. (subseg_get): Likewise. * symbols.c (define_dollar_label): Likewise. (symbol_relc_make_sym): Likewise. * write.c (write_relocs): Likewise.
2016-04-06 22:26:46 +02:00
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* app.c (app_push): Use XNEW and related macros.
* as.c (parse_args): Likewise.
* cgen.c (make_right_shifted_expr): Likewise.
(gas_cgen_tc_gen_reloc): Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff.c (stack_init): Likewise.
(stack_push): Likewise.
(coff_obj_symbol_new_hook): Likewise.
(coff_obj_symbol_clone_hook): Likewise.
(add_lineno): Likewise.
(coff_frob_symbol): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(build_group_lists): Likewise.
* config/obj-evax.c (evax_symbol_new_hook): Likewise.
* config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise.
* config/tc-aarch64.c (insert_reg_alias): Likewise.
(find_or_make_literal_pool): Likewise.
(add_to_lit_pool): Likewise.
(fill_instruction_hash_table): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(emit_jsrjmp): Likewise.
(s_alpha_ent): Likewise.
(s_alpha_end): Likewise.
(s_alpha_linkage): Likewise.
(md_begin): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (arc_insert_opcode): Likewise.
(arc_extcorereg): Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c (preprocess_reglist): Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-frv.c (frv_insert_vliw_insn): Likewise.
(frv_tomcat_shuffle): Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-i370.c (i370_macro): Likewise.
* config/tc-i386.c (lex_got): Likewise.
(md_parse_option): Likewise.
* config/tc-ia64.c (alloc_record): Likewise.
(set_imask): Likewise.
(save_prologue_count): Likewise.
(dot_proc): Likewise.
(dot_endp): Likewise.
(ia64_frob_label): Likewise.
(add_qp_imply): Likewise.
(add_qp_mutex): Likewise.
(mark_resource): Likewise.
(dot_alias): Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c (m68k_frob_label): Likewise.
(s_save): Likewise.
(mri_control_label): Likewise.
(push_mri_control): Likewise.
(build_mri_control_operand): Likewise.
(s_mri_else): Likewise.
(s_mri_break): Likewise.
(s_mri_next): Likewise.
(s_mri_for): Likewise.
(s_mri_endw): Likewise.
* config/tc-metag.c (create_mnemonic_htab): Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mmix.c (s_loc): Likewise.
* config/tc-nds32.c (nds32_relax_hint): Likewise.
* config/tc-nios2.c (nios2_insn_reloc_new): Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c (shmedia_frob_section_type): Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-spu.c: Likewise.
* config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise.
(tic6x_start_unwind_section): Likewise.
* config/tc-tilegx.c: Likewise.
* config/tc-tilepro.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise.
(new_resource_table): Likewise.
(resize_resource_table): Likewise.
(xtensa_create_trampoline_frag): Likewise.
(xtensa_maybe_create_literal_pool_frag): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c (append_transition): Likewise.
(append_condition): Likewise.
(append_value_condition): Likewise.
(append_constant_value_condition): Likewise.
(append_literal_op): Likewise.
(append_label_op): Likewise.
(append_constant_op): Likewise.
(append_field_op): Likewise.
(append_user_fn_field_op): Likewise.
(enter_opname_n): Likewise.
(enter_opname): Likewise.
(split_string): Likewise.
(parse_insn_templ): Likewise.
(clone_req_or_option_list): Likewise.
(clone_req_option_list): Likewise.
(parse_option_cond): Likewise.
(parse_insn_pattern): Likewise.
(parse_insn_repl): Likewise.
(build_transition): Likewise.
(build_transition_table): Likewise.
* dw2gencfi.c (alloc_fde_entry): Likewise.
(alloc_cfi_insn_data): Likewise.
(cfi_add_CFA_remember_state): Likewise.
(dot_cfi_escape): Likewise.
(dot_cfi_fde_data): Likewise.
(select_cie_for_fde): Likewise.
* dwarf2dbg.c (dwarf2_directive_loc): Likewise.
* ecoff.c (ecoff_add_bytes): Likewise.
(ecoff_build_debug): Likewise.
* input-scrub.c (input_scrub_push): Likewise.
(input_scrub_begin): Likewise.
(input_scrub_next_buffer): Likewise.
* itbl-ops.c (append_insns_as_macros): Likewise.
(alloc_entry): Likewise.
(alloc_field): Likewise.
* listing.c (listing_newline): Likewise.
(listing_listing): Likewise.
* macro.c (get_any_string): Likewise.
(delete_macro): Likewise.
* stabs.c (generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
* subsegs.c (subseg_change): Likewise.
(subseg_get): Likewise.
* symbols.c (define_dollar_label): Likewise.
(symbol_relc_make_sym): Likewise.
* write.c (write_relocs): Likewise.
use xstrdup, xmemdup0 and concat more gas/ChangeLog: 2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/obj-coff.c (obj_coff_def): Simplify string copying. (weak_name2altname): Likewise. (weak_uniquify): Likewise. (obj_coff_section): Likewise. (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_section_name): Likewise. (obj_elf_init_stab_section): Likewise. * config/obj-evax.c (evax_shorten_name): Likewise. * config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise. * config/tc-aarch64.c (create_register_alias): Likewise. * config/tc-alpha.c (load_expression): Likewise. (s_alpha_file): Likewise. (s_alpha_section_name): Likewise. (tc_gen_reloc): Likewise. * config/tc-arc.c (md_assemble): Likewise. * config/tc-arm.c (create_neon_reg_alias): Likewise. (start_unwind_section): Likewise. * config/tc-hppa.c (pa_build_unwind_subspace): Likewise. (hppa_elf_mark_end_of_function): Likewise. * config/tc-nios2.c (nios2_modify_arg): Likewise. (nios2_negate_arg): Likewise. * config/tc-rx.c (rx_section): Likewise. * config/tc-sh64.c (sh64_consume_datalabel): Likewise. * config/tc-tic30.c (tic30_find_parallel_insn): Likewise. * config/tc-tic54x.c (tic54x_include): Likewise. (tic54x_macro_info): Likewise. (subsym_get_arg): Likewise. (subsym_substitute): Likewise. (tic54x_start_line_hook): Likewise. * config/tc-xtensa.c (xtensa_literal_prefix): Likewise. (xg_reverse_shift_count): Likewise. * config/xtensa-relax.c (enter_opname_n): Likewise. (split_string): Likewise. * dwarf2dbg.c (get_filenum): Likewise. (process_entries): Likewise. * expr.c (operand): Likewise. * itbl-ops.c (alloc_entry): Likewise. * listing.c (listing_message): Likewise. (listing_title): Likewise. * macro.c (check_macro): Likewise. * stabs.c (s_xstab): Likewise. * symbols.c (symbol_relc_make_expr): Likewise. * write.c (compress_debug): Likewise.
2016-03-28 11:49:15 +02:00
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-coff.c (obj_coff_def): Simplify string copying.
(weak_name2altname): Likewise.
(weak_uniquify): Likewise.
(obj_coff_section): Likewise.
(obj_coff_init_stab_section): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(obj_elf_init_stab_section): Likewise.
* config/obj-evax.c (evax_shorten_name): Likewise.
* config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise.
* config/tc-aarch64.c (create_register_alias): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(s_alpha_file): Likewise.
(s_alpha_section_name): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (md_assemble): Likewise.
* config/tc-arm.c (create_neon_reg_alias): Likewise.
(start_unwind_section): Likewise.
* config/tc-hppa.c (pa_build_unwind_subspace): Likewise.
(hppa_elf_mark_end_of_function): Likewise.
* config/tc-nios2.c (nios2_modify_arg): Likewise.
(nios2_negate_arg): Likewise.
* config/tc-rx.c (rx_section): Likewise.
* config/tc-sh64.c (sh64_consume_datalabel): Likewise.
* config/tc-tic30.c (tic30_find_parallel_insn): Likewise.
* config/tc-tic54x.c (tic54x_include): Likewise.
(tic54x_macro_info): Likewise.
(subsym_get_arg): Likewise.
(subsym_substitute): Likewise.
(tic54x_start_line_hook): Likewise.
* config/tc-xtensa.c (xtensa_literal_prefix): Likewise.
(xg_reverse_shift_count): Likewise.
* config/xtensa-relax.c (enter_opname_n): Likewise.
(split_string): Likewise.
* dwarf2dbg.c (get_filenum): Likewise.
(process_entries): Likewise.
* expr.c (operand): Likewise.
* itbl-ops.c (alloc_entry): Likewise.
* listing.c (listing_message): Likewise.
(listing_title): Likewise.
* macro.c (check_macro): Likewise.
* stabs.c (s_xstab): Likewise.
* symbols.c (symbol_relc_make_expr): Likewise.
* write.c (compress_debug): Likewise.
2016-05-12 Nick Clifton <nickc@redhat.com>
PR target/20068
* testsuite/gas/arm/pr20068.d: Use correct regexp syntax.
2016-05-11 Nick Clifton <nickc@redhat.com>
PR target/20068
* testsuite/gas/arm/pr20068.d: Adjust expected output to allow for
big endian ARM configurations.
2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (options): Add OPTION_DSPR3 and
OPTION_NO_DSPR3.
(md_longopts): Likewise.
(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
(mips_ases): Define availability for DSPr3.
(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
* doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
formatting.
* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
.set nodspr3. Fix -mdspr2 formatting.
* testsuite/gas/mips/mips32-dspr3.d: New file.
* testsuite/gas/mips/mips32-dspr3.s: Likewise.
* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
2016-05-11 Nick Clifton <nickc@redhat.com>
PR target/20068
* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
to the pool uses O_constant.
* testsuite/gas/arm/pr20068.s: New test.
* testsuite/gas/arm/pr20068.d: Test driver.
2016-05-11 Nick Clifton <nickc@redhat.com>
2016-05-11 10:06:58 +02:00
* testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
* testsuite/gas/i386/i386.exp: Run RDPID tests.
* testsuite/gas/i386/prefix.d: Adjust.
* testsuite/gas/i386/rdpid.s: New test.
* testsuite/gas/i386/rdpid.d: Ditto.
* testsuite/gas/i386/rdpid-intel.d: Ditto.
* testsuite/gas/i386/x86-64-rdpid.s: Ditto.
* testsuite/gas/i386/x86-64-rdpid.d: Ditto.
* testsuite/gas/i386/x86-64-rdpid-intel.d: Ditto.
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
* config/tc-i386.c (cpu_arch): Add RDPID.
* doc/c-i386.texi: Document RDPID.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
set branch type of a symbol.
Add support for ARMv8-M Mainline with DSP extension 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (elf32_arm_merge_eabi_attributes): Add merging logic for Tag_DSP_extension. binutils/ * readelf.c (display_arm_attribute): Add output for Tag_DSP_extension. (arm_attr_public_tags): Define DSP_extension attribute. gas/ * NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions. * config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP instructions. (arm_extensions): Add dsp extension for ARMv8-M Mainline. (aeabi_set_public_attributes): Memorize the feature bits of the architecture selected for Tag_CPU_arch. Use it to set Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension. (arm_convert_symbolic_attribute): Define Tag_DSP_extension. * testsuite/gas/arm/arch7em-bad.d: Rename to ... * testsuite/gas/arm/arch7em-bad-1.d: This. * testsuite/gas/arm/arch7em-bad-2.d: New file. * testsuite/gas/arm/arch7em-bad-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise. include/ * elf/arm.h (Tag_DSP_extension): Define. ld/ * testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New test. * testsuite/ld-arm/attr-merge-10b-dsp.s: New file. * testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10 16:15:15 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions.
* config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP
instructions.
(arm_extensions): Add dsp extension for ARMv8-M Mainline.
(aeabi_set_public_attributes): Memorize the feature bits of the
architecture selected for Tag_CPU_arch. Use it to set
Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension.
(arm_convert_symbolic_attribute): Define Tag_DSP_extension.
* testsuite/gas/arm/arch7em-bad.d: Rename to ...
* testsuite/gas/arm/arch7em-bad-1.d: This.
* testsuite/gas/arm/arch7em-bad-2.d: New file.
* testsuite/gas/arm/arch7em-bad-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise.
* testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (struct arm_option_extension_value_table): Make
allowed_archs an array with 2 entries.
(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
(arm_extensions): Use separate entries in allowed_archs when several
archs are allowed to use an extension and change ARCH_ANY in
ARM_ARCH_NONE in allowed_archs.
(arm_parse_extension): Check that, for each allowed_archs entry, all
bits are set in the current architecture, ignoring ARM_ANY entries.
(s_arm_arch_extension): Likewise.
Add support for ARMv8-M security extensions instructions 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
2016-05-10 16:01:53 +02:00
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
shared with a non M profile architecture.
(do_rn): New function.
(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
than arm_ext_v8m.
(v7m_psrs): Add ARMv8-M security extensions new special registers.
(insns): Add ARMv8-M Security Extensions instructions.
(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
arm_ext_v8m_m to decide the profile and the Thumb ISA.
* testsuite/gas/arm/archv8m-cmse.s: New file.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/any-cmse.d: Likewise.
* testsuite/gas/arm/any-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
2016-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED.
(fpu_arch_vfp_v3): Likewise.
(fpu_arch_neon_v1): Likewise.
(arm_arch_full): Likewise.
(parse_neon_el_struct_list): Initialize fields of firsttype.
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
(arc_extinsn): Handle new introduced syntax.
* testsuite/gas/arc/textinsn1op.d: New file.
* testsuite/gas/arc/textinsn1op.s: Likewise.
* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.
2016-05-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* testsuite/gas/lns/lns.exp: Add avr to list of targets using
DW_LNS_fixed_advance_pc.
2016-04-27 Alan Modra <amodra@gmail.com>
* as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define.
(xmemdup0): New inline function.
MIPS/GAS: Fix an ISA override not lifting ABI restrictions Correct a regression introduced with commit 919731affbef ("Add MIPS .module directive") causing code like: .set mips3 dli $2, 0x9000000080000000 to fail assembly with the following error message produced: Error: number (0x9000000080000000) larger than 32 bits if built with `mips3' selected as the global ISA (e.g. `-march=mips3'). This is because a `.set' directive doing an ISA override does not lift the ABI restriction on register sizes if the ISA remains unchanged. Previously the directive always set register sizes from the ISA chosen, which is what some code expects. Restore the old semantics then. gas/ * config/tc-mips.c (code_option_type): New enum. (parse_code_option): Return status indicating option type. (s_mipsset): Update `parse_code_option' call site accordingly. Always set register sizes from the ISA with ISA overrides. (s_module): Update `parse_code_option' call site. * testsuite/gas/mips/isa-override-1.d: New test. * testsuite/gas/mips/micromips@isa-override-1.d: New test. * testsuite/gas/mips/mips1@isa-override-1.d: New test. * testsuite/gas/mips/mips2@isa-override-1.d: New test. * testsuite/gas/mips/mips32@isa-override-1.d: New test. * testsuite/gas/mips/mips32r2@isa-override-1.d: New test. * testsuite/gas/mips/mips32r3@isa-override-1.d: New test. * testsuite/gas/mips/mips32r5@isa-override-1.d: New test. * testsuite/gas/mips/mips32r6@isa-override-1.d: New test. * testsuite/gas/mips/mips64r2@isa-override-1.d: New test. * testsuite/gas/mips/mips64r3@isa-override-1.d: New test. * testsuite/gas/mips/mips64r5@isa-override-1.d: New test. * testsuite/gas/mips/mips64r6@isa-override-1.d: New test. * testsuite/gas/mips/r3000@isa-override-1.d: New test. * testsuite/gas/mips/r3900@isa-override-1.d: New test. * testsuite/gas/mips/r5900@isa-override-1.d: New test. * testsuite/gas/mips/octeon@isa-override-1.d: New test. * testsuite/gas/mips/octeon3@isa-override-1.d: New test. * testsuite/gas/mips/isa-override-2.l: New list test. * testsuite/gas/mips/mips1@isa-override-2.l: New list test. * testsuite/gas/mips/mips2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r3@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r5@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r6@isa-override-2.l: New list test. * testsuite/gas/mips/r3000@isa-override-2.l: New list test. * testsuite/gas/mips/r3900@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-1.l: New stderr output. * testsuite/gas/mips/isa-override-1.s: New test source. * testsuite/gas/mips/r5900@isa-override-1.s: New test source. * testsuite/gas/mips/isa-override-2.s: New test source. * testsuite/gas/mips/mips1@isa-override-2.s: New test source. * testsuite/gas/mips/mips2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: New test source. * testsuite/gas/mips/r3000@isa-override-2.s: New test source. * testsuite/gas/mips/r3900@isa-override-2.s: New test source. * testsuite/gas/mips/octeon3@isa-override-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-22 02:04:52 +02:00
2016-04-22 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (code_option_type): New enum.
(parse_code_option): Return status indicating option type.
(s_mipsset): Update `parse_code_option' call site accordingly.
Always set register sizes from the ISA with ISA overrides.
(s_module): Update `parse_code_option' call site.
* testsuite/gas/mips/isa-override-1.d: New test.
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
* testsuite/gas/mips/isa-override-2.l: New list test.
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/isa-override-1.s: New test source.
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
* testsuite/gas/mips/isa-override-2.s: New test source.
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
update many old style function definitions This includes regenerating a bunch of files in opcodes/ with trunk cgen. gprof/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * basic_blocks.c: Update old style function definitions. * cg_arcs.c: Likewise. * cg_print.c: Likewise. * gen-c-prog.awk: Likewise. * gmon_io.c: Likewise. * hertz.c: Likewise. * hist.c: Likewise. * sym_ids.c: Likewise. bfd/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cache.c: Update old style function definitions. * elf32-m68k.c: Likewise. * elf64-mmix.c: Likewise. * stab-syms.c: Likewise. opcodes/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * alpha-dis.c: Regenerate. * crx-dis.c: Likewise. * disassemble.c: Likewise. * epiphany-opc.c: Likewise. * fr30-opc.c: Likewise. * frv-opc.c: Likewise. * ip2k-opc.c: Likewise. * iq2000-opc.c: Likewise. * lm32-opc.c: Likewise. * lm32-opinst.c: Likewise. * m32c-opc.c: Likewise. * m32r-opc.c: Likewise. * m32r-opinst.c: Likewise. * mep-opc.c: Likewise. * mt-opc.c: Likewise. * or1k-opc.c: Likewise. * or1k-opinst.c: Likewise. * tic80-opc.c: Likewise. * xc16x-opc.c: Likewise. * xstormy16-opc.c: Likewise. ld/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * emultempl/scoreelf.em: Likewise. binutils/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * resres.c: Likewise. gas/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cgen.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-rl78.c: Likewise.
2016-04-14 00:30:46 +02:00
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cgen.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-rl78.c: Likewise.
2016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
-mcpu. Add cross reference to .cpu directive from -mcpu option.
(ARC Directives): Add NPS400 to .cpu directive list.
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-6.d: New file.
* testsuite/gas/arc/nps400-6.s: New file.
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-4.d: New file.
* testsuite/gas/arc/nps400-4.s: New file.
* testsuite/gas/arc/nps400-5.d: New file.
* testsuite/gas/arc/nps400-5.s: New file.
2016-04-19 Martin Galvan <martin.galvan@tallertechnologies.com>
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve
documentation.
2016-04-17 Andrew Burgess <andrew.burgess@embecosm.com>
Revert prevous change.
* config/tc-arc.c (arc_option): Make .cpu directive
case-sensitive again.
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_option): Make .cpu directive
case-insensitive.
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mips.c (md_begin): Remove useless assignment.
2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.in: Regenerated with automake 1.11.6.
* aclocal.m4: Likewise.
* doc/Makefile.in: Likewise.
2016-04-15 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nios2.c (nios2_as_options): Make file static.
* config/tc-ppc.c (toc_reloc_ypes): Likewise.
* config/tc-sparc.c (native_op_table): Likewise.
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32c.c (M32C_Macros): Remove.
* config/tc-msp430.c (option_numbers): Likewise.
arc/nps400 : New cmem instructions and associated relocation Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-30 01:02:19 +02:00
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/add_s-err.s: Update target pattern.
* testsuite/gas/arc/warn.s: Likewise.
* testsuite/gas/elf/elf.exp: Run test for arc.
Fix copying Solaris binaries with objcopy. PR target/19938 bfd * elf-bbfd.h (struct elf_backend_data): New field: elf_strtab_flags. New field: elf_backend_set_special_section_info_and_link * elfxx-target.h (elf_backend_strtab_flags): Define if not already defined. (elf_backend_set_special_section_info_and_link): Define if not already defined. (elfNN_bed): Use elf_backend_set_special_section_info_and_link and elf_backend_strtab_flags macros to initialise fields in structure. * elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS being set even if SHF_MERGE is not set. (elf_fake_sections): Likewise. (section_match): New function. Matches two ELF sections based upon fixed characteristics. (find_link): New function. Locates a section in a BFD that matches a section in a different BFD. (_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link fields of reserved sections. (bfd_elf_compute_section_file_positions): Set the flags for the .shstrtab section based upon the elf_strtab_flags field in the elf_backend_data structure. (swap_out_syms): Likewise for the .strtab section. * elflink.c (bfd_elf_final_link): Set the flags for the .strtab section based upon the elf_strtab_flags field in the elf_backend_data structure. * elf32-i386.c (elf32_i386_set_special_info_link): New function. (elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris targets. (elf_backend_set_special_section_info_and_link): Define for Solaris targets. * elf32-sparc.c: Likewise. * elf64-x86-64.c: Likewise. binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/readelf.s: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-14 13:04:09 +02:00
2016-04-14 Nick Clifton <nickc@redhat.com>
PR target/19938
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
sections possibly having the SHF_STRINGS flag bit set.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (mach_type_specified_p): Change type to
bfd_boolean.
(arc_option): Set private flags when parsing cpu pseudo-op.
(md_parse_option): Set mach_type_specified_p to TRUE.
2016-04-13 16:10:48 +02:00
2016-04-13 Nick Clifton <nickc@redhat.com>
PR target/19937
* testsuite/gas/v850/pr19937.s: New test.
* testsuite/gas/v850/pr19937.d: New test control file.
* testsuite/gas/v850/basic.exp: Run the new test.
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the target is a weak symbol.
(relaxed_micromips_32bit_branch_length): Likewise.
(relaxed_micromips_16bit_branch_length): Likewise.
* testsuite/gas/mips/branch-weak-1.d: New test.
* testsuite/gas/mips/branch-weak-2.d: New test.
* testsuite/gas/mips/branch-weak-3.d: New test.
* testsuite/gas/mips/branch-weak-4.d: New test.
* testsuite/gas/mips/branch-weak-5.d: New test.
* testsuite/gas/mips/branch-weak.l: New stderr output.
* testsuite/gas/mips/branch-weak.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS: Relax branches to symbols resolved at link time Where branch relaxation is enabled emit the long sequence for branches whose distance cannot be determined, i.e. to symbols that are undefined or in a different segment. These symbols are only resolved at link time and therefore the longer sequence ensures the branch target is in range, which cannot be guaranteed with a direct branch. This is the opposite to the current implementation, originally proposed here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The proposal was then extensively discussed before the final version was posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html> and eventually committed: commit 4a6a3df43dbb37853a7b88b10ae97d9ec5daf987 Author: Alexandre Oliva <aoliva@redhat.com> Date: Sat Oct 12 05:23:33 2002 +0000 The case considered here was not commented in the review however and the original version remains. With branch relaxation enabled it makes more sense to do it consistently, so that all code impure with respect to branch distances can be linked. Direct branches are still produced for the cases concerned where branch relaxation is disabled, which is the default. gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the distance cannot be determined. (relaxed_micromips_32bit_branch_length): Likewise. * testsuite/gas/mips/branch-extern-1.d: New test. * testsuite/gas/mips/branch-extern-2.d: New test. * testsuite/gas/mips/branch-extern-3.d: New test. * testsuite/gas/mips/branch-extern-4.d: New test. * testsuite/gas/mips/branch-extern.l: New stderr output. * testsuite/gas/mips/branch-extern.s: New test source. * testsuite/gas/mips/branch-section-1.d: New test. * testsuite/gas/mips/branch-section-2.d: New test. * testsuite/gas/mips/branch-section-3.d: New test. * testsuite/gas/mips/branch-section-4.d: New test. * testsuite/gas/mips/branch-section.l: New stderr output. * testsuite/gas/mips/branch-section.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 01:20:35 +02:00
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the distance cannot be determined.
(relaxed_micromips_32bit_branch_length): Likewise.
* testsuite/gas/mips/branch-extern-1.d: New test.
* testsuite/gas/mips/branch-extern-2.d: New test.
* testsuite/gas/mips/branch-extern-3.d: New test.
* testsuite/gas/mips/branch-extern-4.d: New test.
* testsuite/gas/mips/branch-extern.l: New stderr output.
* testsuite/gas/mips/branch-extern.s: New test source.
* testsuite/gas/mips/branch-section-1.d: New test.
* testsuite/gas/mips/branch-section-2.d: New test.
* testsuite/gas/mips/branch-section-3.d: New test.
* testsuite/gas/mips/branch-section-4.d: New test.
* testsuite/gas/mips/branch-section.l: New stderr output.
* testsuite/gas/mips/branch-section.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add support for .extCondCode, .extCoreRegister and .extAuxRegister. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-06 16:08:04 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (arc_flags): Delete code, add flgp.
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/noargs_a7.d: New file.
* testsuite/gas/arc/noargs_a7.s: Likewise.
* testsuite/gas/arc/noargs_hs.d: Likewise.
* testsuite/gas/arc/noargs_hs.s: Likewise.
Add support for .extInstruction pseudo-op. gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
(arc_adjust_symtab): New function.
* config/tc-arc.h (ARC_FLAG_AUX): Define.
(obj_adjust_symtab): Likewise.
* testsuite/gas/arc/taux.d: New file.
* testsuite/gas/arc/taux.s: Likewise.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (s_option): Sanitize `.option picX'
pseudo-op.
* testsuite/gas/mips/option-pic-1.d: New test.
* testsuite/gas/mips/option-pic-2.l: New list test.
* testsuite/gas/mips/option-pic-1.s: New test source.
* testsuite/gas/mips/option-pic-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
PIC.
* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (can_swap_branch_p): Correct call formatting.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* messages.c (as_bad): Fix a typo in description.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_check_options): Unify messages.
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_check_options): Use `opts->isa'
consistently.
2016-04-08 Nick Clifton <nickc@redhat.com>
PR target/19910
* testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with
COFF and AOUT sparc targets.
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7.
* testsuite/gas/arc/nps400-2.d: New file.
* testsuite/gas/arc/nps400-2.s: New file.
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
structure.
(arc_opcode_hash_entry_iterator_init): New function.
(arc_opcode_hash_entry_iterator_next): New function.
(find_opcode_match): Iterate over all arc_opcode entries
referenced by the arc_opcode_hash_entry passed in as a parameter.
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_find_opcode): Now returns
arc_opcode_hash_entry pointer.
(find_opcode_match): Update argument type, extract arc_opcode from
incoming arc_opcode_hash_entry.
(find_special_case_pseudo): Update return type.
(find_special_case_flag): Update return type.
(find_special_case): Update return type.
(assemble_tokens): Lookup arc_opcode_hash_entry based on
instruction mnemonic, then use find_opcode_match to identify
specific arc_opcode.
2016-03-28 15:27:43 +02:00
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
(arc_find_opcode): New function.
(find_special_case_pseudo): Use arc_find_opcode.
(find_special_case_flag): Likewise.
(assemble_tokens): Likewise.
(md_begin): Build hash using struct arc_opcode_hash_entry.
2016-04-07 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (arc_option): Prepare string for automatic
translation.
(declare_register): Likewise.
2016-04-06 James Greenhalgh <james.greenhalgh@arm.com>
* doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE.
Correct entry for RDMA. Alpha sort entries.
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (tokenize_flags): Allow greater range of
characters into flag names.
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
new de_fault label.
(preprocess_operands): Delete.
(assemble_tokens): Remove call to preprocess_operands.
2016-04-07 Nick Clifton <nickc@redhat.com>
PR gas/19910
* config/tc-sparc.c (sparc_ip): Report an error if the expression
inside a %-macro could not be fully parsed.
* expr.c (integer_constant): Accept and ignore U suffixes to
integers.
(operand): When a missing closing parenthesis is encountered,
report the character that was found instead.
* testsuite/gas/mips/tls-ill.l: Update expected error message.
* testsuite/gas/sparc/pr19910-1.d: New test driver.
* testsuite/gas/sparc/pr19910-1.s: New test.
* testsuite/gas/sparc/pr19910-2.l: Expected error output.
* testsuite/gas/sparc/pr19910-2.s: New test.
* testsuite/gas/sparc/sparc.exp: Run the new tests.
2016-04-06 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding
an EINT instruction. Warn/fix as necessary.
* testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP.
* testsuite/gas/msp430/bad.l: Update expected messages.
2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-1.d: Update expected results.
* testsuite/gas/arc/nps400-1.s: Additional test cases.
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (is_code_density_p): Compare directly the
subclass field.
(is_spfp_p, is_dpfp_p, is_spfp_p): Define.
(check_cpu_feature): New function.
(find_opcode_match): Use check_cpu_feature function.
(preprocess_operands): Likewise.
(md_parse_option): Use mfpuda, mdpfp, mspfp options.
* testsuite/gas/arc/tdpfp.d: New file.
* testsuite/gas/arc/tfpuda.d: Likewise.
* testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New tests.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results.
* testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results.
* testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source.
* testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase.
2016-04-07 15:43:14 +02:00
* testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise
for Thumb.
* testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results.
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for
JUMP instructions type.
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/relocs-errors.d: New file.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19909
* config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding
only if i.disp_encoding != disp_encoding_32bit.
* gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32.
* gas/testsuite/gas/i386/x86-64-disp32.s: Likewise.
* gas/testsuite/gas/i386/disp32.d: Updated.
* gas/testsuite/gas/i386/x86-64-disp32.d: Likewise.
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19498
* testsuite/gas/i386/i386.exp: Run pr19498.
* testsuite/gas/i386/pr19498.d: New file.
* testsuite/gas/i386/pr19498.s: Likewise.
2016-04-04 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h: Include 'opcode/arc.h'.
(MAX_INSN_ARGS): Delete.
(MAX_INSN_FLGS): Delete.
2016-04-04 Alan Modra <amodra@gmail.com>
PR 19498
* symbols.c (resolve_symbol_value): Clear sy_resolving on exit
from function on all paths that set sy_resolving.
use XNEW and related macros more gas/ChangeLog: 2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * app.c (app_push): use XNEW macro. * as.c: Likewise. * config/obj-elf.c (obj_elf_change_section): Likewise. (elf_copy_symbol_attributes): Likewise. (obj_elf_size): Likewise. (build_group_lists): Likewise. * config/tc-aarch64.c (add_operand_error_record): Likewise. (md_assemble): Likewise. (tc_gen_reloc): Likewise. (get_upper_str): Likewise. (aarch64_parse_features): Likewise. * config/tc-arm.c (insert_reg_alias): Likewise. (insert_neon_reg_alias): Likewise. (find_or_make_literal_pool): Likewise. (s_arm_elf_cons): Likewise. (add_unwind_opcode): Likewise. (arm_parse_extension): Likewise. * config/tc-avr.c (create_record_for_frag): Likewise. * config/tc-crx.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c (s_proc): Likewise. * config/tc-ft32.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c (pa_proc): Likewise. (create_new_space): Likewise. (create_new_subspace): Likewise. * config/tc-i860.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-iq2000.c (iq2000_add_macro): Likewise. (iq2000_record_hi16): Likewise. * config/tc-m32c.c (m32c_indirect_operand): Likewise. * config/tc-m32r.c (debug_sym): Likewise. (m32r_record_hi16): Likewise. * config/tc-m68k.c (m68k_ip): Likewise. (md_begin): Likewise. * config/tc-mcore.c: Likewise. * config/tc-microblaze.c (check_got): Likewise. * config/tc-mips.c (append_insn): Likewise. (s_mipsset): Likewise. (mips_record_label): Likewise. (s_mips_end): Likewise. * config/tc-mmix.c (mmix_frob_file): Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-moxie.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise. * config/tc-ns32k.c: Likewise. * config/tc-or1k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-pj.c (fake_opcode): Likewise. * config/tc-ppc.c (ppc_apuinfo_section_add): Likewise. (ppc_macro): Likewise. (ppc_dwsect): Likewise. (ppc_machine): Likewise. * config/tc-rl78.c (rl78_frag_init): Likewise. * config/tc-rx.c (rx_frag_init): Likewise. * config/tc-s390.c (s390_lit_suffix): Likewise. (s390_machine): Likewise. (s390_machinemode): Likewise. * config/tc-score.c (s3_insert_reg): Likewise. (s3_gen_reloc): Likewise. * config/tc-score7.c (s7_insert_reg): Likewise. (s7_gen_reloc): Likewise. * config/tc-tic30.c (tic30_operand): Likewise. * config/tc-tic4x.c (tic4x_inst_make): Likewise. * config/tc-tic54x.c (stag_add_field): Likewise. (tic54x_struct): Likewise. (tic54x_space): Likewise. (tic54x_field): Likewise. (tic54x_mlib): Likewise. (subsym_substitute): Likewise. * config/tc-tic6x.c (tic6x_frob_label): Likewise. * config/tc-vax.c: Likewise. * config/tc-xc16x.c: Likewise. * config/tc-xtensa.c (xtensa_add_insn_label): Likewise. (directive_push): Likewise. (xtensa_begin_directive): Likewise. (tokenize_arguments): Likewise. (xtensa_add_literal_sym): Likewise. (new_resource_table): Likewise. (resize_resource_table): Likewise. (emit_single_op): Likewise. (xtensa_create_trampoline_frag): Likewise. (xtensa_maybe_create_literal_pool_frag): Likewise. (xtensa_add_config_info): Likewise. (xtensa_realloc_fixup_cache): Likewise. (add_subseg_info): Likewise. (cache_literal_section): Likewise. (add_xt_block_frags): Likewise. (add_xt_prop_frags): Likewise. (init_op_placement_info_table): Likewise. (build_section_rename): Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * depend.c (register_dependency): Likewise. * dwarf2dbg.c (get_line_subseg): Likewise. (dwarf2_gen_line_info_1): Likewise. (get_filenum): Likewise. * ecoff.c (allocate_scope): Likewise. (allocate_vlinks): Likewise. (allocate_shash): Likewise. (allocate_thash): Likewise. (allocate_tag): Likewise. (allocate_forward): Likewise. (allocate_thead): Likewise. (allocate_lineno_list): Likewise. * expr.c (make_expr_symbol): Likewise. * hash.c (hash_new_sized): Likewise. * input-file.c (input_file_push): Likewise. * listing.c (file_info): Likewise. (listing_newline): Likewise. * macro.c (new_formal): Likewise. (define_macro): Likewise. * remap.c (add_debug_prefix_map): Likewise. * symbols.c (symbol_find_noref): Likewise. (define_dollar_label): Likewise. (fb_label_instance_inc): Likewise. (symbol_relc_make_value): Likewise.
2016-04-01 15:26:30 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* app.c (app_push): use XNEW macro.
* as.c: Likewise.
* config/obj-elf.c (obj_elf_change_section): Likewise.
(elf_copy_symbol_attributes): Likewise.
(obj_elf_size): Likewise.
(build_group_lists): Likewise.
* config/tc-aarch64.c (add_operand_error_record): Likewise.
(md_assemble): Likewise.
(tc_gen_reloc): Likewise.
(get_upper_str): Likewise.
(aarch64_parse_features): Likewise.
* config/tc-arm.c (insert_reg_alias): Likewise.
(insert_neon_reg_alias): Likewise.
(find_or_make_literal_pool): Likewise.
(s_arm_elf_cons): Likewise.
(add_unwind_opcode): Likewise.
(arm_parse_extension): Likewise.
* config/tc-avr.c (create_record_for_frag): Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c (s_proc): Likewise.
* config/tc-ft32.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c (pa_proc): Likewise.
(create_new_space): Likewise.
(create_new_subspace): Likewise.
* config/tc-i860.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-iq2000.c (iq2000_add_macro): Likewise.
(iq2000_record_hi16): Likewise.
* config/tc-m32c.c (m32c_indirect_operand): Likewise.
* config/tc-m32r.c (debug_sym): Likewise.
(m32r_record_hi16): Likewise.
* config/tc-m68k.c (m68k_ip): Likewise.
(md_begin): Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-microblaze.c (check_got): Likewise.
* config/tc-mips.c (append_insn): Likewise.
(s_mipsset): Likewise.
(mips_record_label): Likewise.
(s_mips_end): Likewise.
* config/tc-mmix.c (mmix_frob_file): Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-moxie.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-or1k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-pj.c (fake_opcode): Likewise.
* config/tc-ppc.c (ppc_apuinfo_section_add): Likewise.
(ppc_macro): Likewise.
(ppc_dwsect): Likewise.
(ppc_machine): Likewise.
* config/tc-rl78.c (rl78_frag_init): Likewise.
* config/tc-rx.c (rx_frag_init): Likewise.
* config/tc-s390.c (s390_lit_suffix): Likewise.
(s390_machine): Likewise.
(s390_machinemode): Likewise.
* config/tc-score.c (s3_insert_reg): Likewise.
(s3_gen_reloc): Likewise.
* config/tc-score7.c (s7_insert_reg): Likewise.
(s7_gen_reloc): Likewise.
* config/tc-tic30.c (tic30_operand): Likewise.
* config/tc-tic4x.c (tic4x_inst_make): Likewise.
* config/tc-tic54x.c (stag_add_field): Likewise.
(tic54x_struct): Likewise.
(tic54x_space): Likewise.
(tic54x_field): Likewise.
(tic54x_mlib): Likewise.
(subsym_substitute): Likewise.
* config/tc-tic6x.c (tic6x_frob_label): Likewise.
* config/tc-vax.c: Likewise.
* config/tc-xc16x.c: Likewise.
* config/tc-xtensa.c (xtensa_add_insn_label): Likewise.
(directive_push): Likewise.
(xtensa_begin_directive): Likewise.
(tokenize_arguments): Likewise.
(xtensa_add_literal_sym): Likewise.
(new_resource_table): Likewise.
(resize_resource_table): Likewise.
(emit_single_op): Likewise.
(xtensa_create_trampoline_frag): Likewise.
(xtensa_maybe_create_literal_pool_frag): Likewise.
(xtensa_add_config_info): Likewise.
(xtensa_realloc_fixup_cache): Likewise.
(add_subseg_info): Likewise.
(cache_literal_section): Likewise.
(add_xt_block_frags): Likewise.
(add_xt_prop_frags): Likewise.
(init_op_placement_info_table): Likewise.
(build_section_rename): Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* depend.c (register_dependency): Likewise.
* dwarf2dbg.c (get_line_subseg): Likewise.
(dwarf2_gen_line_info_1): Likewise.
(get_filenum): Likewise.
* ecoff.c (allocate_scope): Likewise.
(allocate_vlinks): Likewise.
(allocate_shash): Likewise.
(allocate_thash): Likewise.
(allocate_tag): Likewise.
(allocate_forward): Likewise.
(allocate_thead): Likewise.
(allocate_lineno_list): Likewise.
* expr.c (make_expr_symbol): Likewise.
* hash.c (hash_new_sized): Likewise.
* input-file.c (input_file_push): Likewise.
* listing.c (file_info): Likewise.
(listing_newline): Likewise.
* macro.c (new_formal): Likewise.
(define_macro): Likewise.
* remap.c (add_debug_prefix_map): Likewise.
* symbols.c (symbol_find_noref): Likewise.
(define_dollar_label): Likewise.
(fb_label_instance_inc): Likewise.
(symbol_relc_make_value): Likewise.
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-elf.c (obj_elf_vendor_attribute): Use xstrdup.
* config/tc-ppc.c (ppc_frob_file_before_adjust): Likewise.
(ppc_znop): Likewise.
(ppc_pe_section): Likewise.
(ppc_frob_symbol): Likewise.
* config/tc-tic30.c (tic30_operand): Likewise.
* config/tc-tic4x.c (tic4x_sect): Likewise.
(tic4x_usect): Likewise.
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-alpha.c: Const qualify FLT_CHARS.
* config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS.
* config/tc-cris.h: Likewise.
* expr.c: Likewise.
* config/tc-mmix.c (md_atof): Adjust comment.
* config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros.
* tc.h: Declare FLT_CHARS and EXP_CHARS.
2016-04-04 01:49:05 +02:00
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-score.c (s3_gen_reloc): Add const qualifiers.
* config/tc-score7.c (s7_gen_reloc): Likewise.
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (do_t_branch): Change the type of reloc to
bfd_reloc_code_real_type.
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/bfin-parse.y (current_inputline): Remove definition.
* config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (md_parse_option): Use strcasecmp () to compare
strings.
2016-04-02 Alan Modra <amodra@gmail.com>
PR 19896
* read.c (assign_symbol): Consume rest of line after an error
rather than continuing to process the line.
2016-04-01 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to...
(MAX_FLAG_NAME_LENGTH): ...this.
(struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH.
* config/tc-arc.c (tokenize_flags): Likewise.
Constify more * cgen.c (weak_operand_overflow_check): Return const char*. * messages.c (as_internal_value_out_of_range): Formatting. (as_warn_value_out_of_range): Consify prefix param. (as_bad_value_out_of_range): Likewise. * read.c (s_errwarn): Constify msg.. (s_float_space, float_cons): ..and err. * as.h (as_warn_value_out_of_range, as_bad_value_out_of_range, ieee_md_atof, vax_md_atof): Update prototypes. * tc.h (md_atof): Update prototype. * config/atof-ieee.c (ieee_md_atof): Return const char*. * config/atof-vax.c (vax_md_atof): Likewise. * config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg. * config/tc-aarch64.c (md_atof): Return const char*. * config/tc-alpha.c (s_alpha_section_name): Likewise. (s_alpha_comm): Constify sec_name. (section_name): Constify. (s_alpha_section): Consify name.. (alpha_elf_section_letter): ..and ptr_msg param.. (md_atof): ..and return. * config/tc-alpha.h (alpha_elf_section_letter): Update prototype. * config/tc-arc.c (md_atof): Return const char*. * config/tc-arm.c (md_atof): Likewise. * config/tc-avr.c (md_atof): Likewise. * config/tc-bfin.c (md_atof): Likewise. * config/tc-cr16.c (md_atof): Likewise. * config/tc-cris.c (md_atof): Likewise. * config/tc-crx.c (md_atof): Likewise. * config/tc-d10v.c (md_atof): Likewise. * config/tc-d30v.c (md_atof): Likewise. * config/tc-dlx.c (md_atof): Likewise. * config/tc-epiphany.c (md_atof): Likewise. * config/tc-fr30.c (md_atof): Likewise. * config/tc-frv.c (md_atof): Likewise. * config/tc-ft32.c (md_atof): Likewise. * config/tc-h8300.c (md_atof): Likewise. * config/tc-hppa.c (struct default_subspace_dict): Constify name. (struct default_space_dict): Likewise. (create_new_space): Constify name param. (create_new_subspace): Likewise. (is_defined_space, is_defined_subspace): Likewise. (pa_parse_space_stmt): Constify space_name param. (md_atof): Return const char*. (pa_spaces_begin): Constify name. * config/tc-i370.c (md_atof): Return const char*. * config/tc-i386.c (md_atof): Likewise. (x86_64_section_letter): Constify ptr_msg param. * config/tc-i386.h (x86_64_section_letter): Update prototype. * config/tc-i860.c (struct i860_it): Constify error. (md_atof): Return const char*. * config/tc-i960.c (md_atof): Likewise. * config/tc-ia64.c (md_atof): Likewise. (ia64_elf_section_letter): Constify ptr_msg param. * config/tc-ia64.h (ia64_elf_section_letter): Update prototype. * config/tc-ip2k.c (md_atof): Return const char*. * config/tc-iq2000.c (md_atof): Likewise. * config/tc-lm32.c (md_atof): Likewise. * config/tc-m32c.c (md_atof): Likewise. * config/tc-m32r.c (md_atof): Likewise. * config/tc-m68hc11.c (md_atof): Likewise. * config/tc-m68k.c (md_atof): Likewise. * config/tc-mcore.c (md_atof): Likewise. * config/tc-mep.c (md_atof): Likewise. (mep_elf_section_letter): Constify ptr_msg param. * config/tc-mep.h (mep_elf_section_letter): Update prototype. * config/tc-metag.c (md_atof): Return const char*. * config/tc-microblaze.c (md_atof): Likewise. * config/tc-microblaze.h (md_atof): Delete prototype. * config/tc-mips.c (mips_parse_argument_token): Constify err. (md_atof): Return const char*. * config/tc-mmix.c (md_atof): Likewise. * config/tc-mn10200.c (md_atof): Likewise. * config/tc-mn10300.c (md_atof): Likewise. * config/tc-moxie.c (md_atof): Likewise. * config/tc-msp430.c (md_atof): Likewise. * config/tc-mt.c (md_atof): Likewise. * config/tc-nds32.c (md_atof): Likewise. * config/tc-nios2.c (md_atof): Likewise. (nios2_elf_section_letter): Constify ptr_msg param. * config/tc-nios2.h (nios2_elf_section_letter): Update prototype. * config/tc-ns32k.c (md_atof): Return const char*. * config/tc-or1k.c (md_atof): Likewise. * config/tc-pdp11.c (struct pdp11_code): Constify error. (md_atof): Return const char*. * config/tc-pj.c (md_atof): Likewise. * config/tc-ppc.c (md_atof): Likewise. * config/tc-rl78.c (md_atof): Likewise. * config/tc-rx.c (md_atof): Likewise. * config/tc-s390.c (md_atof): Likewise. * config/tc-score.c (s3_atof, md_atof): Likewise. * config/tc-sh.c (md_atof): Likewise. * config/tc-sparc.c (struct sparc_it): Constify error. (md_atof): Return const char*. * config/tc-spu.c (md_atof): Likewise. * config/tc-tic30.c (md_atof): Likewise. * config/tc-tic4x.c (md_atof): Likewise. * config/tc-tic54x.c (md_atof): Likewise. * config/tc-tic6x.c (md_atof): Likewise. * config/tc-tilegx.c (md_atof): Likewise. * config/tc-tilepro.c (md_atof): Likewise. * config/tc-v850.c (parse_register_list, md_atof): Likewise. * config/tc-vax.c (md_atof): Likewise. * config/tc-visium.c (md_atof): Likewise. * config/tc-xc16x.c (md_atof): Likewise. * config/tc-xgate.c (md_atof): Likewise. * config/tc-xstormy16.c (md_atof): Likewise. * config/tc-xtensa.c (md_atof): Likewise. * config/tc-z80.c (md_atof): Likewise. * config/tc-z8k.c (md_atof): Likewise.
2016-04-01 14:07:50 +02:00
2016-04-01 Alan Modra <amodra@gmail.com>
* cgen.c (weak_operand_overflow_check): Return const char*.
* messages.c (as_internal_value_out_of_range): Formatting.
(as_warn_value_out_of_range): Consify prefix param.
(as_bad_value_out_of_range): Likewise.
* read.c (s_errwarn): Constify msg..
(s_float_space, float_cons): ..and err.
* as.h (as_warn_value_out_of_range, as_bad_value_out_of_range,
ieee_md_atof, vax_md_atof): Update prototypes.
* tc.h (md_atof): Update prototype.
* config/atof-ieee.c (ieee_md_atof): Return const char*.
* config/atof-vax.c (vax_md_atof): Likewise.
* config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg.
* config/tc-aarch64.c (md_atof): Return const char*.
* config/tc-alpha.c (s_alpha_section_name): Likewise.
(s_alpha_comm): Constify sec_name.
(section_name): Constify.
(s_alpha_section): Consify name..
(alpha_elf_section_letter): ..and ptr_msg param..
(md_atof): ..and return.
* config/tc-alpha.h (alpha_elf_section_letter): Update prototype.
* config/tc-arc.c (md_atof): Return const char*.
* config/tc-arm.c (md_atof): Likewise.
* config/tc-avr.c (md_atof): Likewise.
* config/tc-bfin.c (md_atof): Likewise.
* config/tc-cr16.c (md_atof): Likewise.
* config/tc-cris.c (md_atof): Likewise.
* config/tc-crx.c (md_atof): Likewise.
* config/tc-d10v.c (md_atof): Likewise.
* config/tc-d30v.c (md_atof): Likewise.
* config/tc-dlx.c (md_atof): Likewise.
* config/tc-epiphany.c (md_atof): Likewise.
* config/tc-fr30.c (md_atof): Likewise.
* config/tc-frv.c (md_atof): Likewise.
* config/tc-ft32.c (md_atof): Likewise.
* config/tc-h8300.c (md_atof): Likewise.
* config/tc-hppa.c (struct default_subspace_dict): Constify name.
(struct default_space_dict): Likewise.
(create_new_space): Constify name param.
(create_new_subspace): Likewise.
(is_defined_space, is_defined_subspace): Likewise.
(pa_parse_space_stmt): Constify space_name param.
(md_atof): Return const char*.
(pa_spaces_begin): Constify name.
* config/tc-i370.c (md_atof): Return const char*.
* config/tc-i386.c (md_atof): Likewise.
(x86_64_section_letter): Constify ptr_msg param.
* config/tc-i386.h (x86_64_section_letter): Update prototype.
* config/tc-i860.c (struct i860_it): Constify error.
(md_atof): Return const char*.
* config/tc-i960.c (md_atof): Likewise.
* config/tc-ia64.c (md_atof): Likewise.
(ia64_elf_section_letter): Constify ptr_msg param.
* config/tc-ia64.h (ia64_elf_section_letter): Update prototype.
* config/tc-ip2k.c (md_atof): Return const char*.
* config/tc-iq2000.c (md_atof): Likewise.
* config/tc-lm32.c (md_atof): Likewise.
* config/tc-m32c.c (md_atof): Likewise.
* config/tc-m32r.c (md_atof): Likewise.
* config/tc-m68hc11.c (md_atof): Likewise.
* config/tc-m68k.c (md_atof): Likewise.
* config/tc-mcore.c (md_atof): Likewise.
* config/tc-mep.c (md_atof): Likewise.
(mep_elf_section_letter): Constify ptr_msg param.
* config/tc-mep.h (mep_elf_section_letter): Update prototype.
* config/tc-metag.c (md_atof): Return const char*.
* config/tc-microblaze.c (md_atof): Likewise.
* config/tc-microblaze.h (md_atof): Delete prototype.
* config/tc-mips.c (mips_parse_argument_token): Constify err.
(md_atof): Return const char*.
* config/tc-mmix.c (md_atof): Likewise.
* config/tc-mn10200.c (md_atof): Likewise.
* config/tc-mn10300.c (md_atof): Likewise.
* config/tc-moxie.c (md_atof): Likewise.
* config/tc-msp430.c (md_atof): Likewise.
* config/tc-mt.c (md_atof): Likewise.
* config/tc-nds32.c (md_atof): Likewise.
* config/tc-nios2.c (md_atof): Likewise.
(nios2_elf_section_letter): Constify ptr_msg param.
* config/tc-nios2.h (nios2_elf_section_letter): Update prototype.
* config/tc-ns32k.c (md_atof): Return const char*.
* config/tc-or1k.c (md_atof): Likewise.
* config/tc-pdp11.c (struct pdp11_code): Constify error.
(md_atof): Return const char*.
* config/tc-pj.c (md_atof): Likewise.
* config/tc-ppc.c (md_atof): Likewise.
* config/tc-rl78.c (md_atof): Likewise.
* config/tc-rx.c (md_atof): Likewise.
* config/tc-s390.c (md_atof): Likewise.
* config/tc-score.c (s3_atof, md_atof): Likewise.
* config/tc-sh.c (md_atof): Likewise.
* config/tc-sparc.c (struct sparc_it): Constify error.
(md_atof): Return const char*.
* config/tc-spu.c (md_atof): Likewise.
* config/tc-tic30.c (md_atof): Likewise.
* config/tc-tic4x.c (md_atof): Likewise.
* config/tc-tic54x.c (md_atof): Likewise.
* config/tc-tic6x.c (md_atof): Likewise.
* config/tc-tilegx.c (md_atof): Likewise.
* config/tc-tilepro.c (md_atof): Likewise.
* config/tc-v850.c (parse_register_list, md_atof): Likewise.
* config/tc-vax.c (md_atof): Likewise.
* config/tc-visium.c (md_atof): Likewise.
* config/tc-xc16x.c (md_atof): Likewise.
* config/tc-xgate.c (md_atof): Likewise.
* config/tc-xstormy16.c (md_atof): Likewise.
* config/tc-xtensa.c (md_atof): Likewise.
* config/tc-z80.c (md_atof): Likewise.
* config/tc-z8k.c (md_atof): Likewise.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct rename_section_struct): Make old_name
const.
(xtensa_section_rename): Make argument type const char *.
* config/tc-xtensa.h (xtensa_section_rename): Adjust.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_ldconst): Cast to char * when assigning to
args[0].
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to
char *.
(m32c_indirect_operand): Likewise.
* config/tc-nds32.c (do_pseudo_b): Likewise.
(do_pseudo_bal): Likewise.
(do_pseudo_ls_bhw): Likewise.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (parse_args): Cast literal to char * when assigning to optarg.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (md_assemble): Add temporary variable to pass to
get_symbol_name ().
* config/tc-sparc.c (s_register): Cast a literal to char * in
assignment.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_expr): Cast to char * when assigning to
input_line_pointer.
* config/tc-m32r.c (expand_debug_syms): Likewise.
* config/tc-msp430.c (msp430_dstoperand): Likewise.
* config/tc-z80.c (md_begin): Likewise.
* stabs.c (stabs_generate_asm_func): Likewise.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cgen.c: Modernize the way functions declare arguments.
* config/tc-bfin.c: Likewise.
* config/tc-pdp11.c: Likewise.
* literal.c: Likewise.
* read.c: Likewise.
* stabs.c: Likewise.
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c (aarch64_handle_align): Make the type of some
variables unsigned char[].
* config/tc-alpha.c (alpha_handle_align): Likewise.
* config/tc-arm.c (arm_handle_align): Likewise.
* config/tc-z80.c: Likewise.
2016-03-30 Nick Clifton <nickc@redhat.com>
PR target/19880
* config/tc-arm.c (do_t_push_pop): Cast bitmask to unsigned before
shifting.
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* testsuite/gas/all/gas.exp: Don't xfail on ARC.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/all/redef3.d: Allow execution for ARC.
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/warn.exp: Fix matching pattern.
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
make md_parse_option () take a const char * This is mostly just adding const in many places, however there are a couple interesting things. We need to add casts in tc-s390.c and tc-cris.c because they have functions that assign to input_line_pointer an argument that sometimes comes from md_parse_option. Presumably this is safe because those targets never pass literals to md_parse_option (), but this code should probably be improved in the future. Also xtensa passes the argument to strtoll which is a rather odd function, it takes a const char * as argument and returns a pointer into that string as a char * through an out argument, but we can work around that by adding more variables. gas/ChangeLog: 2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-aarch64.c (struct aarch64_long_option_table): Ad const qualifier. * config/tc-alpha.c (md_parse_option): Likewise. * config/tc-arc.c (md_parse_option): Likewise. * config/tc-arm.c (struct arm_long_option_table): Likewise. (md_parse_option): Likewise. * config/tc-avr.c (md_parse_option): Likewise. * config/tc-bfin.c (md_parse_option): Likewise. * config/tc-cr16.c (md_parse_option): Likewise. * config/tc-cris.c (s_cris_arch): Likewise. (md_parse_option): Likewise. * config/tc-crx.c (md_parse_option): Likewise. * config/tc-d10v.c (md_parse_option): Likewise. * config/tc-d30v.c (md_parse_option): Likewise. * config/tc-dlx.c (md_parse_option): Likewise. * config/tc-epiphany.c (md_parse_option): Likewise. * config/tc-fr30.c (md_parse_option): Likewise. * config/tc-frv.c (md_parse_option): Likewise. * config/tc-ft32.c (md_parse_option): Likewise. * config/tc-h8300.c (md_parse_option): Likewise. * config/tc-hppa.c (md_parse_option): Likewise. * config/tc-i370.c (md_parse_option): Likewise. * config/tc-i386.c (md_parse_option): Likewise. * config/tc-i860.c (md_parse_option): Likewise. * config/tc-i960.c (md_parse_option): Likewise. * config/tc-ia64.c (md_parse_option): Likewise. * config/tc-ip2k.c (md_parse_option): Likewise. * config/tc-iq2000.c (md_parse_option): Likewise. * config/tc-lm32.c (md_parse_option): Likewise. * config/tc-m32c.c (md_parse_option): Likewise. * config/tc-m32r.c (md_parse_option): Likewise. * config/tc-m68hc11.c (md_parse_option): Likewise. * config/tc-m68k.c (md_parse_option): Likewise. * config/tc-mcore.c (md_parse_option): Likewise. * config/tc-mep.c (md_parse_option): Likewise. * config/tc-metag.c (struct metag_long_option): Likewise. (md_parse_option): Likewise. * config/tc-microblaze.c (md_parse_option): Likewise. * config/tc-microblaze.h (md_parse_option): Remove prototype. * config/tc-mips.c (md_parse_option): Adjust. * config/tc-mmix.c (md_parse_option): Likewise. * config/tc-mn10200.c (md_parse_option): Likewise. * config/tc-mn10300.c (md_parse_option): Likewise. * config/tc-moxie.c (md_parse_option): Likewise. * config/tc-msp430.c (md_parse_option): Likewise. * config/tc-mt.c (md_parse_option): Likewise. * config/tc-nds32.c (md_parse_option): Likewise. * config/tc-nds32.h (nds32_parse_option): Likewise. * config/tc-nios2.c (md_parse_option): Likewise. * config/tc-ns32k.c (md_parse_option): Likewise. * config/tc-or1k.c (md_parse_option): Likewise. * config/tc-pdp11.c (md_parse_option): Likewise. * config/tc-pj.c (md_parse_option): Likewise. * config/tc-ppc.c (md_parse_option): Likewise. * config/tc-rl78.c (md_parse_option): Likewise. * config/tc-rx.c (md_parse_option): Likewise. * config/tc-s390.c (s390_parse_cpu): Likewise. * config/tc-score.c (md_parse_option): Likewise. * config/tc-sh.c (md_parse_option): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. * config/tc-spu.c (md_parse_option): Likewise. * config/tc-tic30.c (md_parse_option): Likewise. * config/tc-tic4x.c (md_parse_option): Likewise. * config/tc-tic54x.c (md_parse_option): Likewise. * config/tc-tic6x.c (md_parse_option): Likewise. * config/tc-tilegx.c (md_parse_option): Likewise. * config/tc-tilepro.c (md_parse_option): Likewise. * config/tc-v850.c (md_parse_option): Likewise. * config/tc-vax.c (md_parse_option): Likewise. * config/tc-visium.c (struct visium_long_option_table): Likewise. * config/tc-xc16x.c (md_parse_option): Likewise. * config/tc-xgate.c (md_parse_option): Likewise. * config/tc-xstormy16.c (md_parse_option): Likewise. * config/tc-xtensa.c (md_parse_option): Likewise. * config/tc-z80.c (md_parse_option): Likewise. * config/tc-z8k.c (md_parse_option): Likewise. * tc.h (md_parse_option): Likewise.
2016-02-27 15:35:32 +01:00
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c (struct aarch64_long_option_table): Ad const
qualifier.
* config/tc-alpha.c (md_parse_option): Likewise.
* config/tc-arc.c (md_parse_option): Likewise.
* config/tc-arm.c (struct arm_long_option_table): Likewise.
(md_parse_option): Likewise.
* config/tc-avr.c (md_parse_option): Likewise.
* config/tc-bfin.c (md_parse_option): Likewise.
* config/tc-cr16.c (md_parse_option): Likewise.
* config/tc-cris.c (s_cris_arch): Likewise.
(md_parse_option): Likewise.
* config/tc-crx.c (md_parse_option): Likewise.
* config/tc-d10v.c (md_parse_option): Likewise.
* config/tc-d30v.c (md_parse_option): Likewise.
* config/tc-dlx.c (md_parse_option): Likewise.
* config/tc-epiphany.c (md_parse_option): Likewise.
* config/tc-fr30.c (md_parse_option): Likewise.
* config/tc-frv.c (md_parse_option): Likewise.
* config/tc-ft32.c (md_parse_option): Likewise.
* config/tc-h8300.c (md_parse_option): Likewise.
* config/tc-hppa.c (md_parse_option): Likewise.
* config/tc-i370.c (md_parse_option): Likewise.
* config/tc-i386.c (md_parse_option): Likewise.
* config/tc-i860.c (md_parse_option): Likewise.
* config/tc-i960.c (md_parse_option): Likewise.
* config/tc-ia64.c (md_parse_option): Likewise.
* config/tc-ip2k.c (md_parse_option): Likewise.
* config/tc-iq2000.c (md_parse_option): Likewise.
* config/tc-lm32.c (md_parse_option): Likewise.
* config/tc-m32c.c (md_parse_option): Likewise.
* config/tc-m32r.c (md_parse_option): Likewise.
* config/tc-m68hc11.c (md_parse_option): Likewise.
* config/tc-m68k.c (md_parse_option): Likewise.
* config/tc-mcore.c (md_parse_option): Likewise.
* config/tc-mep.c (md_parse_option): Likewise.
* config/tc-metag.c (struct metag_long_option): Likewise.
(md_parse_option): Likewise.
* config/tc-microblaze.c (md_parse_option): Likewise.
* config/tc-microblaze.h (md_parse_option): Remove prototype.
* config/tc-mips.c (md_parse_option): Adjust.
* config/tc-mmix.c (md_parse_option): Likewise.
* config/tc-mn10200.c (md_parse_option): Likewise.
* config/tc-mn10300.c (md_parse_option): Likewise.
* config/tc-moxie.c (md_parse_option): Likewise.
* config/tc-msp430.c (md_parse_option): Likewise.
* config/tc-mt.c (md_parse_option): Likewise.
* config/tc-nds32.c (md_parse_option): Likewise.
* config/tc-nds32.h (nds32_parse_option): Likewise.
* config/tc-nios2.c (md_parse_option): Likewise.
* config/tc-ns32k.c (md_parse_option): Likewise.
* config/tc-or1k.c (md_parse_option): Likewise.
* config/tc-pdp11.c (md_parse_option): Likewise.
* config/tc-pj.c (md_parse_option): Likewise.
* config/tc-ppc.c (md_parse_option): Likewise.
* config/tc-rl78.c (md_parse_option): Likewise.
* config/tc-rx.c (md_parse_option): Likewise.
* config/tc-s390.c (s390_parse_cpu): Likewise.
* config/tc-score.c (md_parse_option): Likewise.
* config/tc-sh.c (md_parse_option): Likewise.
* config/tc-sparc.c (md_parse_option): Likewise.
* config/tc-spu.c (md_parse_option): Likewise.
* config/tc-tic30.c (md_parse_option): Likewise.
* config/tc-tic4x.c (md_parse_option): Likewise.
* config/tc-tic54x.c (md_parse_option): Likewise.
* config/tc-tic6x.c (md_parse_option): Likewise.
* config/tc-tilegx.c (md_parse_option): Likewise.
* config/tc-tilepro.c (md_parse_option): Likewise.
* config/tc-v850.c (md_parse_option): Likewise.
* config/tc-vax.c (md_parse_option): Likewise.
* config/tc-visium.c (struct visium_long_option_table): Likewise.
* config/tc-xc16x.c (md_parse_option): Likewise.
* config/tc-xgate.c (md_parse_option): Likewise.
* config/tc-xstormy16.c (md_parse_option): Likewise.
* config/tc-xtensa.c (md_parse_option): Likewise.
* config/tc-z80.c (md_parse_option): Likewise.
* config/tc-z8k.c (md_parse_option): Likewise.
* tc.h (md_parse_option): Likewise.
2016-03-29 13:40:22 +02:00
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-bfin.c (gencode): Use XOBNEW obstack_alloc () wrapper.
* config/tc-hppa.c (fix_new_hppa): Likewise.
(pa_vtable_entry): Likewise.
(pa_vtable_inherit): Likewise.
* config/tc-m68k.c (md_begin): Likewise.
2016-03-28 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-elf.c (obj_elf_section_name): Return const char *.
* config/obj-elf.h (obj_elf_section_name): Adjust.
* config/tc-aarch64.c (aarch64_parse_features): Likewise.
(aarch64_parse_cpu): Likewise.
(aarch64_parse_arch): Likewise.
* config/tc-arm.c (arm_parse_extension): Likewise.
(arm_parse_cpu): Likewise.
(arm_parse_arch): Likewise.
* config/tc-nds32.c: Likewise.
* config/xtensa-relax.c (parse_special_fn): Likewise.
* stabs.c (generate_asm_file): Likewise.
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-cr16.c (cr16_assemble): New function.
(md_assemble): Call cr16_assemble.
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (parse_args): Adjust.
* as.h (flag_size_check): Rename to flag_allow_nonconst_size.
* config/obj-elf.c (elf_frob_symbol): Adjust.
2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR
registers to be in the 16..31 range.
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-microblaze.c (md_assemble): Cast opc to char * when calling
frag_var ().
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-visium.c (md_atof): Localize the string returned on
failure.
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-h8300.c (h8300_elf_section): Add const qualifiers.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-m68hc11.c (md_begin): Likewise.
(print_opcode_list): Likewise.
* config/tc-msp430.c (msp430_section): Likewise.
* config/tc-score.c (struct s3_insn_to_dependency): Likewise.
(s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (struct s7_insn_to_dependency): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(subsym_get_arg): Likewise.
* config/tc-xtensa.c (struct suffix_reloc_map): Likewise.
(get_directive): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c: Likewise.
* symbols.c (symbol_create): Likewise.
(local_symbol_make): Likewise.
(symbol_relc_make_expr): Likewise.
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-pdp11.c (md_assemble): Remove useless if and assignment to
str.
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr ()
call with a switch.
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (ia64_do_align): Remove.
(ia64_cons_align): Call do_align () directly.
(dot_proc): Likewise.
(stmt_float_cons): Likewise.
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* listing.c (listing_message): Use XNEW style allocation macros.
* read.c (read_a_source_file): Likewise.
(read_symbol_name): Likewise.
(s_mri_common): Likewise.
(assign_symbol): Likewise.
(s_reloc): Likewise.
(emit_expr_with_reloc): Likewise.
(s_incbin): Likewise.
(s_include): Likewise.
* sb.c (sb_build): Likewise.
(sb_check): Likewise.
2016-03-22 Alan Modra <amodra@gmail.com>
* write.c (record_alignment): Revert 2016-02-18 change.
2016-03-22 Alan Modra <amodra@gmail.com>
* config/tc-alpha.c (load_expression): Replace alloca with xmalloc.
(emit_jsrjmp, tc_gen_reloc): Likewise.
* config/tc-i370.c (i370_macro): Likewise.
2016-03-22 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
arc/opcodes: Use flag operand class to handle multiple flag matches When parsing the operand instruction flags we don't currently detect the case where multiple flags are provided from the same class set, these will be accepted and the bit values merged together, resulting in the wrong instruction being assembled. For example: adc.n.eq r0,r0,r2 Will assemble without error, yet, upon disassembly, the instruction will actually be: adc.c r0,r0,r2 In a later commit the concept of required flags will be introduced. Required flags are just like normal instruction flags, except that they must be present for the instruction to match. Adding this will allow for simpler instructions in the instruction table, and allow for more sharing of operand extraction and insertion functions. To solve both of the above issues (multiple flags being invalid, and required flags), this commit reworks the flag class mechanism. Currently the flag class is never used. Each instruction can reference multiple flag classes, each flag class has a class type and a set of flags. However, at present, the class type is never used. The current values identify the type of instruction that the flag will be used in, but this is not required information. Instead, this commit discards the old flag classes, and introduces 3 new classes. The first F_CLASS_NONE, is just a NULL marker value, and is only used in the NULL marker flag class. The other two flag classes are F_FLAG_OPTIONAL, and F_FLAG_REQUIRED. The class F_FLAG_OPTIONAL has the property that at most one of the flags in the flag set for that class must be present in the instruction. The "at most" one means that no flags being present is fine. The class F_FLAG_REQUIRED is not currently used, but will be soon. With this class, exactly one of the flags from this class must be present in the instruction. If the flag class contains a single flag, then of course that flag must be present. However, if the flag class contained two or more, then one, and only one of them must be present. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. Handle flag class. * testsuite/gas/arc/asm-errors.d: New file. * testsuite/gas/arc/asm-errors.err: New file. * testsuite/gas/arc/asm-errors.s: New file. include/ChangeLog: * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. opcodes/ChangeLog: * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values.
2016-03-14 23:17:47 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
2016-03-15 22:51:50 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
arc: Remove EF_ARC_CPU_GENERIC constant. The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h file, and is used in a few places in binutils, however, this constant should never make it into the elf header flags; we always set a valid cpu type in the assembler, which should then be copied over during linking. There are some non-gnu arc compilers that don't write an architecture type into the e_flags field, instead leaving the field as 0, which is the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine type to distinguish between the old and newer arc architectures, setting the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700 architectures, while using EM_ARC_COMPACT2 for newer arcem and archs architectures. Previously when displaying the machine flags for an older EM_ARC_COMPACT machine, if the e_flags had not been filled in, then we relied on the default case statement to display the message "Generic ARCompact", while in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC to print "ARC Generic", leaving the default case to print a message about unrecognised cpu flag. After this commit EF_ARC_CPU_GENERIC has been removed, for both machine types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case statement to handle the situation where the e_flags has not been filled in. The message displayed is now "Unknown ARCompact" (for older arc architectures) and "Unknown ARC" (for the newer architectures). The switch from "Generic" to "Unknown" in the message string is for clarity, calling the file "Generic" can give the impression that the file is compiled for a common sub-set of the architectures, and would therefore run on any type of machine (or at least any type of new or old machine depending on if the machine type is ARC or ARCv2). However, this was not what "Generic" meant, it really meant "Unknown", so that's what we now say. As part of the merging of the readelf flag reading code, I have unified the strings used in displaying the ELF ABI. This means that for older arc machines (arc600, arc601, and arc700) the string used for the original ABI, and ABIv2 have changed, the current ABIv3 remains the same. For the newer architectures (arcem and archs) the abi strings remain unchanged in all cases. bfd/ChangeLog: * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of EF_ARC_CPU_GENERIC. (arc_elf_final_write_processing): Don't bother setting cpu field in e_flags, this will have been set elsewhere. binutils/ChangeLog: * readelf.c (get_machine_flags): Move arc processing into... (decode_ARC_machine_flags): ... new function. Remove use of EF_ARC_CPU_GENERIC, change default case from "generic arc" to "unknown arc". Merged ABI printing between two machine types. gas/ChangeLog: * config/tc-arc.c (arc_select_cpu): Remove use of EF_ARC_CPU_GENERIC. include/ChangeLog: * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-15 22:38:30 +01:00
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
2016-03-21 Nick Clifton <nickc@redhat.com>
* atof-generic.c: Replace use of alloca with call to xmalloc.
* cgen.c: Likewise.
* dwarf2dbg.c: Likewise.
* macro.c: Likewise.
* remap.c: Likewise.
* stabs.c: Likewise.
* symbols.c: Likewise.
* config/obj-elf.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic30.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/te-vms.c: Likewise.
* configure: Regenerate.
2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* tc-i386.c (f32_1): Change type to unsigned char[].
(f32_2): Likewise.
(f32_3): Likewise.
(f32_4): Likewise.
(f32_5): Likewise.
(f32_6): Likewise.
(f32_7): Likewise.
(f32_8): Likewise.
(f32_9): Likewise.
(f32_10): Likewise.
(f32_11): Likewise.
(f32_12): Likewise.
(f32_13): Likewise.
(f32_14): Likewise.
(f16_3): Likewise.
(f16_4): Likewise.
(f16_5): Likewise.
(f16_6): Likewise.
(f16_7): Likewise.
(f16_8): Likewise.
(jump_31): Likewise.
(f32_patt): Likewise.
(f16_patt): Likewise.
(alt_3): Likewise.
(alt_4): Likewise.
(alt_5): Likewise.
(alt_6): Likewise.
(alt_7): Likewise.
(alt_8): Likewise.
(alt_9): Likewise.
(alt_10): Likewise.
(alt_patt): Likewise.
2016-03-18 Nick Clifton <nickc@redhat.com>
* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
.tlsdescldr and .xword directives.
PR target/19721
* testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
* doc/as.texinfo: Place the target specific command line options
into their own man page section.
2016-03-16 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (N_S_32): New.
(N_F_16_32): Likewise.
(N_SUF_32): Support N_F16.
(N_IF_32): Likewise.
(neon_dyadic_misc): Likewise.
(do_neon_cmp): Likewise.
(do_neon_cmp_inv): Likewise.
(do_neon_mul): Likewise.
(do_neon_fcmp_absolute): Likewise.
(do_neon_step): Likewise.
(do_neon_abs_neg): Likewise.
(CVT_FLAVOR_VAR): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_recip_est): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(neon_check_type): Check architecture support for FP16 extension.
(insns): Update comments.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
error file.
2016-03-16 Nick Clifton <nickc@redhat.com>
* read.c (emit_expr_with_reloc): Add code check a bignum with
nbytes == 1.
* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
other than 32-bits.
* testsuite/gas/elf/bignum.s: New test source file.
* testsuite/gas/elf/bignum.d: New test driver file.
* testsuite/gas/elf/elf.exp: Run the new test.
2016-03-15 Ulrich Drepper <drepper@gmail.com>
* doc/c-i386.texi (Register Naming): Update to details of the
2016-04-07 15:43:14 +02:00
latest architecture version.
2016-03-10 Mickael Guene <mickael.guene@st.com>
PR gas/19744
* config/tc-arm.c (do_arit): Protect against bad relocations usage.
(do_mov): Likewise.
(do_t_add_sub): Allow pcrop relocations for Thumb-2 targets.
(do_t_mov_cmp): Likewise.
(do_t_add_sub): Protect against bad relocations usage.
(do_t_mov_cmp): Likewise.
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.s: New.
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.d: New.
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.s: New.
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.d: New.
2016-03-09 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (neon_alignment_bit): Rename do_align to
do_alignment.
(do_neon_ld_st_lane): Likewise.
(do_neon_ld_dup): Likewise.
2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: New file.
* testsuite/gas/arc/inline-data-1.s: New file.
2016-03-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (arm_cpus): Add cortex-r8.
* doc/c-arm.texi: Add cortex-r8.
Add const qualifiers at various places. opcodes * mcore-opc.h: Add const qualifiers. * microblaze-opc.h (struct op_code_struct): Likewise. * sh-opc.h: Likewise. * tic4x-dis.c (tic4x_print_indirect): Likewise. (tic4x_print_op): Likewise. include * opcode/dlx.h (struct dlx_opcode): Add const qualifiers. * opcode/h8300.h (struct h8_opcode): Likewise. * opcode/hppa.h (struct pa_opcode): Likewise. * opcode/msp430.h: Likewise. * opcode/spu.h (struct spu_opcode): Likewise. * opcode/tic30.h (struct _register): Likewise. * opcode/tic4x.h (struct tic4x_register): Likewise. (struct tic4x_cond): Likewise. (struct tic4x_indirect): Likewise. (struct tic4x_inst): Likewise. * opcode/visium.h (struct reg_entry): Likewise. gas * config/tc-arc.c: Add const qualifiers. * config/tc-h8300.c (md_begin): Likewise. * config/tc-ia64.c (print_prmask): Likewise. * config/tc-msp430.c (msp430_operands): Likewise. * config/tc-nds32.c (struct suffix_name): Likewise. (struct nds32_parse_option_table): Likewise. (struct nds32_set_option_table): Likewise. (do_pseudo_pushpopm): Likewise. (do_pseudo_pushpop_stack): Likewise. (nds32_relax_relocs): Likewise. (nds32_flag): Likewise. (struct nds32_hint_map): Likewise. (nds32_find_reloc_table): Likewise. (nds32_match_hint_insn): Likewise. * config/tc-s390.c: Likewise. * config/tc-sh.c (get_specific): Likewise. * config/tc-tic30.c: Likewise. * config/tc-tic4x.c (tic4x_inst_add): Likewise. (tic4x_indirect_parse): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-z80.c (struct reg_entry): Likewise. * config/tc-epiphany.c (md_assemble): Adjust. (epiphany_assemble): New function. (epiphany_elf_section_rtn): Call do_align directly. (epiphany_elf_section_text): Likewise. * config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise. (ip2k_elf_section_text): Likewise. * read.c (do_align): Make it not static. * read.h (do_align): New prototype.
2016-03-07 16:16:28 +01:00
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arc.c: Add const qualifiers.
* config/tc-h8300.c (md_begin): Likewise.
* config/tc-ia64.c (print_prmask): Likewise.
* config/tc-msp430.c (msp430_operands): Likewise.
* config/tc-nds32.c (struct suffix_name): Likewise.
(struct nds32_parse_option_table): Likewise.
(struct nds32_set_option_table): Likewise.
(do_pseudo_pushpopm): Likewise.
(do_pseudo_pushpop_stack): Likewise.
(nds32_relax_relocs): Likewise.
(nds32_flag): Likewise.
(struct nds32_hint_map): Likewise.
(nds32_find_reloc_table): Likewise.
(nds32_match_hint_insn): Likewise.
* config/tc-s390.c: Likewise.
* config/tc-sh.c (get_specific): Likewise.
* config/tc-tic30.c: Likewise.
* config/tc-tic4x.c (tic4x_inst_add): Likewise.
(tic4x_indirect_parse): Likewise.
* config/tc-vax.c (vax_cons): Likewise.
* config/tc-z80.c (struct reg_entry): Likewise.
* config/tc-epiphany.c (md_assemble): Adjust.
(epiphany_assemble): New function.
(epiphany_elf_section_rtn): Call do_align directly.
(epiphany_elf_section_text): Likewise.
* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
(ip2k_elf_section_text): Likewise.
* read.c (do_align): Make it not static.
* read.h (do_align): New prototype.
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Emit attribute
for ARMv8.1 AdvSIMD use.
* testsuite/gas/arm/attr-march-armv8-a+rdma.d: New.
* testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New.
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
feature.
(record_feature_use): New.
(mark_feature_used): Use record_feature_use.
(do_neon_qrdmlah): New.
(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
variants.
(arm_extensions): Put into alphabetical order. Re-indent "simd"
and "rdma" entries. Fix the incorrect merge value for "+rdma".
* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
Make source file explicit.
* testsuite/gas/arm/armv8-a+rdma.l: New.
* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
directives. Fix white-space.
* testsuite/gas/arm/armv8_1-a+simd.d: New.
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (arc_extra_reloc): Change size to 0.
(tc_arc_fix_adjustable): Changed default return value to 1.
* testsuite/gas/arc/j.d: Updated expected symbol
* testsuite/gas/arc/jl.d: Likewise
* testsuite/gas/arc/relax-avoid1.d: Likewise
* testsuite/gas/arc/st.d: Likewise
2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
* config/tc-arc.c: Enable code density instructions for ARC EM.
2016-02-26 15:44:03 +01:00
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
for ELF assemblers.
* as.c (flag_use_elf_stt_common): New.
(show_usage): Add --elf-stt-common=.
(option_values): Add OPTION_ELF_STT_COMMON.
(std_longopts): Add --elf-stt-common=.
(parse_args): Handle --elf-stt-common=.
* as.h (flag_use_elf_stt_common): New.
* config.in: Regenerated.
* configure: Likewise.
* configure.ac: Add --enable-elf-stt-common and define
DEFAULT_GENERATE_ELF_STT_COMMON.
* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
* doc/as.texinfo: Document --elf-stt-common=.
* testsuite/gas/elf/common3.s: New file.
* testsuite/gas/elf/common3a.d: Likewise.
* testsuite/gas/elf/common3b.d: Likewise.
* testsuite/gas/elf/common4.s: Likewise.
* testsuite/gas/elf/common4a.d: Likewise.
* testsuite/gas/elf/common4b.d: Likewise.
* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
and common4b.
* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compress-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compressed-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
of dw2-compress-3 and dw2-compressed-3.
Convert more variables to a constant form. * as.c (select_emulation_mode): Add const qualifiers. * as.h: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c (struct aarch64_option_table): Likewise. (struct aarch64_cpu_option_table): Likewise. (struct aarch64_arch_option_table): Likewise. (struct aarch64_option_cpu_value_table): Likewise. (struct aarch64_long_option_table): Likewise. (struct aarch64_option_abi_value_table): Likewise. * config/tc-arm.c (struct reloc_entry): Likewise. (tc_gen_reloc): Likewise. (struct arm_option_table): Likewise. (struct arm_legacy_option_table): Likewise. (struct arm_cpu_option_table): Likewise. (struct arm_arch_option_table): Likewise. (struct arm_option_extension_value_table): Likewise. (struct arm_option_fpu_value_table): Likewise. (struct arm_option_value_table): Likewise. (struct arm_long_option_table): Likewise. * config/tc-avr.c (struct avr_opcodes_s): Likewise. (struct mcu_type_s): Likewise. (struct exp_mod_s): Likewise. (avr_operand): Likewise. (avr_operands): Likewise. * config/tc-d10v.c (md_begin): Likewise. * config/tc-dlx.c: Likewise. * config/tc-fr30.c (fr30_is_colon_insn): Likewise. * config/tc-ft32.c (parse_condition): Likewise. * config/tc-h8300.c (do_a_fix_imm): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (hppa_regname_to_dw2regnum): Likewise. * config/tc-i370.c (i370_elf_suffix): Likewise. * config/tc-i960.c (struct tabentry): Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-m68k.h: Likewise. * config/tc-mcore.c (parse_psrmod): Likewise. * config/tc-metag.c (struct metag_core_option): Likewise. (struct metag_long_option): Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c (macro): Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c (struct rcodes_s): Likewise. (struct hcodes_s): Likewise. (md_parse_option): Likewise. * config/tc-ns32k.c (struct ns32k_option): Likewise. (optlist): Likewise. * config/tc-ppc.c (ppc_elf_suffix): Likewise. (tc_ppc_regname_to_dw2regnum): Likewise. * config/tc-ppc.h: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c (struct cpu_type): Likewise. * config/tc-sh.c (sh_regname_to_dw2regnum): Likewise. * config/tc-sparc.c (struct priv_reg_entry): Likewise. (sparc_ip): Likewise. * config/tc-spu.c (insn_fmt_string): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. * config/tc-v850.c: Likewise. * config/tc-visium.c (struct visium_arch_option_table): Likewise. (struct visium_long_option_table): Likewise. * config/tc-xgate.c: Likewise. * config/tc-z8k.c: Likewise. * read.c (add_include_dir): Likewise. * read.h: Likewise.
2016-02-25 17:55:21 +01:00
2016-02-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (select_emulation_mode): Add const qualifiers.
* as.h: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c (struct aarch64_option_table): Likewise.
(struct aarch64_cpu_option_table): Likewise.
(struct aarch64_arch_option_table): Likewise.
(struct aarch64_option_cpu_value_table): Likewise.
(struct aarch64_long_option_table): Likewise.
(struct aarch64_option_abi_value_table): Likewise.
* config/tc-arm.c (struct reloc_entry): Likewise.
(tc_gen_reloc): Likewise.
(struct arm_option_table): Likewise.
(struct arm_legacy_option_table): Likewise.
(struct arm_cpu_option_table): Likewise.
(struct arm_arch_option_table): Likewise.
(struct arm_option_extension_value_table): Likewise.
(struct arm_option_fpu_value_table): Likewise.
(struct arm_option_value_table): Likewise.
(struct arm_long_option_table): Likewise.
* config/tc-avr.c (struct avr_opcodes_s): Likewise.
(struct mcu_type_s): Likewise.
(struct exp_mod_s): Likewise.
(avr_operand): Likewise.
(avr_operands): Likewise.
* config/tc-d10v.c (md_begin): Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-fr30.c (fr30_is_colon_insn): Likewise.
* config/tc-ft32.c (parse_condition): Likewise.
* config/tc-h8300.c (do_a_fix_imm): Likewise.
* config/tc-hppa.c (pa_ip): Likewise.
(hppa_regname_to_dw2regnum): Likewise.
* config/tc-i370.c (i370_elf_suffix): Likewise.
* config/tc-i960.c (struct tabentry): Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-m68k.h: Likewise.
* config/tc-mcore.c (parse_psrmod): Likewise.
* config/tc-metag.c (struct metag_core_option): Likewise.
(struct metag_long_option): Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c (macro): Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c (struct rcodes_s): Likewise.
(struct hcodes_s): Likewise.
(md_parse_option): Likewise.
* config/tc-ns32k.c (struct ns32k_option): Likewise.
(optlist): Likewise.
* config/tc-ppc.c (ppc_elf_suffix): Likewise.
(tc_ppc_regname_to_dw2regnum): Likewise.
* config/tc-ppc.h: Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c (struct cpu_type): Likewise.
* config/tc-sh.c (sh_regname_to_dw2regnum): Likewise.
* config/tc-sparc.c (struct priv_reg_entry): Likewise.
(sparc_ip): Likewise.
* config/tc-spu.c (insn_fmt_string): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
* config/tc-v850.c: Likewise.
* config/tc-visium.c (struct visium_arch_option_table): Likewise.
(struct visium_long_option_table): Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-z8k.c: Likewise.
* read.c (add_include_dir): Likewise.
* read.h: Likewise.
2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/all/gas.exp: Change target pattern to cover
arceb-*.
* testsuite/gas/all/redef3.d: Likewise.
* testsuite/gas/elf/elf.exp: Likewise.
2016-02-24 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (BAD_FP16): New error message macro.
(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
fp16 scalar instructions.
(neon_check_type): Allow different size from key.
(do_vfp_nsyn_add_sub): Add support SE_H shape support.
(try_vfp_nsyn): Likewise.
(do_vfp_nsyn_mla_mls): Likewise.
(do_vfp_nsyn_fma_fms): Likewise.
(do_vfp_nsyn_ldm_stm): Likewise
(do_vfp_nsyn_sqrt): Likewise
(do_vfp_nsyn_div): Likewise
(do_vfp_nsyn_nmul): Likewise.
(do_vfp_nsyn_cmp): Likewise.
(do_neon_shll): Likewise.
(do_vfp_nsyn_cvt_fpv8): Likewise.
(do_neon_cvttb_2): Likewise.
(do_neon_mov): Likewise.
(do_neon_rshift_round_imm): Likewise.
(do_neon_ldr_str): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(insns): New entry for vins, vmovx.
(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
2016-02-24 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape.
(neon_shape_class): New SC_HALF.
(neon_shape_el): New SE_H.
(neon_shape_el_size): New size for SE_H.
(N_F_ALL): New macro to aggregate N_F16, N_F32, N_64.
(neon_select_shape): Add SE_H support code.
(el_type_of_type_chk): Use N_F_ALL.
(do_vfp_nsyn_cvt): Add SE_H shape support.
(do_neon_cvtz): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_cvttb_1): Likewise.
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.d: Adjust output.
* testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/mask_1.d: New.
* testsuite/gas/arm/mask_1.s: New.
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
* testsuite/gas/arm/copro.d: Update.
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add entry for cortex-a32.
* doc/c-arm.texi (ARM Options): Document cortex-a32.
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2016-04-07 15:43:14 +02:00
* doc/c-arm.texi (ARM Options): Document cortex-a17.
2016-02-23 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/elf/elf.exp: Skip tests for common directive on
hpux.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
2016-02-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* output-file.c (output_file_create): Make file name argument const.
(output_file_close): Likewise.
* output-file.h (output_file_create): Adjust.
(output_file_close): Likewise.
* depend.c (quote_string_for_make): Make src argument const char *.
(register_dependency): Likewise.
(wrap_output): Likewise.
* as.h (register_dependency): Adjust.
* config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to
as_where ();
* symbols.c (S_SET_EXTERNAL): Likewise.
* input-scrub.c (as_where): Return the file name.
* as.h (as_where): Adjust prototype.
* app.c (do_scrub_chars): Adjust.
* cond.c (s_elseif): Likewise.
(s_else): Likewise.
(initialize_cframe): Likewise.
* config/obj-coff.c (obj_coff_init_stab_section): Likewise.
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
* config/obj-som.c (obj_som_init_stab_section): Likewise.
* config/tc-aarch64.c (output_info): Likewise.
* config/tc-ia64.c (md_assemble): Likewise.
(dot_alias): Likewise.
* config/tc-m68k.c (m68k_frob_label): Likewise.
* config/tc-mmix.c (s_bspec): Likewise.
(mmix_handle_mmixal): Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(tic54x_adjust_symtab): Likewise.
* config/tc-xtensa.c (directive_push): Likewise.
(xtensa_sanity_check): Likewise.
(xtensa_relax_frag): Likewise.
(md_convert_frag): Likewise.
(tinsn_to_slotbuf): Likewise.
* dwarf2dbg.c (dwarf2_where): Likewise.
* ecoff.c (add_file): Likewise.
(ecoff_generate_asm_lineno): Likewise.
* expr.c (make_expr_symbol): Likewise.
* frags.c (frag_new): Likewise.
(frag_var_init): Likewise.
* listing.c (listing_newline): Likewise.
* messages.c (identify): Likewise.
(as_show_where): Likewise.
(as_warn_internal): Likewise.
(as_bad_internal): Likewise.
* read.c (s_irp): Likewise.
(s_macro): Likewise.
(s_reloc): Likewise.
* stabs.c (stabs_generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_func): Likewise.
* write.c (fix_new_internal): Likewise.
* as.h (PRINTF_WHERE_LIKE): Make file name argument const.
(as_warn_value_out_of_range): Adjust prototype.
(as_bad_value_out_of_range): Adjust prototype.
* messages.c (identify): Make file name argument const char *.
(as_warn_internal): Likewise.
(as_warn_where): Likewise.
(as_bad_internal): Likewise.
(as_bad_where): Likewise.
(as_internal_value_out_of_range): Likewise.
(as_warn_value_out_of_range): Likewise.
(as_bad_value_out_of_range): Likewise.
* as.h (found_comment_file): Change type to const char *.
* cond.c (file_line::file): Likewise.
* config/obj-coff.c (obj_coff_init_stab_section): Make variable const.
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
* config/obj-som.c (obj_som_init_stab_section): Likewise.
* config/tc-aarch64.c (output_info): Likewise.
* config/tc-alpha.c (insert_operand): Likewise.
* config/tc-arc.c (insert_operand): Likewise.
* config/tc-d30v.c (check_size): Likewise.
* config/tc-ia64.c (struct alias): Likewise.
* config/tc-m68k.c (struct label_line): Likewise.
* config/tc-mcore.c (md_apply_fix): Likewise.
* config/tc-microblaze.c (md_estimate_size_before_relax): Likewise.
* config/tc-mips.c (mips16_immed): Likewise.
* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
* config/tc-ppc.c (ppc_insert_operand): Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-s390.c (s390_insert_operand): Likewise.
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
(tic54x_adjust_symtab): Likewise.
* config/tc-tilegx.c (insert_operand): Likewise.
(apply_special_operator): Likewise.
* config/tc-tilepro.c (insert_operand): Likewise.
* config/tc-xtensa.c (directive_push): Likewise.
* ecoff.c (add_file): Likewise.
(ecoff_generate_asm_lineno): Likewise.
* listing.c (listing_newline): Likewise.
* read.c (s_irp): Likewise.
* write.c (install_reloc): Likewise.
* write.h (struct fix): Likewise.
* input-file.c (file_name): Change type to const char *.
(saved_file::file_name): Likewise.
(input_file_open): Change type of argument to const char *.
* input-file.h (input_file_open): Adjust.
* input-scrub.c (logical_input_file): change type to const char *.
(physical_input_file): Likewise.
2016-04-07 15:43:14 +02:00
(struct input_save): Adjust.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
(input_scrub_push): Adjust.
(input_scrub_begin): Adjust.
(as_where): Adjust.
* input-scrub.c (input_scrub_new_file): Make file name argument const.
(input_scrub_include_file): Likewise.
(new_logical_line_flags): Likewise.
(new_logical_line): Likewise.
* as.h: Adjust.
* frags.h (struct frag): Change type of fr_file to const char *.
* expr.c (expr_symbol_where): Change type of file argument to
const char **.
* expr.h (expr_symbol_where): Likewise.
* config/tc-i370.c (md_apply_fix): adjust.
* config/tc-mmix.c (mmix_md_end): Likewise.
* config/tc-ppc.c (md_apply_fix): Likewise.
* config/tc-s390.c (md_apply_fix): Likewise.
* symbols.c (report_op_error): Likewise.
(resolve_symbol_value): Likewise.
* config/tc-ia64.c (slot::src_file): Change type to const char *.
(rsrc::file): Likewise.
* config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to
const char *.
(xtensa_relax_frag): Likewise.
(md_convert_frag): Likewise.
(tinsn_to_slotbuf): Likewise.
* expr.c (expr_symbol_line): Likewise.
* macro.c (define_macro): Likewise.
* macro.h (macro_struct): Likewise.
* messages.c (as_show_where): Likewise.
* read.c (s_macro): Likewise.
* stabs.c (stabs_generate_asm_file): Likewise.
(generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
* write.h (struct reloc_list): Likewise.
* input-scrub.c (as_where): Change return type to const char *.
* as.h (as_wheree): Adjust.
2016-02-21 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Move BFD compression bits setting
to ...
(write_object_file): Here.
2016-02-20 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (register_number): Check RegVRex.
* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
with %zmm19 and %zmm3.
* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
2016-02-19 Matthew Wahab <matthew.wahab@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (arm_ext_fp16): New.
(arm_extensions): New entry for "fp16".
2016-02-19 Nick Clifton <nickc@redhat.com>
PR 19630
* read.c (read_a_source_file): Check for assemble_one returning
with input_line_pointer set to NULL.
Add more const type qualifiers to GAS sources. * output-file.c (output_file_create): Make file name argument const. (output_file_close): Likewise. * output-file.h (output_file_create): Adjust. (output_file_close): Likewise. * depend.c (quote_string_for_make): Make src argument const char *. (register_dependency): Likewise. (wrap_output): Likewise. * as.h (register_dependency): Adjust. * config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to as_where (); * symbols.c (S_SET_EXTERNAL): Likewise. * input-scrub.c (as_where): Return the file name. * as.h (as_where): Adjust prototype. * app.c (do_scrub_chars): Adjust. * cond.c (s_elseif): Likewise. (s_else): Likewise. (initialize_cframe): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-ia64.c (md_assemble): Likewise. (dot_alias): Likewise. * config/tc-m68k.c (m68k_frob_label): Likewise. * config/tc-mmix.c (s_bspec): Likewise. (mmix_handle_mmixal): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-xtensa.c (directive_push): Likewise. (xtensa_sanity_check): Likewise. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * dwarf2dbg.c (dwarf2_where): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * expr.c (make_expr_symbol): Likewise. * frags.c (frag_new): Likewise. (frag_var_init): Likewise. * listing.c (listing_newline): Likewise. * messages.c (identify): Likewise. (as_show_where): Likewise. (as_warn_internal): Likewise. (as_bad_internal): Likewise. * read.c (s_irp): Likewise. (s_macro): Likewise. (s_reloc): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_func): Likewise. * write.c (fix_new_internal): Likewise. * as.h (PRINTF_WHERE_LIKE): Make file name argument const. (as_warn_value_out_of_range): Adjust prototype. (as_bad_value_out_of_range): Adjust prototype. * messages.c (identify): Make file name argument const char *. (as_warn_internal): Likewise. (as_warn_where): Likewise. (as_bad_internal): Likewise. (as_bad_where): Likewise. (as_internal_value_out_of_range): Likewise. (as_warn_value_out_of_range): Likewise. (as_bad_value_out_of_range): Likewise. * as.h (found_comment_file): Change type to const char *. * cond.c (file_line::file): Likewise. * config/obj-coff.c (obj_coff_init_stab_section): Make variable const. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/tc-aarch64.c (output_info): Likewise. * config/tc-alpha.c (insert_operand): Likewise. * config/tc-arc.c (insert_operand): Likewise. * config/tc-d30v.c (check_size): Likewise. * config/tc-ia64.c (struct alias): Likewise. * config/tc-m68k.c (struct label_line): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-microblaze.c (md_estimate_size_before_relax): Likewise. * config/tc-mips.c (mips16_immed): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-ppc.c (ppc_insert_operand): Likewise. * config/tc-rx.c (rx_include): Likewise. * config/tc-s390.c (s390_insert_operand): Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (tic54x_adjust_symtab): Likewise. * config/tc-tilegx.c (insert_operand): Likewise. (apply_special_operator): Likewise. * config/tc-tilepro.c (insert_operand): Likewise. * config/tc-xtensa.c (directive_push): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * listing.c (listing_newline): Likewise. * read.c (s_irp): Likewise. * write.c (install_reloc): Likewise. * write.h (struct fix): Likewise. * input-file.c (file_name): Change type to const char *. (saved_file::file_name): Likewise. (input_file_open): Change type of argument to const char *. * input-file.h (input_file_open): Adjust. * input-scrub.c (logical_input_file): change type to const char *. (physical_input_file): Likewise. (struct input_save): Adjust. (input_scrub_push): Adjust. (input_scrub_begin): Adjust. (as_where): Adjust. * input-scrub.c (input_scrub_new_file): Make file name argument const. (input_scrub_include_file): Likewise. (new_logical_line_flags): Likewise. (new_logical_line): Likewise. * as.h: Adjust. * frags.h (struct frag): Change type of fr_file to const char *. * expr.c (expr_symbol_where): Change type of file argument to const char **. * expr.h (expr_symbol_where): Likewise. * config/tc-i370.c (md_apply_fix): adjust. * config/tc-mmix.c (mmix_md_end): Likewise. * config/tc-ppc.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * symbols.c (report_op_error): Likewise. (resolve_symbol_value): Likewise. * config/tc-ia64.c (slot::src_file): Change type to const char *. (rsrc::file): Likewise. * config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to const char *. (xtensa_relax_frag): Likewise. (md_convert_frag): Likewise. (tinsn_to_slotbuf): Likewise. * expr.c (expr_symbol_line): Likewise. * macro.c (define_macro): Likewise. * macro.h (macro_struct): Likewise. * messages.c (as_show_where): Likewise. * read.c (s_macro): Likewise. * stabs.c (stabs_generate_asm_file): Likewise. (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise. * write.h (struct reloc_list): Likewise. * input-scrub.c (as_where): Change return type to const char *. * as.h (as_wheree): Adjust.
2016-02-22 15:11:27 +01:00
2016-02-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* listing.c (rebuffer_line): Change return type to void.
* symbols.c (decode_local_label_name): Make type a const char *.
* listing.c (print_source): Make type of p const char *.
(print_line): Make type of string const char *.
(buffer_line): Return const char *.
(title): Make type const char *.
(subtitle): Likewise.
(listing_listing): Make type of p const char *.
* messages.c (as_internal_value_out_of_range): Make type of prefix
const char *.
* stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname
and string const char *.
* read.c (_bfd_rel): Make type of name const char *.
* app.c (out_string): Change type to const char *.
2016-04-07 15:43:14 +02:00
(struct app_save::out_string): Likewise.
2016-02-18 Dan Gisselquist <dgisselq@verizon.net>
Nick Clifton <nickc@redhat.com>
* read.c (finish_bundle): Avoid recording a negative alignment.
(do_align): Use unsigned values for n, len and max. Only create
a frag if the alignment requirement is greater than the minimum
byte alignment. Avoid recording a negative alignment.
(s_align): Use unsigned values where appropriate.
(bss_alloc): Use an unsigned value for the alignment.
(sizeof_sleb128): Add a comment noting that we encode one octet
per byte, regardless of the value of OCTETS_PER_BYTE_POWER.
(emit_leb129_expr): Abort if the emitted encoding was longer than
expected.
* read.h (output_leb128): Update prototype.
(sizeof_leb128): Update prototype.
(bss_alloc): Update prototype.
* write.c (record_alignment): Use an unsigned value for the
alignment. Do not record alignments less than the minimum
alignment for a byte.
* write.h (record_alignment): Update prototype.
2016-02-17 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_move_literals): Fix check for
.init.literal/.fini.literal section name.
* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
list of xtensa tests.
* testsuite/gas/xtensa/init-fini-literals.d: New file:
init-fini-literals test result patterns.
* testsuite/gas/xtensa/init-fini-literals.s: New file:
init-fini-literals test.
2016-02-17 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
devices.csv file as of March 2016.
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tc_arc_frame_initial_instructions): New
function.
(tc_arc_regname_to_dw2regnum): Likewise.
* config/tc-arc.h (TARGET_USE_CFIPOP): Define
(tc_cfi_frame_initial_instructions): Likewise.
(tc_regname_to_dw2regnum): Likewise.
* testsuite/gas/cfi/cfi-arc-1.d: New file.
* testsuite/gas/cfi/cfi-arc-1.s: Likewise.
* testsuite/gas/cfi/cfi.exp: Allow running tests for arc.
2016-02-16 Trevor Saunders <tbsaunde@tbsaunde.org>
* doc/internals.texi (S_IS_EXTERN): Remove.
2016-02-16 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Section): Fix up texinfo snafus in previous
update.
2016-02-16 Renlin Li <renlin.li@arm.com>
PR gas/19620
* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
* testsuite/gas/aarch64/movw_label.d: New.
* testsuite/gas/aarch64/movw_label.s: New.
2016-02-16 01:11:23 +01:00
2016-02-15 Vinay Kumar G. <Vinay.G@kpit.com>
PR gas/19556
* config/rx-parse.y (MOV): Opcode generation for index
register addressing mode.
* testsuite/gas/rx/rx.exp: Updated for new testcase.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/mov.d: Update expected output.
2016-02-16 01:11:23 +01:00
2016-02-15 Nick Clifton <nickc@redhat.com>
Enhance GAS's .section directive so that it can take numeric values for the flags and type fields. (ELF only) gas * doc/as.texinfo (.section): Document that numeric values can now be used for the flags and type fields of the ELF target's .section directive. Add notes about the restrictions on setting flags and types. * config/obj-elf.c (obj_elf_change_section): Allow known sections to be given processor specific section types. Allow processor and application specific flags of a section to be set after definition. (obj_elf_parse_section_letters): Handle parsing numeric values. (obj_elf_section_type): Handle parsing numeric values. (obj_elf_section): Allow numeric type values. * config/obj-elf.h (obj_elf_change_section): Update prototype. * testsuite/gas/elf/section10.d: New test. * testsuite/gas/elf/section10.s: Source file for new test. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. * NEWS: Mention the new feature. bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values for length and type fields. Use a signed value for the suffix_length field. binutils* readelf.c (get_section_type_name): Add hex prefix to offsets printed for LOPROC and LOOS values. Ensure that a result is always returned for the V850 target, even when an unrecognised processor specific value is encountered. (process_section_headers): Display key values in the order in which they appear to the user. Add the "C (compressed)" value to the list. ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/ld-i386/pr12921.d: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sh/tlsbin-2.d: Likewise. * testsuite/ld-sh/tlspic-2.d: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/ilp32-4.d: Likewise. * testsuite/ld-x86-64/pr12718.d: Likewise. * testsuite/ld-x86-64/pr12921.d: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/split-by-file.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-xtensa/tlsbin.rd: Likewise. * testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-02-15 12:11:46 +01:00
* doc/as.texinfo (.section): Document that numeric values can now
be used for the flags and type fields of the ELF target's .section
directive. Add notes about the restrictions on setting flags and
types.
* config/obj-elf.c (obj_elf_change_section): Allow known sections
to be given processor specific section types. Allow processor and
application specific flags of a section to be set after
definition.
(obj_elf_parse_section_letters): Handle parsing numeric values.
(obj_elf_section_type): Handle parsing numeric values.
(obj_elf_section): Allow numeric type values.
* config/obj-elf.h (obj_elf_change_section): Update prototype.
* testsuite/gas/elf/section10.d: New test.
* testsuite/gas/elf/section10.s: Source file for new test.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
the description of the flags produced by readelf.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
* NEWS: Mention the new feature.
2016-02-11 Nick Clifton <nickc@redhat.com>
PR gas/19614
* dw2gencfi.c (cfi_sections_set): Delay setting this variable
until it is actually used.
(cfi_set_sections): Set cfi_sections_set to true.
(dot_cfi_startproc): Likewise.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
(dot_cfi_sections): Do not set cfi_sections_set.
* doc/as.texinfo (.cfi_sections): Note that targets can provide
their own cfi section name. Also note that the directive can be
reissued provided that CFI generation has not started.
* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
.cfi_endproc directives so that the redefinition of .cfi_sections
will trigger the generation of the error message.
* testsuite/gas/mips/compact-eh-err2.l: Update expected line
number of error message.
Add support for ARC instruction relaxation in the assembler. gas/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS) (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE): Define. (arc_flags, arc_relax_type): New structure. * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY) (RELAX_TABLE_ENTRY_MAX): New define. (relaxation_state, md_relax_table, arc_relaxable_insns) (arc_num_relaxable_ins): New variable. (rlx_operand_type, arc_rlx_types): New enums. (arc_relaxable_ins): New structure. (OPTION_RELAX): New option. (arc_insn): New relax member. (arc_flags): Remove. (relax_insn_p): New function. (apply_fixups): Likewise. (relaxable_operand): Likewise. (may_relax_expr): Likewise. (relaxable_flag): Likewise. (arc_pcrel_adjust): Likewise. (md_estimate_size_before_relax): Implement. (md_convert_frag): Likewise. (md_parse_option): Handle new mrelax option. (md_show_usage): Likewise. (assemble_insn): Set relax member. (emit_insn0): New function. (emit_insn1): Likewise. (emit_insn): Handle relaxation case. * NEWS: Mention the new relaxation option. * doc/c-arc.texi (ARC Options): Document new mrelax option. gas/testsuite 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> * gas/arc/relax-avoid1.d: New file. * gas/arc/relax-avoid1.s: Likewise. * gas/arc/relax-avoid2.d: Likewise. * gas/arc/relax-avoid2.s: Likewise. * gas/arc/relax-avoid3.d: Likewise. * gas/arc/relax-avoid3.s: Likewise. * gas/arc/relax-b.d: Likewise. * gas/arc/relax-b.s: Likewise. include/opcode/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes): Declare. opcodes/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New variable.
2016-02-10 13:09:01 +01:00
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
* doc/as.texinfo (Target ARC Options): Likewise.
* testsuite/gas/arc/relax-avoid1.d: New file.
* testsuite/gas/arc/relax-avoid1.s: Likewise.
* testsuite/gas/arc/relax-avoid2.d: Likewise.
* testsuite/gas/arc/relax-avoid2.s: Likewise.
* testsuite/gas/arc/relax-avoid3.d: Likewise.
* testsuite/gas/arc/relax-avoid3.s: Likewise.
* testsuite/gas/arc/relax-b.d: Likewise.
* testsuite/gas/arc/relax-b.s: Likewise.
2016-02-08 Nick Clifton <nickc@redhat.com>
* config/tc-ia64.c (dot_prologue): Fix formatting.
2016-02-04 Nick Clifton <nickc@redhat.com>
* config/obj-elf.c (obj_elf_change_section): Remove support for
ARM NOREAD sections.
* config/tc-arm.c (arm_elf_section_letter): Delete.
* config/tc-arm.h (md_elf_section_letter): Delete.
* doc/c-arm.texi (ARM Section Attribute): Delete section.
* testsuite/gas/arm/section-execute-only.d: Delete.
* testsuite/gas/arm/section-execute-only.s: Delete.
2016-02-04 Nick Clifton <nickc@redhat.com>
PR target/19561
* config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
substitutions for BFD_RELOC_* as unsigned.
* testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests.
* testsuite/gas/xtensa/loc.d: New file: loc test result patterns.
* testsuite/gas/xtensa/loc.s: New file: loc test.
msp430: Set DWARF2_ADDR_SIZE to 4. This change makes gas's notion of the msp430 dwarf2 address size match that of gcc and gdb. This is needed so that the format of addresses generated for DW_LNE_set_address in .debug_line will match the address size for the compilation unit. In gcc/config/msp430/msp430.h, it's set to 4: #define DWARF2_ADDR_SIZE 4 Likewise in gdb/msp430-tdep.c: set_gdbarch_dwarf2_addr_size (gdbarch, 4); (As far as I can tell, however, GDB doesn't use this value when decoding .debug_line. Instead, GDB uses the Pointer Size from the compilation unit.) readelf is able to seamlessly handle mismatches between these various sizes by using the size of the DW_LNE_set_address instruction to determine the address size. Another way to fix this problem is to make GDB behave in a similar manner. In my opinion, GDB should detect and inform the user about these mismatches; it's not clear to me if it's correct for GDB to go ahead and read the address anyway when a size mismatch is detected. Without this change, addresses in .debug_line are encoded in two bytes for some multilibs. When GDB reads the address for DW_LNE_set_address, it uses the pointer size provided by the CU. When these values don't match, GDB reads the wrong number of bytes. In the cases that I've looked at, GDB is reading 4 bytes from a 2 byte container, which results in a garbage address. GDB discards lines which have a bogus address; the end result is that GDB records no line number information for CUs which have a mismatch between the address size (from the CU) and the format of the address used by DW_LNE_set_address. gas/ChangeLog: * config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-27 20:44:38 +01:00
2016-02-03 Kevin Buettner <kevinb@redhat.com>
2016-04-07 15:43:14 +02:00
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
msp430: Set DWARF2_ADDR_SIZE to 4. This change makes gas's notion of the msp430 dwarf2 address size match that of gcc and gdb. This is needed so that the format of addresses generated for DW_LNE_set_address in .debug_line will match the address size for the compilation unit. In gcc/config/msp430/msp430.h, it's set to 4: #define DWARF2_ADDR_SIZE 4 Likewise in gdb/msp430-tdep.c: set_gdbarch_dwarf2_addr_size (gdbarch, 4); (As far as I can tell, however, GDB doesn't use this value when decoding .debug_line. Instead, GDB uses the Pointer Size from the compilation unit.) readelf is able to seamlessly handle mismatches between these various sizes by using the size of the DW_LNE_set_address instruction to determine the address size. Another way to fix this problem is to make GDB behave in a similar manner. In my opinion, GDB should detect and inform the user about these mismatches; it's not clear to me if it's correct for GDB to go ahead and read the address anyway when a size mismatch is detected. Without this change, addresses in .debug_line are encoded in two bytes for some multilibs. When GDB reads the address for DW_LNE_set_address, it uses the pointer size provided by the CU. When these values don't match, GDB reads the wrong number of bytes. In the cases that I've looked at, GDB is reading 4 bytes from a 2 byte container, which results in a garbage address. GDB discards lines which have a bogus address; the end result is that GDB records no line number information for CUs which have a mismatch between the address size (from the CU) and the format of the address used by DW_LNE_set_address. gas/ChangeLog: * config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-27 20:44:38 +01:00
Add -mrelax-relocations= to x86 assembler The x86 relax relocations introduced in binutils 2.26 aren't supported by linker on Solaris older than Solaris 12. To use x86 assembler with older Solaris linker, this patch adds 1. A command line option -mrelax-relocations= to x86 assembler to control whether to generate relax relocations. 2. A configure option --enable-x86-relax-relocations to decide whether x86 assembler should generate relax relocations by default. It is defaulted to yes, except for x86 Solaris targets older than Solaris 12. gas/ PR gas/19520 * NEWS: Mention new command line option -mrelax-relocations and new configure option --enable-x86-relax-relocations for x86 target. * config.in: Regenerated. * configure.ac: Add --enable-x86-relax-relocations. (ac_default_x86_relax_relocations): New. Default to 1 except for x86 Solaris targets older than Solaris 12. (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define. * configure: Likewise. * config/tc-i386.c (generate_relax_relocations): New. (OPTION_MRELAX_RELOCATIONS): Likewise. (output_disp): Don't generate relax relocations if generate_relax_relocations is 0. (md_longopts): Add -mrelax-relocations. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS. * doc/c-i386.texi: Document -mrelax-relocations=. * testsuite/gas/i386/got-no-relax.d: New file. * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise. * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as. * testsuite/gas/i386/localpic.d: Likewise. * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise. * testsuite/gas/i386/reloc32.d: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. * testsuite/gas/i386/i386.exp: Run got-no-relax and x86-64-gotpcrel-no-relax. ld/ PR gas/19520 * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as. * testsuite/ld-i386/call1.d: Likewise. * testsuite/ld-i386/call2.d: Likewise. * testsuite/ld-i386/call3a.d: Likewise. * testsuite/ld-i386/call3b.d: Likewise. * testsuite/ld-i386/call3c.d: Likewise. * testsuite/ld-i386/call3d.d: Likewise. * testsuite/ld-i386/call3e.d: Likewise. * testsuite/ld-i386/call3f.d: Likewise. * testsuite/ld-i386/call3g.d: Likewise. * testsuite/ld-i386/call3h.d: Likewise. * testsuite/ld-i386/jmp1.d: Likewise. * testsuite/ld-i386/jmp2.d: Likewise. * testsuite/ld-i386/lea1c.d: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/load2.d: Likewise. * testsuite/ld-i386/load3.d: Likewise. * testsuite/ld-i386/load4a.d: Likewise. * testsuite/ld-i386/load5a.d: Likewise. * testsuite/ld-i386/mov2b.d: Likewise. * testsuite/ld-i386/mov3.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-x86-64/call1a.d: Likewise. * testsuite/ld-x86-64/call1b.d: Likewise. * testsuite/ld-x86-64/call1c.d: Likewise. * testsuite/ld-x86-64/call1d.d: Likewise. * testsuite/ld-x86-64/call1e.d: Likewise. * testsuite/ld-x86-64/call1f.d: Likewise. * testsuite/ld-x86-64/call1h.d: Likewise. * testsuite/ld-x86-64/call1i.d: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it. * testsuite/ld-i386/got1.dd: Updated. * testsuite/ld-i386/got1d.S (1): Removed. * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-02-03 17:25:15 +01:00
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19520
* NEWS: Mention new command line option -mrelax-relocations and
new configure option --enable-x86-relax-relocations for x86
target.
* config.in: Regenerated.
* configure.ac: Add --enable-x86-relax-relocations.
(ac_default_x86_relax_relocations): New. Default to 1 except
for x86 Solaris targets older than Solaris 12.
(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
* configure: Likewise.
* config/tc-i386.c (generate_relax_relocations): New.
(OPTION_MRELAX_RELOCATIONS): Likewise.
(output_disp): Don't generate relax relocations if
generate_relax_relocations is 0.
(md_longopts): Add -mrelax-relocations.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
* doc/c-i386.texi: Document -mrelax-relocations=.
* testsuite/gas/i386/got-no-relax.d: New file.
* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
* testsuite/gas/i386/localpic.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
* testsuite/gas/i386/reloc32.d: Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/i386.exp: Run got-no-relax and
x86-64-gotpcrel-no-relax.
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention new command line option -mfence-as-lock-add=yes
for x86 target.
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Remove duplicated marker for 2.26.
2016-02-02 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/ip2k/allinsn.d: New file.
* testsuite/gas/ip2k/allinsn.s: New file.
* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
suffixes from instruction mnemonics in expected output.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/addr-syntax.d: Update expected register
names.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/epiphany/sample.d: Update expected output.
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07 15:43:14 +02:00
* config/tc-arc.c (md_apply_fix): Allow addendum.
(arc_reloc_op): Allow complex expressions for tpoff.
(md_apply_fix): Handle resolved TLS local symbol.
* testsuite/gas/arc/tls-relocs1.d: New file.
* testsuite/gas/arc/tls-relocs1.s: Likewise.
2016-02-01 Loria <Loria@phantasia.org>
PR target/19311
* config/tc-arm.c (encode_arm_immediate): Recode to improve
efficiency and avoid an LLVM loop optimization bug.
2016-02-01 Nick Clifton <nickc@redhat.com>
* config/tc-microblaze.c (parse_imm): Fix compile time warning
message extending a negative 32-bit value into a larger signed
value on a 32-bit host.
2016-01-29 H.J. Lu <hongjiu.lu@intel.com>
PR gas/19532
* configure.ac (compressed_debug_sections): Replace == with =.
* configure: Regenerated.
2016-01-29 Andrew Senkevich <andrew.senkevich@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (avoid_fence): New.
(output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
is true.
(OPTION_FENCE_AS_LOCK_ADD): New.
(md_longopts): Add -mfence-as-lock-add.
(md_parse_option): Handle -mfence-as-lock-add.
(md_show_usage): Add -mfence-as-lock-add=[no|yes].
* doc/c-i386.texi (-mfence-as-lock-add): Document.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/fence-as-lock-add.s: New.
* testsuite/gas/i386/fence-as-lock-add-yes.d: Likewise.
* testsuite/gas/i386/fence-as-lock-add-no.d: Likewise.
* testsuite/gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
* testsuite/gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-27 H.J. Lu <hongjiu.lu@intel.com>
* configure.ac (compressed_debug_sections): Remove trailing `]'.
* configure: Regenerated.
2016-01-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ...
(OPTION_MOMIT_LOCK_PREFIX): This.
(md_longopts): Updated.
(md_parse_option): Likewise.
2016-01-25 Catherine Moore <clm@codesourcery.com>
* config/mips/tc-mips.c (md_begin): Avoid gp-relative addressing
if abicalls are in effect.
* testsuite/gas/mips/sdata-gp.s: New test.
* testsuite/gas/mips/sdata-gp.d: New expected output
* testsuite/gas/mips/mips.exp: Run new test.
2016-01-25 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/thumb2_it_search.d: New.
* testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-21 Nick Clifton <nickc@redhat.com>
PR gas/19454
* testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope
with arm-netbsdelf target.
* testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
2016-01-20 Nick Clifton <nickc@redhat.com>
PR 19456
* testsuite/gas/arm/weakdef-1.d: Skip for VxWorks.
* testsuite/gas/arm/blx-bl-convert.d
* testsuite/gas/arm/plt-1.d: Likewise.
* testsuite/gas/arm/reloc-bad.d: Likewise.
* testsuite/gas/arm/thumb-w-good.d: Likewise.
* testsuite/gas/arm/thumb2_pool.d: Likewise.
* testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks
* testsuite/gas/arm/tls_vxworks.d: Update expected output.
PR 19499
* doc/as.texinfo (Errors): Correct documentation describing the
interaction of .file and .line with warning and error messages.
PR 19458
* testsuite/gas/arm/armv8_2-a.d: Skip for COFF based targets.
* testsuite/gas/arm/archv8m-main.d: Likewise.
* testsuite/gas/arm/archv8m-base.d: Likewise.
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.
2016-01-20 Mickael Guene <mickael.guene@st.com>
Terry Guo <terry.guo@arm.com>
* config/obj-elf.c (obj_elf_change_section) : Allow arm section with
SHF_ARM_NOREAD section flag.
* config/tc-arm.h (md_elf_section_letter) : Implement this hook to
handle letter 'y'.
(arm_elf_section_letter) : Declare it.
* config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
SHF_ARM_NOREAD section flag.
* doc/c-arm.texi (ARM section attribute): Document the 'y' attribute.
* testsuite/gas/arm/section-execute-only.s: New test case.
* testsuite/gas/arm/section-execute-only.d: Expected output.
2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
2016-01-18 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2016-01-17 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2016-01-17 Alan Modra <amodra@gmail.com>
* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
2016-01-14 Nick Clifton <nickc@redhat.com>
* testsuite/gas/rl78/sp-relative-movw.s: New test.
* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
* testsuite/gas/rl78/rl78.exp: Run the new test.
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-2.l: New.
* testsuite/gas/aarch64/illegal-sysreg-2.d: New.
2016-01-13 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-nios2.c (output_movia): Preset `code' to 0.
2016-01-13 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/tc-h8300.c (get_operand): Remove spurious condition in
test for closing parenthesis.
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): New.
(insns): Add "esb".
* testsuite/gas/arm/armv8_2-a.d: New.
* testsuite/gas/arm/armv8_2-a.s: New.
2016-01-12 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/vsx3.d: Accept nop padding.
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
xvcmpnesp, xvcmpnesp.>: Delete tests.
* testsuite/gas/ppc/power9.s: Likewise.
* testsuite/gas/ppc/vsx3.d: Likewise.
* testsuite/gas/ppc/vsx3.s: Likewise.
2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
PR gas/13050
* testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2.
* testsuite/gas/m68k/p13050-1.s: New file.
* testsuite/gas/m68k/p13050-2.d: New file.
* testsuite/gas/m68k/p13050-2.s: New file.
bfd/arc: Add R_ prefix to all relocation names The convention within for relocation names is that they start with the string "R_", however, this is not so for ARC for the display names of relocations, however, internally, the names for the relocations types do have the 'R_' prefix. I suspect that the missing 'R_' on the output strings was an oversight, as I can't see any comment to the contrary. To bring ARC into line with other targets, this commit adds the 'R_' prefix to the output strings used for relocation names, and updates all of the assembler tests where this was exposed. bfd/ChangeLog: * elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to place 'R_' before the reloc name returned. (elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before the relocation string. gas/ChangeLog: * testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names. * testsuite/gas/arc/add.d: Likewise. * testsuite/gas/arc/and.d: Likewise. * testsuite/gas/arc/asl.d: Likewise. * testsuite/gas/arc/asr.d: Likewise. * testsuite/gas/arc/bic.d: Likewise. * testsuite/gas/arc/extb.d: Likewise. * testsuite/gas/arc/extw.d: Likewise. * testsuite/gas/arc/j.d: Likewise. * testsuite/gas/arc/jl.d: Likewise. * testsuite/gas/arc/ld2.d: Likewise. * testsuite/gas/arc/lsr.d: Likewise. * testsuite/gas/arc/mov.d: Likewise. * testsuite/gas/arc/or.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/rlc.d: Likewise. * testsuite/gas/arc/ror.d: Likewise. * testsuite/gas/arc/rrc.d: Likewise. * testsuite/gas/arc/sbc.d: Likewise. * testsuite/gas/arc/sda-relocs.d: Likewise. * testsuite/gas/arc/sda-relocs2.d: Likewise. * testsuite/gas/arc/sexb.d: Likewise. * testsuite/gas/arc/sexw.d: Likewise. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/sub.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/xor.d: Likewise.
2016-01-05 15:46:39 +01:00
2016-01-06 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
* testsuite/gas/arc/add.d: Likewise.
* testsuite/gas/arc/and.d: Likewise.
* testsuite/gas/arc/asl.d: Likewise.
* testsuite/gas/arc/asr.d: Likewise.
* testsuite/gas/arc/bic.d: Likewise.
* testsuite/gas/arc/extb.d: Likewise.
* testsuite/gas/arc/extw.d: Likewise.
* testsuite/gas/arc/j.d: Likewise.
* testsuite/gas/arc/jl.d: Likewise.
* testsuite/gas/arc/ld2.d: Likewise.
* testsuite/gas/arc/lsr.d: Likewise.
* testsuite/gas/arc/mov.d: Likewise.
* testsuite/gas/arc/or.d: Likewise.
* testsuite/gas/arc/pcl-relocs.d: Likewise.
* testsuite/gas/arc/pcrel-relocs.d: Likewise.
* testsuite/gas/arc/pic-relocs.d: Likewise.
* testsuite/gas/arc/plt-relocs.d: Likewise.
* testsuite/gas/arc/rlc.d: Likewise.
* testsuite/gas/arc/ror.d: Likewise.
* testsuite/gas/arc/rrc.d: Likewise.
* testsuite/gas/arc/sbc.d: Likewise.
* testsuite/gas/arc/sda-relocs.d: Likewise.
* testsuite/gas/arc/sda-relocs2.d: Likewise.
* testsuite/gas/arc/sexb.d: Likewise.
* testsuite/gas/arc/sexw.d: Likewise.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/sub.d: Likewise.
* testsuite/gas/arc/tls-relocs.d: Likewise.
* testsuite/gas/arc/xor.d: Likewise.
2016-01-01 12:25:12 +01:00
2016-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
For older changes see ChangeLog-2015 and testsuite/ChangeLog-2015
Copyright (C) 2016 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
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