Rename PowerPC64 pcrel GOT TLS relocations
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
2020-06-06 04:26:20 +02:00
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2020-06-06 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c: Update throughout for reloc renaming.
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2020-06-05 16:23:30 +02:00
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2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com>
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* config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
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stringop-overflow.
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2020-05-29 09:31:46 +02:00
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2020-06-05 Nelson Chu <nelson.chu@sifive.com>
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* config/tc-riscv.c (explicit_csr): New static boolean.
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Used to indicate CSR are explictly used.
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(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
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(riscv_write_out_attrs): If we already have set elf priv
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attributes, then generate them. Otherwise, don't generate
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them when no CSR are used.
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* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
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* testsuite/gas/riscv/attribute-02.d: Likewise.
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* testsuite/gas/riscv/attribute-03.d: Likewise.
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* testsuite/gas/riscv/attribute-04.d: Likewise.
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* testsuite/gas/riscv/attribute-05.d: Likewise.
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* testsuite/gas/riscv/attribute-06.d: Likewise.
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* testsuite/gas/riscv/attribute-07.d: Likewise.
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* testsuite/gas/riscv/attribute-08.d: Likewise.
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* testsuite/gas/riscv/attribute-09.d: Likewise.
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* testsuite/gas/riscv/attribute-10.d: Likewise.
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* testsuite/gas/riscv/attribute-unknown.d: Likewise.
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* testsuite/gas/riscv/attribute-11.s: New testcase.
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* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
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used, so we should output the ELF priv attributes.
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* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
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used, so output the priv attributes according to the -mpriv-spec.
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* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
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used, so ignore the -mpriv-spec setting.
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2020-06-04 20:15:06 +02:00
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2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
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cgen_get_insn_value.
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* config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
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endianness to cgen_get_insn_value and cgen_put_insn_value.
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2020-06-04 16:33:34 +02:00
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2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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* config/tc-bpf.c (md_apply_fix): Simplify and avoid using
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cgen_put_insn_value.
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2020-06-04 16:17:07 +02:00
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2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
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bpf_cgen_cpu_open.
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(md_assemble): Remove no longer needed hack.
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opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
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2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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* cgen.c (gas_cgen_finish_insn): Pass the endianness to
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cgen_put_insn_value.
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(gas_cgen_md_apply_fix): Likewise.
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(gas_cgen_md_apply_fix): Likewise.
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* config/tc-bpf.c (md_apply_fix): Pass data endianness to
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cgen_put_insn_value.
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* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
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cgen_put_insn_value.
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2020-06-04 08:30:46 +02:00
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2020-06-04 Alan Modra <amodra@gmail.com>
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* testsuite/config/default.exp: Remove global directive outside
|
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proc body.
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* testsuite/gas/mep/complex-relocs.exp: Likewise.
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* testsuite/gas/microblaze/relax_size.exp: Likewise.
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* testsuite/gas/microblaze/reloc_sym.exp: Likewise.
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* testsuite/gas/mt/relocs.exp: Likewise.
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* testsuite/gas/rx/rx.exp: Likewise.
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2020-06-03 22:42:54 +02:00
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2020-06-03 Stephen Casner <casner@acm.org>
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* doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.
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2020-06-03 03:36:14 +02:00
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2020-06-02 Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
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Jim Wilson <jimw@sifive.com>
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PR 26051
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* doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
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simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B
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formats using simm12(rs1). Correct SB and B to use rs1 and rs2.
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Move B before SB. Move J before UJ.
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2020-05-29 17:04:50 +02:00
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2020-06-01 Alex Coplan <alex.coplan@arm.com>
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* write.c (relax_segment): Fix handling of negative offset when
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relaxing an rs_org frag.
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* testsuite/gas/aarch64/org-neg.d: New test.
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* testsuite/gas/aarch64/org-neg.l: Error output for test.
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* testsuite/gas/aarch64/org-neg.s: Input for test.
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* testsuite/gas/arm/org-neg.d: New test.
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* testsuite/gas/arm/org-neg.l: Error output for test.
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* testsuite/gas/arm/org-neg.s: Input for test.
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2020-05-28 19:11:59 +02:00
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2020-05-28 Stephen Casner <casner@acm.org>
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Fix unexpected failures in gas testsuite for pdp11-aout target.
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These are caused by the PDP11's mix of little-endian octets in
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shorts but shorts in big endian order for long or quad.
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* config/tc-pdp11.c (md_number_to_chars): Implement .quad
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* testsuite/gas/all/gas.exp: Select alternate test scripts for
|
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pdp11, skip octa test completely.
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* testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
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* testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
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* testsuite/gas/all/cond-pdp11.l: Match different octet order.
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2020-05-28 15:30:34 +02:00
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2020-05-28 Alex Coplan <alex.coplan@arm.com>
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* frags.c (frag_grow): Fix comment.
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2020-05-28 03:40:38 +02:00
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2020-05-27 Stephen Casner <casner@acm.org>
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PR gas/26001
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* config/tc-pdp11.c (parse_reg): Distinguish register names from
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symbols that begin with a register name.
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* testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
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* testsuite/gas/pdp11/pr26001.s: Likewise.
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* testsuite/gas/pdp11/pr26001.d: Likewise.
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2020-05-27 18:34:58 +02:00
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2020-05-27 Simon Cook <simon.cook@embecosm.com>
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* config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
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pointer when creating struct riscv_csr_extra.
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2020-05-26 23:17:09 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
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* testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
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* testsuite/gas/i386/inval-avx512f.l: Updated.
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2020-05-26 18:34:39 +02:00
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2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
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* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
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load/store instruction variants with alignment hints.
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* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
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instruction variants with alignment hints.
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2020-05-26 18:33:48 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26044
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* config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X
|
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instead of R_XGATE_PCREL_X.
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(xgate_parse_operand): Replace R_XGATE_PCREL_X with
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BFD_RELOC_XGATE_PCREL_X.
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2020-05-26 16:54:05 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26044
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* config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal
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with &fragP->fr_literal[0].
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2020-05-26 16:41:07 +02:00
|
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26044
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* config/tc-vax.c (md_estimate_size_before_relax): Replace
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fragP->fr_literal with &fragP->fr_literal[0].
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(md_convert_frag): Likewise.
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2020-05-26 15:56:18 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26044
|
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* config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal
|
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with &fragP->fr_literal[0].
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2020-05-26 15:46:26 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
|
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PR gas/26044
|
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* config/tc-crx.c (getreg_image): Change argument type to int.
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(md_convert_frag): Replace fragP->fr_literal with
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&fragP->fr_literal[0].
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2020-05-26 15:09:54 +02:00
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2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26044
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* onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping
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sprintf with memmove.
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2020-05-26 04:37:54 +02:00
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2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal
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with &fragP->fr_literal[0].
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2020-05-26 04:29:22 +02:00
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2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26041
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* config/tc-cr16.c (md_assemble): Use memmove to concatenate
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2 overlapping strings.
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2020-05-26 01:17:50 +02:00
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2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal
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with &fragP->fr_literal[0].
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2020-05-25 13:50:56 +02:00
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2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal
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with &fragp->fr_literal[0].
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* config/tc-microblaze.c (md_apply_fix): Likewise.
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* config/tc-sh.c (md_convert_frag): Likewise.
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2020-05-25 01:42:21 +02:00
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2020-05-24 Jim Wilson <jimw@sifive.com>
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PR 26025
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* config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
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asection to segT. New locals seg and subseg. Call subseg_set before
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fix_new_exp. Call subseg_set after loop to restore original values.
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2020-05-20 15:19:01 +02:00
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2020-05-21 Alan Modra <amodra@gmail.com>
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* atof-generic.c: Replace "if (x) free (x)" with "free (x)"
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throughout.
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* config/obj-elf.c: Likewise.
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* config/tc-aarch64.c: Likewise.
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* config/tc-arm.c: Likewise.
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* config/tc-m68k.c: Likewise.
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* config/tc-nios2.c: Likewise.
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* config/tc-tic30.c: Likewise.
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* ecoff.c: Likewise.
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* read.c: Likewise.
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* stabs.c: Likewise.
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* symbols.c: Likewise.
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* testsuite/gas/all/test-gen.c: Likewise.
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[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
2020-05-20 18:22:48 +02:00
|
|
|
|
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
|
|
|
|
|
|
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
|
|
|
|
|
|
Static variables which are used to set the ISA extensions. You can
|
|
|
|
|
|
use -march (or ELF build attributes) and -misa-spec to set them,
|
|
|
|
|
|
respectively.
|
|
|
|
|
|
(ext_version_hash): The hash table used to handle the extensions
|
|
|
|
|
|
with versions.
|
|
|
|
|
|
(init_ext_version_hash): Initialize the ext_version_hash according
|
|
|
|
|
|
to riscv_ext_version_table.
|
|
|
|
|
|
(riscv_get_default_ext_version): The callback function of
|
|
|
|
|
|
riscv_parse_subset_t. According to the choosed ISA spec,
|
|
|
|
|
|
get the default version for the specific extension.
|
|
|
|
|
|
(riscv_set_arch): Set the callback function.
|
|
|
|
|
|
(enum options, struct option md_longopts): Add new option -misa-spec.
|
|
|
|
|
|
(md_parse_option): Do not call riscv_set_arch for -march. We will
|
|
|
|
|
|
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
|
|
|
|
|
|
to set default_isa_spec class.
|
|
|
|
|
|
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
|
|
|
|
|
|
ext_version_hash, and then call riscv_set_arch to set the architecture
|
|
|
|
|
|
with versions according to default_arch_with_ext.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
|
|
|
|
|
|
x extensions.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-03.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
|
|
|
|
|
|
already set it's version to 2p1 by march, so no need to use the default
|
|
|
|
|
|
2p2 version. For m-ext, we do not set the version by -march and ELF arch
|
|
|
|
|
|
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
|
|
|
|
|
|
ISA spec 2p2, so set 0p0 to it.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
|
|
|
|
|
|
zicsr is 2p0 according to ISA spec 20191213.
|
|
|
|
|
|
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
|
|
|
|
|
|
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
|
|
|
|
|
|
You can set them by configure options --with-arch and
|
|
|
|
|
|
--with-isa-spec, respectively.
|
|
|
|
|
|
(riscv_set_default_isa_spec): New function used to set the
|
|
|
|
|
|
default ISA spec.
|
|
|
|
|
|
(md_parse_option): Call riscv_set_default_isa_spec rather than
|
|
|
|
|
|
call riscv_get_isa_spec_class directly.
|
|
|
|
|
|
(riscv_after_parse_args): If the -isa-spec is not set, then we
|
|
|
|
|
|
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
|
|
|
|
|
|
calling riscv_set_default_isa_spec.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
|
|
|
|
|
|
the --with-isa-spec may be set to different ISA spec.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-03.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-04.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-05.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-06.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-07.d: Likewise.
|
|
|
|
|
|
* configure.ac: Add configure options, --with-arch and
|
|
|
|
|
|
--with-isa-spec.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* config.in: Regenerated.
|
|
|
|
|
|
* config/tc-riscv.c (default_priv_spec): Static variable which is
|
|
|
|
|
|
used to check if the CSR is valid for the chosen privilege spec. You
|
|
|
|
|
|
can use -mpriv-spec to set it.
|
|
|
|
|
|
(enum reg_class): We now get the CSR address from csr_extra_hash rather
|
|
|
|
|
|
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
|
|
|
|
|
|
(riscv_init_csr_hashes): Only need to initialize one hash table
|
|
|
|
|
|
csr_extra_hash.
|
|
|
|
|
|
(riscv_csr_class_check): Change the return type to void. Don't check
|
|
|
|
|
|
the ISA dependency if -mcsr-check isn't set.
|
|
|
|
|
|
(riscv_csr_version_check): New function. Check and find the CSR address
|
|
|
|
|
|
from csr_extra_hash, according to default_priv_spec. Report warning
|
|
|
|
|
|
for the invalid CSR if -mcsr-check is set.
|
|
|
|
|
|
(reg_csr_lookup_internal): Updated.
|
|
|
|
|
|
(reg_lookup_internal): Likewise.
|
|
|
|
|
|
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
|
|
|
|
|
|
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
|
|
|
|
|
|
(md_parse_option): Call riscv_set_default_priv_version to set
|
|
|
|
|
|
default_priv_spec.
|
|
|
|
|
|
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
|
|
|
|
|
|
privilege spec to the newest one.
|
|
|
|
|
|
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
|
|
|
|
|
|
include/opcode/riscv.h.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
|
|
|
|
|
|
to check the ISA dependency for CSR, so fix the spec version by adding
|
|
|
|
|
|
-mpriv-spec=1.11.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
|
|
|
|
|
|
version warnings for the test case.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
|
|
|
|
|
|
Check whether the CSR is valid when privilege version 1.9 is choosed.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
|
|
|
|
|
|
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
|
|
|
|
|
|
Check whether the CSR is valid when privilege version 1.10 is choosed.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
|
|
|
|
|
|
Check whether the CSR is valid when privilege version 1.11 is choosed.
|
|
|
|
|
|
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
|
|
|
|
|
|
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
|
|
|
|
|
|
setting. You can set it by configure option --with-priv-spec.
|
|
|
|
|
|
(riscv_set_default_priv_spec): New function used to set the default
|
|
|
|
|
|
privilege spec.
|
|
|
|
|
|
(md_parse_option): Call riscv_set_default_priv_spec rather than
|
|
|
|
|
|
call riscv_get_priv_spec_class directly.
|
|
|
|
|
|
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
|
|
|
|
|
|
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
|
|
|
|
|
|
calling riscv_set_default_priv_spec.
|
|
|
|
|
|
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
|
|
|
|
|
|
the --with-priv-spec may be set to different privilege spec.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.d: Likewise.
|
|
|
|
|
|
* configure.ac: Add configure option --with-priv-spec.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* config.in: Regenerated.
|
|
|
|
|
|
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
|
|
|
|
|
|
explicit_attr. Set it to TRUE if any ELF attribute is found.
|
|
|
|
|
|
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
|
|
|
|
|
|
the priv attributes are set.
|
|
|
|
|
|
(md_assemble): Set the default_priv_spec according to the priv
|
|
|
|
|
|
attributes when we start to assemble instruction.
|
|
|
|
|
|
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
|
|
|
|
|
|
riscv_write_out_attrs. Update the arch and priv attributes. If we
|
|
|
|
|
|
don't set the corresponding ELF attributes, then try to output the
|
|
|
|
|
|
default ones.
|
|
|
|
|
|
(riscv_set_public_attributes): If any ELF attribute or -march-attr
|
|
|
|
|
|
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
|
|
|
|
|
|
to update the arch and priv attributes.
|
|
|
|
|
|
(s_riscv_attribute): Make sure all arch and priv attributes are set
|
|
|
|
|
|
before any instruction.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
|
|
|
|
|
|
ELF attribute or -march-attr is set. If the priv attributes are not
|
|
|
|
|
|
set, then try to update them by the default setting (-mpriv-spec or
|
|
|
|
|
|
--with-priv-spec).
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-03.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-04.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-06.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-07.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-08.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-09.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-10.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
|
|
|
|
|
|
set by priv attributes must be supported.
|
|
|
|
|
|
* testsuite/gas/riscv/attribute-05.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
|
|
|
|
|
|
priv attributes according to the -mpriv-spec option.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.d: Removed.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
|
|
|
|
|
|
CSR according to the priv spec 1.9.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
|
|
|
|
|
|
CSR according to the priv spec 1.9.1.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
|
|
|
|
|
|
CSR according to the priv spec 1.10.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
|
|
|
|
|
|
CSR according to the priv spec 1.11.
|
|
|
|
|
|
* config/tc-riscv.c (md_show_usage): Add descriptions about
|
|
|
|
|
|
the new GAS options.
|
|
|
|
|
|
* doc/c-riscv.texi: Likewise.
|
|
|
|
|
|
|
Power10 dcbf, sync, and wait extensions.
opcodes/
* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
WC values on POWER10 sync, dcbf and wait instructions.
(insert_pl, extract_pl): New functions.
(L2OPT, LS, WC): Use insert_ls and extract_ls.
(LS3): New , 3-bit L for sync.
(LS3, L3OPT): New, 3-bit L for sync and dcbf.
(SC2, PL): New, 2-bit SC and PL for sync and wait.
(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
(XOPL3, XWCPL, XSYNCLS): New opcode macros.
(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
<wait>: Enable PL operand on POWER10.
<dcbf>: Enable L3OPT operand on POWER10.
<sync>: Enable SC2 operand on POWER10.
gas/
* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
sync, wait, waitrsv>: Add tests.
* testsuite/gas/ppc/power10.d: Likewise.
2020-05-20 01:09:51 +02:00
|
|
|
|
2020-05-19 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
|
|
|
|
|
|
pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
|
|
|
|
|
|
sync, wait, waitrsv>: Add tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power10.d: Likewise.
|
|
|
|
|
|
|
2020-05-19 13:45:42 +02:00
|
|
|
|
2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25992
|
|
|
|
|
|
* config/tc-arm.c : Add arm_ext_v8r feature.
|
|
|
|
|
|
(it_fsm_post_encode): Check arm_ext_v8r feature.
|
|
|
|
|
|
(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.
|
|
|
|
|
|
|
2020-05-19 05:25:27 +02:00
|
|
|
|
2020-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (write_contents): Use bfd_get_filename rather than
|
|
|
|
|
|
accessing bfd->filename directly. Use bfd_section_name rather
|
|
|
|
|
|
than accessing section->name directly.
|
|
|
|
|
|
|
2020-05-18 07:00:06 +02:00
|
|
|
|
2020-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* symbols.c (local_symbol_make): Init all of lsy_flags.
|
|
|
|
|
|
|
2020-05-18 06:00:59 +02:00
|
|
|
|
2020-05-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK
|
|
|
|
|
|
before looking at add_symbol->sy_flags.
|
|
|
|
|
|
|
2020-05-09 09:02:50 +02:00
|
|
|
|
2020-05-18 Hongtao Liu <hongtao.liu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c: Not handle lret/iret.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-b.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-c.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-d.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret.s: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
|
|
|
|
|
|
|
2020-05-15 10:36:05 +02:00
|
|
|
|
2020-05-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
Alex Coplan <alex.coplan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* symbols.c (struct local_symbol): Update comment.
|
|
|
|
|
|
(resolve_symbol_value): For resolved symbols equated to other
|
|
|
|
|
|
symbols, verify that the referenced symbol is not a local_symbol
|
|
|
|
|
|
before accessing sy_value. Don't leave symbol loops during
|
|
|
|
|
|
finalize_syms resolution.
|
|
|
|
|
|
* testsuite/gas/all/assign-bad-recursive.d: New test.
|
|
|
|
|
|
* testsuite/gas/all/assign-bad-recursive.l: Error output for test.
|
|
|
|
|
|
* testsuite/gas/all/assign-bad-recursive.s: Assembly for test.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Run it.
|
|
|
|
|
|
|
2020-05-14 12:26:26 +02:00
|
|
|
|
2020-05-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2020-05-11 02:19:29 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/scalarquad.d,
|
|
|
|
|
|
* testsuite/gas/ppc/scalarquad.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:18:29 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/rightmost.d,
|
|
|
|
|
|
* testsuite/gas/ppc/rightmost.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:17:38 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/xvtlsbb.d,
|
|
|
|
|
|
* testsuite/gas/ppc/xvtlsbb.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 string operations
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
* testsuite/gas/ppc/stringop.d,
* testsuite/gas/ppc/stringop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:16:45 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/stringop.d,
|
|
|
|
|
|
* testsuite/gas/ppc/stringop.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:15:42 +02:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/set_bool.d,
|
|
|
|
|
|
* testsuite/gas/ppc/set_bool.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 bit manipulation operations
opcodes/
* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
(prefix_opcodes): Add xxeval.
gas/
* testsuite/gas/ppc/bitmanip.d,
* testsuite/gas/ppc/bitmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:14:25 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/bitmanip.d,
|
|
|
|
|
|
* testsuite/gas/ppc/bitmanip.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:13:15 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/genpcv.d,
|
|
|
|
|
|
* testsuite/gas/ppc/genpcv.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 VSX Mask Manipulation Operations
opcodes/
* ppc-opc.c (MP, VXVAM_MASK): Define.
(VXVAPS_MASK): Use VXVA_MASK.
(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
* testsuite/gas/ppc/maskmanip.d,
* testsuite/gas/ppc/maskmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:11:57 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/maskmanip.d,
|
|
|
|
|
|
* testsuite/gas/ppc/maskmanip.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 Reduced precision outer product operations
include/
* opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following
PPC_OPERAND defines.
opcodes/
* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
New functions.
(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
YMSK2, XA6a, XA6ap, XB6a entries.
(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
(PPCVSX4): Define.
(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
* config/tc-ppc.c (pre_defined_registers): Add accumulators.
(md_assemble): Check acc specified in correct operand.
* testsuite/gas/ppc/outerprod.d,
* testsuite/gas/ppc/outerprod.s,
* testsuite/gas/ppc/vsx4.d,
* testsuite/gas/ppc/vsx4.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 02:10:42 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (pre_defined_registers): Add accumulators.
|
|
|
|
|
|
(md_assemble): Check acc specified in correct operand.
|
|
|
|
|
|
* testsuite/gas/ppc/outerprod.d,
|
|
|
|
|
|
* testsuite/gas/ppc/outerprod.s,
|
|
|
|
|
|
* testsuite/gas/ppc/vsx4.d,
|
|
|
|
|
|
* testsuite/gas/ppc/vsx4.s: New tests.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run them.
|
|
|
|
|
|
|
Power10 SIMD permute class operations
opcodes/
* ppc-opc.c (insert_imm32, extract_imm32): New functions.
(insert_xts, extract_xts): New functions.
(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
(VXRC_MASK, VXSH_MASK): Define.
(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
xxblendvh, xxblendvw, xxblendvd, xxpermx.
gas/
* testsuite/gas/ppc/simd_perm.d,
* testsuite/gas/ppc/simd_perm.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:07:14 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/simd_perm.d,
|
|
|
|
|
|
* testsuite/gas/ppc/simd_perm.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 128-bit binary integer operations
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
gas/
* testsuite/gas/ppc/int128.d,
* testsuite/gas/ppc/int128.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:06:11 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/int128.d,
|
|
|
|
|
|
* testsuite/gas/ppc/int128.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:04:49 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/vsx_32byte.d,
|
|
|
|
|
|
* testsuite/gas/ppc/vsx_32byte.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
Power10 vector integer multiply, divide, modulo insns
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
gas/
* testsuite/gas/ppc/vec_mul.s,
* testsuite/gas/ppc/vec_mul.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 02:02:56 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/vec_mul.s,
|
|
|
|
|
|
* testsuite/gas/ppc/vec_mul.d: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:01:40 +02:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/byte_rev.d,
|
|
|
|
|
|
* testsuite/gas/ppc/byte_rev.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 02:00:19 +02:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power10.d: Add paste. tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power10.s: Likewise.
|
|
|
|
|
|
|
2020-05-11 01:57:48 +02:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power10.s: New test.
|
|
|
|
|
|
* testsuite/gas/ppc/power10.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
|
|
|
|
|
2020-05-11 01:54:14 +02:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
|
|
|
|
|
|
renaming.
|
|
|
|
|
|
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
|
|
|
|
|
|
place of -mfuture/-Mfuture.
|
|
|
|
|
|
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
|
|
|
|
|
|
|
2020-05-06 15:17:36 +02:00
|
|
|
|
2020-05-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2020-05-06 14:21:02 +02:00
|
|
|
|
2020-05-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25927
|
|
|
|
|
|
* doc/as.texi (Preprocessing): Replace cross reference to not
|
|
|
|
|
|
existant document with a URL to the equivalent page in the GCC
|
|
|
|
|
|
manual.
|
|
|
|
|
|
|
2020-05-05 17:16:03 +02:00
|
|
|
|
2020-05-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
|
|
|
|
|
|
construction of a DWARF-5 directory name table.
|
|
|
|
|
|
* testsuite/gas/elf/pr25917.d: Update expected output.
|
|
|
|
|
|
|
2020-05-05 11:19:41 +02:00
|
|
|
|
2020-05-05 Gunther Nikl <gnikl@justmail.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rx.c (elf_flags): Initialize for non-linux targets.
|
|
|
|
|
|
(md_parse_option): Remove initialization of elf_flags.
|
2020-05-04 14:50:05 +02:00
|
|
|
|
|
2020-05-04 14:05:42 +02:00
|
|
|
|
2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25863
|
|
|
|
|
|
* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
|
|
|
|
|
|
* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
|
|
|
|
|
|
|
2020-05-04 11:19:38 +02:00
|
|
|
|
2020-05-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25917
|
|
|
|
|
|
* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
|
|
|
|
|
|
table's existence before looking at its entries.
|
2020-05-04 14:50:05 +02:00
|
|
|
|
Also do not emit a default directory entry if there are no
|
|
|
|
|
|
directories in use.
|
|
|
|
|
|
|
2020-05-04 11:19:38 +02:00
|
|
|
|
* testsuite/gas/elf/pr25917.s: New test source file.
|
|
|
|
|
|
* testsuite/gas/elf/pr25917.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
|
|
|
|
|
|
|
2020-04-30 16:47:30 +02:00
|
|
|
|
2020-04-30 Alex Coplan <alex.coplan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (fix_insn): Implement for
|
|
|
|
|
|
AARCH64_OPND_UNDEFINED.
|
|
|
|
|
|
(parse_operands): Implement for AARCH64_OPND_UNDEFINED.
|
|
|
|
|
|
* testsuite/gas/aarch64/udf.s: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/udf.d: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/udf-invalid.s: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/udf-invalid.l: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/udf-invalid.d: New.
|
|
|
|
|
|
|
2020-04-30 14:35:37 +02:00
|
|
|
|
2020-04-30 Yoshinori Sato <ysato@users.sourceforge.jp>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rx.c (elf_flags): Reset default value.
|
|
|
|
|
|
(md_parse_option): For rx-elf Initialize elf_flags with RX_ABI.
|
|
|
|
|
|
|
2020-04-28 13:15:05 +02:00
|
|
|
|
2020-04-29 Max Filippov <jcmvbkbc@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0
|
|
|
|
|
|
if it's not defined.
|
|
|
|
|
|
(microarch_earliest): New static variable.
|
|
|
|
|
|
(xg_translate_idioms): Translate "simcall" to "simcall 0" when
|
|
|
|
|
|
simcall opcode has mandatory parameter.
|
|
|
|
|
|
(xg_init_global_config): Initialize microarch_earliest.
|
|
|
|
|
|
|
2020-04-29 14:13:55 +02:00
|
|
|
|
2020-04-29 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22699
|
|
|
|
|
|
* config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
|
|
|
|
|
|
IMM0_8S and add support for IMM0_8U.
|
|
|
|
|
|
* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
|
|
|
|
|
|
unsigned 8-bit immediate.
|
|
|
|
|
|
* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
|
2020-04-29 18:18:56 +02:00
|
|
|
|
* testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly.
|
2020-04-29 14:13:55 +02:00
|
|
|
|
|
2020-04-27 18:39:31 +02:00
|
|
|
|
2020-04-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Add news entry for big-obj.
|
|
|
|
|
|
* config/tc-i386.c (i386_target_format): Support new format.
|
|
|
|
|
|
* doc/c-i386.texi: Add i386 support.
|
|
|
|
|
|
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
|
|
|
|
|
|
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
|
|
|
|
|
|
|
2020-04-27 12:35:25 +02:00
|
|
|
|
2020-04-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25878
|
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* dwarf2dbg.c (struct file_entry): Add auto_assigned field.
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(assign_file_to_slot): New function. Fills in an entry in the
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files table.
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(allocate_filenum): Use new function.
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(allocate_filename_to_slot): Use new function. If the specified
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slot entry is already in use, but was chosen automatically then
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reassign the automatic entry.
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2020-03-16 04:03:12 +01:00
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2020-04-26 Hongtao Liu <hongtao.liu@intel.com
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* config/tc-i386.c (lfence_before_ret_shl): New member.
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(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
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for Anysize insns.
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(insert_after_load): Issue warning for REP CMPS/SCAS.
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(insert_before_before): Handle iret, Handle
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-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
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(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
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-mlfence-before-ret=[none/not/or/shl/yes].
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Enable -mlfence-before-ret=shl when
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-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
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(md_show_usage): Ditto.
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* doc/c-i386.texi: Ditto.
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* testsuite/gas/i386/i386.exp: Add new testcases.
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* testsuite/gas/i386/lfence-load-b.d: New.
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* testsuite/gas/i386/lfence-load-b.e: New.
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* testsuite/gas/i386/lfence-load.d: Modified.
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* testsuite/gas/i386/lfence-load.e: New.
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* testsuite/gas/i386/lfence-load.s: Modified.
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* testsuite/gas/i386/lfence-ret-a.d: Modified.
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* testsuite/gas/i386/lfence-ret-b.d: Modified.
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* testsuite/gas/i386/lfence-ret-c.d: New.
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* testsuite/gas/i386/lfence-ret-d.d: New.
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* testsuite/gas/i386/lfence-ret.s: Modified.
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* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
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* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
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* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
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* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
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* testsuite/gas/i386/x86-64-lfence-ret.e: New.
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* testsuite/gas/i386/x86-64-lfence-ret.s: New.
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xtensa: fix PR ld/25861
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-20 04:04:41 +02:00
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2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
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PR ld/25861
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* config/tc-xtensa.c (md_apply_fix): Replace
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BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
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BFD_RELOC_XTENSA_PDIFF{8,16,32} and
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BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
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* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
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with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
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2020-04-22 04:22:13 +02:00
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2020-04-22 Alan Modra <amodra@gmail.com>
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* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
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symbol for ".symver .. remove".
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* doc/as.texi (.symver): Update.
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* testsuite/gas/symver/symver11.s: Make foo weak.
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* testsuite/gas/symver/symver11.d: Expect an error.
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* testsuite/gas/symver/symver7.d: Allow other random symbols.
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2020-04-22 03:21:56 +02:00
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2020-04-21 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/symver/symver11.s: Add ".balign 8".
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2020-04-18 14:32:39 +02:00
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2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
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PR 25848
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* testsuite/gas/m68k/operands.s: Add tests for cmpi.
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* testsuite/gas/m68k/operands.d: Update.
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* testsuite/gas/m68k/op68000.d: Update for new error messages.
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2020-04-21 16:16:21 +02:00
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2020-04-21 Tamar Christina <tamar.christina@arm.com>
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PR binutils/24753
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* testsuite/gas/arm/pr24753.d: New test.
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* testsuite/gas/arm/pr24753.s: New test.
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gas: Extend .symver directive
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:
.symver foo, foo@VERS_1, local # Change foo to a local symbol.
.symver foo, foo@VERS_2, hidden # Change foo to a hidden symbol.
.symver foo, foo@@VERS_3, remove # Remove foo from symbol table.
.symver foo, bar@V1 # Assign foo to bar@V1 and baz@V2.
.symver foo, baz@V2
PR gas/23840
PR gas/25295
* NEWS: Mention .symver extension.
* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
function.
(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
add a version name. Add local, hidden and remove visibility
support.
(elf_frob_symbol): Handle the list of version names. Update the
original symbol to local, hidden or remove it from the symbol
table.
(elf_frob_file_before_adjust): Handle the list of version names.
* config/obj-elf.h (elf_visibility): New.
(elf_versioned_name_list): Likewise.
(elf_obj_sy): Change local to bitfield. Add rename, bad_version
and visibility. Change versioned_name pointer to struct
elf_versioned_name_list.
* doc/as.texi: Update .symver directive.
* testsuite/gas/symver/symver.exp: Run all *.d tests. Add more
error checking tests.
* testsuite/gas/symver/symver6.d: New file.
* testsuite/gas/symver/symver7.d: Likewise.
* testsuite/gas/symver/symver7.s: Likewise.
* testsuite/gas/symver/symver8.d: Likewise.
* testsuite/gas/symver/symver8.s: Likewise.
* testsuite/gas/symver/symver9.s: Likewise.
* testsuite/gas/symver/symver9a.d: Likewise.
* testsuite/gas/symver/symver9b.d: Likewise.
* testsuite/gas/symver/symver10.s: Likewise.
* testsuite/gas/symver/symver10a.d: Likewise.
* testsuite/gas/symver/symver10b.d: Likewise.
* testsuite/gas/symver/symver11.d: Likewise.
* testsuite/gas/symver/symver11.s: Likewise.
* testsuite/gas/symver/symver12.d: Likewise.
* testsuite/gas/symver/symver12.s: Likewise.
* testsuite/gas/symver/symver13.d: Likewise.
* testsuite/gas/symver/symver13.s: Likewise.
* testsuite/gas/symver/symver14.d: Likewise.
* testsuite/gas/symver/symver14.l: Likewise.
* testsuite/gas/symver/symver15.d: Likewise.
* testsuite/gas/symver/symver15.l: Likewise.
* testsuite/gas/symver/symver6.l: Removed.
* testsuite/gas/symver/symver6.s: Updated.
2020-04-21 14:33:04 +02:00
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2020-04-21 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/23840
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PR gas/25295
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* NEWS: Mention .symver extension.
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* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
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function.
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(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
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add a version name. Add local, hidden and remove visibility
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support.
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(elf_frob_symbol): Handle the list of version names. Update the
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original symbol to local, hidden or remove it from the symbol
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table.
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(elf_frob_file_before_adjust): Handle the list of version names.
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* config/obj-elf.h (elf_visibility): New.
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(elf_versioned_name_list): Likewise.
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(elf_obj_sy): Change local to bitfield. Add rename, bad_version
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and visibility. Change versioned_name pointer to struct
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elf_versioned_name_list.
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* doc/as.texi: Update .symver directive.
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* testsuite/gas/symver/symver.exp: Run all *.d tests. Add more
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error checking tests.
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* testsuite/gas/symver/symver6.d: New file.
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* testsuite/gas/symver/symver7.d: Likewise.
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* testsuite/gas/symver/symver7.s: Likewise.
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* testsuite/gas/symver/symver8.d: Likewise.
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* testsuite/gas/symver/symver8.s: Likewise.
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* testsuite/gas/symver/symver9.s: Likewise.
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* testsuite/gas/symver/symver9a.d: Likewise.
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* testsuite/gas/symver/symver9b.d: Likewise.
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* testsuite/gas/symver/symver10.s: Likewise.
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* testsuite/gas/symver/symver10a.d: Likewise.
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* testsuite/gas/symver/symver10b.d: Likewise.
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* testsuite/gas/symver/symver11.d: Likewise.
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* testsuite/gas/symver/symver11.s: Likewise.
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* testsuite/gas/symver/symver12.d: Likewise.
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* testsuite/gas/symver/symver12.s: Likewise.
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* testsuite/gas/symver/symver13.d: Likewise.
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* testsuite/gas/symver/symver13.s: Likewise.
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* testsuite/gas/symver/symver14.d: Likewise.
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* testsuite/gas/symver/symver14.l: Likewise.
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* testsuite/gas/symver/symver15.d: Likewise.
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* testsuite/gas/symver/symver15.l: Likewise.
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* testsuite/gas/symver/symver6.l: Removed.
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* testsuite/gas/symver/symver6.s: Updated.
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2020-04-20 11:58:16 +02:00
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_barrier_psb): Update error messages
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to include TSB.
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* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
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* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
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* testsuite/gas/aarch64/system.d: Update.
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[AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2020-04-20 11:50:52 +02:00
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/bti.d: Update -march option.
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* testsuite/gas/aarch64/illegal-bti.d: Remove.
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* testsuite/gas/aarch64/illegal-bti.l: Remove.
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* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
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* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
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2020-04-17 05:08:19 +02:00
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2020-04-17 Alan Modra <amodra@gmail.com>
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* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
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2020-04-16 19:02:10 +02:00
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2020-04-16 Gagan Singh Sidhu <broly@mac.com>
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Nick Clifton <nickc@redhat.com>
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PR 25803
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* config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
|
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targets.
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* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
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for the type-2 test.
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* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
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targets running this test.
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2020-04-16 09:52:57 +02:00
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2020-02-16 David Faust <david.faust@oracle.com>
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* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
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* testsuite/gas/bpf/jump32.s: New file.
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* testsuite/gas/bpf/jump32.d: Likewise.
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2020-04-09 04:31:45 +02:00
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2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
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documentation.
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2020-04-08 12:11:43 +02:00
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|
2020-04-08 Gunther Nikl <gnikl@justmail.de>
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* config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define.
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|
|
(md_pcrel_from): Remove prototytpe.
|
2020-04-08 12:15:28 +02:00
|
|
|
|
* config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate
|
|
|
|
|
|
define.
|
|
|
|
|
|
(md_pcrel_from_section): Remove duplicate prototype.
|
2020-04-08 13:28:10 +02:00
|
|
|
|
* tc.h (md_pcrel_from_section): Add prototype.
|
|
|
|
|
|
* config/tc-aarch64.h (md_pcrel_from_section): Remove prototype.
|
|
|
|
|
|
* config/tc-arc.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-arm.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-avr.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-bfin.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-bpf.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-csky.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-d10v.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-d30v.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-epiphany.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-fr30.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-frv.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-iq2000.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-lm32.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-m32c.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-m32r.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-mcore.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-mep.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-metag.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-mmix.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-moxie.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-msp430.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-mt.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-or1k.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-ppc.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-rl78.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-rx.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-s390.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-sh.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-xc16x.h (md_pcrel_from_section): Likewise.
|
|
|
|
|
|
* config/tc-xstormy16.h (md_pcrel_from_section): Likewise.
|
[PATCH 1/4]: microblaze: remove duplicate prototypes
The microblaze target header duplicates prototypes already provided by tc.h.
* config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol,
md_show_usage, md_convert_frag, md_operand, md_number_to_chars,
md_estimate_size_before_relax, md_section_align, tc_gen_reloc,
md_apply_fix3): Delete prototypes.
2020-04-08 13:33:16 +02:00
|
|
|
|
* config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol,
|
|
|
|
|
|
md_show_usage, md_convert_frag, md_operand, md_number_to_chars,
|
|
|
|
|
|
md_estimate_size_before_relax, md_section_align, tc_gen_reloc,
|
|
|
|
|
|
md_apply_fix3): Delete prototypes.
|
2020-04-08 12:11:43 +02:00
|
|
|
|
|
2020-04-07 13:43:49 +02:00
|
|
|
|
2020-04-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Mention support for Intel SERIALIZE and TSXLDTRK
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
gas/doc/c-z80.texi: Fix @xref warnings
Fix
gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not )
* doc/c-z80.texi: Fix @xref warnings.
2020-04-07 13:17:01 +02:00
|
|
|
|
2020-04-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-z80.texi: Fix @xref warnings.
|
|
|
|
|
|
|
2020-04-07 07:59:50 +02:00
|
|
|
|
2020-04-07 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
|
|
|
|
|
|
(cpu_noarch): Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Document TSXLDTRK.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
|
|
|
|
|
|
* testsuite/gas/i386/tsxldtrk.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/tsxldtrk.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
|
|
|
|
|
|
|
2020-03-06 07:38:15 +01:00
|
|
|
|
2020-04-02 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .serialize.
|
|
|
|
|
|
(cpu_noarch): Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Document serialize.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run serialize tests
|
|
|
|
|
|
* testsuite/gas/i386/serialize.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-serialize.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/serialize.s: Likewise.
|
|
|
|
|
|
|
ld: Disable ifunc tests on Solaris
A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86:
FAIL: ld-ifunc/ifunc-10-x86-64
FAIL: ld-ifunc/ifunc-11-x86-64
FAIL: ld-ifunc/ifunc-12-x86-64
FAIL: ld-ifunc/ifunc-13-x86-64
FAIL: ld-ifunc/ifunc-14a-x86-64
FAIL: ld-ifunc/ifunc-14b-x86-64
FAIL: ld-ifunc/ifunc-14c-x86-64
FAIL: ld-ifunc/ifunc-14d-x86-64
FAIL: ld-ifunc/ifunc-14e-x86-64
FAIL: ld-ifunc/ifunc-14f-x86-64
FAIL: ld-ifunc/ifunc-15-x86-64
FAIL: ld-ifunc/ifunc-17a-x86-64
FAIL: ld-ifunc/ifunc-17b-x86-64
FAIL: ld-ifunc/ifunc-2-local-x86-64-now
FAIL: ld-ifunc/ifunc-2-local-x86-64
FAIL: ld-ifunc/ifunc-2-x86-64-now
FAIL: ld-ifunc/ifunc-2-x86-64
FAIL: ld-ifunc/ifunc-20-x86-64
FAIL: ld-ifunc/pr17154-x86-64-now
FAIL: ld-ifunc/pr17154-x86-64
For one, the actual error is weird:
./ld-new: target elf64-x86-64 not found
failed with: <./ld-new: target elf64-x86-64 not found>, no expected output
FAIL: ld-ifunc/ifunc-10-x86-64
although ld -V does report the elf_x86_64 emulation as supported:
$ ./ld/ld-new -V
GNU ld (GNU Binutils) 2.34.50.20200328
Supported emulations:
elf_x86_64_sol2
elf_x86_64
[...]
When using ld -m elf_x86_64_sol2 instead, one of the testcases links
successfully.
However, there's no point in pursuing this: Solaris does not support
ifunc, as can be seen in <sys/elf.h>:
/*
* GNU/Linux specific symbol type not used by Solaris
*/
#define STT_GNU_IFUNC 10
and never will, given that it has symbol capabilities as solution to
effectively the same problem:
http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/
Therefore this patch disables ifunc testing on Solaris completely by
removing Solaris from binutils/testsuite/lib/binutils-common.exp
(supports_gnu_osabi). The ifunc part is justified above. SHF_GNU_MBIND is
in the OS-specific range and conflicts with
#define SHF_SUNW_REALLOC 0x01000000 /* internal: krtld realloc */
While the comment suggests this might be relocatable without too much
problems, the description of mbind (no formal spec AFAICS, just the
comment in the binutils patch submission) strongly suggests that this
isn't relevant to Solaris at all.
Indirectly, clearing supports_gnu_osabi on Solaris disables
supports_gnu_unique. Again, Solaris <sys/elf.h> has
/*
* GNU/Linux specific binding not used by Solaris
*/
#define STB_GNU_UNIQUE 10
so this seems the right thing to do.
Afterwards, one can remove the explicit mentions of *-*-solaris2* in
quite a number of (but not all) the ld-ifunc dump file notarget lists.
There's one fallout, though: two gas tests now XPASS because they are
xfail'ed for !supports_gnu_osabi:
XPASS: mbind sections 12
XPASS: mbind section contents 16
XPASS: mbind sections 16
XPASS: mbind section contents 16
To fix that, I've changed
#xfail: ![supports_gnu_osabi]
to notarget.
Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.
ld:
* testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from
notarget.
* ifunc-11-i386.d: Likewise.
* ifunc-12-i386.d: Likewise.
* ifunc-13-i386.d: Likewise.
* ifunc-14a-i386.d: Likewise.
* ifunc-14b-i386.d: Likewise.
* ifunc-14c-i386.d: Likewise.
* ifunc-14d-i386.d: Likewise.
* ifunc-14e-i386.d: Likewise.
* ifunc-14f-i386.d: Likewise.
* ifunc-15-i386.d: Likewise.
* ifunc-16-i386-now.d: Likewise.
* ifunc-16-i386.d: Likewise.
* ifunc-17a-i386.d: Likewise.
* ifunc-17b-i386.d: Likewise.
* ifunc-18a-i386.d: Likewise.
* ifunc-18b-i386.d: Likewise.
* ifunc-19a-i386.d: Likewise.
* ifunc-19b-i386.d: Likewise.
* ifunc-2-i386-now.d: Likewise.
* ifunc-2-i386.d: Likewise.
* ifunc-2-local-i386-now.d: Likewise.
* ifunc-2-local-i386.d: Likewise.
* ifunc-20-i386.d: Likewise.
* ifunc-21-i386.d: Likewise.
* ifunc-22-i386.d: Likewise.
* ifunc-5a-i386.d: Likewise.
* ifunc-5a-local-i386.d: Likewise.
* ifunc-5b-i386.d: Likewise.
* ifunc-5b-local-i386.d: Likewise.
* ifunc-5r-local-i386.d: Likewise.
* ifunc-6a-i386.d: Likewise.
* ifunc-6b-i386.d: Likewise.
* ifunc-7a-i386.d: Likewise.
* ifunc-7b-i386.d: Likewise.
* ifunc-8-i386.d: Likewise.
* ifunc-9-i386.d: Likewise.
* pr17154-i386-now.d: Likewise.
* pr17154-i386.d: Likewise.
* ifunc-23a-x86.d: Remove notarget.
* ifunc-24a-x86.d: Likewise.
* ifunc-25a-x86.d: Likewise.
gas:
* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
binutils:
* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't
enable on *-*-solaris*.
2020-04-02 10:52:57 +02:00
|
|
|
|
2020-04-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
|
|
|
|
|
|
* testsuite/gas/elf/section12b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16b.d: Likewise.
|
|
|
|
|
|
|
2020-04-02 09:57:45 +02:00
|
|
|
|
2020-04-02 Gunther Nikl <gnikl@justmail.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m68k.c (m68k_ip): Fix range check for index register
|
|
|
|
|
|
with a suppressed address register.
|
|
|
|
|
|
|
2020-04-01 14:40:45 +02:00
|
|
|
|
2020-04-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25756
|
|
|
|
|
|
* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
|
|
|
|
|
|
* testsuite/gas/i386/localpic.s: Add a test for relocation
|
|
|
|
|
|
against local absolute symbol.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-localpic.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/localpic.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
|
|
|
|
|
|
|
2020-04-01 14:10:34 +02:00
|
|
|
|
2020-04-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25732
|
|
|
|
|
|
* testsuite/gas/i386/solaris/x86-64-branch-2.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
|
|
|
|
|
|
testsuite/gas/i386/x86-64-jump.d.
|
|
|
|
|
|
* gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
|
|
|
|
|
|
Incorporate changes to
|
|
|
|
|
|
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
|
|
|
|
|
|
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
|
|
|
|
|
|
changes to testsuite/gas/i386/x86-64-mpx-branch-2.d.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-3.d: Likewise.
|
|
|
|
|
|
|
2020-04-01 00:01:36 +02:00
|
|
|
|
2020-03-31 Maciej W. Rozycki <macro@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25611
|
|
|
|
|
|
PR 25614
|
|
|
|
|
|
* dwarf2dbg.c: Do not include "bignum.h".
|
|
|
|
|
|
|
2020-03-12 10:48:39 +01:00
|
|
|
|
2020-03-30 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
|
|
|
|
|
|
* testsuite/gas/riscv/alias-csr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/no-aliases-csr.d: Move this
|
|
|
|
|
|
to priv-reg-pseudo-noalias.
|
|
|
|
|
|
* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
|
|
|
|
|
|
* testsuite/gas/riscv/bad-csr.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/bad-csr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
|
|
|
|
|
|
* testsuite/gas/riscv/satp.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
|
|
|
|
|
|
csr instruction, including alias-csr testcase.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
|
|
|
|
|
|
pseudo instruction with objdump -Mno-aliases.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
|
|
|
|
|
|
|
2020-03-25 12:52:07 +01:00
|
|
|
|
2020-03-25 J.W. Jagersma <jwjagersma@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-coff.c (obj_coff_section): Set the bss flag on
|
|
|
|
|
|
sections with the "b" attribute.
|
|
|
|
|
|
|
s12z disassembler tidy
Don't ignore buffer memory read failure, or malloc failure. Lots of
functions get a return status to pass these failures up the chain in
this patch.
opcodes/
* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
* s12z-opc.c: Formatting.
(operands_f): Return an int.
(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
(exg_sex_discrim): Likewise.
(create_immediate_operand, create_bitfield_operand),
(create_register_operand_with_size, create_register_all_operand),
(create_register_all16_operand, create_simple_memory_operand),
(create_memory_operand, create_memory_auto_operand): Don't
segfault on malloc failure.
(z_ext24_decode): Return an int status, negative on fail, zero
on success.
(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
(loop_primitive_decode, shift_decode, psh_pul_decode),
(bit_field_decode): Similarly.
(z_decode_signed_value, decode_signed_value): Similarly. Add arg
to return value, update callers.
(x_opr_decode_with_size): Check all reads, returning NULL on fail.
Don't segfault on NULL operand.
(decode_operation): Return OP_INVALID on first fail.
(decode_s12z): Check all reads, returning -1 on fail.
gas/
* testsuite/gas/s12z/truncated.d: Update expected output.
2020-03-22 05:32:27 +01:00
|
|
|
|
2020-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/s12z/truncated.d: Update expected output.
|
|
|
|
|
|
|
2020-03-20 14:53:02 +01:00
|
|
|
|
2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25690
|
|
|
|
|
|
* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
|
|
|
|
|
|
* doc/c-z80.texi: Update documentation.
|
|
|
|
|
|
|
2020-03-17 18:02:15 +01:00
|
|
|
|
2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25641
|
|
|
|
|
|
PR 25668
|
|
|
|
|
|
PR 25633
|
|
|
|
|
|
Fix disassembling ED+A4/AC/B4/BC opcodes.
|
|
|
|
|
|
Fix assembling lines containing colonless label and instruction
|
|
|
|
|
|
with first operand inside parentheses.
|
|
|
|
|
|
Fix registration of unsupported by target CPU registers.
|
|
|
|
|
|
* config/tc-z80.c: See above.
|
|
|
|
|
|
* config/tc-z80.h: See above.
|
|
|
|
|
|
* testsuite/gas/z80/colonless.d: Update test.
|
|
|
|
|
|
* testsuite/gas/z80/colonless.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/gbz80_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/unsup_regs.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z180_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80.exp: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_unsup_regs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_unsup_regs.d: Likewise.
|
|
|
|
|
|
|
2020-03-13 14:31:56 +01:00
|
|
|
|
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25660
|
|
|
|
|
|
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
|
|
|
|
|
|
(parse_operands): Handle new operand codes.
|
|
|
|
|
|
(do_neon_dyadic_long): Make shape check accept the scalar variants.
|
|
|
|
|
|
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
|
|
|
|
|
|
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
|
|
|
|
|
|
|
2020-03-11 17:56:17 +01:00
|
|
|
|
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Mention x86 assembler options for CVE-2020-0551.
|
|
|
|
|
|
|
2020-03-11 17:46:19 +01:00
|
|
|
|
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-byte.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-byte.e: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-byte.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-indbr-a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-indbr-b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-indbr-c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-indbr.e: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-indbr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-load.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-load.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret-b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/lfence-ret.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-byte.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-byte.e: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-byte.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-load.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
|
|
|
|
|
|
|
2020-03-11 17:46:19 +01:00
|
|
|
|
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (lfence_after_load): New.
|
|
|
|
|
|
(lfence_before_indirect_branch_kind): New.
|
|
|
|
|
|
(lfence_before_indirect_branch): New.
|
|
|
|
|
|
(lfence_before_ret_kind): New.
|
|
|
|
|
|
(lfence_before_ret): New.
|
|
|
|
|
|
(last_insn): New.
|
|
|
|
|
|
(load_insn_p): New.
|
|
|
|
|
|
(insert_lfence_after): New.
|
|
|
|
|
|
(insert_lfence_before): New.
|
|
|
|
|
|
(md_assemble): Call insert_lfence_before and insert_lfence_after.
|
|
|
|
|
|
Set last_insn.
|
|
|
|
|
|
(OPTION_MLFENCE_AFTER_LOAD): New.
|
|
|
|
|
|
(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
|
|
|
|
|
|
(OPTION_MLFENCE_BEFORE_RET): New.
|
|
|
|
|
|
(md_longopts): Add -mlfence-after-load=,
|
|
|
|
|
|
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
|
|
|
|
|
|
(md_parse_option): Handle -mlfence-after-load=,
|
|
|
|
|
|
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
|
|
|
|
|
|
(md_show_usage): Display -mlfence-after-load=,
|
|
|
|
|
|
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
|
|
|
|
|
|
(i386_cons_align): New.
|
|
|
|
|
|
* config/tc-i386.h (i386_cons_align): New.
|
|
|
|
|
|
(md_cons_align): New.
|
|
|
|
|
|
* doc/c-i386.texi: Document -mlfence-after-load=,
|
|
|
|
|
|
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
|
|
|
|
|
|
|
2020-03-11 11:17:14 +01:00
|
|
|
|
2020-03-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25611
|
|
|
|
|
|
PR 25614
|
|
|
|
|
|
* dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
|
|
|
|
|
|
(DWARF2_FILE_SIZE_NAME): Default to -1.
|
|
|
|
|
|
(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
|
|
|
|
|
|
whichever is higher.
|
|
|
|
|
|
(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
|
|
|
|
|
|
(NUM_MD5_BYTES): Define.
|
|
|
|
|
|
(struct file entry): Add md5 field.
|
|
|
|
|
|
(get_filenum): Delete and replace with...
|
|
|
|
|
|
(get_basename): New function.
|
|
|
|
|
|
(get_directory_table_entry): New function.
|
|
|
|
|
|
(allocate_filenum): New function.
|
|
|
|
|
|
(allocate_filename_to_slot): New function.
|
|
|
|
|
|
(dwarf2_where): Use new functions.
|
|
|
|
|
|
(dwarf2_directive_filename): Add support for extended .file
|
|
|
|
|
|
pseudo-op.
|
|
|
|
|
|
(dwarf2_directive_loc): Allow the use of file number zero with
|
|
|
|
|
|
DWARF 5 or higher.
|
|
|
|
|
|
(out_file_list): Rename to...
|
|
|
|
|
|
(out_dir_and_file_list): Add DWARF 5 support.
|
|
|
|
|
|
(out_debug_line): Emit extra values into the section header for
|
|
|
|
|
|
DWARF 5.
|
|
|
|
|
|
(out_debug_str): Allow for file 0 to be used with DWARF 5.
|
|
|
|
|
|
* doc/as.texi (.file): Update the description of this pseudo-op.
|
|
|
|
|
|
* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
|
|
|
|
|
|
* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
|
|
|
|
|
|
* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
|
|
|
|
|
|
* NEWS: Mention the new feature.
|
|
|
|
|
|
|
2020-03-10 12:22:50 +01:00
|
|
|
|
2020-03-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions
|
|
|
|
|
|
to avoid signed overflow.
|
|
|
|
|
|
* config/tc-mcore.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (SET_ADDEND): Likewise.
|
|
|
|
|
|
* config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
|
|
|
|
|
|
|
2020-03-09 10:13:43 +01:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx.s: Add long-form VCMP[PS][SD] pseudos.
|
|
|
|
|
|
* testsuite/gas/i386/avx.d, testsuite/gas/i386/avx-16bit.d,
|
|
|
|
|
|
testsuite/gas/i386/avx-intel.d: Adjust expectations.
|
|
|
|
|
|
|
2020-03-07 10:39:57 +01:00
|
|
|
|
2020-03-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in
|
|
|
|
|
|
first column.
|
|
|
|
|
|
|
2020-03-06 18:13:22 +01:00
|
|
|
|
2020-03-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25614
|
|
|
|
|
|
* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
|
|
|
|
|
|
0 if the dwarf_level is 5 or more. Complain if a filename follows
|
|
|
|
|
|
a file 0.
|
|
|
|
|
|
* testsuite/gas/elf/dwarf-5-file0.s: New test.
|
|
|
|
|
|
* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run the new test.
|
|
|
|
|
|
|
|
|
|
|
|
PR 25612
|
|
|
|
|
|
* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
|
|
|
|
|
|
* doc/as.texi: Fix another typo.
|
|
|
|
|
|
|
2020-03-06 15:52:14 +01:00
|
|
|
|
2020-03-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25612
|
|
|
|
|
|
* as.c (dwarf_level): Define.
|
|
|
|
|
|
(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
|
|
|
|
|
|
(parse_args): Add support for the new options.
|
|
|
|
|
|
as.h (dwarf_level): Prototype.
|
|
|
|
|
|
* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
|
|
|
|
|
|
value.
|
|
|
|
|
|
* config/tc-ia64.h (DWARF2_VERISION): Update definition.
|
|
|
|
|
|
(DWARF2_LINE_VERSION): Remove definition.
|
|
|
|
|
|
* doc/as.texi: Document the new options.
|
|
|
|
|
|
|
2020-03-06 11:44:12 +01:00
|
|
|
|
2020-03-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25572
|
|
|
|
|
|
* as.c (main): Allow matching input and outputs when they are
|
|
|
|
|
|
not regular files.
|
|
|
|
|
|
|
2020-03-06 08:56:47 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_mem_size): Generalize broadcast special
|
|
|
|
|
|
casing.
|
|
|
|
|
|
(check_VecOperands): Zap xmmword/ymmword/zmmword when more than
|
|
|
|
|
|
one of byte/word/dword/qword is set alongside a SIMD register in
|
|
|
|
|
|
a template's operand.
|
|
|
|
|
|
|
x86: drop/replace IgnoreSize
Even after commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06 08:55:52 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_template): Extend code in logic
|
|
|
|
|
|
rejecting certain suffixes in certain modes to also cover mask
|
|
|
|
|
|
register use and VecSIB. Drop special casing of broadcast. Skip
|
|
|
|
|
|
immediates in the check.
|
|
|
|
|
|
|
2020-03-06 08:55:03 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_template): Fold duplicate code in
|
|
|
|
|
|
logic rejecting certain suffixes in certain modes. Drop
|
|
|
|
|
|
pointless "else".
|
|
|
|
|
|
|
2020-03-06 08:53:18 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Exlucde !vexw insns
|
|
|
|
|
|
alongside !norex64 ones.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
|
|
|
|
|
|
with both 32- and 64-bit GPR operands.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
|
|
|
|
|
|
32- and 64-bit GPR operands.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512bw-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512bw.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512f-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
|
|
|
|
|
|
|
2020-03-06 08:52:12 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Drop use of rex64.
|
|
|
|
|
|
(process_suffix): For REX.W for 64-bit CRC32.
|
|
|
|
|
|
|
2020-03-06 08:50:56 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (i386_addressing_mode): For 32-bit
|
|
|
|
|
|
addressing for MPX insns without base/index.
|
|
|
|
|
|
* testsuite/gas/i386/mpx-16bit.s,
|
|
|
|
|
|
* testsuite/gas/i386/mpx-16bit.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-03-06 08:49:45 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
|
|
|
|
|
|
testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
|
|
|
|
|
|
testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
|
|
|
|
|
|
testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
|
|
|
|
|
|
* testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
|
|
|
|
|
|
as well as a BSWAP one.
|
|
|
|
|
|
* testsuite/gas/i386/rdpid.s: Add 16-bit case.
|
|
|
|
|
|
* testsuite/gas/i386/sse2-16bit.s: Cover more insns.
|
|
|
|
|
|
* testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
|
|
|
|
|
|
testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
|
|
|
|
|
|
testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
|
|
|
|
|
|
testsuite/gas/i386/vmx.d: Adjust expectations.
|
|
|
|
|
|
|
2020-03-06 08:48:48 +01:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
|
|
|
|
|
|
from having their operands swapped.
|
|
|
|
|
|
* testsuite/gas/i386/waitpkg.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
|
|
|
|
|
|
3-operand cases as well as testing of 16-bit code generation.
|
|
|
|
|
|
* testsuite/gas/i386/waitpkg.d,
|
|
|
|
|
|
testsuite/gas/i386/waitpkg-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-waitpkg.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
|
|
|
|
|
|
|
2020-03-04 06:08:04 +01:00
|
|
|
|
2020-03-04 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
2020-03-04 06:08:05 +01:00
|
|
|
|
* config/tc-riscv.c (percent_op_utype): Support the modifier
|
|
|
|
|
|
%got_pcrel_hi.
|
|
|
|
|
|
* doc/c-riscv.texi: Add documentation.
|
|
|
|
|
|
* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
|
|
|
|
|
|
modifier %got_pcrel_hi.
|
|
|
|
|
|
* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/relax-reloc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/relax-reloc.s: Likewise.
|
|
|
|
|
|
|
2020-03-04 06:08:04 +01:00
|
|
|
|
* doc/c-riscv.texi (relocation modifiers): Add documentation.
|
|
|
|
|
|
(RISC-V-Formats): Update the section name from "Instruction Formats"
|
|
|
|
|
|
to "RISC-V Instruction Formats".
|
|
|
|
|
|
|
2020-03-04 18:28:46 +01:00
|
|
|
|
2020-03-04 Alexandre Oliva <oliva@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
|
|
|
|
|
|
detected in a section which does not have at least 4 byte
|
|
|
|
|
|
alignment.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
|
|
|
|
|
|
* testsuite/gas/arm/ldr-t.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
|
|
|
|
|
|
disassembly, ignoring any NOPs that may have been inserted because
|
|
|
|
|
|
of section alignment.
|
|
|
|
|
|
* testsuite/gas/arm/ldr-t.d: Likewise.
|
|
|
|
|
|
|
2020-03-04 08:58:13 +01:00
|
|
|
|
2020-03-04 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .sev_es entry.
|
|
|
|
|
|
* doc/c-i386.texi: Mention sev_es.
|
|
|
|
|
|
* testsuite/gas/i386/arch-13.s: Add SEV-ES case.
|
|
|
|
|
|
* testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
|
|
|
|
|
|
expectations.
|
|
|
|
|
|
* testsuite/gas/i386/arch-13-znver1.d,
|
|
|
|
|
|
testsuite/gas/i386/arch-13-znver2.d: Extend -march=.
|
|
|
|
|
|
|
2020-03-03 20:24:16 +01:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_template): Replace ignoresize and
|
|
|
|
|
|
defaultsize with mnemonicsize.
|
|
|
|
|
|
(process_suffix): Likewise.
|
|
|
|
|
|
|
2020-03-03 17:31:42 +01:00
|
|
|
|
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25627
|
|
|
|
|
|
* config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
|
|
|
|
|
|
instruction LD IY,(HL).
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
|
|
|
|
|
|
|
x86: Allow integer conversion without suffix in AT&T syntax
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
2020-03-03 16:39:18 +01:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25622
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
|
|
|
|
|
|
x86-64-default-suffix-avx.
|
|
|
|
|
|
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
|
|
|
|
|
|
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
|
|
|
|
|
|
* testsuite/gas/i386/noreg64.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/noreg64.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
|
|
|
|
|
|
|
2020-03-03 14:09:19 +01:00
|
|
|
|
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25604
|
|
|
|
|
|
* config/tc-z80.c (contains_register): Prevent an illegal memory
|
|
|
|
|
|
access when checking an expression for a register name.
|
|
|
|
|
|
|
2020-03-02 23:14:26 +01:00
|
|
|
|
2020-03-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips
|
|
|
|
|
|
support.
|
|
|
|
|
|
|
2020-03-02 00:47:18 +01:00
|
|
|
|
2020-03-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section.
|
|
|
|
|
|
* config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata
|
|
|
|
|
|
and .sbss sections.
|
|
|
|
|
|
* config/tc-score.c: Delete !BFD_ASSEMBLER code throughout.
|
|
|
|
|
|
(s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section.
|
|
|
|
|
|
(s3_s_score_lcomm): Likewise.
|
|
|
|
|
|
* config/tc-score7.c: Similarly.
|
|
|
|
|
|
* read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
|
|
|
|
|
|
|
2020-02-28 08:58:13 +01:00
|
|
|
|
2020-02-28 YunQiang Su <syq@debian.org>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25539
|
|
|
|
|
|
* config/tc-mips.c (fix_loongson3_llsc): Compare label value
|
|
|
|
|
|
to handle multi-labels.
|
|
|
|
|
|
(has_label_name): New.
|
|
|
|
|
|
|
2020-02-26 15:23:11 +01:00
|
|
|
|
2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (enum pred_instruction_type): Remove
|
|
|
|
|
|
NEUTRAL_IT_NO_VPT_INSN predication type.
|
|
|
|
|
|
(cxn_handle_predication): Modify to require condition suffixes.
|
|
|
|
|
|
(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
|
|
|
|
|
|
* testsuite/gas/arm/cde-scalar.s: Update test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.l: Update test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.s: Update test.
|
|
|
|
|
|
|
2020-02-26 03:27:19 +01:00
|
|
|
|
2020-02-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
|
|
|
|
|
|
N_() on empty string.
|
|
|
|
|
|
|
2020-02-26 03:08:11 +01:00
|
|
|
|
2020-02-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (read_a_source_file): Call strncpy with length one
|
|
|
|
|
|
less than size of original_case_string.
|
|
|
|
|
|
|
2020-02-25 06:04:46 +01:00
|
|
|
|
2020-02-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c: Indent labels correctly.
|
|
|
|
|
|
* config/obj-macho.c: Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c: Likewise.
|
|
|
|
|
|
* config/tc-alpha.c: Likewise.
|
|
|
|
|
|
* config/tc-arm.c: Likewise.
|
|
|
|
|
|
* config/tc-cr16.c: Likewise.
|
|
|
|
|
|
* config/tc-crx.c: Likewise.
|
|
|
|
|
|
* config/tc-frv.c: Likewise.
|
|
|
|
|
|
* config/tc-i386-intel.c: Likewise.
|
|
|
|
|
|
* config/tc-i386.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-nds32.c: Likewise.
|
|
|
|
|
|
* config/tc-riscv.c: Likewise.
|
|
|
|
|
|
* config/tc-s12z.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c: Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
* read.c: Likewise.
|
|
|
|
|
|
* symbols.c: Likewise.
|
|
|
|
|
|
* write.c: Likewise.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 11:18:49 +01:00
|
|
|
|
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
2020-02-12 11:18:51 +01:00
|
|
|
|
* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
|
|
|
|
|
|
we are assembling instruction with CSR. Call riscv_csr_read_only_check
|
|
|
|
|
|
after parsing all arguments.
|
|
|
|
|
|
(enum csr_insn_type): New enum is used to classify the CSR instruction.
|
|
|
|
|
|
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
|
|
|
|
|
|
are used to check if we write a read-only CSR by the CSR instruction.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
|
|
|
|
|
|
all CSR for the read-only CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
|
|
|
|
|
|
all CSR instructions for the read-only CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
|
|
|
|
|
|
|
2020-02-12 11:18:50 +01:00
|
|
|
|
* config/tc-riscv.c (struct riscv_set_options): New field csr_check.
|
|
|
|
|
|
(riscv_opts): Initialize it.
|
|
|
|
|
|
(reg_lookup_internal): Check the `riscv_opts.csr_check`
|
|
|
|
|
|
before doing the CSR checking.
|
|
|
|
|
|
(enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK.
|
|
|
|
|
|
(md_longopts): Add mcsr-check and mno-csr-check.
|
|
|
|
|
|
(md_parse_option): Handle new enum option values.
|
|
|
|
|
|
(s_riscv_option): Handle new long options.
|
|
|
|
|
|
* doc/c-riscv.texi: Add description for the new .option and assembler
|
|
|
|
|
|
options.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
|
|
|
|
|
|
the CSR checking.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 11:18:49 +01:00
|
|
|
|
* config/tc-riscv.c (csr_extra_hash): New.
|
|
|
|
|
|
(enum riscv_csr_class): New enum. Used to decide
|
|
|
|
|
|
whether or not this CSR is legal in the current ISA string.
|
|
|
|
|
|
(struct riscv_csr_extra): New structure to hold all extra information
|
|
|
|
|
|
of CSR.
|
|
|
|
|
|
(riscv_init_csr_hashes): New. According to the DECLARE_CSR and
|
|
|
|
|
|
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
|
|
|
|
|
|
Call hash_reg_name to insert CSR address into reg_names_hash.
|
|
|
|
|
|
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
|
|
|
|
|
|
Decide whether the CSR is valid according to the csr_extra_hash.
|
|
|
|
|
|
(reg_lookup_internal): Call reg_csr_lookup_internal for CSRs.
|
|
|
|
|
|
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
|
|
|
|
|
|
not a boolean. This is same as riscv_init_csr_hash, so keep the
|
|
|
|
|
|
consistent usage.
|
|
|
|
|
|
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
|
|
|
|
|
|
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
|
|
|
|
|
|
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
|
|
|
|
|
|
f-ext CSR are not allowed.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
|
|
|
|
|
|
source file is `priv-reg.s`, and the ISA is rv64if, so the
|
|
|
|
|
|
rv32-only CSR are not allowed.
|
|
|
|
|
|
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
|
|
|
|
|
|
|
2020-02-20 14:05:21 +01:00
|
|
|
|
2020-02-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32.
|
|
|
|
|
|
(tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
|
|
|
|
|
|
|
PR25569, PDP11 ld -s clobbers last data byte
This patch fixes an ancient wart in aout support, in that text and
data section sizes are rounded up for alignment rather that just the
corresponding header sizes. Changing section sizes could conceivably
result in buffer overflows if section contents were held in memory.
Also, keeping the original section sizes allows this PR to be fixed
nicely.
bfd/
PR 25569
* aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use
"text", "data" and "bss" section pointer vars. Don't update
section size, just exec header sizes.
(adjust_sizes_and_vmas): Don't update text section size. Set
initial exec header a_text. Print exec headers sizes.
* pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic),
(adjust_sizes_and_vmas): Similarly. Formatting.
(final_link): Correct final file extension.
gas/
PR 25569
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
on section size adjustment, instead perform another write if
exec header size is larger than section size.
2020-02-20 12:23:44 +01:00
|
|
|
|
2020-02-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25569
|
|
|
|
|
|
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
|
|
|
|
|
|
on section size adjustment, instead perform another write if
|
|
|
|
|
|
exec header size is larger than section size.
|
|
|
|
|
|
|
2020-02-06 04:14:21 +01:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-riscv.texi: Add the doc entries for -march-attr/
|
|
|
|
|
|
-mno-arch-attr command line options.
|
|
|
|
|
|
|
2020-02-19 23:51:07 +01:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/c-add-addi.d: New testcase.
|
|
|
|
|
|
* testsuite/gas/riscv/c-add-addi.s: Likewise.
|
|
|
|
|
|
|
2020-02-19 18:46:10 +01:00
|
|
|
|
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25576
|
|
|
|
|
|
* config/tc-z80.c (md_parse_option): Do not use an underscore
|
|
|
|
|
|
prefix for local labels in SDCC compatability mode.
|
|
|
|
|
|
(z80_start_line_hook): Remove SDCC dollar label support.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.s: Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25517
|
|
|
|
|
|
* config/tc-z80.c: Add -march option.
|
|
|
|
|
|
* doc/as.texi: Update Z80 documentation.
|
|
|
|
|
|
* doc/c-z80.texi: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_all.d: Update command line.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/gbz80_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_extra.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_ii8.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/r800_z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/sdcc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z180.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z180_z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_doc.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_ii8.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_in_f_c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_out_c_0.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80_sli.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_all.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_reloc.d: Likewise.
|
|
|
|
|
|
|
2020-02-19 13:54:45 +01:00
|
|
|
|
2020-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
|
|
|
|
|
|
with GNU_PROPERTY_X86_FEATURE_2_MMX.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run property-3 and
|
|
|
|
|
|
x86-64-property-3.
|
|
|
|
|
|
* testsuite/gas/i386/property-3.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/property-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
|
|
|
|
|
|
|
2020-02-17 16:12:10 +01:00
|
|
|
|
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .popcnt.
|
|
|
|
|
|
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
|
|
|
|
|
|
Add a tab before @samp{.sse4a}.
|
|
|
|
|
|
|
2020-02-17 08:59:07 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Don't try to guess a suffix
|
|
|
|
|
|
for AddrPrefixOpReg templates. Combine the two pieces of
|
|
|
|
|
|
addrprefixopreg handling. Reject 16-bit address reg in 64-bit
|
|
|
|
|
|
mode.
|
|
|
|
|
|
|
2020-02-17 08:57:54 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/14439
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Also suppress operand
|
|
|
|
|
|
swapping for MONITOR{,X} and MWAIT{,X}.
|
|
|
|
|
|
* testsuite/gas/i386/sse3.s, testsuite/gas/i386/x86-64-sse3.s:
|
|
|
|
|
|
Add Intel syntax monitor/mwait tests.
|
|
|
|
|
|
* testsuite/gas/i386/sse3.d, testsuite/gas/i386/x86-64-sse3.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
*testsuite/gas/i386/sse3-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse3-intel.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-02-17 08:56:18 +01:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/6518
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Re-work Intel-syntax
|
|
|
|
|
|
[XYZ]MMWord memory operand ambiguity recognition logic (largely
|
|
|
|
|
|
re-indentation).
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps
|
|
|
|
|
|
cases.
|
|
|
|
|
|
* testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/inval-avx.l,
|
|
|
|
|
|
testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-ambig.s,
|
|
|
|
|
|
testsuite/gas/i386/avx512vl-ambig.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-16 17:36:51 +01:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
|
|
|
|
|
|
nosse4.
|
|
|
|
|
|
* doc/c-i386.texi: Document sse4a and nosse4a.
|
|
|
|
|
|
|
2020-02-14 15:09:28 +01:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi: Remove the old movsx and movzx documentation
|
|
|
|
|
|
for AT&T syntax.
|
|
|
|
|
|
|
2020-02-14 14:27:28 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Move movsx/movzx special
|
|
|
|
|
|
casing ...
|
|
|
|
|
|
(process_suffix): ... here. Consider just the first operand
|
|
|
|
|
|
initially.
|
|
|
|
|
|
(check_long_reg): Drop opcode 0x63 special case again.
|
|
|
|
|
|
* testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s,
|
|
|
|
|
|
testsuite/gas/i386/ilp32/x86-64.s, testsuite/gas/i386/x86_64.s:
|
|
|
|
|
|
Move ambiguous operand size tests ...
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: ... here.
|
|
|
|
|
|
* testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d
|
|
|
|
|
|
testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d,
|
|
|
|
|
|
testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
|
|
|
|
|
|
testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l,
|
|
|
|
|
|
testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-movsxd.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-movsxd-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86_64.d, testsuite/gas/i386/x86_64-intel.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l,
|
|
|
|
|
|
testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l,
|
|
|
|
|
|
testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-02-14 14:04:23 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Also skip segment
|
|
|
|
|
|
override prefix emission if it matches an already present one.
|
|
|
|
|
|
* testsuite/gas/i386/prefix32.s: Add double segment override
|
|
|
|
|
|
cases.
|
|
|
|
|
|
* testsuite/gas/i386/prefix32.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-14 14:03:19 +01:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Drop ineffectual segment
|
|
|
|
|
|
overrides when optimizing.
|
|
|
|
|
|
* testsuite/gas/i386/lea-optimize.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
|
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
2020-02-14 14:02:05 +01:00
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_operands): Also check insn prefix
|
|
|
|
|
|
for ineffectual segment override warning. Don't cover possible
|
|
|
|
|
|
VEX/EVEX encoded insns there.
|
|
|
|
|
|
* testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d,
|
|
|
|
|
|
testsuite/gas/i386/lea.e: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-14 13:57:01 +01:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
|
|
|
|
|
|
syntax.
|
|
|
|
|
|
|
2020-02-13 22:44:17 +01:00
|
|
|
|
2020-02-13 Fangrui Song <maskray@google.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25551
|
|
|
|
|
|
* config/tc-i386.c (tc_i386_fix_adjustable): Don't check
|
|
|
|
|
|
BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4.
|
|
|
|
|
|
* testsuite/gas/i386/relax-5.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/relax-5.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-relax-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-relax-4.s: Likewise.
|
|
|
|
|
|
|
2020-02-13 10:19:28 +01:00
|
|
|
|
2020-02-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in
|
|
|
|
|
|
"nosse4" entry.
|
|
|
|
|
|
|
2020-02-12 16:20:56 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (avx512): New (at file scope), moved from
|
|
|
|
|
|
(check_VecOperands): ... here.
|
|
|
|
|
|
(process_suffix): Add [XYZ]MMword operand size handling.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS
|
|
|
|
|
|
tests.
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/noavx512-2.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-12 16:19:03 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24546
|
|
|
|
|
|
* config/tc-i386.c (match_template): Apply AMD64 check to 64-bit
|
|
|
|
|
|
code only.
|
|
|
|
|
|
* config/tc-i386-intel.c (i386_intel_operand): Also handle
|
|
|
|
|
|
CALL/JMP in O_tbyte_ptr case.
|
|
|
|
|
|
* doc/c-i386.texi: Mention far call and full pointer load ISA
|
|
|
|
|
|
differences.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-3.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-3.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-5.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-5.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-02-12 10:59:32 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (REGISTER_WARNINGS): Delete.
|
|
|
|
|
|
(check_byte_reg): Skip only source operand of CRC32. Drop Non-
|
|
|
|
|
|
64-bit-only warning.
|
|
|
|
|
|
(check_word_reg): Consistently error on mismatching register
|
|
|
|
|
|
size and suffix.
|
|
|
|
|
|
* testsuite/gas/i386/general.s: Replace dword GPR with word one
|
|
|
|
|
|
for movw. Replace suffix / GPR for orb.
|
|
|
|
|
|
* testsuite/gas/i386/inval.s: Add tests for movw with dword and
|
|
|
|
|
|
byte GPRs as well as ones for inb/outb with a word accumulator.
|
|
|
|
|
|
* testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l,
|
|
|
|
|
|
testsuite/gas/i386/inval.l: Adjust expectations.
|
|
|
|
|
|
|
2020-02-12 10:58:42 +01:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (operand_type_register_match): Also fall
|
|
|
|
|
|
through initial two if()-s when the template allows for a GPR
|
|
|
|
|
|
operand. Adjust comment.
|
|
|
|
|
|
|
2020-02-11 11:20:55 +01:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
(struct _i386_insn): New field "short_form".
|
|
|
|
|
|
(optimize_encoding): Drop setting of shortform field.
|
|
|
|
|
|
(process_suffix): Set i.short_form. Replace shortform use.
|
|
|
|
|
|
(process_operands): Replace shortform use.
|
|
|
|
|
|
|
2020-02-11 11:17:33 +01:00
|
|
|
|
2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (vcx_handle_register_arguments): Remove `for`
|
|
|
|
|
|
loop initial declaration.
|
|
|
|
|
|
|
2020-02-10 17:39:02 +01:00
|
|
|
|
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
|
|
|
|
|
|
instructions that can have 5 arguments.
|
|
|
|
|
|
(enum operand_parse_code): Add new operands.
|
|
|
|
|
|
(parse_operands): Account for new operands.
|
|
|
|
|
|
(S5): New macro.
|
|
|
|
|
|
(enum neon_shape_el): Introduce P suffixes for coprocessor.
|
|
|
|
|
|
(neon_select_shape): Account for P suffix.
|
|
|
|
|
|
(LOW1): Move macro to global position.
|
|
|
|
|
|
(HI4): Move macro to global position.
|
|
|
|
|
|
(vcx_assign_vec_d): New.
|
|
|
|
|
|
(vcx_assign_vec_m): New.
|
|
|
|
|
|
(vcx_assign_vec_n): New.
|
|
|
|
|
|
(enum vcx_reg_type): New.
|
|
|
|
|
|
(vcx_get_reg_type): New.
|
|
|
|
|
|
(vcx_size_pos): New.
|
|
|
|
|
|
(vcx_vec_pos): New.
|
|
|
|
|
|
(vcx_handle_shape): New.
|
|
|
|
|
|
(vcx_ensure_register_in_range): New.
|
|
|
|
|
|
(vcx_handle_register_arguments): New.
|
|
|
|
|
|
(vcx_handle_insn_block): New.
|
|
|
|
|
|
(vcx_handle_common_checks): New.
|
|
|
|
|
|
(do_vcx1): New.
|
|
|
|
|
|
(do_vcx2): New.
|
|
|
|
|
|
(do_vcx3): New.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-fp.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-fp.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-mve.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-missing-mve.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve-or-neon.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve-or-neon.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-mve.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.l:
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.s:
|
|
|
|
|
|
* testsuite/gas/arm/cde.d:
|
|
|
|
|
|
* testsuite/gas/arm/cde.s:
|
|
|
|
|
|
|
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 17:38:00 +01:00
|
|
|
|
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
|
|
|
|
|
|
Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
|
|
|
|
|
|
CDE coprocessor that can be enabled.
|
|
|
|
|
|
(enum pred_instruction_type): New pred type.
|
|
|
|
|
|
(BAD_NO_VPT): New error message.
|
|
|
|
|
|
(BAD_CDE): New error message.
|
|
|
|
|
|
(BAD_CDE_COPROC): New error message.
|
|
|
|
|
|
(enum operand_parse_code): Add new immediate operands.
|
|
|
|
|
|
(parse_operands): Account for new immediate operands.
|
|
|
|
|
|
(check_cde_operand): New.
|
|
|
|
|
|
(cde_coproc_enabled): New.
|
|
|
|
|
|
(cde_coproc_pos): New.
|
|
|
|
|
|
(cde_handle_coproc): New.
|
|
|
|
|
|
(cxn_handle_predication): New.
|
|
|
|
|
|
(do_custom_instruction_1): New.
|
|
|
|
|
|
(do_custom_instruction_2): New.
|
|
|
|
|
|
(do_custom_instruction_3): New.
|
|
|
|
|
|
(do_cx1): New.
|
|
|
|
|
|
(do_cx1a): New.
|
|
|
|
|
|
(do_cx1d): New.
|
|
|
|
|
|
(do_cx1da): New.
|
|
|
|
|
|
(do_cx2): New.
|
|
|
|
|
|
(do_cx2a): New.
|
|
|
|
|
|
(do_cx2d): New.
|
|
|
|
|
|
(do_cx2da): New.
|
|
|
|
|
|
(do_cx3): New.
|
|
|
|
|
|
(do_cx3a): New.
|
|
|
|
|
|
(do_cx3d): New.
|
|
|
|
|
|
(do_cx3da): New.
|
|
|
|
|
|
(handle_pred_state): Define new IT block behaviour.
|
|
|
|
|
|
(insns): Add newn CX*{,d}{,a} instructions.
|
|
|
|
|
|
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
|
|
|
|
|
|
Define new cdecp extension strings.
|
|
|
|
|
|
* doc/c-arm.texi: Document new cdecp extension arguments.
|
|
|
|
|
|
* testsuite/gas/arm/cde-scalar.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-scalar.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.l: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde-warnings.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/cde.s: New test.
|
|
|
|
|
|
|
2020-02-10 17:37:22 +01:00
|
|
|
|
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25516
|
|
|
|
|
|
* config/tc-i386.c (intel64): Renamed to ...
|
|
|
|
|
|
(isa64): This.
|
|
|
|
|
|
(match_template): Accept Intel64 only instruction by default.
|
|
|
|
|
|
(i386_displacement): Updated.
|
|
|
|
|
|
(md_parse_option): Updated.
|
|
|
|
|
|
* c-i386.texi: Update -mamd64/-mintel64 documentation.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
|
|
|
|
|
|
-mamd64 to x86-64-sysenter-amd.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sysenter.d: New file.
|
|
|
|
|
|
|
2020-02-06 15:12:45 +01:00
|
|
|
|
2020-02-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section): Error for section
|
|
|
|
|
|
type, attr or entsize changes in assembly.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test.
|
|
|
|
|
|
* testsuite/gas/elf/section5.l: Update.
|
|
|
|
|
|
|
2020-02-10 01:57:16 +01:00
|
|
|
|
2020-02-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* output-file.c (output_file_close): Do a normal close when
|
|
|
|
|
|
flag_always_generate_output.
|
|
|
|
|
|
* write.c (write_object_file): Don't stop output when
|
|
|
|
|
|
flag_always_generate_output.
|
|
|
|
|
|
|
2020-02-07 15:53:46 +01:00
|
|
|
|
2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25469
|
|
|
|
|
|
* config/tc-z80.c: Add -gbz80 command line option to generate code
|
|
|
|
|
|
for the GameBoy Z80. Add support for generating DWARF.
|
|
|
|
|
|
* config/tc-z80.h: Add support for DWARF debug information
|
|
|
|
|
|
generation.
|
|
|
|
|
|
* doc/c-z80.texi: Document new command line option.
|
|
|
|
|
|
* testsuite/gas/z80/gbz80_all.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/gbz80_all.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80.exp: Run the new tests.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_all.d: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_all.s: New file.
|
|
|
|
|
|
* testsuite/gas/z80/z80n_reloc.d: New file.
|
|
|
|
|
|
|
ELF: Support the section flag 'o' in .section directive
As shown in
https://sourceware.org/bugzilla/show_bug.cgi?id=25490
--gc-sections will silently remove __patchable_function_entries section
and generate corrupt result. This patch adds the section flag 'o' to
.section directive:
.section __patchable_function_entries,"awo",@progbits,foo
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat
.section __patchable_function_entries,"awo",@progbits,bar,unique,4
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1
which specifies the symbol name which the section references. Assmebler
will set its elf_linked_to_section to a local section where the symbol
is defined.
Linker is updated to call mark_hook if gc_mark of any of its linked-to
sections is set after all sections, except for backend specific ones,
have been garbage collected.
bfd/
PR gas/25381
* bfd-in2.h: Regenerated.
* elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook
on section if gc_mark of any of its linked-to sections is set
and don't set gc_mark again.
* section.c (asection): Add linked_to_symbol_name to map_head
union.
gas/
PR gas/25381
* config/obj-elf.c (get_section): Also check
linked_to_symbol_name.
(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
(obj_elf_parse_section_letters): Handle the 'o' flag.
(build_group_lists): Renamed to ...
(build_additional_section_info): This. Set elf_linked_to_section
from map_head.linked_to_symbol_name.
(elf_adjust_symtab): Updated.
* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
* doc/as.texi: Document the 'o' flag.
* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
* testsuite/gas/elf/section18.d: New file.
* testsuite/gas/elf/section18.s: Likewise.
* testsuite/gas/elf/section19.d: Likewise.
* testsuite/gas/elf/section19.s: Likewise.
* testsuite/gas/elf/section20.d: Likewise.
* testsuite/gas/elf/section20.s: Likewise.
* testsuite/gas/elf/section21.d: Likewise.
* testsuite/gas/elf/section21.l: Likewise.
* testsuite/gas/elf/section21.s: Likewise.
ld/
PR ld/24526
PR ld/25021
PR ld/25490
* testsuite/ld-elf/elf.exp: Run PR ld/25490 tests.
* testsuite/ld-elf/pr24526.d: New file.
* testsuite/ld-elf/pr24526.s: Likewise.
* testsuite/ld-elf/pr25021.d: Likewise.
* testsuite/ld-elf/pr25021.s: Likewise.
* testsuite/ld-elf/pr25490-2-16.rd: Likewise.
* testsuite/ld-elf/pr25490-2-32.rd: Likewise.
* testsuite/ld-elf/pr25490-2-64.rd: Likewise.
* testsuite/ld-elf/pr25490-2.s: Likewise.
* testsuite/ld-elf/pr25490-3-16.rd: Likewise.
* testsuite/ld-elf/pr25490-3-32.rd: Likewise.
* testsuite/ld-elf/pr25490-3-64.rd: Likewise.
* testsuite/ld-elf/pr25490-3.s: Likewise.
* testsuite/ld-elf/pr25490-4-16.rd: Likewise.
* testsuite/ld-elf/pr25490-4-32.rd: Likewise.
* testsuite/ld-elf/pr25490-4-64.rd: Likewise.
* testsuite/ld-elf/pr25490-4.s: Likewise.
* testsuite/ld-elf/pr25490-5-16.rd: Likewise.
* testsuite/ld-elf/pr25490-5-32.rd: Likewise.
* testsuite/ld-elf/pr25490-5-64.rd: Likewise.
* testsuite/ld-elf/pr25490-5.s: Likewise.
* testsuite/ld-elf/pr25490-6-16.rd: Likewise.
* testsuite/ld-elf/pr25490-6-32.rd: Likewise.
* testsuite/ld-elf/pr25490-6-64.rd: Likewise.
* testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-07 03:04:58 +01:00
|
|
|
|
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25381
|
|
|
|
|
|
* config/obj-elf.c (get_section): Also check
|
|
|
|
|
|
linked_to_symbol_name.
|
|
|
|
|
|
(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
|
|
|
|
|
|
(obj_elf_parse_section_letters): Handle the 'o' flag.
|
|
|
|
|
|
(build_group_lists): Renamed to ...
|
|
|
|
|
|
(build_additional_section_info): This. Set elf_linked_to_section
|
|
|
|
|
|
from map_head.linked_to_symbol_name.
|
|
|
|
|
|
(elf_adjust_symtab): Updated.
|
|
|
|
|
|
* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
|
|
|
|
|
|
* doc/as.texi: Document the 'o' flag.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
|
|
|
|
|
|
* testsuite/gas/elf/section18.d: New file.
|
|
|
|
|
|
* testsuite/gas/elf/section18.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section19.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section19.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section20.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section20.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section21.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section21.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section21.s: Likewise.
|
|
|
|
|
|
|
2020-02-06 16:50:16 +01:00
|
|
|
|
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Mention x86 assembler options to align branches for
|
|
|
|
|
|
binutils 2.34.
|
|
|
|
|
|
|
2020-02-06 13:44:39 +01:00
|
|
|
|
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique
|
|
|
|
|
|
only for ELF targets.
|
|
|
|
|
|
* testsuite/gas/i386/unique.d: Don't xfail.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
|
|
|
|
|
|
2020-02-06 01:22:29 +01:00
|
|
|
|
2020-02-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/unique.d: xfail for non-elf targets.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
|
|
|
|
|
|
2020-02-05 06:49:17 +01:00
|
|
|
|
2020-02-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in
|
|
|
|
|
|
xfail, and rename test.
|
|
|
|
|
|
* testsuite/gas/elf/section12b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16b.d: Likewise.
|
|
|
|
|
|
|
ELF: Add support for unique section ID to assembler
Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-03 02:07:51 +01:00
|
|
|
|
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25380
|
|
|
|
|
|
* config/obj-elf.c (section_match): Removed.
|
|
|
|
|
|
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
|
|
|
|
|
|
section_id.
|
|
|
|
|
|
(obj_elf_change_section): Replace info and group_name arguments
|
|
|
|
|
|
with match_p. Also update the section ID and flags from match_p.
|
|
|
|
|
|
(obj_elf_section): Handle "unique,N". Update call to
|
|
|
|
|
|
obj_elf_change_section.
|
|
|
|
|
|
* config/obj-elf.h (elf_section_match): New.
|
|
|
|
|
|
(obj_elf_change_section): Updated.
|
|
|
|
|
|
* config/tc-arm.c (start_unwind_section): Update call to
|
|
|
|
|
|
obj_elf_change_section.
|
|
|
|
|
|
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (microblaze_s_data): Likewise.
|
|
|
|
|
|
(microblaze_s_sdata): Likewise.
|
|
|
|
|
|
(microblaze_s_rdata): Likewise.
|
|
|
|
|
|
(microblaze_s_bss): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (s_change_section): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_profiler): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (parse_rx_section): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
|
|
|
|
|
|
* doc/as.texi: Document "unique,N" in .section directive.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
|
|
|
|
|
|
* testsuite/gas/elf/section15.d: New file.
|
|
|
|
|
|
* testsuite/gas/elf/section15.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section16b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/section17.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/unique.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/unique.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unique.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
|
|
|
|
|
|
|
2020-02-02 17:20:18 +01:00
|
|
|
|
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
|
|
|
|
|
|
|
2020-02-02 02:59:19 +01:00
|
|
|
|
2020-02-01 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-moxie.c (md_begin): Don't force big-endian mode.
|
|
|
|
|
|
|
2020-01-31 19:32:48 +01:00
|
|
|
|
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_cons): Handle %gotoff as well as
|
|
|
|
|
|
%tls_ldo.
|
|
|
|
|
|
|
2020-01-31 18:13:18 +01:00
|
|
|
|
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25472
|
|
|
|
|
|
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
|
|
|
|
|
|
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
|
|
|
|
|
|
+mve.
|
|
|
|
|
|
* testsuite/gas/arm/mve_dsp.d: New test.
|
|
|
|
|
|
|
2020-01-31 17:43:57 +01:00
|
|
|
|
2020-01-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE
|
|
|
|
|
|
rather than BFD_RELOC_NONE.
|
|
|
|
|
|
|
2020-01-31 17:16:19 +01:00
|
|
|
|
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
|
|
|
|
|
|
to support VLDMIA instruction for MVE.
|
|
|
|
|
|
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
|
|
|
|
|
|
instruction for MVE.
|
|
|
|
|
|
* testsuite/gas/arm/mve-ldst.d: New test.
|
|
|
|
|
|
* testsuite/gas/arm/mve-ldst.s: Likewise.
|
|
|
|
|
|
|
2020-01-31 15:45:51 +01:00
|
|
|
|
2020-01-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po: Updated French translation.
|
|
|
|
|
|
* po/ru.po: Updated Russian translation.
|
|
|
|
|
|
|
2020-01-31 09:03:56 +01:00
|
|
|
|
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
|
|
|
|
|
|
.s for the movprfx.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.d,
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.l,
|
|
|
|
|
|
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
|
|
|
|
|
|
|
2020-01-30 17:03:22 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_disp): Tighten base_opcode check.
|
|
|
|
|
|
* testsuite/gas/i386/got.s: Add LSL, MOVLPS, and BNDCN cases.
|
|
|
|
|
|
* testsuite/gas/i386/got-no-relax.d, testsuite/gas/i386/got.d:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
|
2020-01-30 13:59:04 +01:00
|
|
|
|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
|
|
|
|
|
|
* testsuite/gas/bpf/alu-be.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
|
|
|
|
|
|
* testsuite/gas/bpf/alu32-be.d: Likewise.
|
|
|
|
|
|
|
2020-01-30 11:36:33 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-2.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-4.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch.s: Add RETW cases.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-branch.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-2.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch-4.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-branch.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-30 11:35:20 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): .
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add IRET and LRET cases.
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET.
|
|
|
|
|
|
Add LRETQ case.
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without
|
|
|
|
|
|
suffix.
|
|
|
|
|
|
testsuite/gas/i386/x86_64.s: Add RETF cases.
|
|
|
|
|
|
* testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86_64-intel.d
|
|
|
|
|
|
testsuite/gas/i386/x86_64.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-suffix.e,
|
|
|
|
|
|
testsuite/gas/i386/x86_64.e: New.
|
|
|
|
|
|
|
2020-01-30 11:33:53 +01:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Redo and move FLDENV et al
|
|
|
|
|
|
special case.
|
|
|
|
|
|
|
2020-01-27 13:38:10 +01:00
|
|
|
|
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/25445
|
|
|
|
|
|
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
|
|
|
|
|
|
movsxd.
|
|
|
|
|
|
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
|
|
|
|
|
|
differences. Document movslq and movsxd.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
|
|
|
|
|
|
|
2020-01-27 01:21:52 +01:00
|
|
|
|
2020-01-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Replace case statements with switch
|
|
|
|
|
|
statements.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Likewise.
|
|
|
|
|
|
* testsuite/gas/macros/macros.exp: Likewise.
|
|
|
|
|
|
* testsuite/lib/gas-defs.exp: Likewise.
|
|
|
|
|
|
|
2020-01-27 11:40:02 +01:00
|
|
|
|
2020-01-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25403
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_4-a.s: Likewise.
|
|
|
|
|
|
|
2020-01-23 01:45:04 +01:00
|
|
|
|
2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
|
|
|
|
|
|
s exts must be known, so rename *ok* to *fail*.
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-sx.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
|
|
|
|
|
|
above change.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.
|
|
|
|
|
|
|
2020-01-22 18:24:14 +01:00
|
|
|
|
2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* config/tc-i386.c (check_long_reg): Always disallow double word
|
|
|
|
|
|
suffix in mnemonic with word general register.
|
|
|
|
|
|
* testsuite/gas/i386/general.s: Replace word general register
|
|
|
|
|
|
with double word general register for movl.
|
|
|
|
|
|
* testsuite/gas/i386/inval.s: Add tests for movl with word general
|
|
|
|
|
|
register.
|
|
|
|
|
|
* testsuite/gas/i386/general.l: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/inval.l: Likewise.
|
|
|
|
|
|
|
PowerPC64 __tls_get_addr_desc
This implements register saving and restoring in the __tls_get_addr
call stub, so that when glibc supports the optimized tls call stub gcc
can generate code that assumes only r0, r12 and of course r3 are
changed on a __tls_get_addr call. When gcc expects __tls_get_addr
calls to preserve registers the call will be to __tls_get_addr_desc,
which will be translated by the linker to a call to __tls_get_addr_opt.
bfd/
* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
tga_desc_fd.
(is_tls_get_addr): Match tga_desc and tga_desc_df too.
(STDU_R1_0R1, ADDI_R1_R1): Define.
(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd. Indirect
tga_desc_fd to opt_fd, and tga_desc to opt. Set
no_tls_get_addr_regsave.
(branch_reloc_hash_match): Add hash3 and hash4.
(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
(ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_relocate_section): Likewise.
(plt_stub_size, build_plt_stub): Likewise. Size regsave
__tls_get_addr stub.
(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
eh_frame.
(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too. Size
eh_frame for regsave __tls_get_addr.
gas/
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
__tls_get_addr_desc and __tls_get_addr_opt.
ld/
* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
--tls-get-addr-regsave and --no-tls-get-addr-regsave.
(params): Init new field.
* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
Document.
* testsuite/ld-powerpc/tlsdesc.s,
* testsuite/ld-powerpc/tlsdesc.d,
* testsuite/ld-powerpc/tlsdesc.wf,
* testsuite/ld-powerpc/tlsdesc2.d,
* testsuite/ld-powerpc/tlsdesc2.wf,
* testsuite/ld-powerpc/tlsexenors.d,
* testsuite/ld-powerpc/tlsexenors.r,
* testsuite/ld-powerpc/tlsexers.d,
* testsuite/ld-powerpc/tlsexers.r,
* testsuite/ld-powerpc/tlsexetocnors.d,
* testsuite/ld-powerpc/tlsexetocrs.d,
* testsuite/ld-powerpc/tlsexetocrs.r,
* testsuite/ld-powerpc/tlsopt6.d,
* testsuite/ld-powerpc/tlsopt6.wf: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
2020-01-20 03:08:00 +01:00
|
|
|
|
2020-01-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
|
|
|
|
|
|
__tls_get_addr_desc and __tls_get_addr_opt.
|
|
|
|
|
|
|
2020-01-21 14:41:05 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.s: Add alignment directive.
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.l: Adjust expectations.
|
|
|
|
|
|
|
2020-01-21 08:30:05 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Merge CRC32 handling into
|
|
|
|
|
|
generic code path. Deal with No_lSuf being set in a template.
|
|
|
|
|
|
* testsuite/gas/i386/inval-crc32.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
|
|
|
|
|
|
instead of error(s) when operand size is ambiguous.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add CRC32 tests.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
|
|
|
|
|
|
Adjust expectations.
|
|
|
|
|
|
|
x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Drop SYSRET special case
|
|
|
|
|
|
and an intel_syntax check. Re-write lack-of-suffix processing
|
|
|
|
|
|
logic.
|
|
|
|
|
|
* doc/c-i386.texi: Document operand size defaults for suffix-
|
|
|
|
|
|
less AT&T syntax insns.
|
|
|
|
|
|
* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
|
|
|
|
|
|
testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx-scalar.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-bundle.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-lock-1.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse2avx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
|
|
|
|
|
|
* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-nops.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse-noavx.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
|
|
|
|
|
|
insns.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.s: Add further tests.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-nops.d,
|
|
|
|
|
|
testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
|
|
|
|
|
|
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
|
|
|
|
|
|
testsuite/gas/i386/sse-noavx.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-intel64.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-nops.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-opcode.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-ptwrite.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-simd.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sse-noavx.d
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
|
|
|
|
|
|
* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
|
|
|
|
|
|
testsuite/gas/i386/noreg64.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-01-21 08:25:31 +01:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx512_bf16_vl.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Add broadcast forms
|
|
|
|
|
|
of VCVTNEPS2BF16{X,Y}. Add operand-size less Intel syntax
|
|
|
|
|
|
broadcast forms of VCVTNEPS2BF16.
|
|
|
|
|
|
* testsuite/gas/i386/avx512_bf16_vl.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Adjust expectations.
|
|
|
|
|
|
|
2020-01-20 16:10:23 +01:00
|
|
|
|
2020-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
x86-64: Fix TLSDESC relaxation for x32
For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix
even if it isn't required. Otherwise linker can’t safely perform
GDesc -> IE/LE optimization. X32 TLSDESC sequences can be:
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
...
67 ff 10 call *x@TLSCALL(%eax)
or the same sequence as LP64:
48 8d 05 00 00 00 00 lea foo@TLSDESC(%rip), %reg
...
ff 10 call *foo@TLSCALL(%rax)
We need to support both sequences for x32. For both GDesc -> IE/LE
transitions,
67 ff 10 call *x@TLSCALL(%eax)
should relaxed to
0f 1f 00 nopl (%rax)
For GDesc -> LE transition,
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
should relaxed to
40 c7 c0 fc ff ff ff rex movl $x@tpoff, %reg
For GDesc -> IE transition,
40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg
should relaxed to
40 8b 05 00 00 00 00 rex movl x@gottpoff(%rip), %eax
bfd/
PR ld/25416
* elf64-x86-64.c (elf_x86_64_check_tls_transition): Support
"rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in
X32 mode.
(elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE
transition, relax "rex leal x@tlsdesc(%rip), %reg" to
"rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax
"rex leal x@tlsdesc(%rip), %reg" to
"rex movl x@gottpoff(%rip), %eax". For both transitions, relax
"call *(%eax)" to "nopl (%rax)".
gas/
PR ld/25416
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
x32 object.
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
R_X86_64_GOTPC32_TLSDESC relocation.
ld/
PR ld/25416
* testsuite/ld-x86-64/pr25416-1.s: New file
* testsuite/ld-x86-64/pr25416-1a.d: Likewise.
* testsuite/ld-x86-64/pr25416-1b.d: Likewise.
* testsuite/ld-x86-64/pr25416-1.s: Likewise.
* testsuite/ld-x86-64/pr25416-2.s: Likewise.
* testsuite/ld-x86-64/pr25416-2a.d: Likewise.
* testsuite/ld-x86-64/pr25416-2b.d: Likewise.
* testsuite/ld-x86-64/pr25416-3.d: Likewise.
* testsuite/ld-x86-64/pr25416-3.s: Likewise.
* testsuite/ld-x86-64/pr25416-4.d: Likewise.
* testsuite/ld-x86-64/pr25416-4.s: Likewise.
* testsuite/ld-x86-64/pr25416-5a.c: Likewise.
* testsuite/ld-x86-64/pr25416-5b.s: Likewise.
* testsuite/ld-x86-64/pr25416-5c.s: Likewise.
* testsuite/ld-x86-64/pr25416-5d.s: Likewise.
* testsuite/ld-x86-64/pr25416-5e.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
2020-01-20 15:58:51 +01:00
|
|
|
|
2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/25416
|
|
|
|
|
|
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
|
|
|
|
|
|
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
|
|
|
|
|
|
x32 object.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
|
|
|
|
|
|
R_X86_64_GOTPC32_TLSDESC relocation.
|
|
|
|
|
|
|
2020-01-18 15:12:07 +01:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/gas.pot: Regenerate.
|
|
|
|
|
|
|
2020-01-18 14:50:25 +01:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Binutils 2.34 branch created.
|
|
|
|
|
|
|
2020-01-17 16:07:55 +01:00
|
|
|
|
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
|
|
|
|
|
|
with vex_encoding_vex.
|
|
|
|
|
|
(parse_insn): Likewise.
|
|
|
|
|
|
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
|
|
|
|
|
|
and {vex3} documentation.
|
|
|
|
|
|
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
|
|
|
|
|
|
{vex}.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
|
|
|
|
|
|
|
2020-01-16 14:50:52 +01:00
|
|
|
|
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25376
|
|
|
|
|
|
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
|
|
|
|
|
|
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
|
|
|
|
|
|
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
|
|
|
|
|
|
|
2020-01-16 10:07:36 +01:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (match_template): Drop found_cpu_match local
|
|
|
|
|
|
variable.
|
|
|
|
|
|
|
2020-01-16 10:05:35 +01:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx512dq-inval.l,
|
|
|
|
|
|
testsuite/gas/i386/avx512dq-inval.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
2020-01-15 14:17:27 +01:00
|
|
|
|
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
|
|
|
|
|
|
relocations when the target is 430X, except when extracting part of an
|
|
|
|
|
|
expression.
|
|
|
|
|
|
(msp430_srcoperand): Adjust comment.
|
|
|
|
|
|
Initialize the expp member of the msp430_operand_s struct as
|
|
|
|
|
|
appropriate.
|
|
|
|
|
|
(msp430_dstoperand): Likewise.
|
|
|
|
|
|
* testsuite/gas/msp430/msp430.exp: Run new test.
|
|
|
|
|
|
* testsuite/gas/msp430/reloc-lo-430x.d: New test.
|
|
|
|
|
|
* testsuite/gas/msp430/reloc-lo-430x.s: New test.
|
|
|
|
|
|
|
2020-01-15 06:45:43 +01:00
|
|
|
|
2020-01-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Add sparc-*-freebsd case.
|
|
|
|
|
|
|
2020-01-14 17:59:37 +01:00
|
|
|
|
2020-01-14 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1a.d: Updated for Darwin.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1d.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1e.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1f.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1g.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1h.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-1i.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/align-branch-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a,
|
|
|
|
|
|
x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin.
|
|
|
|
|
|
|
2020-01-14 14:13:57 +01:00
|
|
|
|
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25377
|
|
|
|
|
|
* config/tc-z80.c: Add support for half precision, single
|
|
|
|
|
|
precision and double precision floating point values.
|
|
|
|
|
|
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
|
|
|
|
|
|
* doc/as.texi: Add new z80 command line options.
|
|
|
|
|
|
* doc/c-z80.texi: Document new z80 command line options.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.s: New test.
|
|
|
|
|
|
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/z80/z80.exp: Run the new test.
|
|
|
|
|
|
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
|
|
|
|
|
|
* testsuite/gas/z80/fp_zeda32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/z80/strings.d: Update expected output.
|
|
|
|
|
|
|
2020-01-13 16:31:39 +01:00
|
|
|
|
2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
|
|
|
|
|
|
dependency.
|
|
|
|
|
|
|
2020-01-13 10:16:47 +01:00
|
|
|
|
2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
|
|
|
|
|
|
the CPU.
|
|
|
|
|
|
* config/tc-arc.h: Add header if/defs.
|
|
|
|
|
|
* testsuite/gas/arc/pseudos.d: Improve matching pattern.
|
|
|
|
|
|
|
2020-01-13 04:57:19 +01:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/wasm32/allinsn.d: Update expected output.
|
|
|
|
|
|
|
2020-01-12 10:46:22 +01:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
|
|
|
|
|
|
insertion.
|
|
|
|
|
|
|
2020-01-10 07:59:59 +01:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/pr14891.s: Don't start directives in first column.
|
|
|
|
|
|
* testsuite/gas/elf/pr21661.d: Don't run on hpux.
|
|
|
|
|
|
|
2020-01-09 12:47:44 +01:00
|
|
|
|
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25224
|
|
|
|
|
|
* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
|
|
|
|
|
|
opcode byte values.
|
|
|
|
|
|
(emit_ld_r_r): Likewise.
|
|
|
|
|
|
(emit_ld_rr_m): Likewise.
|
|
|
|
|
|
(emit_ld_rr_nn): Likewise.
|
|
|
|
|
|
|
2020-01-09 11:40:04 +01:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (optimize_encoding): Add
|
|
|
|
|
|
is_any_vex_encoding() invocations. Drop respective
|
|
|
|
|
|
i.tm.extension_opcode == None checks.
|
|
|
|
|
|
|
2020-01-09 11:39:33 +01:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Check RegRex is clear during
|
|
|
|
|
|
REX transformations. Correct comment indentation.
|
|
|
|
|
|
|
2020-01-09 11:38:59 +01:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (optimize_encoding): Generalize register
|
|
|
|
|
|
transformation for TEST optimization.
|
|
|
|
|
|
|
2020-01-09 11:38:01 +01:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-sysenter-amd.s,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sysenter-amd.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sysenter-amd.l,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sysenter-intel.d,
|
|
|
|
|
|
testsuite/gas/i386/x86-64-sysenter-mixed.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2020-01-08 18:00:54 +01:00
|
|
|
|
2020-01-08 Nick Clifton <nickc@redhat.com>
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PR 25284
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* doc/as.texi (Align): Document the fact that all arguments can be
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omitted.
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(Balign): Likewise.
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(P2align): Likewise.
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2020-01-08 17:30:20 +01:00
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2020-01-08 Nick Clifton <nickc@redhat.com>
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PR 14891
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* config/obj-elf.c (obj_elf_section): Fail if the section name is
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already defined as a different symbol type.
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* testsuite/gas/elf/pr14891.s: New test source file.
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* testsuite/gas/elf/pr14891.d: New test driver.
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* testsuite/gas/elf/pr14891.s: New test expected error output.
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* testsuite/gas/elf/elf.exp: Run the new test.
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2020-01-08 02:12:36 +01:00
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2020-01-08 Alan Modra <amodra@gmail.com>
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* config/tc-z8k.c (md_begin): Make idx unsigned.
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(get_specific): Likewise for this_index.
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2020-01-07 14:29:16 +01:00
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2020-01-07 Claudiu Zissulescu <claziss@synopsys.com>
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* onfig/tc-arc.c (parse_reloc_symbol): New function.
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(tokenize_arguments): Clean up, use parse_reloc_symbol function.
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(md_operand): Set X_md to absent.
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(arc_parse_name): Check for X_md.
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2020-01-03 17:23:19 +01:00
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2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25311
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* as.h (TC_STRING_ESCAPES): Provide a default definition.
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* app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of
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NO_STRING_ESCAPES.
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* read.c (next_char_of_string): Likewise.
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* config/tc-ppc.h (TC_STRING_ESCAPES): Define.
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* config/tc-z80.h (TC_STRING_ESCAPES): Define.
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2020-01-03 13:59:54 +01:00
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2020-01-03 Nick Clifton <nickc@redhat.com>
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* po/sv.po: Updated Swedish translation.
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2020-01-03 10:16:44 +01:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
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* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
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2020-01-03 10:14:16 +01:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
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by-element usdot. Add 64-bit form tests for by-element sudot.
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* testsuite/gas/aarch64/i8mm.d: Adjust expectations.
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2020-01-03 10:13:31 +01:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
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* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
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2020-01-03 10:12:49 +01:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/f64mm.d,
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testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
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2020-01-02 15:10:40 +01:00
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2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
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* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add
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support for assembler code generated by SDCC. Add new relocation
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types. Add z80-elf target support.
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* config/tc-z80.h: Add z80-elf target support. Enable dollar local
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labels. Local labels starts from ".L".
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* NEWS: Mention the new support.
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* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
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* testsuite/gas/all/fwdexp.s: Likewise.
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* testsuite/gas/all/cond.l: Likewise.
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* testsuite/gas/all/cond.s: Likewise.
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* testsuite/gas/all/fwdexp.d: Likewise.
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* testsuite/gas/all/fwdexp.s: Likewise.
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* testsuite/gas/elf/section2.e-mips: Likewise.
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* testsuite/gas/elf/section2.l: Likewise.
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* testsuite/gas/elf/section2.s: Likewise.
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* testsuite/gas/macros/app1.d: Likewise.
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* testsuite/gas/macros/app1.s: Likewise.
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* testsuite/gas/macros/app2.d: Likewise.
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* testsuite/gas/macros/app2.s: Likewise.
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* testsuite/gas/macros/app3.d: Likewise.
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* testsuite/gas/macros/app3.s: Likewise.
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* testsuite/gas/macros/app4.d: Likewise.
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* testsuite/gas/macros/app4.s: Likewise.
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* testsuite/gas/macros/app4b.s: Likewise.
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* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
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* testsuite/gas/z80/z80.exp: Add new tests
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* testsuite/gas/z80/dollar.d: New file.
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* testsuite/gas/z80/dollar.s: New file.
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* testsuite/gas/z80/ez80_adl_all.d: New file.
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* testsuite/gas/z80/ez80_adl_all.s: New file.
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* testsuite/gas/z80/ez80_adl_suf.d: New file.
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* testsuite/gas/z80/ez80_isuf.s: New file.
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* testsuite/gas/z80/ez80_z80_all.d: New file.
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* testsuite/gas/z80/ez80_z80_all.s: New file.
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* testsuite/gas/z80/ez80_z80_suf.d: New file.
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* testsuite/gas/z80/r800_extra.d: New file.
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* testsuite/gas/z80/r800_extra.s: New file.
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* testsuite/gas/z80/r800_ii8.d: New file.
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* testsuite/gas/z80/r800_z80_doc.d: New file.
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* testsuite/gas/z80/z180.d: New file.
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* testsuite/gas/z80/z180.s: New file.
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* testsuite/gas/z80/z180_z80_doc.d: New file.
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* testsuite/gas/z80/z80_doc.d: New file.
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* testsuite/gas/z80/z80_doc.s: New file.
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* testsuite/gas/z80/z80_ii8.d: New file.
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* testsuite/gas/z80/z80_ii8.s: New file.
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* testsuite/gas/z80/z80_in_f_c.d: New file.
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* testsuite/gas/z80/z80_in_f_c.s: New file.
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* testsuite/gas/z80/z80_op_ii_ld.d: New file.
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* testsuite/gas/z80/z80_op_ii_ld.s: New file.
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* testsuite/gas/z80/z80_out_c_0.d: New file.
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* testsuite/gas/z80/z80_out_c_0.s: New file.
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* testsuite/gas/z80/z80_reloc.d: New file.
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* testsuite/gas/z80/z80_reloc.s: New file.
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* testsuite/gas/z80/z80_sli.d: New file.
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* testsuite/gas/z80/z80_sli.s: New file.
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2019-10-21 17:59:11 +02:00
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2020-01-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
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REGLIST_RN.
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2020-01-01 09:22:19 +01:00
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2020-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2020-01-01 08:37:11 +01:00
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For older changes see ChangeLog-2019
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2016-01-01 11:44:31 +01:00
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2020-01-01 08:37:11 +01:00
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Copyright (C) 2020 Free Software Foundation, Inc.
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2016-01-01 11:44:31 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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