If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are
all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv
when disassembling VEX and EVEX instructions.
gas/
PR binutils/24626
* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
and EVEX.vvvv.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24626
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
EVEX.vvvv when disassembling VEX and EVEX instructions.
(OP_VEX): Set vex.register_specifier to 0 after readding
vex.register_specifier.
(OP_Vex_2src_1): Likewise.
(OP_Vex_2src_2): Likewise.
(OP_LWP_E): Likewise.
(OP_EX_Vex): Don't check vex.register_specifier.
(OP_XMM_Vex): Likewise.
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.
gas/
PR gas/24625
* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
instructions with invalid broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
opcodes/
PR gas/24625
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
Disp8ShiftVL.
* i386-tbl.h: Regenerated.
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
This patch adds support for the Linux kernel eBPF architecture to the
opcodes. The port is based on CGEN.
opcodes/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
* configure: Regenerated.
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
and cpu/bpf.opc.
(HFILES): Add bpf-desc.h and bpf-opc.h.
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
bpf-ibld.c and bpf-opc.c.
(BPF_DEPS): Define.
* Makefile.in: Regenerated.
* disassemble.c (ARCH_bpf): Define.
(disassembler): Add case for bfd_arch_bpf.
(disassemble_init_for_target): Likewise.
(enum epbf_isa_attr): Define.
* disassemble.h: extern print_insn_bpf.
* bpf-asm.c: Generated.
* bpf-opc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-ibld.c: Likewise.
* bpf-dis.c: Likewise.
* bpf-desc.h: Likewise.
* bpf-desc.c: Likewise.
This patch makes changes to the <spec_reg> operand for VMRS and VMSR
instructions as per the Armv8.1-M Mainline.
New <spec_reg> options to support are:
0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags.
0b1100: VPR, privileged only access to the VPR register.
0b1101: P0, access to VPR.P0 predicate fields
0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating
point context.
0b1111: FPCXT_S, enables saving and restoring of Secure floating point
context
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
The MIPS64R6 TRM requires that the source register for DAUI
not be r0.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 67-68.
gas/
* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.s: this and add test
case for DAUI.
* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.l: this and add test
for DAUI.
* testsuite/gas/mips/mips.exp: Rename test from
r6-branch-constraints to r6-reg-constraints.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Change source register
constraint for DAUI.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(print_insn_thumb32): Handle new instructions.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_unpredictable): Likewise.
(mve_opcodes): Add new instructions.
(print_mve_unpredictable): Handle new reasons.
(print_mve_register_blocks): New print function.
(print_mve_size): Handle new instructions.
(print_insn_mve): Likewise.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new values.
(mve_opcodes): Add new instructions.
(vec_condnames): New array with vector conditions.
(mve_predicatenames): New array with predicate suffixes.
(mve_vec_sizename): New array with vector sizes.
(enum vpt_pred_state): New enum with vector predication states.
(struct vpt_block): New struct type for vpt blocks.
(vpt_block_state): Global struct to keep track of state.
(mve_extract_pred_mask): New helper function.
(num_instructions_vpt_block): Likewise.
(mark_outside_vpt_block): Likewise.
(mark_inside_vpt_block): Likewise.
(invert_next_predicate_state): Likewise.
(update_next_predicate_state): Likewise.
(update_vpt_block_state): Likewise.
(is_vpt_instruction): Likewise.
(is_mve_encoding_conflict): Add entries for new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_unpredictable): Handle new cases.
(print_instruction_predicate): Likewise.
(print_mve_size): New function.
(print_vec_condition): New function.
(print_insn_mve): Handle vpt blocks and new print operands.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
8, 14 and 15 for Armv8.1-M Mainline.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
opcodes/
* ppc-dis.c (skip_optional_operands): Change return type and returns.
(print_insn_powerpc) <skip_optional>: Change type.
Call skip_optional_operands if we have not skipped any operands.
gas/
* testsuite/gas/ppc/476.d: Update expected output.
* testsuite/gas/ppc/power6.d: Likewise.
This patch adds all the SVE2 instructions and their associated qualifier
sets.
Ok for trunk?
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
(OP_SVE_BBB): New variant set.
(OP_SVE_DDDD): New variant set.
(OP_SVE_HHH): New variant set.
(OP_SVE_HHHU): New variant set.
(OP_SVE_SSS): New variant set.
(OP_SVE_SSSU): New variant set.
(OP_SVE_SHH): New variant set.
(OP_SVE_SBBU): New variant set.
(OP_SVE_DSS): New variant set.
(OP_SVE_DHHU): New variant set.
(OP_SVE_VMV_HSD_BHS): New variant set.
(OP_SVE_VVU_HSD_BHS): New variant set.
(OP_SVE_VVVU_SD_BH): New variant set.
(OP_SVE_VVVU_BHSD): New variant set.
(OP_SVE_VVV_QHD_DBS): New variant set.
(OP_SVE_VVV_HSD_BHS): New variant set.
(OP_SVE_VVV_HSD_BHS2): New variant set.
(OP_SVE_VVV_BHS_HSD): New variant set.
(OP_SVE_VV_BHS_HSD): New variant set.
(OP_SVE_VVV_SD): New variant set.
(OP_SVE_VVU_BHS_HSD): New variant set.
(OP_SVE_VZVV_SD): New variant set.
(OP_SVE_VZVV_BH): New variant set.
(OP_SVE_VZV_SD): New variant set.
(aarch64_opcode_table): Add sve2 instructions.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Add sve_size_013 instruction class
This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_013 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_013 iclass decode.
Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_bh iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_bh iclass decode.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
SVE2 introduces a number of new instructions that work with the movprfx
instruction. This commit ensures that SVE2 instructions are accounted
for.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
instructions.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order
*** gas/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_features): Add "tme".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/tme-invalid.d: New test.
* testsuite/gas/aarch64/tme-invalid.l: New test.
* testsuite/gas/aarch64/tme-invalid.s: New test.
* testsuite/gas/aarch64/tme.d: New test.
* testsuite/gas/aarch64/tme.s: New test.
*** include/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
*** opcodes/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_IMM_NIL): New.
(TME): New.
(_TME_INSN): New.
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message.
The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests.
It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction.
Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
The coprocessor_opcodes table is used both to share commonalities in coprocessor-related instructions and to avoid duplication between Arm and Thumb mode. However, some instructions do have differences between Arm and Thumb. For instance, vldmia allows PC as base register in Arm mode but not in Thumb mode.
In that very case the distinction becomes necessary because the encoding with PC as base register is used in Thumb mode to denote a VSCCLRM. It is thus necessary to distinguish what is Arm or Thumb only from what is shared. This patch adds an extra field to the coprocessor_opcodes table entries to indicate what mode is a given instruction available in. The print_insn_coprocessor then uses that field to determine if an entry that matched the mark and value checked should be allowed to match or not given the current mode.
ChangeLog entry is as follows:
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (enum isa): New enum.
(struct sopcode32): New structure.
(coprocessor_opcodes): change type of entries to struct sopcode32 and
set isa field of all current entries to ANY.
(print_insn_coprocessor): Change type of insn to struct sopcode32.
Only match an entry if its isa field allows the current mode.
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions.
In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators.
parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand.
Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function.
Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BFL instruction.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfl.s: New.
* testsuite/ld-arm/bfl.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BF instruction.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.
This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
1. Use single entry for vcvtne2ps2bf16 and vdpbf16ps with Disp8ShiftVL.
2. Use 5 entries, instead of 8, for vcvtneps2bf16.
* i386-opc.tbl: Consolidate AVX512 BF16 entries.
* i386-init.h: Regenerated.
* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
op_separator to control printing of spaces, comma and parens
rather than need_comma, need_paren and spaces vars.
This patch fixes a problem with disassembly of branch instructions
for processors complying with PowerPC ISA versions prior to version
2.0, ie. those that use "y" bit branch taken hints. Many of the
extended bcctr and bclr mnemonics that should have disassembled with a
"-" suffix, ie. not taken, did not display the "-" due to the ordering
in powerpc_opcodes. I believe it's been that way from the original
85dcf36d72 commit of ppc-opc.c.
I've also added a BH field (optional) to a few opcodes. This gives
better disassembly in raw mode, showing the branch taken hint in the
mnemonic as is done for bc. It would be reasonable to add a BH
field to all bcctr, bclr, and bctar extended mnemonics but that runs
into a small difficulty: Currently we print all or none of the
optional operands. That means for example that "bgectr cr2" would
display as "bgectr cr2,0" if a BH field is added to bgectr.
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
to favour printing of "-" branch hint when using the "y" bit.
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
When an instruction has operands, the PowerPC disassembler prints
spaces after the opcode so as to line up operands. If the operands
are all optional and all default value, then no operands are printed,
leaving trailing spaces. This patch fixes that.
opcodes/
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
opcode until first operand is output.
gas/
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
ld/
* testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
* testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Similar to the AArch64 patches the Arm disassembler has the same issues with
out of order sections but also a few short comings.
For one thing there are multiple code blocks to determine mapping symbols, and
they all work slightly different, and neither fully correct. The first thing
this patch does is centralise the mapping symbols search into one function
mapping_symbol_for_insn. This function is then updated to perform a search in
a similar way as AArch64.
Their used to be a value has_mapping_symbols which was used to determine the
default disassembly for objects that have no mapping symbols. The problem with
the approach was that it was determining this value in the same loop that needed
it, which is why this field could take on the states -1, 0, 1 where -1 means
"don't know". However this means that until you actually find a mapping symbol
or reach the end of the disassembly glob, you don't know if you did the right
action or not, and if you didn't you can't correct it anymore.
This is why the two jump-reloc-veneers-* testcases end up disassembling some
insn as data when they shouldn't.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for Arm [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix
this we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section
than we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7
binutils/ChangeLog:
* testsuite/binutils-all/arm/in-order-all.d: New test.
* testsuite/binutils-all/arm/in-order.d: New test.
* testsuite/binutils-all/arm/objdump.exp: Support .d tests.
* testsuite/binutils-all/arm/out-of-order-all.d: New test.
* testsuite/binutils-all/arm/out-of-order.T: New test.
* testsuite/binutils-all/arm/out-of-order.d: New test.
* testsuite/binutils-all/arm/out-of-order.s: New test.
ld/ChangeLog:
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly.
* testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly.
opcodes/ChangeLog:
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
(mapping_symbol_for_insn): Implement new algorithm.
(print_insn): Remove duplicate code.
The documentation for -D says that on Arm platforms -D should disassemble
data as instructions.
"If the target is an ARM architecture this switch also has the effect of
forcing the disassembler to decode pieces of data found in code sections
as if they were instructions. "
This makes it do as it says on the tincan so it's more consistent with
aarch32. The usecase here is for baremetal developers who have created
their instructions using .word directives instead if .insn.
Though for Linux users I do find this behavior somewhat non-optimal.
Perhaps there should be a new flag that just disassembles the values
following the actual mapping symbol?
binutils/ChangeLog:
* testsuite/binutils-all/aarch64/in-order-all.d: New test.
* testsuite/binutils-all/aarch64/out-of-order-all.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.d:
opcodes/ChangeLog:
* aarch64-dis.c (print_insn_aarch64):
Implement override.
My previous patch for AArch64 was not enough to catch all the cases where
disassembling an out-of-order section could go wrong. It had missed the case
DATA sections could be incorrectly disassembled as TEXT.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for AArch64 [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix this
we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section than
we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4#aaelf64-section4-5-4
binutils/ChangeLog:
* testsuite/binutils-all/aarch64/in-order.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.d: Disassemble data as
well.
opcodes/ChangeLog:
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
order.
The AArch64 disassembler has an optimization that it uses to reduce the amount
it has to search for mapping symbols during disassembly. This optimization
assumes that sections are listed in the section header in monotonic increasing
VMAs. However this is not a requirement for the ELF specification.
Because of this when such "out of order" sections occur the disassembler would
pick the wrong mapping symbol to disassemble the section with.
This fixes it by explicitly passing along the stop offset for the current
disassembly glob and when this changes compared to the previous one we've seen
the optimization won't be performed. In effect this restarts the search from
a well defined starting point. Usually the symbol's address.
The existing stop_vma can't be used for this as it is allowed to be unset and
setting this unconditionally would change the semantics of this field.
binutils/ChangeLog:
* objdump.c (disassemble_bytes): Pass stop_offset.
* testsuite/binutils-all/aarch64/out-of-order.T: New test.
* testsuite/binutils-all/aarch64/out-of-order.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.s: New test.
include/ChangeLog:
* dis-asm.h (struct disassemble_info): Add stop_offset.
opcodes/ChangeLog:
* aarch64-dis.c (last_stop_offset): New.
(print_insn_aarch64): Use stop_offset.
Stafford Horne
Peter Bergner
H.J. Lu
Alan Hayward
Alan Modra
Jose E. Marchesi
Sudakshina Das
Faraz Shahbazker
Nick Clifton
Andre Vieira
Matthew Malcomson
John Darrington
Andrew Bennett
Robert Suchanek
Xuepeng Guo
Peter Bergner
Tamar Christina
Andreas Krebbel
Jim Wilson