2019-09-10 18:17:01 +02:00
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2019-09-10 Miod Vallat <miod@online.fr>
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PR 24982
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* m68k-opc.c: Correct aliases for tdivsl and tdivul.
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2019-09-09 11:27:03 +02:00
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2019-09-09 Phil Blundell <pb@pbcl.net>
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binutils 2.33 branch created.
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2019-09-03 16:37:12 +02:00
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2019-09-03 Nick Clifton <nickc@redhat.com>
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PR 24961
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* tic30-dis.c (get_indirect_operand): Check for bufcnt being
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greater than zero before indexing via (bufcnt -1).
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2019-09-03 10:53:25 +02:00
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2019-09-03 Nick Clifton <nickc@redhat.com>
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PR 24958
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* mmix-dis.c (MAX_REG_NAME_LEN): Define.
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(MAX_SPEC_REG_NAME_LEN): Define.
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(struct mmix_dis_info): Use defined constants for array lengths.
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(get_reg_name): New function.
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(get_sprec_reg_name): New function.
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(print_insn_mmix): Use new functions.
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2019-08-27 13:08:21 +02:00
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2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
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* arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
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(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
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(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
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[AArch64][gas] Update MTE system register encodings
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.
The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3
Tested check-gas for aarch64-none-elf.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
(aarch64_sys_reg_supported_p): Update checks for the above.
gas/
* testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-22 11:20:01 +02:00
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2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
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tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
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(aarch64_sys_reg_supported_p): Update checks for the above.
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2019-08-12 18:17:18 +02:00
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2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
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* arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
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cases MVE_SQRSHRL and MVE_UQRSHLL.
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(print_insn_mve): Add case for specifier 'k' to check
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specific bit of the instruction.
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2019-08-07 18:22:29 +02:00
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2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
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PR 24854
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* arc-dis.c (arc_insn_length): Return 0 rather than aborting when
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encountering an unknown machine type.
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(print_insn_arc): Handle arc_insn_length returning 0. In error
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cases return -1 rather than calling abort.
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2019-08-07 10:46:52 +02:00
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2019-08-07 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
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(fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
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IgnoreSize.
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* i386-tbl.h: Re-generate.
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2019-08-05 13:43:38 +02:00
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2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
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* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
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instructions.
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RISC-V: Fix minor issues with FP csr instructions.
Mel Chen <mel.chen@sifive.com>
gas/
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
alias instructions.
* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
-Mno-aliases.
* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
* testsuite/gas/riscv/priv-reg.d: Update.
opcodes/
* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
fscsr.
2019-07-30 23:42:16 +02:00
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2019-07-30 Mel Chen <mel.chen@sifive.com>
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* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
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fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
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* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
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fscsr.
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2019-07-24 15:52:23 +02:00
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2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
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and MPY class instructions.
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(parse_option): Add nps400 option.
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(print_arc_disassembler_options): Add nps400 info.
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2019-07-24 15:46:01 +02:00
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2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-ext-tbl.h (bspeek): Remove it, added to main table.
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(bspop): Likewise.
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(modapp): Likewise.
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* arc-opc.c (RAD_CHK): Add.
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* arc-tbl.h: Regenerate.
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2019-07-23 16:54:54 +02:00
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2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
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(aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
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2019-07-23 10:47:06 +02:00
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2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
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* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
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instructions as UNPREDICTABLE.
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2019-07-19 15:35:43 +02:00
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2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-desc.c: Regenerated.
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2019-07-17 09:15:49 +02:00
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2019-07-17 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (static_assert): Define.
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(main): Use it.
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* i386-opc.h (Opcode_Modifier_Max): Rename to ...
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(Opcode_Modifier_Num): ... this.
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(Mem): Delete.
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2019-07-16 09:31:36 +02:00
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2019-07-16 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_types): Move RegMem ...
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(opcode_modifiers): ... here.
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* i386-opc.h (RegMem): Move to opcode modifer enum.
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(union i386_operand_type): Move regmem field ...
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(struct i386_opcode_modifier): ... here.
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* i386-opc.tbl (RegMem): Define.
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(mov, movq): Move RegMem on segment, control, debug, and test
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register flavors.
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(pextrb): Move RegMem on register only flavors. Add IgnoreSize
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to non-SSE2AVX flavor.
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(extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
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Move RegMem on register only flavors. Drop IgnoreSize from
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legacy encoding flavors.
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(movss, movsd, vmovss, vmovsd): Drop RegMem from register only
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flavors.
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(vpinsrb, vpinsrw): Drop IgnoreSize where still present on
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register only flavors.
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(vmovd): Move RegMem and drop IgnoreSize on register only
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flavor. Change opcode and operand order to store form.
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* opcodes/i386-init.h, i386-tbl.h: Re-generate.
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2019-07-16 09:30:29 +02:00
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2019-07-16 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init, operand_types): Replace SReg
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entries.
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* i386-opc.h (SReg2, SReg3): Replace by ...
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(SReg): ... this.
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(union i386_operand_type): Replace sreg fields.
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* i386-opc.tbl (mov, ): Use SReg.
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(push, pop): Likewies. Drop i386 and x86-64 specific segment
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register flavors.
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* i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
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* opcodes/i386-init.h, i386-tbl.h: Re-generate.
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2019-07-15 16:00:28 +02:00
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2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-desc.c: Regenerate.
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* bpf-opc.c: Likewise.
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* bpf-opc.h: Likewise.
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cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument. Instead, they put the loaded value in %r0, implicitly.
This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.
Tested in a x86-64 host.
cpu/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
explicit 'dst' argument.
opcodes/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
gas/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
ldabs and ldind instructions.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 14:45:31 +02:00
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2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-desc.c: Regenerate.
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* bpf-opc.c: Likewise.
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2019-07-10 18:38:19 +02:00
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2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
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* arm-dis.c (print_insn_coprocessor): Rename index to
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index_operand.
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2019-07-05 09:19:11 +02:00
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2019-07-05 Kito Cheng <kito.cheng@sifive.com>
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* riscv-opc.c (riscv_insn_types): Add r4 type.
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* riscv-opc.c (riscv_insn_types): Add b and j type.
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* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
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format for sb type and correct s type.
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2019-07-02 11:52:16 +02:00
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2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
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SVE FMOV alias of FCPY.
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[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02 11:51:09 +02:00
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2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
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to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
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2019-07-02 11:51:05 +02:00
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2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
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registers in an instruction prefixed by MOVPRFX.
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[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.
Only the variant specifying .Q -> .D sizes should have that
restriction.
This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).
We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size. This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.
Regtested targeting aarch64-linux.
gas/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
include/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
renamed to sve_size_13.
opcodes/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
2019-07-01 16:17:22 +02:00
|
|
|
|
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
|
|
|
|
|
|
sve_size_13 icode to account for variant behaviour of
|
|
|
|
|
|
pmull{t,b}.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
|
|
|
|
|
|
sve_size_13 icode to account for variant behaviour of
|
|
|
|
|
|
pmull{t,b}.
|
|
|
|
|
|
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
|
|
|
|
|
|
(OP_SVE_VVV_Q_D): Add new qualifier.
|
|
|
|
|
|
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
|
|
|
|
|
|
(struct aarch64_opcode): Split pmull{t,b} into those requiring
|
|
|
|
|
|
AES and those not.
|
|
|
|
|
|
|
2019-07-01 08:38:50 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/i386-gen.c (operand_type_init): Remove
|
|
|
|
|
|
OPERAND_TYPE_VEC_IMM4 entry.
|
|
|
|
|
|
(operand_types): Remove Vec_Imm4.
|
|
|
|
|
|
* opcodes/i386-opc.h (Vec_Imm4): Delete.
|
|
|
|
|
|
(union i386_operand_type): Remove vec_imm4.
|
|
|
|
|
|
* i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
|
|
|
|
|
|
* opcodes/i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:37:40 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
|
|
|
|
|
|
vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
|
|
|
|
|
|
rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
|
|
|
|
|
|
vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
|
|
|
|
|
|
xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
|
|
|
|
|
|
monitorx, mwaitx): Drop ImmExt from operand-less forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:35:08 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
|
|
|
|
|
|
register operands.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:33:56 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (C): New.
|
|
|
|
|
|
(paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
|
|
|
|
|
|
pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
|
|
|
|
|
|
por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
|
|
|
|
|
|
cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
|
|
|
|
|
|
pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
|
|
|
|
|
|
cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
|
|
|
|
|
|
cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
|
|
|
|
|
|
vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
|
|
|
|
|
|
vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
|
|
|
|
|
|
vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
|
|
|
|
|
|
vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
|
|
|
|
|
|
vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
|
|
|
|
|
|
vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
|
|
|
|
|
|
vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
|
|
|
|
|
|
vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
|
|
|
|
|
|
vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
|
|
|
|
|
|
vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
|
|
|
|
|
|
vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
|
|
|
|
|
|
vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
|
|
|
|
|
|
vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
|
|
|
|
|
|
vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
|
|
|
|
|
|
vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
|
|
|
|
|
|
vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
|
|
|
|
|
|
vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
|
|
|
|
|
|
vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
|
|
|
|
|
|
vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
|
|
|
|
|
|
flavors.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:31:14 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
|
|
|
|
|
|
register operands.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:28:58 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
|
|
|
|
|
|
* i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
|
|
|
|
|
|
vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:27:38 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
|
|
|
|
|
|
Disp8MemShift from register only templates.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-07-01 08:23:41 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
|
|
|
|
|
|
MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
|
|
|
|
|
|
MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
|
|
|
|
|
|
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
|
|
|
|
|
|
EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
|
|
|
|
|
|
EVEX_W_0F11_P_3_M_1): Delete.
|
|
|
|
|
|
(EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
|
|
|
|
|
|
EVEX_W_0F11_P_3): New.
|
|
|
|
|
|
* i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
|
|
|
|
|
|
MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
|
|
|
|
|
|
MOD_EVEX_0F11_PREFIX_3 table entries.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
|
|
|
|
|
|
PREFIX_EVEX_0F11 table entries.
|
|
|
|
|
|
* i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
|
|
|
|
|
|
EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
|
|
|
|
|
|
EVEX_W_0F11_P_3_M_{0,1} table entries.
|
|
|
|
|
|
|
2019-07-01 08:22:37 +02:00
|
|
|
|
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
|
|
|
|
|
|
Delete.
|
|
|
|
|
|
|
i386: Check vector length for scatter/gather prefetch instructions
Since not all vector lengths are supported by scatter/gather prefetch
instructions, decode them only with supported vector lengths.
gas/
PR binutils/24719
* testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps
with invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24719
* i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
EVEX_LEN_0F38C7_R_6_P_2_W_1.
* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
PREFIX_EVEX_0F38C6_REG_6 entries.
* i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
EVEX_W_0F38C7_R_6_P_2 entries.
* i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-27 22:39:19 +02:00
|
|
|
|
2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24719
|
|
|
|
|
|
* i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
|
|
|
|
|
|
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
|
|
|
|
|
|
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_6_P_2_W_1.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
|
|
|
|
|
|
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
|
|
|
|
|
|
PREFIX_EVEX_0F38C6_REG_6 entries.
|
|
|
|
|
|
* i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
|
|
|
|
|
|
EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
|
|
|
|
|
|
EVEX_W_0F38C7_R_6_P_2 entries.
|
|
|
|
|
|
* i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
|
|
|
|
|
|
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
|
|
|
|
|
|
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
|
|
|
|
|
|
EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
|
|
|
|
|
|
|
2019-06-27 08:50:28 +02:00
|
|
|
|
2019-06-27 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
|
|
|
|
|
|
VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
|
|
|
|
|
|
VEX_LEN_0F2D_P_3): Delete.
|
|
|
|
|
|
(vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
|
|
|
|
|
|
vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
|
|
|
|
|
|
(prefix_table): ... here.
|
|
|
|
|
|
|
2019-06-27 08:49:40 +02:00
|
|
|
|
2019-06-27 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Iq): Delete.
|
|
|
|
|
|
(Id): New.
|
|
|
|
|
|
(reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
|
|
|
|
|
|
TBM insns.
|
|
|
|
|
|
(vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
|
|
|
|
|
|
vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
|
|
|
|
|
|
(OP_E_memory): Also honor needindex when deciding whether an
|
|
|
|
|
|
address size prefix needs printing.
|
|
|
|
|
|
(OP_I): Remove handling of q_mode. Add handling of d_mode.
|
|
|
|
|
|
|
2019-06-27 02:17:09 +02:00
|
|
|
|
2019-06-26 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24739
|
|
|
|
|
|
* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
|
|
|
|
|
|
Set info->display_endian to info->endian_code.
|
|
|
|
|
|
|
2019-06-25 09:41:33 +02:00
|
|
|
|
2019-06-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
|
|
|
|
|
|
entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
|
|
|
|
|
|
OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
|
|
|
|
|
|
OPERAND_TYPE_ACC64 entries.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2019-06-25 09:28:33 +02:00
|
|
|
|
2019-06-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
|
|
|
|
|
|
Delete.
|
|
|
|
|
|
(intel_operand_size, OP_E_register, OP_E_memory): Drop handling
|
|
|
|
|
|
of dqa_mode.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
|
|
|
|
|
|
entries here.
|
|
|
|
|
|
* i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
|
|
|
|
|
|
entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
|
|
|
|
|
|
|
2019-06-25 09:27:05 +02:00
|
|
|
|
2019-06-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
|
|
|
|
|
|
variables.
|
|
|
|
|
|
|
2019-06-25 09:25:26 +02:00
|
|
|
|
2019-06-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
|
|
|
|
|
|
Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
|
|
|
|
|
|
movnti.
|
2019-06-27 02:17:09 +02:00
|
|
|
|
* i386-opc.tbl (movnti): Add IgnoreSize.
|
2019-06-25 09:25:26 +02:00
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-06-25 09:23:48 +02:00
|
|
|
|
2019-06-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (and): Mark Imm8S form for optimization.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2019-06-21 22:18:41 +02:00
|
|
|
|
2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis-evex.h: Break into ...
|
|
|
|
|
|
* i386-dis-evex-len.h: New file.
|
|
|
|
|
|
* i386-dis-evex-mod.h: Likewise.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Likewise.
|
|
|
|
|
|
* i386-dis-evex-reg.h: Likewise.
|
|
|
|
|
|
* i386-dis-evex-w.h: Likewise.
|
|
|
|
|
|
* i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
|
|
|
|
|
|
i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
|
|
|
|
|
|
i386-dis-evex-mod.h.
|
|
|
|
|
|
|
i386: Check vector length for EVEX broadcast instructions
Since not all vector lengths are supported by EVEX broadcast instructions,
decode them only with supported vector lengths.
gas/
PR binutils/24700
* testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8
with invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24700
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
EVEX_W_0F385B_P_2.
(evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
EVEX_LEN_0F385B_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
(EVEX_LEN_0F3819_P_2_W_1): Likewise.
(EVEX_LEN_0F381A_P_2_W_0): Likewise.
(EVEX_LEN_0F381A_P_2_W_1): Likewise.
(EVEX_LEN_0F381B_P_2_W_0): Likewise.
(EVEX_LEN_0F381B_P_2_W_1): Likewise.
(EVEX_LEN_0F385A_P_2_W_0): Likewise.
(EVEX_LEN_0F385A_P_2_W_1): Likewise.
(EVEX_LEN_0F385B_P_2_W_0): Likewise.
(EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-19 19:01:27 +02:00
|
|
|
|
2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24700
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
|
|
|
|
|
|
EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
|
|
|
|
|
|
EVEX_W_0F385B_P_2.
|
|
|
|
|
|
(evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
|
|
|
|
|
|
EVEX_LEN_0F385B_P_2_W_1.
|
|
|
|
|
|
* i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
|
|
|
|
|
|
(EVEX_LEN_0F3819_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F381A_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F381A_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F381B_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F381B_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F385A_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F385A_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F385B_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F385B_P_2_W_1): Likewise.
|
|
|
|
|
|
|
i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX
Since not all vector lengths are supported by vshufXXX, vinsertXXX and
vextractXXX, decode them only with supported vector lengths.
gas/
PR binutils/24691
* testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with
invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24691
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
(evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
EVEX_LEN_0F3A43_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
(EVEX_LEN_0F3A23_P_2_W_1): Likewise.
(EVEX_LEN_0F3A38_P_2_W_0): Likewise.
(EVEX_LEN_0F3A38_P_2_W_1): Likewise.
(EVEX_LEN_0F3A39_P_2_W_0): Likewise.
(EVEX_LEN_0F3A39_P_2_W_1): Likewise.
(EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
(EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
(EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
(EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
(EVEX_LEN_0F3A43_P_2_W_0): Likewise.
(EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-17 19:20:04 +02:00
|
|
|
|
2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24691
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
|
|
|
|
|
|
EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
|
|
|
|
|
|
EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
|
|
|
|
|
|
(evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
|
|
|
|
|
|
EVEX_LEN_0F3A43_P_2_W_1.
|
|
|
|
|
|
* i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
|
|
|
|
|
|
(EVEX_LEN_0F3A23_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A38_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A38_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A39_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A39_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A43_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A43_P_2_W_1): Likewise.
|
|
|
|
|
|
|
2019-06-14 12:43:53 +02:00
|
|
|
|
2019-06-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po; Updated French translation.
|
|
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
|
2019-06-13 Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* or1k-asm.c: Regenerated.
|
|
|
|
|
|
* or1k-desc.c: Regenerated.
|
|
|
|
|
|
* or1k-desc.h: Regenerated.
|
|
|
|
|
|
* or1k-dis.c: Regenerated.
|
|
|
|
|
|
* or1k-ibld.c: Regenerated.
|
|
|
|
|
|
* or1k-opc.c: Regenerated.
|
|
|
|
|
|
* or1k-opc.h: Regenerated.
|
|
|
|
|
|
* or1k-opinst.c: Regenerated.
|
|
|
|
|
|
|
2019-06-12 22:51:01 +02:00
|
|
|
|
2019-06-12 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
|
|
|
|
|
|
|
i386: Check vector length for EVEX vextractfXX and vinsertfXX
Since not all vector lengths are supported by EVEX vextractfXX and
vinsertfXX, decode them only with supported vector lengths.
gas/
PR binutils/24633
* testsuite/gas/i386/disassem.s: Add tests for invalid vector
lengths for EVEX vextractfXX and vinsertfXX.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24633
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
(evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
EVEX_LEN_0F3A1B_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
(EVEX_LEN_0F3A18_P_2_W_1): Likewise.
(EVEX_LEN_0F3A19_P_2_W_0): Likewise.
(EVEX_LEN_0F3A19_P_2_W_1): Likewise.
(EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
(EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
(EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
(EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-05 19:27:08 +02:00
|
|
|
|
2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24633
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
|
|
|
|
|
|
EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
|
|
|
|
|
|
(evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
|
|
|
|
|
|
EVEX_LEN_0F3A1B_P_2_W_1.
|
|
|
|
|
|
* i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
|
|
|
|
|
|
(EVEX_LEN_0F3A18_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A19_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A19_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
|
|
|
|
|
|
(EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
|
|
|
|
|
|
|
2019-06-04 21:45:20 +02:00
|
|
|
|
2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/24626
|
|
|
|
|
|
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
|
|
|
|
|
|
EVEX.vvvv when disassembling VEX and EVEX instructions.
|
|
|
|
|
|
(OP_VEX): Set vex.register_specifier to 0 after readding
|
|
|
|
|
|
vex.register_specifier.
|
|
|
|
|
|
(OP_Vex_2src_1): Likewise.
|
|
|
|
|
|
(OP_Vex_2src_2): Likewise.
|
|
|
|
|
|
(OP_LWP_E): Likewise.
|
|
|
|
|
|
(OP_EX_Vex): Don't check vex.register_specifier.
|
|
|
|
|
|
(OP_XMM_Vex): Likewise.
|
|
|
|
|
|
|
2019-06-04 17:58:21 +02:00
|
|
|
|
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuAVX512_VP2INTERSECT.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx512_vp2intersect.
|
|
|
|
|
|
* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2019-06-04 17:50:10 +02:00
|
|
|
|
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
|
|
|
|
|
|
Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi: Document enqcmd.
|
|
|
|
|
|
* testsuite/gas/i386/enqcmd-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/enqcmd.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/enqcmd.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
|
|
|
|
|
|
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
|
|
|
|
|
|
and x86-64-enqcmd.
|
|
|
|
|
|
|
2019-06-04 15:25:08 +02:00
|
|
|
|
2019-06-04 Alan Hayward <alan.hayward@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
|
|
|
|
|
|
|
2019-06-03 04:16:04 +02:00
|
|
|
|
2019-06-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (prefix_opcd_indices): Correct size.
|
|
|
|
|
|
|
2019-05-28 19:05:28 +02:00
|
|
|
|
2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24625
|
|
|
|
|
|
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
|
|
|
|
|
|
Disp8ShiftVL.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2019-05-24 15:39:56 +02:00
|
|
|
|
2019-05-24 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
PowerPC D-form prefixed loads and stores
opcodes/
* ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
(insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
(extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
(powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
XTOP>): Define and add entries.
(P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
(prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
gas/
* config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that
are 32-bits or smaller.
* messages.c (as_internal_value_out_of_range): Do not truncate
variables and use BFD_VMA_FMT to print them.
* testsuite/gas/ppc/prefix-pcrel.s,
* testsuite/gas/ppc/prefix-pcrel.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2018-07-28 05:21:43 +02:00
|
|
|
|
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
|
|
|
|
|
|
(insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
|
|
|
|
|
|
(extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
|
|
|
|
|
|
(powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
|
|
|
|
|
|
XTOP>): Define and add entries.
|
|
|
|
|
|
(P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
|
|
|
|
|
|
(prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
|
|
|
|
|
|
pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
|
|
|
|
|
|
plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
|
|
|
|
|
|
|
PowerPC add initial -mfuture instruction support
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
2018-05-15 23:48:14 +02:00
|
|
|
|
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "future" entry.
|
|
|
|
|
|
(PREFIX_OPCD_SEGS): Define.
|
|
|
|
|
|
(prefix_opcd_indices): New array.
|
|
|
|
|
|
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
|
|
|
|
|
|
(lookup_prefix): New function.
|
|
|
|
|
|
(print_insn_powerpc): Handle 64-bit prefix instructions.
|
|
|
|
|
|
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
|
|
|
|
|
|
(PMRR, POWERXX): Define.
|
|
|
|
|
|
(prefix_opcodes): New instruction table.
|
|
|
|
|
|
(prefix_num_opcodes): New constant.
|
|
|
|
|
|
|
2019-05-23 19:04:36 +02:00
|
|
|
|
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
|
|
|
|
|
|
and cpu/bpf.opc.
|
|
|
|
|
|
(HFILES): Add bpf-desc.h and bpf-opc.h.
|
|
|
|
|
|
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
|
|
|
|
|
|
bpf-ibld.c and bpf-opc.c.
|
|
|
|
|
|
(BPF_DEPS): Define.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* disassemble.c (ARCH_bpf): Define.
|
|
|
|
|
|
(disassembler): Add case for bfd_arch_bpf.
|
|
|
|
|
|
(disassemble_init_for_target): Likewise.
|
|
|
|
|
|
(enum epbf_isa_attr): Define.
|
|
|
|
|
|
* disassemble.h: extern print_insn_bpf.
|
|
|
|
|
|
* bpf-asm.c: Generated.
|
|
|
|
|
|
* bpf-opc.h: Likewise.
|
|
|
|
|
|
* bpf-opc.c: Likewise.
|
|
|
|
|
|
* bpf-ibld.c: Likewise.
|
|
|
|
|
|
* bpf-dis.c: Likewise.
|
|
|
|
|
|
* bpf-desc.h: Likewise.
|
|
|
|
|
|
* bpf-desc.c: Likewise.
|
|
|
|
|
|
|
2019-05-21 19:20:48 +02:00
|
|
|
|
2019-05-21 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
|
|
|
|
|
|
and VMSR with the new operands.
|
|
|
|
|
|
|
[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline
This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
2019-05-21 19:15:13 +02:00
|
|
|
|
2019-05-21 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): New enum
|
|
|
|
|
|
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
|
|
|
|
|
|
and cneg.
|
|
|
|
|
|
(mve_opcodes): New instructions as above.
|
|
|
|
|
|
(is_mve_encoding_conflict): Add cases for csinc, csinv,
|
|
|
|
|
|
csneg and csel.
|
|
|
|
|
|
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
|
|
|
|
|
|
|
[binutils, Arm] Add support for shift instructions in MVE
This patch adds the following instructions which are part of
Armv8.1-M MVE:
ASRL (imm)
ASRL (reg)
LSLL (imm)
LSLL (reg)
LSRL
SQRSHRL
SRQSHR
SQSHLL
SQSHL
SRSHRL
SRSHR
UQRSHLL
UQRSHL
UQSHLL
UQSHL
URSHLL
URSHL
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): New entries for
OP_RRnpcsp_I32 (register or integer operands).
(do_mve_scalar_shift): New.
(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
* testsuite/gas/arm/mve-shift.d: New.
* testsuite/gas/arm/mve-shift.s: New.
* testsuite/gas/arm/mve-shift-bad.d: New.
* testsuite/gas/arm/mve-shift-bad.s: New.
* testsuite/gas/arm/mve-shift-bad.l: New.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (emun mve_instructions): Updated for new instructions.
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
uqshl, urshrl and urshr.
(is_mve_okay_in_it): Add new instructions to TRUE list.
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
(print_insn_mve): Updated to accept new %j,
%<bitfield>m and %<bitfield>n patterns.
2019-05-21 19:11:08 +02:00
|
|
|
|
2019-05-21 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (emun mve_instructions): Updated for new instructions.
|
|
|
|
|
|
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
|
|
|
|
|
|
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
|
|
|
|
|
|
uqshl, urshrl and urshr.
|
|
|
|
|
|
(is_mve_okay_in_it): Add new instructions to TRUE list.
|
|
|
|
|
|
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
|
|
|
|
|
|
(print_insn_mve): Updated to accept new %j,
|
|
|
|
|
|
%<bitfield>m and %<bitfield>n patterns.
|
|
|
|
|
|
|
2019-05-14 02:19:37 +02:00
|
|
|
|
2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Change source register
|
|
|
|
|
|
constraint for DAUI.
|
|
|
|
|
|
|
2019-05-20 17:18:19 +02:00
|
|
|
|
2019-05-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po: Updated French translation.
|
|
|
|
|
|
|
2019-05-16 15:48:34 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(enum mve_instructions): Likewise.
|
|
|
|
|
|
(enum mve_undefined): Add new reasons.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:47:12 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(enum mve_instructions): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:45:17 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(enum mve_instructions): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:44:19 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(enum mve_instructions): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:42:53 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(enum mve_instructions): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:41:41 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
|
|
|
|
|
(print_insn_thumb32): Handle new instructions.
|
|
|
|
|
|
|
2019-05-16 15:39:12 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_undefined): Add new reasons.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_mve_shift_n): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:34:44 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_rotate): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:33:36 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
[PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_undefined): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
2019-05-16 15:32:01 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_undefined): Add new reasons.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:30:38 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:29:36 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new reasons.
|
|
|
|
|
|
(enum mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_okay_in_it): Handle new isntructions.
|
|
|
|
|
|
(is_mve_encoding_conflict): Likewise.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_vmov_index): Likewise.
|
|
|
|
|
|
(print_simd_imm8): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:08:17 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new reasons.
|
|
|
|
|
|
(enum mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_rounding_mode): Likewise.
|
|
|
|
|
|
(print_mve_vcvt_size): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:06:46 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new reasons.
|
|
|
|
|
|
(enum mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_undefined): Handle new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:05:38 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_undefined): Add new reasons.
|
|
|
|
|
|
(insns): Add new instructions.
|
|
|
|
|
|
(is_mve_encoding_conflict):
|
|
|
|
|
|
(print_mve_vld_str_addr): New print function.
|
|
|
|
|
|
(is_mve_undefined): Handle new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_size): Likewise.
|
|
|
|
|
|
(print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
|
|
|
|
|
|
(print_insn_mve): Handle new operands.
|
|
|
|
|
|
|
2019-05-16 15:04:35 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new reasons.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(mve_opcodes): Add new instructions.
|
|
|
|
|
|
(print_mve_unpredictable): Handle new reasons.
|
|
|
|
|
|
(print_mve_register_blocks): New print function.
|
|
|
|
|
|
(print_mve_size): Handle new instructions.
|
|
|
|
|
|
(print_insn_mve): Likewise.
|
|
|
|
|
|
|
2019-05-16 15:02:05 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new reasons.
|
|
|
|
|
|
(enum mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Handle new instructions.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(coprocessor_opcodes): Move NEON VDUP from here...
|
|
|
|
|
|
(neon_opcodes): ... to here.
|
|
|
|
|
|
(mve_opcodes): Add new instructions.
|
|
|
|
|
|
(print_mve_undefined): Handle new reasons.
|
|
|
|
|
|
(print_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_size): Handle new instructions.
|
|
|
|
|
|
(print_insn_neon): Handle vdup.
|
|
|
|
|
|
(print_insn_mve): Handle new operands.
|
|
|
|
|
|
|
2019-05-16 14:57:57 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): Add new instructions.
|
|
|
|
|
|
(enum mve_unpredictable): Add new values.
|
|
|
|
|
|
(mve_opcodes): Add new instructions.
|
|
|
|
|
|
(vec_condnames): New array with vector conditions.
|
|
|
|
|
|
(mve_predicatenames): New array with predicate suffixes.
|
|
|
|
|
|
(mve_vec_sizename): New array with vector sizes.
|
|
|
|
|
|
(enum vpt_pred_state): New enum with vector predication states.
|
|
|
|
|
|
(struct vpt_block): New struct type for vpt blocks.
|
|
|
|
|
|
(vpt_block_state): Global struct to keep track of state.
|
|
|
|
|
|
(mve_extract_pred_mask): New helper function.
|
|
|
|
|
|
(num_instructions_vpt_block): Likewise.
|
|
|
|
|
|
(mark_outside_vpt_block): Likewise.
|
|
|
|
|
|
(mark_inside_vpt_block): Likewise.
|
|
|
|
|
|
(invert_next_predicate_state): Likewise.
|
|
|
|
|
|
(update_next_predicate_state): Likewise.
|
|
|
|
|
|
(update_vpt_block_state): Likewise.
|
|
|
|
|
|
(is_vpt_instruction): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Add entries for new instructions.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_unpredictable): Handle new cases.
|
|
|
|
|
|
(print_instruction_predicate): Likewise.
|
|
|
|
|
|
(print_mve_size): New function.
|
|
|
|
|
|
(print_vec_condition): New function.
|
|
|
|
|
|
(print_insn_mve): Handle vpt blocks and new print operands.
|
|
|
|
|
|
|
2019-05-16 14:55:20 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
|
|
|
|
|
|
8, 14 and 15 for Armv8.1-M Mainline.
|
|
|
|
|
|
|
2019-05-16 14:54:24 +02:00
|
|
|
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
Michael Collison <michael.collison@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (enum mve_instructions): New enum.
|
|
|
|
|
|
(enum mve_unpredictable): Likewise.
|
|
|
|
|
|
(enum mve_undefined): Likewise.
|
|
|
|
|
|
(struct mopcode32): New struct.
|
|
|
|
|
|
(is_mve_okay_in_it): New function.
|
|
|
|
|
|
(is_mve_architecture): Likewise.
|
|
|
|
|
|
(arm_decode_field): Likewise.
|
|
|
|
|
|
(arm_decode_field_multiple): Likewise.
|
|
|
|
|
|
(is_mve_encoding_conflict): Likewise.
|
|
|
|
|
|
(is_mve_undefined): Likewise.
|
|
|
|
|
|
(is_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_mve_undefined): Likewise.
|
|
|
|
|
|
(print_mve_unpredictable): Likewise.
|
|
|
|
|
|
(print_insn_coprocessor_1): Use arm_decode_field_multiple.
|
|
|
|
|
|
(print_insn_mve): New function.
|
|
|
|
|
|
(print_insn_thumb32): Handle MVE architecture.
|
|
|
|
|
|
(select_arm_features): Force thumb for Armv8.1-m Mainline.
|
|
|
|
|
|
|
2019-05-10 17:57:31 +02:00
|
|
|
|
2019-05-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 24538
|
|
|
|
|
|
* ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
|
|
|
|
|
|
end of the table prematurely.
|
|
|
|
|
|
|
2019-05-06 18:29:20 +02:00
|
|
|
|
2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
|
|
|
|
|
|
macros for R6.
|
|
|
|
|
|
|
2019-05-11 02:12:00 +02:00
|
|
|
|
2019-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc) Don't skip optional operands
|
|
|
|
|
|
when -Mraw is in effect.
|
|
|
|
|
|
|
2019-05-09 11:29:28 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
|
|
|
|
|
|
(OP_SVE_BBB): New variant set.
|
|
|
|
|
|
(OP_SVE_DDDD): New variant set.
|
|
|
|
|
|
(OP_SVE_HHH): New variant set.
|
|
|
|
|
|
(OP_SVE_HHHU): New variant set.
|
|
|
|
|
|
(OP_SVE_SSS): New variant set.
|
|
|
|
|
|
(OP_SVE_SSSU): New variant set.
|
|
|
|
|
|
(OP_SVE_SHH): New variant set.
|
|
|
|
|
|
(OP_SVE_SBBU): New variant set.
|
|
|
|
|
|
(OP_SVE_DSS): New variant set.
|
|
|
|
|
|
(OP_SVE_DHHU): New variant set.
|
|
|
|
|
|
(OP_SVE_VMV_HSD_BHS): New variant set.
|
|
|
|
|
|
(OP_SVE_VVU_HSD_BHS): New variant set.
|
|
|
|
|
|
(OP_SVE_VVVU_SD_BH): New variant set.
|
|
|
|
|
|
(OP_SVE_VVVU_BHSD): New variant set.
|
|
|
|
|
|
(OP_SVE_VVV_QHD_DBS): New variant set.
|
|
|
|
|
|
(OP_SVE_VVV_HSD_BHS): New variant set.
|
|
|
|
|
|
(OP_SVE_VVV_HSD_BHS2): New variant set.
|
|
|
|
|
|
(OP_SVE_VVV_BHS_HSD): New variant set.
|
|
|
|
|
|
(OP_SVE_VV_BHS_HSD): New variant set.
|
|
|
|
|
|
(OP_SVE_VVV_SD): New variant set.
|
|
|
|
|
|
(OP_SVE_VVU_BHS_HSD): New variant set.
|
|
|
|
|
|
(OP_SVE_VZVV_SD): New variant set.
|
|
|
|
|
|
(OP_SVE_VZVV_BH): New variant set.
|
|
|
|
|
|
(OP_SVE_VZV_SD): New variant set.
|
|
|
|
|
|
(aarch64_opcode_table): Add sve2 instructions.
|
|
|
|
|
|
|
2019-05-09 11:29:27 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_SHLIMM_UNPRED_22.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
|
|
|
|
|
|
operand.
|
|
|
|
|
|
|
2019-05-09 11:29:26 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_tsz_bhs iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_tsz_bhs iclass decode.
|
|
|
|
|
|
|
2019-05-09 11:29:24 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_Zm4_11_INDEX.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
|
|
|
|
|
|
(fields): Handle SVE_i2h field.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
|
|
|
|
|
|
|
2019-05-09 11:29:23 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_shift_tsz_bhsd iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_shift_tsz_bhsd iclass decode.
|
|
|
|
|
|
|
2019-05-09 11:29:22 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_sve_shrimm):
|
|
|
|
|
|
(aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_shift_tsz_hsd iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_shift_tsz_hsd iclass decode.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_SHRIMM_UNPRED_22.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
|
|
|
|
|
|
operand.
|
|
|
|
|
|
|
2019-05-09 11:29:21 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_013 iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_013 iclass decode.
|
|
|
|
|
|
|
2019-05-09 11:29:20 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_bh iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_bh iclass decode.
|
|
|
|
|
|
|
2019-05-09 11:29:19 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_sd2 iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_sd2 iclass decode.
|
|
|
|
|
|
* aarch64-opc.c (fields): Handle SVE_sz2 field.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
|
|
|
|
|
|
|
2019-05-09 11:29:18 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_ADDR_ZX.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
|
|
|
|
|
|
|
2019-05-09 11:29:17 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_Zm3_11_INDEX.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
|
|
|
|
|
|
(fields): Handle SVE_i3l and SVE_i3h2 fields.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
|
|
|
|
|
|
fields.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
|
|
|
|
|
|
|
2019-05-09 11:29:16 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_hsd2 iclass encode.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
|
|
|
|
|
|
sve_size_hsd2 iclass decode.
|
|
|
|
|
|
* aarch64-opc.c (fields): Handle SVE_size field.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
|
|
|
|
|
|
|
2019-05-09 11:29:15 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
|
|
|
|
|
for SVE_IMM_ROT3.
|
|
|
|
|
|
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
|
|
|
|
|
|
(fields): Handle SVE_rot3 field.
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
|
|
|
|
|
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
|
|
|
|
|
|
|
2019-05-09 11:29:13 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 11:29:12 +02:00
|
|
|
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h
|
|
|
|
|
|
(aarch64_feature_sve2, aarch64_feature_sve2aes,
|
|
|
|
|
|
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
|
|
|
|
|
|
aarch64_feature_sve2bitperm): New feature sets.
|
|
|
|
|
|
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
|
|
|
|
|
|
for feature set addresses.
|
|
|
|
|
|
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
|
|
|
|
|
|
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
|
|
|
|
|
|
|
Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-04-29 03:21:00 +02:00
|
|
|
|
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
Faraz Shahbazker <fshahbazker@wavecomp.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_calculate_combination_ases): Add ISA
|
|
|
|
|
|
argument and set ASE_EVA_R6 appropriately.
|
|
|
|
|
|
(set_default_mips_dis_options): Pass ISA to above.
|
|
|
|
|
|
(parse_mips_dis_option): Likewise.
|
|
|
|
|
|
* mips-opc.c (EVAR6): New macro.
|
|
|
|
|
|
(mips_builtin_opcodes): Add llwpe, scwpe.
|
|
|
|
|
|
|
2019-05-01 18:14:01 +02:00
|
|
|
|
2019-05-01 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
|
|
|
|
|
|
AARCH64_OPND_TME_UIMM16.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (QL_IMM_NIL): New.
|
|
|
|
|
|
(TME): New.
|
|
|
|
|
|
(_TME_INSN): New.
|
|
|
|
|
|
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
|
|
|
|
|
|
|
2019-04-29 16:05:54 +02:00
|
|
|
|
2019-04-29 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
|
|
|
|
|
|
|
[MIPS] Add load-link, store-conditional paired instructions
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-23 00:12:09 +02:00
|
|
|
|
2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
Faraz Shahbazker <fshahbazker@wavecomp.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
|
|
|
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2019-04-15 09:25:23 +02:00
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2019-04-24 John Darrington <john@darrington.wattle.id.au>
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* s12z-opc.h: Add extern "C" bracketing to help
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|
users who wish to use this interface in c++ code.
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2019-04-24 09:41:23 +02:00
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2019-04-24 John Darrington <john@darrington.wattle.id.au>
|
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* s12z-opc.c (bm_decode): Handle bit map operations with the
|
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|
"reserved0" mode.
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2019-04-15 13:23:24 +02:00
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
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* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
|
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|
|
specifier. Add entries for VLDR and VSTR of system registers.
|
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|
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
|
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|
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
|
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|
of %J and %K format specifier.
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2019-04-15 13:18:16 +02:00
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|
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
|
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Add new entries for VSCCLRM instruction.
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(print_insn_coprocessor): Handle new %C format control code.
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2019-04-15 13:14:38 +02:00
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|
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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* arm-dis.c (enum isa): New enum.
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(struct sopcode32): New structure.
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|
(coprocessor_opcodes): change type of entries to struct sopcode32 and
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|
set isa field of all current entries to ANY.
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(print_insn_coprocessor): Change type of insn to struct sopcode32.
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|
Only match an entry if its isa field allows the current mode.
|
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2019-04-15 13:07:20 +02:00
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
|
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|
CLRM.
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|
(print_insn_thumb32): Add logic to print %n CLRM register list.
|
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|
2019-04-15 12:58:47 +02:00
|
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|
|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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|
|
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
|
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|
and %Q patterns.
|
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|
2019-04-15 12:53:25 +02:00
|
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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|
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
|
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|
|
(print_insn_thumb32): Edit the switch case for %Z.
|
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2019-04-15 12:46:54 +02:00
|
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
|
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2019-04-15 12:42:10 +02:00
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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* arm-dis.c (thumb32_opcodes): New instruction bfl.
|
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2019-04-15 12:37:51 +02:00
|
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
|
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2019-04-15 12:29:14 +02:00
|
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|
|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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|
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
|
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|
|
Arm register with r13 and r15 unpredictable.
|
|
|
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|
|
(thumb32_opcodes): New instructions for bfx and bflx.
|
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2019-04-15 12:25:12 +02:00
|
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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|
* arm-dis.c (thumb32_opcodes): New instructions for bf.
|
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2019-04-15 12:18:57 +02:00
|
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|
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
|
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2019-04-15 12:06:30 +02:00
|
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
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* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
|
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2019-04-15 11:54:42 +02:00
|
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|
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
|
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
|
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|
2019-04-12 18:39:01 +02:00
|
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2019-04-12 John Darrington <john@darrington.wattle.id.au>
|
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|
|
s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
|
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|
|
"optr". ("operator" is a reserved word in c++).
|
|
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|
|
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-04-11 11:19:37 +02:00
|
|
|
|
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
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|
|
|
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|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Add case for
|
|
|
|
|
|
AARCH64_OPND_Rt_SP.
|
|
|
|
|
|
(verify_constraints): Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
|
|
|
|
|
|
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
|
|
|
|
|
|
to accept Rt|SP as first operand.
|
|
|
|
|
|
(AARCH64_OPERANDS): Add new Rt_SP.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2019-04-11 11:13:23 +02:00
|
|
|
|
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
|
|
|
|
|
|
|
2019-04-09 11:30:26 +02:00
|
|
|
|
2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
|
|
|
|
|
|
|
2019-04-08 20:06:04 +02:00
|
|
|
|
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Consolidate AVX512 BF16 entries.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2019-04-07 13:17:06 +02:00
|
|
|
|
2019-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
|
|
|
|
|
|
op_separator to control printing of spaces, comma and parens
|
|
|
|
|
|
rather than need_comma, need_paren and spaces vars.
|
|
|
|
|
|
|
2019-04-07 13:12:16 +02:00
|
|
|
|
2019-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 24421
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
|
|
|
|
|
|
(print_insn_neon, print_insn_arm): Likewise.
|
|
|
|
|
|
|
2019-04-05 20:03:01 +02:00
|
|
|
|
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Updated to support BF16
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
|
|
|
|
|
|
and EVEX_W_0F3872_P_3.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add bitfield for CpuAVX512_BF16.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuAVX512_BF16.
|
|
|
|
|
|
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
|
|
|
|
|
|
* i386-opc.tbl: Add AVX512 BF16 instructions.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
PowerPC bc extended branch mnemonics and "y" hints
This patch fixes a problem with disassembly of branch instructions
for processors complying with PowerPC ISA versions prior to version
2.0, ie. those that use "y" bit branch taken hints. Many of the
extended bcctr and bclr mnemonics that should have disassembled with a
"-" suffix, ie. not taken, did not display the "-" due to the ordering
in powerpc_opcodes. I believe it's been that way from the original
85dcf36d72b commit of ppc-opc.c.
I've also added a BH field (optional) to a few opcodes. This gives
better disassembly in raw mode, showing the branch taken hint in the
mnemonic as is done for bc. It would be reasonable to add a BH
field to all bcctr, bclr, and bctar extended mnemonics but that runs
into a small difficulty: Currently we print all or none of the
optional operands. That means for example that "bgectr cr2" would
display as "bgectr cr2,0" if a BH field is added to bgectr.
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
to favour printing of "-" branch hint when using the "y" bit.
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2019-04-04 09:49:03 +02:00
|
|
|
|
2019-04-05 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
|
|
|
|
|
|
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
|
|
|
|
|
|
to favour printing of "-" branch hint when using the "y" bit.
|
|
|
|
|
|
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
|
|
|
|
|
|
|
2019-04-05 00:50:16 +02:00
|
|
|
|
2019-04-05 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
|
|
|
|
|
|
opcode until first operand is output.
|
|
|
|
|
|
|
Add extended mnemonics for bctar. Fix setting of 'at' branch hints.
opcodes/
PR gas/24349
* ppc-opc.c (valid_bo_pre_v2): Add comments.
(valid_bo_post_v2): Add support for 'at' branch hints.
(insert_bo): Only error on branch on ctr.
(get_bo_hint_mask): New function.
(insert_boe): Add new 'branch_taken' formal argument. Add support
for inserting 'at' branch hints.
(extract_boe): Add new 'branch_taken' formal argument. Add support
for extracting 'at' branch hints.
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
(BOE): Delete operand.
(BOM, BOP): New operands.
(RM): Update value.
(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+>: New extended mnemonics.
gas/
PR gas/24349
* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+): Add tests of extended mnemonics.
* testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
to expect new extended mnemonics.
* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
to not use illegal BO value. Use a more convenient BI value.
* testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-04-04 16:00:29 +02:00
|
|
|
|
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24349
|
|
|
|
|
|
* ppc-opc.c (valid_bo_pre_v2): Add comments.
|
|
|
|
|
|
(valid_bo_post_v2): Add support for 'at' branch hints.
|
|
|
|
|
|
(insert_bo): Only error on branch on ctr.
|
|
|
|
|
|
(get_bo_hint_mask): New function.
|
|
|
|
|
|
(insert_boe): Add new 'branch_taken' formal argument. Add support
|
|
|
|
|
|
for inserting 'at' branch hints.
|
|
|
|
|
|
(extract_boe): Add new 'branch_taken' formal argument. Add support
|
|
|
|
|
|
for extracting 'at' branch hints.
|
|
|
|
|
|
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
|
|
|
|
|
|
(BOE): Delete operand.
|
|
|
|
|
|
(BOM, BOP): New operands.
|
|
|
|
|
|
(RM): Update value.
|
|
|
|
|
|
(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
|
|
|
|
|
|
(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
|
|
|
|
|
|
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
|
|
|
|
|
|
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
|
|
|
|
|
|
bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
|
|
|
|
|
|
<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
|
|
|
|
|
|
bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
|
|
|
|
|
|
bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
|
|
|
|
|
|
bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
|
|
|
|
|
|
bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
|
|
|
|
|
|
bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
|
|
|
|
|
|
bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
|
|
|
|
|
|
bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
|
|
|
|
|
|
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
|
|
|
|
|
|
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
|
|
|
|
|
|
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
|
|
|
|
|
|
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
|
|
|
|
|
|
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
|
|
|
|
|
|
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
|
|
|
|
|
|
bttarl+>: New extended mnemonics.
|
|
|
|
|
|
|
2019-03-28 01:06:55 +01:00
|
|
|
|
2019-03-28 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 24390
|
|
|
|
|
|
* ppc-opc.c (BTF): Define.
|
|
|
|
|
|
(powerpc_opcodes): Use for mtfsb*.
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Print fields with both
|
|
|
|
|
|
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
|
|
|
|
|
|
|
Arm: Fix Arm disassembler mapping symbol search.
Similar to the AArch64 patches the Arm disassembler has the same issues with
out of order sections but also a few short comings.
For one thing there are multiple code blocks to determine mapping symbols, and
they all work slightly different, and neither fully correct. The first thing
this patch does is centralise the mapping symbols search into one function
mapping_symbol_for_insn. This function is then updated to perform a search in
a similar way as AArch64.
Their used to be a value has_mapping_symbols which was used to determine the
default disassembly for objects that have no mapping symbols. The problem with
the approach was that it was determining this value in the same loop that needed
it, which is why this field could take on the states -1, 0, 1 where -1 means
"don't know". However this means that until you actually find a mapping symbol
or reach the end of the disassembly glob, you don't know if you did the right
action or not, and if you didn't you can't correct it anymore.
This is why the two jump-reloc-veneers-* testcases end up disassembling some
insn as data when they shouldn't.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for Arm [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix
this we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section
than we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7
binutils/ChangeLog:
* testsuite/binutils-all/arm/in-order-all.d: New test.
* testsuite/binutils-all/arm/in-order.d: New test.
* testsuite/binutils-all/arm/objdump.exp: Support .d tests.
* testsuite/binutils-all/arm/out-of-order-all.d: New test.
* testsuite/binutils-all/arm/out-of-order.T: New test.
* testsuite/binutils-all/arm/out-of-order.d: New test.
* testsuite/binutils-all/arm/out-of-order.s: New test.
ld/ChangeLog:
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly.
* testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly.
opcodes/ChangeLog:
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
(mapping_symbol_for_insn): Implement new algorithm.
(print_insn): Remove duplicate code.
2019-03-25 13:16:17 +01:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
|
|
|
|
|
|
(mapping_symbol_for_insn): Implement new algorithm.
|
|
|
|
|
|
(print_insn): Remove duplicate code.
|
|
|
|
|
|
|
2019-03-25 13:14:37 +01:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (print_insn_aarch64):
|
|
|
|
|
|
Implement override.
|
|
|
|
|
|
|
2019-03-25 13:12:03 +01:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
|
|
|
|
|
|
order.
|
|
|
|
|
|
|
2019-03-25 13:08:53 +01:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (last_stop_offset): New.
|
|
|
|
|
|
(print_insn_aarch64): Use stop_offset.
|
|
|
|
|
|
|
2019-03-19 14:08:15 +01:00
|
|
|
|
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24359
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
|
|
|
|
|
|
CPU_ANY_AVX2_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2019-03-18 01:56:10 +01:00
|
|
|
|
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24348
|
|
|
|
|
|
* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
|
|
|
|
|
|
vmovdqu16, vmovdqu32 and vmovdqu64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2019-03-12 14:23:10 +01:00
|
|
|
|
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
|
|
|
|
|
|
from vstrszb, vstrszh, and vstrszf.
|
|
|
|
|
|
|
|
|
|
|
|
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.txt: Add instruction descriptions.
|
|
|
|
|
|
|
2019-02-08 22:21:52 +01:00
|
|
|
|
2019-02-08 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
|
|
|
|
|
|
<bne>: Likewise.
|
|
|
|
|
|
|
2019-02-07 18:12:23 +01:00
|
|
|
|
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
|
|
|
|
|
|
|
2019-02-07 17:55:23 +01:00
|
|
|
|
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23212
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
|
|
|
|
|
|
* aarch64-opc.c (verify_elem_sd): New.
|
|
|
|
|
|
(fields): Add FLD_sz entr.
|
|
|
|
|
|
* aarch64-tbl.h (_SIMD_INSN): New.
|
|
|
|
|
|
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
|
|
|
|
|
|
fmulx scalar and vector by element isns.
|
|
|
|
|
|
|
2019-02-07 15:49:38 +01:00
|
|
|
|
2019-02-07 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2019-01-31 17:01:27 +01:00
|
|
|
|
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (main): Accept arch13 as cpu string.
|
|
|
|
|
|
* s390-opc.c: Add new instruction formats and instruction opcode
|
|
|
|
|
|
masks.
|
|
|
|
|
|
* s390-opc.txt: Add new arch13 instructions.
|
|
|
|
|
|
|
2019-01-25 16:50:01 +01:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_LDST_AT): Update macro.
|
|
|
|
|
|
(aarch64_opcode): Change encoding for stg, stzg
|
|
|
|
|
|
st2g and st2zg.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2019-01-25 15:15:45 +01:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
|
|
|
|
|
|
|
2019-01-25 14:57:14 +01:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
|
|
|
|
|
|
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
|
|
|
|
|
|
* aarch64-dis.h (ext_addr_simple_2): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Remove
|
|
|
|
|
|
case for ldstgv_indexed.
|
|
|
|
|
|
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
|
|
|
|
|
|
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
|
|
|
|
|
|
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2019-01-23 11:26:54 +01:00
|
|
|
|
2019-01-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2019-01-21 13:59:20 +01:00
|
|
|
|
2019-01-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2019-01-20 02:51:30 +01:00
|
|
|
|
2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Fix typo in
|
|
|
|
|
|
gs464, gs464e and gs264e descriptors.
|
|
|
|
|
|
|
2019-01-19 17:51:42 +01:00
|
|
|
|
2019-01-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2019-01-19 16:55:50 +01:00
|
|
|
|
2018-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.32 branch created.
|
|
|
|
|
|
|
2018-12-31 08:48:10 +01:00
|
|
|
|
2019-01-09 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
2019-01-04 09:44:58 +01:00
|
|
|
|
* s12z-dis.c (print_insn_s12z): Do not dereference an operand
|
|
|
|
|
|
if it is null.
|
|
|
|
|
|
-dis.c (opr_emit_disassembly): Do not omit an index if it is
|
2018-12-31 08:48:10 +01:00
|
|
|
|
zero.
|
|
|
|
|
|
|
2019-01-09 04:21:08 +01:00
|
|
|
|
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2019-01-07 05:33:43 +01:00
|
|
|
|
2019-01-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2019-01-03 18:30:40 +01:00
|
|
|
|
2019-01-03 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* s12z-opc.c: New file.
|
|
|
|
|
|
* s12z-opc.h: New file.
|
|
|
|
|
|
* s12z-dis.c: Removed all code not directly related to display
|
|
|
|
|
|
of instructions. Used the interface provided by the new files
|
|
|
|
|
|
instead.
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
|
2019-01-07 05:33:43 +01:00
|
|
|
|
* Makefile.in: Regenerate.
|
2019-01-03 18:30:40 +01:00
|
|
|
|
* configure.ac (bfd_s12z_arch): Correct the dependencies.
|
2019-01-07 05:33:43 +01:00
|
|
|
|
* configure: Regenerate.
|
2019-01-03 18:30:40 +01:00
|
|
|
|
|
2019-01-01 11:31:27 +01:00
|
|
|
|
2019-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2019-01-01 11:53:15 +01:00
|
|
|
|
For older changes see ChangeLog-2018
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
2019-01-01 11:53:15 +01:00
|
|
|
|
Copyright (C) 2019 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
